]>
Commit | Line | Data |
---|---|---|
1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
214d14d4 | 33 | #include "iwl-agn.h" |
1053d35f RR |
34 | #include "iwl-dev.h" |
35 | #include "iwl-core.h" | |
1053d35f RR |
36 | #include "iwl-io.h" |
37 | #include "iwl-helpers.h" | |
253a634c | 38 | #include "iwl-trans-int-pcie.h" |
1053d35f | 39 | |
48d42c42 EG |
40 | /** |
41 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
42 | */ | |
6d8f6eeb | 43 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
44 | struct iwl_tx_queue *txq, |
45 | u16 byte_cnt) | |
46 | { | |
105183b1 | 47 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
48 | struct iwl_trans_pcie *trans_pcie = |
49 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
50 | int write_ptr = txq->q.write_ptr; |
51 | int txq_id = txq->q.id; | |
52 | u8 sec_ctl = 0; | |
53 | u8 sta_id = 0; | |
54 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
55 | __le16 bc_ent; | |
56 | ||
105183b1 EG |
57 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
58 | ||
48d42c42 EG |
59 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
60 | ||
61 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; | |
62 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; | |
63 | ||
64 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
65 | case TX_CMD_SEC_CCM: | |
66 | len += CCMP_MIC_LEN; | |
67 | break; | |
68 | case TX_CMD_SEC_TKIP: | |
69 | len += TKIP_ICV_LEN; | |
70 | break; | |
71 | case TX_CMD_SEC_WEP: | |
72 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
73 | break; | |
74 | } | |
75 | ||
76 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
77 | ||
78 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
79 | ||
80 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
81 | scd_bc_tbl[txq_id]. | |
82 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
83 | } | |
84 | ||
fd4abac5 TW |
85 | /** |
86 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
87 | */ | |
fd656935 | 88 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
89 | { |
90 | u32 reg = 0; | |
fd4abac5 TW |
91 | int txq_id = txq->q.id; |
92 | ||
93 | if (txq->need_update == 0) | |
7bfedc59 | 94 | return; |
fd4abac5 | 95 | |
fd656935 | 96 | if (hw_params(trans).shadow_reg_enable) { |
f81c1f48 | 97 | /* shadow register enabled */ |
fd656935 | 98 | iwl_write32(bus(trans), HBUS_TARG_WRPTR, |
f81c1f48 WYG |
99 | txq->q.write_ptr | (txq_id << 8)); |
100 | } else { | |
101 | /* if we're trying to save power */ | |
fd656935 | 102 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
f81c1f48 WYG |
103 | /* wake up nic if it's powered down ... |
104 | * uCode will wake up, and interrupt us again, so next | |
105 | * time we'll skip this part. */ | |
fd656935 | 106 | reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1); |
fd4abac5 | 107 | |
f81c1f48 | 108 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 109 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
110 | "Tx queue %d requesting wakeup," |
111 | " GP1 = 0x%x\n", txq_id, reg); | |
fd656935 | 112 | iwl_set_bit(bus(trans), CSR_GP_CNTRL, |
f81c1f48 WYG |
113 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
114 | return; | |
115 | } | |
fd4abac5 | 116 | |
fd656935 | 117 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, |
fd4abac5 | 118 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 119 | |
f81c1f48 WYG |
120 | /* |
121 | * else not in power-save mode, | |
122 | * uCode will never sleep when we're | |
123 | * trying to tx (during RFKILL, we're not trying to tx). | |
124 | */ | |
125 | } else | |
fd656935 | 126 | iwl_write32(bus(trans), HBUS_TARG_WRPTR, |
f81c1f48 WYG |
127 | txq->q.write_ptr | (txq_id << 8)); |
128 | } | |
fd4abac5 | 129 | txq->need_update = 0; |
fd4abac5 | 130 | } |
fd4abac5 | 131 | |
214d14d4 JB |
132 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
133 | { | |
134 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
135 | ||
136 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
137 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
138 | addr |= | |
139 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
140 | ||
141 | return addr; | |
142 | } | |
143 | ||
144 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
145 | { | |
146 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
147 | ||
148 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
149 | } | |
150 | ||
151 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
152 | dma_addr_t addr, u16 len) | |
153 | { | |
154 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
155 | u16 hi_n_len = len << 4; | |
156 | ||
157 | put_unaligned_le32(addr, &tb->lo); | |
158 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
159 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
160 | ||
161 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
162 | ||
163 | tfd->num_tbs = idx + 1; | |
164 | } | |
165 | ||
166 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
167 | { | |
168 | return tfd->num_tbs & 0x1f; | |
169 | } | |
170 | ||
6d8f6eeb | 171 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 172 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 173 | { |
214d14d4 JB |
174 | int i; |
175 | int num_tbs; | |
176 | ||
214d14d4 JB |
177 | /* Sanity check on number of chunks */ |
178 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
179 | ||
180 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 181 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
182 | /* @todo issue fatal error, it is quite serious situation */ |
183 | return; | |
184 | } | |
185 | ||
186 | /* Unmap tx_cmd */ | |
187 | if (num_tbs) | |
6d8f6eeb | 188 | dma_unmap_single(bus(trans)->dev, |
4ce7cc2b JB |
189 | dma_unmap_addr(meta, mapping), |
190 | dma_unmap_len(meta, len), | |
795414db | 191 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
192 | |
193 | /* Unmap chunks, if any. */ | |
194 | for (i = 1; i < num_tbs; i++) | |
6d8f6eeb | 195 | dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 196 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
197 | } |
198 | ||
199 | /** | |
200 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 201 | * @trans - transport private data |
4ce7cc2b | 202 | * @txq - tx queue |
1359ca4f | 203 | * @index - the index of the TFD to be freed |
4ce7cc2b JB |
204 | * |
205 | * Does NOT advance any TFD circular buffer read/write indexes | |
206 | * Does NOT free the TFD itself (which is within circular buffer) | |
207 | */ | |
6d8f6eeb | 208 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
1359ca4f | 209 | int index) |
4ce7cc2b JB |
210 | { |
211 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 212 | |
6d8f6eeb | 213 | iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], |
3be3fdb5 | 214 | DMA_TO_DEVICE); |
214d14d4 JB |
215 | |
216 | /* free SKB */ | |
2c452297 | 217 | if (txq->skbs) { |
214d14d4 JB |
218 | struct sk_buff *skb; |
219 | ||
2c452297 | 220 | skb = txq->skbs[index]; |
214d14d4 JB |
221 | |
222 | /* can be called from irqs-disabled context */ | |
223 | if (skb) { | |
224 | dev_kfree_skb_any(skb); | |
2c452297 | 225 | txq->skbs[index] = NULL; |
214d14d4 JB |
226 | } |
227 | } | |
228 | } | |
229 | ||
6d8f6eeb | 230 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
231 | struct iwl_tx_queue *txq, |
232 | dma_addr_t addr, u16 len, | |
4c42db0f | 233 | u8 reset) |
214d14d4 JB |
234 | { |
235 | struct iwl_queue *q; | |
236 | struct iwl_tfd *tfd, *tfd_tmp; | |
237 | u32 num_tbs; | |
238 | ||
239 | q = &txq->q; | |
4ce7cc2b | 240 | tfd_tmp = txq->tfds; |
214d14d4 JB |
241 | tfd = &tfd_tmp[q->write_ptr]; |
242 | ||
243 | if (reset) | |
244 | memset(tfd, 0, sizeof(*tfd)); | |
245 | ||
246 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
247 | ||
248 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
249 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 250 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
251 | IWL_NUM_OF_TBS); |
252 | return -EINVAL; | |
253 | } | |
254 | ||
255 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
256 | return -EINVAL; | |
257 | ||
258 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 259 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
260 | (unsigned long long)addr); |
261 | ||
262 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
fd4abac5 TW |
267 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
268 | * DMA services | |
269 | * | |
270 | * Theory of operation | |
271 | * | |
272 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
273 | * of buffer descriptors, each of which points to one or more data buffers for | |
274 | * the device to read from or fill. Driver and device exchange status of each | |
275 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
276 | * entries in each circular buffer, to protect against confusing empty and full | |
277 | * queue states. | |
278 | * | |
279 | * The device reads or writes the data in the queues via the device's several | |
280 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
281 | * | |
282 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
283 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
284 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
285 | * Tx queue resumed. | |
286 | * | |
fd4abac5 TW |
287 | ***************************************************/ |
288 | ||
289 | int iwl_queue_space(const struct iwl_queue *q) | |
290 | { | |
291 | int s = q->read_ptr - q->write_ptr; | |
292 | ||
293 | if (q->read_ptr > q->write_ptr) | |
294 | s -= q->n_bd; | |
295 | ||
296 | if (s <= 0) | |
297 | s += q->n_window; | |
298 | /* keep some reserve to not confuse empty and full situations */ | |
299 | s -= 2; | |
300 | if (s < 0) | |
301 | s = 0; | |
302 | return s; | |
303 | } | |
fd4abac5 | 304 | |
1053d35f RR |
305 | /** |
306 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
307 | */ | |
6d8f6eeb | 308 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
309 | { |
310 | q->n_bd = count; | |
311 | q->n_window = slots_num; | |
312 | q->id = id; | |
313 | ||
314 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
315 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
316 | if (WARN_ON(!is_power_of_2(count))) |
317 | return -EINVAL; | |
1053d35f RR |
318 | |
319 | /* slots_num must be power-of-two size, otherwise | |
320 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
321 | if (WARN_ON(!is_power_of_2(slots_num))) |
322 | return -EINVAL; | |
1053d35f RR |
323 | |
324 | q->low_mark = q->n_window / 4; | |
325 | if (q->low_mark < 4) | |
326 | q->low_mark = 4; | |
327 | ||
328 | q->high_mark = q->n_window / 8; | |
329 | if (q->high_mark < 2) | |
330 | q->high_mark = 2; | |
331 | ||
332 | q->write_ptr = q->read_ptr = 0; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
6d8f6eeb | 337 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
338 | struct iwl_tx_queue *txq) |
339 | { | |
105183b1 EG |
340 | struct iwl_trans_pcie *trans_pcie = |
341 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 342 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
343 | int txq_id = txq->q.id; |
344 | int read_ptr = txq->q.read_ptr; | |
345 | u8 sta_id = 0; | |
346 | __le16 bc_ent; | |
347 | ||
348 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
349 | ||
6d8f6eeb | 350 | if (txq_id != trans->shrd->cmd_queue) |
48d42c42 EG |
351 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
352 | ||
353 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
354 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
355 | ||
356 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
357 | scd_bc_tbl[txq_id]. | |
358 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
359 | } | |
360 | ||
6d8f6eeb | 361 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
362 | u16 txq_id) |
363 | { | |
364 | u32 tbl_dw_addr; | |
365 | u32 tbl_dw; | |
366 | u16 scd_q2ratid; | |
367 | ||
105183b1 EG |
368 | struct iwl_trans_pcie *trans_pcie = |
369 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
370 | ||
48d42c42 EG |
371 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
372 | ||
105183b1 | 373 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
374 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
375 | ||
83ed9015 | 376 | tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr); |
48d42c42 EG |
377 | |
378 | if (txq_id & 0x1) | |
379 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
380 | else | |
381 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
382 | ||
83ed9015 | 383 | iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw); |
48d42c42 EG |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
6d8f6eeb | 388 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
389 | { |
390 | /* Simply stop the queue, but don't change any configuration; | |
391 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
83ed9015 | 392 | iwl_write_prph(bus(trans), |
48d42c42 EG |
393 | SCD_QUEUE_STATUS_BITS(txq_id), |
394 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
395 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
396 | } | |
397 | ||
6d8f6eeb | 398 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
399 | int txq_id, u32 index) |
400 | { | |
83ed9015 | 401 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, |
48d42c42 | 402 | (index & 0xff) | (txq_id << 8)); |
83ed9015 | 403 | iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
404 | } |
405 | ||
c91bd124 | 406 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
48d42c42 EG |
407 | struct iwl_tx_queue *txq, |
408 | int tx_fifo_id, int scd_retry) | |
409 | { | |
8ad71bef | 410 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 411 | int txq_id = txq->q.id; |
c91bd124 | 412 | int active = |
8ad71bef | 413 | test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0; |
48d42c42 | 414 | |
c91bd124 | 415 | iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
416 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
417 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
418 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
419 | SCD_QUEUE_STTS_REG_MSK); | |
420 | ||
421 | txq->sched_retry = scd_retry; | |
422 | ||
c91bd124 | 423 | IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n", |
48d42c42 EG |
424 | active ? "Activate" : "Deactivate", |
425 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
426 | } | |
427 | ||
e13c0c59 EG |
428 | static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie, |
429 | u8 ctx, u16 tid) | |
ba562f71 | 430 | { |
e13c0c59 | 431 | const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx]; |
ba562f71 | 432 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) |
e13c0c59 | 433 | return ac_to_fifo[tid_to_ac[tid]]; |
ba562f71 EG |
434 | |
435 | /* no support for TIDs 8-15 yet */ | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
c91bd124 EG |
439 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, |
440 | enum iwl_rxon_context_id ctx, int sta_id, | |
441 | int tid, int frame_limit) | |
48d42c42 EG |
442 | { |
443 | int tx_fifo, txq_id, ssn_idx; | |
444 | u16 ra_tid; | |
445 | unsigned long flags; | |
446 | struct iwl_tid_data *tid_data; | |
447 | ||
105183b1 EG |
448 | struct iwl_trans_pcie *trans_pcie = |
449 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
450 | ||
48d42c42 EG |
451 | if (WARN_ON(sta_id == IWL_INVALID_STATION)) |
452 | return; | |
5f85a789 | 453 | if (WARN_ON(tid >= IWL_MAX_TID_COUNT)) |
48d42c42 EG |
454 | return; |
455 | ||
e13c0c59 | 456 | tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid); |
ba562f71 EG |
457 | if (WARN_ON(tx_fifo < 0)) { |
458 | IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo); | |
459 | return; | |
460 | } | |
461 | ||
c91bd124 EG |
462 | spin_lock_irqsave(&trans->shrd->sta_lock, flags); |
463 | tid_data = &trans->shrd->tid_data[sta_id][tid]; | |
48d42c42 EG |
464 | ssn_idx = SEQ_TO_SN(tid_data->seq_number); |
465 | txq_id = tid_data->agg.txq_id; | |
c91bd124 | 466 | spin_unlock_irqrestore(&trans->shrd->sta_lock, flags); |
48d42c42 EG |
467 | |
468 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
469 | ||
c91bd124 | 470 | spin_lock_irqsave(&trans->shrd->lock, flags); |
48d42c42 EG |
471 | |
472 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 473 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
474 | |
475 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 476 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
477 | |
478 | /* Set this queue as a chain-building queue */ | |
c91bd124 | 479 | iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id)); |
48d42c42 EG |
480 | |
481 | /* enable aggregations for the queue */ | |
c91bd124 | 482 | iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id)); |
48d42c42 EG |
483 | |
484 | /* Place first TFD at index corresponding to start sequence number. | |
485 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
8ad71bef EG |
486 | trans_pcie->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); |
487 | trans_pcie->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
6d8f6eeb | 488 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx); |
48d42c42 EG |
489 | |
490 | /* Set up Tx window size and frame limit for this queue */ | |
c91bd124 | 491 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + |
48d42c42 EG |
492 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
493 | sizeof(u32), | |
494 | ((frame_limit << | |
495 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
496 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
497 | ((frame_limit << | |
498 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
499 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
500 | ||
c91bd124 | 501 | iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
502 | |
503 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 504 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
c91bd124 | 505 | tx_fifo, 1); |
48d42c42 | 506 | |
8ad71bef EG |
507 | trans_pcie->txq[txq_id].sta_id = sta_id; |
508 | trans_pcie->txq[txq_id].tid = tid; | |
a0eaad71 | 509 | |
c91bd124 | 510 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
48d42c42 EG |
511 | } |
512 | ||
288712a6 EG |
513 | /* |
514 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
515 | * Called only when finding queue for aggregation. | |
516 | * Should never return anything < 7, because they should already | |
517 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
518 | */ | |
519 | static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans) | |
520 | { | |
8ad71bef | 521 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 EG |
522 | int txq_id; |
523 | ||
524 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) | |
525 | if (!test_and_set_bit(txq_id, | |
8ad71bef | 526 | &trans_pcie->txq_ctx_active_msk)) |
288712a6 EG |
527 | return txq_id; |
528 | return -1; | |
529 | } | |
530 | ||
531 | int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, | |
532 | enum iwl_rxon_context_id ctx, int sta_id, | |
533 | int tid, u16 *ssn) | |
534 | { | |
8ad71bef | 535 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 EG |
536 | struct iwl_tid_data *tid_data; |
537 | unsigned long flags; | |
4690c33d | 538 | int txq_id; |
288712a6 EG |
539 | |
540 | txq_id = iwlagn_txq_ctx_activate_free(trans); | |
541 | if (txq_id == -1) { | |
542 | IWL_ERR(trans, "No free aggregation queue available\n"); | |
543 | return -ENXIO; | |
544 | } | |
545 | ||
546 | spin_lock_irqsave(&trans->shrd->sta_lock, flags); | |
547 | tid_data = &trans->shrd->tid_data[sta_id][tid]; | |
548 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
549 | tid_data->agg.txq_id = txq_id; | |
8ad71bef | 550 | iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id); |
288712a6 EG |
551 | |
552 | tid_data = &trans->shrd->tid_data[sta_id][tid]; | |
553 | if (tid_data->tfds_in_queue == 0) { | |
554 | IWL_DEBUG_HT(trans, "HW queue is empty\n"); | |
555 | tid_data->agg.state = IWL_AGG_ON; | |
556 | iwl_start_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid); | |
557 | } else { | |
558 | IWL_DEBUG_HT(trans, "HW queue is NOT empty: %d packets in HW" | |
559 | "queue\n", tid_data->tfds_in_queue); | |
560 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
561 | } | |
3e10caeb | 562 | spin_unlock_irqrestore(&trans->shrd->sta_lock, flags); |
288712a6 EG |
563 | |
564 | return 0; | |
565 | } | |
7f01d567 EG |
566 | |
567 | void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id) | |
48d42c42 | 568 | { |
8ad71bef | 569 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7f01d567 EG |
570 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
571 | ||
572 | iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id)); | |
573 | ||
8ad71bef EG |
574 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
575 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
7f01d567 EG |
576 | /* supposes that ssn_idx is valid (!= 0xFFF) */ |
577 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); | |
578 | ||
579 | iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id)); | |
8ad71bef EG |
580 | iwl_txq_ctx_deactivate(trans_pcie, txq_id); |
581 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0); | |
7f01d567 EG |
582 | } |
583 | ||
584 | int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, | |
585 | enum iwl_rxon_context_id ctx, int sta_id, | |
586 | int tid) | |
587 | { | |
8ad71bef | 588 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7f01d567 EG |
589 | unsigned long flags; |
590 | int read_ptr, write_ptr; | |
591 | struct iwl_tid_data *tid_data; | |
592 | int txq_id; | |
593 | ||
594 | spin_lock_irqsave(&trans->shrd->sta_lock, flags); | |
595 | ||
596 | tid_data = &trans->shrd->tid_data[sta_id][tid]; | |
597 | txq_id = tid_data->agg.txq_id; | |
598 | ||
48d42c42 EG |
599 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || |
600 | (IWLAGN_FIRST_AMPDU_QUEUE + | |
7f01d567 EG |
601 | hw_params(trans).num_ampdu_queues <= txq_id)) { |
602 | IWL_ERR(trans, | |
48d42c42 EG |
603 | "queue number out of range: %d, must be %d to %d\n", |
604 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, | |
605 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7f01d567 EG |
606 | hw_params(trans).num_ampdu_queues - 1); |
607 | spin_unlock_irqrestore(&trans->shrd->sta_lock, flags); | |
48d42c42 EG |
608 | return -EINVAL; |
609 | } | |
610 | ||
7f01d567 EG |
611 | switch (trans->shrd->tid_data[sta_id][tid].agg.state) { |
612 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
613 | /* | |
614 | * This can happen if the peer stops aggregation | |
615 | * again before we've had a chance to drain the | |
616 | * queue we selected previously, i.e. before the | |
617 | * session was really started completely. | |
618 | */ | |
619 | IWL_DEBUG_HT(trans, "AGG stop before setup done\n"); | |
620 | goto turn_off; | |
621 | case IWL_AGG_ON: | |
622 | break; | |
623 | default: | |
624 | IWL_WARN(trans, "Stopping AGG while state not ON" | |
625 | "or starting\n"); | |
626 | } | |
48d42c42 | 627 | |
8ad71bef EG |
628 | write_ptr = trans_pcie->txq[txq_id].q.write_ptr; |
629 | read_ptr = trans_pcie->txq[txq_id].q.read_ptr; | |
48d42c42 | 630 | |
7f01d567 EG |
631 | /* The queue is not empty */ |
632 | if (write_ptr != read_ptr) { | |
633 | IWL_DEBUG_HT(trans, "Stopping a non empty AGG HW QUEUE\n"); | |
634 | trans->shrd->tid_data[sta_id][tid].agg.state = | |
635 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
636 | spin_unlock_irqrestore(&trans->shrd->sta_lock, flags); | |
637 | return 0; | |
638 | } | |
639 | ||
640 | IWL_DEBUG_HT(trans, "HW queue is empty\n"); | |
641 | turn_off: | |
642 | trans->shrd->tid_data[sta_id][tid].agg.state = IWL_AGG_OFF; | |
643 | ||
644 | /* do not restore/save irqs */ | |
645 | spin_unlock(&trans->shrd->sta_lock); | |
646 | spin_lock(&trans->shrd->lock); | |
647 | ||
648 | iwl_trans_pcie_txq_agg_disable(trans, txq_id); | |
649 | ||
650 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
48d42c42 | 651 | |
7f01d567 | 652 | iwl_stop_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid); |
48d42c42 EG |
653 | |
654 | return 0; | |
655 | } | |
656 | ||
fd4abac5 TW |
657 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
658 | ||
659 | /** | |
660 | * iwl_enqueue_hcmd - enqueue a uCode command | |
661 | * @priv: device private data point | |
662 | * @cmd: a point to the ucode command structure | |
663 | * | |
664 | * The function returns < 0 values to indicate the operation is | |
665 | * failed. On success, it turns the index (> 0) of command in the | |
666 | * command queue. | |
667 | */ | |
6d8f6eeb | 668 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 669 | { |
8ad71bef EG |
670 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
671 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
fd4abac5 | 672 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
673 | struct iwl_device_cmd *out_cmd; |
674 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 675 | dma_addr_t phys_addr; |
fd4abac5 | 676 | unsigned long flags; |
f3674227 | 677 | u32 idx; |
4ce7cc2b | 678 | u16 copy_size, cmd_size; |
0975cc8f | 679 | bool is_ct_kill = false; |
4ce7cc2b JB |
680 | bool had_nocopy = false; |
681 | int i; | |
682 | u8 *cmd_dest; | |
683 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
684 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
685 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
686 | int trace_idx; | |
687 | #endif | |
fd4abac5 | 688 | |
6d8f6eeb EG |
689 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { |
690 | IWL_WARN(trans, "fw recovery, no hcmd send\n"); | |
3083d03c WYG |
691 | return -EIO; |
692 | } | |
693 | ||
fd656935 | 694 | if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) && |
eedb6e35 | 695 | !(cmd->flags & CMD_ON_DEMAND)) { |
6d8f6eeb | 696 | IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n"); |
eedb6e35 WYG |
697 | return -EIO; |
698 | } | |
699 | ||
4ce7cc2b JB |
700 | copy_size = sizeof(out_cmd->hdr); |
701 | cmd_size = sizeof(out_cmd->hdr); | |
702 | ||
703 | /* need one for the header if the first is NOCOPY */ | |
704 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
705 | ||
706 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
707 | if (!cmd->len[i]) | |
708 | continue; | |
709 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
710 | had_nocopy = true; | |
711 | } else { | |
712 | /* NOCOPY must not be followed by normal! */ | |
713 | if (WARN_ON(had_nocopy)) | |
714 | return -EINVAL; | |
715 | copy_size += cmd->len[i]; | |
716 | } | |
717 | cmd_size += cmd->len[i]; | |
718 | } | |
fd4abac5 | 719 | |
3e41ace5 JB |
720 | /* |
721 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
722 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
723 | * allocated into separate TFDs, then we will need to | |
724 | * increase the size of the buffers. | |
3e41ace5 | 725 | */ |
4ce7cc2b | 726 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 727 | return -EINVAL; |
fd4abac5 | 728 | |
6d8f6eeb EG |
729 | if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) { |
730 | IWL_WARN(trans, "Not sending command - %s KILL\n", | |
731 | iwl_is_rfkill(trans->shrd) ? "RF" : "CT"); | |
fd4abac5 TW |
732 | return -EIO; |
733 | } | |
7b21f00e | 734 | |
72012474 | 735 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
3598e177 | 736 | |
c2acea8e | 737 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
72012474 | 738 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
3598e177 | 739 | |
6d8f6eeb | 740 | IWL_ERR(trans, "No space in command queue\n"); |
fd656935 | 741 | is_ct_kill = iwl_check_for_ct_kill(priv(trans)); |
0975cc8f | 742 | if (!is_ct_kill) { |
6d8f6eeb | 743 | IWL_ERR(trans, "Restarting adapter queue is full\n"); |
fd656935 | 744 | iwlagn_fw_error(priv(trans), false); |
7812b167 | 745 | } |
fd4abac5 TW |
746 | return -ENOSPC; |
747 | } | |
748 | ||
4ce7cc2b | 749 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 750 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
751 | out_meta = &txq->meta[idx]; |
752 | ||
8ce73f3a | 753 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
754 | if (cmd->flags & CMD_WANT_SKB) |
755 | out_meta->source = cmd; | |
756 | if (cmd->flags & CMD_ASYNC) | |
757 | out_meta->callback = cmd->callback; | |
fd4abac5 | 758 | |
4ce7cc2b | 759 | /* set up the header */ |
fd4abac5 | 760 | |
4ce7cc2b | 761 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 762 | out_cmd->hdr.flags = 0; |
cefeaa5f | 763 | out_cmd->hdr.sequence = |
6d8f6eeb | 764 | cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) | |
cefeaa5f | 765 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
766 | |
767 | /* and copy the data that needs to be copied */ | |
768 | ||
769 | cmd_dest = &out_cmd->cmd.payload[0]; | |
770 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
771 | if (!cmd->len[i]) | |
772 | continue; | |
773 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
774 | break; | |
775 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
776 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 777 | } |
4ce7cc2b | 778 | |
6d8f6eeb | 779 | IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, " |
4ce7cc2b JB |
780 | "%d bytes at %d[%d]:%d\n", |
781 | get_cmd_string(out_cmd->hdr.cmd), | |
782 | out_cmd->hdr.cmd, | |
783 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
6d8f6eeb | 784 | q->write_ptr, idx, trans->shrd->cmd_queue); |
4ce7cc2b | 785 | |
6d8f6eeb | 786 | phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size, |
795414db | 787 | DMA_BIDIRECTIONAL); |
6d8f6eeb | 788 | if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { |
2c46f72e JB |
789 | idx = -ENOMEM; |
790 | goto out; | |
791 | } | |
792 | ||
2e724443 | 793 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
794 | dma_unmap_len_set(out_meta, len, copy_size); |
795 | ||
6d8f6eeb EG |
796 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
797 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
798 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
799 | trace_bufs[0] = &out_cmd->hdr; | |
800 | trace_lens[0] = copy_size; | |
801 | trace_idx = 1; | |
802 | #endif | |
803 | ||
804 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
805 | if (!cmd->len[i]) | |
806 | continue; | |
807 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
808 | continue; | |
6d8f6eeb EG |
809 | phys_addr = dma_map_single(bus(trans)->dev, |
810 | (void *)cmd->data[i], | |
3be3fdb5 | 811 | cmd->len[i], DMA_BIDIRECTIONAL); |
6d8f6eeb EG |
812 | if (dma_mapping_error(bus(trans)->dev, phys_addr)) { |
813 | iwlagn_unmap_tfd(trans, out_meta, | |
e815407d | 814 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 815 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
816 | idx = -ENOMEM; |
817 | goto out; | |
818 | } | |
819 | ||
6d8f6eeb | 820 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
821 | cmd->len[i], 0); |
822 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
823 | trace_bufs[trace_idx] = cmd->data[i]; | |
824 | trace_lens[trace_idx] = cmd->len[i]; | |
825 | trace_idx++; | |
826 | #endif | |
827 | } | |
df833b1d | 828 | |
afaf6b57 | 829 | out_meta->flags = cmd->flags; |
2c46f72e JB |
830 | |
831 | txq->need_update = 1; | |
832 | ||
4ce7cc2b JB |
833 | /* check that tracing gets all possible blocks */ |
834 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
835 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
fd656935 | 836 | trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags, |
4ce7cc2b JB |
837 | trace_bufs[0], trace_lens[0], |
838 | trace_bufs[1], trace_lens[1], | |
839 | trace_bufs[2], trace_lens[2]); | |
840 | #endif | |
df833b1d | 841 | |
fd4abac5 TW |
842 | /* Increment and update queue's write index */ |
843 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 844 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 845 | |
2c46f72e | 846 | out: |
72012474 | 847 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
7bfedc59 | 848 | return idx; |
fd4abac5 TW |
849 | } |
850 | ||
17b88929 TW |
851 | /** |
852 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
853 | * | |
854 | * When FW advances 'R' index, all entries between old and new 'R' index | |
855 | * need to be reclaimed. As result, some free space forms. If there is | |
856 | * enough free space (> low mark), wake the stack that feeds us. | |
857 | */ | |
3e10caeb EG |
858 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
859 | int idx) | |
17b88929 | 860 | { |
3e10caeb | 861 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 862 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
863 | struct iwl_queue *q = &txq->q; |
864 | int nfreed = 0; | |
865 | ||
499b1883 | 866 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 867 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
868 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
869 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
870 | return; |
871 | } | |
872 | ||
499b1883 TW |
873 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
874 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 875 | |
499b1883 | 876 | if (nfreed++ > 0) { |
3e10caeb | 877 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 878 | q->write_ptr, q->read_ptr); |
3e10caeb | 879 | iwlagn_fw_error(priv(trans), false); |
17b88929 | 880 | } |
da99c4b6 | 881 | |
17b88929 TW |
882 | } |
883 | } | |
884 | ||
885 | /** | |
886 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
887 | * @rxb: Rx buffer to reclaim | |
888 | * | |
889 | * If an Rx buffer has an async callback associated with it the callback | |
890 | * will be executed. The attached skb (if present) will only be freed | |
891 | * if the callback returns 1 | |
892 | */ | |
3e10caeb | 893 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb) |
17b88929 | 894 | { |
2f301227 | 895 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
896 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
897 | int txq_id = SEQ_TO_QUEUE(sequence); | |
898 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 899 | int cmd_index; |
c2acea8e JB |
900 | struct iwl_device_cmd *cmd; |
901 | struct iwl_cmd_meta *meta; | |
8ad71bef EG |
902 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
903 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
3598e177 | 904 | unsigned long flags; |
17b88929 TW |
905 | |
906 | /* If a Tx command is being handled and it isn't in the actual | |
907 | * command queue then there a command routing bug has been introduced | |
908 | * in the queue management code. */ | |
6d8f6eeb | 909 | if (WARN(txq_id != trans->shrd->cmd_queue, |
13bb9483 | 910 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
6d8f6eeb | 911 | txq_id, trans->shrd->cmd_queue, sequence, |
8ad71bef EG |
912 | trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr, |
913 | trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) { | |
3e10caeb | 914 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 915 | return; |
01ef9323 | 916 | } |
17b88929 | 917 | |
4ce7cc2b | 918 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
919 | cmd = txq->cmd[cmd_index]; |
920 | meta = &txq->meta[cmd_index]; | |
17b88929 | 921 | |
6d8f6eeb EG |
922 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
923 | DMA_BIDIRECTIONAL); | |
c33de625 | 924 | |
17b88929 | 925 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 926 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
927 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
928 | rxb->page = NULL; | |
2624e96c | 929 | } else if (meta->callback) |
3e10caeb | 930 | meta->callback(trans->shrd, cmd, pkt); |
2624e96c | 931 | |
72012474 | 932 | spin_lock_irqsave(&trans->hcmd_lock, flags); |
17b88929 | 933 | |
3e10caeb | 934 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 935 | |
c2acea8e | 936 | if (!(meta->flags & CMD_ASYNC)) { |
6d8f6eeb EG |
937 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
938 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", | |
d2dfe6df | 939 | get_cmd_string(cmd->hdr.cmd)); |
3e10caeb | 940 | wake_up_interruptible(&trans->shrd->wait_command_queue); |
17b88929 | 941 | } |
3598e177 | 942 | |
dd487449 | 943 | meta->flags = 0; |
3598e177 | 944 | |
72012474 | 945 | spin_unlock_irqrestore(&trans->hcmd_lock, flags); |
17b88929 | 946 | } |
253a634c EG |
947 | |
948 | const char *get_cmd_string(u8 cmd) | |
949 | { | |
950 | switch (cmd) { | |
951 | IWL_CMD(REPLY_ALIVE); | |
952 | IWL_CMD(REPLY_ERROR); | |
953 | IWL_CMD(REPLY_RXON); | |
954 | IWL_CMD(REPLY_RXON_ASSOC); | |
955 | IWL_CMD(REPLY_QOS_PARAM); | |
956 | IWL_CMD(REPLY_RXON_TIMING); | |
957 | IWL_CMD(REPLY_ADD_STA); | |
958 | IWL_CMD(REPLY_REMOVE_STA); | |
959 | IWL_CMD(REPLY_REMOVE_ALL_STA); | |
960 | IWL_CMD(REPLY_TXFIFO_FLUSH); | |
961 | IWL_CMD(REPLY_WEPKEY); | |
962 | IWL_CMD(REPLY_TX); | |
963 | IWL_CMD(REPLY_LEDS_CMD); | |
964 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | |
965 | IWL_CMD(COEX_PRIORITY_TABLE_CMD); | |
966 | IWL_CMD(COEX_MEDIUM_NOTIFICATION); | |
967 | IWL_CMD(COEX_EVENT_CMD); | |
968 | IWL_CMD(REPLY_QUIET_CMD); | |
969 | IWL_CMD(REPLY_CHANNEL_SWITCH); | |
970 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | |
971 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | |
972 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | |
973 | IWL_CMD(POWER_TABLE_CMD); | |
974 | IWL_CMD(PM_SLEEP_NOTIFICATION); | |
975 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | |
976 | IWL_CMD(REPLY_SCAN_CMD); | |
977 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | |
978 | IWL_CMD(SCAN_START_NOTIFICATION); | |
979 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | |
980 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | |
981 | IWL_CMD(BEACON_NOTIFICATION); | |
982 | IWL_CMD(REPLY_TX_BEACON); | |
983 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | |
984 | IWL_CMD(QUIET_NOTIFICATION); | |
985 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | |
986 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | |
987 | IWL_CMD(REPLY_BT_CONFIG); | |
988 | IWL_CMD(REPLY_STATISTICS_CMD); | |
989 | IWL_CMD(STATISTICS_NOTIFICATION); | |
990 | IWL_CMD(REPLY_CARD_STATE_CMD); | |
991 | IWL_CMD(CARD_STATE_NOTIFICATION); | |
992 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | |
993 | IWL_CMD(REPLY_CT_KILL_CONFIG_CMD); | |
994 | IWL_CMD(SENSITIVITY_CMD); | |
995 | IWL_CMD(REPLY_PHY_CALIBRATION_CMD); | |
996 | IWL_CMD(REPLY_RX_PHY_CMD); | |
997 | IWL_CMD(REPLY_RX_MPDU_CMD); | |
998 | IWL_CMD(REPLY_RX); | |
999 | IWL_CMD(REPLY_COMPRESSED_BA); | |
1000 | IWL_CMD(CALIBRATION_CFG_CMD); | |
1001 | IWL_CMD(CALIBRATION_RES_NOTIFICATION); | |
1002 | IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION); | |
1003 | IWL_CMD(REPLY_TX_POWER_DBM_CMD); | |
1004 | IWL_CMD(TEMPERATURE_NOTIFICATION); | |
1005 | IWL_CMD(TX_ANT_CONFIGURATION_CMD); | |
1006 | IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF); | |
1007 | IWL_CMD(REPLY_BT_COEX_PRIO_TABLE); | |
1008 | IWL_CMD(REPLY_BT_COEX_PROT_ENV); | |
1009 | IWL_CMD(REPLY_WIPAN_PARAMS); | |
1010 | IWL_CMD(REPLY_WIPAN_RXON); | |
1011 | IWL_CMD(REPLY_WIPAN_RXON_TIMING); | |
1012 | IWL_CMD(REPLY_WIPAN_RXON_ASSOC); | |
1013 | IWL_CMD(REPLY_WIPAN_QOS_PARAM); | |
1014 | IWL_CMD(REPLY_WIPAN_WEPKEY); | |
1015 | IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH); | |
1016 | IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION); | |
1017 | IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE); | |
c8ac61cf JB |
1018 | IWL_CMD(REPLY_WOWLAN_PATTERNS); |
1019 | IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER); | |
1020 | IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS); | |
1021 | IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS); | |
1022 | IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL); | |
1023 | IWL_CMD(REPLY_WOWLAN_GET_STATUS); | |
253a634c EG |
1024 | default: |
1025 | return "UNKNOWN"; | |
1026 | ||
1027 | } | |
1028 | } | |
1029 | ||
1030 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) | |
1031 | ||
3e10caeb | 1032 | static void iwl_generic_cmd_callback(struct iwl_shared *shrd, |
253a634c EG |
1033 | struct iwl_device_cmd *cmd, |
1034 | struct iwl_rx_packet *pkt) | |
1035 | { | |
1036 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
3e10caeb | 1037 | IWL_ERR(shrd->trans, "Bad return from %s (0x%08X)\n", |
253a634c EG |
1038 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
1039 | return; | |
1040 | } | |
1041 | ||
1042 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1043 | switch (cmd->hdr.cmd) { | |
1044 | case REPLY_TX_LINK_QUALITY_CMD: | |
1045 | case SENSITIVITY_CMD: | |
3e10caeb | 1046 | IWL_DEBUG_HC_DUMP(shrd->trans, "back from %s (0x%08X)\n", |
253a634c EG |
1047 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
1048 | break; | |
1049 | default: | |
3e10caeb | 1050 | IWL_DEBUG_HC(shrd->trans, "back from %s (0x%08X)\n", |
253a634c EG |
1051 | get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
1052 | } | |
1053 | #endif | |
1054 | } | |
1055 | ||
6d8f6eeb | 1056 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
1057 | { |
1058 | int ret; | |
1059 | ||
1060 | /* An asynchronous command can not expect an SKB to be set. */ | |
1061 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1062 | return -EINVAL; | |
1063 | ||
1064 | /* Assign a generic callback if one is not provided */ | |
1065 | if (!cmd->callback) | |
1066 | cmd->callback = iwl_generic_cmd_callback; | |
1067 | ||
6d8f6eeb | 1068 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
253a634c EG |
1069 | return -EBUSY; |
1070 | ||
6d8f6eeb | 1071 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 1072 | if (ret < 0) { |
6d8f6eeb | 1073 | IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
1074 | get_cmd_string(cmd->id), ret); |
1075 | return ret; | |
1076 | } | |
1077 | return 0; | |
1078 | } | |
1079 | ||
6d8f6eeb | 1080 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1081 | { |
8ad71bef | 1082 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1083 | int cmd_idx; |
1084 | int ret; | |
1085 | ||
6d8f6eeb | 1086 | lockdep_assert_held(&trans->shrd->mutex); |
253a634c EG |
1087 | |
1088 | /* A synchronous command can not have a callback set. */ | |
1089 | if (WARN_ON(cmd->callback)) | |
1090 | return -EINVAL; | |
1091 | ||
6d8f6eeb | 1092 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
253a634c EG |
1093 | get_cmd_string(cmd->id)); |
1094 | ||
6d8f6eeb EG |
1095 | set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
1096 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", | |
253a634c EG |
1097 | get_cmd_string(cmd->id)); |
1098 | ||
6d8f6eeb | 1099 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
1100 | if (cmd_idx < 0) { |
1101 | ret = cmd_idx; | |
6d8f6eeb EG |
1102 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
1103 | IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n", | |
253a634c EG |
1104 | get_cmd_string(cmd->id), ret); |
1105 | return ret; | |
1106 | } | |
1107 | ||
3e10caeb | 1108 | ret = wait_event_interruptible_timeout(trans->shrd->wait_command_queue, |
6d8f6eeb | 1109 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), |
253a634c EG |
1110 | HOST_COMPLETE_TIMEOUT); |
1111 | if (!ret) { | |
6d8f6eeb EG |
1112 | if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
1113 | IWL_ERR(trans, | |
253a634c EG |
1114 | "Error sending %s: time out after %dms.\n", |
1115 | get_cmd_string(cmd->id), | |
1116 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
1117 | ||
6d8f6eeb EG |
1118 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
1119 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command" | |
253a634c EG |
1120 | "%s\n", get_cmd_string(cmd->id)); |
1121 | ret = -ETIMEDOUT; | |
1122 | goto cancel; | |
1123 | } | |
1124 | } | |
1125 | ||
6d8f6eeb EG |
1126 | if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) { |
1127 | IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n", | |
253a634c EG |
1128 | get_cmd_string(cmd->id)); |
1129 | ret = -ECANCELED; | |
1130 | goto fail; | |
1131 | } | |
6d8f6eeb EG |
1132 | if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) { |
1133 | IWL_ERR(trans, "Command %s failed: FW Error\n", | |
253a634c EG |
1134 | get_cmd_string(cmd->id)); |
1135 | ret = -EIO; | |
1136 | goto fail; | |
1137 | } | |
1138 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { | |
6d8f6eeb | 1139 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
253a634c EG |
1140 | get_cmd_string(cmd->id)); |
1141 | ret = -EIO; | |
1142 | goto cancel; | |
1143 | } | |
1144 | ||
1145 | return 0; | |
1146 | ||
1147 | cancel: | |
1148 | if (cmd->flags & CMD_WANT_SKB) { | |
1149 | /* | |
1150 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1151 | * TX cmd queue. Otherwise in case the cmd comes | |
1152 | * in later, it will possibly set an invalid | |
1153 | * address (cmd->meta.source). | |
1154 | */ | |
8ad71bef | 1155 | trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
1156 | ~CMD_WANT_SKB; |
1157 | } | |
1158 | fail: | |
1159 | if (cmd->reply_page) { | |
6d8f6eeb | 1160 | iwl_free_pages(trans->shrd, cmd->reply_page); |
253a634c EG |
1161 | cmd->reply_page = 0; |
1162 | } | |
1163 | ||
1164 | return ret; | |
1165 | } | |
1166 | ||
6d8f6eeb | 1167 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
1168 | { |
1169 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 1170 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 1171 | |
6d8f6eeb | 1172 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
1173 | } |
1174 | ||
6d8f6eeb | 1175 | int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags, |
e6bb4c9c | 1176 | u16 len, const void *data) |
253a634c EG |
1177 | { |
1178 | struct iwl_host_cmd cmd = { | |
1179 | .id = id, | |
1180 | .len = { len, }, | |
1181 | .data = { data, }, | |
1182 | .flags = flags, | |
1183 | }; | |
1184 | ||
6d8f6eeb | 1185 | return iwl_trans_pcie_send_cmd(trans, &cmd); |
253a634c | 1186 | } |
a0eaad71 EG |
1187 | |
1188 | /* Frees buffers until index _not_ inclusive */ | |
464021ff EG |
1189 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
1190 | struct sk_buff_head *skbs) | |
a0eaad71 | 1191 | { |
8ad71bef EG |
1192 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1193 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 1194 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 1195 | int last_to_free; |
464021ff | 1196 | int freed = 0; |
a0eaad71 EG |
1197 | |
1198 | /*Since we free until index _not_ inclusive, the one before index is | |
1199 | * the last we will free. This one must be used */ | |
1200 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
1201 | ||
1202 | if ((index >= q->n_bd) || | |
1203 | (iwl_queue_used(q, last_to_free) == 0)) { | |
1204 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
1205 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
1206 | __func__, txq_id, last_to_free, q->n_bd, | |
1207 | q->write_ptr, q->read_ptr); | |
464021ff | 1208 | return 0; |
a0eaad71 EG |
1209 | } |
1210 | ||
1211 | IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id, | |
1212 | q->read_ptr, index); | |
1213 | ||
1214 | if (WARN_ON(!skb_queue_empty(skbs))) | |
464021ff | 1215 | return 0; |
a0eaad71 EG |
1216 | |
1217 | for (; | |
1218 | q->read_ptr != index; | |
1219 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1220 | ||
2c452297 | 1221 | if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL)) |
a0eaad71 EG |
1222 | continue; |
1223 | ||
2c452297 | 1224 | __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]); |
a0eaad71 | 1225 | |
2c452297 | 1226 | txq->skbs[txq->q.read_ptr] = NULL; |
a0eaad71 | 1227 | |
6d8f6eeb | 1228 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 1229 | |
6d8f6eeb | 1230 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr); |
464021ff | 1231 | freed++; |
a0eaad71 | 1232 | } |
464021ff | 1233 | return freed; |
a0eaad71 | 1234 | } |