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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a0f6b0a2 | 63 | #include "iwl-dev.h" |
c85eb619 | 64 | #include "iwl-trans.h" |
02aca585 EG |
65 | #include "iwl-core.h" |
66 | #include "iwl-helpers.h" | |
67 | /*TODO remove uneeded includes when the transport layer tx_free will be here */ | |
68 | #include "iwl-agn.h" | |
e419d62d | 69 | #include "iwl-core.h" |
c85eb619 EG |
70 | |
71 | static int iwl_trans_rx_alloc(struct iwl_priv *priv) | |
72 | { | |
73 | struct iwl_rx_queue *rxq = &priv->rxq; | |
74 | struct device *dev = priv->bus.dev; | |
75 | ||
76 | memset(&priv->rxq, 0, sizeof(priv->rxq)); | |
77 | ||
78 | spin_lock_init(&rxq->lock); | |
79 | INIT_LIST_HEAD(&rxq->rx_free); | |
80 | INIT_LIST_HEAD(&rxq->rx_used); | |
81 | ||
82 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
83 | return -EINVAL; | |
84 | ||
85 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
a0f6b0a2 EG |
86 | rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
87 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
88 | if (!rxq->bd) |
89 | goto err_bd; | |
a0f6b0a2 | 90 | memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE); |
c85eb619 EG |
91 | |
92 | /*Allocate the driver's pointer to receive buffer status */ | |
93 | rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts), | |
94 | &rxq->rb_stts_dma, GFP_KERNEL); | |
95 | if (!rxq->rb_stts) | |
96 | goto err_rb_stts; | |
97 | memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); | |
98 | ||
99 | return 0; | |
100 | ||
101 | err_rb_stts: | |
a0f6b0a2 EG |
102 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
103 | rxq->bd, rxq->bd_dma); | |
c85eb619 EG |
104 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
105 | rxq->bd = NULL; | |
106 | err_bd: | |
107 | return -ENOMEM; | |
108 | } | |
109 | ||
a0f6b0a2 | 110 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_priv *priv) |
c85eb619 EG |
111 | { |
112 | struct iwl_rx_queue *rxq = &priv->rxq; | |
a0f6b0a2 | 113 | int i; |
c85eb619 EG |
114 | |
115 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
116 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
117 | /* In the reset function, these buffers may have been allocated | |
118 | * to an SKB, so we need to unmap and free potential storage */ | |
119 | if (rxq->pool[i].page != NULL) { | |
120 | dma_unmap_page(priv->bus.dev, rxq->pool[i].page_dma, | |
121 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
122 | DMA_FROM_DEVICE); | |
123 | __iwl_free_pages(priv, rxq->pool[i].page); | |
124 | rxq->pool[i].page = NULL; | |
125 | } | |
126 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
127 | } | |
a0f6b0a2 EG |
128 | } |
129 | ||
130 | static int iwl_trans_rx_init(struct iwl_priv *priv) | |
131 | { | |
132 | struct iwl_rx_queue *rxq = &priv->rxq; | |
133 | int i, err; | |
134 | unsigned long flags; | |
135 | ||
136 | if (!rxq->bd) { | |
137 | err = iwl_trans_rx_alloc(priv); | |
138 | if (err) | |
139 | return err; | |
140 | } | |
141 | ||
142 | spin_lock_irqsave(&rxq->lock, flags); | |
143 | INIT_LIST_HEAD(&rxq->rx_free); | |
144 | INIT_LIST_HEAD(&rxq->rx_used); | |
145 | ||
146 | iwl_trans_rxq_free_rx_bufs(priv); | |
c85eb619 EG |
147 | |
148 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
149 | rxq->queue[i] = NULL; | |
150 | ||
151 | /* Set us so that we have processed and used all buffers, but have | |
152 | * not restocked the Rx queue with fresh buffers */ | |
153 | rxq->read = rxq->write = 0; | |
154 | rxq->write_actual = 0; | |
155 | rxq->free_count = 0; | |
156 | spin_unlock_irqrestore(&rxq->lock, flags); | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
a0f6b0a2 EG |
161 | static void iwl_trans_rx_free(struct iwl_priv *priv) |
162 | { | |
163 | struct iwl_rx_queue *rxq = &priv->rxq; | |
164 | unsigned long flags; | |
165 | ||
166 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
167 | * exit now */ | |
168 | if (!rxq->bd) { | |
169 | IWL_DEBUG_INFO(priv, "Free NULL rx context\n"); | |
170 | return; | |
171 | } | |
172 | ||
173 | spin_lock_irqsave(&rxq->lock, flags); | |
174 | iwl_trans_rxq_free_rx_bufs(priv); | |
175 | spin_unlock_irqrestore(&rxq->lock, flags); | |
176 | ||
177 | dma_free_coherent(priv->bus.dev, sizeof(__le32) * RX_QUEUE_SIZE, | |
178 | rxq->bd, rxq->bd_dma); | |
179 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
180 | rxq->bd = NULL; | |
181 | ||
182 | if (rxq->rb_stts) | |
183 | dma_free_coherent(priv->bus.dev, | |
184 | sizeof(struct iwl_rb_status), | |
185 | rxq->rb_stts, rxq->rb_stts_dma); | |
186 | else | |
187 | IWL_DEBUG_INFO(priv, "Free rxq->rb_stts which is NULL\n"); | |
188 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); | |
189 | rxq->rb_stts = NULL; | |
190 | } | |
191 | ||
c2c52e8b EG |
192 | static int iwl_trans_rx_stop(struct iwl_priv *priv) |
193 | { | |
194 | ||
195 | /* stop Rx DMA */ | |
196 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
197 | return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, | |
198 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
199 | } | |
200 | ||
02aca585 EG |
201 | static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv, |
202 | struct iwl_dma_ptr *ptr, size_t size) | |
203 | { | |
204 | if (WARN_ON(ptr->addr)) | |
205 | return -EINVAL; | |
206 | ||
207 | ptr->addr = dma_alloc_coherent(priv->bus.dev, size, | |
208 | &ptr->dma, GFP_KERNEL); | |
209 | if (!ptr->addr) | |
210 | return -ENOMEM; | |
211 | ptr->size = size; | |
212 | return 0; | |
213 | } | |
214 | ||
1359ca4f EG |
215 | static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv, |
216 | struct iwl_dma_ptr *ptr) | |
217 | { | |
218 | if (unlikely(!ptr->addr)) | |
219 | return; | |
220 | ||
221 | dma_free_coherent(priv->bus.dev, ptr->size, ptr->addr, ptr->dma); | |
222 | memset(ptr, 0, sizeof(*ptr)); | |
223 | } | |
224 | ||
02aca585 EG |
225 | static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
226 | int slots_num, u32 txq_id) | |
227 | { | |
228 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; | |
229 | int i; | |
230 | ||
231 | if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds)) | |
232 | return -EINVAL; | |
233 | ||
1359ca4f EG |
234 | txq->q.n_window = slots_num; |
235 | ||
02aca585 EG |
236 | txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num, |
237 | GFP_KERNEL); | |
238 | txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num, | |
239 | GFP_KERNEL); | |
240 | ||
241 | if (!txq->meta || !txq->cmd) | |
242 | goto error; | |
243 | ||
244 | for (i = 0; i < slots_num; i++) { | |
245 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), | |
246 | GFP_KERNEL); | |
247 | if (!txq->cmd[i]) | |
248 | goto error; | |
249 | } | |
250 | ||
251 | /* Alloc driver data array and TFD circular buffer */ | |
252 | /* Driver private data, only for Tx (not command) queues, | |
253 | * not shared with device. */ | |
254 | if (txq_id != priv->cmd_queue) { | |
255 | txq->txb = kzalloc(sizeof(txq->txb[0]) * | |
256 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
257 | if (!txq->txb) { | |
258 | IWL_ERR(priv, "kmalloc for auxiliary BD " | |
259 | "structures failed\n"); | |
260 | goto error; | |
261 | } | |
262 | } else { | |
263 | txq->txb = NULL; | |
264 | } | |
265 | ||
266 | /* Circular buffer of transmit frame descriptors (TFDs), | |
267 | * shared with device */ | |
268 | txq->tfds = dma_alloc_coherent(priv->bus.dev, tfd_sz, &txq->q.dma_addr, | |
269 | GFP_KERNEL); | |
270 | if (!txq->tfds) { | |
271 | IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz); | |
272 | goto error; | |
273 | } | |
274 | txq->q.id = txq_id; | |
275 | ||
276 | return 0; | |
277 | error: | |
278 | kfree(txq->txb); | |
279 | txq->txb = NULL; | |
280 | /* since txq->cmd has been zeroed, | |
281 | * all non allocated cmd[i] will be NULL */ | |
282 | if (txq->cmd) | |
283 | for (i = 0; i < slots_num; i++) | |
284 | kfree(txq->cmd[i]); | |
285 | kfree(txq->meta); | |
286 | kfree(txq->cmd); | |
287 | txq->meta = NULL; | |
288 | txq->cmd = NULL; | |
289 | ||
290 | return -ENOMEM; | |
291 | ||
292 | } | |
293 | ||
294 | static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, | |
295 | int slots_num, u32 txq_id) | |
296 | { | |
297 | int ret; | |
298 | ||
299 | txq->need_update = 0; | |
300 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); | |
301 | ||
302 | /* | |
303 | * For the default queues 0-3, set up the swq_id | |
304 | * already -- all others need to get one later | |
305 | * (if they need one at all). | |
306 | */ | |
307 | if (txq_id < 4) | |
308 | iwl_set_swq_id(txq, txq_id, txq_id); | |
309 | ||
310 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
311 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
312 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
313 | ||
314 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
315 | ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
316 | txq_id); | |
317 | if (ret) | |
318 | return ret; | |
319 | ||
320 | /* | |
321 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
322 | * given Tx queue, and enable the DMA channel used for that queue. | |
323 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
324 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
325 | txq->q.dma_addr >> 8); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
c170b867 EG |
330 | /** |
331 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
332 | */ | |
333 | static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id) | |
334 | { | |
335 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
336 | struct iwl_queue *q = &txq->q; | |
337 | ||
338 | if (!q->n_bd) | |
339 | return; | |
340 | ||
341 | while (q->write_ptr != q->read_ptr) { | |
342 | /* The read_ptr needs to bound by q->n_window */ | |
343 | iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr)); | |
344 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); | |
345 | } | |
346 | } | |
347 | ||
1359ca4f EG |
348 | /** |
349 | * iwl_tx_queue_free - Deallocate DMA queue. | |
350 | * @txq: Transmit queue to deallocate. | |
351 | * | |
352 | * Empty queue by removing and destroying all BD's. | |
353 | * Free all buffers. | |
354 | * 0-fill, but do not free "txq" descriptor structure. | |
355 | */ | |
356 | static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) | |
357 | { | |
358 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
359 | struct device *dev = priv->bus.dev; | |
360 | int i; | |
361 | if (WARN_ON(!txq)) | |
362 | return; | |
363 | ||
364 | iwl_tx_queue_unmap(priv, txq_id); | |
365 | ||
366 | /* De-alloc array of command/tx buffers */ | |
367 | for (i = 0; i < txq->q.n_window; i++) | |
368 | kfree(txq->cmd[i]); | |
369 | ||
370 | /* De-alloc circular buffer of TFDs */ | |
371 | if (txq->q.n_bd) { | |
372 | dma_free_coherent(dev, priv->hw_params.tfd_size * | |
373 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
374 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
375 | } | |
376 | ||
377 | /* De-alloc array of per-TFD driver data */ | |
378 | kfree(txq->txb); | |
379 | txq->txb = NULL; | |
380 | ||
381 | /* deallocate arrays */ | |
382 | kfree(txq->cmd); | |
383 | kfree(txq->meta); | |
384 | txq->cmd = NULL; | |
385 | txq->meta = NULL; | |
386 | ||
387 | /* 0-fill queue descriptor structure */ | |
388 | memset(txq, 0, sizeof(*txq)); | |
389 | } | |
390 | ||
391 | /** | |
392 | * iwl_trans_tx_free - Free TXQ Context | |
393 | * | |
394 | * Destroy all TX DMA queues and structures | |
395 | */ | |
396 | static void iwl_trans_tx_free(struct iwl_priv *priv) | |
397 | { | |
398 | int txq_id; | |
399 | ||
400 | /* Tx queues */ | |
401 | if (priv->txq) { | |
402 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
403 | iwl_tx_queue_free(priv, txq_id); | |
404 | } | |
405 | ||
406 | kfree(priv->txq); | |
407 | priv->txq = NULL; | |
408 | ||
409 | iwlagn_free_dma_ptr(priv, &priv->kw); | |
410 | ||
411 | iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
412 | } | |
413 | ||
02aca585 EG |
414 | /** |
415 | * iwl_trans_tx_alloc - allocate TX context | |
416 | * Allocate all Tx DMA structures and initialize them | |
417 | * | |
418 | * @param priv | |
419 | * @return error code | |
420 | */ | |
421 | static int iwl_trans_tx_alloc(struct iwl_priv *priv) | |
422 | { | |
423 | int ret; | |
424 | int txq_id, slots_num; | |
425 | ||
426 | /*It is not allowed to alloc twice, so warn when this happens. | |
427 | * We cannot rely on the previous allocation, so free and fail */ | |
428 | if (WARN_ON(priv->txq)) { | |
429 | ret = -EINVAL; | |
430 | goto error; | |
431 | } | |
432 | ||
433 | ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls, | |
434 | priv->hw_params.scd_bc_tbls_size); | |
435 | if (ret) { | |
436 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); | |
437 | goto error; | |
438 | } | |
439 | ||
440 | /* Alloc keep-warm buffer */ | |
441 | ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); | |
442 | if (ret) { | |
443 | IWL_ERR(priv, "Keep Warm allocation failed\n"); | |
444 | goto error; | |
445 | } | |
446 | ||
447 | priv->txq = kzalloc(sizeof(struct iwl_tx_queue) * | |
448 | priv->cfg->base_params->num_of_queues, GFP_KERNEL); | |
449 | if (!priv->txq) { | |
450 | IWL_ERR(priv, "Not enough memory for txq\n"); | |
451 | ret = ENOMEM; | |
452 | goto error; | |
453 | } | |
454 | ||
455 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
456 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
457 | slots_num = (txq_id == priv->cmd_queue) ? | |
458 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
459 | ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num, | |
460 | txq_id); | |
461 | if (ret) { | |
462 | IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id); | |
463 | goto error; | |
464 | } | |
465 | } | |
466 | ||
467 | return 0; | |
468 | ||
469 | error: | |
bdfbf092 | 470 | trans_tx_free(priv); |
02aca585 EG |
471 | |
472 | return ret; | |
473 | } | |
474 | static int iwl_trans_tx_init(struct iwl_priv *priv) | |
475 | { | |
476 | int ret; | |
477 | int txq_id, slots_num; | |
478 | unsigned long flags; | |
479 | bool alloc = false; | |
480 | ||
481 | if (!priv->txq) { | |
482 | ret = iwl_trans_tx_alloc(priv); | |
483 | if (ret) | |
484 | goto error; | |
485 | alloc = true; | |
486 | } | |
487 | ||
488 | spin_lock_irqsave(&priv->lock, flags); | |
489 | ||
490 | /* Turn off all Tx DMA fifos */ | |
491 | iwl_write_prph(priv, IWLAGN_SCD_TXFACT, 0); | |
492 | ||
493 | /* Tell NIC where to find the "keep warm" buffer */ | |
494 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
495 | ||
496 | spin_unlock_irqrestore(&priv->lock, flags); | |
497 | ||
498 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
499 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
500 | slots_num = (txq_id == priv->cmd_queue) ? | |
501 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
502 | ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num, | |
503 | txq_id); | |
504 | if (ret) { | |
505 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); | |
506 | goto error; | |
507 | } | |
508 | } | |
509 | ||
510 | return 0; | |
511 | error: | |
512 | /*Upon error, free only if we allocated something */ | |
513 | if (alloc) | |
bdfbf092 | 514 | trans_tx_free(priv); |
02aca585 EG |
515 | return ret; |
516 | } | |
517 | ||
c170b867 EG |
518 | /** |
519 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
520 | */ | |
521 | static int iwl_trans_tx_stop(struct iwl_priv *priv) | |
522 | { | |
523 | int ch, txq_id; | |
524 | unsigned long flags; | |
525 | ||
526 | /* Turn off all Tx DMA fifos */ | |
527 | spin_lock_irqsave(&priv->lock, flags); | |
528 | ||
529 | iwlagn_txq_set_sched(priv, 0); | |
530 | ||
531 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 532 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
c170b867 EG |
533 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
534 | if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, | |
535 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), | |
536 | 1000)) | |
537 | IWL_ERR(priv, "Failing on timeout while stopping" | |
538 | " DMA channel %d [0x%08x]", ch, | |
539 | iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG)); | |
540 | } | |
541 | spin_unlock_irqrestore(&priv->lock, flags); | |
542 | ||
543 | if (!priv->txq) { | |
544 | IWL_WARN(priv, "Stopping tx queues that aren't allocated..."); | |
545 | return 0; | |
546 | } | |
547 | ||
548 | /* Unmap DMA from host system and free skb's */ | |
549 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
550 | iwl_tx_queue_unmap(priv, txq_id); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
47c1b496 EG |
555 | static struct iwl_tx_cmd *iwl_trans_get_tx_cmd(struct iwl_priv *priv, |
556 | int txq_id) | |
557 | { | |
558 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
559 | struct iwl_queue *q = &txq->q; | |
560 | struct iwl_device_cmd *dev_cmd; | |
561 | ||
562 | if (unlikely(iwl_queue_space(q) < q->high_mark)) | |
563 | return NULL; | |
564 | ||
565 | /* | |
566 | * Set up the Tx-command (not MAC!) header. | |
567 | * Store the chosen Tx queue and TFD index within the sequence field; | |
568 | * after Tx, uCode's Tx response will return this value so driver can | |
569 | * locate the frame within the tx queue and do post-tx processing. | |
570 | */ | |
571 | dev_cmd = txq->cmd[q->write_ptr]; | |
572 | memset(dev_cmd, 0, sizeof(*dev_cmd)); | |
573 | dev_cmd->hdr.cmd = REPLY_TX; | |
574 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
575 | INDEX_TO_SEQ(q->write_ptr))); | |
576 | return &dev_cmd->cmd.tx; | |
577 | } | |
578 | ||
579 | static int iwl_trans_tx(struct iwl_priv *priv, struct sk_buff *skb, | |
580 | struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu, | |
581 | struct iwl_rxon_context *ctx) | |
582 | { | |
583 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
584 | struct iwl_queue *q = &txq->q; | |
585 | struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr]; | |
586 | struct iwl_cmd_meta *out_meta; | |
587 | ||
588 | dma_addr_t phys_addr = 0; | |
589 | dma_addr_t txcmd_phys; | |
590 | dma_addr_t scratch_phys; | |
591 | u16 len, firstlen, secondlen; | |
592 | u8 wait_write_ptr = 0; | |
593 | u8 hdr_len = ieee80211_hdrlen(fc); | |
594 | ||
595 | /* Set up driver data for this TFD */ | |
596 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
597 | txq->txb[q->write_ptr].skb = skb; | |
598 | txq->txb[q->write_ptr].ctx = ctx; | |
599 | ||
600 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
601 | out_meta = &txq->meta[q->write_ptr]; | |
602 | ||
603 | /* | |
604 | * Use the first empty entry in this queue's command buffer array | |
605 | * to contain the Tx command and MAC header concatenated together | |
606 | * (payload data will be in another buffer). | |
607 | * Size of this varies, due to varying MAC header length. | |
608 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
609 | * of the MAC header (device reads on dword boundaries). | |
610 | * We'll tell device about this padding later. | |
611 | */ | |
612 | len = sizeof(struct iwl_tx_cmd) + | |
613 | sizeof(struct iwl_cmd_header) + hdr_len; | |
614 | firstlen = (len + 3) & ~3; | |
615 | ||
616 | /* Tell NIC about any 2-byte padding after MAC header */ | |
617 | if (firstlen != len) | |
618 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
619 | ||
620 | /* Physical address of this Tx command's header (not MAC header!), | |
621 | * within command buffer array. */ | |
622 | txcmd_phys = dma_map_single(priv->bus.dev, | |
623 | &dev_cmd->hdr, firstlen, | |
624 | DMA_BIDIRECTIONAL); | |
625 | if (unlikely(dma_mapping_error(priv->bus.dev, txcmd_phys))) | |
626 | return -1; | |
627 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
628 | dma_unmap_len_set(out_meta, len, firstlen); | |
629 | ||
630 | if (!ieee80211_has_morefrags(fc)) { | |
631 | txq->need_update = 1; | |
632 | } else { | |
633 | wait_write_ptr = 1; | |
634 | txq->need_update = 0; | |
635 | } | |
636 | ||
637 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
638 | * if any (802.11 null frames have no payload). */ | |
639 | secondlen = skb->len - hdr_len; | |
640 | if (secondlen > 0) { | |
641 | phys_addr = dma_map_single(priv->bus.dev, skb->data + hdr_len, | |
642 | secondlen, DMA_TO_DEVICE); | |
643 | if (unlikely(dma_mapping_error(priv->bus.dev, phys_addr))) { | |
644 | dma_unmap_single(priv->bus.dev, | |
645 | dma_unmap_addr(out_meta, mapping), | |
646 | dma_unmap_len(out_meta, len), | |
647 | DMA_BIDIRECTIONAL); | |
648 | return -1; | |
649 | } | |
650 | } | |
651 | ||
652 | /* Attach buffers to TFD */ | |
653 | iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1); | |
654 | if (secondlen > 0) | |
655 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, | |
656 | secondlen, 0); | |
657 | ||
658 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
659 | offsetof(struct iwl_tx_cmd, scratch); | |
660 | ||
661 | /* take back ownership of DMA buffer to enable update */ | |
662 | dma_sync_single_for_cpu(priv->bus.dev, txcmd_phys, firstlen, | |
663 | DMA_BIDIRECTIONAL); | |
664 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
665 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
666 | ||
667 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n", | |
668 | le16_to_cpu(dev_cmd->hdr.sequence)); | |
669 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); | |
670 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
671 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
672 | ||
673 | /* Set up entry for this TFD in Tx byte-count array */ | |
674 | if (ampdu) | |
675 | iwlagn_txq_update_byte_cnt_tbl(priv, txq, | |
676 | le16_to_cpu(tx_cmd->len)); | |
677 | ||
678 | dma_sync_single_for_device(priv->bus.dev, txcmd_phys, firstlen, | |
679 | DMA_BIDIRECTIONAL); | |
680 | ||
681 | trace_iwlwifi_dev_tx(priv, | |
682 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
683 | sizeof(struct iwl_tfd), | |
684 | &dev_cmd->hdr, firstlen, | |
685 | skb->data + hdr_len, secondlen); | |
686 | ||
687 | /* Tell device the write index *just past* this latest filled TFD */ | |
688 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
689 | iwl_txq_update_write_ptr(priv, txq); | |
690 | ||
691 | /* | |
692 | * At this point the frame is "transmitted" successfully | |
693 | * and we will get a TX status notification eventually, | |
694 | * regardless of the value of ret. "ret" only indicates | |
695 | * whether or not we should update the write pointer. | |
696 | */ | |
697 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { | |
698 | if (wait_write_ptr) { | |
699 | txq->need_update = 1; | |
700 | iwl_txq_update_write_ptr(priv, txq); | |
701 | } else { | |
702 | iwl_stop_queue(priv, txq); | |
703 | } | |
704 | } | |
705 | return 0; | |
706 | } | |
707 | ||
34c1b7ba EG |
708 | static void iwl_trans_free(struct iwl_priv *priv) |
709 | { | |
710 | free_irq(priv->bus.irq, priv); | |
711 | iwl_free_isr_ict(priv); | |
712 | } | |
713 | ||
c85eb619 EG |
714 | static const struct iwl_trans_ops trans_ops = { |
715 | .rx_init = iwl_trans_rx_init, | |
c2c52e8b | 716 | .rx_stop = iwl_trans_rx_stop, |
a0f6b0a2 | 717 | .rx_free = iwl_trans_rx_free, |
02aca585 EG |
718 | |
719 | .tx_init = iwl_trans_tx_init, | |
c170b867 | 720 | .tx_stop = iwl_trans_tx_stop, |
1359ca4f | 721 | .tx_free = iwl_trans_tx_free, |
e419d62d EG |
722 | |
723 | .send_cmd = iwl_send_cmd, | |
724 | .send_cmd_pdu = iwl_send_cmd_pdu, | |
47c1b496 EG |
725 | |
726 | .get_tx_cmd = iwl_trans_get_tx_cmd, | |
727 | .tx = iwl_trans_tx, | |
34c1b7ba EG |
728 | |
729 | .free = iwl_trans_free, | |
c85eb619 EG |
730 | }; |
731 | ||
34c1b7ba | 732 | int iwl_trans_register(struct iwl_priv *priv) |
c85eb619 | 733 | { |
34c1b7ba EG |
734 | int err; |
735 | ||
736 | priv->trans.ops = &trans_ops; | |
737 | ||
738 | iwl_alloc_isr_ict(priv); | |
739 | ||
740 | err = request_irq(priv->bus.irq, iwl_isr_ict, IRQF_SHARED, | |
741 | DRV_NAME, priv); | |
742 | if (err) { | |
743 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus.irq); | |
744 | iwl_free_isr_ict(priv); | |
745 | return err; | |
746 | } | |
747 | ||
748 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
749 | iwl_irq_tasklet, (unsigned long)priv); | |
750 | ||
751 | return 0; | |
c85eb619 | 752 | } |