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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
c85eb619 EG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
c85eb619 EG |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8d193ca2 | 35 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
c85eb619 EG |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
41c50542 EG |
65 | #ifndef __iwl_trans_h__ |
66 | #define __iwl_trans_h__ | |
253a634c | 67 | |
e679378d | 68 | #include <linux/ieee80211.h> |
930dfd5f | 69 | #include <linux/mm.h> /* for page_address */ |
2bfb5092 | 70 | #include <linux/lockdep.h> |
a72b8b08 | 71 | |
69655ebf | 72 | #include "iwl-debug.h" |
6238b008 JB |
73 | #include "iwl-config.h" |
74 | #include "iwl-fw.h" | |
2a988e98 | 75 | #include "iwl-op-mode.h" |
87e5666c | 76 | |
60396183 EG |
77 | /** |
78 | * DOC: Transport layer - what is it ? | |
79 | * | |
0d365ae5 | 80 | * The transport layer is the layer that deals with the HW directly. It provides |
60396183 EG |
81 | * an abstraction of the underlying HW to the upper layer. The transport layer |
82 | * doesn't provide any policy, algorithm or anything of this kind, but only | |
0d365ae5 | 83 | * mechanisms to make the HW do something. It is not completely stateless but |
60396183 EG |
84 | * close to it. |
85 | * We will have an implementation for each different supported bus. | |
86 | */ | |
87 | ||
88 | /** | |
89 | * DOC: Life cycle of the transport layer | |
90 | * | |
91 | * The transport layer has a very precise life cycle. | |
92 | * | |
93 | * 1) A helper function is called during the module initialization and | |
94 | * registers the bus driver's ops with the transport's alloc function. | |
95 | * 2) Bus's probe calls to the transport layer's allocation functions. | |
96 | * Of course this function is bus specific. | |
97 | * 3) This allocation functions will spawn the upper layer which will | |
98 | * register mac80211. | |
99 | * | |
100 | * 4) At some point (i.e. mac80211's start call), the op_mode will call | |
101 | * the following sequence: | |
102 | * start_hw | |
103 | * start_fw | |
104 | * | |
105 | * 5) Then when finished (or reset): | |
a4082843 | 106 | * stop_device |
60396183 EG |
107 | * |
108 | * 6) Eventually, the free function will be called. | |
109 | */ | |
110 | ||
60396183 EG |
111 | /** |
112 | * DOC: Host command section | |
113 | * | |
0d365ae5 | 114 | * A host command is a command issued by the upper layer to the fw. There are |
60396183 EG |
115 | * several versions of fw that have several APIs. The transport layer is |
116 | * completely agnostic to these differences. | |
0d365ae5 | 117 | * The transport does provide helper functionality (i.e. SYNC / ASYNC mode), |
60396183 | 118 | */ |
f8d7c1a1 JB |
119 | #define SEQ_TO_QUEUE(s) (((s) >> 8) & 0x1f) |
120 | #define QUEUE_TO_SEQ(q) (((q) & 0x1f) << 8) | |
121 | #define SEQ_TO_INDEX(s) ((s) & 0xff) | |
122 | #define INDEX_TO_SEQ(i) ((i) & 0xff) | |
123 | #define SEQ_RX_FRAME cpu_to_le16(0x8000) | |
124 | ||
ab02165c AE |
125 | /* |
126 | * those functions retrieve specific information from | |
127 | * the id field in the iwl_host_cmd struct which contains | |
128 | * the command id, the group id and the version of the command | |
129 | * and vice versa | |
130 | */ | |
131 | static inline u8 iwl_cmd_opcode(u32 cmdid) | |
132 | { | |
133 | return cmdid & 0xFF; | |
134 | } | |
135 | ||
136 | static inline u8 iwl_cmd_groupid(u32 cmdid) | |
137 | { | |
138 | return ((cmdid & 0xFF00) >> 8); | |
139 | } | |
140 | ||
141 | static inline u8 iwl_cmd_version(u32 cmdid) | |
142 | { | |
143 | return ((cmdid & 0xFF0000) >> 16); | |
144 | } | |
145 | ||
146 | static inline u32 iwl_cmd_id(u8 opcode, u8 groupid, u8 version) | |
147 | { | |
148 | return opcode + (groupid << 8) + (version << 16); | |
149 | } | |
150 | ||
6eb031d2 SS |
151 | /* make u16 wide id out of u8 group and opcode */ |
152 | #define WIDE_ID(grp, opcode) ((grp << 8) | opcode) | |
153 | ||
88742c9e JB |
154 | /* due to the conversion, this group is special; new groups |
155 | * should be defined in the appropriate fw-api header files | |
156 | */ | |
157 | #define IWL_ALWAYS_LONG_GROUP 1 | |
158 | ||
f8d7c1a1 JB |
159 | /** |
160 | * struct iwl_cmd_header | |
161 | * | |
162 | * This header format appears in the beginning of each command sent from the | |
163 | * driver, and each response/notification received from uCode. | |
164 | */ | |
165 | struct iwl_cmd_header { | |
166 | u8 cmd; /* Command ID: REPLY_RXON, etc. */ | |
ab02165c | 167 | u8 group_id; |
f8d7c1a1 JB |
168 | /* |
169 | * The driver sets up the sequence number to values of its choosing. | |
170 | * uCode does not use this value, but passes it back to the driver | |
171 | * when sending the response to each driver-originated command, so | |
172 | * the driver can match the response to the command. Since the values | |
173 | * don't get used by uCode, the driver may set up an arbitrary format. | |
174 | * | |
175 | * There is one exception: uCode sets bit 15 when it originates | |
176 | * the response/notification, i.e. when the response/notification | |
177 | * is not a direct response to a command sent by the driver. For | |
178 | * example, uCode issues REPLY_RX when it sends a received frame | |
179 | * to the driver; it is not a direct response to any driver command. | |
180 | * | |
181 | * The Linux driver uses the following format: | |
182 | * | |
183 | * 0:7 tfd index - position within TX queue | |
184 | * 8:12 TX queue id | |
185 | * 13:14 reserved | |
186 | * 15 unsolicited RX or uCode-originated notification | |
187 | */ | |
188 | __le16 sequence; | |
189 | } __packed; | |
190 | ||
ab02165c AE |
191 | /** |
192 | * struct iwl_cmd_header_wide | |
193 | * | |
194 | * This header format appears in the beginning of each command sent from the | |
195 | * driver, and each response/notification received from uCode. | |
196 | * this is the wide version that contains more information about the command | |
197 | * like length, version and command type | |
198 | */ | |
199 | struct iwl_cmd_header_wide { | |
200 | u8 cmd; | |
201 | u8 group_id; | |
202 | __le16 sequence; | |
203 | __le16 length; | |
204 | u8 reserved; | |
205 | u8 version; | |
206 | } __packed; | |
207 | ||
f8d7c1a1 | 208 | #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ |
0c19744c JB |
209 | #define FH_RSCSR_FRAME_INVALID 0x55550000 |
210 | #define FH_RSCSR_FRAME_ALIGN 0x40 | |
f8d7c1a1 JB |
211 | |
212 | struct iwl_rx_packet { | |
213 | /* | |
214 | * The first 4 bytes of the RX frame header contain both the RX frame | |
215 | * size and some flags. | |
216 | * Bit fields: | |
217 | * 31: flag flush RB request | |
218 | * 30: flag ignore TC (terminal counter) request | |
219 | * 29: flag fast IRQ request | |
220 | * 28-14: Reserved | |
221 | * 13-00: RX frame size | |
222 | */ | |
223 | __le32 len_n_flags; | |
224 | struct iwl_cmd_header hdr; | |
225 | u8 data[]; | |
226 | } __packed; | |
522376d2 | 227 | |
65b30348 JB |
228 | static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) |
229 | { | |
230 | return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
231 | } | |
232 | ||
233 | static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) | |
234 | { | |
235 | return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); | |
236 | } | |
237 | ||
60396183 EG |
238 | /** |
239 | * enum CMD_MODE - how to send the host commands ? | |
240 | * | |
e89044d7 | 241 | * @CMD_ASYNC: Return right away and don't wait for the response |
a1022927 EG |
242 | * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of |
243 | * the response. The caller needs to call iwl_free_resp when done. | |
98ee7783 | 244 | * @CMD_HIGH_PRIO: The command is high priority - it goes to the front of the |
0d365ae5 | 245 | * command queue, but after other high priority commands. Valid only |
98ee7783 AN |
246 | * with CMD_ASYNC. |
247 | * @CMD_SEND_IN_IDLE: The command should be sent even when the trans is idle. | |
248 | * @CMD_MAKE_TRANS_IDLE: The command response should mark the trans as idle. | |
249 | * @CMD_WAKE_UP_TRANS: The command response should wake up the trans | |
250 | * (i.e. mark it as non-idle). | |
206eea78 JB |
251 | * @CMD_TB_BITMAP_POS: Position of the first bit for the TB bitmap. We need to |
252 | * check that we leave enough room for the TBs bitmap which needs 20 bits. | |
60396183 EG |
253 | */ |
254 | enum CMD_MODE { | |
4a4ee101 JB |
255 | CMD_ASYNC = BIT(0), |
256 | CMD_WANT_SKB = BIT(1), | |
4f59334b | 257 | CMD_SEND_IN_RFKILL = BIT(2), |
98ee7783 AN |
258 | CMD_HIGH_PRIO = BIT(3), |
259 | CMD_SEND_IN_IDLE = BIT(4), | |
260 | CMD_MAKE_TRANS_IDLE = BIT(5), | |
261 | CMD_WAKE_UP_TRANS = BIT(6), | |
206eea78 JB |
262 | |
263 | CMD_TB_BITMAP_POS = 11, | |
522376d2 EG |
264 | }; |
265 | ||
266 | #define DEF_CMD_PAYLOAD_SIZE 320 | |
267 | ||
268 | /** | |
269 | * struct iwl_device_cmd | |
270 | * | |
271 | * For allocation of the command and tx queues, this establishes the overall | |
272 | * size of the largest command we send to uCode, except for commands that | |
273 | * aren't fully copied and use other TFD space. | |
274 | */ | |
275 | struct iwl_device_cmd { | |
ab02165c AE |
276 | union { |
277 | struct { | |
278 | struct iwl_cmd_header hdr; /* uCode API */ | |
279 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
280 | }; | |
281 | struct { | |
282 | struct iwl_cmd_header_wide hdr_wide; | |
283 | u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - | |
284 | sizeof(struct iwl_cmd_header_wide) + | |
285 | sizeof(struct iwl_cmd_header)]; | |
286 | }; | |
287 | }; | |
522376d2 EG |
288 | } __packed; |
289 | ||
290 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) | |
291 | ||
1afbfb60 JB |
292 | /* |
293 | * number of transfer buffers (fragments) per transmit frame descriptor; | |
294 | * this is just the driver's idea, the hardware supports 20 | |
295 | */ | |
296 | #define IWL_MAX_CMD_TBS_PER_TFD 2 | |
522376d2 | 297 | |
60396183 EG |
298 | /** |
299 | * struct iwl_hcmd_dataflag - flag for each one of the chunks of the command | |
300 | * | |
f4feb8ac | 301 | * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's |
60396183 | 302 | * ring. The transport layer doesn't map the command's buffer to DMA, but |
e89044d7 | 303 | * rather copies it to a previously allocated DMA buffer. This flag tells |
60396183 | 304 | * the transport layer not to copy the command, but to map the existing |
3e2c1592 JB |
305 | * buffer (that is passed in) instead. This saves the memcpy and allows |
306 | * commands that are bigger than the fixed buffer to be submitted. | |
307 | * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. | |
f4feb8ac JB |
308 | * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this |
309 | * chunk internally and free it again after the command completes. This | |
310 | * can (currently) be used only once per command. | |
3e2c1592 | 311 | * Note that a TFD entry after a DUP one cannot be a normal copied one. |
60396183 | 312 | */ |
522376d2 EG |
313 | enum iwl_hcmd_dataflag { |
314 | IWL_HCMD_DFL_NOCOPY = BIT(0), | |
f4feb8ac | 315 | IWL_HCMD_DFL_DUP = BIT(1), |
522376d2 EG |
316 | }; |
317 | ||
318 | /** | |
319 | * struct iwl_host_cmd - Host command to the uCode | |
60396183 | 320 | * |
522376d2 | 321 | * @data: array of chunks that composes the data of the host command |
65b94a4a JB |
322 | * @resp_pkt: response packet, if %CMD_WANT_SKB was set |
323 | * @_rx_page_order: (internally used to free response packet) | |
324 | * @_rx_page_addr: (internally used to free response packet) | |
60396183 | 325 | * @flags: can be CMD_* |
e89044d7 | 326 | * @len: array of the lengths of the chunks in data |
60396183 | 327 | * @dataflags: IWL_HCMD_DFL_* |
ab02165c AE |
328 | * @id: command id of the host command, for wide commands encoding the |
329 | * version and group as well | |
522376d2 EG |
330 | */ |
331 | struct iwl_host_cmd { | |
1afbfb60 | 332 | const void *data[IWL_MAX_CMD_TBS_PER_TFD]; |
65b94a4a JB |
333 | struct iwl_rx_packet *resp_pkt; |
334 | unsigned long _rx_page_addr; | |
335 | u32 _rx_page_order; | |
247c61d6 | 336 | |
522376d2 | 337 | u32 flags; |
ab02165c | 338 | u32 id; |
1afbfb60 JB |
339 | u16 len[IWL_MAX_CMD_TBS_PER_TFD]; |
340 | u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; | |
522376d2 | 341 | }; |
41c50542 | 342 | |
65b94a4a JB |
343 | static inline void iwl_free_resp(struct iwl_host_cmd *cmd) |
344 | { | |
345 | free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); | |
346 | } | |
347 | ||
930dfd5f JB |
348 | struct iwl_rx_cmd_buffer { |
349 | struct page *_page; | |
0c19744c JB |
350 | int _offset; |
351 | bool _page_stolen; | |
d13f1862 | 352 | u32 _rx_page_order; |
ed90542b | 353 | unsigned int truesize; |
930dfd5f JB |
354 | }; |
355 | ||
356 | static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) | |
357 | { | |
0c19744c JB |
358 | return (void *)((unsigned long)page_address(r->_page) + r->_offset); |
359 | } | |
360 | ||
361 | static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) | |
362 | { | |
363 | return r->_offset; | |
930dfd5f JB |
364 | } |
365 | ||
366 | static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) | |
367 | { | |
0c19744c JB |
368 | r->_page_stolen = true; |
369 | get_page(r->_page); | |
370 | return r->_page; | |
930dfd5f JB |
371 | } |
372 | ||
d13f1862 EG |
373 | static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) |
374 | { | |
375 | __free_pages(r->_page, r->_rx_page_order); | |
376 | } | |
377 | ||
d663ee73 JB |
378 | #define MAX_NO_RECLAIM_CMDS 6 |
379 | ||
ff110c8f GG |
380 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
381 | ||
9eae88fa JB |
382 | /* |
383 | * Maximum number of HW queues the transport layer | |
384 | * currently supports | |
385 | */ | |
386 | #define IWL_MAX_HW_QUEUES 32 | |
b04db9ac EG |
387 | #define IWL_MAX_TID_COUNT 8 |
388 | #define IWL_FRAME_LIMIT 64 | |
9eae88fa | 389 | |
ddaf5a5b JB |
390 | /** |
391 | * enum iwl_wowlan_status - WoWLAN image/device status | |
392 | * @IWL_D3_STATUS_ALIVE: firmware is still running after resume | |
393 | * @IWL_D3_STATUS_RESET: device was reset while suspended | |
394 | */ | |
395 | enum iwl_d3_status { | |
396 | IWL_D3_STATUS_ALIVE, | |
397 | IWL_D3_STATUS_RESET, | |
398 | }; | |
399 | ||
eb7ff77e AN |
400 | /** |
401 | * enum iwl_trans_status: transport status flags | |
402 | * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed | |
403 | * @STATUS_DEVICE_ENABLED: APM is enabled | |
404 | * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) | |
405 | * @STATUS_INT_ENABLED: interrupts are enabled | |
406 | * @STATUS_RFKILL: the HW RFkill switch is in KILL position | |
407 | * @STATUS_FW_ERROR: the fw is in error state | |
98ee7783 AN |
408 | * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands |
409 | * are sent | |
410 | * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent | |
eb7ff77e AN |
411 | */ |
412 | enum iwl_trans_status { | |
413 | STATUS_SYNC_HCMD_ACTIVE, | |
414 | STATUS_DEVICE_ENABLED, | |
415 | STATUS_TPOWER_PMI, | |
416 | STATUS_INT_ENABLED, | |
417 | STATUS_RFKILL, | |
418 | STATUS_FW_ERROR, | |
98ee7783 AN |
419 | STATUS_TRANS_GOING_IDLE, |
420 | STATUS_TRANS_IDLE, | |
eb7ff77e AN |
421 | }; |
422 | ||
92d743ae MV |
423 | /** |
424 | * struct iwl_trans_config - transport configuration | |
425 | * | |
426 | * @op_mode: pointer to the upper layer. | |
c6f600fc MV |
427 | * @cmd_queue: the index of the command queue. |
428 | * Must be set before start_fw. | |
b04db9ac | 429 | * @cmd_fifo: the fifo for host commands |
4cf677fd | 430 | * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. |
d663ee73 JB |
431 | * @no_reclaim_cmds: Some devices erroneously don't set the |
432 | * SEQ_RX_FRAME bit on some notifications, this is the | |
433 | * list of such notifications to filter. Max length is | |
434 | * %MAX_NO_RECLAIM_CMDS. | |
435 | * @n_no_reclaim_cmds: # of commands in list | |
b2cf410c JB |
436 | * @rx_buf_size_8k: 8 kB RX buffer size needed for A-MSDUs, |
437 | * if unset 4k will be the RX buffer size | |
046db346 EG |
438 | * @bc_table_dword: set to true if the BC table expects the byte count to be |
439 | * in DWORD (as opposed to bytes) | |
3a736bcb | 440 | * @scd_set_active: should the transport configure the SCD for HCMD queue |
ab02165c | 441 | * @wide_cmd_header: firmware supports wide host command header |
d9fb6465 JB |
442 | * @command_names: array of command names, must be 256 entries |
443 | * (one for each command); for debugging only | |
b4821767 LK |
444 | * @sdio_adma_addr: the default address to set for the ADMA in SDIO mode until |
445 | * we get the ALIVE from the uCode | |
92d743ae MV |
446 | */ |
447 | struct iwl_trans_config { | |
448 | struct iwl_op_mode *op_mode; | |
9eae88fa | 449 | |
c6f600fc | 450 | u8 cmd_queue; |
b04db9ac | 451 | u8 cmd_fifo; |
4cf677fd | 452 | unsigned int cmd_q_wdg_timeout; |
d663ee73 | 453 | const u8 *no_reclaim_cmds; |
84cf0e62 | 454 | unsigned int n_no_reclaim_cmds; |
b2cf410c JB |
455 | |
456 | bool rx_buf_size_8k; | |
046db346 | 457 | bool bc_table_dword; |
3a736bcb | 458 | bool scd_set_active; |
ab02165c | 459 | bool wide_cmd_header; |
e5209263 | 460 | const char *const *command_names; |
b4821767 LK |
461 | |
462 | u32 sdio_adma_addr; | |
92d743ae MV |
463 | }; |
464 | ||
48eb7b34 EG |
465 | struct iwl_trans_dump_data { |
466 | u32 len; | |
467 | u8 data[]; | |
468 | }; | |
469 | ||
87ce05a2 EG |
470 | struct iwl_trans; |
471 | ||
fea7795f JB |
472 | struct iwl_trans_txq_scd_cfg { |
473 | u8 fifo; | |
474 | s8 sta_id; | |
475 | u8 tid; | |
64ba8930 | 476 | bool aggregate; |
fea7795f JB |
477 | int frame_limit; |
478 | }; | |
479 | ||
41c50542 EG |
480 | /** |
481 | * struct iwl_trans_ops - transport specific operations | |
60396183 EG |
482 | * |
483 | * All the handlers MUST be implemented | |
484 | * | |
8d193ca2 EH |
485 | * @start_hw: starts the HW. If low_power is true, the NIC needs to be taken |
486 | * out of a low power state. From that point on, the HW can send | |
487 | * interrupts. May sleep. | |
a4082843 | 488 | * @op_mode_leave: Turn off the HW RF kill indication if on |
60396183 | 489 | * May sleep |
cf614297 | 490 | * @start_fw: allocates and inits all the resources for the transport |
60396183 EG |
491 | * layer. Also kick a fw image. |
492 | * May sleep | |
adca1235 EG |
493 | * @fw_alive: called when the fw sends alive notification. If the fw provides |
494 | * the SCD base address in SRAM, then provide it here, or 0 otherwise. | |
60396183 | 495 | * May sleep |
a4082843 | 496 | * @stop_device: stops the whole device (embedded CPU put to reset) and stops |
8d193ca2 EH |
497 | * the HW. If low_power is true, the NIC will be put in low power state. |
498 | * From that point on, the HW will be stopped but will still issue an | |
499 | * interrupt if the HW RF kill switch is triggered. | |
500 | * This callback must do the right thing and not crash even if %start_hw() | |
501 | * was called but not &start_fw(). May sleep. | |
ddaf5a5b | 502 | * @d3_suspend: put the device into the correct mode for WoWLAN during |
2dd4f9f7 JB |
503 | * suspend. This is optional, if not implemented WoWLAN will not be |
504 | * supported. This callback may sleep. | |
ddaf5a5b JB |
505 | * @d3_resume: resume the device after WoWLAN, enabling the opmode to |
506 | * talk to the WoWLAN image to get its status. This is optional, if not | |
507 | * implemented WoWLAN will not be supported. This callback may sleep. | |
f946b529 EG |
508 | * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. |
509 | * If RFkill is asserted in the middle of a SYNC host command, it must | |
510 | * return -ERFKILL straight away. | |
a1022927 | 511 | * May sleep only if CMD_ASYNC is not set |
41c50542 | 512 | * @tx: send an skb |
60396183 | 513 | * Must be atomic |
a0eaad71 | 514 | * @reclaim: free packet until ssn. Returns a list of freed packets. |
60396183 | 515 | * Must be atomic |
b04db9ac EG |
516 | * @txq_enable: setup a queue. To setup an AC queue, use the |
517 | * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before | |
d4578ea8 JB |
518 | * this one. The op_mode must not configure the HCMD queue. The scheduler |
519 | * configuration may be %NULL, in which case the hardware will not be | |
520 | * configured. May sleep. | |
d0624be6 | 521 | * @txq_disable: de-configure a Tx queue to send AMPDUs |
b0b46192 | 522 | * Must be atomic |
3cafdbe6 | 523 | * @wait_tx_queue_empty: wait until tx queues are empty. May sleep. |
e0b8d405 EG |
524 | * @freeze_txq_timer: prevents the timer of the queue from firing until the |
525 | * queue is set to awake. Must be atomic. | |
87e5666c EG |
526 | * @dbgfs_register: add the dbgfs files under this directory. Files will be |
527 | * automatically deleted. | |
03905495 EG |
528 | * @write8: write a u8 to a register at offset ofs from the BAR |
529 | * @write32: write a u32 to a register at offset ofs from the BAR | |
530 | * @read32: read a u32 register at offset ofs from the BAR | |
6a06b6c1 EG |
531 | * @read_prph: read a DWORD from a periphery register |
532 | * @write_prph: write a DWORD to a periphery register | |
4fd442db | 533 | * @read_mem: read device's SRAM in DWORD |
01387ffd EG |
534 | * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory |
535 | * will be zeroed. | |
c6f600fc | 536 | * @configure: configure parameters required by the transport layer from |
3dc420be EG |
537 | * the op_mode. May be called several times before start_fw, can't be |
538 | * called after that. | |
47107e84 | 539 | * @set_pmi: set the power pmi state |
e56b04ef LE |
540 | * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. |
541 | * Sleeping is not allowed between grab_nic_access and | |
542 | * release_nic_access. | |
543 | * @release_nic_access: let the NIC go to sleep. The "flags" parameter | |
544 | * must be the same one that was sent before to the grab_nic_access. | |
e139dc4a | 545 | * @set_bits_mask - set SRAM register according to value and mask. |
440c411d EP |
546 | * @ref: grab a reference to the transport/FW layers, disallowing |
547 | * certain low power states | |
548 | * @unref: release a reference previously taken with @ref. Note that | |
549 | * initially the reference count is 1, making an initial @unref | |
550 | * necessary to allow low power states. | |
48eb7b34 EG |
551 | * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last |
552 | * TX'ed commands and similar. The buffer will be vfree'd by the caller. | |
4d075007 | 553 | * Note that the transport must fill in the proper file headers. |
41c50542 EG |
554 | */ |
555 | struct iwl_trans_ops { | |
556 | ||
8d193ca2 | 557 | int (*start_hw)(struct iwl_trans *iwl_trans, bool low_power); |
a4082843 | 558 | void (*op_mode_leave)(struct iwl_trans *iwl_trans); |
6ae02f3e EG |
559 | int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, |
560 | bool run_in_rfkill); | |
91479b64 EH |
561 | int (*update_sf)(struct iwl_trans *trans, |
562 | struct iwl_sf_region *st_fwrd_space); | |
adca1235 | 563 | void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); |
8d193ca2 | 564 | void (*stop_device)(struct iwl_trans *trans, bool low_power); |
41c50542 | 565 | |
debff618 JB |
566 | void (*d3_suspend)(struct iwl_trans *trans, bool test); |
567 | int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, | |
568 | bool test); | |
2dd4f9f7 | 569 | |
6d8f6eeb | 570 | int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
41c50542 | 571 | |
e13c0c59 | 572 | int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa JB |
573 | struct iwl_device_cmd *dev_cmd, int queue); |
574 | void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, | |
575 | struct sk_buff_head *skbs); | |
576 | ||
fea7795f | 577 | void (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, |
4cf677fd EG |
578 | const struct iwl_trans_txq_scd_cfg *cfg, |
579 | unsigned int queue_wdg_timeout); | |
d4578ea8 JB |
580 | void (*txq_disable)(struct iwl_trans *trans, int queue, |
581 | bool configure_scd); | |
41c50542 | 582 | |
87e5666c | 583 | int (*dbgfs_register)(struct iwl_trans *trans, struct dentry* dir); |
3cafdbe6 | 584 | int (*wait_tx_queue_empty)(struct iwl_trans *trans, u32 txq_bm); |
e0b8d405 EG |
585 | void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, |
586 | bool freeze); | |
5fdda047 | 587 | |
03905495 EG |
588 | void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); |
589 | void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); | |
590 | u32 (*read32)(struct iwl_trans *trans, u32 ofs); | |
6a06b6c1 EG |
591 | u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); |
592 | void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); | |
4fd442db EG |
593 | int (*read_mem)(struct iwl_trans *trans, u32 addr, |
594 | void *buf, int dwords); | |
595 | int (*write_mem)(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 596 | const void *buf, int dwords); |
c6f600fc MV |
597 | void (*configure)(struct iwl_trans *trans, |
598 | const struct iwl_trans_config *trans_cfg); | |
47107e84 | 599 | void (*set_pmi)(struct iwl_trans *trans, bool state); |
e56b04ef LE |
600 | bool (*grab_nic_access)(struct iwl_trans *trans, bool silent, |
601 | unsigned long *flags); | |
602 | void (*release_nic_access)(struct iwl_trans *trans, | |
603 | unsigned long *flags); | |
e139dc4a LE |
604 | void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, |
605 | u32 value); | |
440c411d EP |
606 | void (*ref)(struct iwl_trans *trans); |
607 | void (*unref)(struct iwl_trans *trans); | |
c43fe907 | 608 | int (*suspend)(struct iwl_trans *trans); |
8e551e50 | 609 | void (*resume)(struct iwl_trans *trans); |
4d075007 | 610 | |
36fb9017 OG |
611 | struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, |
612 | struct iwl_fw_dbg_trigger_tlv | |
613 | *trigger); | |
41c50542 EG |
614 | }; |
615 | ||
69655ebf EG |
616 | /** |
617 | * enum iwl_trans_state - state of the transport layer | |
618 | * | |
619 | * @IWL_TRANS_NO_FW: no fw has sent an alive response | |
620 | * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response | |
621 | */ | |
622 | enum iwl_trans_state { | |
623 | IWL_TRANS_NO_FW = 0, | |
624 | IWL_TRANS_FW_ALIVE = 1, | |
625 | }; | |
626 | ||
0f8f93d6 EP |
627 | /** |
628 | * enum iwl_d0i3_mode - d0i3 mode | |
629 | * | |
630 | * @IWL_D0I3_MODE_OFF - d0i3 is disabled | |
631 | * @IWL_D0I3_MODE_ON_IDLE - enter d0i3 when device is idle | |
632 | * (e.g. no active references) | |
633 | * @IWL_D0I3_MODE_ON_SUSPEND - enter d0i3 only on suspend | |
634 | * (in case of 'any' trigger) | |
635 | */ | |
636 | enum iwl_d0i3_mode { | |
637 | IWL_D0I3_MODE_OFF = 0, | |
638 | IWL_D0I3_MODE_ON_IDLE, | |
639 | IWL_D0I3_MODE_ON_SUSPEND, | |
640 | }; | |
641 | ||
6fbfae8e EG |
642 | /** |
643 | * struct iwl_trans - transport common data | |
60396183 | 644 | * |
6fbfae8e | 645 | * @ops - pointer to iwl_trans_ops |
ed277c93 | 646 | * @op_mode - pointer to the op_mode |
035f7ff2 | 647 | * @cfg - pointer to the configuration |
eb7ff77e | 648 | * @status: a bit-mask of transport status flags |
a42a1844 | 649 | * @dev - pointer to struct device * that represents the device |
206eea78 JB |
650 | * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. |
651 | * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. | |
0d365ae5 | 652 | * @hw_id: a u32 with the ID of the device / sub-device. |
60396183 | 653 | * Set during transport allocation. |
9ca85961 | 654 | * @hw_id_str: a string with info about HW ID. Set during transport allocation. |
f6d0e9be | 655 | * @pm_support: set to true in start_hw if link pm is supported |
9180ac50 | 656 | * @ltr_enabled: set to true if the LTR is enabled |
59c647b6 EG |
657 | * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. |
658 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
659 | * @dev_cmd_headroom: room needed for the transport's private use before the | |
660 | * device_cmd for Tx - for internal use only | |
661 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
f042c2eb JB |
662 | * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before |
663 | * starting the firmware, used for tracing | |
664 | * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the | |
665 | * start of the 802.11 header in the @rx_mpdu_cmd | |
bcb079a1 | 666 | * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) |
09e350f7 LK |
667 | * @dbg_dest_tlv: points to the destination TLV for debug |
668 | * @dbg_conf_tlv: array of pointers to configuration TLVs for debug | |
d2709ad7 | 669 | * @dbg_trigger_tlv: array of pointers to triggers TLVs for debug |
09e350f7 | 670 | * @dbg_dest_reg_num: num of reg_ops in %dbg_dest_tlv |
e1120187 MG |
671 | * @paging_req_addr: The location were the FW will upload / download the pages |
672 | * from. The address is set by the opmode | |
673 | * @paging_db: Pointer to the opmode paging data base, the pointer is set by | |
674 | * the opmode. | |
675 | * @paging_download_buf: Buffer used for copying all of the pages before | |
676 | * downloading them to the FW. The buffer is allocated in the opmode | |
6fbfae8e | 677 | */ |
41c50542 EG |
678 | struct iwl_trans { |
679 | const struct iwl_trans_ops *ops; | |
ed277c93 | 680 | struct iwl_op_mode *op_mode; |
035f7ff2 | 681 | const struct iwl_cfg *cfg; |
69655ebf | 682 | enum iwl_trans_state state; |
eb7ff77e | 683 | unsigned long status; |
e6bb4c9c | 684 | |
a42a1844 | 685 | struct device *dev; |
206eea78 | 686 | u32 max_skb_frags; |
08079a49 | 687 | u32 hw_rev; |
99673ee5 | 688 | u32 hw_id; |
9ca85961 | 689 | char hw_id_str[52]; |
a42a1844 | 690 | |
f042c2eb JB |
691 | u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; |
692 | ||
f6d0e9be | 693 | bool pm_support; |
9180ac50 | 694 | bool ltr_enabled; |
97b52cfd | 695 | |
59c647b6 EG |
696 | /* The following fields are internal only */ |
697 | struct kmem_cache *dev_cmd_pool; | |
698 | size_t dev_cmd_headroom; | |
3ec45882 | 699 | char dev_cmd_pool_name[50]; |
59c647b6 | 700 | |
9da987ac MV |
701 | struct dentry *dbgfs_dir; |
702 | ||
2bfb5092 JB |
703 | #ifdef CONFIG_LOCKDEP |
704 | struct lockdep_map sync_cmd_lockdep_map; | |
705 | #endif | |
706 | ||
bcb079a1 IY |
707 | u64 dflt_pwr_limit; |
708 | ||
09e350f7 | 709 | const struct iwl_fw_dbg_dest_tlv *dbg_dest_tlv; |
d2709ad7 EG |
710 | const struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX]; |
711 | struct iwl_fw_dbg_trigger_tlv * const *dbg_trigger_tlv; | |
09e350f7 LK |
712 | u8 dbg_dest_reg_num; |
713 | ||
e1120187 MG |
714 | /* |
715 | * Paging parameters - All of the parameters should be set by the | |
716 | * opmode when paging is enabled | |
717 | */ | |
718 | u32 paging_req_addr; | |
719 | struct iwl_fw_paging *paging_db; | |
720 | void *paging_download_buf; | |
721 | ||
0f8f93d6 EP |
722 | enum iwl_d0i3_mode d0i3_mode; |
723 | ||
54154618 EP |
724 | bool wowlan_d0i3; |
725 | ||
e6bb4c9c EG |
726 | /* pointer to trans specific struct */ |
727 | /*Ensure that this pointer will always be aligned to sizeof pointer */ | |
cbe6ab4e | 728 | char trans_specific[0] __aligned(sizeof(void *)); |
41c50542 EG |
729 | }; |
730 | ||
ed277c93 | 731 | static inline void iwl_trans_configure(struct iwl_trans *trans, |
92d743ae | 732 | const struct iwl_trans_config *trans_cfg) |
ed277c93 | 733 | { |
92d743ae | 734 | trans->op_mode = trans_cfg->op_mode; |
c6f600fc MV |
735 | |
736 | trans->ops->configure(trans, trans_cfg); | |
ed277c93 EG |
737 | } |
738 | ||
8d193ca2 | 739 | static inline int _iwl_trans_start_hw(struct iwl_trans *trans, bool low_power) |
e6bb4c9c | 740 | { |
60396183 EG |
741 | might_sleep(); |
742 | ||
8d193ca2 EH |
743 | return trans->ops->start_hw(trans, low_power); |
744 | } | |
745 | ||
746 | static inline int iwl_trans_start_hw(struct iwl_trans *trans) | |
747 | { | |
748 | return trans->ops->start_hw(trans, true); | |
e6bb4c9c EG |
749 | } |
750 | ||
a4082843 | 751 | static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 752 | { |
60396183 EG |
753 | might_sleep(); |
754 | ||
a4082843 AN |
755 | if (trans->ops->op_mode_leave) |
756 | trans->ops->op_mode_leave(trans); | |
69655ebf | 757 | |
a4082843 | 758 | trans->op_mode = NULL; |
b4991f3f | 759 | |
69655ebf | 760 | trans->state = IWL_TRANS_NO_FW; |
cc56feb2 EG |
761 | } |
762 | ||
adca1235 | 763 | static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 764 | { |
60396183 EG |
765 | might_sleep(); |
766 | ||
69655ebf | 767 | trans->state = IWL_TRANS_FW_ALIVE; |
b04db9ac | 768 | |
adca1235 | 769 | trans->ops->fw_alive(trans, scd_addr); |
ed6a3803 EG |
770 | } |
771 | ||
0692fe41 | 772 | static inline int iwl_trans_start_fw(struct iwl_trans *trans, |
6ae02f3e EG |
773 | const struct fw_img *fw, |
774 | bool run_in_rfkill) | |
bdfbf092 | 775 | { |
cf614297 EG |
776 | might_sleep(); |
777 | ||
f042c2eb JB |
778 | WARN_ON_ONCE(!trans->rx_mpdu_cmd); |
779 | ||
efbf6e3b | 780 | clear_bit(STATUS_FW_ERROR, &trans->status); |
6ae02f3e | 781 | return trans->ops->start_fw(trans, fw, run_in_rfkill); |
bdfbf092 EG |
782 | } |
783 | ||
91479b64 EH |
784 | static inline int iwl_trans_update_sf(struct iwl_trans *trans, |
785 | struct iwl_sf_region *st_fwrd_space) | |
786 | { | |
787 | might_sleep(); | |
788 | ||
789 | if (trans->ops->update_sf) | |
790 | return trans->ops->update_sf(trans, st_fwrd_space); | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
8d193ca2 EH |
795 | static inline void _iwl_trans_stop_device(struct iwl_trans *trans, |
796 | bool low_power) | |
bdfbf092 | 797 | { |
60396183 EG |
798 | might_sleep(); |
799 | ||
8d193ca2 | 800 | trans->ops->stop_device(trans, low_power); |
69655ebf EG |
801 | |
802 | trans->state = IWL_TRANS_NO_FW; | |
bdfbf092 EG |
803 | } |
804 | ||
8d193ca2 EH |
805 | static inline void iwl_trans_stop_device(struct iwl_trans *trans) |
806 | { | |
807 | _iwl_trans_stop_device(trans, true); | |
808 | } | |
809 | ||
debff618 | 810 | static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test) |
ddaf5a5b JB |
811 | { |
812 | might_sleep(); | |
80de4321 EP |
813 | if (trans->ops->d3_suspend) |
814 | trans->ops->d3_suspend(trans, test); | |
ddaf5a5b JB |
815 | } |
816 | ||
817 | static inline int iwl_trans_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
818 | enum iwl_d3_status *status, |
819 | bool test) | |
2dd4f9f7 JB |
820 | { |
821 | might_sleep(); | |
80de4321 EP |
822 | if (!trans->ops->d3_resume) |
823 | return 0; | |
824 | ||
debff618 | 825 | return trans->ops->d3_resume(trans, status, test); |
2dd4f9f7 JB |
826 | } |
827 | ||
440c411d EP |
828 | static inline void iwl_trans_ref(struct iwl_trans *trans) |
829 | { | |
830 | if (trans->ops->ref) | |
831 | trans->ops->ref(trans); | |
832 | } | |
833 | ||
834 | static inline void iwl_trans_unref(struct iwl_trans *trans) | |
835 | { | |
836 | if (trans->ops->unref) | |
837 | trans->ops->unref(trans); | |
838 | } | |
839 | ||
c43fe907 | 840 | static inline int iwl_trans_suspend(struct iwl_trans *trans) |
8e551e50 | 841 | { |
c43fe907 EP |
842 | if (!trans->ops->suspend) |
843 | return 0; | |
844 | ||
845 | return trans->ops->suspend(trans); | |
8e551e50 EP |
846 | } |
847 | ||
848 | static inline void iwl_trans_resume(struct iwl_trans *trans) | |
849 | { | |
850 | if (trans->ops->resume) | |
851 | trans->ops->resume(trans); | |
852 | } | |
853 | ||
48eb7b34 | 854 | static inline struct iwl_trans_dump_data * |
36fb9017 OG |
855 | iwl_trans_dump_data(struct iwl_trans *trans, |
856 | struct iwl_fw_dbg_trigger_tlv *trigger) | |
4d075007 JB |
857 | { |
858 | if (!trans->ops->dump_data) | |
48eb7b34 | 859 | return NULL; |
36fb9017 | 860 | return trans->ops->dump_data(trans, trigger); |
4d075007 | 861 | } |
4d075007 | 862 | |
e6bb4c9c | 863 | static inline int iwl_trans_send_cmd(struct iwl_trans *trans, |
2bfb5092 | 864 | struct iwl_host_cmd *cmd) |
bdfbf092 | 865 | { |
2bfb5092 JB |
866 | int ret; |
867 | ||
fba1c627 EG |
868 | if (unlikely(!(cmd->flags & CMD_SEND_IN_RFKILL) && |
869 | test_bit(STATUS_RFKILL, &trans->status))) | |
870 | return -ERFKILL; | |
871 | ||
3fc07953 AN |
872 | if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) |
873 | return -EIO; | |
874 | ||
f39a52bf | 875 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) { |
3c6acb61 | 876 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
8ca95995 EG |
877 | return -EIO; |
878 | } | |
69655ebf | 879 | |
2bfb5092 JB |
880 | if (!(cmd->flags & CMD_ASYNC)) |
881 | lock_map_acquire_read(&trans->sync_cmd_lockdep_map); | |
882 | ||
883 | ret = trans->ops->send_cmd(trans, cmd); | |
884 | ||
885 | if (!(cmd->flags & CMD_ASYNC)) | |
886 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
887 | ||
888 | return ret; | |
bdfbf092 EG |
889 | } |
890 | ||
59c647b6 EG |
891 | static inline struct iwl_device_cmd * |
892 | iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) | |
893 | { | |
894 | u8 *dev_cmd_ptr = kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC); | |
895 | ||
896 | if (unlikely(dev_cmd_ptr == NULL)) | |
897 | return NULL; | |
898 | ||
899 | return (struct iwl_device_cmd *) | |
900 | (dev_cmd_ptr + trans->dev_cmd_headroom); | |
901 | } | |
902 | ||
903 | static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, | |
904 | struct iwl_device_cmd *dev_cmd) | |
905 | { | |
906 | u8 *dev_cmd_ptr = (u8 *)dev_cmd - trans->dev_cmd_headroom; | |
907 | ||
908 | kmem_cache_free(trans->dev_cmd_pool, dev_cmd_ptr); | |
909 | } | |
910 | ||
e6bb4c9c | 911 | static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa | 912 | struct iwl_device_cmd *dev_cmd, int queue) |
a0eaad71 | 913 | { |
3fc07953 AN |
914 | if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) |
915 | return -EIO; | |
916 | ||
f39a52bf | 917 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
3c6acb61 | 918 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
69655ebf | 919 | |
9eae88fa | 920 | return trans->ops->tx(trans, skb, dev_cmd, queue); |
a0eaad71 EG |
921 | } |
922 | ||
9eae88fa JB |
923 | static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, |
924 | int ssn, struct sk_buff_head *skbs) | |
48d42c42 | 925 | { |
f39a52bf | 926 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
3c6acb61 | 927 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
69655ebf | 928 | |
9eae88fa | 929 | trans->ops->reclaim(trans, queue, ssn, skbs); |
48d42c42 EG |
930 | } |
931 | ||
d4578ea8 JB |
932 | static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, |
933 | bool configure_scd) | |
288712a6 | 934 | { |
d4578ea8 JB |
935 | trans->ops->txq_disable(trans, queue, configure_scd); |
936 | } | |
937 | ||
938 | static inline void | |
939 | iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, | |
4cf677fd EG |
940 | const struct iwl_trans_txq_scd_cfg *cfg, |
941 | unsigned int queue_wdg_timeout) | |
d4578ea8 JB |
942 | { |
943 | might_sleep(); | |
944 | ||
945 | if (unlikely((trans->state != IWL_TRANS_FW_ALIVE))) | |
946 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); | |
947 | ||
4cf677fd | 948 | trans->ops->txq_enable(trans, queue, ssn, cfg, queue_wdg_timeout); |
288712a6 EG |
949 | } |
950 | ||
4beaf6c2 EG |
951 | static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, |
952 | int fifo, int sta_id, int tid, | |
4cf677fd EG |
953 | int frame_limit, u16 ssn, |
954 | unsigned int queue_wdg_timeout) | |
48d42c42 | 955 | { |
fea7795f JB |
956 | struct iwl_trans_txq_scd_cfg cfg = { |
957 | .fifo = fifo, | |
958 | .sta_id = sta_id, | |
959 | .tid = tid, | |
960 | .frame_limit = frame_limit, | |
64ba8930 | 961 | .aggregate = sta_id >= 0, |
fea7795f JB |
962 | }; |
963 | ||
4cf677fd | 964 | iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); |
48d42c42 EG |
965 | } |
966 | ||
4cf677fd EG |
967 | static inline |
968 | void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, | |
969 | unsigned int queue_wdg_timeout) | |
b04db9ac | 970 | { |
d4578ea8 JB |
971 | struct iwl_trans_txq_scd_cfg cfg = { |
972 | .fifo = fifo, | |
973 | .sta_id = -1, | |
974 | .tid = IWL_MAX_TID_COUNT, | |
975 | .frame_limit = IWL_FRAME_LIMIT, | |
64ba8930 | 976 | .aggregate = false, |
d4578ea8 JB |
977 | }; |
978 | ||
4cf677fd | 979 | iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); |
d4578ea8 JB |
980 | } |
981 | ||
e0b8d405 EG |
982 | static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, |
983 | unsigned long txqs, | |
984 | bool freeze) | |
985 | { | |
986 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) | |
987 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); | |
988 | ||
989 | if (trans->ops->freeze_txq_timer) | |
990 | trans->ops->freeze_txq_timer(trans, txqs, freeze); | |
991 | } | |
992 | ||
3cafdbe6 | 993 | static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans, |
4cf677fd | 994 | u32 txqs) |
5f178cd2 | 995 | { |
f39a52bf | 996 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
3c6acb61 | 997 | IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); |
69655ebf | 998 | |
4cf677fd | 999 | return trans->ops->wait_tx_queue_empty(trans, txqs); |
5f178cd2 EG |
1000 | } |
1001 | ||
87e5666c | 1002 | static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans, |
4fd442db | 1003 | struct dentry *dir) |
87e5666c EG |
1004 | { |
1005 | return trans->ops->dbgfs_register(trans, dir); | |
1006 | } | |
1007 | ||
03905495 EG |
1008 | static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1009 | { | |
1010 | trans->ops->write8(trans, ofs, val); | |
1011 | } | |
1012 | ||
1013 | static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1014 | { | |
1015 | trans->ops->write32(trans, ofs, val); | |
1016 | } | |
1017 | ||
1018 | static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) | |
1019 | { | |
1020 | return trans->ops->read32(trans, ofs); | |
1021 | } | |
1022 | ||
6a06b6c1 EG |
1023 | static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) |
1024 | { | |
1025 | return trans->ops->read_prph(trans, ofs); | |
1026 | } | |
1027 | ||
1028 | static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, | |
1029 | u32 val) | |
1030 | { | |
1031 | return trans->ops->write_prph(trans, ofs, val); | |
1032 | } | |
1033 | ||
4fd442db EG |
1034 | static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, |
1035 | void *buf, int dwords) | |
1036 | { | |
1037 | return trans->ops->read_mem(trans, addr, buf, dwords); | |
1038 | } | |
1039 | ||
1040 | #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ | |
1041 | do { \ | |
1042 | if (__builtin_constant_p(bufsize)) \ | |
1043 | BUILD_BUG_ON((bufsize) % sizeof(u32)); \ | |
1044 | iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ | |
1045 | } while (0) | |
1046 | ||
1047 | static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) | |
1048 | { | |
1049 | u32 value; | |
1050 | ||
1051 | if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) | |
1052 | return 0xa5a5a5a5; | |
1053 | ||
1054 | return value; | |
1055 | } | |
1056 | ||
1057 | static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1058 | const void *buf, int dwords) |
4fd442db EG |
1059 | { |
1060 | return trans->ops->write_mem(trans, addr, buf, dwords); | |
1061 | } | |
1062 | ||
1063 | static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, | |
1064 | u32 val) | |
1065 | { | |
1066 | return iwl_trans_write_mem(trans, addr, &val, 1); | |
1067 | } | |
1068 | ||
47107e84 DF |
1069 | static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) |
1070 | { | |
128cb89e AN |
1071 | if (trans->ops->set_pmi) |
1072 | trans->ops->set_pmi(trans, state); | |
47107e84 DF |
1073 | } |
1074 | ||
e139dc4a LE |
1075 | static inline void |
1076 | iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) | |
1077 | { | |
1078 | trans->ops->set_bits_mask(trans, reg, mask, value); | |
1079 | } | |
1080 | ||
e56b04ef | 1081 | #define iwl_trans_grab_nic_access(trans, silent, flags) \ |
abae2386 | 1082 | __cond_lock(nic_access, \ |
e56b04ef | 1083 | likely((trans)->ops->grab_nic_access(trans, silent, flags))) |
7a65d170 | 1084 | |
abae2386 | 1085 | static inline void __releases(nic_access) |
e56b04ef | 1086 | iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) |
7a65d170 | 1087 | { |
e56b04ef | 1088 | trans->ops->release_nic_access(trans, flags); |
abae2386 | 1089 | __release(nic_access); |
7a65d170 EG |
1090 | } |
1091 | ||
2a988e98 AN |
1092 | static inline void iwl_trans_fw_error(struct iwl_trans *trans) |
1093 | { | |
1094 | if (WARN_ON_ONCE(!trans->op_mode)) | |
1095 | return; | |
1096 | ||
1097 | /* prevent double restarts due to the same erroneous FW */ | |
1098 | if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) | |
1099 | iwl_op_mode_nic_error(trans->op_mode); | |
1100 | } | |
1101 | ||
7b501d10 JB |
1102 | /***************************************************** |
1103 | * transport helper functions | |
1104 | *****************************************************/ | |
1105 | struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, | |
1106 | struct device *dev, | |
1107 | const struct iwl_cfg *cfg, | |
1108 | const struct iwl_trans_ops *ops, | |
1109 | size_t dev_cmd_headroom); | |
1110 | void iwl_trans_free(struct iwl_trans *trans); | |
1111 | ||
b52e7ea1 | 1112 | /***************************************************** |
d1ff5253 | 1113 | * driver (transport) register/unregister functions |
b52e7ea1 | 1114 | ******************************************************/ |
36a79223 EG |
1115 | int __must_check iwl_pci_register_driver(void); |
1116 | void iwl_pci_unregister_driver(void); | |
b52e7ea1 | 1117 | |
41c50542 | 1118 | #endif /* __iwl_trans_h__ */ |