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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
c85eb619 EG |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
51368bf7 | 33 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
41c50542 EG |
63 | #ifndef __iwl_trans_h__ |
64 | #define __iwl_trans_h__ | |
253a634c | 65 | |
e679378d | 66 | #include <linux/ieee80211.h> |
930dfd5f | 67 | #include <linux/mm.h> /* for page_address */ |
2bfb5092 | 68 | #include <linux/lockdep.h> |
a72b8b08 | 69 | |
69655ebf | 70 | #include "iwl-debug.h" |
6238b008 JB |
71 | #include "iwl-config.h" |
72 | #include "iwl-fw.h" | |
2a988e98 | 73 | #include "iwl-op-mode.h" |
87e5666c | 74 | |
60396183 EG |
75 | /** |
76 | * DOC: Transport layer - what is it ? | |
77 | * | |
78 | * The tranport layer is the layer that deals with the HW directly. It provides | |
79 | * an abstraction of the underlying HW to the upper layer. The transport layer | |
80 | * doesn't provide any policy, algorithm or anything of this kind, but only | |
81 | * mechanisms to make the HW do something.It is not completely stateless but | |
82 | * close to it. | |
83 | * We will have an implementation for each different supported bus. | |
84 | */ | |
85 | ||
86 | /** | |
87 | * DOC: Life cycle of the transport layer | |
88 | * | |
89 | * The transport layer has a very precise life cycle. | |
90 | * | |
91 | * 1) A helper function is called during the module initialization and | |
92 | * registers the bus driver's ops with the transport's alloc function. | |
93 | * 2) Bus's probe calls to the transport layer's allocation functions. | |
94 | * Of course this function is bus specific. | |
95 | * 3) This allocation functions will spawn the upper layer which will | |
96 | * register mac80211. | |
97 | * | |
98 | * 4) At some point (i.e. mac80211's start call), the op_mode will call | |
99 | * the following sequence: | |
100 | * start_hw | |
101 | * start_fw | |
102 | * | |
103 | * 5) Then when finished (or reset): | |
a4082843 | 104 | * stop_device |
60396183 EG |
105 | * |
106 | * 6) Eventually, the free function will be called. | |
107 | */ | |
108 | ||
60396183 EG |
109 | /** |
110 | * DOC: Host command section | |
111 | * | |
112 | * A host command is a commaned issued by the upper layer to the fw. There are | |
113 | * several versions of fw that have several APIs. The transport layer is | |
114 | * completely agnostic to these differences. | |
115 | * The transport does provide helper functionnality (i.e. SYNC / ASYNC mode), | |
116 | */ | |
f8d7c1a1 JB |
117 | #define SEQ_TO_QUEUE(s) (((s) >> 8) & 0x1f) |
118 | #define QUEUE_TO_SEQ(q) (((q) & 0x1f) << 8) | |
119 | #define SEQ_TO_INDEX(s) ((s) & 0xff) | |
120 | #define INDEX_TO_SEQ(i) ((i) & 0xff) | |
121 | #define SEQ_RX_FRAME cpu_to_le16(0x8000) | |
122 | ||
123 | /** | |
124 | * struct iwl_cmd_header | |
125 | * | |
126 | * This header format appears in the beginning of each command sent from the | |
127 | * driver, and each response/notification received from uCode. | |
128 | */ | |
129 | struct iwl_cmd_header { | |
130 | u8 cmd; /* Command ID: REPLY_RXON, etc. */ | |
131 | u8 flags; /* 0:5 reserved, 6 abort, 7 internal */ | |
132 | /* | |
133 | * The driver sets up the sequence number to values of its choosing. | |
134 | * uCode does not use this value, but passes it back to the driver | |
135 | * when sending the response to each driver-originated command, so | |
136 | * the driver can match the response to the command. Since the values | |
137 | * don't get used by uCode, the driver may set up an arbitrary format. | |
138 | * | |
139 | * There is one exception: uCode sets bit 15 when it originates | |
140 | * the response/notification, i.e. when the response/notification | |
141 | * is not a direct response to a command sent by the driver. For | |
142 | * example, uCode issues REPLY_RX when it sends a received frame | |
143 | * to the driver; it is not a direct response to any driver command. | |
144 | * | |
145 | * The Linux driver uses the following format: | |
146 | * | |
147 | * 0:7 tfd index - position within TX queue | |
148 | * 8:12 TX queue id | |
149 | * 13:14 reserved | |
150 | * 15 unsolicited RX or uCode-originated notification | |
151 | */ | |
152 | __le16 sequence; | |
153 | } __packed; | |
154 | ||
c08ce20c JB |
155 | /* iwl_cmd_header flags value */ |
156 | #define IWL_CMD_FAILED_MSK 0x40 | |
157 | ||
f8d7c1a1 JB |
158 | |
159 | #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ | |
0c19744c JB |
160 | #define FH_RSCSR_FRAME_INVALID 0x55550000 |
161 | #define FH_RSCSR_FRAME_ALIGN 0x40 | |
f8d7c1a1 JB |
162 | |
163 | struct iwl_rx_packet { | |
164 | /* | |
165 | * The first 4 bytes of the RX frame header contain both the RX frame | |
166 | * size and some flags. | |
167 | * Bit fields: | |
168 | * 31: flag flush RB request | |
169 | * 30: flag ignore TC (terminal counter) request | |
170 | * 29: flag fast IRQ request | |
171 | * 28-14: Reserved | |
172 | * 13-00: RX frame size | |
173 | */ | |
174 | __le32 len_n_flags; | |
175 | struct iwl_cmd_header hdr; | |
176 | u8 data[]; | |
177 | } __packed; | |
522376d2 | 178 | |
65b30348 JB |
179 | static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) |
180 | { | |
181 | return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
182 | } | |
183 | ||
184 | static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) | |
185 | { | |
186 | return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); | |
187 | } | |
188 | ||
60396183 EG |
189 | /** |
190 | * enum CMD_MODE - how to send the host commands ? | |
191 | * | |
192 | * @CMD_SYNC: The caller will be stalled until the fw responds to the command | |
e89044d7 | 193 | * @CMD_ASYNC: Return right away and don't wait for the response |
60396183 | 194 | * @CMD_WANT_SKB: valid only with CMD_SYNC. The caller needs the buffer of the |
96791422 | 195 | * response. The caller needs to call iwl_free_resp when done. |
60396183 EG |
196 | */ |
197 | enum CMD_MODE { | |
4a4ee101 JB |
198 | CMD_SYNC = 0, |
199 | CMD_ASYNC = BIT(0), | |
200 | CMD_WANT_SKB = BIT(1), | |
4f59334b | 201 | CMD_SEND_IN_RFKILL = BIT(2), |
522376d2 EG |
202 | }; |
203 | ||
204 | #define DEF_CMD_PAYLOAD_SIZE 320 | |
205 | ||
206 | /** | |
207 | * struct iwl_device_cmd | |
208 | * | |
209 | * For allocation of the command and tx queues, this establishes the overall | |
210 | * size of the largest command we send to uCode, except for commands that | |
211 | * aren't fully copied and use other TFD space. | |
212 | */ | |
213 | struct iwl_device_cmd { | |
214 | struct iwl_cmd_header hdr; /* uCode API */ | |
132f98c2 | 215 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; |
522376d2 EG |
216 | } __packed; |
217 | ||
218 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) | |
219 | ||
1afbfb60 JB |
220 | /* |
221 | * number of transfer buffers (fragments) per transmit frame descriptor; | |
222 | * this is just the driver's idea, the hardware supports 20 | |
223 | */ | |
224 | #define IWL_MAX_CMD_TBS_PER_TFD 2 | |
522376d2 | 225 | |
60396183 EG |
226 | /** |
227 | * struct iwl_hcmd_dataflag - flag for each one of the chunks of the command | |
228 | * | |
f4feb8ac | 229 | * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's |
60396183 | 230 | * ring. The transport layer doesn't map the command's buffer to DMA, but |
e89044d7 | 231 | * rather copies it to a previously allocated DMA buffer. This flag tells |
60396183 | 232 | * the transport layer not to copy the command, but to map the existing |
3e2c1592 JB |
233 | * buffer (that is passed in) instead. This saves the memcpy and allows |
234 | * commands that are bigger than the fixed buffer to be submitted. | |
235 | * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. | |
f4feb8ac JB |
236 | * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this |
237 | * chunk internally and free it again after the command completes. This | |
238 | * can (currently) be used only once per command. | |
3e2c1592 | 239 | * Note that a TFD entry after a DUP one cannot be a normal copied one. |
60396183 | 240 | */ |
522376d2 EG |
241 | enum iwl_hcmd_dataflag { |
242 | IWL_HCMD_DFL_NOCOPY = BIT(0), | |
f4feb8ac | 243 | IWL_HCMD_DFL_DUP = BIT(1), |
522376d2 EG |
244 | }; |
245 | ||
246 | /** | |
247 | * struct iwl_host_cmd - Host command to the uCode | |
60396183 | 248 | * |
522376d2 | 249 | * @data: array of chunks that composes the data of the host command |
65b94a4a JB |
250 | * @resp_pkt: response packet, if %CMD_WANT_SKB was set |
251 | * @_rx_page_order: (internally used to free response packet) | |
252 | * @_rx_page_addr: (internally used to free response packet) | |
247c61d6 EG |
253 | * @handler_status: return value of the handler of the command |
254 | * (put in setup_rx_handlers) - valid for SYNC mode only | |
60396183 | 255 | * @flags: can be CMD_* |
e89044d7 | 256 | * @len: array of the lengths of the chunks in data |
60396183 | 257 | * @dataflags: IWL_HCMD_DFL_* |
522376d2 EG |
258 | * @id: id of the host command |
259 | */ | |
260 | struct iwl_host_cmd { | |
1afbfb60 | 261 | const void *data[IWL_MAX_CMD_TBS_PER_TFD]; |
65b94a4a JB |
262 | struct iwl_rx_packet *resp_pkt; |
263 | unsigned long _rx_page_addr; | |
264 | u32 _rx_page_order; | |
247c61d6 EG |
265 | int handler_status; |
266 | ||
522376d2 | 267 | u32 flags; |
1afbfb60 JB |
268 | u16 len[IWL_MAX_CMD_TBS_PER_TFD]; |
269 | u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; | |
522376d2 EG |
270 | u8 id; |
271 | }; | |
41c50542 | 272 | |
65b94a4a JB |
273 | static inline void iwl_free_resp(struct iwl_host_cmd *cmd) |
274 | { | |
275 | free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); | |
276 | } | |
277 | ||
930dfd5f JB |
278 | struct iwl_rx_cmd_buffer { |
279 | struct page *_page; | |
0c19744c JB |
280 | int _offset; |
281 | bool _page_stolen; | |
d13f1862 | 282 | u32 _rx_page_order; |
ed90542b | 283 | unsigned int truesize; |
930dfd5f JB |
284 | }; |
285 | ||
286 | static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) | |
287 | { | |
0c19744c JB |
288 | return (void *)((unsigned long)page_address(r->_page) + r->_offset); |
289 | } | |
290 | ||
291 | static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) | |
292 | { | |
293 | return r->_offset; | |
930dfd5f JB |
294 | } |
295 | ||
296 | static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) | |
297 | { | |
0c19744c JB |
298 | r->_page_stolen = true; |
299 | get_page(r->_page); | |
300 | return r->_page; | |
930dfd5f JB |
301 | } |
302 | ||
d13f1862 EG |
303 | static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) |
304 | { | |
305 | __free_pages(r->_page, r->_rx_page_order); | |
306 | } | |
307 | ||
d663ee73 JB |
308 | #define MAX_NO_RECLAIM_CMDS 6 |
309 | ||
ff110c8f GG |
310 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
311 | ||
9eae88fa JB |
312 | /* |
313 | * Maximum number of HW queues the transport layer | |
314 | * currently supports | |
315 | */ | |
316 | #define IWL_MAX_HW_QUEUES 32 | |
b04db9ac EG |
317 | #define IWL_MAX_TID_COUNT 8 |
318 | #define IWL_FRAME_LIMIT 64 | |
9eae88fa | 319 | |
ddaf5a5b JB |
320 | /** |
321 | * enum iwl_wowlan_status - WoWLAN image/device status | |
322 | * @IWL_D3_STATUS_ALIVE: firmware is still running after resume | |
323 | * @IWL_D3_STATUS_RESET: device was reset while suspended | |
324 | */ | |
325 | enum iwl_d3_status { | |
326 | IWL_D3_STATUS_ALIVE, | |
327 | IWL_D3_STATUS_RESET, | |
328 | }; | |
329 | ||
eb7ff77e AN |
330 | /** |
331 | * enum iwl_trans_status: transport status flags | |
332 | * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed | |
333 | * @STATUS_DEVICE_ENABLED: APM is enabled | |
334 | * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) | |
335 | * @STATUS_INT_ENABLED: interrupts are enabled | |
336 | * @STATUS_RFKILL: the HW RFkill switch is in KILL position | |
337 | * @STATUS_FW_ERROR: the fw is in error state | |
338 | */ | |
339 | enum iwl_trans_status { | |
340 | STATUS_SYNC_HCMD_ACTIVE, | |
341 | STATUS_DEVICE_ENABLED, | |
342 | STATUS_TPOWER_PMI, | |
343 | STATUS_INT_ENABLED, | |
344 | STATUS_RFKILL, | |
345 | STATUS_FW_ERROR, | |
346 | }; | |
347 | ||
92d743ae MV |
348 | /** |
349 | * struct iwl_trans_config - transport configuration | |
350 | * | |
351 | * @op_mode: pointer to the upper layer. | |
c6f600fc MV |
352 | * @cmd_queue: the index of the command queue. |
353 | * Must be set before start_fw. | |
b04db9ac | 354 | * @cmd_fifo: the fifo for host commands |
d663ee73 JB |
355 | * @no_reclaim_cmds: Some devices erroneously don't set the |
356 | * SEQ_RX_FRAME bit on some notifications, this is the | |
357 | * list of such notifications to filter. Max length is | |
358 | * %MAX_NO_RECLAIM_CMDS. | |
359 | * @n_no_reclaim_cmds: # of commands in list | |
b2cf410c JB |
360 | * @rx_buf_size_8k: 8 kB RX buffer size needed for A-MSDUs, |
361 | * if unset 4k will be the RX buffer size | |
046db346 EG |
362 | * @bc_table_dword: set to true if the BC table expects the byte count to be |
363 | * in DWORD (as opposed to bytes) | |
7c5ba4a8 JB |
364 | * @queue_watchdog_timeout: time (in ms) after which queues |
365 | * are considered stuck and will trigger device restart | |
d9fb6465 JB |
366 | * @command_names: array of command names, must be 256 entries |
367 | * (one for each command); for debugging only | |
92d743ae MV |
368 | */ |
369 | struct iwl_trans_config { | |
370 | struct iwl_op_mode *op_mode; | |
9eae88fa | 371 | |
c6f600fc | 372 | u8 cmd_queue; |
b04db9ac | 373 | u8 cmd_fifo; |
d663ee73 | 374 | const u8 *no_reclaim_cmds; |
84cf0e62 | 375 | unsigned int n_no_reclaim_cmds; |
b2cf410c JB |
376 | |
377 | bool rx_buf_size_8k; | |
046db346 | 378 | bool bc_table_dword; |
7c5ba4a8 | 379 | unsigned int queue_watchdog_timeout; |
d9fb6465 | 380 | const char **command_names; |
92d743ae MV |
381 | }; |
382 | ||
87ce05a2 EG |
383 | struct iwl_trans; |
384 | ||
41c50542 EG |
385 | /** |
386 | * struct iwl_trans_ops - transport specific operations | |
60396183 EG |
387 | * |
388 | * All the handlers MUST be implemented | |
389 | * | |
57a1dc89 | 390 | * @start_hw: starts the HW- from that point on, the HW can send interrupts |
60396183 | 391 | * May sleep |
a4082843 | 392 | * @op_mode_leave: Turn off the HW RF kill indication if on |
60396183 | 393 | * May sleep |
cf614297 | 394 | * @start_fw: allocates and inits all the resources for the transport |
60396183 EG |
395 | * layer. Also kick a fw image. |
396 | * May sleep | |
adca1235 EG |
397 | * @fw_alive: called when the fw sends alive notification. If the fw provides |
398 | * the SCD base address in SRAM, then provide it here, or 0 otherwise. | |
60396183 | 399 | * May sleep |
a4082843 AN |
400 | * @stop_device: stops the whole device (embedded CPU put to reset) and stops |
401 | * the HW. From that point on, the HW will be in low power but will still | |
402 | * issue interrupt if the HW RF kill is triggered. This callback must do | |
403 | * the right thing and not crash even if start_hw() was called but not | |
404 | * start_fw(). May sleep | |
ddaf5a5b | 405 | * @d3_suspend: put the device into the correct mode for WoWLAN during |
2dd4f9f7 JB |
406 | * suspend. This is optional, if not implemented WoWLAN will not be |
407 | * supported. This callback may sleep. | |
ddaf5a5b JB |
408 | * @d3_resume: resume the device after WoWLAN, enabling the opmode to |
409 | * talk to the WoWLAN image to get its status. This is optional, if not | |
410 | * implemented WoWLAN will not be supported. This callback may sleep. | |
f946b529 EG |
411 | * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. |
412 | * If RFkill is asserted in the middle of a SYNC host command, it must | |
413 | * return -ERFKILL straight away. | |
60396183 | 414 | * May sleep only if CMD_SYNC is set |
41c50542 | 415 | * @tx: send an skb |
60396183 | 416 | * Must be atomic |
a0eaad71 | 417 | * @reclaim: free packet until ssn. Returns a list of freed packets. |
60396183 | 418 | * Must be atomic |
b04db9ac EG |
419 | * @txq_enable: setup a queue. To setup an AC queue, use the |
420 | * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before | |
421 | * this one. The op_mode must not configure the HCMD queue. May sleep. | |
d0624be6 | 422 | * @txq_disable: de-configure a Tx queue to send AMPDUs |
b0b46192 | 423 | * Must be atomic |
5f178cd2 | 424 | * @wait_tx_queue_empty: wait until all tx queues are empty |
60396183 | 425 | * May sleep |
87e5666c EG |
426 | * @dbgfs_register: add the dbgfs files under this directory. Files will be |
427 | * automatically deleted. | |
03905495 EG |
428 | * @write8: write a u8 to a register at offset ofs from the BAR |
429 | * @write32: write a u32 to a register at offset ofs from the BAR | |
430 | * @read32: read a u32 register at offset ofs from the BAR | |
6a06b6c1 EG |
431 | * @read_prph: read a DWORD from a periphery register |
432 | * @write_prph: write a DWORD to a periphery register | |
4fd442db | 433 | * @read_mem: read device's SRAM in DWORD |
01387ffd EG |
434 | * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory |
435 | * will be zeroed. | |
c6f600fc | 436 | * @configure: configure parameters required by the transport layer from |
3dc420be EG |
437 | * the op_mode. May be called several times before start_fw, can't be |
438 | * called after that. | |
47107e84 | 439 | * @set_pmi: set the power pmi state |
e56b04ef LE |
440 | * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. |
441 | * Sleeping is not allowed between grab_nic_access and | |
442 | * release_nic_access. | |
443 | * @release_nic_access: let the NIC go to sleep. The "flags" parameter | |
444 | * must be the same one that was sent before to the grab_nic_access. | |
e139dc4a | 445 | * @set_bits_mask - set SRAM register according to value and mask. |
41c50542 EG |
446 | */ |
447 | struct iwl_trans_ops { | |
448 | ||
57a1dc89 | 449 | int (*start_hw)(struct iwl_trans *iwl_trans); |
a4082843 | 450 | void (*op_mode_leave)(struct iwl_trans *iwl_trans); |
6ae02f3e EG |
451 | int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, |
452 | bool run_in_rfkill); | |
adca1235 | 453 | void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); |
6d8f6eeb | 454 | void (*stop_device)(struct iwl_trans *trans); |
41c50542 | 455 | |
debff618 JB |
456 | void (*d3_suspend)(struct iwl_trans *trans, bool test); |
457 | int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, | |
458 | bool test); | |
2dd4f9f7 | 459 | |
6d8f6eeb | 460 | int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
41c50542 | 461 | |
e13c0c59 | 462 | int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa JB |
463 | struct iwl_device_cmd *dev_cmd, int queue); |
464 | void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, | |
465 | struct sk_buff_head *skbs); | |
466 | ||
4beaf6c2 EG |
467 | void (*txq_enable)(struct iwl_trans *trans, int queue, int fifo, |
468 | int sta_id, int tid, int frame_limit, u16 ssn); | |
d0624be6 | 469 | void (*txq_disable)(struct iwl_trans *trans, int queue); |
41c50542 | 470 | |
87e5666c | 471 | int (*dbgfs_register)(struct iwl_trans *trans, struct dentry* dir); |
5f178cd2 | 472 | int (*wait_tx_queue_empty)(struct iwl_trans *trans); |
5fdda047 | 473 | |
03905495 EG |
474 | void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); |
475 | void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); | |
476 | u32 (*read32)(struct iwl_trans *trans, u32 ofs); | |
6a06b6c1 EG |
477 | u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); |
478 | void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); | |
4fd442db EG |
479 | int (*read_mem)(struct iwl_trans *trans, u32 addr, |
480 | void *buf, int dwords); | |
481 | int (*write_mem)(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 482 | const void *buf, int dwords); |
c6f600fc MV |
483 | void (*configure)(struct iwl_trans *trans, |
484 | const struct iwl_trans_config *trans_cfg); | |
47107e84 | 485 | void (*set_pmi)(struct iwl_trans *trans, bool state); |
e56b04ef LE |
486 | bool (*grab_nic_access)(struct iwl_trans *trans, bool silent, |
487 | unsigned long *flags); | |
488 | void (*release_nic_access)(struct iwl_trans *trans, | |
489 | unsigned long *flags); | |
e139dc4a LE |
490 | void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, |
491 | u32 value); | |
41c50542 EG |
492 | }; |
493 | ||
69655ebf EG |
494 | /** |
495 | * enum iwl_trans_state - state of the transport layer | |
496 | * | |
497 | * @IWL_TRANS_NO_FW: no fw has sent an alive response | |
498 | * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response | |
499 | */ | |
500 | enum iwl_trans_state { | |
501 | IWL_TRANS_NO_FW = 0, | |
502 | IWL_TRANS_FW_ALIVE = 1, | |
503 | }; | |
504 | ||
6fbfae8e EG |
505 | /** |
506 | * struct iwl_trans - transport common data | |
60396183 | 507 | * |
6fbfae8e | 508 | * @ops - pointer to iwl_trans_ops |
ed277c93 | 509 | * @op_mode - pointer to the op_mode |
035f7ff2 | 510 | * @cfg - pointer to the configuration |
eb7ff77e | 511 | * @status: a bit-mask of transport status flags |
a42a1844 | 512 | * @dev - pointer to struct device * that represents the device |
99673ee5 | 513 | * @hw_id: a u32 with the ID of the device / subdevice. |
60396183 | 514 | * Set during transport allocation. |
9ca85961 | 515 | * @hw_id_str: a string with info about HW ID. Set during transport allocation. |
f6d0e9be | 516 | * @pm_support: set to true in start_hw if link pm is supported |
59c647b6 EG |
517 | * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. |
518 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
519 | * @dev_cmd_headroom: room needed for the transport's private use before the | |
520 | * device_cmd for Tx - for internal use only | |
521 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
f042c2eb JB |
522 | * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before |
523 | * starting the firmware, used for tracing | |
524 | * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the | |
525 | * start of the 802.11 header in the @rx_mpdu_cmd | |
6fbfae8e | 526 | */ |
41c50542 EG |
527 | struct iwl_trans { |
528 | const struct iwl_trans_ops *ops; | |
ed277c93 | 529 | struct iwl_op_mode *op_mode; |
035f7ff2 | 530 | const struct iwl_cfg *cfg; |
69655ebf | 531 | enum iwl_trans_state state; |
eb7ff77e | 532 | unsigned long status; |
e6bb4c9c | 533 | |
a42a1844 | 534 | struct device *dev; |
08079a49 | 535 | u32 hw_rev; |
99673ee5 | 536 | u32 hw_id; |
9ca85961 | 537 | char hw_id_str[52]; |
a42a1844 | 538 | |
f042c2eb JB |
539 | u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; |
540 | ||
f6d0e9be | 541 | bool pm_support; |
97b52cfd | 542 | |
59c647b6 EG |
543 | /* The following fields are internal only */ |
544 | struct kmem_cache *dev_cmd_pool; | |
545 | size_t dev_cmd_headroom; | |
3ec45882 | 546 | char dev_cmd_pool_name[50]; |
59c647b6 | 547 | |
9da987ac MV |
548 | struct dentry *dbgfs_dir; |
549 | ||
2bfb5092 JB |
550 | #ifdef CONFIG_LOCKDEP |
551 | struct lockdep_map sync_cmd_lockdep_map; | |
552 | #endif | |
553 | ||
e6bb4c9c EG |
554 | /* pointer to trans specific struct */ |
555 | /*Ensure that this pointer will always be aligned to sizeof pointer */ | |
cbe6ab4e | 556 | char trans_specific[0] __aligned(sizeof(void *)); |
41c50542 EG |
557 | }; |
558 | ||
ed277c93 | 559 | static inline void iwl_trans_configure(struct iwl_trans *trans, |
92d743ae | 560 | const struct iwl_trans_config *trans_cfg) |
ed277c93 | 561 | { |
92d743ae | 562 | trans->op_mode = trans_cfg->op_mode; |
c6f600fc MV |
563 | |
564 | trans->ops->configure(trans, trans_cfg); | |
ed277c93 EG |
565 | } |
566 | ||
57a1dc89 | 567 | static inline int iwl_trans_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 568 | { |
60396183 EG |
569 | might_sleep(); |
570 | ||
57a1dc89 | 571 | return trans->ops->start_hw(trans); |
e6bb4c9c EG |
572 | } |
573 | ||
a4082843 | 574 | static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 575 | { |
60396183 EG |
576 | might_sleep(); |
577 | ||
a4082843 AN |
578 | if (trans->ops->op_mode_leave) |
579 | trans->ops->op_mode_leave(trans); | |
69655ebf | 580 | |
a4082843 | 581 | trans->op_mode = NULL; |
b4991f3f | 582 | |
69655ebf | 583 | trans->state = IWL_TRANS_NO_FW; |
cc56feb2 EG |
584 | } |
585 | ||
adca1235 | 586 | static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 587 | { |
60396183 EG |
588 | might_sleep(); |
589 | ||
69655ebf | 590 | trans->state = IWL_TRANS_FW_ALIVE; |
b04db9ac | 591 | |
adca1235 | 592 | trans->ops->fw_alive(trans, scd_addr); |
ed6a3803 EG |
593 | } |
594 | ||
0692fe41 | 595 | static inline int iwl_trans_start_fw(struct iwl_trans *trans, |
6ae02f3e EG |
596 | const struct fw_img *fw, |
597 | bool run_in_rfkill) | |
bdfbf092 | 598 | { |
cf614297 EG |
599 | might_sleep(); |
600 | ||
f042c2eb JB |
601 | WARN_ON_ONCE(!trans->rx_mpdu_cmd); |
602 | ||
efbf6e3b | 603 | clear_bit(STATUS_FW_ERROR, &trans->status); |
6ae02f3e | 604 | return trans->ops->start_fw(trans, fw, run_in_rfkill); |
bdfbf092 EG |
605 | } |
606 | ||
e6bb4c9c | 607 | static inline void iwl_trans_stop_device(struct iwl_trans *trans) |
bdfbf092 | 608 | { |
60396183 EG |
609 | might_sleep(); |
610 | ||
6d8f6eeb | 611 | trans->ops->stop_device(trans); |
69655ebf EG |
612 | |
613 | trans->state = IWL_TRANS_NO_FW; | |
bdfbf092 EG |
614 | } |
615 | ||
debff618 | 616 | static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test) |
ddaf5a5b JB |
617 | { |
618 | might_sleep(); | |
debff618 | 619 | trans->ops->d3_suspend(trans, test); |
ddaf5a5b JB |
620 | } |
621 | ||
622 | static inline int iwl_trans_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
623 | enum iwl_d3_status *status, |
624 | bool test) | |
2dd4f9f7 JB |
625 | { |
626 | might_sleep(); | |
debff618 | 627 | return trans->ops->d3_resume(trans, status, test); |
2dd4f9f7 JB |
628 | } |
629 | ||
e6bb4c9c | 630 | static inline int iwl_trans_send_cmd(struct iwl_trans *trans, |
2bfb5092 | 631 | struct iwl_host_cmd *cmd) |
bdfbf092 | 632 | { |
2bfb5092 JB |
633 | int ret; |
634 | ||
fba1c627 EG |
635 | if (unlikely(!(cmd->flags & CMD_SEND_IN_RFKILL) && |
636 | test_bit(STATUS_RFKILL, &trans->status))) | |
637 | return -ERFKILL; | |
638 | ||
3fc07953 AN |
639 | if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) |
640 | return -EIO; | |
641 | ||
f39a52bf | 642 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) { |
8ca95995 EG |
643 | IWL_ERR(trans, "%s bad state = %d", __func__, trans->state); |
644 | return -EIO; | |
645 | } | |
69655ebf | 646 | |
2bfb5092 JB |
647 | if (!(cmd->flags & CMD_ASYNC)) |
648 | lock_map_acquire_read(&trans->sync_cmd_lockdep_map); | |
649 | ||
650 | ret = trans->ops->send_cmd(trans, cmd); | |
651 | ||
652 | if (!(cmd->flags & CMD_ASYNC)) | |
653 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
654 | ||
655 | return ret; | |
bdfbf092 EG |
656 | } |
657 | ||
59c647b6 EG |
658 | static inline struct iwl_device_cmd * |
659 | iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) | |
660 | { | |
661 | u8 *dev_cmd_ptr = kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC); | |
662 | ||
663 | if (unlikely(dev_cmd_ptr == NULL)) | |
664 | return NULL; | |
665 | ||
666 | return (struct iwl_device_cmd *) | |
667 | (dev_cmd_ptr + trans->dev_cmd_headroom); | |
668 | } | |
669 | ||
670 | static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, | |
671 | struct iwl_device_cmd *dev_cmd) | |
672 | { | |
673 | u8 *dev_cmd_ptr = (u8 *)dev_cmd - trans->dev_cmd_headroom; | |
674 | ||
675 | kmem_cache_free(trans->dev_cmd_pool, dev_cmd_ptr); | |
676 | } | |
677 | ||
e6bb4c9c | 678 | static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa | 679 | struct iwl_device_cmd *dev_cmd, int queue) |
a0eaad71 | 680 | { |
3fc07953 AN |
681 | if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) |
682 | return -EIO; | |
683 | ||
f39a52bf SG |
684 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
685 | IWL_ERR(trans, "%s bad state = %d", __func__, trans->state); | |
69655ebf | 686 | |
9eae88fa | 687 | return trans->ops->tx(trans, skb, dev_cmd, queue); |
a0eaad71 EG |
688 | } |
689 | ||
9eae88fa JB |
690 | static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, |
691 | int ssn, struct sk_buff_head *skbs) | |
48d42c42 | 692 | { |
f39a52bf SG |
693 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
694 | IWL_ERR(trans, "%s bad state = %d", __func__, trans->state); | |
69655ebf | 695 | |
9eae88fa | 696 | trans->ops->reclaim(trans, queue, ssn, skbs); |
48d42c42 EG |
697 | } |
698 | ||
d0624be6 | 699 | static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue) |
288712a6 | 700 | { |
d0624be6 | 701 | trans->ops->txq_disable(trans, queue); |
288712a6 EG |
702 | } |
703 | ||
4beaf6c2 EG |
704 | static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, |
705 | int fifo, int sta_id, int tid, | |
706 | int frame_limit, u16 ssn) | |
48d42c42 | 707 | { |
60396183 EG |
708 | might_sleep(); |
709 | ||
f39a52bf SG |
710 | if (unlikely((trans->state != IWL_TRANS_FW_ALIVE))) |
711 | IWL_ERR(trans, "%s bad state = %d", __func__, trans->state); | |
69655ebf | 712 | |
4beaf6c2 | 713 | trans->ops->txq_enable(trans, queue, fifo, sta_id, tid, |
9eae88fa | 714 | frame_limit, ssn); |
48d42c42 EG |
715 | } |
716 | ||
b04db9ac EG |
717 | static inline void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, |
718 | int fifo) | |
719 | { | |
881acd89 | 720 | iwl_trans_txq_enable(trans, queue, fifo, -1, |
b04db9ac EG |
721 | IWL_MAX_TID_COUNT, IWL_FRAME_LIMIT, 0); |
722 | } | |
723 | ||
5f178cd2 EG |
724 | static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans) |
725 | { | |
f39a52bf SG |
726 | if (unlikely(trans->state != IWL_TRANS_FW_ALIVE)) |
727 | IWL_ERR(trans, "%s bad state = %d", __func__, trans->state); | |
69655ebf | 728 | |
5f178cd2 EG |
729 | return trans->ops->wait_tx_queue_empty(trans); |
730 | } | |
731 | ||
87e5666c | 732 | static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans, |
4fd442db | 733 | struct dentry *dir) |
87e5666c EG |
734 | { |
735 | return trans->ops->dbgfs_register(trans, dir); | |
736 | } | |
737 | ||
03905495 EG |
738 | static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
739 | { | |
740 | trans->ops->write8(trans, ofs, val); | |
741 | } | |
742 | ||
743 | static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
744 | { | |
745 | trans->ops->write32(trans, ofs, val); | |
746 | } | |
747 | ||
748 | static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) | |
749 | { | |
750 | return trans->ops->read32(trans, ofs); | |
751 | } | |
752 | ||
6a06b6c1 EG |
753 | static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) |
754 | { | |
755 | return trans->ops->read_prph(trans, ofs); | |
756 | } | |
757 | ||
758 | static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, | |
759 | u32 val) | |
760 | { | |
761 | return trans->ops->write_prph(trans, ofs, val); | |
762 | } | |
763 | ||
4fd442db EG |
764 | static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, |
765 | void *buf, int dwords) | |
766 | { | |
767 | return trans->ops->read_mem(trans, addr, buf, dwords); | |
768 | } | |
769 | ||
770 | #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ | |
771 | do { \ | |
772 | if (__builtin_constant_p(bufsize)) \ | |
773 | BUILD_BUG_ON((bufsize) % sizeof(u32)); \ | |
774 | iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ | |
775 | } while (0) | |
776 | ||
777 | static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) | |
778 | { | |
779 | u32 value; | |
780 | ||
781 | if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) | |
782 | return 0xa5a5a5a5; | |
783 | ||
784 | return value; | |
785 | } | |
786 | ||
787 | static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 788 | const void *buf, int dwords) |
4fd442db EG |
789 | { |
790 | return trans->ops->write_mem(trans, addr, buf, dwords); | |
791 | } | |
792 | ||
793 | static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, | |
794 | u32 val) | |
795 | { | |
796 | return iwl_trans_write_mem(trans, addr, &val, 1); | |
797 | } | |
798 | ||
47107e84 DF |
799 | static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) |
800 | { | |
128cb89e AN |
801 | if (trans->ops->set_pmi) |
802 | trans->ops->set_pmi(trans, state); | |
47107e84 DF |
803 | } |
804 | ||
e139dc4a LE |
805 | static inline void |
806 | iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) | |
807 | { | |
808 | trans->ops->set_bits_mask(trans, reg, mask, value); | |
809 | } | |
810 | ||
e56b04ef | 811 | #define iwl_trans_grab_nic_access(trans, silent, flags) \ |
abae2386 | 812 | __cond_lock(nic_access, \ |
e56b04ef | 813 | likely((trans)->ops->grab_nic_access(trans, silent, flags))) |
7a65d170 | 814 | |
abae2386 | 815 | static inline void __releases(nic_access) |
e56b04ef | 816 | iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) |
7a65d170 | 817 | { |
e56b04ef | 818 | trans->ops->release_nic_access(trans, flags); |
abae2386 | 819 | __release(nic_access); |
7a65d170 EG |
820 | } |
821 | ||
2a988e98 AN |
822 | static inline void iwl_trans_fw_error(struct iwl_trans *trans) |
823 | { | |
824 | if (WARN_ON_ONCE(!trans->op_mode)) | |
825 | return; | |
826 | ||
827 | /* prevent double restarts due to the same erroneous FW */ | |
828 | if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) | |
829 | iwl_op_mode_nic_error(trans->op_mode); | |
830 | } | |
831 | ||
b52e7ea1 | 832 | /***************************************************** |
d1ff5253 | 833 | * driver (transport) register/unregister functions |
b52e7ea1 | 834 | ******************************************************/ |
36a79223 EG |
835 | int __must_check iwl_pci_register_driver(void); |
836 | void iwl_pci_unregister_driver(void); | |
b52e7ea1 | 837 | |
2bfb5092 JB |
838 | static inline void trans_lockdep_init(struct iwl_trans *trans) |
839 | { | |
840 | #ifdef CONFIG_LOCKDEP | |
841 | static struct lock_class_key __key; | |
842 | ||
843 | lockdep_init_map(&trans->sync_cmd_lockdep_map, "sync_cmd_lockdep_map", | |
844 | &__key, 0); | |
845 | #endif | |
846 | } | |
847 | ||
41c50542 | 848 | #endif /* __iwl_trans_h__ */ |