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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
128e63ef | 8 | * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
c85eb619 EG |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
128e63ef | 33 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
41c50542 EG |
63 | #ifndef __iwl_trans_h__ |
64 | #define __iwl_trans_h__ | |
253a634c | 65 | |
e679378d | 66 | #include <linux/ieee80211.h> |
930dfd5f | 67 | #include <linux/mm.h> /* for page_address */ |
2bfb5092 | 68 | #include <linux/lockdep.h> |
a72b8b08 | 69 | |
69655ebf | 70 | #include "iwl-debug.h" |
6238b008 JB |
71 | #include "iwl-config.h" |
72 | #include "iwl-fw.h" | |
87e5666c | 73 | |
60396183 EG |
74 | /** |
75 | * DOC: Transport layer - what is it ? | |
76 | * | |
77 | * The tranport layer is the layer that deals with the HW directly. It provides | |
78 | * an abstraction of the underlying HW to the upper layer. The transport layer | |
79 | * doesn't provide any policy, algorithm or anything of this kind, but only | |
80 | * mechanisms to make the HW do something.It is not completely stateless but | |
81 | * close to it. | |
82 | * We will have an implementation for each different supported bus. | |
83 | */ | |
84 | ||
85 | /** | |
86 | * DOC: Life cycle of the transport layer | |
87 | * | |
88 | * The transport layer has a very precise life cycle. | |
89 | * | |
90 | * 1) A helper function is called during the module initialization and | |
91 | * registers the bus driver's ops with the transport's alloc function. | |
92 | * 2) Bus's probe calls to the transport layer's allocation functions. | |
93 | * Of course this function is bus specific. | |
94 | * 3) This allocation functions will spawn the upper layer which will | |
95 | * register mac80211. | |
96 | * | |
97 | * 4) At some point (i.e. mac80211's start call), the op_mode will call | |
98 | * the following sequence: | |
99 | * start_hw | |
100 | * start_fw | |
101 | * | |
102 | * 5) Then when finished (or reset): | |
103 | * stop_fw (a.k.a. stop device for the moment) | |
104 | * stop_hw | |
105 | * | |
106 | * 6) Eventually, the free function will be called. | |
107 | */ | |
108 | ||
60396183 EG |
109 | /** |
110 | * DOC: Host command section | |
111 | * | |
112 | * A host command is a commaned issued by the upper layer to the fw. There are | |
113 | * several versions of fw that have several APIs. The transport layer is | |
114 | * completely agnostic to these differences. | |
115 | * The transport does provide helper functionnality (i.e. SYNC / ASYNC mode), | |
116 | */ | |
f8d7c1a1 JB |
117 | #define SEQ_TO_QUEUE(s) (((s) >> 8) & 0x1f) |
118 | #define QUEUE_TO_SEQ(q) (((q) & 0x1f) << 8) | |
119 | #define SEQ_TO_INDEX(s) ((s) & 0xff) | |
120 | #define INDEX_TO_SEQ(i) ((i) & 0xff) | |
121 | #define SEQ_RX_FRAME cpu_to_le16(0x8000) | |
122 | ||
123 | /** | |
124 | * struct iwl_cmd_header | |
125 | * | |
126 | * This header format appears in the beginning of each command sent from the | |
127 | * driver, and each response/notification received from uCode. | |
128 | */ | |
129 | struct iwl_cmd_header { | |
130 | u8 cmd; /* Command ID: REPLY_RXON, etc. */ | |
131 | u8 flags; /* 0:5 reserved, 6 abort, 7 internal */ | |
132 | /* | |
133 | * The driver sets up the sequence number to values of its choosing. | |
134 | * uCode does not use this value, but passes it back to the driver | |
135 | * when sending the response to each driver-originated command, so | |
136 | * the driver can match the response to the command. Since the values | |
137 | * don't get used by uCode, the driver may set up an arbitrary format. | |
138 | * | |
139 | * There is one exception: uCode sets bit 15 when it originates | |
140 | * the response/notification, i.e. when the response/notification | |
141 | * is not a direct response to a command sent by the driver. For | |
142 | * example, uCode issues REPLY_RX when it sends a received frame | |
143 | * to the driver; it is not a direct response to any driver command. | |
144 | * | |
145 | * The Linux driver uses the following format: | |
146 | * | |
147 | * 0:7 tfd index - position within TX queue | |
148 | * 8:12 TX queue id | |
149 | * 13:14 reserved | |
150 | * 15 unsolicited RX or uCode-originated notification | |
151 | */ | |
152 | __le16 sequence; | |
153 | } __packed; | |
154 | ||
c08ce20c JB |
155 | /* iwl_cmd_header flags value */ |
156 | #define IWL_CMD_FAILED_MSK 0x40 | |
157 | ||
f8d7c1a1 JB |
158 | |
159 | #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ | |
0c19744c JB |
160 | #define FH_RSCSR_FRAME_INVALID 0x55550000 |
161 | #define FH_RSCSR_FRAME_ALIGN 0x40 | |
f8d7c1a1 JB |
162 | |
163 | struct iwl_rx_packet { | |
164 | /* | |
165 | * The first 4 bytes of the RX frame header contain both the RX frame | |
166 | * size and some flags. | |
167 | * Bit fields: | |
168 | * 31: flag flush RB request | |
169 | * 30: flag ignore TC (terminal counter) request | |
170 | * 29: flag fast IRQ request | |
171 | * 28-14: Reserved | |
172 | * 13-00: RX frame size | |
173 | */ | |
174 | __le32 len_n_flags; | |
175 | struct iwl_cmd_header hdr; | |
176 | u8 data[]; | |
177 | } __packed; | |
522376d2 | 178 | |
60396183 EG |
179 | /** |
180 | * enum CMD_MODE - how to send the host commands ? | |
181 | * | |
182 | * @CMD_SYNC: The caller will be stalled until the fw responds to the command | |
e89044d7 | 183 | * @CMD_ASYNC: Return right away and don't wait for the response |
60396183 | 184 | * @CMD_WANT_SKB: valid only with CMD_SYNC. The caller needs the buffer of the |
96791422 | 185 | * response. The caller needs to call iwl_free_resp when done. |
60396183 EG |
186 | */ |
187 | enum CMD_MODE { | |
4a4ee101 JB |
188 | CMD_SYNC = 0, |
189 | CMD_ASYNC = BIT(0), | |
190 | CMD_WANT_SKB = BIT(1), | |
4f59334b | 191 | CMD_SEND_IN_RFKILL = BIT(2), |
522376d2 EG |
192 | }; |
193 | ||
194 | #define DEF_CMD_PAYLOAD_SIZE 320 | |
195 | ||
196 | /** | |
197 | * struct iwl_device_cmd | |
198 | * | |
199 | * For allocation of the command and tx queues, this establishes the overall | |
200 | * size of the largest command we send to uCode, except for commands that | |
201 | * aren't fully copied and use other TFD space. | |
202 | */ | |
203 | struct iwl_device_cmd { | |
204 | struct iwl_cmd_header hdr; /* uCode API */ | |
132f98c2 | 205 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; |
522376d2 EG |
206 | } __packed; |
207 | ||
208 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) | |
209 | ||
1afbfb60 JB |
210 | /* |
211 | * number of transfer buffers (fragments) per transmit frame descriptor; | |
212 | * this is just the driver's idea, the hardware supports 20 | |
213 | */ | |
214 | #define IWL_MAX_CMD_TBS_PER_TFD 2 | |
522376d2 | 215 | |
60396183 EG |
216 | /** |
217 | * struct iwl_hcmd_dataflag - flag for each one of the chunks of the command | |
218 | * | |
f4feb8ac | 219 | * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's |
60396183 | 220 | * ring. The transport layer doesn't map the command's buffer to DMA, but |
e89044d7 | 221 | * rather copies it to a previously allocated DMA buffer. This flag tells |
60396183 | 222 | * the transport layer not to copy the command, but to map the existing |
3e2c1592 JB |
223 | * buffer (that is passed in) instead. This saves the memcpy and allows |
224 | * commands that are bigger than the fixed buffer to be submitted. | |
225 | * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. | |
f4feb8ac JB |
226 | * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this |
227 | * chunk internally and free it again after the command completes. This | |
228 | * can (currently) be used only once per command. | |
3e2c1592 | 229 | * Note that a TFD entry after a DUP one cannot be a normal copied one. |
60396183 | 230 | */ |
522376d2 EG |
231 | enum iwl_hcmd_dataflag { |
232 | IWL_HCMD_DFL_NOCOPY = BIT(0), | |
f4feb8ac | 233 | IWL_HCMD_DFL_DUP = BIT(1), |
522376d2 EG |
234 | }; |
235 | ||
236 | /** | |
237 | * struct iwl_host_cmd - Host command to the uCode | |
60396183 | 238 | * |
522376d2 | 239 | * @data: array of chunks that composes the data of the host command |
65b94a4a JB |
240 | * @resp_pkt: response packet, if %CMD_WANT_SKB was set |
241 | * @_rx_page_order: (internally used to free response packet) | |
242 | * @_rx_page_addr: (internally used to free response packet) | |
247c61d6 EG |
243 | * @handler_status: return value of the handler of the command |
244 | * (put in setup_rx_handlers) - valid for SYNC mode only | |
60396183 | 245 | * @flags: can be CMD_* |
e89044d7 | 246 | * @len: array of the lengths of the chunks in data |
60396183 | 247 | * @dataflags: IWL_HCMD_DFL_* |
522376d2 EG |
248 | * @id: id of the host command |
249 | */ | |
250 | struct iwl_host_cmd { | |
1afbfb60 | 251 | const void *data[IWL_MAX_CMD_TBS_PER_TFD]; |
65b94a4a JB |
252 | struct iwl_rx_packet *resp_pkt; |
253 | unsigned long _rx_page_addr; | |
254 | u32 _rx_page_order; | |
247c61d6 EG |
255 | int handler_status; |
256 | ||
522376d2 | 257 | u32 flags; |
1afbfb60 JB |
258 | u16 len[IWL_MAX_CMD_TBS_PER_TFD]; |
259 | u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; | |
522376d2 EG |
260 | u8 id; |
261 | }; | |
41c50542 | 262 | |
65b94a4a JB |
263 | static inline void iwl_free_resp(struct iwl_host_cmd *cmd) |
264 | { | |
265 | free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); | |
266 | } | |
267 | ||
930dfd5f JB |
268 | struct iwl_rx_cmd_buffer { |
269 | struct page *_page; | |
0c19744c JB |
270 | int _offset; |
271 | bool _page_stolen; | |
d13f1862 | 272 | u32 _rx_page_order; |
ed90542b | 273 | unsigned int truesize; |
930dfd5f JB |
274 | }; |
275 | ||
276 | static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) | |
277 | { | |
0c19744c JB |
278 | return (void *)((unsigned long)page_address(r->_page) + r->_offset); |
279 | } | |
280 | ||
281 | static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) | |
282 | { | |
283 | return r->_offset; | |
930dfd5f JB |
284 | } |
285 | ||
286 | static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) | |
287 | { | |
0c19744c JB |
288 | r->_page_stolen = true; |
289 | get_page(r->_page); | |
290 | return r->_page; | |
930dfd5f JB |
291 | } |
292 | ||
d13f1862 EG |
293 | static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) |
294 | { | |
295 | __free_pages(r->_page, r->_rx_page_order); | |
296 | } | |
297 | ||
d663ee73 JB |
298 | #define MAX_NO_RECLAIM_CMDS 6 |
299 | ||
ff110c8f GG |
300 | #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
301 | ||
9eae88fa JB |
302 | /* |
303 | * Maximum number of HW queues the transport layer | |
304 | * currently supports | |
305 | */ | |
306 | #define IWL_MAX_HW_QUEUES 32 | |
b04db9ac EG |
307 | #define IWL_MAX_TID_COUNT 8 |
308 | #define IWL_FRAME_LIMIT 64 | |
9eae88fa | 309 | |
ddaf5a5b JB |
310 | /** |
311 | * enum iwl_wowlan_status - WoWLAN image/device status | |
312 | * @IWL_D3_STATUS_ALIVE: firmware is still running after resume | |
313 | * @IWL_D3_STATUS_RESET: device was reset while suspended | |
314 | */ | |
315 | enum iwl_d3_status { | |
316 | IWL_D3_STATUS_ALIVE, | |
317 | IWL_D3_STATUS_RESET, | |
318 | }; | |
319 | ||
92d743ae MV |
320 | /** |
321 | * struct iwl_trans_config - transport configuration | |
322 | * | |
323 | * @op_mode: pointer to the upper layer. | |
c6f600fc MV |
324 | * @cmd_queue: the index of the command queue. |
325 | * Must be set before start_fw. | |
b04db9ac | 326 | * @cmd_fifo: the fifo for host commands |
d663ee73 JB |
327 | * @no_reclaim_cmds: Some devices erroneously don't set the |
328 | * SEQ_RX_FRAME bit on some notifications, this is the | |
329 | * list of such notifications to filter. Max length is | |
330 | * %MAX_NO_RECLAIM_CMDS. | |
331 | * @n_no_reclaim_cmds: # of commands in list | |
b2cf410c JB |
332 | * @rx_buf_size_8k: 8 kB RX buffer size needed for A-MSDUs, |
333 | * if unset 4k will be the RX buffer size | |
046db346 EG |
334 | * @bc_table_dword: set to true if the BC table expects the byte count to be |
335 | * in DWORD (as opposed to bytes) | |
7c5ba4a8 JB |
336 | * @queue_watchdog_timeout: time (in ms) after which queues |
337 | * are considered stuck and will trigger device restart | |
d9fb6465 JB |
338 | * @command_names: array of command names, must be 256 entries |
339 | * (one for each command); for debugging only | |
92d743ae MV |
340 | */ |
341 | struct iwl_trans_config { | |
342 | struct iwl_op_mode *op_mode; | |
9eae88fa | 343 | |
c6f600fc | 344 | u8 cmd_queue; |
b04db9ac | 345 | u8 cmd_fifo; |
d663ee73 JB |
346 | const u8 *no_reclaim_cmds; |
347 | int n_no_reclaim_cmds; | |
b2cf410c JB |
348 | |
349 | bool rx_buf_size_8k; | |
046db346 | 350 | bool bc_table_dword; |
7c5ba4a8 | 351 | unsigned int queue_watchdog_timeout; |
d9fb6465 | 352 | const char **command_names; |
92d743ae MV |
353 | }; |
354 | ||
87ce05a2 EG |
355 | struct iwl_trans; |
356 | ||
41c50542 EG |
357 | /** |
358 | * struct iwl_trans_ops - transport specific operations | |
60396183 EG |
359 | * |
360 | * All the handlers MUST be implemented | |
361 | * | |
57a1dc89 | 362 | * @start_hw: starts the HW- from that point on, the HW can send interrupts |
60396183 | 363 | * May sleep |
cc56feb2 | 364 | * @stop_hw: stops the HW- from that point on, the HW will be in low power but |
218733cf EG |
365 | * will still issue interrupt if the HW RF kill is triggered unless |
366 | * op_mode_leaving is true. | |
60396183 | 367 | * May sleep |
cf614297 | 368 | * @start_fw: allocates and inits all the resources for the transport |
60396183 EG |
369 | * layer. Also kick a fw image. |
370 | * May sleep | |
adca1235 EG |
371 | * @fw_alive: called when the fw sends alive notification. If the fw provides |
372 | * the SCD base address in SRAM, then provide it here, or 0 otherwise. | |
60396183 | 373 | * May sleep |
41c50542 | 374 | * @stop_device:stops the whole device (embedded CPU put to reset) |
60396183 | 375 | * May sleep |
ddaf5a5b | 376 | * @d3_suspend: put the device into the correct mode for WoWLAN during |
2dd4f9f7 JB |
377 | * suspend. This is optional, if not implemented WoWLAN will not be |
378 | * supported. This callback may sleep. | |
ddaf5a5b JB |
379 | * @d3_resume: resume the device after WoWLAN, enabling the opmode to |
380 | * talk to the WoWLAN image to get its status. This is optional, if not | |
381 | * implemented WoWLAN will not be supported. This callback may sleep. | |
f946b529 EG |
382 | * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. |
383 | * If RFkill is asserted in the middle of a SYNC host command, it must | |
384 | * return -ERFKILL straight away. | |
60396183 | 385 | * May sleep only if CMD_SYNC is set |
41c50542 | 386 | * @tx: send an skb |
60396183 | 387 | * Must be atomic |
a0eaad71 | 388 | * @reclaim: free packet until ssn. Returns a list of freed packets. |
60396183 | 389 | * Must be atomic |
b04db9ac EG |
390 | * @txq_enable: setup a queue. To setup an AC queue, use the |
391 | * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before | |
392 | * this one. The op_mode must not configure the HCMD queue. May sleep. | |
d0624be6 | 393 | * @txq_disable: de-configure a Tx queue to send AMPDUs |
b0b46192 | 394 | * Must be atomic |
5f178cd2 | 395 | * @wait_tx_queue_empty: wait until all tx queues are empty |
60396183 | 396 | * May sleep |
87e5666c EG |
397 | * @dbgfs_register: add the dbgfs files under this directory. Files will be |
398 | * automatically deleted. | |
03905495 EG |
399 | * @write8: write a u8 to a register at offset ofs from the BAR |
400 | * @write32: write a u32 to a register at offset ofs from the BAR | |
401 | * @read32: read a u32 register at offset ofs from the BAR | |
6a06b6c1 EG |
402 | * @read_prph: read a DWORD from a periphery register |
403 | * @write_prph: write a DWORD to a periphery register | |
4fd442db | 404 | * @read_mem: read device's SRAM in DWORD |
01387ffd EG |
405 | * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory |
406 | * will be zeroed. | |
c6f600fc | 407 | * @configure: configure parameters required by the transport layer from |
3dc420be EG |
408 | * the op_mode. May be called several times before start_fw, can't be |
409 | * called after that. | |
47107e84 | 410 | * @set_pmi: set the power pmi state |
e56b04ef LE |
411 | * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. |
412 | * Sleeping is not allowed between grab_nic_access and | |
413 | * release_nic_access. | |
414 | * @release_nic_access: let the NIC go to sleep. The "flags" parameter | |
415 | * must be the same one that was sent before to the grab_nic_access. | |
e139dc4a | 416 | * @set_bits_mask - set SRAM register according to value and mask. |
41c50542 EG |
417 | */ |
418 | struct iwl_trans_ops { | |
419 | ||
57a1dc89 | 420 | int (*start_hw)(struct iwl_trans *iwl_trans); |
218733cf | 421 | void (*stop_hw)(struct iwl_trans *iwl_trans, bool op_mode_leaving); |
6ae02f3e EG |
422 | int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, |
423 | bool run_in_rfkill); | |
adca1235 | 424 | void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); |
6d8f6eeb | 425 | void (*stop_device)(struct iwl_trans *trans); |
41c50542 | 426 | |
debff618 JB |
427 | void (*d3_suspend)(struct iwl_trans *trans, bool test); |
428 | int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, | |
429 | bool test); | |
2dd4f9f7 | 430 | |
6d8f6eeb | 431 | int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); |
41c50542 | 432 | |
e13c0c59 | 433 | int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa JB |
434 | struct iwl_device_cmd *dev_cmd, int queue); |
435 | void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, | |
436 | struct sk_buff_head *skbs); | |
437 | ||
4beaf6c2 EG |
438 | void (*txq_enable)(struct iwl_trans *trans, int queue, int fifo, |
439 | int sta_id, int tid, int frame_limit, u16 ssn); | |
d0624be6 | 440 | void (*txq_disable)(struct iwl_trans *trans, int queue); |
41c50542 | 441 | |
87e5666c | 442 | int (*dbgfs_register)(struct iwl_trans *trans, struct dentry* dir); |
5f178cd2 | 443 | int (*wait_tx_queue_empty)(struct iwl_trans *trans); |
5fdda047 | 444 | |
03905495 EG |
445 | void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); |
446 | void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); | |
447 | u32 (*read32)(struct iwl_trans *trans, u32 ofs); | |
6a06b6c1 EG |
448 | u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); |
449 | void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); | |
4fd442db EG |
450 | int (*read_mem)(struct iwl_trans *trans, u32 addr, |
451 | void *buf, int dwords); | |
452 | int (*write_mem)(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 453 | const void *buf, int dwords); |
c6f600fc MV |
454 | void (*configure)(struct iwl_trans *trans, |
455 | const struct iwl_trans_config *trans_cfg); | |
47107e84 | 456 | void (*set_pmi)(struct iwl_trans *trans, bool state); |
e56b04ef LE |
457 | bool (*grab_nic_access)(struct iwl_trans *trans, bool silent, |
458 | unsigned long *flags); | |
459 | void (*release_nic_access)(struct iwl_trans *trans, | |
460 | unsigned long *flags); | |
e139dc4a LE |
461 | void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, |
462 | u32 value); | |
41c50542 EG |
463 | }; |
464 | ||
69655ebf EG |
465 | /** |
466 | * enum iwl_trans_state - state of the transport layer | |
467 | * | |
468 | * @IWL_TRANS_NO_FW: no fw has sent an alive response | |
469 | * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response | |
470 | */ | |
471 | enum iwl_trans_state { | |
472 | IWL_TRANS_NO_FW = 0, | |
473 | IWL_TRANS_FW_ALIVE = 1, | |
474 | }; | |
475 | ||
6fbfae8e EG |
476 | /** |
477 | * struct iwl_trans - transport common data | |
60396183 | 478 | * |
6fbfae8e | 479 | * @ops - pointer to iwl_trans_ops |
ed277c93 | 480 | * @op_mode - pointer to the op_mode |
035f7ff2 | 481 | * @cfg - pointer to the configuration |
a42a1844 | 482 | * @dev - pointer to struct device * that represents the device |
99673ee5 | 483 | * @hw_id: a u32 with the ID of the device / subdevice. |
60396183 | 484 | * Set during transport allocation. |
9ca85961 | 485 | * @hw_id_str: a string with info about HW ID. Set during transport allocation. |
f6d0e9be | 486 | * @pm_support: set to true in start_hw if link pm is supported |
59c647b6 EG |
487 | * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. |
488 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
489 | * @dev_cmd_headroom: room needed for the transport's private use before the | |
490 | * device_cmd for Tx - for internal use only | |
491 | * The user should use iwl_trans_{alloc,free}_tx_cmd. | |
f042c2eb JB |
492 | * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before |
493 | * starting the firmware, used for tracing | |
494 | * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the | |
495 | * start of the 802.11 header in the @rx_mpdu_cmd | |
6fbfae8e | 496 | */ |
41c50542 EG |
497 | struct iwl_trans { |
498 | const struct iwl_trans_ops *ops; | |
ed277c93 | 499 | struct iwl_op_mode *op_mode; |
035f7ff2 | 500 | const struct iwl_cfg *cfg; |
69655ebf | 501 | enum iwl_trans_state state; |
e6bb4c9c | 502 | |
a42a1844 | 503 | struct device *dev; |
08079a49 | 504 | u32 hw_rev; |
99673ee5 | 505 | u32 hw_id; |
9ca85961 | 506 | char hw_id_str[52]; |
a42a1844 | 507 | |
f042c2eb JB |
508 | u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; |
509 | ||
f6d0e9be | 510 | bool pm_support; |
97b52cfd | 511 | |
59c647b6 EG |
512 | /* The following fields are internal only */ |
513 | struct kmem_cache *dev_cmd_pool; | |
514 | size_t dev_cmd_headroom; | |
3ec45882 | 515 | char dev_cmd_pool_name[50]; |
59c647b6 | 516 | |
9da987ac MV |
517 | struct dentry *dbgfs_dir; |
518 | ||
2bfb5092 JB |
519 | #ifdef CONFIG_LOCKDEP |
520 | struct lockdep_map sync_cmd_lockdep_map; | |
521 | #endif | |
522 | ||
e6bb4c9c EG |
523 | /* pointer to trans specific struct */ |
524 | /*Ensure that this pointer will always be aligned to sizeof pointer */ | |
cbe6ab4e | 525 | char trans_specific[0] __aligned(sizeof(void *)); |
41c50542 EG |
526 | }; |
527 | ||
ed277c93 | 528 | static inline void iwl_trans_configure(struct iwl_trans *trans, |
92d743ae | 529 | const struct iwl_trans_config *trans_cfg) |
ed277c93 | 530 | { |
92d743ae | 531 | trans->op_mode = trans_cfg->op_mode; |
c6f600fc MV |
532 | |
533 | trans->ops->configure(trans, trans_cfg); | |
ed277c93 EG |
534 | } |
535 | ||
57a1dc89 | 536 | static inline int iwl_trans_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 537 | { |
60396183 EG |
538 | might_sleep(); |
539 | ||
57a1dc89 | 540 | return trans->ops->start_hw(trans); |
e6bb4c9c EG |
541 | } |
542 | ||
218733cf EG |
543 | static inline void iwl_trans_stop_hw(struct iwl_trans *trans, |
544 | bool op_mode_leaving) | |
cc56feb2 | 545 | { |
60396183 EG |
546 | might_sleep(); |
547 | ||
218733cf | 548 | trans->ops->stop_hw(trans, op_mode_leaving); |
69655ebf | 549 | |
b4991f3f EG |
550 | if (op_mode_leaving) |
551 | trans->op_mode = NULL; | |
552 | ||
69655ebf | 553 | trans->state = IWL_TRANS_NO_FW; |
cc56feb2 EG |
554 | } |
555 | ||
adca1235 | 556 | static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 557 | { |
60396183 EG |
558 | might_sleep(); |
559 | ||
69655ebf | 560 | trans->state = IWL_TRANS_FW_ALIVE; |
b04db9ac | 561 | |
adca1235 | 562 | trans->ops->fw_alive(trans, scd_addr); |
ed6a3803 EG |
563 | } |
564 | ||
0692fe41 | 565 | static inline int iwl_trans_start_fw(struct iwl_trans *trans, |
6ae02f3e EG |
566 | const struct fw_img *fw, |
567 | bool run_in_rfkill) | |
bdfbf092 | 568 | { |
cf614297 EG |
569 | might_sleep(); |
570 | ||
f042c2eb JB |
571 | WARN_ON_ONCE(!trans->rx_mpdu_cmd); |
572 | ||
6ae02f3e | 573 | return trans->ops->start_fw(trans, fw, run_in_rfkill); |
bdfbf092 EG |
574 | } |
575 | ||
e6bb4c9c | 576 | static inline void iwl_trans_stop_device(struct iwl_trans *trans) |
bdfbf092 | 577 | { |
60396183 EG |
578 | might_sleep(); |
579 | ||
6d8f6eeb | 580 | trans->ops->stop_device(trans); |
69655ebf EG |
581 | |
582 | trans->state = IWL_TRANS_NO_FW; | |
bdfbf092 EG |
583 | } |
584 | ||
debff618 | 585 | static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test) |
ddaf5a5b JB |
586 | { |
587 | might_sleep(); | |
debff618 | 588 | trans->ops->d3_suspend(trans, test); |
ddaf5a5b JB |
589 | } |
590 | ||
591 | static inline int iwl_trans_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
592 | enum iwl_d3_status *status, |
593 | bool test) | |
2dd4f9f7 JB |
594 | { |
595 | might_sleep(); | |
debff618 | 596 | return trans->ops->d3_resume(trans, status, test); |
2dd4f9f7 JB |
597 | } |
598 | ||
e6bb4c9c | 599 | static inline int iwl_trans_send_cmd(struct iwl_trans *trans, |
2bfb5092 | 600 | struct iwl_host_cmd *cmd) |
bdfbf092 | 601 | { |
2bfb5092 JB |
602 | int ret; |
603 | ||
f0d120af JB |
604 | WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE, |
605 | "%s bad state = %d", __func__, trans->state); | |
69655ebf | 606 | |
2bfb5092 JB |
607 | if (!(cmd->flags & CMD_ASYNC)) |
608 | lock_map_acquire_read(&trans->sync_cmd_lockdep_map); | |
609 | ||
610 | ret = trans->ops->send_cmd(trans, cmd); | |
611 | ||
612 | if (!(cmd->flags & CMD_ASYNC)) | |
613 | lock_map_release(&trans->sync_cmd_lockdep_map); | |
614 | ||
615 | return ret; | |
bdfbf092 EG |
616 | } |
617 | ||
59c647b6 EG |
618 | static inline struct iwl_device_cmd * |
619 | iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) | |
620 | { | |
621 | u8 *dev_cmd_ptr = kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC); | |
622 | ||
623 | if (unlikely(dev_cmd_ptr == NULL)) | |
624 | return NULL; | |
625 | ||
626 | return (struct iwl_device_cmd *) | |
627 | (dev_cmd_ptr + trans->dev_cmd_headroom); | |
628 | } | |
629 | ||
630 | static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, | |
631 | struct iwl_device_cmd *dev_cmd) | |
632 | { | |
633 | u8 *dev_cmd_ptr = (u8 *)dev_cmd - trans->dev_cmd_headroom; | |
634 | ||
635 | kmem_cache_free(trans->dev_cmd_pool, dev_cmd_ptr); | |
636 | } | |
637 | ||
e6bb4c9c | 638 | static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa | 639 | struct iwl_device_cmd *dev_cmd, int queue) |
a0eaad71 | 640 | { |
f0d120af JB |
641 | WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE, |
642 | "%s bad state = %d", __func__, trans->state); | |
69655ebf | 643 | |
9eae88fa | 644 | return trans->ops->tx(trans, skb, dev_cmd, queue); |
a0eaad71 EG |
645 | } |
646 | ||
9eae88fa JB |
647 | static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, |
648 | int ssn, struct sk_buff_head *skbs) | |
48d42c42 | 649 | { |
f0d120af JB |
650 | WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE, |
651 | "%s bad state = %d", __func__, trans->state); | |
69655ebf | 652 | |
9eae88fa | 653 | trans->ops->reclaim(trans, queue, ssn, skbs); |
48d42c42 EG |
654 | } |
655 | ||
d0624be6 | 656 | static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue) |
288712a6 | 657 | { |
f0d120af JB |
658 | WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE, |
659 | "%s bad state = %d", __func__, trans->state); | |
69655ebf | 660 | |
d0624be6 | 661 | trans->ops->txq_disable(trans, queue); |
288712a6 EG |
662 | } |
663 | ||
4beaf6c2 EG |
664 | static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, |
665 | int fifo, int sta_id, int tid, | |
666 | int frame_limit, u16 ssn) | |
48d42c42 | 667 | { |
60396183 EG |
668 | might_sleep(); |
669 | ||
f0d120af JB |
670 | WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE, |
671 | "%s bad state = %d", __func__, trans->state); | |
69655ebf | 672 | |
4beaf6c2 | 673 | trans->ops->txq_enable(trans, queue, fifo, sta_id, tid, |
9eae88fa | 674 | frame_limit, ssn); |
48d42c42 EG |
675 | } |
676 | ||
b04db9ac EG |
677 | static inline void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, |
678 | int fifo) | |
679 | { | |
881acd89 | 680 | iwl_trans_txq_enable(trans, queue, fifo, -1, |
b04db9ac EG |
681 | IWL_MAX_TID_COUNT, IWL_FRAME_LIMIT, 0); |
682 | } | |
683 | ||
5f178cd2 EG |
684 | static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans) |
685 | { | |
f0d120af JB |
686 | WARN_ONCE(trans->state != IWL_TRANS_FW_ALIVE, |
687 | "%s bad state = %d", __func__, trans->state); | |
69655ebf | 688 | |
5f178cd2 EG |
689 | return trans->ops->wait_tx_queue_empty(trans); |
690 | } | |
691 | ||
87e5666c | 692 | static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans, |
4fd442db | 693 | struct dentry *dir) |
87e5666c EG |
694 | { |
695 | return trans->ops->dbgfs_register(trans, dir); | |
696 | } | |
697 | ||
03905495 EG |
698 | static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
699 | { | |
700 | trans->ops->write8(trans, ofs, val); | |
701 | } | |
702 | ||
703 | static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
704 | { | |
705 | trans->ops->write32(trans, ofs, val); | |
706 | } | |
707 | ||
708 | static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) | |
709 | { | |
710 | return trans->ops->read32(trans, ofs); | |
711 | } | |
712 | ||
6a06b6c1 EG |
713 | static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) |
714 | { | |
715 | return trans->ops->read_prph(trans, ofs); | |
716 | } | |
717 | ||
718 | static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, | |
719 | u32 val) | |
720 | { | |
721 | return trans->ops->write_prph(trans, ofs, val); | |
722 | } | |
723 | ||
4fd442db EG |
724 | static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, |
725 | void *buf, int dwords) | |
726 | { | |
727 | return trans->ops->read_mem(trans, addr, buf, dwords); | |
728 | } | |
729 | ||
730 | #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ | |
731 | do { \ | |
732 | if (__builtin_constant_p(bufsize)) \ | |
733 | BUILD_BUG_ON((bufsize) % sizeof(u32)); \ | |
734 | iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ | |
735 | } while (0) | |
736 | ||
737 | static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) | |
738 | { | |
739 | u32 value; | |
740 | ||
741 | if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) | |
742 | return 0xa5a5a5a5; | |
743 | ||
744 | return value; | |
745 | } | |
746 | ||
747 | static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 748 | const void *buf, int dwords) |
4fd442db EG |
749 | { |
750 | return trans->ops->write_mem(trans, addr, buf, dwords); | |
751 | } | |
752 | ||
753 | static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, | |
754 | u32 val) | |
755 | { | |
756 | return iwl_trans_write_mem(trans, addr, &val, 1); | |
757 | } | |
758 | ||
47107e84 DF |
759 | static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) |
760 | { | |
761 | trans->ops->set_pmi(trans, state); | |
762 | } | |
763 | ||
e139dc4a LE |
764 | static inline void |
765 | iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) | |
766 | { | |
767 | trans->ops->set_bits_mask(trans, reg, mask, value); | |
768 | } | |
769 | ||
e56b04ef | 770 | #define iwl_trans_grab_nic_access(trans, silent, flags) \ |
abae2386 | 771 | __cond_lock(nic_access, \ |
e56b04ef | 772 | likely((trans)->ops->grab_nic_access(trans, silent, flags))) |
7a65d170 | 773 | |
abae2386 | 774 | static inline void __releases(nic_access) |
e56b04ef | 775 | iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) |
7a65d170 | 776 | { |
e56b04ef | 777 | trans->ops->release_nic_access(trans, flags); |
abae2386 | 778 | __release(nic_access); |
7a65d170 EG |
779 | } |
780 | ||
b52e7ea1 | 781 | /***************************************************** |
d1ff5253 | 782 | * driver (transport) register/unregister functions |
b52e7ea1 | 783 | ******************************************************/ |
36a79223 EG |
784 | int __must_check iwl_pci_register_driver(void); |
785 | void iwl_pci_unregister_driver(void); | |
b52e7ea1 | 786 | |
2bfb5092 JB |
787 | static inline void trans_lockdep_init(struct iwl_trans *trans) |
788 | { | |
789 | #ifdef CONFIG_LOCKDEP | |
790 | static struct lock_class_key __key; | |
791 | ||
792 | lockdep_init_map(&trans->sync_cmd_lockdep_map, "sync_cmd_lockdep_map", | |
793 | &__key, 0); | |
794 | #endif | |
795 | } | |
796 | ||
41c50542 | 797 | #endif /* __iwl_trans_h__ */ |