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iwlwifi: add iwl_cmd_queue_free for readability
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
1053d35f
RR		 31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
30e553e3
TW		 39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
30e553e3 59
1053d35f
RR		 60/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
a33c2f47 66static int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
1053d35f
RR		 67{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
1053d35f
RR		 75 /* Sanity check on number of chunks */
76 counter = IWL_GET_BITS(*bd, num_tbs);
77 if (counter > MAX_NUM_OF_TBS) {
78 IWL_ERROR("Too many chunks: %i\n", counter);
79 /* @todo issue fatal error, it is quite serious situation */
80 return 0;
81 }
82
83 /* Unmap chunks, if any.
84 * TFD info for odd chunks is different format than for even chunks. */
85 for (i = 0; i < counter; i++) {
86 index = i / 2;
87 is_odd = i & 0x1;
88
89 if (is_odd)
90 pci_unmap_single(
91 dev,
92 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
93 (IWL_GET_BITS(bd->pa[index],
94 tb2_addr_hi20) << 16),
95 IWL_GET_BITS(bd->pa[index], tb2_len),
96 PCI_DMA_TODEVICE);
97
98 else if (i > 0)
99 pci_unmap_single(dev,
100 le32_to_cpu(bd->pa[index].tb1_addr),
101 IWL_GET_BITS(bd->pa[index], tb1_len),
102 PCI_DMA_TODEVICE);
103
104 /* Free SKB, if any, for this chunk */
105 if (txq->txb[txq->q.read_ptr].skb[i]) {
106 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
107
108 dev_kfree_skb(skb);
109 txq->txb[txq->q.read_ptr].skb[i] = NULL;
110 }
111 }
112 return 0;
113}
1053d35f 114
a33c2f47 115static int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
fd4abac5
TW		 116 dma_addr_t addr, u16 len)
117{
118 int index, is_odd;
119 struct iwl_tfd_frame *tfd = ptr;
120 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
121
122 /* Each TFD can point to a maximum 20 Tx buffers */
73ae98a1 123 if (num_tbs >= MAX_NUM_OF_TBS) {
fd4abac5
TW		 124 IWL_ERROR("Error can not send more than %d chunks\n",
125 MAX_NUM_OF_TBS);
126 return -EINVAL;
127 }
128
129 index = num_tbs / 2;
130 is_odd = num_tbs & 0x1;
131
132 if (!is_odd) {
133 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
134 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
135 iwl_get_dma_hi_address(addr));
136 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
137 } else {
138 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
139 (u32) (addr & 0xffff));
140 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
141 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
142 }
143
144 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
145
146 return 0;
147}
fd4abac5
TW		 148
149/**
150 * iwl_txq_update_write_ptr - Send new write index to hardware
151 */
152int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
153{
154 u32 reg = 0;
155 int ret = 0;
156 int txq_id = txq->q.id;
157
158 if (txq->need_update == 0)
159 return ret;
160
161 /* if we're trying to save power */
162 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
163 /* wake up nic if it's powered down ...
164 * uCode will wake up, and interrupt us again, so next
165 * time we'll skip this part. */
166 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
167
168 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
169 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
170 iwl_set_bit(priv, CSR_GP_CNTRL,
171 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
172 return ret;
173 }
174
175 /* restore this queue's parameters in nic hardware. */
176 ret = iwl_grab_nic_access(priv);
177 if (ret)
178 return ret;
179 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
180 txq->q.write_ptr | (txq_id << 8));
181 iwl_release_nic_access(priv);
182
183 /* else not in power-save mode, uCode will never sleep when we're
184 * trying to tx (during RFKILL, we're not trying to tx). */
185 } else
186 iwl_write32(priv, HBUS_TARG_WRPTR,
187 txq->q.write_ptr | (txq_id << 8));
188
189 txq->need_update = 0;
190
191 return ret;
192}
193EXPORT_SYMBOL(iwl_txq_update_write_ptr);
194
195
1053d35f
RR		 196/**
197 * iwl_tx_queue_free - Deallocate DMA queue.
198 * @txq: Transmit queue to deallocate.
199 *
200 * Empty queue by removing and destroying all BD's.
201 * Free all buffers.
202 * 0-fill, but do not free "txq" descriptor structure.
203 */
da99c4b6 204static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
1053d35f 205{
da99c4b6 206 struct iwl_tx_queue *txq = &priv->txq[txq_id];
443cfd45 207 struct iwl_queue *q = &txq->q;
1053d35f 208 struct pci_dev *dev = priv->pci_dev;
961ba60a 209 int i, len;
1053d35f
RR		 210
211 if (q->n_bd == 0)
212 return;
213
214 /* first, empty all BD's */
215 for (; q->write_ptr != q->read_ptr;
216 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
217 iwl_hw_txq_free_tfd(priv, txq);
218
219 len = sizeof(struct iwl_cmd) * q->n_window;
1053d35f
RR		 220
221 /* De-alloc array of command/tx buffers */
961ba60a 222 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
da99c4b6 223 kfree(txq->cmd[i]);
1053d35f
RR		 224
225 /* De-alloc circular buffer of TFDs */
226 if (txq->q.n_bd)
227 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
228 txq->q.n_bd, txq->bd, txq->q.dma_addr);
229
230 /* De-alloc array of per-TFD driver data */
231 kfree(txq->txb);
232 txq->txb = NULL;
233
234 /* 0-fill queue descriptor structure */
235 memset(txq, 0, sizeof(*txq));
236}
237
961ba60a
TW		 238
239/**
240 * iwl_cmd_queue_free - Deallocate DMA queue.
241 * @txq: Transmit queue to deallocate.
242 *
243 * Empty queue by removing and destroying all BD's.
244 * Free all buffers.
245 * 0-fill, but do not free "txq" descriptor structure.
246 */
247static void iwl_cmd_queue_free(struct iwl_priv *priv)
248{
249 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
250 struct iwl_queue *q = &txq->q;
251 struct pci_dev *dev = priv->pci_dev;
252 int i, len;
253
254 if (q->n_bd == 0)
255 return;
256
257 len = sizeof(struct iwl_cmd) * q->n_window;
258 len += IWL_MAX_SCAN_SIZE;
259
260 /* De-alloc array of command/tx buffers */
261 for (i = 0; i <= TFD_CMD_SLOTS; i++)
262 kfree(txq->cmd[i]);
263
264 /* De-alloc circular buffer of TFDs */
265 if (txq->q.n_bd)
266 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
267 txq->q.n_bd, txq->bd, txq->q.dma_addr);
268
269 /* 0-fill queue descriptor structure */
270 memset(txq, 0, sizeof(*txq));
271}
fd4abac5
TW		 272/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
273 * DMA services
274 *
275 * Theory of operation
276 *
277 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
278 * of buffer descriptors, each of which points to one or more data buffers for
279 * the device to read from or fill. Driver and device exchange status of each
280 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
281 * entries in each circular buffer, to protect against confusing empty and full
282 * queue states.
283 *
284 * The device reads or writes the data in the queues via the device's several
285 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
286 *
287 * For Tx queue, there are low mark and high mark limits. If, after queuing
288 * the packet for Tx, free space become < low mark, Tx queue stopped. When
289 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
290 * Tx queue resumed.
291 *
292 * See more detailed info in iwl-4965-hw.h.
293 ***************************************************/
294
295int iwl_queue_space(const struct iwl_queue *q)
296{
297 int s = q->read_ptr - q->write_ptr;
298
299 if (q->read_ptr > q->write_ptr)
300 s -= q->n_bd;
301
302 if (s <= 0)
303 s += q->n_window;
304 /* keep some reserve to not confuse empty and full situations */
305 s -= 2;
306 if (s < 0)
307 s = 0;
308 return s;
309}
310EXPORT_SYMBOL(iwl_queue_space);
311
312
1053d35f
RR		 313/**
314 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
315 */
443cfd45 316static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 317 int count, int slots_num, u32 id)
318{
319 q->n_bd = count;
320 q->n_window = slots_num;
321 q->id = id;
322
323 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
324 * and iwl_queue_dec_wrap are broken. */
325 BUG_ON(!is_power_of_2(count));
326
327 /* slots_num must be power-of-two size, otherwise
328 * get_cmd_index is broken. */
329 BUG_ON(!is_power_of_2(slots_num));
330
331 q->low_mark = q->n_window / 4;
332 if (q->low_mark < 4)
333 q->low_mark = 4;
334
335 q->high_mark = q->n_window / 8;
336 if (q->high_mark < 2)
337 q->high_mark = 2;
338
339 q->write_ptr = q->read_ptr = 0;
340
341 return 0;
342}
343
344/**
345 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
346 */
347static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 348 struct iwl_tx_queue *txq, u32 id)
1053d35f
RR		 349{
350 struct pci_dev *dev = priv->pci_dev;
351
352 /* Driver private data, only for Tx (not command) queues,
353 * not shared with device. */
354 if (id != IWL_CMD_QUEUE_NUM) {
355 txq->txb = kmalloc(sizeof(txq->txb[0]) *
356 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
357 if (!txq->txb) {
358 IWL_ERROR("kmalloc for auxiliary BD "
359 "structures failed\n");
360 goto error;
361 }
362 } else
363 txq->txb = NULL;
364
365 /* Circular buffer of transmit frame descriptors (TFDs),
366 * shared with device */
367 txq->bd = pci_alloc_consistent(dev,
368 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
369 &txq->q.dma_addr);
370
371 if (!txq->bd) {
372 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
373 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
374 goto error;
375 }
376 txq->q.id = id;
377
378 return 0;
379
380 error:
381 kfree(txq->txb);
382 txq->txb = NULL;
383
384 return -ENOMEM;
385}
386
387/*
388 * Tell nic where to find circular buffer of Tx Frame Descriptors for
389 * given Tx queue, and enable the DMA channel used for that queue.
390 *
391 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
392 * channels supported in hardware.
393 */
394static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
16466903 395 struct iwl_tx_queue *txq)
1053d35f
RR		 396{
397 int rc;
398 unsigned long flags;
399 int txq_id = txq->q.id;
400
401 spin_lock_irqsave(&priv->lock, flags);
402 rc = iwl_grab_nic_access(priv);
403 if (rc) {
404 spin_unlock_irqrestore(&priv->lock, flags);
405 return rc;
406 }
407
408 /* Circular buffer (TFD queue in DRAM) physical base address */
409 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
410 txq->q.dma_addr >> 8);
411
412 /* Enable DMA channel, using same id as for TFD queue */
413 iwl_write_direct32(
414 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
415 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
416 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
417 iwl_release_nic_access(priv);
418 spin_unlock_irqrestore(&priv->lock, flags);
419
420 return 0;
421}
422
423/**
424 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
425 */
73b7d742 426static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
1053d35f
RR		 427 int slots_num, u32 txq_id)
428{
da99c4b6 429 int i, len;
73b7d742 430 int ret;
1053d35f
RR		 431
432 /*
433 * Alloc buffer array for commands (Tx or other types of commands).
434 * For the command queue (#4), allocate command space + one big
435 * command for scan, since scan command is very huge; the system will
436 * not have two scans at the same time, so only one is needed.
437 * For normal Tx queues (all other queues), no super-size command
438 * space is needed.
439 */
da99c4b6
GG		 440 len = sizeof(struct iwl_cmd);
441 for (i = 0; i <= slots_num; i++) {
442 if (i == slots_num) {
443 if (txq_id == IWL_CMD_QUEUE_NUM)
444 len += IWL_MAX_SCAN_SIZE;
445 else
446 continue;
447 }
448
49898852 449 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
da99c4b6 450 if (!txq->cmd[i])
73b7d742 451 goto err;
da99c4b6 452 }
1053d35f
RR		 453
454 /* Alloc driver data array and TFD circular buffer */
73b7d742
TW		 455 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
456 if (ret)
457 goto err;
1053d35f 458
1053d35f
RR		 459 txq->need_update = 0;
460
461 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
462 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
463 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
464
465 /* Initialize queue's high/low-water marks, and head/tail indexes */
466 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
467
468 /* Tell device where to find queue */
469 iwl_hw_tx_queue_init(priv, txq);
470
471 return 0;
73b7d742
TW		 472err:
473 for (i = 0; i < slots_num; i++) {
474 kfree(txq->cmd[i]);
475 txq->cmd[i] = NULL;
476 }
477
478 if (txq_id == IWL_CMD_QUEUE_NUM) {
479 kfree(txq->cmd[slots_num]);
480 txq->cmd[slots_num] = NULL;
481 }
482 return -ENOMEM;
1053d35f 483}
da1bc453
TW		 484/**
485 * iwl_hw_txq_ctx_free - Free TXQ Context
486 *
487 * Destroy all TX DMA queues and structures
488 */
489void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
490{
491 int txq_id;
492
493 /* Tx queues */
494 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
961ba60a
TW		 495 if (txq_id == IWL_CMD_QUEUE_NUM)
496 iwl_cmd_queue_free(priv);
497 else
498 iwl_tx_queue_free(priv, txq_id);
da1bc453
TW		 499
500 /* Keep-warm buffer */
501 iwl_kw_free(priv);
502}
503EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
504
1053d35f
RR		 505/**
506 * iwl_txq_ctx_reset - Reset TX queue context
507 * Destroys all DMA structures and initialise them again
508 *
509 * @param priv
510 * @return error code
511 */
512int iwl_txq_ctx_reset(struct iwl_priv *priv)
513{
514 int ret = 0;
515 int txq_id, slots_num;
da1bc453 516 unsigned long flags;
1053d35f
RR		 517
518 iwl_kw_free(priv);
519
520 /* Free all tx/cmd queues and keep-warm buffer */
521 iwl_hw_txq_ctx_free(priv);
522
523 /* Alloc keep-warm buffer */
524 ret = iwl_kw_alloc(priv);
525 if (ret) {
6f147926 526 IWL_ERROR("Keep Warm allocation failed\n");
1053d35f
RR		 527 goto error_kw;
528 }
da1bc453
TW		 529 spin_lock_irqsave(&priv->lock, flags);
530 ret = iwl_grab_nic_access(priv);
531 if (unlikely(ret)) {
532 spin_unlock_irqrestore(&priv->lock, flags);
533 goto error_reset;
534 }
1053d35f
RR		 535
536 /* Turn off all Tx DMA fifos */
da1bc453
TW		 537 priv->cfg->ops->lib->txq_set_sched(priv, 0);
538
539 iwl_release_nic_access(priv);
540 spin_unlock_irqrestore(&priv->lock, flags);
541
1053d35f
RR		 542
543 /* Tell nic where to find the keep-warm buffer */
544 ret = iwl_kw_init(priv);
545 if (ret) {
546 IWL_ERROR("kw_init failed\n");
547 goto error_reset;
548 }
549
da1bc453 550 /* Alloc and init all Tx queues, including the command queue (#4) */
1053d35f
RR		 551 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
552 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
553 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
554 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
555 txq_id);
556 if (ret) {
557 IWL_ERROR("Tx %d queue init failed\n", txq_id);
558 goto error;
559 }
560 }
561
562 return ret;
563
564 error:
565 iwl_hw_txq_ctx_free(priv);
566 error_reset:
567 iwl_kw_free(priv);
568 error_kw:
569 return ret;
570}
a33c2f47 571
da1bc453
TW		 572/**
573 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
574 */
575void iwl_txq_ctx_stop(struct iwl_priv *priv)
576{
577
578 int txq_id;
579 unsigned long flags;
580
581
582 /* Turn off all Tx DMA fifos */
583 spin_lock_irqsave(&priv->lock, flags);
584 if (iwl_grab_nic_access(priv)) {
585 spin_unlock_irqrestore(&priv->lock, flags);
586 return;
587 }
588
589 priv->cfg->ops->lib->txq_set_sched(priv, 0);
590
591 /* Stop each Tx DMA channel, and wait for it to be idle */
592 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
593 iwl_write_direct32(priv,
594 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
595 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
596 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
597 (txq_id), 200);
598 }
599 iwl_release_nic_access(priv);
600 spin_unlock_irqrestore(&priv->lock, flags);
601
602 /* Deallocate memory for all Tx queues */
603 iwl_hw_txq_ctx_free(priv);
604}
605EXPORT_SYMBOL(iwl_txq_ctx_stop);
fd4abac5
TW		 606
607/*
608 * handle build REPLY_TX command notification.
609 */
610static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
611 struct iwl_tx_cmd *tx_cmd,
e039fa4a 612 struct ieee80211_tx_info *info,
fd4abac5
TW		 613 struct ieee80211_hdr *hdr,
614 int is_unicast, u8 std_id)
615{
fd7c8a40 616 __le16 fc = hdr->frame_control;
fd4abac5
TW		 617 __le32 tx_flags = tx_cmd->tx_flags;
618
619 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 620 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
fd4abac5 621 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 622 if (ieee80211_is_mgmt(fc))
fd4abac5 623 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 624 if (ieee80211_is_probe_resp(fc) &&
fd4abac5
TW		 625 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
626 tx_flags |= TX_CMD_FLG_TSF_MSK;
627 } else {
628 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
629 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
630 }
631
fd7c8a40 632 if (ieee80211_is_back_req(fc))
fd4abac5
TW		 633 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
634
635
636 tx_cmd->sta_id = std_id;
8b7b1e05 637 if (ieee80211_has_morefrags(fc))
fd4abac5
TW		 638 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
639
fd7c8a40
HH		 640 if (ieee80211_is_data_qos(fc)) {
641 u8 *qc = ieee80211_get_qos_ctl(hdr);
fd4abac5
TW		 642 tx_cmd->tid_tspec = qc[0] & 0xf;
643 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
644 } else {
645 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
646 }
647
a326a5d0 648 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
fd4abac5
TW		 649
650 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
651 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
652
653 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 654 if (ieee80211_is_mgmt(fc)) {
655 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 656 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
657 else
658 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
659 } else {
660 tx_cmd->timeout.pm_frame_timeout = 0;
661 }
662
663 tx_cmd->driver_txop = 0;
664 tx_cmd->tx_flags = tx_flags;
665 tx_cmd->next_frame_len = 0;
666}
667
668#define RTS_HCCA_RETRY_LIMIT 3
669#define RTS_DFAULT_RETRY_LIMIT 60
670
671static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
672 struct iwl_tx_cmd *tx_cmd,
e039fa4a 673 struct ieee80211_tx_info *info,
fd7c8a40 674 __le16 fc, int sta_id,
fd4abac5
TW		 675 int is_hcca)
676{
677 u8 rts_retry_limit = 0;
678 u8 data_retry_limit = 0;
679 u8 rate_plcp;
680 u16 rate_flags = 0;
2e92e6f2
JB		 681 int rate_idx;
682
e039fa4a 683 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
2e92e6f2 684 IWL_RATE_COUNT - 1);
fd4abac5
TW		 685
686 rate_plcp = iwl_rates[rate_idx].plcp;
687
688 rts_retry_limit = (is_hcca) ?
689 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
690
691 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
692 rate_flags |= RATE_MCS_CCK_MSK;
693
694
fd7c8a40 695 if (ieee80211_is_probe_resp(fc)) {
fd4abac5
TW		 696 data_retry_limit = 3;
697 if (data_retry_limit < rts_retry_limit)
698 rts_retry_limit = data_retry_limit;
699 } else
700 data_retry_limit = IWL_DEFAULT_TX_RETRY;
701
702 if (priv->data_retry_limit != -1)
703 data_retry_limit = priv->data_retry_limit;
704
705
706 if (ieee80211_is_data(fc)) {
707 tx_cmd->initial_rate_index = 0;
708 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
709 } else {
fd7c8a40
HH		 710 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
711 case cpu_to_le16(IEEE80211_STYPE_AUTH):
712 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
713 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
714 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
fd4abac5
TW		 715 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
716 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
717 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
718 }
719 break;
720 default:
721 break;
722 }
723
724 /* Alternate between antenna A and B for successive frames */
725 if (priv->use_ant_b_for_management_frame) {
726 priv->use_ant_b_for_management_frame = 0;
727 rate_flags |= RATE_MCS_ANT_B_MSK;
728 } else {
729 priv->use_ant_b_for_management_frame = 1;
730 rate_flags |= RATE_MCS_ANT_A_MSK;
731 }
732 }
733
734 tx_cmd->rts_retry_limit = rts_retry_limit;
735 tx_cmd->data_retry_limit = data_retry_limit;
e7d326ac 736 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
fd4abac5
TW		 737}
738
739static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
e039fa4a 740 struct ieee80211_tx_info *info,
fd4abac5
TW		 741 struct iwl_tx_cmd *tx_cmd,
742 struct sk_buff *skb_frag,
743 int sta_id)
744{
e039fa4a 745 struct ieee80211_key_conf *keyconf = info->control.hw_key;
fd4abac5 746
ccc038ab 747 switch (keyconf->alg) {
fd4abac5
TW		 748 case ALG_CCMP:
749 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
ccc038ab 750 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
e039fa4a 751 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 752 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
753 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
754 break;
755
756 case ALG_TKIP:
757 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
ccc038ab 758 ieee80211_get_tkip_key(keyconf, skb_frag,
fd4abac5
TW		 759 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
760 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
761 break;
762
763 case ALG_WEP:
fd4abac5 764 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
ccc038ab
EG		 765 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
766
767 if (keyconf->keylen == WEP_KEY_LEN_128)
768 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
769
770 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
fd4abac5
TW		 771
772 IWL_DEBUG_TX("Configuring packet for WEP encryption "
ccc038ab 773 "with key %d\n", keyconf->keyidx);
fd4abac5
TW		 774 break;
775
776 default:
ccc038ab 777 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
fd4abac5
TW		 778 break;
779 }
780}
781
782static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
783{
784 /* 0 - mgmt, 1 - cnt, 2 - data */
785 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
786 priv->tx_stats[idx].cnt++;
787 priv->tx_stats[idx].bytes += len;
788}
789
790/*
791 * start REPLY_TX command process
792 */
e039fa4a 793int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
fd4abac5
TW		 794{
795 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 796 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fd4abac5 797 struct iwl_tfd_frame *tfd;
f3674227
TW		 798 struct iwl_tx_queue *txq;
799 struct iwl_queue *q;
800 struct iwl_cmd *out_cmd;
801 struct iwl_tx_cmd *tx_cmd;
802 int swq_id, txq_id;
fd4abac5
TW		 803 dma_addr_t phys_addr;
804 dma_addr_t txcmd_phys;
805 dma_addr_t scratch_phys;
fd4abac5
TW		 806 u16 len, idx, len_org;
807 u16 seq_number = 0;
fd7c8a40 808 __le16 fc;
f3674227
TW		 809 u8 hdr_len, unicast;
810 u8 sta_id;
fd4abac5
TW		 811 u8 wait_write_ptr = 0;
812 u8 tid = 0;
813 u8 *qc = NULL;
814 unsigned long flags;
815 int ret;
816
817 spin_lock_irqsave(&priv->lock, flags);
818 if (iwl_is_rfkill(priv)) {
819 IWL_DEBUG_DROP("Dropping - RF KILL\n");
820 goto drop_unlock;
821 }
822
e039fa4a 823 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
2e92e6f2 824 IWL_INVALID_RATE) {
fd4abac5
TW		 825 IWL_ERROR("ERROR: No TX rate available.\n");
826 goto drop_unlock;
827 }
828
829 unicast = !is_multicast_ether_addr(hdr->addr1);
fd4abac5 830
fd7c8a40 831 fc = hdr->frame_control;
fd4abac5
TW		 832
833#ifdef CONFIG_IWLWIFI_DEBUG
834 if (ieee80211_is_auth(fc))
835 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 836 else if (ieee80211_is_assoc_req(fc))
fd4abac5 837 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 838 else if (ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 839 IWL_DEBUG_TX("Sending REASSOC frame\n");
840#endif
841
842 /* drop all data frame if we are not associated */
fd7c8a40 843 if (ieee80211_is_data(fc) &&
05c914fe 844 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
d10c4ec8
SG		 845 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
846 (!iwl_is_associated(priv) ||
05c914fe 847 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
d10c4ec8 848 !priv->assoc_station_added)) {
fd4abac5
TW		 849 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
850 goto drop_unlock;
851 }
852
853 spin_unlock_irqrestore(&priv->lock, flags);
854
7294ec95 855 hdr_len = ieee80211_hdrlen(fc);
fd4abac5
TW		 856
857 /* Find (or create) index into station table for destination station */
858 sta_id = iwl_get_sta_id(priv, hdr);
859 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 860 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
861 hdr->addr1);
fd4abac5
TW		 862 goto drop;
863 }
864
865 IWL_DEBUG_TX("station Id %d\n", sta_id);
866
f3674227
TW		 867 swq_id = skb_get_queue_mapping(skb);
868 txq_id = swq_id;
fd7c8a40
HH		 869 if (ieee80211_is_data_qos(fc)) {
870 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 871 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f3674227
TW		 872 seq_number = priv->stations[sta_id].tid[tid].seq_number;
873 seq_number &= IEEE80211_SCTL_SEQ;
874 hdr->seq_ctrl = hdr->seq_ctrl &
875 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
876 hdr->seq_ctrl |= cpu_to_le16(seq_number);
fd4abac5 877 seq_number += 0x10;
fd4abac5 878 /* aggregation is on for this <sta,tid> */
e039fa4a 879 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 880 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
881 priv->stations[sta_id].tid[tid].tfds_in_queue++;
fd4abac5
TW		 882 }
883
884 /* Descriptor for chosen Tx queue */
885 txq = &priv->txq[txq_id];
886 q = &txq->q;
887
888 spin_lock_irqsave(&priv->lock, flags);
889
890 /* Set up first empty TFD within this queue's circular TFD buffer */
891 tfd = &txq->bd[q->write_ptr];
892 memset(tfd, 0, sizeof(*tfd));
fd4abac5
TW		 893 idx = get_cmd_index(q, q->write_ptr, 0);
894
895 /* Set up driver data for this TFD */
896 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
897 txq->txb[q->write_ptr].skb[0] = skb;
fd4abac5
TW		 898
899 /* Set up first empty entry in queue's array of Tx/cmd buffers */
da99c4b6 900 out_cmd = txq->cmd[idx];
fd4abac5
TW		 901 tx_cmd = &out_cmd->cmd.tx;
902 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
903 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
904
905 /*
906 * Set up the Tx-command (not MAC!) header.
907 * Store the chosen Tx queue and TFD index within the sequence field;
908 * after Tx, uCode's Tx response will return this value so driver can
909 * locate the frame within the tx queue and do post-tx processing.
910 */
911 out_cmd->hdr.cmd = REPLY_TX;
912 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
913 INDEX_TO_SEQ(q->write_ptr)));
914
915 /* Copy MAC header from skb into command buffer */
916 memcpy(tx_cmd->hdr, hdr, hdr_len);
917
918 /*
919 * Use the first empty entry in this queue's command buffer array
920 * to contain the Tx command and MAC header concatenated together
921 * (payload data will be in another buffer).
922 * Size of this varies, due to varying MAC header length.
923 * If end is not dword aligned, we'll have 2 extra bytes at the end
924 * of the MAC header (device reads on dword boundaries).
925 * We'll tell device about this padding later.
926 */
927 len = sizeof(struct iwl_tx_cmd) +
928 sizeof(struct iwl_cmd_header) + hdr_len;
929
930 len_org = len;
931 len = (len + 3) & ~3;
932
933 if (len_org != len)
934 len_org = 1;
935 else
936 len_org = 0;
937
938 /* Physical address of this Tx command's header (not MAC header!),
939 * within command buffer array. */
da99c4b6
GG		 940 txcmd_phys = pci_map_single(priv->pci_dev, out_cmd,
941 sizeof(struct iwl_cmd), PCI_DMA_TODEVICE);
942 txcmd_phys += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 943
944 /* Add buffer containing Tx command and MAC(!) header to TFD's
945 * first entry */
946 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
947
d0f09804 948 if (info->control.hw_key)
e039fa4a 949 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
fd4abac5
TW		 950
951 /* Set up TFD's 2nd entry to point directly to remainder of skb,
952 * if any (802.11 null frames have no payload). */
953 len = skb->len - hdr_len;
954 if (len) {
955 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
956 len, PCI_DMA_TODEVICE);
957 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
958 }
959
960 /* Tell NIC about any 2-byte padding after MAC header */
961 if (len_org)
962 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
963
964 /* Total # bytes to be transmitted */
965 len = (u16)skb->len;
966 tx_cmd->len = cpu_to_le16(len);
967 /* TODO need this for burst mode later on */
e039fa4a 968 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
fd4abac5
TW		 969
970 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 971 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
fd4abac5 972
fd7c8a40 973 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
fd4abac5
TW		 974
975 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
976 offsetof(struct iwl_tx_cmd, scratch);
977 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
978 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
979
8b7b1e05 980 if (!ieee80211_has_morefrags(hdr->frame_control)) {
fd4abac5
TW		 981 txq->need_update = 1;
982 if (qc)
983 priv->stations[sta_id].tid[tid].seq_number = seq_number;
984 } else {
985 wait_write_ptr = 1;
986 txq->need_update = 0;
987 }
988
989 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
990
991 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
992
993 /* Set up entry for this TFD in Tx byte-count array */
994 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
995
996 /* Tell device the write index *just past* this latest filled TFD */
997 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
998 ret = iwl_txq_update_write_ptr(priv, txq);
999 spin_unlock_irqrestore(&priv->lock, flags);
1000
1001 if (ret)
1002 return ret;
1003
143b09ef 1004 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
fd4abac5
TW		 1005 if (wait_write_ptr) {
1006 spin_lock_irqsave(&priv->lock, flags);
1007 txq->need_update = 1;
1008 iwl_txq_update_write_ptr(priv, txq);
1009 spin_unlock_irqrestore(&priv->lock, flags);
143b09ef 1010 } else {
f3674227 1011 ieee80211_stop_queue(priv->hw, swq_id);
fd4abac5 1012 }
fd4abac5
TW		 1013 }
1014
1015 return 0;
1016
1017drop_unlock:
1018 spin_unlock_irqrestore(&priv->lock, flags);
1019drop:
1020 return -1;
1021}
1022EXPORT_SYMBOL(iwl_tx_skb);
1023
1024/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1025
1026/**
1027 * iwl_enqueue_hcmd - enqueue a uCode command
1028 * @priv: device private data point
1029 * @cmd: a point to the ucode command structure
1030 *
1031 * The function returns < 0 values to indicate the operation is
1032 * failed. On success, it turns the index (> 0) of command in the
1033 * command queue.
1034 */
1035int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1036{
1037 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1038 struct iwl_queue *q = &txq->q;
1039 struct iwl_tfd_frame *tfd;
fd4abac5 1040 struct iwl_cmd *out_cmd;
fd4abac5 1041 dma_addr_t phys_addr;
fd4abac5 1042 unsigned long flags;
f3674227
TW		 1043 int len, ret;
1044 u32 idx;
1045 u16 fix_size;
fd4abac5
TW		 1046
1047 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1048 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1049
1050 /* If any of the command structures end up being larger than
1051 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1052 * we will need to increase the size of the TFD entries */
1053 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1054 !(cmd->meta.flags & CMD_SIZE_HUGE));
1055
1056 if (iwl_is_rfkill(priv)) {
1057 IWL_DEBUG_INFO("Not sending command - RF KILL");
1058 return -EIO;
1059 }
1060
1061 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1062 IWL_ERROR("No space for Tx\n");
1063 return -ENOSPC;
1064 }
1065
1066 spin_lock_irqsave(&priv->hcmd_lock, flags);
1067
1068 tfd = &txq->bd[q->write_ptr];
1069 memset(tfd, 0, sizeof(*tfd));
1070
fd4abac5
TW		 1071
1072 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
da99c4b6 1073 out_cmd = txq->cmd[idx];
fd4abac5
TW		 1074
1075 out_cmd->hdr.cmd = cmd->id;
1076 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1077 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1078
1079 /* At this point, the out_cmd now has all of the incoming cmd
1080 * information */
1081
1082 out_cmd->hdr.flags = 0;
1083 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1084 INDEX_TO_SEQ(q->write_ptr));
1085 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
9734cb23 1086 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
da99c4b6
GG		 1087 len = (idx == TFD_CMD_SLOTS) ?
1088 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1089 phys_addr = pci_map_single(priv->pci_dev, out_cmd, len,
1090 PCI_DMA_TODEVICE);
1091 phys_addr += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 1092 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1093
ded2ae7c
EK		 1094#ifdef CONFIG_IWLWIFI_DEBUG
1095 switch (out_cmd->hdr.cmd) {
1096 case REPLY_TX_LINK_QUALITY_CMD:
1097 case SENSITIVITY_CMD:
1098 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1099 "%d bytes at %d[%d]:%d\n",
1100 get_cmd_string(out_cmd->hdr.cmd),
1101 out_cmd->hdr.cmd,
1102 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1103 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1104 break;
1105 default:
1106 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1107 "%d bytes at %d[%d]:%d\n",
1108 get_cmd_string(out_cmd->hdr.cmd),
1109 out_cmd->hdr.cmd,
1110 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1111 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1112 }
1113#endif
fd4abac5
TW		 1114 txq->need_update = 1;
1115
1116 /* Set up entry in queue's byte count circular buffer */
1117 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1118
1119 /* Increment and update queue's write index */
1120 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1121 ret = iwl_txq_update_write_ptr(priv, txq);
1122
1123 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1124 return ret ? ret : idx;
1125}
1126
17b88929
TW		 1127int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1128{
1129 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1130 struct iwl_queue *q = &txq->q;
1131 struct iwl_tx_info *tx_info;
1132 int nfreed = 0;
1133
1134 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1135 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1136 "is out of range [0-%d] %d %d.\n", txq_id,
1137 index, q->n_bd, q->write_ptr, q->read_ptr);
1138 return 0;
1139 }
1140
1141 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1142 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1143
1144 tx_info = &txq->txb[txq->q.read_ptr];
1145 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1146 tx_info->skb[0] = NULL;
17b88929 1147
972cf447
TW		 1148 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1149 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1150
1151 iwl_hw_txq_free_tfd(priv, txq);
17b88929
TW		 1152 nfreed++;
1153 }
1154 return nfreed;
1155}
1156EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1157
1158
1159/**
1160 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1161 *
1162 * When FW advances 'R' index, all entries between old and new 'R' index
1163 * need to be reclaimed. As result, some free space forms. If there is
1164 * enough free space (> low mark), wake the stack that feeds us.
1165 */
1166static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1167{
1168 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1169 struct iwl_queue *q = &txq->q;
da99c4b6
GG		 1170 struct iwl_tfd_frame *bd = &txq->bd[index];
1171 dma_addr_t dma_addr;
1172 int is_odd, buf_len;
17b88929
TW		 1173 int nfreed = 0;
1174
1175 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1176 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1177 "is out of range [0-%d] %d %d.\n", txq_id,
1178 index, q->n_bd, q->write_ptr, q->read_ptr);
1179 return;
1180 }
1181
1182 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1183 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1184
1185 if (nfreed > 1) {
1186 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1187 q->write_ptr, q->read_ptr);
1188 queue_work(priv->workqueue, &priv->restart);
1189 }
da99c4b6
GG		 1190 is_odd = (index/2) & 0x1;
1191 if (is_odd) {
1192 dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1193 (IWL_GET_BITS(bd->pa[index],
1194 tb2_addr_hi20) << 16);
1195 buf_len = IWL_GET_BITS(bd->pa[index], tb2_len);
1196 } else {
1197 dma_addr = le32_to_cpu(bd->pa[index].tb1_addr);
1198 buf_len = IWL_GET_BITS(bd->pa[index], tb1_len);
1199 }
1200
1201 pci_unmap_single(priv->pci_dev, dma_addr, buf_len,
1202 PCI_DMA_TODEVICE);
17b88929
TW		 1203 nfreed++;
1204 }
1205}
1206
1207/**
1208 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1209 * @rxb: Rx buffer to reclaim
1210 *
1211 * If an Rx buffer has an async callback associated with it the callback
1212 * will be executed. The attached skb (if present) will only be freed
1213 * if the callback returns 1
1214 */
1215void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1216{
1217 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1218 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1219 int txq_id = SEQ_TO_QUEUE(sequence);
1220 int index = SEQ_TO_INDEX(sequence);
17b88929 1221 int cmd_index;
9734cb23 1222 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
17b88929
TW		 1223 struct iwl_cmd *cmd;
1224
1225 /* If a Tx command is being handled and it isn't in the actual
1226 * command queue then there a command routing bug has been introduced
1227 * in the queue management code. */
55d6a3cd
JB		 1228 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1229 "wrong command queue %d, command id 0x%X\n", txq_id, pkt->hdr.cmd))
1230 return;
17b88929
TW		 1231
1232 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
da99c4b6 1233 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
17b88929
TW		 1234
1235 /* Input error checking is done when commands are added to queue. */
1236 if (cmd->meta.flags & CMD_WANT_SKB) {
1237 cmd->meta.source->u.skb = rxb->skb;
1238 rxb->skb = NULL;
1239 } else if (cmd->meta.u.callback &&
1240 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1241 rxb->skb = NULL;
1242
1243 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1244
1245 if (!(cmd->meta.flags & CMD_ASYNC)) {
1246 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1247 wake_up_interruptible(&priv->wait_command_queue);
1248 }
1249}
1250EXPORT_SYMBOL(iwl_tx_cmd_complete);
1251
30e553e3
TW		 1252/*
1253 * Find first available (lowest unused) Tx Queue, mark it "active".
1254 * Called only when finding queue for aggregation.
1255 * Should never return anything < 7, because they should already
1256 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1257 */
1258static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1259{
1260 int txq_id;
1261
1262 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1263 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1264 return txq_id;
1265 return -1;
1266}
1267
1268int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1269{
1270 int sta_id;
1271 int tx_fifo;
1272 int txq_id;
1273 int ret;
1274 unsigned long flags;
1275 struct iwl_tid_data *tid_data;
30e553e3
TW		 1276
1277 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1278 tx_fifo = default_tid_to_tx_fifo[tid];
1279 else
1280 return -EINVAL;
1281
e174961c
JB		 1282 IWL_WARNING("%s on ra = %pM tid = %d\n",
1283 __func__, ra, tid);
30e553e3
TW		 1284
1285 sta_id = iwl_find_station(priv, ra);
1286 if (sta_id == IWL_INVALID_STATION)
1287 return -ENXIO;
1288
1289 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1290 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1291 return -ENXIO;
1292 }
1293
1294 txq_id = iwl_txq_ctx_activate_free(priv);
1295 if (txq_id == -1)
1296 return -ENXIO;
1297
1298 spin_lock_irqsave(&priv->sta_lock, flags);
1299 tid_data = &priv->stations[sta_id].tid[tid];
1300 *ssn = SEQ_TO_SN(tid_data->seq_number);
1301 tid_data->agg.txq_id = txq_id;
1302 spin_unlock_irqrestore(&priv->sta_lock, flags);
1303
1304 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1305 sta_id, tid, *ssn);
1306 if (ret)
1307 return ret;
1308
1309 if (tid_data->tfds_in_queue == 0) {
1310 printk(KERN_ERR "HW queue is empty\n");
1311 tid_data->agg.state = IWL_AGG_ON;
1312 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1313 } else {
1314 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1315 tid_data->tfds_in_queue);
1316 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1317 }
1318 return ret;
1319}
1320EXPORT_SYMBOL(iwl_tx_agg_start);
1321
1322int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1323{
1324 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1325 struct iwl_tid_data *tid_data;
1326 int ret, write_ptr, read_ptr;
1327 unsigned long flags;
30e553e3
TW		 1328
1329 if (!ra) {
1330 IWL_ERROR("ra = NULL\n");
1331 return -EINVAL;
1332 }
1333
1334 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1335 tx_fifo_id = default_tid_to_tx_fifo[tid];
1336 else
1337 return -EINVAL;
1338
1339 sta_id = iwl_find_station(priv, ra);
1340
1341 if (sta_id == IWL_INVALID_STATION)
1342 return -ENXIO;
1343
1344 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1345 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1346
1347 tid_data = &priv->stations[sta_id].tid[tid];
1348 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1349 txq_id = tid_data->agg.txq_id;
1350 write_ptr = priv->txq[txq_id].q.write_ptr;
1351 read_ptr = priv->txq[txq_id].q.read_ptr;
1352
1353 /* The queue is not empty */
1354 if (write_ptr != read_ptr) {
1355 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1356 priv->stations[sta_id].tid[tid].agg.state =
1357 IWL_EMPTYING_HW_QUEUE_DELBA;
1358 return 0;
1359 }
1360
1361 IWL_DEBUG_HT("HW queue is empty\n");
1362 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1363
1364 spin_lock_irqsave(&priv->lock, flags);
1365 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1366 tx_fifo_id);
1367 spin_unlock_irqrestore(&priv->lock, flags);
1368
1369 if (ret)
1370 return ret;
1371
1372 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1373
1374 return 0;
1375}
1376EXPORT_SYMBOL(iwl_tx_agg_stop);
1377
1378int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1379{
1380 struct iwl_queue *q = &priv->txq[txq_id].q;
1381 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1382 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1383
1384 switch (priv->stations[sta_id].tid[tid].agg.state) {
1385 case IWL_EMPTYING_HW_QUEUE_DELBA:
1386 /* We are reclaiming the last packet of the */
1387 /* aggregated HW queue */
1388 if (txq_id == tid_data->agg.txq_id &&
1389 q->read_ptr == q->write_ptr) {
1390 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1391 int tx_fifo = default_tid_to_tx_fifo[tid];
1392 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1393 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1394 ssn, tx_fifo);
1395 tid_data->agg.state = IWL_AGG_OFF;
1396 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1397 }
1398 break;
1399 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1400 /* We are reclaiming the last packet of the queue */
1401 if (tid_data->tfds_in_queue == 0) {
1402 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1403 tid_data->agg.state = IWL_AGG_ON;
1404 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1405 }
1406 break;
1407 }
1408 return 0;
1409}
1410EXPORT_SYMBOL(iwl_txq_check_empty);
30e553e3 1411
653fa4a0
EG		 1412/**
1413 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1414 *
1415 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1416 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1417 */
1418static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1419 struct iwl_ht_agg *agg,
1420 struct iwl_compressed_ba_resp *ba_resp)
1421
1422{
1423 int i, sh, ack;
1424 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1425 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1426 u64 bitmap;
1427 int successes = 0;
1428 struct ieee80211_tx_info *info;
1429
1430 if (unlikely(!agg->wait_for_ba)) {
1431 IWL_ERROR("Received BA when not expected\n");
1432 return -EINVAL;
1433 }
1434
1435 /* Mark that the expected block-ack response arrived */
1436 agg->wait_for_ba = 0;
1437 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1438
1439 /* Calculate shift to align block-ack bits with our Tx window bits */
1440 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
1441 if (sh < 0) /* tbw something is wrong with indices */
1442 sh += 0x100;
1443
1444 /* don't use 64-bit values for now */
1445 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1446
1447 if (agg->frame_count > (64 - sh)) {
1448 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1449 return -1;
1450 }
1451
1452 /* check for success or failure according to the
1453 * transmitted bitmap and block-ack bitmap */
1454 bitmap &= agg->bitmap;
1455
1456 /* For each frame attempted in aggregation,
1457 * update driver's record of tx frame's status. */
1458 for (i = 0; i < agg->frame_count ; i++) {
4aa41f12 1459 ack = bitmap & (1ULL << i);
653fa4a0
EG		 1460 successes += !!ack;
1461 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1462 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
1463 agg->start_idx + i);
1464 }
1465
1466 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1467 memset(&info->status, 0, sizeof(info->status));
1468 info->flags = IEEE80211_TX_STAT_ACK;
1469 info->flags |= IEEE80211_TX_STAT_AMPDU;
1470 info->status.ampdu_ack_map = successes;
1471 info->status.ampdu_ack_len = agg->frame_count;
1472 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1473
1474 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1475
1476 return 0;
1477}
1478
1479/**
1480 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1481 *
1482 * Handles block-acknowledge notification from device, which reports success
1483 * of frames sent via aggregation.
1484 */
1485void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1486 struct iwl_rx_mem_buffer *rxb)
1487{
1488 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1489 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1490 int index;
1491 struct iwl_tx_queue *txq = NULL;
1492 struct iwl_ht_agg *agg;
653fa4a0
EG		 1493
1494 /* "flow" corresponds to Tx queue */
1495 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1496
1497 /* "ssn" is start of block-ack Tx window, corresponds to index
1498 * (in Tx queue's circular buffer) of first TFD/frame in window */
1499 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1500
1501 if (scd_flow >= priv->hw_params.max_txq_num) {
6f147926 1502 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
653fa4a0
EG		 1503 return;
1504 }
1505
1506 txq = &priv->txq[scd_flow];
1507 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
1508
1509 /* Find index just before block-ack window */
1510 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1511
1512 /* TODO: Need to get this copy more safely - now good for debug */
1513
e174961c 1514 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %pM, "
653fa4a0
EG		 1515 "sta_id = %d\n",
1516 agg->wait_for_ba,
e174961c 1517 (u8 *) &ba_resp->sta_addr_lo32,
653fa4a0
EG		 1518 ba_resp->sta_id);
1519 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1520 "%d, scd_ssn = %d\n",
1521 ba_resp->tid,
1522 ba_resp->seq_ctl,
1523 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1524 ba_resp->scd_flow,
1525 ba_resp->scd_ssn);
1526 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1527 agg->start_idx,
1528 (unsigned long long)agg->bitmap);
1529
1530 /* Update driver's record of ACK vs. not for each frame in window */
1531 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1532
1533 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1534 * block-ack window (we assume that they've been successfully
1535 * transmitted ... if not, it's too late anyway). */
1536 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1537 /* calculate mac80211 ampdu sw queue to wake */
1538 int ampdu_q =
1539 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
1540 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1541 priv->stations[ba_resp->sta_id].
1542 tid[ba_resp->tid].tfds_in_queue -= freed;
1543 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1544 priv->mac80211_registered &&
1545 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
1546 ieee80211_wake_queue(priv->hw, ampdu_q);
1547
1548 iwl_txq_check_empty(priv, ba_resp->sta_id,
1549 ba_resp->tid, scd_flow);
1550 }
1551}
1552EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1553
994d31f7 1554#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW		 1555#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1556
1557const char *iwl_get_tx_fail_reason(u32 status)
1558{
1559 switch (status & TX_STATUS_MSK) {
1560 case TX_STATUS_SUCCESS:
1561 return "SUCCESS";
1562 TX_STATUS_ENTRY(SHORT_LIMIT);
1563 TX_STATUS_ENTRY(LONG_LIMIT);
1564 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1565 TX_STATUS_ENTRY(MGMNT_ABORT);
1566 TX_STATUS_ENTRY(NEXT_FRAG);
1567 TX_STATUS_ENTRY(LIFE_EXPIRE);
1568 TX_STATUS_ENTRY(DEST_PS);
1569 TX_STATUS_ENTRY(ABORTED);
1570 TX_STATUS_ENTRY(BT_RETRY);
1571 TX_STATUS_ENTRY(STA_INVALID);
1572 TX_STATUS_ENTRY(FRAG_DROPPED);
1573 TX_STATUS_ENTRY(TID_DISABLE);
1574 TX_STATUS_ENTRY(FRAME_FLUSHED);
1575 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1576 TX_STATUS_ENTRY(TX_LOCKED);
1577 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1578 }
1579
1580 return "UNKNOWN";
1581}
1582EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1583#endif /* CONFIG_IWLWIFI_DEBUG */
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