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Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
43 | #include <net/ieee80211_radiotap.h> | |
7e272fcf | 44 | #include <net/lib80211.h> |
b481de9c ZY |
45 | #include <net/mac80211.h> |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwl3945" |
50 | ||
600c0e11 | 51 | #include "iwl-commands.h" |
b481de9c | 52 | #include "iwl-3945.h" |
bddadf86 | 53 | #include "iwl-3945-fh.h" |
b481de9c | 54 | #include "iwl-helpers.h" |
5747d47f | 55 | #include "iwl-core.h" |
d20b3c65 | 56 | #include "iwl-dev.h" |
b481de9c | 57 | |
4a8a4322 | 58 | static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 59 | struct iwl3945_tx_queue *txq); |
416e1438 | 60 | |
b481de9c ZY |
61 | /****************************************************************************** |
62 | * | |
63 | * module boiler plate | |
64 | * | |
65 | ******************************************************************************/ | |
66 | ||
67 | /* module parameters */ | |
6440adb5 | 68 | static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */ |
95aa194a | 69 | static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */ |
6440adb5 | 70 | static int iwl3945_param_disable; /* def: 0 = enable radio */ |
9fbab516 | 71 | static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */ |
6440adb5 | 72 | int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */ |
dfe7d458 | 73 | int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */ |
b481de9c ZY |
74 | |
75 | /* | |
76 | * module name, copyright, version, etc. | |
b481de9c ZY |
77 | */ |
78 | ||
79 | #define DRV_DESCRIPTION \ | |
80 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
81 | ||
c8b0e6e1 | 82 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
83 | #define VD "d" |
84 | #else | |
85 | #define VD | |
86 | #endif | |
87 | ||
c8b0e6e1 | 88 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
89 | #define VS "s" |
90 | #else | |
91 | #define VS | |
92 | #endif | |
93 | ||
eaa686c3 | 94 | #define IWL39_VERSION "1.2.26k" VD VS |
eb7ae89c | 95 | #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation" |
a7b75207 | 96 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
eaa686c3 | 97 | #define DRV_VERSION IWL39_VERSION |
b481de9c | 98 | |
b481de9c ZY |
99 | |
100 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
101 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 102 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
103 | MODULE_LICENSE("GPL"); |
104 | ||
8318d78a | 105 | static const struct ieee80211_supported_band *iwl3945_get_band( |
4a8a4322 | 106 | struct iwl_priv *priv, enum ieee80211_band band) |
b481de9c | 107 | { |
8318d78a | 108 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
109 | } |
110 | ||
b481de9c ZY |
111 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
112 | * DMA services | |
113 | * | |
114 | * Theory of operation | |
115 | * | |
6440adb5 BC |
116 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
117 | * of buffer descriptors, each of which points to one or more data buffers for | |
118 | * the device to read from or fill. Driver and device exchange status of each | |
119 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
120 | * entries in each circular buffer, to protect against confusing empty and full | |
121 | * queue states. | |
122 | * | |
123 | * The device reads or writes the data in the queues via the device's several | |
124 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
125 | * |
126 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
127 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
128 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
129 | * Tx queue resumed. | |
130 | * | |
6440adb5 BC |
131 | * The 3945 operates with six queues: One receive queue, one transmit queue |
132 | * (#4) for sending commands to the device firmware, and four transmit queues | |
133 | * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused. | |
b481de9c ZY |
134 | ***************************************************/ |
135 | ||
d20b3c65 | 136 | int iwl3945_x2_queue_used(const struct iwl_queue *q, int i) |
b481de9c | 137 | { |
fc4b6853 TW |
138 | return q->write_ptr > q->read_ptr ? |
139 | (i >= q->read_ptr && i < q->write_ptr) : | |
140 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
141 | } |
142 | ||
6440adb5 BC |
143 | /** |
144 | * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes | |
145 | */ | |
4a8a4322 | 146 | static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
b481de9c ZY |
147 | int count, int slots_num, u32 id) |
148 | { | |
149 | q->n_bd = count; | |
150 | q->n_window = slots_num; | |
151 | q->id = id; | |
152 | ||
c54b679d TW |
153 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
154 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
155 | BUG_ON(!is_power_of_2(count)); |
156 | ||
157 | /* slots_num must be power-of-two size, otherwise | |
158 | * get_cmd_index is broken. */ | |
159 | BUG_ON(!is_power_of_2(slots_num)); | |
160 | ||
161 | q->low_mark = q->n_window / 4; | |
162 | if (q->low_mark < 4) | |
163 | q->low_mark = 4; | |
164 | ||
165 | q->high_mark = q->n_window / 8; | |
166 | if (q->high_mark < 2) | |
167 | q->high_mark = 2; | |
168 | ||
fc4b6853 | 169 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
170 | |
171 | return 0; | |
172 | } | |
173 | ||
6440adb5 BC |
174 | /** |
175 | * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
176 | */ | |
4a8a4322 | 177 | static int iwl3945_tx_queue_alloc(struct iwl_priv *priv, |
bb8c093b | 178 | struct iwl3945_tx_queue *txq, u32 id) |
b481de9c ZY |
179 | { |
180 | struct pci_dev *dev = priv->pci_dev; | |
181 | ||
6440adb5 BC |
182 | /* Driver private data, only for Tx (not command) queues, |
183 | * not shared with device. */ | |
b481de9c ZY |
184 | if (id != IWL_CMD_QUEUE_NUM) { |
185 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
186 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
187 | if (!txq->txb) { | |
01ebd063 | 188 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
189 | "structures failed\n"); |
190 | goto error; | |
191 | } | |
192 | } else | |
193 | txq->txb = NULL; | |
194 | ||
6440adb5 BC |
195 | /* Circular buffer of transmit frame descriptors (TFDs), |
196 | * shared with device */ | |
b481de9c ZY |
197 | txq->bd = pci_alloc_consistent(dev, |
198 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
199 | &txq->q.dma_addr); | |
200 | ||
201 | if (!txq->bd) { | |
202 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
203 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
204 | goto error; | |
205 | } | |
206 | txq->q.id = id; | |
207 | ||
208 | return 0; | |
209 | ||
210 | error: | |
3ac7f146 TW |
211 | kfree(txq->txb); |
212 | txq->txb = NULL; | |
b481de9c ZY |
213 | |
214 | return -ENOMEM; | |
215 | } | |
216 | ||
6440adb5 BC |
217 | /** |
218 | * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue | |
219 | */ | |
4a8a4322 | 220 | int iwl3945_tx_queue_init(struct iwl_priv *priv, |
bb8c093b | 221 | struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id) |
b481de9c ZY |
222 | { |
223 | struct pci_dev *dev = priv->pci_dev; | |
224 | int len; | |
225 | int rc = 0; | |
226 | ||
6440adb5 BC |
227 | /* |
228 | * Alloc buffer array for commands (Tx or other types of commands). | |
229 | * For the command queue (#4), allocate command space + one big | |
230 | * command for scan, since scan command is very huge; the system will | |
231 | * not have two scans at the same time, so only one is needed. | |
232 | * For data Tx queues (all other queues), no super-size command | |
233 | * space is needed. | |
234 | */ | |
bb8c093b | 235 | len = sizeof(struct iwl3945_cmd) * slots_num; |
b481de9c ZY |
236 | if (txq_id == IWL_CMD_QUEUE_NUM) |
237 | len += IWL_MAX_SCAN_SIZE; | |
238 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
239 | if (!txq->cmd) | |
240 | return -ENOMEM; | |
241 | ||
6440adb5 | 242 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 243 | rc = iwl3945_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
244 | if (rc) { |
245 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
246 | ||
247 | return -ENOMEM; | |
248 | } | |
249 | txq->need_update = 0; | |
250 | ||
251 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 252 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 253 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
6440adb5 BC |
254 | |
255 | /* Initialize queue high/low-water, head/tail indexes */ | |
bb8c093b | 256 | iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 257 | |
6440adb5 | 258 | /* Tell device where to find queue, enable DMA channel. */ |
bb8c093b | 259 | iwl3945_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
260 | |
261 | return 0; | |
262 | } | |
263 | ||
264 | /** | |
bb8c093b | 265 | * iwl3945_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
266 | * @txq: Transmit queue to deallocate. |
267 | * | |
268 | * Empty queue by removing and destroying all BD's. | |
6440adb5 BC |
269 | * Free all buffers. |
270 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 271 | */ |
4a8a4322 | 272 | void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq) |
b481de9c | 273 | { |
d20b3c65 | 274 | struct iwl_queue *q = &txq->q; |
b481de9c ZY |
275 | struct pci_dev *dev = priv->pci_dev; |
276 | int len; | |
277 | ||
278 | if (q->n_bd == 0) | |
279 | return; | |
280 | ||
281 | /* first, empty all BD's */ | |
fc4b6853 | 282 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 283 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 284 | iwl3945_hw_txq_free_tfd(priv, txq); |
b481de9c | 285 | |
bb8c093b | 286 | len = sizeof(struct iwl3945_cmd) * q->n_window; |
b481de9c ZY |
287 | if (q->id == IWL_CMD_QUEUE_NUM) |
288 | len += IWL_MAX_SCAN_SIZE; | |
289 | ||
6440adb5 | 290 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
291 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
292 | ||
6440adb5 | 293 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 294 | if (txq->q.n_bd) |
bb8c093b | 295 | pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) * |
b481de9c ZY |
296 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
297 | ||
6440adb5 | 298 | /* De-alloc array of per-TFD driver data */ |
3ac7f146 TW |
299 | kfree(txq->txb); |
300 | txq->txb = NULL; | |
b481de9c | 301 | |
6440adb5 | 302 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
303 | memset(txq, 0, sizeof(*txq)); |
304 | } | |
305 | ||
b481de9c | 306 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 307 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
308 | * the functionality provided here |
309 | */ | |
310 | ||
311 | /**************************************************************/ | |
01ebd063 | 312 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 BC |
313 | /** |
314 | * iwl3945_remove_station - Remove driver's knowledge of station. | |
315 | * | |
316 | * NOTE: This does not remove station from device's station table. | |
317 | */ | |
4a8a4322 | 318 | static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
319 | { |
320 | int index = IWL_INVALID_STATION; | |
321 | int i; | |
322 | unsigned long flags; | |
323 | ||
324 | spin_lock_irqsave(&priv->sta_lock, flags); | |
325 | ||
326 | if (is_ap) | |
327 | index = IWL_AP_ID; | |
328 | else if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 329 | index = priv->hw_params.bcast_sta_id; |
b481de9c | 330 | else |
3832ec9d | 331 | for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) |
f2c7e521 AK |
332 | if (priv->stations_39[i].used && |
333 | !compare_ether_addr(priv->stations_39[i].sta.sta.addr, | |
b481de9c ZY |
334 | addr)) { |
335 | index = i; | |
336 | break; | |
337 | } | |
338 | ||
339 | if (unlikely(index == IWL_INVALID_STATION)) | |
340 | goto out; | |
341 | ||
f2c7e521 AK |
342 | if (priv->stations_39[index].used) { |
343 | priv->stations_39[index].used = 0; | |
b481de9c ZY |
344 | priv->num_stations--; |
345 | } | |
346 | ||
347 | BUG_ON(priv->num_stations < 0); | |
348 | ||
349 | out: | |
350 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
351 | return 0; | |
352 | } | |
556f8db7 | 353 | #endif |
6440adb5 BC |
354 | |
355 | /** | |
356 | * iwl3945_clear_stations_table - Clear the driver's station table | |
357 | * | |
358 | * NOTE: This does not clear or otherwise alter the device's station table. | |
359 | */ | |
4a8a4322 | 360 | static void iwl3945_clear_stations_table(struct iwl_priv *priv) |
b481de9c ZY |
361 | { |
362 | unsigned long flags; | |
363 | ||
364 | spin_lock_irqsave(&priv->sta_lock, flags); | |
365 | ||
366 | priv->num_stations = 0; | |
f2c7e521 | 367 | memset(priv->stations_39, 0, sizeof(priv->stations_39)); |
b481de9c ZY |
368 | |
369 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
370 | } | |
371 | ||
6440adb5 BC |
372 | /** |
373 | * iwl3945_add_station - Add station to station tables in driver and device | |
374 | */ | |
4a8a4322 | 375 | u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags) |
b481de9c ZY |
376 | { |
377 | int i; | |
378 | int index = IWL_INVALID_STATION; | |
bb8c093b | 379 | struct iwl3945_station_entry *station; |
b481de9c | 380 | unsigned long flags_spin; |
c14c521e | 381 | u8 rate; |
b481de9c ZY |
382 | |
383 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
384 | if (is_ap) | |
385 | index = IWL_AP_ID; | |
386 | else if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 387 | index = priv->hw_params.bcast_sta_id; |
b481de9c | 388 | else |
3832ec9d | 389 | for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) { |
f2c7e521 | 390 | if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr, |
b481de9c ZY |
391 | addr)) { |
392 | index = i; | |
393 | break; | |
394 | } | |
395 | ||
f2c7e521 | 396 | if (!priv->stations_39[i].used && |
b481de9c ZY |
397 | index == IWL_INVALID_STATION) |
398 | index = i; | |
399 | } | |
400 | ||
01ebd063 | 401 | /* These two conditions has the same outcome but keep them separate |
b481de9c ZY |
402 | since they have different meaning */ |
403 | if (unlikely(index == IWL_INVALID_STATION)) { | |
404 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
405 | return index; | |
406 | } | |
407 | ||
f2c7e521 AK |
408 | if (priv->stations_39[index].used && |
409 | !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) { | |
b481de9c ZY |
410 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
411 | return index; | |
412 | } | |
413 | ||
e174961c | 414 | IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr); |
f2c7e521 | 415 | station = &priv->stations_39[index]; |
b481de9c ZY |
416 | station->used = 1; |
417 | priv->num_stations++; | |
418 | ||
6440adb5 | 419 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 420 | memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd)); |
b481de9c ZY |
421 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
422 | station->sta.mode = 0; | |
423 | station->sta.sta.sta_id = index; | |
424 | station->sta.station_flags = 0; | |
425 | ||
8318d78a | 426 | if (priv->band == IEEE80211_BAND_5GHZ) |
69946333 TW |
427 | rate = IWL_RATE_6M_PLCP; |
428 | else | |
429 | rate = IWL_RATE_1M_PLCP; | |
c14c521e ZY |
430 | |
431 | /* Turn on both antennas for the station... */ | |
432 | station->sta.rate_n_flags = | |
bb8c093b | 433 | iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK); |
c14c521e | 434 | |
b481de9c | 435 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
6440adb5 BC |
436 | |
437 | /* Add station to device's station table */ | |
bb8c093b | 438 | iwl3945_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
439 | return index; |
440 | ||
441 | } | |
442 | ||
443 | /*************** DRIVER STATUS FUNCTIONS *****/ | |
444 | ||
4a8a4322 | 445 | static inline int iwl3945_is_ready(struct iwl_priv *priv) |
b481de9c ZY |
446 | { |
447 | /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are | |
448 | * set but EXIT_PENDING is not */ | |
449 | return test_bit(STATUS_READY, &priv->status) && | |
450 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) && | |
451 | !test_bit(STATUS_EXIT_PENDING, &priv->status); | |
452 | } | |
453 | ||
4a8a4322 | 454 | static inline int iwl3945_is_alive(struct iwl_priv *priv) |
b481de9c ZY |
455 | { |
456 | return test_bit(STATUS_ALIVE, &priv->status); | |
457 | } | |
458 | ||
4a8a4322 | 459 | static inline int iwl3945_is_init(struct iwl_priv *priv) |
b481de9c ZY |
460 | { |
461 | return test_bit(STATUS_INIT, &priv->status); | |
462 | } | |
463 | ||
4a8a4322 | 464 | static inline int iwl3945_is_rfkill_sw(struct iwl_priv *priv) |
80fcc9e2 AG |
465 | { |
466 | return test_bit(STATUS_RF_KILL_SW, &priv->status); | |
467 | } | |
468 | ||
4a8a4322 | 469 | static inline int iwl3945_is_rfkill_hw(struct iwl_priv *priv) |
80fcc9e2 AG |
470 | { |
471 | return test_bit(STATUS_RF_KILL_HW, &priv->status); | |
472 | } | |
473 | ||
4a8a4322 | 474 | static inline int iwl3945_is_rfkill(struct iwl_priv *priv) |
b481de9c | 475 | { |
80fcc9e2 AG |
476 | return iwl3945_is_rfkill_hw(priv) || |
477 | iwl3945_is_rfkill_sw(priv); | |
b481de9c ZY |
478 | } |
479 | ||
4a8a4322 | 480 | static inline int iwl3945_is_ready_rf(struct iwl_priv *priv) |
b481de9c ZY |
481 | { |
482 | ||
bb8c093b | 483 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
484 | return 0; |
485 | ||
bb8c093b | 486 | return iwl3945_is_ready(priv); |
b481de9c ZY |
487 | } |
488 | ||
489 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
490 | ||
c3056065 | 491 | #define IWL_CMD(x) case x: return #x |
b481de9c ZY |
492 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) |
493 | ||
494 | /** | |
bb8c093b | 495 | * iwl3945_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
496 | * @priv: device private data point |
497 | * @cmd: a point to the ucode command structure | |
498 | * | |
499 | * The function returns < 0 values to indicate the operation is | |
500 | * failed. On success, it turns the index (> 0) of command in the | |
501 | * command queue. | |
502 | */ | |
4a8a4322 | 503 | static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 504 | { |
f2c7e521 | 505 | struct iwl3945_tx_queue *txq = &priv->txq39[IWL_CMD_QUEUE_NUM]; |
d20b3c65 | 506 | struct iwl_queue *q = &txq->q; |
bb8c093b | 507 | struct iwl3945_tfd_frame *tfd; |
b481de9c | 508 | u32 *control_flags; |
bb8c093b | 509 | struct iwl3945_cmd *out_cmd; |
b481de9c ZY |
510 | u32 idx; |
511 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
512 | dma_addr_t phys_addr; | |
513 | int pad; | |
514 | u16 count; | |
515 | int ret; | |
516 | unsigned long flags; | |
517 | ||
518 | /* If any of the command structures end up being larger than | |
519 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
520 | * we will need to increase the size of the TFD entries */ | |
d20b3c65 | 521 | BUG_ON((fix_size > TFD39_MAX_PAYLOAD_SIZE) && |
b481de9c ZY |
522 | !(cmd->meta.flags & CMD_SIZE_HUGE)); |
523 | ||
c342a1b9 GG |
524 | |
525 | if (iwl3945_is_rfkill(priv)) { | |
526 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
527 | return -EIO; | |
528 | } | |
529 | ||
d20b3c65 | 530 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
531 | IWL_ERROR("No space for Tx\n"); |
532 | return -ENOSPC; | |
533 | } | |
534 | ||
535 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
536 | ||
fc4b6853 | 537 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
538 | memset(tfd, 0, sizeof(*tfd)); |
539 | ||
540 | control_flags = (u32 *) tfd; | |
541 | ||
fc4b6853 | 542 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
543 | out_cmd = &txq->cmd[idx]; |
544 | ||
545 | out_cmd->hdr.cmd = cmd->id; | |
546 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
547 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
548 | ||
549 | /* At this point, the out_cmd now has all of the incoming cmd | |
550 | * information */ | |
551 | ||
552 | out_cmd->hdr.flags = 0; | |
553 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 554 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c | 555 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
600c0e11 | 556 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
b481de9c ZY |
557 | |
558 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
bb8c093b CH |
559 | offsetof(struct iwl3945_cmd, hdr); |
560 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | |
b481de9c ZY |
561 | |
562 | pad = U32_PAD(cmd->len); | |
563 | count = TFD_CTL_COUNT_GET(*control_flags); | |
564 | *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad); | |
565 | ||
566 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
567 | "%d bytes at %d[%d]:%d\n", | |
568 | get_cmd_string(out_cmd->hdr.cmd), | |
569 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 570 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
571 | |
572 | txq->need_update = 1; | |
6440adb5 BC |
573 | |
574 | /* Increment and update queue's write index */ | |
c54b679d | 575 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 576 | ret = iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
577 | |
578 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
579 | return ret ? ret : idx; | |
580 | } | |
581 | ||
4a8a4322 | 582 | static int iwl3945_send_cmd_async(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
583 | { |
584 | int ret; | |
585 | ||
586 | BUG_ON(!(cmd->meta.flags & CMD_ASYNC)); | |
587 | ||
588 | /* An asynchronous command can not expect an SKB to be set. */ | |
589 | BUG_ON(cmd->meta.flags & CMD_WANT_SKB); | |
590 | ||
591 | /* An asynchronous command MUST have a callback. */ | |
592 | BUG_ON(!cmd->meta.u.callback); | |
593 | ||
594 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
595 | return -EBUSY; | |
596 | ||
bb8c093b | 597 | ret = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c | 598 | if (ret < 0) { |
bb8c093b | 599 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
600 | get_cmd_string(cmd->id), ret); |
601 | return ret; | |
602 | } | |
603 | return 0; | |
604 | } | |
605 | ||
4a8a4322 | 606 | static int iwl3945_send_cmd_sync(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
607 | { |
608 | int cmd_idx; | |
609 | int ret; | |
b481de9c ZY |
610 | |
611 | BUG_ON(cmd->meta.flags & CMD_ASYNC); | |
612 | ||
613 | /* A synchronous command can not have a callback set. */ | |
614 | BUG_ON(cmd->meta.u.callback != NULL); | |
615 | ||
e5472978 | 616 | if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) { |
b481de9c ZY |
617 | IWL_ERROR("Error sending %s: Already sending a host command\n", |
618 | get_cmd_string(cmd->id)); | |
e5472978 TW |
619 | ret = -EBUSY; |
620 | goto out; | |
b481de9c ZY |
621 | } |
622 | ||
623 | set_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
624 | ||
625 | if (cmd->meta.flags & CMD_WANT_SKB) | |
626 | cmd->meta.source = &cmd->meta; | |
627 | ||
bb8c093b | 628 | cmd_idx = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c ZY |
629 | if (cmd_idx < 0) { |
630 | ret = cmd_idx; | |
bb8c093b | 631 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
632 | get_cmd_string(cmd->id), ret); |
633 | goto out; | |
634 | } | |
635 | ||
636 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
637 | !test_bit(STATUS_HCMD_ACTIVE, &priv->status), | |
638 | HOST_COMPLETE_TIMEOUT); | |
639 | if (!ret) { | |
640 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) { | |
641 | IWL_ERROR("Error sending %s: time out after %dms.\n", | |
642 | get_cmd_string(cmd->id), | |
643 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
644 | ||
645 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
646 | ret = -ETIMEDOUT; | |
647 | goto cancel; | |
648 | } | |
649 | } | |
650 | ||
651 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
652 | IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n", | |
653 | get_cmd_string(cmd->id)); | |
654 | ret = -ECANCELED; | |
655 | goto fail; | |
656 | } | |
657 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { | |
658 | IWL_DEBUG_INFO("Command %s failed: FW Error\n", | |
659 | get_cmd_string(cmd->id)); | |
660 | ret = -EIO; | |
661 | goto fail; | |
662 | } | |
663 | if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) { | |
664 | IWL_ERROR("Error: Response NULL in '%s'\n", | |
665 | get_cmd_string(cmd->id)); | |
666 | ret = -EIO; | |
73e1a65d | 667 | goto cancel; |
b481de9c ZY |
668 | } |
669 | ||
670 | ret = 0; | |
671 | goto out; | |
672 | ||
673 | cancel: | |
674 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
bb8c093b | 675 | struct iwl3945_cmd *qcmd; |
b481de9c ZY |
676 | |
677 | /* Cancel the CMD_WANT_SKB flag for the cmd in the | |
678 | * TX cmd queue. Otherwise in case the cmd comes | |
679 | * in later, it will possibly set an invalid | |
680 | * address (cmd->meta.source). */ | |
f2c7e521 | 681 | qcmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; |
b481de9c ZY |
682 | qcmd->meta.flags &= ~CMD_WANT_SKB; |
683 | } | |
684 | fail: | |
685 | if (cmd->meta.u.skb) { | |
686 | dev_kfree_skb_any(cmd->meta.u.skb); | |
687 | cmd->meta.u.skb = NULL; | |
688 | } | |
689 | out: | |
e5472978 | 690 | clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status); |
b481de9c ZY |
691 | return ret; |
692 | } | |
693 | ||
4a8a4322 | 694 | int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 695 | { |
b481de9c | 696 | if (cmd->meta.flags & CMD_ASYNC) |
bb8c093b | 697 | return iwl3945_send_cmd_async(priv, cmd); |
b481de9c | 698 | |
bb8c093b | 699 | return iwl3945_send_cmd_sync(priv, cmd); |
b481de9c ZY |
700 | } |
701 | ||
4a8a4322 | 702 | int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data) |
b481de9c | 703 | { |
bb8c093b | 704 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
705 | .id = id, |
706 | .len = len, | |
707 | .data = data, | |
708 | }; | |
709 | ||
bb8c093b | 710 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
711 | } |
712 | ||
4a8a4322 | 713 | static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val) |
b481de9c | 714 | { |
bb8c093b | 715 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
716 | .id = id, |
717 | .len = sizeof(val), | |
718 | .data = &val, | |
719 | }; | |
720 | ||
bb8c093b | 721 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
722 | } |
723 | ||
4a8a4322 | 724 | int iwl3945_send_statistics_request(struct iwl_priv *priv) |
b481de9c | 725 | { |
bb8c093b | 726 | return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0); |
b481de9c ZY |
727 | } |
728 | ||
b481de9c | 729 | /** |
bb8c093b | 730 | * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON |
8318d78a JB |
731 | * @band: 2.4 or 5 GHz band |
732 | * @channel: Any channel valid for the requested band | |
b481de9c | 733 | |
8318d78a | 734 | * In addition to setting the staging RXON, priv->band is also set. |
b481de9c ZY |
735 | * |
736 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
8318d78a | 737 | * in the staging RXON flag structure based on the band |
b481de9c | 738 | */ |
4a8a4322 | 739 | static int iwl3945_set_rxon_channel(struct iwl_priv *priv, |
8318d78a JB |
740 | enum ieee80211_band band, |
741 | u16 channel) | |
b481de9c | 742 | { |
8318d78a | 743 | if (!iwl3945_get_channel_info(priv, band, channel)) { |
b481de9c | 744 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
8318d78a | 745 | channel, band); |
b481de9c ZY |
746 | return -EINVAL; |
747 | } | |
748 | ||
f2c7e521 | 749 | if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) && |
8318d78a | 750 | (priv->band == band)) |
b481de9c ZY |
751 | return 0; |
752 | ||
f2c7e521 | 753 | priv->staging39_rxon.channel = cpu_to_le16(channel); |
8318d78a | 754 | if (band == IEEE80211_BAND_5GHZ) |
f2c7e521 | 755 | priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
b481de9c | 756 | else |
f2c7e521 | 757 | priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
b481de9c | 758 | |
8318d78a | 759 | priv->band = band; |
b481de9c | 760 | |
8318d78a | 761 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); |
b481de9c ZY |
762 | |
763 | return 0; | |
764 | } | |
765 | ||
766 | /** | |
bb8c093b | 767 | * iwl3945_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
768 | * |
769 | * NOTE: This is really only useful during development and can eventually | |
770 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
771 | * making changes | |
772 | */ | |
4a8a4322 | 773 | static int iwl3945_check_rxon_cmd(struct iwl_priv *priv) |
b481de9c ZY |
774 | { |
775 | int error = 0; | |
776 | int counter = 1; | |
f2c7e521 | 777 | struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon; |
b481de9c ZY |
778 | |
779 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
780 | error |= le32_to_cpu(rxon->flags & | |
781 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
782 | RXON_FLG_RADAR_DETECT_MSK)); | |
783 | if (error) | |
784 | IWL_WARNING("check 24G fields %d | %d\n", | |
785 | counter++, error); | |
786 | } else { | |
787 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
788 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
789 | if (error) | |
790 | IWL_WARNING("check 52 fields %d | %d\n", | |
791 | counter++, error); | |
792 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
793 | if (error) | |
794 | IWL_WARNING("check 52 CCK %d | %d\n", | |
795 | counter++, error); | |
796 | } | |
797 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
798 | if (error) | |
799 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
800 | ||
801 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
802 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
803 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
804 | if (error) | |
805 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
806 | ||
807 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
808 | if (error) | |
809 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
810 | ||
811 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
812 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
813 | if (error) | |
814 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
815 | counter++, error); | |
816 | ||
817 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
818 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
819 | if (error) | |
820 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
821 | counter++, error); | |
822 | ||
823 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
824 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
825 | if (error) | |
826 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
827 | counter++, error); | |
828 | ||
829 | if ((rxon->flags & RXON_FLG_DIS_DIV_MSK)) | |
830 | error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK | | |
831 | RXON_FLG_ANT_A_MSK)) == 0); | |
832 | if (error) | |
833 | IWL_WARNING("check antenna %d %d\n", counter++, error); | |
834 | ||
835 | if (error) | |
836 | IWL_WARNING("Tuning to channel %d\n", | |
837 | le16_to_cpu(rxon->channel)); | |
838 | ||
839 | if (error) { | |
bb8c093b | 840 | IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
841 | return -1; |
842 | } | |
843 | return 0; | |
844 | } | |
845 | ||
846 | /** | |
9fbab516 | 847 | * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 848 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 849 | * |
9fbab516 BC |
850 | * If the RXON structure is changing enough to require a new tune, |
851 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
852 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 853 | */ |
4a8a4322 | 854 | static int iwl3945_full_rxon_required(struct iwl_priv *priv) |
b481de9c ZY |
855 | { |
856 | ||
857 | /* These items are only settable from the full RXON command */ | |
5d1e2325 | 858 | if (!(iwl3945_is_associated(priv)) || |
f2c7e521 AK |
859 | compare_ether_addr(priv->staging39_rxon.bssid_addr, |
860 | priv->active39_rxon.bssid_addr) || | |
861 | compare_ether_addr(priv->staging39_rxon.node_addr, | |
862 | priv->active39_rxon.node_addr) || | |
863 | compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr, | |
864 | priv->active39_rxon.wlap_bssid_addr) || | |
865 | (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) || | |
866 | (priv->staging39_rxon.channel != priv->active39_rxon.channel) || | |
867 | (priv->staging39_rxon.air_propagation != | |
868 | priv->active39_rxon.air_propagation) || | |
869 | (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id)) | |
b481de9c ZY |
870 | return 1; |
871 | ||
872 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
873 | * be updated with the RXON_ASSOC command -- however only some | |
874 | * flag transitions are allowed using RXON_ASSOC */ | |
875 | ||
876 | /* Check if we are not switching bands */ | |
f2c7e521 AK |
877 | if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) != |
878 | (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
b481de9c ZY |
879 | return 1; |
880 | ||
881 | /* Check if we are switching association toggle */ | |
f2c7e521 AK |
882 | if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != |
883 | (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
b481de9c ZY |
884 | return 1; |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
4a8a4322 | 889 | static int iwl3945_send_rxon_assoc(struct iwl_priv *priv) |
b481de9c ZY |
890 | { |
891 | int rc = 0; | |
3d24a9f7 | 892 | struct iwl_rx_packet *res = NULL; |
bb8c093b CH |
893 | struct iwl3945_rxon_assoc_cmd rxon_assoc; |
894 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
895 | .id = REPLY_RXON_ASSOC, |
896 | .len = sizeof(rxon_assoc), | |
897 | .meta.flags = CMD_WANT_SKB, | |
898 | .data = &rxon_assoc, | |
899 | }; | |
f2c7e521 AK |
900 | const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon; |
901 | const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon; | |
b481de9c ZY |
902 | |
903 | if ((rxon1->flags == rxon2->flags) && | |
904 | (rxon1->filter_flags == rxon2->filter_flags) && | |
905 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
906 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
907 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
908 | return 0; | |
909 | } | |
910 | ||
f2c7e521 AK |
911 | rxon_assoc.flags = priv->staging39_rxon.flags; |
912 | rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags; | |
913 | rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates; | |
914 | rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates; | |
b481de9c ZY |
915 | rxon_assoc.reserved = 0; |
916 | ||
bb8c093b | 917 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
918 | if (rc) |
919 | return rc; | |
920 | ||
3d24a9f7 | 921 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
922 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
923 | IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n"); | |
924 | rc = -EIO; | |
925 | } | |
926 | ||
927 | priv->alloc_rxb_skb--; | |
928 | dev_kfree_skb_any(cmd.meta.u.skb); | |
929 | ||
930 | return rc; | |
931 | } | |
932 | ||
933 | /** | |
bb8c093b | 934 | * iwl3945_commit_rxon - commit staging_rxon to hardware |
b481de9c | 935 | * |
01ebd063 | 936 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
937 | * the active_rxon structure is updated with the new data. This |
938 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
939 | * a HW tune is required based on the RXON structure changes. | |
940 | */ | |
4a8a4322 | 941 | static int iwl3945_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
942 | { |
943 | /* cast away the const for active_rxon in this function */ | |
f2c7e521 | 944 | struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon; |
b481de9c ZY |
945 | int rc = 0; |
946 | ||
bb8c093b | 947 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
948 | return -1; |
949 | ||
950 | /* always get timestamp with Rx frame */ | |
f2c7e521 | 951 | priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK; |
b481de9c ZY |
952 | |
953 | /* select antenna */ | |
f2c7e521 | 954 | priv->staging39_rxon.flags &= |
b481de9c | 955 | ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); |
f2c7e521 | 956 | priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv); |
b481de9c | 957 | |
a3139c59 | 958 | rc = iwl3945_check_rxon_cmd(priv); |
b481de9c ZY |
959 | if (rc) { |
960 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
961 | return -EINVAL; | |
962 | } | |
963 | ||
964 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 965 | * iwl3945_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 966 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
967 | if (!iwl3945_full_rxon_required(priv)) { |
968 | rc = iwl3945_send_rxon_assoc(priv); | |
b481de9c ZY |
969 | if (rc) { |
970 | IWL_ERROR("Error setting RXON_ASSOC " | |
971 | "configuration (%d).\n", rc); | |
972 | return rc; | |
973 | } | |
974 | ||
f2c7e521 | 975 | memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon)); |
b481de9c ZY |
976 | |
977 | return 0; | |
978 | } | |
979 | ||
980 | /* If we are currently associated and the new config requires | |
981 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
982 | * we must clear the associated from the active configuration | |
983 | * before we apply the new config */ | |
bb8c093b | 984 | if (iwl3945_is_associated(priv) && |
f2c7e521 | 985 | (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
b481de9c ZY |
986 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); |
987 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
988 | ||
bb8c093b CH |
989 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
990 | sizeof(struct iwl3945_rxon_cmd), | |
f2c7e521 | 991 | &priv->active39_rxon); |
b481de9c ZY |
992 | |
993 | /* If the mask clearing failed then we set | |
994 | * active_rxon back to what it was previously */ | |
995 | if (rc) { | |
996 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
997 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
998 | "configuration (%d).\n", rc); | |
999 | return rc; | |
1000 | } | |
b481de9c ZY |
1001 | } |
1002 | ||
1003 | IWL_DEBUG_INFO("Sending RXON\n" | |
1004 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
1005 | "* channel = %d\n" | |
e174961c | 1006 | "* bssid = %pM\n", |
f2c7e521 | 1007 | ((priv->staging39_rxon.filter_flags & |
b481de9c | 1008 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), |
f2c7e521 | 1009 | le16_to_cpu(priv->staging39_rxon.channel), |
e174961c | 1010 | priv->staging_rxon.bssid_addr); |
b481de9c ZY |
1011 | |
1012 | /* Apply the new configuration */ | |
bb8c093b | 1013 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
f2c7e521 | 1014 | sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon); |
b481de9c ZY |
1015 | if (rc) { |
1016 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
1017 | return rc; | |
1018 | } | |
1019 | ||
f2c7e521 | 1020 | memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon)); |
b481de9c | 1021 | |
bb8c093b | 1022 | iwl3945_clear_stations_table(priv); |
556f8db7 | 1023 | |
b481de9c ZY |
1024 | /* If we issue a new RXON command which required a tune then we must |
1025 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 1026 | rc = iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
1027 | if (rc) { |
1028 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
1029 | return rc; | |
1030 | } | |
1031 | ||
1032 | /* Add the broadcast address so we can send broadcast frames */ | |
b5323d36 | 1033 | if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) == |
b481de9c ZY |
1034 | IWL_INVALID_STATION) { |
1035 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
1036 | return -EIO; | |
1037 | } | |
1038 | ||
1039 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
1040 | * add the IWL_AP_ID to the station rate table */ | |
bb8c093b | 1041 | if (iwl3945_is_associated(priv) && |
05c914fe | 1042 | (priv->iw_mode == NL80211_IFTYPE_STATION)) |
f2c7e521 | 1043 | if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0) |
b481de9c ZY |
1044 | == IWL_INVALID_STATION) { |
1045 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
1046 | return -EIO; | |
1047 | } | |
1048 | ||
8318d78a | 1049 | /* Init the hardware's rate fallback order based on the band */ |
b481de9c ZY |
1050 | rc = iwl3945_init_hw_rate_table(priv); |
1051 | if (rc) { | |
1052 | IWL_ERROR("Error setting HW rate table: %02X\n", rc); | |
1053 | return -EIO; | |
1054 | } | |
1055 | ||
1056 | return 0; | |
1057 | } | |
1058 | ||
4a8a4322 | 1059 | static int iwl3945_send_bt_config(struct iwl_priv *priv) |
b481de9c | 1060 | { |
4c897253 | 1061 | struct iwl_bt_cmd bt_cmd = { |
b481de9c ZY |
1062 | .flags = 3, |
1063 | .lead_time = 0xAA, | |
1064 | .max_kill = 1, | |
1065 | .kill_ack_mask = 0, | |
1066 | .kill_cts_mask = 0, | |
1067 | }; | |
1068 | ||
bb8c093b | 1069 | return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
4c897253 | 1070 | sizeof(bt_cmd), &bt_cmd); |
b481de9c ZY |
1071 | } |
1072 | ||
4a8a4322 | 1073 | static int iwl3945_send_scan_abort(struct iwl_priv *priv) |
b481de9c ZY |
1074 | { |
1075 | int rc = 0; | |
3d24a9f7 | 1076 | struct iwl_rx_packet *res; |
bb8c093b | 1077 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
1078 | .id = REPLY_SCAN_ABORT_CMD, |
1079 | .meta.flags = CMD_WANT_SKB, | |
1080 | }; | |
1081 | ||
1082 | /* If there isn't a scan actively going on in the hardware | |
1083 | * then we are in between scan bands and not actually | |
1084 | * actively scanning, so don't send the abort command */ | |
1085 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1086 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1087 | return 0; | |
1088 | } | |
1089 | ||
bb8c093b | 1090 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1091 | if (rc) { |
1092 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1093 | return rc; | |
1094 | } | |
1095 | ||
3d24a9f7 | 1096 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1097 | if (res->u.status != CAN_ABORT_STATUS) { |
1098 | /* The scan abort will return 1 for success or | |
1099 | * 2 for "failure". A failure condition can be | |
1100 | * due to simply not being in an active scan which | |
1101 | * can occur if we send the scan abort before we | |
1102 | * the microcode has notified us that a scan is | |
1103 | * completed. */ | |
1104 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
1105 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1106 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
1107 | } | |
1108 | ||
1109 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1110 | ||
1111 | return rc; | |
1112 | } | |
1113 | ||
4a8a4322 | 1114 | static int iwl3945_card_state_sync_callback(struct iwl_priv *priv, |
bb8c093b | 1115 | struct iwl3945_cmd *cmd, |
b481de9c ZY |
1116 | struct sk_buff *skb) |
1117 | { | |
1118 | return 1; | |
1119 | } | |
1120 | ||
1121 | /* | |
1122 | * CARD_STATE_CMD | |
1123 | * | |
9fbab516 | 1124 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
1125 | * |
1126 | * When in the 'enable' state the card operates as normal. | |
1127 | * When in the 'disable' state, the card enters into a low power mode. | |
1128 | * When in the 'halt' state, the card is shut down and must be fully | |
1129 | * restarted to come back on. | |
1130 | */ | |
4a8a4322 | 1131 | static int iwl3945_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1132 | { |
bb8c093b | 1133 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
1134 | .id = REPLY_CARD_STATE_CMD, |
1135 | .len = sizeof(u32), | |
1136 | .data = &flags, | |
1137 | .meta.flags = meta_flag, | |
1138 | }; | |
1139 | ||
1140 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1141 | cmd.meta.u.callback = iwl3945_card_state_sync_callback; |
b481de9c | 1142 | |
bb8c093b | 1143 | return iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1144 | } |
1145 | ||
4a8a4322 | 1146 | static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv, |
bb8c093b | 1147 | struct iwl3945_cmd *cmd, struct sk_buff *skb) |
b481de9c | 1148 | { |
3d24a9f7 | 1149 | struct iwl_rx_packet *res = NULL; |
b481de9c ZY |
1150 | |
1151 | if (!skb) { | |
1152 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1153 | return 1; | |
1154 | } | |
1155 | ||
3d24a9f7 | 1156 | res = (struct iwl_rx_packet *)skb->data; |
b481de9c ZY |
1157 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1158 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1159 | res->hdr.flags); | |
1160 | return 1; | |
1161 | } | |
1162 | ||
1163 | switch (res->u.add_sta.status) { | |
1164 | case ADD_STA_SUCCESS_MSK: | |
1165 | break; | |
1166 | default: | |
1167 | break; | |
1168 | } | |
1169 | ||
1170 | /* We didn't cache the SKB; let the caller free it */ | |
1171 | return 1; | |
1172 | } | |
1173 | ||
4a8a4322 | 1174 | int iwl3945_send_add_station(struct iwl_priv *priv, |
bb8c093b | 1175 | struct iwl3945_addsta_cmd *sta, u8 flags) |
b481de9c | 1176 | { |
3d24a9f7 | 1177 | struct iwl_rx_packet *res = NULL; |
b481de9c | 1178 | int rc = 0; |
bb8c093b | 1179 | struct iwl3945_host_cmd cmd = { |
b481de9c | 1180 | .id = REPLY_ADD_STA, |
bb8c093b | 1181 | .len = sizeof(struct iwl3945_addsta_cmd), |
b481de9c ZY |
1182 | .meta.flags = flags, |
1183 | .data = sta, | |
1184 | }; | |
1185 | ||
1186 | if (flags & CMD_ASYNC) | |
bb8c093b | 1187 | cmd.meta.u.callback = iwl3945_add_sta_sync_callback; |
b481de9c ZY |
1188 | else |
1189 | cmd.meta.flags |= CMD_WANT_SKB; | |
1190 | ||
bb8c093b | 1191 | rc = iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1192 | |
1193 | if (rc || (flags & CMD_ASYNC)) | |
1194 | return rc; | |
1195 | ||
3d24a9f7 | 1196 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1197 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1198 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1199 | res->hdr.flags); | |
1200 | rc = -EIO; | |
1201 | } | |
1202 | ||
1203 | if (rc == 0) { | |
1204 | switch (res->u.add_sta.status) { | |
1205 | case ADD_STA_SUCCESS_MSK: | |
1206 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1207 | break; | |
1208 | default: | |
1209 | rc = -EIO; | |
1210 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1211 | break; | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | priv->alloc_rxb_skb--; | |
1216 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1217 | ||
1218 | return rc; | |
1219 | } | |
1220 | ||
4a8a4322 | 1221 | static int iwl3945_update_sta_key_info(struct iwl_priv *priv, |
b481de9c ZY |
1222 | struct ieee80211_key_conf *keyconf, |
1223 | u8 sta_id) | |
1224 | { | |
1225 | unsigned long flags; | |
1226 | __le16 key_flags = 0; | |
1227 | ||
1228 | switch (keyconf->alg) { | |
1229 | case ALG_CCMP: | |
1230 | key_flags |= STA_KEY_FLG_CCMP; | |
1231 | key_flags |= cpu_to_le16( | |
1232 | keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
1233 | key_flags &= ~STA_KEY_FLG_INVALID; | |
1234 | break; | |
1235 | case ALG_TKIP: | |
1236 | case ALG_WEP: | |
b481de9c ZY |
1237 | default: |
1238 | return -EINVAL; | |
1239 | } | |
1240 | spin_lock_irqsave(&priv->sta_lock, flags); | |
f2c7e521 AK |
1241 | priv->stations_39[sta_id].keyinfo.alg = keyconf->alg; |
1242 | priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen; | |
1243 | memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
1244 | keyconf->keylen); |
1245 | ||
f2c7e521 | 1246 | memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key, |
b481de9c | 1247 | keyconf->keylen); |
f2c7e521 AK |
1248 | priv->stations_39[sta_id].sta.key.key_flags = key_flags; |
1249 | priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1250 | priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
1251 | |
1252 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1253 | ||
1254 | IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); | |
f2c7e521 | 1255 | iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0); |
b481de9c ZY |
1256 | return 0; |
1257 | } | |
1258 | ||
4a8a4322 | 1259 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
1260 | { |
1261 | unsigned long flags; | |
1262 | ||
1263 | spin_lock_irqsave(&priv->sta_lock, flags); | |
f2c7e521 AK |
1264 | memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key)); |
1265 | memset(&priv->stations_39[sta_id].sta.key, 0, | |
4c897253 | 1266 | sizeof(struct iwl4965_keyinfo)); |
f2c7e521 AK |
1267 | priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
1268 | priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1269 | priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
1270 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1271 | ||
1272 | IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); | |
f2c7e521 | 1273 | iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0); |
b481de9c ZY |
1274 | return 0; |
1275 | } | |
1276 | ||
4a8a4322 | 1277 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
1278 | { |
1279 | struct list_head *element; | |
1280 | ||
1281 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1282 | priv->frames_count); | |
1283 | ||
1284 | while (!list_empty(&priv->free_frames)) { | |
1285 | element = priv->free_frames.next; | |
1286 | list_del(element); | |
bb8c093b | 1287 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
1288 | priv->frames_count--; |
1289 | } | |
1290 | ||
1291 | if (priv->frames_count) { | |
1292 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1293 | priv->frames_count); | |
1294 | priv->frames_count = 0; | |
1295 | } | |
1296 | } | |
1297 | ||
4a8a4322 | 1298 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 1299 | { |
bb8c093b | 1300 | struct iwl3945_frame *frame; |
b481de9c ZY |
1301 | struct list_head *element; |
1302 | if (list_empty(&priv->free_frames)) { | |
1303 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1304 | if (!frame) { | |
1305 | IWL_ERROR("Could not allocate frame!\n"); | |
1306 | return NULL; | |
1307 | } | |
1308 | ||
1309 | priv->frames_count++; | |
1310 | return frame; | |
1311 | } | |
1312 | ||
1313 | element = priv->free_frames.next; | |
1314 | list_del(element); | |
bb8c093b | 1315 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
1316 | } |
1317 | ||
4a8a4322 | 1318 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
1319 | { |
1320 | memset(frame, 0, sizeof(*frame)); | |
1321 | list_add(&frame->list, &priv->free_frames); | |
1322 | } | |
1323 | ||
4a8a4322 | 1324 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 1325 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 1326 | int left) |
b481de9c ZY |
1327 | { |
1328 | ||
bb8c093b | 1329 | if (!iwl3945_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
1330 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
1331 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
1332 | return 0; |
1333 | ||
1334 | if (priv->ibss_beacon->len > left) | |
1335 | return 0; | |
1336 | ||
1337 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1338 | ||
1339 | return priv->ibss_beacon->len; | |
1340 | } | |
1341 | ||
4a8a4322 | 1342 | static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv) |
b481de9c ZY |
1343 | { |
1344 | u8 i; | |
c24f0817 KA |
1345 | int rate_mask; |
1346 | ||
1347 | /* Set rate mask*/ | |
f2c7e521 | 1348 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) |
dbce56a4 | 1349 | rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK; |
c24f0817 | 1350 | else |
dbce56a4 | 1351 | rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK; |
b481de9c ZY |
1352 | |
1353 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1354 | i = iwl3945_rates[i].next_ieee) { |
b481de9c | 1355 | if (rate_mask & (1 << i)) |
bb8c093b | 1356 | return iwl3945_rates[i].plcp; |
b481de9c ZY |
1357 | } |
1358 | ||
c24f0817 | 1359 | /* No valid rate was found. Assign the lowest one */ |
f2c7e521 | 1360 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) |
c24f0817 KA |
1361 | return IWL_RATE_1M_PLCP; |
1362 | else | |
1363 | return IWL_RATE_6M_PLCP; | |
b481de9c ZY |
1364 | } |
1365 | ||
4a8a4322 | 1366 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 1367 | { |
bb8c093b | 1368 | struct iwl3945_frame *frame; |
b481de9c ZY |
1369 | unsigned int frame_size; |
1370 | int rc; | |
1371 | u8 rate; | |
1372 | ||
bb8c093b | 1373 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
1374 | |
1375 | if (!frame) { | |
1376 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1377 | "command.\n"); | |
1378 | return -ENOMEM; | |
1379 | } | |
1380 | ||
c24f0817 | 1381 | rate = iwl3945_rate_get_lowest_plcp(priv); |
b481de9c | 1382 | |
bb8c093b | 1383 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1384 | |
bb8c093b | 1385 | rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1386 | &frame->u.cmd[0]); |
1387 | ||
bb8c093b | 1388 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
1389 | |
1390 | return rc; | |
1391 | } | |
1392 | ||
1393 | /****************************************************************************** | |
1394 | * | |
1395 | * EEPROM related functions | |
1396 | * | |
1397 | ******************************************************************************/ | |
1398 | ||
4a8a4322 | 1399 | static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac) |
b481de9c | 1400 | { |
f2c7e521 | 1401 | memcpy(mac, priv->eeprom39.mac_address, 6); |
b481de9c ZY |
1402 | } |
1403 | ||
74a3a250 RC |
1404 | /* |
1405 | * Clear the OWNER_MSK, to establish driver (instead of uCode running on | |
1406 | * embedded controller) as EEPROM reader; each read is a series of pulses | |
1407 | * to/from the EEPROM chip, not a single event, so even reads could conflict | |
1408 | * if they weren't arbitrated by some ownership mechanism. Here, the driver | |
1409 | * simply claims ownership, which should be safe when this function is called | |
1410 | * (i.e. before loading uCode!). | |
1411 | */ | |
4a8a4322 | 1412 | static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv) |
74a3a250 | 1413 | { |
5d49f498 | 1414 | _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); |
74a3a250 RC |
1415 | return 0; |
1416 | } | |
1417 | ||
b481de9c | 1418 | /** |
bb8c093b | 1419 | * iwl3945_eeprom_init - read EEPROM contents |
b481de9c | 1420 | * |
f2c7e521 | 1421 | * Load the EEPROM contents from adapter into priv->eeprom39 |
b481de9c ZY |
1422 | * |
1423 | * NOTE: This routine uses the non-debug IO access functions. | |
1424 | */ | |
4a8a4322 | 1425 | int iwl3945_eeprom_init(struct iwl_priv *priv) |
b481de9c | 1426 | { |
f2c7e521 | 1427 | u16 *e = (u16 *)&priv->eeprom39; |
5d49f498 | 1428 | u32 gp = iwl_read32(priv, CSR_EEPROM_GP); |
f2c7e521 | 1429 | int sz = sizeof(priv->eeprom39); |
3d5717ad | 1430 | int ret; |
b481de9c ZY |
1431 | u16 addr; |
1432 | ||
1433 | /* The EEPROM structure has several padding buffers within it | |
1434 | * and when adding new EEPROM maps is subject to programmer errors | |
1435 | * which may be very difficult to identify without explicitly | |
1436 | * checking the resulting size of the eeprom map. */ | |
f2c7e521 | 1437 | BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE); |
b481de9c ZY |
1438 | |
1439 | if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { | |
6f147926 | 1440 | IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); |
b481de9c ZY |
1441 | return -ENOENT; |
1442 | } | |
1443 | ||
6440adb5 | 1444 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ |
3d5717ad ZY |
1445 | ret = iwl3945_eeprom_acquire_semaphore(priv); |
1446 | if (ret < 0) { | |
91e17473 | 1447 | IWL_ERROR("Failed to acquire EEPROM semaphore.\n"); |
b481de9c ZY |
1448 | return -ENOENT; |
1449 | } | |
1450 | ||
1451 | /* eeprom is an array of 16bit values */ | |
1452 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
3d5717ad | 1453 | u32 r; |
b481de9c | 1454 | |
5d49f498 | 1455 | _iwl_write32(priv, CSR_EEPROM_REG, |
3d5717ad | 1456 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); |
5d49f498 AK |
1457 | _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); |
1458 | ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG, | |
3d5717ad ZY |
1459 | CSR_EEPROM_REG_READ_VALID_MSK, |
1460 | IWL_EEPROM_ACCESS_TIMEOUT); | |
1461 | if (ret < 0) { | |
6f147926 | 1462 | IWL_ERROR("Time out reading EEPROM[%d]\n", addr); |
3d5717ad | 1463 | return ret; |
b481de9c | 1464 | } |
3d5717ad | 1465 | |
5d49f498 | 1466 | r = _iwl_read_direct32(priv, CSR_EEPROM_REG); |
58ff6d4d | 1467 | e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); |
b481de9c ZY |
1468 | } |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
4a8a4322 | 1473 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 1474 | { |
3832ec9d | 1475 | if (priv->shared_virt) |
b481de9c | 1476 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 1477 | sizeof(struct iwl3945_shared), |
3832ec9d AK |
1478 | priv->shared_virt, |
1479 | priv->shared_phys); | |
b481de9c ZY |
1480 | } |
1481 | ||
1482 | /** | |
bb8c093b | 1483 | * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1484 | * |
1485 | * return : set the bit for each supported rate insert in ie | |
1486 | */ | |
bb8c093b | 1487 | static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1488 | u16 basic_rate, int *left) |
b481de9c ZY |
1489 | { |
1490 | u16 ret_rates = 0, bit; | |
1491 | int i; | |
c7c46676 TW |
1492 | u8 *cnt = ie; |
1493 | u8 *rates = ie + 1; | |
b481de9c ZY |
1494 | |
1495 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1496 | if (bit & supported_rate) { | |
1497 | ret_rates |= bit; | |
bb8c093b | 1498 | rates[*cnt] = iwl3945_rates[i].ieee | |
c7c46676 TW |
1499 | ((bit & basic_rate) ? 0x80 : 0x00); |
1500 | (*cnt)++; | |
1501 | (*left)--; | |
1502 | if ((*left <= 0) || | |
1503 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1504 | break; |
1505 | } | |
1506 | } | |
1507 | ||
1508 | return ret_rates; | |
1509 | } | |
1510 | ||
1511 | /** | |
bb8c093b | 1512 | * iwl3945_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1513 | */ |
4a8a4322 | 1514 | static u16 iwl3945_fill_probe_req(struct iwl_priv *priv, |
b481de9c | 1515 | struct ieee80211_mgmt *frame, |
430cfe95 | 1516 | int left) |
b481de9c ZY |
1517 | { |
1518 | int len = 0; | |
1519 | u8 *pos = NULL; | |
c7c46676 | 1520 | u16 active_rates, ret_rates, cck_rates; |
b481de9c ZY |
1521 | |
1522 | /* Make sure there is enough space for the probe request, | |
1523 | * two mandatory IEs and the data */ | |
1524 | left -= 24; | |
1525 | if (left < 0) | |
1526 | return 0; | |
1527 | len += 24; | |
1528 | ||
1529 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
b5323d36 | 1530 | memcpy(frame->da, iwl_bcast_addr, ETH_ALEN); |
b481de9c | 1531 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
b5323d36 | 1532 | memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN); |
b481de9c ZY |
1533 | frame->seq_ctrl = 0; |
1534 | ||
1535 | /* fill in our indirect SSID IE */ | |
1536 | /* ...next IE... */ | |
1537 | ||
1538 | left -= 2; | |
1539 | if (left < 0) | |
1540 | return 0; | |
1541 | len += 2; | |
1542 | pos = &(frame->u.probe_req.variable[0]); | |
1543 | *pos++ = WLAN_EID_SSID; | |
1544 | *pos++ = 0; | |
1545 | ||
b481de9c ZY |
1546 | /* fill in supported rate */ |
1547 | /* ...next IE... */ | |
1548 | left -= 2; | |
1549 | if (left < 0) | |
1550 | return 0; | |
c7c46676 | 1551 | |
b481de9c ZY |
1552 | /* ... fill it in... */ |
1553 | *pos++ = WLAN_EID_SUPP_RATES; | |
1554 | *pos = 0; | |
c7c46676 TW |
1555 | |
1556 | priv->active_rate = priv->rates_mask; | |
1557 | active_rates = priv->active_rate; | |
b481de9c ZY |
1558 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; |
1559 | ||
c7c46676 | 1560 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1561 | ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates, |
c7c46676 TW |
1562 | priv->active_rate_basic, &left); |
1563 | active_rates &= ~ret_rates; | |
1564 | ||
bb8c093b | 1565 | ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 TW |
1566 | priv->active_rate_basic, &left); |
1567 | active_rates &= ~ret_rates; | |
1568 | ||
b481de9c ZY |
1569 | len += 2 + *pos; |
1570 | pos += (*pos) + 1; | |
c7c46676 | 1571 | if (active_rates == 0) |
b481de9c ZY |
1572 | goto fill_end; |
1573 | ||
1574 | /* fill in supported extended rate */ | |
1575 | /* ...next IE... */ | |
1576 | left -= 2; | |
1577 | if (left < 0) | |
1578 | return 0; | |
1579 | /* ... fill it in... */ | |
1580 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1581 | *pos = 0; | |
bb8c093b | 1582 | iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 | 1583 | priv->active_rate_basic, &left); |
b481de9c ZY |
1584 | if (*pos > 0) |
1585 | len += 2 + *pos; | |
1586 | ||
1587 | fill_end: | |
1588 | return (u16)len; | |
1589 | } | |
1590 | ||
1591 | /* | |
1592 | * QoS support | |
1593 | */ | |
4a8a4322 | 1594 | static int iwl3945_send_qos_params_command(struct iwl_priv *priv, |
4c897253 | 1595 | struct iwl_qosparam_cmd *qos) |
b481de9c ZY |
1596 | { |
1597 | ||
bb8c093b | 1598 | return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
4c897253 | 1599 | sizeof(struct iwl_qosparam_cmd), qos); |
b481de9c ZY |
1600 | } |
1601 | ||
4a8a4322 | 1602 | static void iwl3945_reset_qos(struct iwl_priv *priv) |
b481de9c ZY |
1603 | { |
1604 | u16 cw_min = 15; | |
1605 | u16 cw_max = 1023; | |
1606 | u8 aifs = 2; | |
1607 | u8 is_legacy = 0; | |
1608 | unsigned long flags; | |
1609 | int i; | |
1610 | ||
1611 | spin_lock_irqsave(&priv->lock, flags); | |
1612 | priv->qos_data.qos_active = 0; | |
1613 | ||
6d1ef1a3 WT |
1614 | /* QoS always active in AP and ADHOC mode |
1615 | * In STA mode wait for association | |
1616 | */ | |
1617 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC || | |
1618 | priv->iw_mode == NL80211_IFTYPE_AP) | |
1619 | priv->qos_data.qos_active = 1; | |
1620 | else | |
1621 | priv->qos_data.qos_active = 0; | |
1622 | ||
1623 | ||
1624 | /* check for legacy mode */ | |
1625 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC && | |
1626 | (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) || | |
1627 | (priv->iw_mode == NL80211_IFTYPE_STATION && | |
f2c7e521 | 1628 | (priv->staging39_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) { |
b481de9c ZY |
1629 | cw_min = 31; |
1630 | is_legacy = 1; | |
1631 | } | |
1632 | ||
1633 | if (priv->qos_data.qos_active) | |
1634 | aifs = 3; | |
1635 | ||
1636 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); | |
1637 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
1638 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
1639 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
1640 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
1641 | ||
1642 | if (priv->qos_data.qos_active) { | |
1643 | i = 1; | |
1644 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
1645 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
1646 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
1647 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1648 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1649 | ||
1650 | i = 2; | |
1651 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1652 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
1653 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1654 | cpu_to_le16(cw_max); | |
1655 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1656 | if (is_legacy) | |
1657 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1658 | cpu_to_le16(6016); | |
1659 | else | |
1660 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1661 | cpu_to_le16(3008); | |
1662 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1663 | ||
1664 | i = 3; | |
1665 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1666 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
1667 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1668 | cpu_to_le16((cw_max + 1) / 2 - 1); | |
1669 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1670 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1671 | if (is_legacy) | |
1672 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1673 | cpu_to_le16(3264); | |
1674 | else | |
1675 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1676 | cpu_to_le16(1504); | |
1677 | } else { | |
1678 | for (i = 1; i < 4; i++) { | |
1679 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1680 | cpu_to_le16(cw_min); | |
1681 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1682 | cpu_to_le16(cw_max); | |
1683 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
1684 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1685 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1686 | } | |
1687 | } | |
1688 | IWL_DEBUG_QOS("set QoS to default \n"); | |
1689 | ||
1690 | spin_unlock_irqrestore(&priv->lock, flags); | |
1691 | } | |
1692 | ||
4a8a4322 | 1693 | static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force) |
b481de9c ZY |
1694 | { |
1695 | unsigned long flags; | |
1696 | ||
b481de9c ZY |
1697 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1698 | return; | |
1699 | ||
b481de9c ZY |
1700 | spin_lock_irqsave(&priv->lock, flags); |
1701 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1702 | ||
1703 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1704 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1705 | priv->qos_data.def_qos_parm.qos_flags |= | |
1706 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
1707 | ||
1708 | if (priv->qos_data.qos_active) | |
1709 | priv->qos_data.def_qos_parm.qos_flags |= | |
1710 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1711 | ||
1712 | spin_unlock_irqrestore(&priv->lock, flags); | |
1713 | ||
bb8c093b | 1714 | if (force || iwl3945_is_associated(priv)) { |
a96a27f9 | 1715 | IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n", |
b481de9c ZY |
1716 | priv->qos_data.qos_active); |
1717 | ||
bb8c093b | 1718 | iwl3945_send_qos_params_command(priv, |
b481de9c ZY |
1719 | &(priv->qos_data.def_qos_parm)); |
1720 | } | |
1721 | } | |
1722 | ||
b481de9c ZY |
1723 | /* |
1724 | * Power management (not Tx power!) functions | |
1725 | */ | |
1726 | #define MSEC_TO_USEC 1024 | |
1727 | ||
600c0e11 TW |
1728 | |
1729 | #define NOSLP __constant_cpu_to_le16(0), 0, 0 | |
1730 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
b481de9c ZY |
1731 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) |
1732 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1733 | __constant_cpu_to_le32(X1), \ | |
1734 | __constant_cpu_to_le32(X2), \ | |
1735 | __constant_cpu_to_le32(X3), \ | |
1736 | __constant_cpu_to_le32(X4)} | |
1737 | ||
b481de9c | 1738 | /* default power management (not Tx power) table values */ |
a96a27f9 | 1739 | /* for TIM 0-10 */ |
1125eff3 | 1740 | static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = { |
b481de9c ZY |
1741 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1742 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1743 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1744 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1745 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1746 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1747 | }; | |
1748 | ||
a96a27f9 | 1749 | /* for TIM > 10 */ |
1125eff3 | 1750 | static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = { |
b481de9c ZY |
1751 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1752 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1753 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1754 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1755 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1756 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1757 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1758 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1759 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1760 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1761 | }; | |
1762 | ||
4a8a4322 | 1763 | int iwl3945_power_init_handle(struct iwl_priv *priv) |
b481de9c ZY |
1764 | { |
1765 | int rc = 0, i; | |
bb8c093b | 1766 | struct iwl3945_power_mgr *pow_data; |
1125eff3 | 1767 | int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC; |
b481de9c ZY |
1768 | u16 pci_pm; |
1769 | ||
1770 | IWL_DEBUG_POWER("Initialize power \n"); | |
1771 | ||
f2c7e521 | 1772 | pow_data = &(priv->power_data_39); |
b481de9c ZY |
1773 | |
1774 | memset(pow_data, 0, sizeof(*pow_data)); | |
1775 | ||
1776 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1777 | pow_data->dtim_val = 0xffff; | |
1778 | ||
1779 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1780 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1781 | ||
1782 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1783 | if (rc != 0) | |
1784 | return 0; | |
1785 | else { | |
600c0e11 | 1786 | struct iwl_powertable_cmd *cmd; |
b481de9c ZY |
1787 | |
1788 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1789 | ||
1125eff3 | 1790 | for (i = 0; i < IWL39_POWER_AC; i++) { |
b481de9c ZY |
1791 | cmd = &pow_data->pwr_range_0[i].cmd; |
1792 | ||
1793 | if (pci_pm & 0x1) | |
1794 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1795 | else | |
1796 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1797 | } | |
1798 | } | |
1799 | return rc; | |
1800 | } | |
1801 | ||
4a8a4322 | 1802 | static int iwl3945_update_power_cmd(struct iwl_priv *priv, |
600c0e11 | 1803 | struct iwl_powertable_cmd *cmd, u32 mode) |
b481de9c ZY |
1804 | { |
1805 | int rc = 0, i; | |
1806 | u8 skip; | |
1807 | u32 max_sleep = 0; | |
1125eff3 | 1808 | struct iwl_power_vec_entry *range; |
b481de9c | 1809 | u8 period = 0; |
bb8c093b | 1810 | struct iwl3945_power_mgr *pow_data; |
b481de9c ZY |
1811 | |
1812 | if (mode > IWL_POWER_INDEX_5) { | |
1813 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1814 | return -1; | |
1815 | } | |
f2c7e521 | 1816 | pow_data = &(priv->power_data_39); |
b481de9c ZY |
1817 | |
1818 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1819 | range = &pow_data->pwr_range_0[0]; | |
1820 | else | |
1821 | range = &pow_data->pwr_range_1[1]; | |
1822 | ||
bb8c093b | 1823 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd)); |
b481de9c ZY |
1824 | |
1825 | #ifdef IWL_MAC80211_DISABLE | |
1826 | if (priv->assoc_network != NULL) { | |
1827 | unsigned long flags; | |
1828 | ||
1829 | period = priv->assoc_network->tim.tim_period; | |
1830 | } | |
1831 | #endif /*IWL_MAC80211_DISABLE */ | |
1832 | skip = range[mode].no_dtim; | |
1833 | ||
1834 | if (period == 0) { | |
1835 | period = 1; | |
1836 | skip = 0; | |
1837 | } | |
1838 | ||
1839 | if (skip == 0) { | |
1840 | max_sleep = period; | |
1841 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1842 | } else { | |
1843 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1844 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1845 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1846 | } | |
1847 | ||
1848 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1849 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1850 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1851 | } | |
1852 | ||
1853 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1854 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1855 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1856 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1857 | le32_to_cpu(cmd->sleep_interval[0]), | |
1858 | le32_to_cpu(cmd->sleep_interval[1]), | |
1859 | le32_to_cpu(cmd->sleep_interval[2]), | |
1860 | le32_to_cpu(cmd->sleep_interval[3]), | |
1861 | le32_to_cpu(cmd->sleep_interval[4])); | |
1862 | ||
1863 | return rc; | |
1864 | } | |
1865 | ||
4a8a4322 | 1866 | static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode) |
b481de9c | 1867 | { |
9a62f73b | 1868 | u32 uninitialized_var(final_mode); |
b481de9c | 1869 | int rc; |
600c0e11 | 1870 | struct iwl_powertable_cmd cmd; |
b481de9c ZY |
1871 | |
1872 | /* If on battery, set to 3, | |
01ebd063 | 1873 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
1874 | * else user level */ |
1875 | switch (mode) { | |
1125eff3 | 1876 | case IWL39_POWER_BATTERY: |
b481de9c ZY |
1877 | final_mode = IWL_POWER_INDEX_3; |
1878 | break; | |
1125eff3 | 1879 | case IWL39_POWER_AC: |
b481de9c ZY |
1880 | final_mode = IWL_POWER_MODE_CAM; |
1881 | break; | |
1882 | default: | |
1883 | final_mode = mode; | |
1884 | break; | |
1885 | } | |
1886 | ||
bb8c093b | 1887 | iwl3945_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 1888 | |
600c0e11 TW |
1889 | /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */ |
1890 | rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, | |
1891 | sizeof(struct iwl3945_powertable_cmd), &cmd); | |
b481de9c ZY |
1892 | |
1893 | if (final_mode == IWL_POWER_MODE_CAM) | |
1894 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
1895 | else | |
1896 | set_bit(STATUS_POWER_PMI, &priv->status); | |
1897 | ||
1898 | return rc; | |
1899 | } | |
1900 | ||
b481de9c | 1901 | /** |
bb8c093b | 1902 | * iwl3945_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
1903 | * |
1904 | * NOTE: priv->mutex is not required before calling this function | |
1905 | */ | |
4a8a4322 | 1906 | static int iwl3945_scan_cancel(struct iwl_priv *priv) |
b481de9c ZY |
1907 | { |
1908 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1909 | clear_bit(STATUS_SCANNING, &priv->status); | |
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1914 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1915 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
1916 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1917 | queue_work(priv->workqueue, &priv->abort_scan); | |
1918 | ||
1919 | } else | |
1920 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
1921 | ||
1922 | return test_bit(STATUS_SCANNING, &priv->status); | |
1923 | } | |
1924 | ||
1925 | return 0; | |
1926 | } | |
1927 | ||
1928 | /** | |
bb8c093b | 1929 | * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
1930 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
1931 | * | |
1932 | * NOTE: priv->mutex must be held before calling this function | |
1933 | */ | |
4a8a4322 | 1934 | static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms) |
b481de9c ZY |
1935 | { |
1936 | unsigned long now = jiffies; | |
1937 | int ret; | |
1938 | ||
bb8c093b | 1939 | ret = iwl3945_scan_cancel(priv); |
b481de9c ZY |
1940 | if (ret && ms) { |
1941 | mutex_unlock(&priv->mutex); | |
1942 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
1943 | test_bit(STATUS_SCANNING, &priv->status)) | |
1944 | msleep(1); | |
1945 | mutex_lock(&priv->mutex); | |
1946 | ||
1947 | return test_bit(STATUS_SCANNING, &priv->status); | |
1948 | } | |
1949 | ||
1950 | return ret; | |
1951 | } | |
1952 | ||
b481de9c ZY |
1953 | #define MAX_UCODE_BEACON_INTERVAL 1024 |
1954 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
1955 | ||
bb8c093b | 1956 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
1957 | { |
1958 | u16 new_val = 0; | |
1959 | u16 beacon_factor = 0; | |
1960 | ||
1961 | beacon_factor = | |
1962 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
1963 | / MAX_UCODE_BEACON_INTERVAL; | |
1964 | new_val = beacon_val / beacon_factor; | |
1965 | ||
1966 | return cpu_to_le16(new_val); | |
1967 | } | |
1968 | ||
4a8a4322 | 1969 | static void iwl3945_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
1970 | { |
1971 | u64 interval_tm_unit; | |
1972 | u64 tsf, result; | |
1973 | unsigned long flags; | |
1974 | struct ieee80211_conf *conf = NULL; | |
1975 | u16 beacon_int = 0; | |
1976 | ||
1977 | conf = ieee80211_get_hw_conf(priv->hw); | |
1978 | ||
1979 | spin_lock_irqsave(&priv->lock, flags); | |
28afaf91 | 1980 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b481de9c ZY |
1981 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; |
1982 | ||
28afaf91 | 1983 | tsf = priv->timestamp; |
b481de9c ZY |
1984 | |
1985 | beacon_int = priv->beacon_int; | |
1986 | spin_unlock_irqrestore(&priv->lock, flags); | |
1987 | ||
05c914fe | 1988 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
b481de9c ZY |
1989 | if (beacon_int == 0) { |
1990 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
1991 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
1992 | } else { | |
1993 | priv->rxon_timing.beacon_interval = | |
1994 | cpu_to_le16(beacon_int); | |
1995 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1996 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
1997 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
1998 | } | |
1999 | ||
2000 | priv->rxon_timing.atim_window = 0; | |
2001 | } else { | |
2002 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2003 | iwl3945_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
2004 | /* TODO: we need to get atim_window from upper stack |
2005 | * for now we set to 0 */ | |
2006 | priv->rxon_timing.atim_window = 0; | |
2007 | } | |
2008 | ||
2009 | interval_tm_unit = | |
2010 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
2011 | result = do_div(tsf, interval_tm_unit); | |
2012 | priv->rxon_timing.beacon_init_val = | |
2013 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
2014 | ||
2015 | IWL_DEBUG_ASSOC | |
2016 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
2017 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
2018 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
2019 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
2020 | } | |
2021 | ||
4a8a4322 | 2022 | static int iwl3945_scan_initiate(struct iwl_priv *priv) |
b481de9c | 2023 | { |
bb8c093b | 2024 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
2025 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
2026 | return -EIO; | |
2027 | } | |
2028 | ||
2029 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2030 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
2031 | return -EAGAIN; | |
2032 | } | |
2033 | ||
2034 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2035 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
2036 | "Queuing.\n"); | |
2037 | return -EAGAIN; | |
2038 | } | |
2039 | ||
2040 | IWL_DEBUG_INFO("Starting scan...\n"); | |
66b5004d RR |
2041 | if (priv->cfg->sku & IWL_SKU_G) |
2042 | priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ); | |
2043 | if (priv->cfg->sku & IWL_SKU_A) | |
2044 | priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ); | |
b481de9c ZY |
2045 | set_bit(STATUS_SCANNING, &priv->status); |
2046 | priv->scan_start = jiffies; | |
2047 | priv->scan_pass_start = priv->scan_start; | |
2048 | ||
2049 | queue_work(priv->workqueue, &priv->request_scan); | |
2050 | ||
2051 | return 0; | |
2052 | } | |
2053 | ||
4a8a4322 | 2054 | static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
b481de9c | 2055 | { |
f2c7e521 | 2056 | struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon; |
b481de9c ZY |
2057 | |
2058 | if (hw_decrypt) | |
2059 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
2060 | else | |
2061 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
2062 | ||
2063 | return 0; | |
2064 | } | |
2065 | ||
4a8a4322 | 2066 | static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv, |
8318d78a | 2067 | enum ieee80211_band band) |
b481de9c | 2068 | { |
8318d78a | 2069 | if (band == IEEE80211_BAND_5GHZ) { |
f2c7e521 | 2070 | priv->staging39_rxon.flags &= |
b481de9c ZY |
2071 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
2072 | | RXON_FLG_CCK_MSK); | |
f2c7e521 | 2073 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 2074 | } else { |
bb8c093b | 2075 | /* Copied from iwl3945_bg_post_associate() */ |
b481de9c | 2076 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
f2c7e521 | 2077 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 2078 | else |
f2c7e521 | 2079 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 2080 | |
05c914fe | 2081 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
f2c7e521 | 2082 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 2083 | |
f2c7e521 AK |
2084 | priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
2085 | priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
2086 | priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
b481de9c ZY |
2087 | } |
2088 | } | |
2089 | ||
2090 | /* | |
01ebd063 | 2091 | * initialize rxon structure with default values from eeprom |
b481de9c | 2092 | */ |
4a8a4322 | 2093 | static void iwl3945_connection_init_rx_config(struct iwl_priv *priv, |
60294de3 | 2094 | int mode) |
b481de9c | 2095 | { |
d20b3c65 | 2096 | const struct iwl_channel_info *ch_info; |
b481de9c | 2097 | |
f2c7e521 | 2098 | memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon)); |
b481de9c | 2099 | |
60294de3 | 2100 | switch (mode) { |
05c914fe | 2101 | case NL80211_IFTYPE_AP: |
f2c7e521 | 2102 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP; |
b481de9c ZY |
2103 | break; |
2104 | ||
05c914fe | 2105 | case NL80211_IFTYPE_STATION: |
f2c7e521 AK |
2106 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS; |
2107 | priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
b481de9c ZY |
2108 | break; |
2109 | ||
05c914fe | 2110 | case NL80211_IFTYPE_ADHOC: |
f2c7e521 AK |
2111 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS; |
2112 | priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
2113 | priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
b481de9c ZY |
2114 | RXON_FILTER_ACCEPT_GRP_MSK; |
2115 | break; | |
2116 | ||
05c914fe | 2117 | case NL80211_IFTYPE_MONITOR: |
f2c7e521 AK |
2118 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; |
2119 | priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
b481de9c ZY |
2120 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; |
2121 | break; | |
69dc5d9d | 2122 | default: |
60294de3 | 2123 | IWL_ERROR("Unsupported interface type %d\n", mode); |
69dc5d9d | 2124 | break; |
b481de9c ZY |
2125 | } |
2126 | ||
2127 | #if 0 | |
2128 | /* TODO: Figure out when short_preamble would be set and cache from | |
2129 | * that */ | |
2130 | if (!hw_to_local(priv->hw)->short_preamble) | |
f2c7e521 | 2131 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 2132 | else |
f2c7e521 | 2133 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c ZY |
2134 | #endif |
2135 | ||
8318d78a | 2136 | ch_info = iwl3945_get_channel_info(priv, priv->band, |
f2c7e521 | 2137 | le16_to_cpu(priv->active39_rxon.channel)); |
b481de9c ZY |
2138 | |
2139 | if (!ch_info) | |
2140 | ch_info = &priv->channel_info[0]; | |
2141 | ||
2142 | /* | |
2143 | * in some case A channels are all non IBSS | |
2144 | * in this case force B/G channel | |
2145 | */ | |
60294de3 | 2146 | if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info))) |
b481de9c ZY |
2147 | ch_info = &priv->channel_info[0]; |
2148 | ||
f2c7e521 | 2149 | priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel); |
b481de9c | 2150 | if (is_channel_a_band(ch_info)) |
8318d78a | 2151 | priv->band = IEEE80211_BAND_5GHZ; |
b481de9c | 2152 | else |
8318d78a | 2153 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c | 2154 | |
8318d78a | 2155 | iwl3945_set_flags_for_phymode(priv, priv->band); |
b481de9c | 2156 | |
f2c7e521 | 2157 | priv->staging39_rxon.ofdm_basic_rates = |
b481de9c | 2158 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
f2c7e521 | 2159 | priv->staging39_rxon.cck_basic_rates = |
b481de9c ZY |
2160 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
2161 | } | |
2162 | ||
4a8a4322 | 2163 | static int iwl3945_set_mode(struct iwl_priv *priv, int mode) |
b481de9c | 2164 | { |
05c914fe | 2165 | if (mode == NL80211_IFTYPE_ADHOC) { |
d20b3c65 | 2166 | const struct iwl_channel_info *ch_info; |
b481de9c | 2167 | |
bb8c093b | 2168 | ch_info = iwl3945_get_channel_info(priv, |
8318d78a | 2169 | priv->band, |
f2c7e521 | 2170 | le16_to_cpu(priv->staging39_rxon.channel)); |
b481de9c ZY |
2171 | |
2172 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2173 | IWL_ERROR("channel %d not IBSS channel\n", | |
f2c7e521 | 2174 | le16_to_cpu(priv->staging39_rxon.channel)); |
b481de9c ZY |
2175 | return -EINVAL; |
2176 | } | |
2177 | } | |
2178 | ||
60294de3 | 2179 | iwl3945_connection_init_rx_config(priv, mode); |
f2c7e521 | 2180 | memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
b481de9c | 2181 | |
bb8c093b | 2182 | iwl3945_clear_stations_table(priv); |
b481de9c | 2183 | |
a96a27f9 | 2184 | /* don't commit rxon if rf-kill is on*/ |
fde3571f MA |
2185 | if (!iwl3945_is_ready_rf(priv)) |
2186 | return -EAGAIN; | |
2187 | ||
2188 | cancel_delayed_work(&priv->scan_check); | |
2189 | if (iwl3945_scan_cancel_timeout(priv, 100)) { | |
2190 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
2191 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
2192 | return -EAGAIN; | |
2193 | } | |
2194 | ||
bb8c093b | 2195 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
2196 | |
2197 | return 0; | |
2198 | } | |
2199 | ||
4a8a4322 | 2200 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 2201 | struct ieee80211_tx_info *info, |
bb8c093b | 2202 | struct iwl3945_cmd *cmd, |
b481de9c ZY |
2203 | struct sk_buff *skb_frag, |
2204 | int last_frag) | |
2205 | { | |
1c014420 | 2206 | struct iwl3945_hw_key *keyinfo = |
f2c7e521 | 2207 | &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo; |
b481de9c ZY |
2208 | |
2209 | switch (keyinfo->alg) { | |
2210 | case ALG_CCMP: | |
2211 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
2212 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
a96a27f9 | 2213 | IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
2214 | break; |
2215 | ||
2216 | case ALG_TKIP: | |
2217 | #if 0 | |
2218 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; | |
2219 | ||
2220 | if (last_frag) | |
2221 | memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8, | |
2222 | 8); | |
2223 | else | |
2224 | memset(cmd->cmd.tx.tkip_mic.byte, 0, 8); | |
2225 | #endif | |
2226 | break; | |
2227 | ||
2228 | case ALG_WEP: | |
2229 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP | | |
e039fa4a | 2230 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
2231 | |
2232 | if (keyinfo->keylen == 13) | |
2233 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2234 | ||
2235 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen); | |
2236 | ||
2237 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
e039fa4a | 2238 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
2239 | break; |
2240 | ||
b481de9c ZY |
2241 | default: |
2242 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2243 | break; | |
2244 | } | |
2245 | } | |
2246 | ||
2247 | /* | |
2248 | * handle build REPLY_TX command notification. | |
2249 | */ | |
4a8a4322 | 2250 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
bb8c093b | 2251 | struct iwl3945_cmd *cmd, |
e039fa4a | 2252 | struct ieee80211_tx_info *info, |
b481de9c ZY |
2253 | struct ieee80211_hdr *hdr, |
2254 | int is_unicast, u8 std_id) | |
2255 | { | |
fd7c8a40 | 2256 | __le16 fc = hdr->frame_control; |
b481de9c | 2257 | __le32 tx_flags = cmd->cmd.tx.tx_flags; |
e6a9854b | 2258 | u8 rc_flags = info->control.rates[0].flags; |
b481de9c ZY |
2259 | |
2260 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 2261 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 2262 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 2263 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 2264 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 2265 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
2266 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
2267 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2268 | } else { | |
2269 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2270 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2271 | } | |
2272 | ||
2273 | cmd->cmd.tx.sta_id = std_id; | |
8b7b1e05 | 2274 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
2275 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
2276 | ||
fd7c8a40 HH |
2277 | if (ieee80211_is_data_qos(fc)) { |
2278 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
54dbb525 | 2279 | cmd->cmd.tx.tid_tspec = qc[0] & 0xf; |
b481de9c | 2280 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 2281 | } else { |
b481de9c | 2282 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 2283 | } |
b481de9c | 2284 | |
e6a9854b | 2285 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
b481de9c ZY |
2286 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
2287 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e6a9854b | 2288 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
b481de9c ZY |
2289 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
2290 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2291 | } | |
2292 | ||
2293 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2294 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2295 | ||
2296 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
2297 | if (ieee80211_is_mgmt(fc)) { |
2298 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
bc434dd2 | 2299 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2300 | else |
bc434dd2 | 2301 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2302 | } else { |
b481de9c | 2303 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; |
ab53d8af MA |
2304 | #ifdef CONFIG_IWL3945_LEDS |
2305 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); | |
2306 | #endif | |
2307 | } | |
b481de9c ZY |
2308 | |
2309 | cmd->cmd.tx.driver_txop = 0; | |
2310 | cmd->cmd.tx.tx_flags = tx_flags; | |
2311 | cmd->cmd.tx.next_frame_len = 0; | |
2312 | } | |
2313 | ||
6440adb5 BC |
2314 | /** |
2315 | * iwl3945_get_sta_id - Find station's index within station table | |
2316 | */ | |
4a8a4322 | 2317 | static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr) |
b481de9c ZY |
2318 | { |
2319 | int sta_id; | |
2320 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2321 | ||
6440adb5 | 2322 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2323 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2324 | is_multicast_ether_addr(hdr->addr1)) | |
3832ec9d | 2325 | return priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2326 | |
2327 | switch (priv->iw_mode) { | |
2328 | ||
6440adb5 BC |
2329 | /* If we are a client station in a BSS network, use the special |
2330 | * AP station entry (that's the only station we communicate with) */ | |
05c914fe | 2331 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2332 | return IWL_AP_ID; |
2333 | ||
2334 | /* If we are an AP, then find the station, or use BCAST */ | |
05c914fe | 2335 | case NL80211_IFTYPE_AP: |
bb8c093b | 2336 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2337 | if (sta_id != IWL_INVALID_STATION) |
2338 | return sta_id; | |
3832ec9d | 2339 | return priv->hw_params.bcast_sta_id; |
b481de9c | 2340 | |
6440adb5 BC |
2341 | /* If this frame is going out to an IBSS network, find the station, |
2342 | * or create a new station table entry */ | |
05c914fe | 2343 | case NL80211_IFTYPE_ADHOC: { |
6440adb5 | 2344 | /* Create new station table entry */ |
bb8c093b | 2345 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2346 | if (sta_id != IWL_INVALID_STATION) |
2347 | return sta_id; | |
2348 | ||
bb8c093b | 2349 | sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC); |
b481de9c ZY |
2350 | |
2351 | if (sta_id != IWL_INVALID_STATION) | |
2352 | return sta_id; | |
2353 | ||
e174961c | 2354 | IWL_DEBUG_DROP("Station %pM not in station map. " |
b481de9c | 2355 | "Defaulting to broadcast...\n", |
e174961c | 2356 | hdr->addr1); |
40b8ec0b | 2357 | iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
3832ec9d | 2358 | return priv->hw_params.bcast_sta_id; |
0795af57 | 2359 | } |
914233d6 SG |
2360 | /* If we are in monitor mode, use BCAST. This is required for |
2361 | * packet injection. */ | |
05c914fe | 2362 | case NL80211_IFTYPE_MONITOR: |
3832ec9d | 2363 | return priv->hw_params.bcast_sta_id; |
914233d6 | 2364 | |
b481de9c | 2365 | default: |
6f147926 | 2366 | IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode); |
3832ec9d | 2367 | return priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2368 | } |
2369 | } | |
2370 | ||
2371 | /* | |
2372 | * start REPLY_TX command process | |
2373 | */ | |
4a8a4322 | 2374 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
2375 | { |
2376 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 2377 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bb8c093b | 2378 | struct iwl3945_tfd_frame *tfd; |
b481de9c | 2379 | u32 *control_flags; |
e2530083 | 2380 | int txq_id = skb_get_queue_mapping(skb); |
bb8c093b | 2381 | struct iwl3945_tx_queue *txq = NULL; |
d20b3c65 | 2382 | struct iwl_queue *q = NULL; |
b481de9c ZY |
2383 | dma_addr_t phys_addr; |
2384 | dma_addr_t txcmd_phys; | |
bb8c093b | 2385 | struct iwl3945_cmd *out_cmd = NULL; |
54dbb525 TW |
2386 | u16 len, idx, len_org, hdr_len; |
2387 | u8 id; | |
2388 | u8 unicast; | |
b481de9c | 2389 | u8 sta_id; |
54dbb525 | 2390 | u8 tid = 0; |
b481de9c | 2391 | u16 seq_number = 0; |
fd7c8a40 | 2392 | __le16 fc; |
b481de9c | 2393 | u8 wait_write_ptr = 0; |
54dbb525 | 2394 | u8 *qc = NULL; |
b481de9c ZY |
2395 | unsigned long flags; |
2396 | int rc; | |
2397 | ||
2398 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2399 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
2400 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2401 | goto drop_unlock; | |
2402 | } | |
2403 | ||
e039fa4a | 2404 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2405 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2406 | goto drop_unlock; | |
2407 | } | |
2408 | ||
2409 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2410 | id = 0; | |
2411 | ||
fd7c8a40 | 2412 | fc = hdr->frame_control; |
b481de9c | 2413 | |
c8b0e6e1 | 2414 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
2415 | if (ieee80211_is_auth(fc)) |
2416 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
fd7c8a40 | 2417 | else if (ieee80211_is_assoc_req(fc)) |
b481de9c | 2418 | IWL_DEBUG_TX("Sending ASSOC frame\n"); |
fd7c8a40 | 2419 | else if (ieee80211_is_reassoc_req(fc)) |
b481de9c ZY |
2420 | IWL_DEBUG_TX("Sending REASSOC frame\n"); |
2421 | #endif | |
2422 | ||
7878a5a4 | 2423 | /* drop all data frame if we are not associated */ |
914233d6 | 2424 | if (ieee80211_is_data(fc) && |
05c914fe | 2425 | (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */ |
914233d6 | 2426 | (!iwl3945_is_associated(priv) || |
05c914fe | 2427 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
bb8c093b | 2428 | IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n"); |
b481de9c ZY |
2429 | goto drop_unlock; |
2430 | } | |
2431 | ||
2432 | spin_unlock_irqrestore(&priv->lock, flags); | |
2433 | ||
7294ec95 | 2434 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 BC |
2435 | |
2436 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2437 | sta_id = iwl3945_get_sta_id(priv, hdr); |
b481de9c | 2438 | if (sta_id == IWL_INVALID_STATION) { |
e174961c JB |
2439 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n", |
2440 | hdr->addr1); | |
b481de9c ZY |
2441 | goto drop; |
2442 | } | |
2443 | ||
2444 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2445 | ||
fd7c8a40 HH |
2446 | if (ieee80211_is_data_qos(fc)) { |
2447 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 2448 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
f2c7e521 | 2449 | seq_number = priv->stations_39[sta_id].tid[tid].seq_number & |
b481de9c ZY |
2450 | IEEE80211_SCTL_SEQ; |
2451 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2452 | (hdr->seq_ctrl & | |
2453 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2454 | seq_number += 0x10; | |
2455 | } | |
6440adb5 BC |
2456 | |
2457 | /* Descriptor for chosen Tx queue */ | |
f2c7e521 | 2458 | txq = &priv->txq39[txq_id]; |
b481de9c ZY |
2459 | q = &txq->q; |
2460 | ||
2461 | spin_lock_irqsave(&priv->lock, flags); | |
2462 | ||
6440adb5 | 2463 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2464 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2465 | memset(tfd, 0, sizeof(*tfd)); |
2466 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2467 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2468 | |
6440adb5 | 2469 | /* Set up driver data for this TFD */ |
bb8c093b | 2470 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info)); |
fc4b6853 | 2471 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 BC |
2472 | |
2473 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2474 | out_cmd = &txq->cmd[idx]; |
2475 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2476 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 BC |
2477 | |
2478 | /* | |
2479 | * Set up the Tx-command (not MAC!) header. | |
2480 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2481 | * after Tx, uCode's Tx response will return this value so driver can | |
2482 | * locate the frame within the tx queue and do post-tx processing. | |
2483 | */ | |
b481de9c ZY |
2484 | out_cmd->hdr.cmd = REPLY_TX; |
2485 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2486 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
2487 | |
2488 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2489 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2490 | ||
6440adb5 BC |
2491 | /* |
2492 | * Use the first empty entry in this queue's command buffer array | |
2493 | * to contain the Tx command and MAC header concatenated together | |
2494 | * (payload data will be in another buffer). | |
2495 | * Size of this varies, due to varying MAC header length. | |
2496 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2497 | * of the MAC header (device reads on dword boundaries). | |
2498 | * We'll tell device about this padding later. | |
2499 | */ | |
3832ec9d | 2500 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 2501 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
2502 | |
2503 | len_org = len; | |
2504 | len = (len + 3) & ~3; | |
2505 | ||
2506 | if (len_org != len) | |
2507 | len_org = 1; | |
2508 | else | |
2509 | len_org = 0; | |
2510 | ||
6440adb5 BC |
2511 | /* Physical address of this Tx command's header (not MAC header!), |
2512 | * within command buffer array. */ | |
bb8c093b CH |
2513 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx + |
2514 | offsetof(struct iwl3945_cmd, hdr); | |
b481de9c | 2515 | |
6440adb5 BC |
2516 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2517 | * first entry */ | |
bb8c093b | 2518 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c | 2519 | |
d0f09804 | 2520 | if (info->control.hw_key) |
e039fa4a | 2521 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0); |
b481de9c | 2522 | |
6440adb5 BC |
2523 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2524 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2525 | len = skb->len - hdr_len; |
2526 | if (len) { | |
2527 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2528 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2529 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2530 | } |
2531 | ||
b481de9c | 2532 | if (!len) |
6440adb5 | 2533 | /* If there is no payload, then we use only one Tx buffer */ |
b481de9c ZY |
2534 | *control_flags = TFD_CTL_COUNT_SET(1); |
2535 | else | |
6440adb5 BC |
2536 | /* Else use 2 buffers. |
2537 | * Tell 3945 about any padding after MAC header */ | |
b481de9c ZY |
2538 | *control_flags = TFD_CTL_COUNT_SET(2) | |
2539 | TFD_CTL_PAD_SET(U32_PAD(len)); | |
2540 | ||
6440adb5 | 2541 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2542 | len = (u16)skb->len; |
2543 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2544 | ||
2545 | /* TODO need this for burst mode later on */ | |
e039fa4a | 2546 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id); |
b481de9c ZY |
2547 | |
2548 | /* set is_hcca to 0; it probably will never be implemented */ | |
e039fa4a | 2549 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); |
b481de9c ZY |
2550 | |
2551 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; | |
2552 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
2553 | ||
8b7b1e05 | 2554 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
b481de9c | 2555 | txq->need_update = 1; |
3ac7f146 | 2556 | if (qc) |
f2c7e521 | 2557 | priv->stations_39[sta_id].tid[tid].seq_number = seq_number; |
b481de9c ZY |
2558 | } else { |
2559 | wait_write_ptr = 1; | |
2560 | txq->need_update = 0; | |
2561 | } | |
2562 | ||
40b8ec0b | 2563 | iwl_print_hex_dump(priv, IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2564 | sizeof(out_cmd->cmd.tx)); |
2565 | ||
40b8ec0b | 2566 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
7294ec95 | 2567 | ieee80211_hdrlen(fc)); |
b481de9c | 2568 | |
6440adb5 | 2569 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2570 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 2571 | rc = iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2572 | spin_unlock_irqrestore(&priv->lock, flags); |
2573 | ||
2574 | if (rc) | |
2575 | return rc; | |
2576 | ||
d20b3c65 | 2577 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
2578 | && priv->mac80211_registered) { |
2579 | if (wait_write_ptr) { | |
2580 | spin_lock_irqsave(&priv->lock, flags); | |
2581 | txq->need_update = 1; | |
bb8c093b | 2582 | iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2583 | spin_unlock_irqrestore(&priv->lock, flags); |
2584 | } | |
2585 | ||
e2530083 | 2586 | ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb)); |
b481de9c ZY |
2587 | } |
2588 | ||
2589 | return 0; | |
2590 | ||
2591 | drop_unlock: | |
2592 | spin_unlock_irqrestore(&priv->lock, flags); | |
2593 | drop: | |
2594 | return -1; | |
2595 | } | |
2596 | ||
4a8a4322 | 2597 | static void iwl3945_set_rate(struct iwl_priv *priv) |
b481de9c | 2598 | { |
8318d78a | 2599 | const struct ieee80211_supported_band *sband = NULL; |
b481de9c ZY |
2600 | struct ieee80211_rate *rate; |
2601 | int i; | |
2602 | ||
8318d78a JB |
2603 | sband = iwl3945_get_band(priv, priv->band); |
2604 | if (!sband) { | |
c4ba9621 SA |
2605 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); |
2606 | return; | |
2607 | } | |
b481de9c ZY |
2608 | |
2609 | priv->active_rate = 0; | |
2610 | priv->active_rate_basic = 0; | |
2611 | ||
8318d78a JB |
2612 | IWL_DEBUG_RATE("Setting rates for %s GHz\n", |
2613 | sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5"); | |
2614 | ||
2615 | for (i = 0; i < sband->n_bitrates; i++) { | |
2616 | rate = &sband->bitrates[i]; | |
2617 | if ((rate->hw_value < IWL_RATE_COUNT) && | |
2618 | !(rate->flags & IEEE80211_CHAN_DISABLED)) { | |
2619 | IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n", | |
2620 | rate->hw_value, iwl3945_rates[rate->hw_value].plcp); | |
2621 | priv->active_rate |= (1 << rate->hw_value); | |
2622 | } | |
b481de9c ZY |
2623 | } |
2624 | ||
2625 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2626 | priv->active_rate, priv->active_rate_basic); | |
2627 | ||
2628 | /* | |
2629 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2630 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2631 | * OFDM | |
2632 | */ | |
2633 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
f2c7e521 | 2634 | priv->staging39_rxon.cck_basic_rates = |
b481de9c ZY |
2635 | ((priv->active_rate_basic & |
2636 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2637 | else | |
f2c7e521 | 2638 | priv->staging39_rxon.cck_basic_rates = |
b481de9c ZY |
2639 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
2640 | ||
2641 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
f2c7e521 | 2642 | priv->staging39_rxon.ofdm_basic_rates = |
b481de9c ZY |
2643 | ((priv->active_rate_basic & |
2644 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2645 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2646 | else | |
f2c7e521 | 2647 | priv->staging39_rxon.ofdm_basic_rates = |
b481de9c ZY |
2648 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
2649 | } | |
2650 | ||
4a8a4322 | 2651 | static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio) |
b481de9c ZY |
2652 | { |
2653 | unsigned long flags; | |
2654 | ||
2655 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2656 | return; | |
2657 | ||
2658 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2659 | disable_radio ? "OFF" : "ON"); | |
2660 | ||
2661 | if (disable_radio) { | |
bb8c093b | 2662 | iwl3945_scan_cancel(priv); |
b481de9c | 2663 | /* FIXME: This is a workaround for AP */ |
05c914fe | 2664 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
b481de9c | 2665 | spin_lock_irqsave(&priv->lock, flags); |
5d49f498 | 2666 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2667 | CSR_UCODE_SW_BIT_RFKILL); |
2668 | spin_unlock_irqrestore(&priv->lock, flags); | |
bb8c093b | 2669 | iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); |
b481de9c ZY |
2670 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
2671 | } | |
2672 | return; | |
2673 | } | |
2674 | ||
2675 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 2676 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2677 | |
2678 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2679 | spin_unlock_irqrestore(&priv->lock, flags); | |
2680 | ||
2681 | /* wake up ucode */ | |
2682 | msleep(10); | |
2683 | ||
2684 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 AK |
2685 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
2686 | if (!iwl_grab_nic_access(priv)) | |
2687 | iwl_release_nic_access(priv); | |
b481de9c ZY |
2688 | spin_unlock_irqrestore(&priv->lock, flags); |
2689 | ||
2690 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2691 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2692 | "disabled by HW switch\n"); | |
2693 | return; | |
2694 | } | |
2695 | ||
808e72a0 ZY |
2696 | if (priv->is_open) |
2697 | queue_work(priv->workqueue, &priv->restart); | |
b481de9c ZY |
2698 | return; |
2699 | } | |
2700 | ||
4a8a4322 | 2701 | void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2702 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2703 | { | |
2704 | u16 fc = | |
2705 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2706 | ||
f2c7e521 | 2707 | if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) |
b481de9c ZY |
2708 | return; |
2709 | ||
2710 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2711 | return; | |
2712 | ||
2713 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2714 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2715 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2716 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2717 | RX_RES_STATUS_BAD_ICV_MIC) | |
2718 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2719 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2720 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2721 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2722 | RX_RES_STATUS_DECRYPT_OK) { | |
2723 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2724 | stats->flag |= RX_FLAG_DECRYPTED; | |
2725 | } | |
2726 | break; | |
2727 | ||
2728 | default: | |
2729 | break; | |
2730 | } | |
2731 | } | |
2732 | ||
c8b0e6e1 | 2733 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2734 | |
2735 | #include "iwl-spectrum.h" | |
2736 | ||
2737 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2738 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2739 | #define TIME_UNIT 1024 | |
2740 | ||
2741 | /* | |
2742 | * extended beacon time format | |
2743 | * time in usec will be changed into a 32-bit value in 8:24 format | |
2744 | * the high 1 byte is the beacon counts | |
2745 | * the lower 3 bytes is the time in usec within one beacon interval | |
2746 | */ | |
2747 | ||
bb8c093b | 2748 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
2749 | { |
2750 | u32 quot; | |
2751 | u32 rem; | |
2752 | u32 interval = beacon_interval * 1024; | |
2753 | ||
2754 | if (!interval || !usec) | |
2755 | return 0; | |
2756 | ||
2757 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
2758 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
2759 | ||
2760 | return (quot << 24) + rem; | |
2761 | } | |
2762 | ||
2763 | /* base is usually what we get from ucode with each received frame, | |
2764 | * the same as HW timer counter counting down | |
2765 | */ | |
2766 | ||
bb8c093b | 2767 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
2768 | { |
2769 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
2770 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
2771 | u32 interval = beacon_interval * TIME_UNIT; | |
2772 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
2773 | (addon & BEACON_TIME_MASK_HIGH); | |
2774 | ||
2775 | if (base_low > addon_low) | |
2776 | res += base_low - addon_low; | |
2777 | else if (base_low < addon_low) { | |
2778 | res += interval + base_low - addon_low; | |
2779 | res += (1 << 24); | |
2780 | } else | |
2781 | res += (1 << 24); | |
2782 | ||
2783 | return cpu_to_le32(res); | |
2784 | } | |
2785 | ||
4a8a4322 | 2786 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
2787 | struct ieee80211_measurement_params *params, |
2788 | u8 type) | |
2789 | { | |
600c0e11 | 2790 | struct iwl_spectrum_cmd spectrum; |
3d24a9f7 | 2791 | struct iwl_rx_packet *res; |
bb8c093b | 2792 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
2793 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
2794 | .data = (void *)&spectrum, | |
2795 | .meta.flags = CMD_WANT_SKB, | |
2796 | }; | |
2797 | u32 add_time = le64_to_cpu(params->start_time); | |
2798 | int rc; | |
2799 | int spectrum_resp_status; | |
2800 | int duration = le16_to_cpu(params->duration); | |
2801 | ||
bb8c093b | 2802 | if (iwl3945_is_associated(priv)) |
b481de9c | 2803 | add_time = |
bb8c093b | 2804 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
2805 | le64_to_cpu(params->start_time) - priv->last_tsf, |
2806 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2807 | ||
2808 | memset(&spectrum, 0, sizeof(spectrum)); | |
2809 | ||
2810 | spectrum.channel_count = cpu_to_le16(1); | |
2811 | spectrum.flags = | |
2812 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
2813 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
2814 | cmd.len = sizeof(spectrum); | |
2815 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
2816 | ||
bb8c093b | 2817 | if (iwl3945_is_associated(priv)) |
b481de9c | 2818 | spectrum.start_time = |
bb8c093b | 2819 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
2820 | add_time, |
2821 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2822 | else | |
2823 | spectrum.start_time = 0; | |
2824 | ||
2825 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
2826 | spectrum.channels[0].channel = params->channel; | |
2827 | spectrum.channels[0].type = type; | |
f2c7e521 | 2828 | if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
2829 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
2830 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
2831 | ||
bb8c093b | 2832 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2833 | if (rc) |
2834 | return rc; | |
2835 | ||
3d24a9f7 | 2836 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
2837 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
2838 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
2839 | rc = -EIO; | |
2840 | } | |
2841 | ||
2842 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
2843 | switch (spectrum_resp_status) { | |
2844 | case 0: /* Command will be handled */ | |
2845 | if (res->u.spectrum.id != 0xff) { | |
bc434dd2 IS |
2846 | IWL_DEBUG_INFO("Replaced existing measurement: %d\n", |
2847 | res->u.spectrum.id); | |
b481de9c ZY |
2848 | priv->measurement_status &= ~MEASUREMENT_READY; |
2849 | } | |
2850 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
2851 | rc = 0; | |
2852 | break; | |
2853 | ||
2854 | case 1: /* Command will not be handled */ | |
2855 | rc = -EAGAIN; | |
2856 | break; | |
2857 | } | |
2858 | ||
2859 | dev_kfree_skb_any(cmd.meta.u.skb); | |
2860 | ||
2861 | return rc; | |
2862 | } | |
2863 | #endif | |
2864 | ||
4a8a4322 | 2865 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 2866 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2867 | { |
3d24a9f7 TW |
2868 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
2869 | struct iwl_alive_resp *palive; | |
b481de9c ZY |
2870 | struct delayed_work *pwork; |
2871 | ||
2872 | palive = &pkt->u.alive_frame; | |
2873 | ||
2874 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
2875 | "0x%01X 0x%01X\n", | |
2876 | palive->is_valid, palive->ver_type, | |
2877 | palive->ver_subtype); | |
2878 | ||
2879 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
2880 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3d24a9f7 TW |
2881 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
2882 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
2883 | pwork = &priv->init_alive_start; |
2884 | } else { | |
2885 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
2886 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
3d24a9f7 | 2887 | sizeof(struct iwl_alive_resp)); |
b481de9c | 2888 | pwork = &priv->alive_start; |
bb8c093b | 2889 | iwl3945_disable_events(priv); |
b481de9c ZY |
2890 | } |
2891 | ||
2892 | /* We delay the ALIVE response by 5ms to | |
2893 | * give the HW RF Kill time to activate... */ | |
2894 | if (palive->is_valid == UCODE_VALID_OK) | |
2895 | queue_delayed_work(priv->workqueue, pwork, | |
2896 | msecs_to_jiffies(5)); | |
2897 | else | |
2898 | IWL_WARNING("uCode did not respond OK.\n"); | |
2899 | } | |
2900 | ||
4a8a4322 | 2901 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 2902 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2903 | { |
3d24a9f7 | 2904 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2905 | |
2906 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
2907 | return; | |
2908 | } | |
2909 | ||
4a8a4322 | 2910 | static void iwl3945_rx_reply_error(struct iwl_priv *priv, |
6100b588 | 2911 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2912 | { |
3d24a9f7 | 2913 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2914 | |
2915 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
2916 | "seq 0x%04X ser 0x%08X\n", | |
2917 | le32_to_cpu(pkt->u.err_resp.error_type), | |
2918 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
2919 | pkt->u.err_resp.cmd_id, | |
2920 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
2921 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
2922 | } | |
2923 | ||
2924 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
2925 | ||
4a8a4322 | 2926 | static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2927 | { |
3d24a9f7 | 2928 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
f2c7e521 | 2929 | struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon; |
600c0e11 | 2930 | struct iwl_csa_notification *csa = &(pkt->u.csa_notif); |
b481de9c ZY |
2931 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
2932 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
2933 | rxon->channel = csa->channel; | |
f2c7e521 | 2934 | priv->staging39_rxon.channel = csa->channel; |
b481de9c ZY |
2935 | } |
2936 | ||
4a8a4322 | 2937 | static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv, |
6100b588 | 2938 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2939 | { |
c8b0e6e1 | 2940 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
3d24a9f7 | 2941 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
600c0e11 | 2942 | struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif); |
b481de9c ZY |
2943 | |
2944 | if (!report->state) { | |
2945 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
2946 | "Spectrum Measure Notification: Start\n"); | |
2947 | return; | |
2948 | } | |
2949 | ||
2950 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
2951 | priv->measurement_status |= MEASUREMENT_READY; | |
2952 | #endif | |
2953 | } | |
2954 | ||
4a8a4322 | 2955 | static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv, |
6100b588 | 2956 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2957 | { |
c8b0e6e1 | 2958 | #ifdef CONFIG_IWL3945_DEBUG |
3d24a9f7 | 2959 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
600c0e11 | 2960 | struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif); |
b481de9c ZY |
2961 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
2962 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
2963 | #endif | |
2964 | } | |
2965 | ||
4a8a4322 | 2966 | static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
6100b588 | 2967 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2968 | { |
3d24a9f7 | 2969 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2970 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
2971 | "notification for %s:\n", | |
2972 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
40b8ec0b SO |
2973 | iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, |
2974 | le32_to_cpu(pkt->len)); | |
b481de9c ZY |
2975 | } |
2976 | ||
bb8c093b | 2977 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 2978 | { |
4a8a4322 AK |
2979 | struct iwl_priv *priv = |
2980 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
2981 | struct sk_buff *beacon; |
2982 | ||
2983 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 2984 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
2985 | |
2986 | if (!beacon) { | |
2987 | IWL_ERROR("update beacon failed\n"); | |
2988 | return; | |
2989 | } | |
2990 | ||
2991 | mutex_lock(&priv->mutex); | |
2992 | /* new beacon skb is allocated every time; dispose previous.*/ | |
2993 | if (priv->ibss_beacon) | |
2994 | dev_kfree_skb(priv->ibss_beacon); | |
2995 | ||
2996 | priv->ibss_beacon = beacon; | |
2997 | mutex_unlock(&priv->mutex); | |
2998 | ||
bb8c093b | 2999 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3000 | } |
3001 | ||
4a8a4322 | 3002 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 3003 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3004 | { |
c8b0e6e1 | 3005 | #ifdef CONFIG_IWL3945_DEBUG |
3d24a9f7 | 3006 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
bb8c093b | 3007 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
3008 | u8 rate = beacon->beacon_notify_hdr.rate; |
3009 | ||
3010 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3011 | "tsf %d %d rate %d\n", | |
3012 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3013 | beacon->beacon_notify_hdr.failure_frame, | |
3014 | le32_to_cpu(beacon->ibss_mgr_status), | |
3015 | le32_to_cpu(beacon->high_tsf), | |
3016 | le32_to_cpu(beacon->low_tsf), rate); | |
3017 | #endif | |
3018 | ||
05c914fe | 3019 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
3020 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
3021 | queue_work(priv->workqueue, &priv->beacon_update); | |
3022 | } | |
3023 | ||
3024 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
4a8a4322 | 3025 | static void iwl3945_rx_reply_scan(struct iwl_priv *priv, |
6100b588 | 3026 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3027 | { |
c8b0e6e1 | 3028 | #ifdef CONFIG_IWL3945_DEBUG |
3d24a9f7 | 3029 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 TW |
3030 | struct iwl_scanreq_notification *notif = |
3031 | (struct iwl_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3032 | |
3033 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3034 | #endif | |
3035 | } | |
3036 | ||
3037 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
4a8a4322 | 3038 | static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv, |
6100b588 | 3039 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3040 | { |
3d24a9f7 | 3041 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 TW |
3042 | struct iwl_scanstart_notification *notif = |
3043 | (struct iwl_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3044 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3045 | IWL_DEBUG_SCAN("Scan start: " | |
3046 | "%d [802.11%s] " | |
3047 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3048 | notif->channel, | |
3049 | notif->band ? "bg" : "a", | |
3050 | notif->tsf_high, | |
3051 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3052 | } | |
3053 | ||
3054 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
4a8a4322 | 3055 | static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv, |
6100b588 | 3056 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3057 | { |
3d24a9f7 | 3058 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 TW |
3059 | struct iwl_scanresults_notification *notif = |
3060 | (struct iwl_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3061 | |
3062 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3063 | "%d [802.11%s] " | |
3064 | "(TSF: 0x%08X:%08X) - %d " | |
3065 | "elapsed=%lu usec (%dms since last)\n", | |
3066 | notif->channel, | |
3067 | notif->band ? "bg" : "a", | |
3068 | le32_to_cpu(notif->tsf_high), | |
3069 | le32_to_cpu(notif->tsf_low), | |
3070 | le32_to_cpu(notif->statistics[0]), | |
3071 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3072 | jiffies_to_msecs(elapsed_jiffies | |
3073 | (priv->last_scan_jiffies, jiffies))); | |
3074 | ||
3075 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3076 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3077 | } |
3078 | ||
3079 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
4a8a4322 | 3080 | static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv, |
6100b588 | 3081 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3082 | { |
3d24a9f7 | 3083 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 | 3084 | struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw; |
b481de9c ZY |
3085 | |
3086 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3087 | scan_notif->scanned_channels, | |
3088 | scan_notif->tsf_low, | |
3089 | scan_notif->tsf_high, scan_notif->status); | |
3090 | ||
3091 | /* The HW is no longer scanning */ | |
3092 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3093 | ||
3094 | /* The scan completion notification came in, so kill that timer... */ | |
3095 | cancel_delayed_work(&priv->scan_check); | |
3096 | ||
3097 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
66b5004d RR |
3098 | (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ? |
3099 | "2.4" : "5.2", | |
b481de9c ZY |
3100 | jiffies_to_msecs(elapsed_jiffies |
3101 | (priv->scan_pass_start, jiffies))); | |
3102 | ||
66b5004d RR |
3103 | /* Remove this scanned band from the list of pending |
3104 | * bands to scan, band G precedes A in order of scanning | |
3105 | * as seen in iwl3945_bg_request_scan */ | |
3106 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) | |
3107 | priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ); | |
3108 | else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) | |
3109 | priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ); | |
b481de9c ZY |
3110 | |
3111 | /* If a request to abort was given, or the scan did not succeed | |
3112 | * then we reset the scan state machine and terminate, | |
3113 | * re-queuing another scan if one has been requested */ | |
3114 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3115 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3116 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3117 | } else { | |
3118 | /* If there are more bands on this scan pass reschedule */ | |
3119 | if (priv->scan_bands > 0) | |
3120 | goto reschedule; | |
3121 | } | |
3122 | ||
3123 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3124 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3125 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3126 | ||
3127 | clear_bit(STATUS_SCANNING, &priv->status); | |
3128 | ||
3129 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3130 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3131 | ||
3132 | queue_work(priv->workqueue, &priv->scan_completed); | |
3133 | ||
3134 | return; | |
3135 | ||
3136 | reschedule: | |
3137 | priv->scan_pass_start = jiffies; | |
3138 | queue_work(priv->workqueue, &priv->request_scan); | |
3139 | } | |
3140 | ||
3141 | /* Handle notification from uCode that card's power state is changing | |
3142 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 3143 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 3144 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3145 | { |
3d24a9f7 | 3146 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3147 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3148 | unsigned long status = priv->status; | |
3149 | ||
3150 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3151 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3152 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3153 | ||
5d49f498 | 3154 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3155 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3156 | ||
3157 | if (flags & HW_CARD_DISABLED) | |
3158 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3159 | else | |
3160 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3161 | ||
3162 | ||
3163 | if (flags & SW_CARD_DISABLED) | |
3164 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3165 | else | |
3166 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3167 | ||
bb8c093b | 3168 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
3169 | |
3170 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3171 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3172 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3173 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3174 | queue_work(priv->workqueue, &priv->rf_kill); | |
3175 | else | |
3176 | wake_up_interruptible(&priv->wait_command_queue); | |
3177 | } | |
3178 | ||
3179 | /** | |
bb8c093b | 3180 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3181 | * |
3182 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3183 | * to the host. | |
3184 | * | |
3185 | * This function chains into the hardware specific files for them to setup | |
3186 | * any hardware specific handlers as well. | |
3187 | */ | |
4a8a4322 | 3188 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 3189 | { |
bb8c093b CH |
3190 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
3191 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
3192 | priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error; | |
3193 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa; | |
b481de9c | 3194 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3195 | iwl3945_rx_spectrum_measure_notif; |
3196 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif; | |
b481de9c | 3197 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3198 | iwl3945_rx_pm_debug_statistics_notif; |
3199 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; | |
b481de9c | 3200 | |
9fbab516 BC |
3201 | /* |
3202 | * The same handler is used for both the REPLY to a discrete | |
3203 | * statistics request from the host as well as for the periodic | |
3204 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3205 | */ |
bb8c093b CH |
3206 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
3207 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 3208 | |
bb8c093b CH |
3209 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan; |
3210 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif; | |
b481de9c | 3211 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3212 | iwl3945_rx_scan_results_notif; |
b481de9c | 3213 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3214 | iwl3945_rx_scan_complete_notif; |
3215 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; | |
b481de9c | 3216 | |
9fbab516 | 3217 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3218 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
3219 | } |
3220 | ||
91c066f2 TW |
3221 | /** |
3222 | * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries | |
3223 | * When FW advances 'R' index, all entries between old and new 'R' index | |
3224 | * need to be reclaimed. | |
3225 | */ | |
4a8a4322 | 3226 | static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv, |
91c066f2 TW |
3227 | int txq_id, int index) |
3228 | { | |
f2c7e521 | 3229 | struct iwl3945_tx_queue *txq = &priv->txq39[txq_id]; |
d20b3c65 | 3230 | struct iwl_queue *q = &txq->q; |
91c066f2 TW |
3231 | int nfreed = 0; |
3232 | ||
3233 | if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) { | |
3234 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
3235 | "is out of range [0-%d] %d %d.\n", txq_id, | |
3236 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
3237 | return; | |
3238 | } | |
3239 | ||
3240 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
3241 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
3242 | if (nfreed > 1) { | |
3243 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
3244 | q->write_ptr, q->read_ptr); | |
3245 | queue_work(priv->workqueue, &priv->restart); | |
3246 | break; | |
3247 | } | |
3248 | nfreed++; | |
3249 | } | |
3250 | } | |
3251 | ||
3252 | ||
b481de9c | 3253 | /** |
bb8c093b | 3254 | * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3255 | * @rxb: Rx buffer to reclaim |
3256 | * | |
3257 | * If an Rx buffer has an async callback associated with it the callback | |
3258 | * will be executed. The attached skb (if present) will only be freed | |
3259 | * if the callback returns 1 | |
3260 | */ | |
4a8a4322 | 3261 | static void iwl3945_tx_cmd_complete(struct iwl_priv *priv, |
6100b588 | 3262 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3263 | { |
3d24a9f7 | 3264 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3265 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3266 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3267 | int index = SEQ_TO_INDEX(sequence); | |
600c0e11 | 3268 | int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
b481de9c | 3269 | int cmd_index; |
bb8c093b | 3270 | struct iwl3945_cmd *cmd; |
b481de9c | 3271 | |
b481de9c ZY |
3272 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); |
3273 | ||
f2c7e521 AK |
3274 | cmd_index = get_cmd_index(&priv->txq39[IWL_CMD_QUEUE_NUM].q, index, huge); |
3275 | cmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
b481de9c ZY |
3276 | |
3277 | /* Input error checking is done when commands are added to queue. */ | |
3278 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3279 | cmd->meta.source->u.skb = rxb->skb; | |
3280 | rxb->skb = NULL; | |
3281 | } else if (cmd->meta.u.callback && | |
3282 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3283 | rxb->skb = NULL; | |
3284 | ||
91c066f2 | 3285 | iwl3945_cmd_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3286 | |
3287 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3288 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3289 | wake_up_interruptible(&priv->wait_command_queue); | |
3290 | } | |
3291 | } | |
3292 | ||
3293 | /************************** RX-FUNCTIONS ****************************/ | |
3294 | /* | |
3295 | * Rx theory of operation | |
3296 | * | |
3297 | * The host allocates 32 DMA target addresses and passes the host address | |
3298 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
3299 | * 0 to 31 | |
3300 | * | |
3301 | * Rx Queue Indexes | |
3302 | * The host/firmware share two index registers for managing the Rx buffers. | |
3303 | * | |
3304 | * The READ index maps to the first position that the firmware may be writing | |
3305 | * to -- the driver can read up to (but not including) this position and get | |
3306 | * good data. | |
3307 | * The READ index is managed by the firmware once the card is enabled. | |
3308 | * | |
3309 | * The WRITE index maps to the last position the driver has read from -- the | |
3310 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3311 | * | |
3312 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3313 | * WRITE = READ. | |
3314 | * | |
9fbab516 | 3315 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3316 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3317 | * | |
9fbab516 | 3318 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3319 | * and fire the RX interrupt. The driver can then query the READ index and |
3320 | * process as many packets as possible, moving the WRITE index forward as it | |
3321 | * resets the Rx queue buffers with new memory. | |
3322 | * | |
3323 | * The management in the driver is as follows: | |
3324 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3325 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3326 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3327 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3328 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3329 | * 'processed' and 'read' driver indexes as well) | |
3330 | * + A received packet is processed and handed to the kernel network stack, | |
3331 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3332 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3333 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3334 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3335 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3336 | * | |
3337 | * | |
3338 | * Driver sequence: | |
3339 | * | |
9fbab516 BC |
3340 | * iwl3945_rx_queue_alloc() Allocates rx_free |
3341 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3342 | * iwl3945_rx_queue_restock |
9fbab516 | 3343 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3344 | * queue, updates firmware pointers, and updates |
3345 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3346 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
3347 | * |
3348 | * -- enable interrupts -- | |
6100b588 | 3349 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
3350 | * READ INDEX, detaching the SKB from the pool. |
3351 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3352 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
3353 | * slots. |
3354 | * ... | |
3355 | * | |
3356 | */ | |
3357 | ||
3358 | /** | |
bb8c093b | 3359 | * iwl3945_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3360 | */ |
cc2f362c | 3361 | static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q) |
b481de9c ZY |
3362 | { |
3363 | int s = q->read - q->write; | |
3364 | if (s <= 0) | |
3365 | s += RX_QUEUE_SIZE; | |
3366 | /* keep some buffer to not confuse full and empty queue */ | |
3367 | s -= 2; | |
3368 | if (s < 0) | |
3369 | s = 0; | |
3370 | return s; | |
3371 | } | |
3372 | ||
3373 | /** | |
bb8c093b | 3374 | * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3375 | */ |
4a8a4322 | 3376 | int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q) |
b481de9c ZY |
3377 | { |
3378 | u32 reg = 0; | |
3379 | int rc = 0; | |
3380 | unsigned long flags; | |
3381 | ||
3382 | spin_lock_irqsave(&q->lock, flags); | |
3383 | ||
3384 | if (q->need_update == 0) | |
3385 | goto exit_unlock; | |
3386 | ||
6440adb5 | 3387 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3388 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
5d49f498 | 3389 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3390 | |
3391 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
5d49f498 | 3392 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3393 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3394 | goto exit_unlock; | |
3395 | } | |
3396 | ||
5d49f498 | 3397 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
3398 | if (rc) |
3399 | goto exit_unlock; | |
3400 | ||
6440adb5 | 3401 | /* Device expects a multiple of 8 */ |
5d49f498 | 3402 | iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR, |
b481de9c | 3403 | q->write & ~0x7); |
5d49f498 | 3404 | iwl_release_nic_access(priv); |
6440adb5 BC |
3405 | |
3406 | /* Else device is assumed to be awake */ | |
b481de9c | 3407 | } else |
6440adb5 | 3408 | /* Device expects a multiple of 8 */ |
5d49f498 | 3409 | iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3410 | |
3411 | ||
3412 | q->need_update = 0; | |
3413 | ||
3414 | exit_unlock: | |
3415 | spin_unlock_irqrestore(&q->lock, flags); | |
3416 | return rc; | |
3417 | } | |
3418 | ||
3419 | /** | |
9fbab516 | 3420 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3421 | */ |
4a8a4322 | 3422 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
3423 | dma_addr_t dma_addr) |
3424 | { | |
3425 | return cpu_to_le32((u32)dma_addr); | |
3426 | } | |
3427 | ||
3428 | /** | |
bb8c093b | 3429 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3430 | * |
9fbab516 | 3431 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3432 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3433 | * as we can, pulling from rx_free. |
b481de9c ZY |
3434 | * |
3435 | * This moves the 'write' index forward to catch up with 'processed', and | |
3436 | * also updates the memory address in the firmware to reference the new | |
3437 | * target buffer. | |
3438 | */ | |
4a8a4322 | 3439 | static int iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 3440 | { |
cc2f362c | 3441 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 3442 | struct list_head *element; |
6100b588 | 3443 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
3444 | unsigned long flags; |
3445 | int write, rc; | |
3446 | ||
3447 | spin_lock_irqsave(&rxq->lock, flags); | |
3448 | write = rxq->write & ~0x7; | |
bb8c093b | 3449 | while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3450 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3451 | element = rxq->rx_free.next; |
6100b588 | 3452 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 3453 | list_del(element); |
6440adb5 BC |
3454 | |
3455 | /* Point to Rx buffer via next RBD in circular buffer */ | |
6100b588 | 3456 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr); |
b481de9c ZY |
3457 | rxq->queue[rxq->write] = rxb; |
3458 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3459 | rxq->free_count--; | |
3460 | } | |
3461 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3462 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3463 | * refill it */ | |
3464 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3465 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3466 | ||
3467 | ||
6440adb5 BC |
3468 | /* If we've added more space for the firmware to place data, tell it. |
3469 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3470 | if ((write != (rxq->write & ~0x7)) |
3471 | || (abs(rxq->write - rxq->read) > 7)) { | |
3472 | spin_lock_irqsave(&rxq->lock, flags); | |
3473 | rxq->need_update = 1; | |
3474 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3475 | rc = iwl3945_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3476 | if (rc) |
3477 | return rc; | |
3478 | } | |
3479 | ||
3480 | return 0; | |
3481 | } | |
3482 | ||
3483 | /** | |
bb8c093b | 3484 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3485 | * |
3486 | * When moving to rx_free an SKB is allocated for the slot. | |
3487 | * | |
bb8c093b | 3488 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 3489 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3490 | */ |
4a8a4322 | 3491 | static void iwl3945_rx_allocate(struct iwl_priv *priv) |
b481de9c | 3492 | { |
cc2f362c | 3493 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 3494 | struct list_head *element; |
6100b588 | 3495 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
3496 | unsigned long flags; |
3497 | spin_lock_irqsave(&rxq->lock, flags); | |
3498 | while (!list_empty(&rxq->rx_used)) { | |
3499 | element = rxq->rx_used.next; | |
6100b588 | 3500 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
6440adb5 BC |
3501 | |
3502 | /* Alloc a new receive buffer */ | |
b481de9c ZY |
3503 | rxb->skb = |
3504 | alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC); | |
3505 | if (!rxb->skb) { | |
3506 | if (net_ratelimit()) | |
3507 | printk(KERN_CRIT DRV_NAME | |
3508 | ": Can not allocate SKB buffers\n"); | |
3509 | /* We don't reschedule replenish work here -- we will | |
3510 | * call the restock method and if it still needs | |
3511 | * more buffers it will schedule replenish */ | |
3512 | break; | |
3513 | } | |
12342c47 ZY |
3514 | |
3515 | /* If radiotap head is required, reserve some headroom here. | |
3516 | * The physical head count is a variable rx_stats->phy_count. | |
3517 | * We reserve 4 bytes here. Plus these extra bytes, the | |
3518 | * headroom of the physical head should be enough for the | |
3519 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
3520 | */ | |
3521 | skb_reserve(rxb->skb, 4); | |
3522 | ||
b481de9c ZY |
3523 | priv->alloc_rxb_skb++; |
3524 | list_del(element); | |
6440adb5 BC |
3525 | |
3526 | /* Get physical address of RB/SKB */ | |
6100b588 | 3527 | rxb->real_dma_addr = |
b481de9c ZY |
3528 | pci_map_single(priv->pci_dev, rxb->skb->data, |
3529 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3530 | list_add_tail(&rxb->list, &rxq->rx_free); | |
3531 | rxq->free_count++; | |
3532 | } | |
3533 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3534 | } |
3535 | ||
3536 | /* | |
3537 | * this should be called while priv->lock is locked | |
3538 | */ | |
4fd1f841 | 3539 | static void __iwl3945_rx_replenish(void *data) |
5c0eef96 | 3540 | { |
4a8a4322 | 3541 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3542 | |
3543 | iwl3945_rx_allocate(priv); | |
3544 | iwl3945_rx_queue_restock(priv); | |
3545 | } | |
3546 | ||
3547 | ||
3548 | void iwl3945_rx_replenish(void *data) | |
3549 | { | |
4a8a4322 | 3550 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3551 | unsigned long flags; |
3552 | ||
3553 | iwl3945_rx_allocate(priv); | |
b481de9c ZY |
3554 | |
3555 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3556 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3557 | spin_unlock_irqrestore(&priv->lock, flags); |
3558 | } | |
3559 | ||
3560 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3561 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3562 | * This free routine walks the list of POOL entries and if SKB is set to |
3563 | * non NULL it is unmapped and freed | |
3564 | */ | |
4a8a4322 | 3565 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
b481de9c ZY |
3566 | { |
3567 | int i; | |
3568 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3569 | if (rxq->pool[i].skb != NULL) { | |
3570 | pci_unmap_single(priv->pci_dev, | |
6100b588 | 3571 | rxq->pool[i].real_dma_addr, |
b481de9c ZY |
3572 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
3573 | dev_kfree_skb(rxq->pool[i].skb); | |
3574 | } | |
3575 | } | |
3576 | ||
3577 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3578 | rxq->dma_addr); | |
3579 | rxq->bd = NULL; | |
3580 | } | |
3581 | ||
4a8a4322 | 3582 | int iwl3945_rx_queue_alloc(struct iwl_priv *priv) |
b481de9c | 3583 | { |
cc2f362c | 3584 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3585 | struct pci_dev *dev = priv->pci_dev; |
3586 | int i; | |
3587 | ||
3588 | spin_lock_init(&rxq->lock); | |
3589 | INIT_LIST_HEAD(&rxq->rx_free); | |
3590 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 BC |
3591 | |
3592 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3593 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3594 | if (!rxq->bd) | |
3595 | return -ENOMEM; | |
6440adb5 | 3596 | |
b481de9c ZY |
3597 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3598 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3599 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3600 | |
b481de9c ZY |
3601 | /* Set us so that we have processed and used all buffers, but have |
3602 | * not restocked the Rx queue with fresh buffers */ | |
3603 | rxq->read = rxq->write = 0; | |
3604 | rxq->free_count = 0; | |
3605 | rxq->need_update = 0; | |
3606 | return 0; | |
3607 | } | |
3608 | ||
4a8a4322 | 3609 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
b481de9c ZY |
3610 | { |
3611 | unsigned long flags; | |
3612 | int i; | |
3613 | spin_lock_irqsave(&rxq->lock, flags); | |
3614 | INIT_LIST_HEAD(&rxq->rx_free); | |
3615 | INIT_LIST_HEAD(&rxq->rx_used); | |
3616 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
3617 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
3618 | /* In the reset function, these buffers may have been allocated | |
3619 | * to an SKB, so we need to unmap and free potential storage */ | |
3620 | if (rxq->pool[i].skb != NULL) { | |
3621 | pci_unmap_single(priv->pci_dev, | |
6100b588 | 3622 | rxq->pool[i].real_dma_addr, |
b481de9c ZY |
3623 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
3624 | priv->alloc_rxb_skb--; | |
3625 | dev_kfree_skb(rxq->pool[i].skb); | |
3626 | rxq->pool[i].skb = NULL; | |
3627 | } | |
3628 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
3629 | } | |
3630 | ||
3631 | /* Set us so that we have processed and used all buffers, but have | |
3632 | * not restocked the Rx queue with fresh buffers */ | |
3633 | rxq->read = rxq->write = 0; | |
3634 | rxq->free_count = 0; | |
3635 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3636 | } | |
3637 | ||
3638 | /* Convert linear signal-to-noise ratio into dB */ | |
3639 | static u8 ratio2dB[100] = { | |
3640 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3641 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3642 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3643 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3644 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3645 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3646 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3647 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3648 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3649 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3650 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3651 | }; | |
3652 | ||
3653 | /* Calculates a relative dB value from a ratio of linear | |
3654 | * (i.e. not dB) signal levels. | |
3655 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 3656 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 3657 | { |
221c80cf AB |
3658 | /* 1000:1 or higher just report as 60 dB */ |
3659 | if (sig_ratio >= 1000) | |
b481de9c ZY |
3660 | return 60; |
3661 | ||
221c80cf | 3662 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 3663 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 3664 | if (sig_ratio >= 100) |
3ac7f146 | 3665 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
3666 | |
3667 | /* We shouldn't see this */ | |
3668 | if (sig_ratio < 1) | |
3669 | return 0; | |
3670 | ||
3671 | /* Use table for ratios 1:1 - 99:1 */ | |
3672 | return (int)ratio2dB[sig_ratio]; | |
3673 | } | |
3674 | ||
3675 | #define PERFECT_RSSI (-20) /* dBm */ | |
3676 | #define WORST_RSSI (-95) /* dBm */ | |
3677 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
3678 | ||
3679 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
3680 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
3681 | * about formulas used below. */ | |
bb8c093b | 3682 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
3683 | { |
3684 | int sig_qual; | |
3685 | int degradation = PERFECT_RSSI - rssi_dbm; | |
3686 | ||
3687 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
3688 | * as indicator; formula is (signal dbm - noise dbm). | |
3689 | * SNR at or above 40 is a great signal (100%). | |
3690 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
3691 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
3692 | if (noise_dbm) { | |
3693 | if (rssi_dbm - noise_dbm >= 40) | |
3694 | return 100; | |
3695 | else if (rssi_dbm < noise_dbm) | |
3696 | return 0; | |
3697 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
3698 | ||
3699 | /* Else use just the signal level. | |
3700 | * This formula is a least squares fit of data points collected and | |
3701 | * compared with a reference system that had a percentage (%) display | |
3702 | * for signal quality. */ | |
3703 | } else | |
3704 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
3705 | (15 * RSSI_RANGE + 62 * degradation)) / | |
3706 | (RSSI_RANGE * RSSI_RANGE); | |
3707 | ||
3708 | if (sig_qual > 100) | |
3709 | sig_qual = 100; | |
3710 | else if (sig_qual < 1) | |
3711 | sig_qual = 0; | |
3712 | ||
3713 | return sig_qual; | |
3714 | } | |
3715 | ||
3716 | /** | |
9fbab516 | 3717 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
3718 | * |
3719 | * Uses the priv->rx_handlers callback function array to invoke | |
3720 | * the appropriate handlers, including command responses, | |
3721 | * frame-received notifications, and other notifications. | |
3722 | */ | |
4a8a4322 | 3723 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 3724 | { |
6100b588 | 3725 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 3726 | struct iwl_rx_packet *pkt; |
cc2f362c | 3727 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3728 | u32 r, i; |
3729 | int reclaim; | |
3730 | unsigned long flags; | |
5c0eef96 | 3731 | u8 fill_rx = 0; |
d68ab680 | 3732 | u32 count = 8; |
b481de9c | 3733 | |
6440adb5 BC |
3734 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
3735 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 3736 | r = iwl3945_hw_get_rx_read(priv); |
b481de9c ZY |
3737 | i = rxq->read; |
3738 | ||
5c0eef96 MA |
3739 | if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
3740 | fill_rx = 1; | |
b481de9c ZY |
3741 | /* Rx interrupt, but nothing sent from uCode */ |
3742 | if (i == r) | |
3743 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
3744 | ||
3745 | while (i != r) { | |
3746 | rxb = rxq->queue[i]; | |
3747 | ||
9fbab516 | 3748 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
3749 | * then a bug has been introduced in the queue refilling |
3750 | * routines -- catch it here */ | |
3751 | BUG_ON(rxb == NULL); | |
3752 | ||
3753 | rxq->queue[i] = NULL; | |
3754 | ||
6100b588 | 3755 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr, |
b481de9c ZY |
3756 | IWL_RX_BUF_SIZE, |
3757 | PCI_DMA_FROMDEVICE); | |
3d24a9f7 | 3758 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3759 | |
3760 | /* Reclaim a command buffer only if this packet is a response | |
3761 | * to a (driver-originated) command. | |
3762 | * If the packet (e.g. Rx frame) originated from uCode, | |
3763 | * there is no command buffer to reclaim. | |
3764 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
3765 | * but apparently a few don't get set; catch them here. */ | |
3766 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
3767 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
3768 | (pkt->hdr.cmd != REPLY_TX); | |
3769 | ||
3770 | /* Based on type of command response or notification, | |
3771 | * handle those that need handling via function in | |
bb8c093b | 3772 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 3773 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
40b8ec0b | 3774 | IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
3775 | "r = %d, i = %d, %s, 0x%02x\n", r, i, |
3776 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
3777 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
3778 | } else { | |
3779 | /* No handling needed */ | |
40b8ec0b | 3780 | IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
3781 | "r %d i %d No handler needed for %s, 0x%02x\n", |
3782 | r, i, get_cmd_string(pkt->hdr.cmd), | |
3783 | pkt->hdr.cmd); | |
3784 | } | |
3785 | ||
3786 | if (reclaim) { | |
9fbab516 BC |
3787 | /* Invoke any callbacks, transfer the skb to caller, and |
3788 | * fire off the (possibly) blocking iwl3945_send_cmd() | |
b481de9c ZY |
3789 | * as we reclaim the driver command queue */ |
3790 | if (rxb && rxb->skb) | |
bb8c093b | 3791 | iwl3945_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
3792 | else |
3793 | IWL_WARNING("Claim null rxb?\n"); | |
3794 | } | |
3795 | ||
3796 | /* For now we just don't re-use anything. We can tweak this | |
3797 | * later to try and re-use notification packets and SKBs that | |
3798 | * fail to Rx correctly */ | |
3799 | if (rxb->skb != NULL) { | |
3800 | priv->alloc_rxb_skb--; | |
3801 | dev_kfree_skb_any(rxb->skb); | |
3802 | rxb->skb = NULL; | |
3803 | } | |
3804 | ||
6100b588 | 3805 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
b481de9c ZY |
3806 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
3807 | spin_lock_irqsave(&rxq->lock, flags); | |
3808 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
3809 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3810 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
3811 | /* If there are a lot of unused frames, |
3812 | * restock the Rx queue so ucode won't assert. */ | |
3813 | if (fill_rx) { | |
3814 | count++; | |
3815 | if (count >= 8) { | |
3816 | priv->rxq.read = i; | |
3817 | __iwl3945_rx_replenish(priv); | |
3818 | count = 0; | |
3819 | } | |
3820 | } | |
b481de9c ZY |
3821 | } |
3822 | ||
3823 | /* Backtrack one entry */ | |
3824 | priv->rxq.read = i; | |
bb8c093b | 3825 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3826 | } |
3827 | ||
6440adb5 BC |
3828 | /** |
3829 | * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware | |
3830 | */ | |
4a8a4322 | 3831 | static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 3832 | struct iwl3945_tx_queue *txq) |
b481de9c ZY |
3833 | { |
3834 | u32 reg = 0; | |
3835 | int rc = 0; | |
3836 | int txq_id = txq->q.id; | |
3837 | ||
3838 | if (txq->need_update == 0) | |
3839 | return rc; | |
3840 | ||
3841 | /* if we're trying to save power */ | |
3842 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
3843 | /* wake up nic if it's powered down ... | |
3844 | * uCode will wake up, and interrupt us again, so next | |
3845 | * time we'll skip this part. */ | |
5d49f498 | 3846 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3847 | |
3848 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
3849 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
5d49f498 | 3850 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3851 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3852 | return rc; | |
3853 | } | |
3854 | ||
3855 | /* restore this queue's parameters in nic hardware. */ | |
5d49f498 | 3856 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
3857 | if (rc) |
3858 | return rc; | |
5d49f498 | 3859 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 3860 | txq->q.write_ptr | (txq_id << 8)); |
5d49f498 | 3861 | iwl_release_nic_access(priv); |
b481de9c ZY |
3862 | |
3863 | /* else not in power-save mode, uCode will never sleep when we're | |
3864 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
3865 | } else | |
5d49f498 | 3866 | iwl_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 3867 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
3868 | |
3869 | txq->need_update = 0; | |
3870 | ||
3871 | return rc; | |
3872 | } | |
3873 | ||
c8b0e6e1 | 3874 | #ifdef CONFIG_IWL3945_DEBUG |
4a8a4322 | 3875 | static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv, |
40b8ec0b | 3876 | struct iwl3945_rxon_cmd *rxon) |
b481de9c ZY |
3877 | { |
3878 | IWL_DEBUG_RADIO("RX CONFIG:\n"); | |
40b8ec0b | 3879 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
3880 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
3881 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
3882 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
3883 | le32_to_cpu(rxon->filter_flags)); | |
3884 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
3885 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
3886 | rxon->ofdm_basic_rates); | |
3887 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
e174961c JB |
3888 | IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr); |
3889 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
b481de9c ZY |
3890 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
3891 | } | |
3892 | #endif | |
3893 | ||
4a8a4322 | 3894 | static void iwl3945_enable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
3895 | { |
3896 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
3897 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
5d49f498 | 3898 | iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
3899 | } |
3900 | ||
0359facc MA |
3901 | |
3902 | /* call this function to flush any scheduled tasklet */ | |
4a8a4322 | 3903 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 3904 | { |
a96a27f9 | 3905 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
3906 | synchronize_irq(priv->pci_dev->irq); |
3907 | tasklet_kill(&priv->irq_tasklet); | |
3908 | } | |
3909 | ||
3910 | ||
4a8a4322 | 3911 | static inline void iwl3945_disable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
3912 | { |
3913 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
3914 | ||
3915 | /* disable interrupts from uCode/NIC to host */ | |
5d49f498 | 3916 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
3917 | |
3918 | /* acknowledge/clear/reset any interrupts still pending | |
3919 | * from uCode or flow handler (Rx/Tx DMA) */ | |
5d49f498 AK |
3920 | iwl_write32(priv, CSR_INT, 0xffffffff); |
3921 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
3922 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
3923 | } | |
3924 | ||
3925 | static const char *desc_lookup(int i) | |
3926 | { | |
3927 | switch (i) { | |
3928 | case 1: | |
3929 | return "FAIL"; | |
3930 | case 2: | |
3931 | return "BAD_PARAM"; | |
3932 | case 3: | |
3933 | return "BAD_CHECKSUM"; | |
3934 | case 4: | |
3935 | return "NMI_INTERRUPT"; | |
3936 | case 5: | |
3937 | return "SYSASSERT"; | |
3938 | case 6: | |
3939 | return "FATAL_ERROR"; | |
3940 | } | |
3941 | ||
3942 | return "UNKNOWN"; | |
3943 | } | |
3944 | ||
3945 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
3946 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
3947 | ||
4a8a4322 | 3948 | static void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
3949 | { |
3950 | u32 i; | |
3951 | u32 desc, time, count, base, data1; | |
3952 | u32 blink1, blink2, ilink1, ilink2; | |
3953 | int rc; | |
3954 | ||
3955 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
3956 | ||
bb8c093b | 3957 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
3958 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
3959 | return; | |
3960 | } | |
3961 | ||
5d49f498 | 3962 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
3963 | if (rc) { |
3964 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
3965 | return; | |
3966 | } | |
3967 | ||
5d49f498 | 3968 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
3969 | |
3970 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
3971 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 3972 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
3973 | } |
3974 | ||
3975 | IWL_ERROR("Desc Time asrtPC blink2 " | |
3976 | "ilink1 nmiPC Line\n"); | |
3977 | for (i = ERROR_START_OFFSET; | |
3978 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
3979 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 3980 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 3981 | time = |
5d49f498 | 3982 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 3983 | blink1 = |
5d49f498 | 3984 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 3985 | blink2 = |
5d49f498 | 3986 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 3987 | ilink1 = |
5d49f498 | 3988 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 3989 | ilink2 = |
5d49f498 | 3990 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 3991 | data1 = |
5d49f498 | 3992 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c ZY |
3993 | |
3994 | IWL_ERROR | |
3995 | ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
3996 | desc_lookup(desc), desc, time, blink1, blink2, | |
3997 | ilink1, ilink2, data1); | |
3998 | } | |
3999 | ||
5d49f498 | 4000 | iwl_release_nic_access(priv); |
b481de9c ZY |
4001 | |
4002 | } | |
4003 | ||
f58177b9 | 4004 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
4005 | |
4006 | /** | |
bb8c093b | 4007 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 4008 | * |
5d49f498 | 4009 | * NOTE: Must be called with iwl_grab_nic_access() already obtained! |
b481de9c | 4010 | */ |
4a8a4322 | 4011 | static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
4012 | u32 num_events, u32 mode) |
4013 | { | |
4014 | u32 i; | |
4015 | u32 base; /* SRAM byte address of event log header */ | |
4016 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4017 | u32 ptr; /* SRAM byte address of log data */ | |
4018 | u32 ev, time, data; /* event log data */ | |
4019 | ||
4020 | if (num_events == 0) | |
4021 | return; | |
4022 | ||
4023 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4024 | ||
4025 | if (mode == 0) | |
4026 | event_size = 2 * sizeof(u32); | |
4027 | else | |
4028 | event_size = 3 * sizeof(u32); | |
4029 | ||
4030 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4031 | ||
4032 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4033 | * place event id # at far right for easier visual parsing. */ | |
4034 | for (i = 0; i < num_events; i++) { | |
5d49f498 | 4035 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 4036 | ptr += sizeof(u32); |
5d49f498 | 4037 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4038 | ptr += sizeof(u32); |
4039 | if (mode == 0) | |
4040 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4041 | else { | |
5d49f498 | 4042 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4043 | ptr += sizeof(u32); |
4044 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4045 | } | |
4046 | } | |
4047 | } | |
4048 | ||
4a8a4322 | 4049 | static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c ZY |
4050 | { |
4051 | int rc; | |
4052 | u32 base; /* SRAM byte address of event log header */ | |
4053 | u32 capacity; /* event log capacity in # entries */ | |
4054 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4055 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4056 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4057 | u32 size; /* # entries that we'll print */ | |
4058 | ||
4059 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 4060 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4061 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4062 | return; | |
4063 | } | |
4064 | ||
5d49f498 | 4065 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4066 | if (rc) { |
4067 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4068 | return; | |
4069 | } | |
4070 | ||
4071 | /* event log header */ | |
5d49f498 AK |
4072 | capacity = iwl_read_targ_mem(priv, base); |
4073 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4074 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4075 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4076 | |
4077 | size = num_wraps ? capacity : next_entry; | |
4078 | ||
4079 | /* bail out if nothing in log */ | |
4080 | if (size == 0) { | |
583fab37 | 4081 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
5d49f498 | 4082 | iwl_release_nic_access(priv); |
b481de9c ZY |
4083 | return; |
4084 | } | |
4085 | ||
583fab37 | 4086 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4087 | size, num_wraps); |
4088 | ||
4089 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4090 | * i.e the next one that uCode would fill. */ | |
4091 | if (num_wraps) | |
bb8c093b | 4092 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
4093 | capacity - next_entry, mode); |
4094 | ||
4095 | /* (then/else) start at top of log */ | |
bb8c093b | 4096 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4097 | |
5d49f498 | 4098 | iwl_release_nic_access(priv); |
b481de9c ZY |
4099 | } |
4100 | ||
4101 | /** | |
bb8c093b | 4102 | * iwl3945_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4103 | */ |
4a8a4322 | 4104 | static void iwl3945_irq_handle_error(struct iwl_priv *priv) |
b481de9c | 4105 | { |
bb8c093b | 4106 | /* Set the FW error flag -- cleared on iwl3945_down */ |
b481de9c ZY |
4107 | set_bit(STATUS_FW_ERROR, &priv->status); |
4108 | ||
4109 | /* Cancel currently queued command. */ | |
4110 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4111 | ||
c8b0e6e1 | 4112 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 4113 | if (priv->debug_level & IWL_DL_FW_ERRORS) { |
bb8c093b CH |
4114 | iwl3945_dump_nic_error_log(priv); |
4115 | iwl3945_dump_nic_event_log(priv); | |
f2c7e521 | 4116 | iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon); |
b481de9c ZY |
4117 | } |
4118 | #endif | |
4119 | ||
4120 | wake_up_interruptible(&priv->wait_command_queue); | |
4121 | ||
4122 | /* Keep the restart process from trying to send host | |
4123 | * commands by clearing the INIT status bit */ | |
4124 | clear_bit(STATUS_READY, &priv->status); | |
4125 | ||
4126 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4127 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4128 | "Restarting adapter due to uCode error.\n"); | |
4129 | ||
bb8c093b | 4130 | if (iwl3945_is_associated(priv)) { |
f2c7e521 AK |
4131 | memcpy(&priv->recovery39_rxon, &priv->active39_rxon, |
4132 | sizeof(priv->recovery39_rxon)); | |
b481de9c ZY |
4133 | priv->error_recovering = 1; |
4134 | } | |
4135 | queue_work(priv->workqueue, &priv->restart); | |
4136 | } | |
4137 | } | |
4138 | ||
4a8a4322 | 4139 | static void iwl3945_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
4140 | { |
4141 | unsigned long flags; | |
4142 | ||
f2c7e521 AK |
4143 | memcpy(&priv->staging39_rxon, &priv->recovery39_rxon, |
4144 | sizeof(priv->staging39_rxon)); | |
4145 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4146 | iwl3945_commit_rxon(priv); |
b481de9c | 4147 | |
bb8c093b | 4148 | iwl3945_add_station(priv, priv->bssid, 1, 0); |
b481de9c ZY |
4149 | |
4150 | spin_lock_irqsave(&priv->lock, flags); | |
f2c7e521 | 4151 | priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id); |
b481de9c ZY |
4152 | priv->error_recovering = 0; |
4153 | spin_unlock_irqrestore(&priv->lock, flags); | |
4154 | } | |
4155 | ||
4a8a4322 | 4156 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
4157 | { |
4158 | u32 inta, handled = 0; | |
4159 | u32 inta_fh; | |
4160 | unsigned long flags; | |
c8b0e6e1 | 4161 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
4162 | u32 inta_mask; |
4163 | #endif | |
4164 | ||
4165 | spin_lock_irqsave(&priv->lock, flags); | |
4166 | ||
4167 | /* Ack/clear/reset pending uCode interrupts. | |
4168 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4169 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
4170 | inta = iwl_read32(priv, CSR_INT); |
4171 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4172 | |
4173 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4174 | * Any new interrupts that happen after this, either while we're | |
4175 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
4176 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
4177 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4178 | |
c8b0e6e1 | 4179 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 4180 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 4181 | /* just for debug */ |
5d49f498 | 4182 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
b481de9c ZY |
4183 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4184 | inta, inta_mask, inta_fh); | |
4185 | } | |
4186 | #endif | |
4187 | ||
4188 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4189 | * atomic, make sure that inta covers all the interrupts that | |
4190 | * we've discovered, even if FH interrupt came in just after | |
4191 | * reading CSR_INT. */ | |
6f83eaa1 | 4192 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 4193 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4194 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
4195 | inta |= CSR_INT_BIT_FH_TX; |
4196 | ||
4197 | /* Now service all interrupt bits discovered above. */ | |
4198 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4199 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4200 | ||
4201 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4202 | iwl3945_disable_interrupts(priv); |
b481de9c | 4203 | |
bb8c093b | 4204 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4205 | |
4206 | handled |= CSR_INT_BIT_HW_ERR; | |
4207 | ||
4208 | spin_unlock_irqrestore(&priv->lock, flags); | |
4209 | ||
4210 | return; | |
4211 | } | |
4212 | ||
c8b0e6e1 | 4213 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 4214 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 4215 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4216 | if (inta & CSR_INT_BIT_SCD) |
4217 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4218 | "the frame/frames.\n"); | |
b481de9c ZY |
4219 | |
4220 | /* Alive notification via Rx interrupt will do the real work */ | |
4221 | if (inta & CSR_INT_BIT_ALIVE) | |
4222 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4223 | } | |
4224 | #endif | |
4225 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4226 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 4227 | |
b481de9c ZY |
4228 | /* Error detected by uCode */ |
4229 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4230 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4231 | inta); | |
bb8c093b | 4232 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4233 | handled |= CSR_INT_BIT_SW_ERR; |
4234 | } | |
4235 | ||
4236 | /* uCode wakes up after power-down sleep */ | |
4237 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4238 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b | 4239 | iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq); |
f2c7e521 AK |
4240 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[0]); |
4241 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[1]); | |
4242 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[2]); | |
4243 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[3]); | |
4244 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[4]); | |
4245 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[5]); | |
b481de9c ZY |
4246 | |
4247 | handled |= CSR_INT_BIT_WAKEUP; | |
4248 | } | |
4249 | ||
4250 | /* All uCode command responses, including Tx command responses, | |
4251 | * Rx "responses" (frame-received notification), and other | |
4252 | * notifications from uCode come through here*/ | |
4253 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4254 | iwl3945_rx_handle(priv); |
b481de9c ZY |
4255 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4256 | } | |
4257 | ||
4258 | if (inta & CSR_INT_BIT_FH_TX) { | |
4259 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4260 | ||
5d49f498 AK |
4261 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
4262 | if (!iwl_grab_nic_access(priv)) { | |
4263 | iwl_write_direct32(priv, FH39_TCSR_CREDIT | |
bddadf86 | 4264 | (FH39_SRVC_CHNL), 0x0); |
5d49f498 | 4265 | iwl_release_nic_access(priv); |
b481de9c ZY |
4266 | } |
4267 | handled |= CSR_INT_BIT_FH_TX; | |
4268 | } | |
4269 | ||
4270 | if (inta & ~handled) | |
4271 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4272 | ||
4273 | if (inta & ~CSR_INI_SET_MASK) { | |
4274 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4275 | inta & ~CSR_INI_SET_MASK); | |
4276 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4277 | } | |
4278 | ||
4279 | /* Re-enable all interrupts */ | |
0359facc MA |
4280 | /* only Re-enable if disabled by irq */ |
4281 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4282 | iwl3945_enable_interrupts(priv); | |
b481de9c | 4283 | |
c8b0e6e1 | 4284 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 4285 | if (priv->debug_level & (IWL_DL_ISR)) { |
5d49f498 AK |
4286 | inta = iwl_read32(priv, CSR_INT); |
4287 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
4288 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4289 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4290 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4291 | } | |
4292 | #endif | |
4293 | spin_unlock_irqrestore(&priv->lock, flags); | |
4294 | } | |
4295 | ||
bb8c093b | 4296 | static irqreturn_t iwl3945_isr(int irq, void *data) |
b481de9c | 4297 | { |
4a8a4322 | 4298 | struct iwl_priv *priv = data; |
b481de9c ZY |
4299 | u32 inta, inta_mask; |
4300 | u32 inta_fh; | |
4301 | if (!priv) | |
4302 | return IRQ_NONE; | |
4303 | ||
4304 | spin_lock(&priv->lock); | |
4305 | ||
4306 | /* Disable (but don't clear!) interrupts here to avoid | |
4307 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4308 | * If we have something to service, the tasklet will re-enable ints. | |
4309 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
5d49f498 AK |
4310 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
4311 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4312 | |
4313 | /* Discover which interrupts are active/pending */ | |
5d49f498 AK |
4314 | inta = iwl_read32(priv, CSR_INT); |
4315 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4316 | |
4317 | /* Ignore interrupt if there's nothing in NIC to service. | |
4318 | * This may be due to IRQ shared with another device, | |
4319 | * or due to sporadic interrupts thrown from our NIC. */ | |
4320 | if (!inta && !inta_fh) { | |
4321 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4322 | goto none; | |
4323 | } | |
4324 | ||
4325 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
4326 | /* Hardware disappeared */ | |
99df630c | 4327 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta); |
cb4da1a3 | 4328 | goto unplugged; |
b481de9c ZY |
4329 | } |
4330 | ||
4331 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4332 | inta, inta_mask, inta_fh); | |
4333 | ||
25c03d8e JP |
4334 | inta &= ~CSR_INT_BIT_SCD; |
4335 | ||
bb8c093b | 4336 | /* iwl3945_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4337 | if (likely(inta || inta_fh)) |
4338 | tasklet_schedule(&priv->irq_tasklet); | |
cb4da1a3 | 4339 | unplugged: |
b481de9c ZY |
4340 | spin_unlock(&priv->lock); |
4341 | ||
4342 | return IRQ_HANDLED; | |
4343 | ||
4344 | none: | |
4345 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
4346 | /* only Re-enable if disabled by irq */ |
4347 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4348 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
4349 | spin_unlock(&priv->lock); |
4350 | return IRQ_NONE; | |
4351 | } | |
4352 | ||
4353 | /************************** EEPROM BANDS **************************** | |
4354 | * | |
bb8c093b | 4355 | * The iwl3945_eeprom_band definitions below provide the mapping from the |
b481de9c ZY |
4356 | * EEPROM contents to the specific channel number supported for each |
4357 | * band. | |
4358 | * | |
f2c7e521 | 4359 | * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3 |
b481de9c ZY |
4360 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. |
4361 | * The specific geography and calibration information for that channel | |
4362 | * is contained in the eeprom map itself. | |
4363 | * | |
4364 | * During init, we copy the eeprom information and channel map | |
4365 | * information into priv->channel_info_24/52 and priv->channel_map_24/52 | |
4366 | * | |
4367 | * channel_map_24/52 provides the index in the channel_info array for a | |
4368 | * given channel. We have to have two separate maps as there is channel | |
4369 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
4370 | * band_2 | |
4371 | * | |
4372 | * A value of 0xff stored in the channel_map indicates that the channel | |
4373 | * is not supported by the hardware at all. | |
4374 | * | |
4375 | * A value of 0xfe in the channel_map indicates that the channel is not | |
4376 | * valid for Tx with the current hardware. This means that | |
4377 | * while the system can tune and receive on a given channel, it may not | |
4378 | * be able to associate or transmit any frames on that | |
4379 | * channel. There is no corresponding channel information for that | |
4380 | * entry. | |
4381 | * | |
4382 | *********************************************************************/ | |
4383 | ||
4384 | /* 2.4 GHz */ | |
bb8c093b | 4385 | static const u8 iwl3945_eeprom_band_1[14] = { |
b481de9c ZY |
4386 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
4387 | }; | |
4388 | ||
4389 | /* 5.2 GHz bands */ | |
9fbab516 | 4390 | static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */ |
b481de9c ZY |
4391 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 |
4392 | }; | |
4393 | ||
9fbab516 | 4394 | static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */ |
b481de9c ZY |
4395 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
4396 | }; | |
4397 | ||
bb8c093b | 4398 | static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */ |
b481de9c ZY |
4399 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
4400 | }; | |
4401 | ||
bb8c093b | 4402 | static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */ |
b481de9c ZY |
4403 | 145, 149, 153, 157, 161, 165 |
4404 | }; | |
4405 | ||
4a8a4322 | 4406 | static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band, |
b481de9c | 4407 | int *eeprom_ch_count, |
0f741d99 | 4408 | const struct iwl_eeprom_channel |
b481de9c ZY |
4409 | **eeprom_ch_info, |
4410 | const u8 **eeprom_ch_index) | |
4411 | { | |
4412 | switch (band) { | |
4413 | case 1: /* 2.4GHz band */ | |
bb8c093b | 4414 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1); |
f2c7e521 | 4415 | *eeprom_ch_info = priv->eeprom39.band_1_channels; |
bb8c093b | 4416 | *eeprom_ch_index = iwl3945_eeprom_band_1; |
b481de9c | 4417 | break; |
9fbab516 | 4418 | case 2: /* 4.9GHz band */ |
bb8c093b | 4419 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2); |
f2c7e521 | 4420 | *eeprom_ch_info = priv->eeprom39.band_2_channels; |
bb8c093b | 4421 | *eeprom_ch_index = iwl3945_eeprom_band_2; |
b481de9c ZY |
4422 | break; |
4423 | case 3: /* 5.2GHz band */ | |
bb8c093b | 4424 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3); |
f2c7e521 | 4425 | *eeprom_ch_info = priv->eeprom39.band_3_channels; |
bb8c093b | 4426 | *eeprom_ch_index = iwl3945_eeprom_band_3; |
b481de9c | 4427 | break; |
9fbab516 | 4428 | case 4: /* 5.5GHz band */ |
bb8c093b | 4429 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4); |
f2c7e521 | 4430 | *eeprom_ch_info = priv->eeprom39.band_4_channels; |
bb8c093b | 4431 | *eeprom_ch_index = iwl3945_eeprom_band_4; |
b481de9c | 4432 | break; |
9fbab516 | 4433 | case 5: /* 5.7GHz band */ |
bb8c093b | 4434 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5); |
f2c7e521 | 4435 | *eeprom_ch_info = priv->eeprom39.band_5_channels; |
bb8c093b | 4436 | *eeprom_ch_index = iwl3945_eeprom_band_5; |
b481de9c ZY |
4437 | break; |
4438 | default: | |
4439 | BUG(); | |
4440 | return; | |
4441 | } | |
4442 | } | |
4443 | ||
6440adb5 BC |
4444 | /** |
4445 | * iwl3945_get_channel_info - Find driver's private channel info | |
4446 | * | |
4447 | * Based on band and channel number. | |
4448 | */ | |
d20b3c65 | 4449 | const struct iwl_channel_info * |
4a8a4322 | 4450 | iwl3945_get_channel_info(const struct iwl_priv *priv, |
d20b3c65 | 4451 | enum ieee80211_band band, u16 channel) |
b481de9c ZY |
4452 | { |
4453 | int i; | |
4454 | ||
8318d78a JB |
4455 | switch (band) { |
4456 | case IEEE80211_BAND_5GHZ: | |
b481de9c ZY |
4457 | for (i = 14; i < priv->channel_count; i++) { |
4458 | if (priv->channel_info[i].channel == channel) | |
4459 | return &priv->channel_info[i]; | |
4460 | } | |
4461 | break; | |
4462 | ||
8318d78a | 4463 | case IEEE80211_BAND_2GHZ: |
b481de9c ZY |
4464 | if (channel >= 1 && channel <= 14) |
4465 | return &priv->channel_info[channel - 1]; | |
4466 | break; | |
8318d78a JB |
4467 | case IEEE80211_NUM_BANDS: |
4468 | WARN_ON(1); | |
b481de9c ZY |
4469 | } |
4470 | ||
4471 | return NULL; | |
4472 | } | |
4473 | ||
4474 | #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
4475 | ? # x " " : "") | |
4476 | ||
6440adb5 BC |
4477 | /** |
4478 | * iwl3945_init_channel_map - Set up driver's info for all possible channels | |
4479 | */ | |
4a8a4322 | 4480 | static int iwl3945_init_channel_map(struct iwl_priv *priv) |
b481de9c ZY |
4481 | { |
4482 | int eeprom_ch_count = 0; | |
4483 | const u8 *eeprom_ch_index = NULL; | |
0f741d99 | 4484 | const struct iwl_eeprom_channel *eeprom_ch_info = NULL; |
b481de9c | 4485 | int band, ch; |
d20b3c65 | 4486 | struct iwl_channel_info *ch_info; |
b481de9c ZY |
4487 | |
4488 | if (priv->channel_count) { | |
4489 | IWL_DEBUG_INFO("Channel map already initialized.\n"); | |
4490 | return 0; | |
4491 | } | |
4492 | ||
f2c7e521 | 4493 | if (priv->eeprom39.version < 0x2f) { |
b481de9c | 4494 | IWL_WARNING("Unsupported EEPROM version: 0x%04X\n", |
f2c7e521 | 4495 | priv->eeprom39.version); |
b481de9c ZY |
4496 | return -EINVAL; |
4497 | } | |
4498 | ||
4499 | IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n"); | |
4500 | ||
4501 | priv->channel_count = | |
bb8c093b CH |
4502 | ARRAY_SIZE(iwl3945_eeprom_band_1) + |
4503 | ARRAY_SIZE(iwl3945_eeprom_band_2) + | |
4504 | ARRAY_SIZE(iwl3945_eeprom_band_3) + | |
4505 | ARRAY_SIZE(iwl3945_eeprom_band_4) + | |
4506 | ARRAY_SIZE(iwl3945_eeprom_band_5); | |
b481de9c ZY |
4507 | |
4508 | IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count); | |
4509 | ||
d20b3c65 | 4510 | priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) * |
b481de9c ZY |
4511 | priv->channel_count, GFP_KERNEL); |
4512 | if (!priv->channel_info) { | |
4513 | IWL_ERROR("Could not allocate channel_info\n"); | |
4514 | priv->channel_count = 0; | |
4515 | return -ENOMEM; | |
4516 | } | |
4517 | ||
4518 | ch_info = priv->channel_info; | |
4519 | ||
4520 | /* Loop through the 5 EEPROM bands adding them in order to the | |
4521 | * channel map we maintain (that contains additional information than | |
4522 | * what just in the EEPROM) */ | |
4523 | for (band = 1; band <= 5; band++) { | |
4524 | ||
bb8c093b | 4525 | iwl3945_init_band_reference(priv, band, &eeprom_ch_count, |
b481de9c ZY |
4526 | &eeprom_ch_info, &eeprom_ch_index); |
4527 | ||
4528 | /* Loop through each band adding each of the channels */ | |
4529 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
4530 | ch_info->channel = eeprom_ch_index[ch]; | |
8318d78a JB |
4531 | ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ : |
4532 | IEEE80211_BAND_5GHZ; | |
b481de9c ZY |
4533 | |
4534 | /* permanently store EEPROM's channel regulatory flags | |
4535 | * and max power in channel info database. */ | |
4536 | ch_info->eeprom = eeprom_ch_info[ch]; | |
4537 | ||
4538 | /* Copy the run-time flags so they are there even on | |
4539 | * invalid channels */ | |
4540 | ch_info->flags = eeprom_ch_info[ch].flags; | |
4541 | ||
4542 | if (!(is_channel_valid(ch_info))) { | |
4543 | IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - " | |
4544 | "No traffic\n", | |
4545 | ch_info->channel, | |
4546 | ch_info->flags, | |
4547 | is_channel_a_band(ch_info) ? | |
4548 | "5.2" : "2.4"); | |
4549 | ch_info++; | |
4550 | continue; | |
4551 | } | |
4552 | ||
4553 | /* Initialize regulatory-based run-time data */ | |
4554 | ch_info->max_power_avg = ch_info->curr_txpow = | |
4555 | eeprom_ch_info[ch].max_power_avg; | |
4556 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
4557 | ch_info->min_power = 0; | |
4558 | ||
fe7c4040 | 4559 | IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x" |
b481de9c ZY |
4560 | " %ddBm): Ad-Hoc %ssupported\n", |
4561 | ch_info->channel, | |
4562 | is_channel_a_band(ch_info) ? | |
4563 | "5.2" : "2.4", | |
8211ef78 | 4564 | CHECK_AND_PRINT(VALID), |
b481de9c ZY |
4565 | CHECK_AND_PRINT(IBSS), |
4566 | CHECK_AND_PRINT(ACTIVE), | |
4567 | CHECK_AND_PRINT(RADAR), | |
4568 | CHECK_AND_PRINT(WIDE), | |
b481de9c ZY |
4569 | CHECK_AND_PRINT(DFS), |
4570 | eeprom_ch_info[ch].flags, | |
4571 | eeprom_ch_info[ch].max_power_avg, | |
4572 | ((eeprom_ch_info[ch]. | |
4573 | flags & EEPROM_CHANNEL_IBSS) | |
4574 | && !(eeprom_ch_info[ch]. | |
4575 | flags & EEPROM_CHANNEL_RADAR)) | |
4576 | ? "" : "not "); | |
4577 | ||
4578 | /* Set the user_txpower_limit to the highest power | |
4579 | * supported by any channel */ | |
4580 | if (eeprom_ch_info[ch].max_power_avg > | |
4581 | priv->user_txpower_limit) | |
4582 | priv->user_txpower_limit = | |
4583 | eeprom_ch_info[ch].max_power_avg; | |
4584 | ||
4585 | ch_info++; | |
4586 | } | |
4587 | } | |
4588 | ||
6440adb5 | 4589 | /* Set up txpower settings in driver for all channels */ |
b481de9c ZY |
4590 | if (iwl3945_txpower_set_from_eeprom(priv)) |
4591 | return -EIO; | |
4592 | ||
4593 | return 0; | |
4594 | } | |
4595 | ||
849e0dce RC |
4596 | /* |
4597 | * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map | |
4598 | */ | |
4a8a4322 | 4599 | static void iwl3945_free_channel_map(struct iwl_priv *priv) |
849e0dce RC |
4600 | { |
4601 | kfree(priv->channel_info); | |
4602 | priv->channel_count = 0; | |
4603 | } | |
4604 | ||
b481de9c ZY |
4605 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4606 | * sending probe req. This should be set long enough to hear probe responses | |
4607 | * from more than one AP. */ | |
f9340520 AK |
4608 | #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ |
4609 | #define IWL_ACTIVE_DWELL_TIME_52 (20) | |
4610 | ||
4611 | #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3) | |
4612 | #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2) | |
b481de9c ZY |
4613 | |
4614 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4615 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4616 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4617 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4618 | * no other traffic). | |
4619 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4620 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
f9340520 | 4621 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */ |
b481de9c ZY |
4622 | |
4623 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4624 | * Must be set longer than active dwell time. | |
4625 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4626 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4627 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4628 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4629 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4630 | ||
e720ce9d | 4631 | #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1))) |
f9340520 | 4632 | |
4a8a4322 | 4633 | static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv, |
f9340520 AK |
4634 | enum ieee80211_band band, |
4635 | u8 n_probes) | |
b481de9c | 4636 | { |
8318d78a | 4637 | if (band == IEEE80211_BAND_5GHZ) |
f9340520 AK |
4638 | return IWL_ACTIVE_DWELL_TIME_52 + |
4639 | IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1); | |
b481de9c | 4640 | else |
f9340520 AK |
4641 | return IWL_ACTIVE_DWELL_TIME_24 + |
4642 | IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1); | |
b481de9c ZY |
4643 | } |
4644 | ||
4a8a4322 | 4645 | static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv, |
8318d78a | 4646 | enum ieee80211_band band) |
b481de9c | 4647 | { |
8318d78a | 4648 | u16 passive = (band == IEEE80211_BAND_2GHZ) ? |
b481de9c ZY |
4649 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4650 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4651 | ||
bb8c093b | 4652 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4653 | /* If we're associated, we clamp the maximum passive |
4654 | * dwell time to be 98% of the beacon interval (minus | |
4655 | * 2 * channel tune time) */ | |
4656 | passive = priv->beacon_int; | |
4657 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4658 | passive = IWL_PASSIVE_DWELL_BASE; | |
4659 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4660 | } | |
4661 | ||
b481de9c ZY |
4662 | return passive; |
4663 | } | |
4664 | ||
4a8a4322 | 4665 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 4666 | enum ieee80211_band band, |
f9340520 | 4667 | u8 is_active, u8 n_probes, |
bb8c093b | 4668 | struct iwl3945_scan_channel *scan_ch) |
b481de9c ZY |
4669 | { |
4670 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4671 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 4672 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
4673 | u16 passive_dwell = 0; |
4674 | u16 active_dwell = 0; | |
4675 | int added, i; | |
4676 | ||
8318d78a JB |
4677 | sband = iwl3945_get_band(priv, band); |
4678 | if (!sband) | |
b481de9c ZY |
4679 | return 0; |
4680 | ||
8318d78a | 4681 | channels = sband->channels; |
b481de9c | 4682 | |
f9340520 | 4683 | active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes); |
8318d78a | 4684 | passive_dwell = iwl3945_get_passive_dwell_time(priv, band); |
b481de9c | 4685 | |
8f4807a1 AK |
4686 | if (passive_dwell <= active_dwell) |
4687 | passive_dwell = active_dwell + 1; | |
4688 | ||
8318d78a | 4689 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4690 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4691 | continue; | |
4692 | ||
8318d78a | 4693 | scan_ch->channel = channels[i].hw_value; |
b481de9c | 4694 | |
8318d78a | 4695 | ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 4696 | if (!is_channel_valid(ch_info)) { |
66b5004d | 4697 | IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n", |
b481de9c ZY |
4698 | scan_ch->channel); |
4699 | continue; | |
4700 | } | |
4701 | ||
011a0330 AK |
4702 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
4703 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
4704 | /* If passive , set up for auto-switch | |
4705 | * and use long active_dwell time. | |
4706 | */ | |
b481de9c | 4707 | if (!is_active || is_channel_passive(ch_info) || |
011a0330 | 4708 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 4709 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
4710 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
4711 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
4712 | } else { | |
b481de9c | 4713 | scan_ch->type = 1; /* active */ |
011a0330 | 4714 | } |
b481de9c | 4715 | |
011a0330 AK |
4716 | /* Set direct probe bits. These may be used both for active |
4717 | * scan channels (probes gets sent right away), | |
4718 | * or for passive channels (probes get se sent only after | |
4719 | * hearing clear Rx packet).*/ | |
4720 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
4721 | if (n_probes) | |
4722 | scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes); | |
4723 | } else { | |
4724 | /* uCode v1 does not allow setting direct probe bits on | |
4725 | * passive channel. */ | |
4726 | if ((scan_ch->type & 1) && n_probes) | |
4727 | scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes); | |
4728 | } | |
b481de9c | 4729 | |
9fbab516 | 4730 | /* Set txpower levels to defaults */ |
b481de9c ZY |
4731 | scan_ch->tpc.dsp_atten = 110; |
4732 | /* scan_pwr_info->tpc.dsp_atten; */ | |
4733 | ||
4734 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 4735 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4736 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
4737 | else { | |
4738 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
4739 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 4740 | * power level: |
8a1b0245 | 4741 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
4742 | */ |
4743 | } | |
4744 | ||
4745 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
4746 | scan_ch->channel, | |
4747 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
4748 | (scan_ch->type & 1) ? | |
4749 | active_dwell : passive_dwell); | |
4750 | ||
4751 | scan_ch++; | |
4752 | added++; | |
4753 | } | |
4754 | ||
4755 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
4756 | return added; | |
4757 | } | |
4758 | ||
4a8a4322 | 4759 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
4760 | struct ieee80211_rate *rates) |
4761 | { | |
4762 | int i; | |
4763 | ||
4764 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
4765 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
4766 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4767 | rates[i].hw_value_short = i; | |
4768 | rates[i].flags = 0; | |
d9829a67 | 4769 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 4770 | /* |
8318d78a | 4771 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 4772 | */ |
bb8c093b | 4773 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 4774 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 4775 | } |
b481de9c ZY |
4776 | } |
4777 | } | |
4778 | ||
4779 | /** | |
bb8c093b | 4780 | * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 4781 | */ |
4a8a4322 | 4782 | static int iwl3945_init_geos(struct iwl_priv *priv) |
b481de9c | 4783 | { |
d20b3c65 | 4784 | struct iwl_channel_info *ch; |
8211ef78 | 4785 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
4786 | struct ieee80211_channel *channels; |
4787 | struct ieee80211_channel *geo_ch; | |
4788 | struct ieee80211_rate *rates; | |
4789 | int i = 0; | |
b481de9c | 4790 | |
8318d78a JB |
4791 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
4792 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
4793 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
4794 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4795 | return 0; | |
4796 | } | |
4797 | ||
b481de9c ZY |
4798 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
4799 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 4800 | if (!channels) |
b481de9c | 4801 | return -ENOMEM; |
b481de9c | 4802 | |
8211ef78 | 4803 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
4804 | GFP_KERNEL); |
4805 | if (!rates) { | |
b481de9c ZY |
4806 | kfree(channels); |
4807 | return -ENOMEM; | |
4808 | } | |
4809 | ||
b481de9c | 4810 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 TW |
4811 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
4812 | sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)]; | |
4813 | /* just OFDM */ | |
4814 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
4815 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
4816 | ||
4817 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
4818 | sband->channels = channels; | |
4819 | /* OFDM & CCK */ | |
4820 | sband->bitrates = rates; | |
4821 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c ZY |
4822 | |
4823 | priv->ieee_channels = channels; | |
4824 | priv->ieee_rates = rates; | |
4825 | ||
bb8c093b | 4826 | iwl3945_init_hw_rates(priv, rates); |
b481de9c | 4827 | |
8211ef78 | 4828 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
4829 | ch = &priv->channel_info[i]; |
4830 | ||
8211ef78 TW |
4831 | /* FIXME: might be removed if scan is OK*/ |
4832 | if (!is_channel_valid(ch)) | |
b481de9c | 4833 | continue; |
b481de9c ZY |
4834 | |
4835 | if (is_channel_a_band(ch)) | |
8211ef78 | 4836 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
8318d78a | 4837 | else |
8211ef78 | 4838 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
b481de9c | 4839 | |
8211ef78 TW |
4840 | geo_ch = &sband->channels[sband->n_channels++]; |
4841 | ||
4842 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
4843 | geo_ch->max_power = ch->max_power_avg; |
4844 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 4845 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
4846 | |
4847 | if (is_channel_valid(ch)) { | |
8318d78a JB |
4848 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
4849 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 4850 | |
8318d78a JB |
4851 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
4852 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
4853 | |
4854 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 4855 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
4856 | |
4857 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
4858 | priv->max_channel_txpower_limit = | |
4859 | ch->max_power_avg; | |
8211ef78 | 4860 | } else { |
8318d78a | 4861 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
4862 | } |
4863 | ||
4864 | /* Save flags for reg domain usage */ | |
4865 | geo_ch->orig_flags = geo_ch->flags; | |
4866 | ||
4867 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
4868 | ch->channel, geo_ch->center_freq, | |
4869 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
4870 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
4871 | "restricted" : "valid", | |
4872 | geo_ch->flags); | |
b481de9c ZY |
4873 | } |
4874 | ||
82b9a121 TW |
4875 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
4876 | priv->cfg->sku & IWL_SKU_A) { | |
b481de9c ZY |
4877 | printk(KERN_INFO DRV_NAME |
4878 | ": Incorrectly detected BG card as ABG. Please send " | |
4879 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
4880 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 4881 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
4882 | } |
4883 | ||
4884 | printk(KERN_INFO DRV_NAME | |
4885 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
4886 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
4887 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 4888 | |
e0e0a67e JL |
4889 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
4890 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
4891 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
4892 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
4893 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
4894 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 4895 | |
b481de9c ZY |
4896 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
4897 | ||
4898 | return 0; | |
4899 | } | |
4900 | ||
849e0dce RC |
4901 | /* |
4902 | * iwl3945_free_geos - undo allocations in iwl3945_init_geos | |
4903 | */ | |
4a8a4322 | 4904 | static void iwl3945_free_geos(struct iwl_priv *priv) |
849e0dce | 4905 | { |
849e0dce RC |
4906 | kfree(priv->ieee_channels); |
4907 | kfree(priv->ieee_rates); | |
4908 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4909 | } | |
4910 | ||
b481de9c ZY |
4911 | /****************************************************************************** |
4912 | * | |
4913 | * uCode download functions | |
4914 | * | |
4915 | ******************************************************************************/ | |
4916 | ||
4a8a4322 | 4917 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 4918 | { |
98c92211 TW |
4919 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
4920 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
4921 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
4922 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
4923 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
4924 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
4925 | } |
4926 | ||
4927 | /** | |
bb8c093b | 4928 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4929 | * looking at all data. |
4930 | */ | |
4a8a4322 | 4931 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
4932 | { |
4933 | u32 val; | |
4934 | u32 save_len = len; | |
4935 | int rc = 0; | |
4936 | u32 errcnt; | |
4937 | ||
4938 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4939 | ||
5d49f498 | 4940 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4941 | if (rc) |
4942 | return rc; | |
4943 | ||
5d49f498 | 4944 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 4945 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
4946 | |
4947 | errcnt = 0; | |
4948 | for (; len > 0; len -= sizeof(u32), image++) { | |
4949 | /* read data comes through single port, auto-incr addr */ | |
4950 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4951 | * if IWL_DL_IO is set */ | |
5d49f498 | 4952 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4953 | if (val != le32_to_cpu(*image)) { |
4954 | IWL_ERROR("uCode INST section is invalid at " | |
4955 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
4956 | save_len - len, val, le32_to_cpu(*image)); | |
4957 | rc = -EIO; | |
4958 | errcnt++; | |
4959 | if (errcnt >= 20) | |
4960 | break; | |
4961 | } | |
4962 | } | |
4963 | ||
5d49f498 | 4964 | iwl_release_nic_access(priv); |
b481de9c ZY |
4965 | |
4966 | if (!errcnt) | |
bc434dd2 | 4967 | IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); |
b481de9c ZY |
4968 | |
4969 | return rc; | |
4970 | } | |
4971 | ||
4972 | ||
4973 | /** | |
bb8c093b | 4974 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4975 | * using sample data 100 bytes apart. If these sample points are good, |
4976 | * it's a pretty good bet that everything between them is good, too. | |
4977 | */ | |
4a8a4322 | 4978 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
4979 | { |
4980 | u32 val; | |
4981 | int rc = 0; | |
4982 | u32 errcnt = 0; | |
4983 | u32 i; | |
4984 | ||
4985 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4986 | ||
5d49f498 | 4987 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4988 | if (rc) |
4989 | return rc; | |
4990 | ||
4991 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
4992 | /* read data comes through single port, auto-incr addr */ | |
4993 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4994 | * if IWL_DL_IO is set */ | |
5d49f498 | 4995 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 4996 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 4997 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4998 | if (val != le32_to_cpu(*image)) { |
4999 | #if 0 /* Enable this if you want to see details */ | |
5000 | IWL_ERROR("uCode INST section is invalid at " | |
5001 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5002 | i, val, *image); | |
5003 | #endif | |
5004 | rc = -EIO; | |
5005 | errcnt++; | |
5006 | if (errcnt >= 3) | |
5007 | break; | |
5008 | } | |
5009 | } | |
5010 | ||
5d49f498 | 5011 | iwl_release_nic_access(priv); |
b481de9c ZY |
5012 | |
5013 | return rc; | |
5014 | } | |
5015 | ||
5016 | ||
5017 | /** | |
bb8c093b | 5018 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5019 | * and verify its contents |
5020 | */ | |
4a8a4322 | 5021 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
5022 | { |
5023 | __le32 *image; | |
5024 | u32 len; | |
5025 | int rc = 0; | |
5026 | ||
5027 | /* Try bootstrap */ | |
5028 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5029 | len = priv->ucode_boot.len; | |
bb8c093b | 5030 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5031 | if (rc == 0) { |
5032 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5033 | return 0; | |
5034 | } | |
5035 | ||
5036 | /* Try initialize */ | |
5037 | image = (__le32 *)priv->ucode_init.v_addr; | |
5038 | len = priv->ucode_init.len; | |
bb8c093b | 5039 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5040 | if (rc == 0) { |
5041 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5042 | return 0; | |
5043 | } | |
5044 | ||
5045 | /* Try runtime/protocol */ | |
5046 | image = (__le32 *)priv->ucode_code.v_addr; | |
5047 | len = priv->ucode_code.len; | |
bb8c093b | 5048 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5049 | if (rc == 0) { |
5050 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5051 | return 0; | |
5052 | } | |
5053 | ||
5054 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5055 | ||
9fbab516 BC |
5056 | /* Since nothing seems to match, show first several data entries in |
5057 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5058 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5059 | image = (__le32 *)priv->ucode_boot.v_addr; |
5060 | len = priv->ucode_boot.len; | |
bb8c093b | 5061 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
5062 | |
5063 | return rc; | |
5064 | } | |
5065 | ||
5066 | ||
5067 | /* check contents of special bootstrap uCode SRAM */ | |
4a8a4322 | 5068 | static int iwl3945_verify_bsm(struct iwl_priv *priv) |
b481de9c ZY |
5069 | { |
5070 | __le32 *image = priv->ucode_boot.v_addr; | |
5071 | u32 len = priv->ucode_boot.len; | |
5072 | u32 reg; | |
5073 | u32 val; | |
5074 | ||
5075 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
5076 | ||
5077 | /* verify BSM SRAM contents */ | |
5d49f498 | 5078 | val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG); |
b481de9c ZY |
5079 | for (reg = BSM_SRAM_LOWER_BOUND; |
5080 | reg < BSM_SRAM_LOWER_BOUND + len; | |
3ac7f146 | 5081 | reg += sizeof(u32), image++) { |
5d49f498 | 5082 | val = iwl_read_prph(priv, reg); |
b481de9c ZY |
5083 | if (val != le32_to_cpu(*image)) { |
5084 | IWL_ERROR("BSM uCode verification failed at " | |
5085 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
5086 | BSM_SRAM_LOWER_BOUND, | |
5087 | reg - BSM_SRAM_LOWER_BOUND, len, | |
5088 | val, le32_to_cpu(*image)); | |
5089 | return -EIO; | |
5090 | } | |
5091 | } | |
5092 | ||
5093 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
5094 | ||
5095 | return 0; | |
5096 | } | |
5097 | ||
5098 | /** | |
bb8c093b | 5099 | * iwl3945_load_bsm - Load bootstrap instructions |
b481de9c ZY |
5100 | * |
5101 | * BSM operation: | |
5102 | * | |
5103 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
5104 | * in special SRAM that does not power down during RFKILL. When powering back | |
5105 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
5106 | * the bootstrap program into the on-board processor, and starts it. | |
5107 | * | |
5108 | * The bootstrap program loads (via DMA) instructions and data for a new | |
5109 | * program from host DRAM locations indicated by the host driver in the | |
5110 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
5111 | * automatically. | |
5112 | * | |
5113 | * When initializing the NIC, the host driver points the BSM to the | |
5114 | * "initialize" uCode image. This uCode sets up some internal data, then | |
5115 | * notifies host via "initialize alive" that it is complete. | |
5116 | * | |
5117 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
5118 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
5119 | * (filled initially with starting data values for the on-board processor), | |
5120 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
5121 | * which begins normal operation. | |
5122 | * | |
5123 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
5124 | * the backup data cache in DRAM before SRAM is powered down. | |
5125 | * | |
5126 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
5127 | * the runtime uCode instructions and the backup data cache into SRAM, | |
5128 | * and re-launches the runtime uCode from where it left off. | |
5129 | */ | |
4a8a4322 | 5130 | static int iwl3945_load_bsm(struct iwl_priv *priv) |
b481de9c ZY |
5131 | { |
5132 | __le32 *image = priv->ucode_boot.v_addr; | |
5133 | u32 len = priv->ucode_boot.len; | |
5134 | dma_addr_t pinst; | |
5135 | dma_addr_t pdata; | |
5136 | u32 inst_len; | |
5137 | u32 data_len; | |
5138 | int rc; | |
5139 | int i; | |
5140 | u32 done; | |
5141 | u32 reg_offset; | |
5142 | ||
5143 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
5144 | ||
5145 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
250bdd21 | 5146 | if (len > IWL39_MAX_BSM_SIZE) |
b481de9c ZY |
5147 | return -EINVAL; |
5148 | ||
5149 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
9fbab516 | 5150 | * in host DRAM ... host DRAM physical address bits 31:0 for 3945. |
bb8c093b | 5151 | * NOTE: iwl3945_initialize_alive_start() will replace these values, |
b481de9c ZY |
5152 | * after the "initialize" uCode has run, to point to |
5153 | * runtime/protocol instructions and backup data cache. */ | |
5154 | pinst = priv->ucode_init.p_addr; | |
5155 | pdata = priv->ucode_init_data.p_addr; | |
5156 | inst_len = priv->ucode_init.len; | |
5157 | data_len = priv->ucode_init_data.len; | |
5158 | ||
5d49f498 | 5159 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5160 | if (rc) |
5161 | return rc; | |
5162 | ||
5d49f498 AK |
5163 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5164 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5165 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
5166 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
b481de9c ZY |
5167 | |
5168 | /* Fill BSM memory with bootstrap instructions */ | |
5169 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
5170 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
5171 | reg_offset += sizeof(u32), image++) | |
5d49f498 | 5172 | _iwl_write_prph(priv, reg_offset, |
b481de9c ZY |
5173 | le32_to_cpu(*image)); |
5174 | ||
bb8c093b | 5175 | rc = iwl3945_verify_bsm(priv); |
b481de9c | 5176 | if (rc) { |
5d49f498 | 5177 | iwl_release_nic_access(priv); |
b481de9c ZY |
5178 | return rc; |
5179 | } | |
5180 | ||
5181 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
5d49f498 AK |
5182 | iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); |
5183 | iwl_write_prph(priv, BSM_WR_MEM_DST_REG, | |
250bdd21 | 5184 | IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 5185 | iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
b481de9c ZY |
5186 | |
5187 | /* Load bootstrap code into instruction SRAM now, | |
5188 | * to prepare to load "initialize" uCode */ | |
5d49f498 | 5189 | iwl_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5190 | BSM_WR_CTRL_REG_BIT_START); |
5191 | ||
5192 | /* Wait for load of bootstrap uCode to finish */ | |
5193 | for (i = 0; i < 100; i++) { | |
5d49f498 | 5194 | done = iwl_read_prph(priv, BSM_WR_CTRL_REG); |
b481de9c ZY |
5195 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
5196 | break; | |
5197 | udelay(10); | |
5198 | } | |
5199 | if (i < 100) | |
5200 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
5201 | else { | |
5202 | IWL_ERROR("BSM write did not complete!\n"); | |
5203 | return -EIO; | |
5204 | } | |
5205 | ||
5206 | /* Enable future boot loads whenever power management unit triggers it | |
5207 | * (e.g. when powering back up after power-save shutdown) */ | |
5d49f498 | 5208 | iwl_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5209 | BSM_WR_CTRL_REG_BIT_START_EN); |
5210 | ||
5d49f498 | 5211 | iwl_release_nic_access(priv); |
b481de9c ZY |
5212 | |
5213 | return 0; | |
5214 | } | |
5215 | ||
4a8a4322 | 5216 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
5217 | { |
5218 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 5219 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5220 | } |
5221 | ||
5222 | /** | |
bb8c093b | 5223 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5224 | * |
5225 | * Copy into buffers for card to fetch via bus-mastering | |
5226 | */ | |
4a8a4322 | 5227 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 5228 | { |
a78fe754 | 5229 | struct iwl_ucode *ucode; |
a0987a8d | 5230 | int ret = -EINVAL, index; |
b481de9c ZY |
5231 | const struct firmware *ucode_raw; |
5232 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
5233 | const char *name_pre = priv->cfg->fw_name_pre; |
5234 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
5235 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
5236 | char buf[25]; | |
b481de9c ZY |
5237 | u8 *src; |
5238 | size_t len; | |
a0987a8d | 5239 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
5240 | |
5241 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5242 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
5243 | for (index = api_max; index >= api_min; index--) { |
5244 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
5245 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
5246 | if (ret < 0) { | |
5247 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5248 | buf, ret); | |
5249 | if (ret == -ENOENT) | |
5250 | continue; | |
5251 | else | |
5252 | goto error; | |
5253 | } else { | |
5254 | if (index < api_max) | |
5255 | IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n", | |
5256 | buf, api_max); | |
5257 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5258 | buf, ucode_raw->size); | |
5259 | break; | |
5260 | } | |
b481de9c ZY |
5261 | } |
5262 | ||
a0987a8d RC |
5263 | if (ret < 0) |
5264 | goto error; | |
b481de9c ZY |
5265 | |
5266 | /* Make sure that we got at least our header! */ | |
5267 | if (ucode_raw->size < sizeof(*ucode)) { | |
5268 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5269 | ret = -EINVAL; |
b481de9c ZY |
5270 | goto err_release; |
5271 | } | |
5272 | ||
5273 | /* Data from ucode file: header followed by uCode images */ | |
5274 | ucode = (void *)ucode_raw->data; | |
5275 | ||
c02b3acd | 5276 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 5277 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
5278 | inst_size = le32_to_cpu(ucode->inst_size); |
5279 | data_size = le32_to_cpu(ucode->data_size); | |
5280 | init_size = le32_to_cpu(ucode->init_size); | |
5281 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5282 | boot_size = le32_to_cpu(ucode->boot_size); | |
5283 | ||
a0987a8d RC |
5284 | /* api_ver should match the api version forming part of the |
5285 | * firmware filename ... but we don't check for that and only rely | |
5286 | * on the API version read from firware header from here on forward */ | |
5287 | ||
5288 | if (api_ver < api_min || api_ver > api_max) { | |
5289 | IWL_ERROR("Driver unable to support your firmware API. " | |
5290 | "Driver supports v%u, firmware is v%u.\n", | |
5291 | api_max, api_ver); | |
5292 | priv->ucode_ver = 0; | |
5293 | ret = -EINVAL; | |
5294 | goto err_release; | |
5295 | } | |
5296 | if (api_ver != api_max) | |
5297 | IWL_ERROR("Firmware has old API version. Expected %u, " | |
5298 | "got %u. New firmware can be obtained " | |
5299 | "from http://www.intellinuxwireless.org.\n", | |
5300 | api_max, api_ver); | |
5301 | ||
5302 | printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n", | |
c02b3acd CR |
5303 | IWL_UCODE_MAJOR(priv->ucode_ver), |
5304 | IWL_UCODE_MINOR(priv->ucode_ver), | |
5305 | IWL_UCODE_API(priv->ucode_ver), | |
5306 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d RC |
5307 | IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n", |
5308 | priv->ucode_ver); | |
bc434dd2 IS |
5309 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size); |
5310 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size); | |
5311 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size); | |
5312 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size); | |
5313 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size); | |
b481de9c | 5314 | |
a0987a8d | 5315 | |
b481de9c ZY |
5316 | /* Verify size of file vs. image size info in file's header */ |
5317 | if (ucode_raw->size < sizeof(*ucode) + | |
5318 | inst_size + data_size + init_size + | |
5319 | init_data_size + boot_size) { | |
5320 | ||
5321 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5322 | (int)ucode_raw->size); | |
90e759d1 | 5323 | ret = -EINVAL; |
b481de9c ZY |
5324 | goto err_release; |
5325 | } | |
5326 | ||
5327 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 5328 | if (inst_size > IWL39_MAX_INST_SIZE) { |
90e759d1 TW |
5329 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5330 | inst_size); | |
5331 | ret = -EINVAL; | |
b481de9c ZY |
5332 | goto err_release; |
5333 | } | |
5334 | ||
250bdd21 | 5335 | if (data_size > IWL39_MAX_DATA_SIZE) { |
90e759d1 TW |
5336 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5337 | data_size); | |
5338 | ret = -EINVAL; | |
b481de9c ZY |
5339 | goto err_release; |
5340 | } | |
250bdd21 | 5341 | if (init_size > IWL39_MAX_INST_SIZE) { |
90e759d1 TW |
5342 | IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n", |
5343 | init_size); | |
5344 | ret = -EINVAL; | |
b481de9c ZY |
5345 | goto err_release; |
5346 | } | |
250bdd21 | 5347 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
90e759d1 TW |
5348 | IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n", |
5349 | init_data_size); | |
5350 | ret = -EINVAL; | |
b481de9c ZY |
5351 | goto err_release; |
5352 | } | |
250bdd21 | 5353 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
90e759d1 TW |
5354 | IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n", |
5355 | boot_size); | |
5356 | ret = -EINVAL; | |
b481de9c ZY |
5357 | goto err_release; |
5358 | } | |
5359 | ||
5360 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5361 | ||
5362 | /* Runtime instructions and 2 copies of data: | |
5363 | * 1) unmodified from disk | |
5364 | * 2) backup cache for save/restore during power-downs */ | |
5365 | priv->ucode_code.len = inst_size; | |
98c92211 | 5366 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5367 | |
5368 | priv->ucode_data.len = data_size; | |
98c92211 | 5369 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5370 | |
5371 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5372 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 5373 | |
90e759d1 TW |
5374 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
5375 | !priv->ucode_data_backup.v_addr) | |
5376 | goto err_pci_alloc; | |
b481de9c ZY |
5377 | |
5378 | /* Initialization instructions and data */ | |
90e759d1 TW |
5379 | if (init_size && init_data_size) { |
5380 | priv->ucode_init.len = init_size; | |
98c92211 | 5381 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5382 | |
5383 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5384 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5385 | |
5386 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5387 | goto err_pci_alloc; | |
5388 | } | |
b481de9c ZY |
5389 | |
5390 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5391 | if (boot_size) { |
5392 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5393 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5394 | |
90e759d1 TW |
5395 | if (!priv->ucode_boot.v_addr) |
5396 | goto err_pci_alloc; | |
5397 | } | |
b481de9c ZY |
5398 | |
5399 | /* Copy images into buffers for card's bus-master reads ... */ | |
5400 | ||
5401 | /* Runtime instructions (first block of data in file) */ | |
5402 | src = &ucode->data[0]; | |
5403 | len = priv->ucode_code.len; | |
90e759d1 | 5404 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5405 | memcpy(priv->ucode_code.v_addr, src, len); |
5406 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5407 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5408 | ||
5409 | /* Runtime data (2nd block) | |
bb8c093b | 5410 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
5411 | src = &ucode->data[inst_size]; |
5412 | len = priv->ucode_data.len; | |
90e759d1 | 5413 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5414 | memcpy(priv->ucode_data.v_addr, src, len); |
5415 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5416 | ||
5417 | /* Initialization instructions (3rd block) */ | |
5418 | if (init_size) { | |
5419 | src = &ucode->data[inst_size + data_size]; | |
5420 | len = priv->ucode_init.len; | |
90e759d1 TW |
5421 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5422 | len); | |
b481de9c ZY |
5423 | memcpy(priv->ucode_init.v_addr, src, len); |
5424 | } | |
5425 | ||
5426 | /* Initialization data (4th block) */ | |
5427 | if (init_data_size) { | |
5428 | src = &ucode->data[inst_size + data_size + init_size]; | |
5429 | len = priv->ucode_init_data.len; | |
5430 | IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n", | |
5431 | (int)len); | |
5432 | memcpy(priv->ucode_init_data.v_addr, src, len); | |
5433 | } | |
5434 | ||
5435 | /* Bootstrap instructions (5th block) */ | |
5436 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5437 | len = priv->ucode_boot.len; | |
5438 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n", | |
5439 | (int)len); | |
5440 | memcpy(priv->ucode_boot.v_addr, src, len); | |
5441 | ||
5442 | /* We have our copies now, allow OS release its copies */ | |
5443 | release_firmware(ucode_raw); | |
5444 | return 0; | |
5445 | ||
5446 | err_pci_alloc: | |
5447 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5448 | ret = -ENOMEM; |
bb8c093b | 5449 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
5450 | |
5451 | err_release: | |
5452 | release_firmware(ucode_raw); | |
5453 | ||
5454 | error: | |
90e759d1 | 5455 | return ret; |
b481de9c ZY |
5456 | } |
5457 | ||
5458 | ||
5459 | /** | |
bb8c093b | 5460 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5461 | * |
5462 | * Tell initialization uCode where to find runtime uCode. | |
5463 | * | |
5464 | * BSM registers initially contain pointers to initialization uCode. | |
5465 | * We need to replace them to load runtime uCode inst and data, | |
5466 | * and to save runtime data when powering down. | |
5467 | */ | |
4a8a4322 | 5468 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
5469 | { |
5470 | dma_addr_t pinst; | |
5471 | dma_addr_t pdata; | |
5472 | int rc = 0; | |
5473 | unsigned long flags; | |
5474 | ||
5475 | /* bits 31:0 for 3945 */ | |
5476 | pinst = priv->ucode_code.p_addr; | |
5477 | pdata = priv->ucode_data_backup.p_addr; | |
5478 | ||
5479 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 5480 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5481 | if (rc) { |
5482 | spin_unlock_irqrestore(&priv->lock, flags); | |
5483 | return rc; | |
5484 | } | |
5485 | ||
5486 | /* Tell bootstrap uCode where to find image to load */ | |
5d49f498 AK |
5487 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5488 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5489 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5490 | priv->ucode_data.len); |
5491 | ||
a96a27f9 | 5492 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 5493 | * that all new ptr/size info is in place */ |
5d49f498 | 5494 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5495 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5496 | ||
5d49f498 | 5497 | iwl_release_nic_access(priv); |
b481de9c ZY |
5498 | |
5499 | spin_unlock_irqrestore(&priv->lock, flags); | |
5500 | ||
5501 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5502 | ||
5503 | return rc; | |
5504 | } | |
5505 | ||
5506 | /** | |
bb8c093b | 5507 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5508 | * |
5509 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5510 | * | |
b481de9c | 5511 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 5512 | */ |
4a8a4322 | 5513 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5514 | { |
5515 | /* Check alive response for "valid" sign from uCode */ | |
5516 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5517 | /* We had an error bringing up the hardware, so take it | |
5518 | * all the way back down so we can try again */ | |
5519 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5520 | goto restart; | |
5521 | } | |
5522 | ||
5523 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5524 | * This is a paranoid check, because we would not have gotten the | |
5525 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5526 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5527 | /* Runtime instruction load was bad; |
5528 | * take it all the way back down so we can try again */ | |
5529 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5530 | goto restart; | |
5531 | } | |
5532 | ||
5533 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5534 | * load and launch runtime uCode, which will send us another "Alive" | |
5535 | * notification. */ | |
5536 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5537 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5538 | /* Runtime instruction load won't happen; |
5539 | * take it all the way back down so we can try again */ | |
5540 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5541 | goto restart; | |
5542 | } | |
5543 | return; | |
5544 | ||
5545 | restart: | |
5546 | queue_work(priv->workqueue, &priv->restart); | |
5547 | } | |
5548 | ||
5549 | ||
9bdf5eca MA |
5550 | /* temporary */ |
5551 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, | |
5552 | struct sk_buff *skb); | |
5553 | ||
b481de9c | 5554 | /** |
bb8c093b | 5555 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5556 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5557 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 5558 | */ |
4a8a4322 | 5559 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5560 | { |
5561 | int rc = 0; | |
5562 | int thermal_spin = 0; | |
5563 | u32 rfkill; | |
5564 | ||
5565 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5566 | ||
5567 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5568 | /* We had an error bringing up the hardware, so take it | |
5569 | * all the way back down so we can try again */ | |
5570 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5571 | goto restart; | |
5572 | } | |
5573 | ||
5574 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5575 | * This is a paranoid check, because we would not have gotten the | |
5576 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5577 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5578 | /* Runtime instruction load was bad; |
5579 | * take it all the way back down so we can try again */ | |
5580 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5581 | goto restart; | |
5582 | } | |
5583 | ||
bb8c093b | 5584 | iwl3945_clear_stations_table(priv); |
b481de9c | 5585 | |
5d49f498 | 5586 | rc = iwl_grab_nic_access(priv); |
b481de9c | 5587 | if (rc) { |
a96a27f9 | 5588 | IWL_WARNING("Can not read RFKILL status from adapter\n"); |
b481de9c ZY |
5589 | return; |
5590 | } | |
5591 | ||
5d49f498 | 5592 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
b481de9c | 5593 | IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); |
5d49f498 | 5594 | iwl_release_nic_access(priv); |
b481de9c ZY |
5595 | |
5596 | if (rfkill & 0x1) { | |
5597 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 5598 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 5599 | * sensor in adapter to kick in */ |
bb8c093b | 5600 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
5601 | thermal_spin++; |
5602 | udelay(10); | |
5603 | } | |
5604 | ||
5605 | if (thermal_spin) | |
5606 | IWL_DEBUG_INFO("Thermal calibration took %dus\n", | |
5607 | thermal_spin * 10); | |
5608 | } else | |
5609 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5610 | ||
9fbab516 | 5611 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
5612 | set_bit(STATUS_ALIVE, &priv->status); |
5613 | ||
5614 | /* Clear out the uCode error bit if it is set */ | |
5615 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5616 | ||
bb8c093b | 5617 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
5618 | return; |
5619 | ||
36d6825b | 5620 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
5621 | |
5622 | priv->active_rate = priv->rates_mask; | |
5623 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5624 | ||
bb8c093b | 5625 | iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5626 | |
bb8c093b CH |
5627 | if (iwl3945_is_associated(priv)) { |
5628 | struct iwl3945_rxon_cmd *active_rxon = | |
f2c7e521 | 5629 | (struct iwl3945_rxon_cmd *)(&priv->active39_rxon); |
b481de9c | 5630 | |
f2c7e521 AK |
5631 | memcpy(&priv->staging39_rxon, &priv->active39_rxon, |
5632 | sizeof(priv->staging39_rxon)); | |
b481de9c ZY |
5633 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5634 | } else { | |
5635 | /* Initialize our rx_config data */ | |
60294de3 | 5636 | iwl3945_connection_init_rx_config(priv, priv->iw_mode); |
f2c7e521 | 5637 | memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
b481de9c ZY |
5638 | } |
5639 | ||
9fbab516 | 5640 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5641 | iwl3945_send_bt_config(priv); |
b481de9c ZY |
5642 | |
5643 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5644 | iwl3945_commit_rxon(priv); |
b481de9c | 5645 | |
b481de9c ZY |
5646 | iwl3945_reg_txpower_periodic(priv); |
5647 | ||
fe00b5a5 RC |
5648 | iwl3945_led_register(priv); |
5649 | ||
b481de9c | 5650 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5651 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5652 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5653 | |
5654 | if (priv->error_recovering) | |
bb8c093b | 5655 | iwl3945_error_recovery(priv); |
b481de9c | 5656 | |
9bdf5eca MA |
5657 | /* reassociate for ADHOC mode */ |
5658 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
5659 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
5660 | priv->vif); | |
5661 | if (beacon) | |
5662 | iwl3945_mac_beacon_update(priv->hw, beacon); | |
5663 | } | |
5664 | ||
b481de9c ZY |
5665 | return; |
5666 | ||
5667 | restart: | |
5668 | queue_work(priv->workqueue, &priv->restart); | |
5669 | } | |
5670 | ||
4a8a4322 | 5671 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 5672 | |
4a8a4322 | 5673 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
5674 | { |
5675 | unsigned long flags; | |
5676 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5677 | struct ieee80211_conf *conf = NULL; | |
5678 | ||
5679 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5680 | ||
5681 | conf = ieee80211_get_hw_conf(priv->hw); | |
5682 | ||
5683 | if (!exit_pending) | |
5684 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5685 | ||
ab53d8af | 5686 | iwl3945_led_unregister(priv); |
bb8c093b | 5687 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5688 | |
5689 | /* Unblock any waiting calls */ | |
5690 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5691 | ||
b481de9c ZY |
5692 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5693 | * exiting the module */ | |
5694 | if (!exit_pending) | |
5695 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5696 | ||
5697 | /* stop and reset the on-board processor */ | |
5d49f498 | 5698 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5699 | |
5700 | /* tell the device to stop sending interrupts */ | |
0359facc | 5701 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5702 | iwl3945_disable_interrupts(priv); |
0359facc MA |
5703 | spin_unlock_irqrestore(&priv->lock, flags); |
5704 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5705 | |
5706 | if (priv->mac80211_registered) | |
5707 | ieee80211_stop_queues(priv->hw); | |
5708 | ||
bb8c093b | 5709 | /* If we have not previously called iwl3945_init() then |
b481de9c | 5710 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
bb8c093b | 5711 | if (!iwl3945_is_init(priv)) { |
b481de9c ZY |
5712 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5713 | STATUS_RF_KILL_HW | | |
5714 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5715 | STATUS_RF_KILL_SW | | |
9788864e RC |
5716 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5717 | STATUS_GEO_CONFIGURED | | |
b481de9c | 5718 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
ebef2008 AK |
5719 | STATUS_IN_SUSPEND | |
5720 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
5721 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
5722 | goto exit; |
5723 | } | |
5724 | ||
5725 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5726 | * SUSPEND bits and continue taking the NIC down. */ | |
5727 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5728 | STATUS_RF_KILL_HW | | |
5729 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5730 | STATUS_RF_KILL_SW | | |
9788864e RC |
5731 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5732 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5733 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5734 | STATUS_IN_SUSPEND | | |
5735 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
ebef2008 AK |
5736 | STATUS_FW_ERROR | |
5737 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
5738 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
5739 | |
5740 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 5741 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5742 | spin_unlock_irqrestore(&priv->lock, flags); |
5743 | ||
bb8c093b CH |
5744 | iwl3945_hw_txq_ctx_stop(priv); |
5745 | iwl3945_hw_rxq_stop(priv); | |
b481de9c ZY |
5746 | |
5747 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 AK |
5748 | if (!iwl_grab_nic_access(priv)) { |
5749 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5750 | APMG_CLK_VAL_DMA_CLK_RQT); |
5d49f498 | 5751 | iwl_release_nic_access(priv); |
b481de9c ZY |
5752 | } |
5753 | spin_unlock_irqrestore(&priv->lock, flags); | |
5754 | ||
5755 | udelay(5); | |
5756 | ||
bb8c093b | 5757 | iwl3945_hw_nic_stop_master(priv); |
5d49f498 | 5758 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
bb8c093b | 5759 | iwl3945_hw_nic_reset(priv); |
b481de9c ZY |
5760 | |
5761 | exit: | |
3d24a9f7 | 5762 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
5763 | |
5764 | if (priv->ibss_beacon) | |
5765 | dev_kfree_skb(priv->ibss_beacon); | |
5766 | priv->ibss_beacon = NULL; | |
5767 | ||
5768 | /* clear out any free frames */ | |
bb8c093b | 5769 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
5770 | } |
5771 | ||
4a8a4322 | 5772 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
5773 | { |
5774 | mutex_lock(&priv->mutex); | |
bb8c093b | 5775 | __iwl3945_down(priv); |
b481de9c | 5776 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5777 | |
bb8c093b | 5778 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
5779 | } |
5780 | ||
5781 | #define MAX_HW_RESTARTS 5 | |
5782 | ||
4a8a4322 | 5783 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
5784 | { |
5785 | int rc, i; | |
5786 | ||
5787 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5788 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
5789 | return -EIO; | |
5790 | } | |
5791 | ||
5792 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
5793 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
5794 | "parameter)\n"); | |
e655b9f0 ZY |
5795 | return -ENODEV; |
5796 | } | |
5797 | ||
e903fbd4 | 5798 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
a96a27f9 | 5799 | IWL_ERROR("ucode not available for device bring up\n"); |
e903fbd4 RC |
5800 | return -EIO; |
5801 | } | |
5802 | ||
e655b9f0 | 5803 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 5804 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
5805 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
5806 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5807 | else { | |
5808 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5809 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
5810 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); | |
5811 | return -ENODEV; | |
5812 | } | |
b481de9c | 5813 | } |
80fcc9e2 | 5814 | |
5d49f498 | 5815 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 5816 | |
bb8c093b | 5817 | rc = iwl3945_hw_nic_init(priv); |
b481de9c ZY |
5818 | if (rc) { |
5819 | IWL_ERROR("Unable to int nic\n"); | |
5820 | return rc; | |
5821 | } | |
5822 | ||
5823 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
5824 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5825 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
5826 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
5827 | ||
5828 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 5829 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
bb8c093b | 5830 | iwl3945_enable_interrupts(priv); |
b481de9c ZY |
5831 | |
5832 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
5833 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5834 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
5835 | |
5836 | /* Copy original ucode data image from disk into backup cache. | |
5837 | * This will be used to initialize the on-board processor's | |
5838 | * data SRAM for a clean start when the runtime program first loads. */ | |
5839 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 5840 | priv->ucode_data.len); |
b481de9c | 5841 | |
e655b9f0 ZY |
5842 | /* We return success when we resume from suspend and rf_kill is on. */ |
5843 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5844 | return 0; | |
5845 | ||
b481de9c ZY |
5846 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
5847 | ||
bb8c093b | 5848 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5849 | |
5850 | /* load bootstrap state machine, | |
5851 | * load bootstrap program into processor's memory, | |
5852 | * prepare to load the "initialize" uCode */ | |
bb8c093b | 5853 | rc = iwl3945_load_bsm(priv); |
b481de9c ZY |
5854 | |
5855 | if (rc) { | |
5856 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc); | |
5857 | continue; | |
5858 | } | |
5859 | ||
5860 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 5861 | iwl3945_nic_start(priv); |
b481de9c | 5862 | |
b481de9c ZY |
5863 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
5864 | ||
5865 | return 0; | |
5866 | } | |
5867 | ||
5868 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 5869 | __iwl3945_down(priv); |
ebef2008 | 5870 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
5871 | |
5872 | /* tried to restart and config the device for as long as our | |
5873 | * patience could withstand */ | |
5874 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
5875 | return -EIO; | |
5876 | } | |
5877 | ||
5878 | ||
5879 | /***************************************************************************** | |
5880 | * | |
5881 | * Workqueue callbacks | |
5882 | * | |
5883 | *****************************************************************************/ | |
5884 | ||
bb8c093b | 5885 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 5886 | { |
4a8a4322 AK |
5887 | struct iwl_priv *priv = |
5888 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
5889 | |
5890 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5891 | return; | |
5892 | ||
5893 | mutex_lock(&priv->mutex); | |
bb8c093b | 5894 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
5895 | mutex_unlock(&priv->mutex); |
5896 | } | |
5897 | ||
bb8c093b | 5898 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 5899 | { |
4a8a4322 AK |
5900 | struct iwl_priv *priv = |
5901 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
5902 | |
5903 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5904 | return; | |
5905 | ||
5906 | mutex_lock(&priv->mutex); | |
bb8c093b | 5907 | iwl3945_alive_start(priv); |
b481de9c ZY |
5908 | mutex_unlock(&priv->mutex); |
5909 | } | |
5910 | ||
bb8c093b | 5911 | static void iwl3945_bg_rf_kill(struct work_struct *work) |
b481de9c | 5912 | { |
4a8a4322 | 5913 | struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill); |
b481de9c ZY |
5914 | |
5915 | wake_up_interruptible(&priv->wait_command_queue); | |
5916 | ||
5917 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5918 | return; | |
5919 | ||
5920 | mutex_lock(&priv->mutex); | |
5921 | ||
bb8c093b | 5922 | if (!iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
5923 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
5924 | "HW and/or SW RF Kill no longer active, restarting " | |
5925 | "device\n"); | |
5926 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5927 | queue_work(priv->workqueue, &priv->restart); | |
5928 | } else { | |
5929 | ||
5930 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5931 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
5932 | "disabled by SW switch\n"); | |
5933 | else | |
5934 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
5935 | "Kill switch must be turned off for " | |
5936 | "wireless networking to work.\n"); | |
5937 | } | |
ebef2008 | 5938 | |
b481de9c | 5939 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 5940 | iwl3945_rfkill_set_hw_state(priv); |
b481de9c ZY |
5941 | } |
5942 | ||
5943 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) | |
5944 | ||
bb8c093b | 5945 | static void iwl3945_bg_scan_check(struct work_struct *data) |
b481de9c | 5946 | { |
4a8a4322 AK |
5947 | struct iwl_priv *priv = |
5948 | container_of(data, struct iwl_priv, scan_check.work); | |
b481de9c ZY |
5949 | |
5950 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5951 | return; | |
5952 | ||
5953 | mutex_lock(&priv->mutex); | |
5954 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
5955 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5956 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
5957 | "Scan completion watchdog resetting adapter (%dms)\n", | |
5958 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
15e869d8 | 5959 | |
b481de9c | 5960 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 5961 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
5962 | } |
5963 | mutex_unlock(&priv->mutex); | |
5964 | } | |
5965 | ||
bb8c093b | 5966 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 5967 | { |
4a8a4322 AK |
5968 | struct iwl_priv *priv = |
5969 | container_of(data, struct iwl_priv, request_scan); | |
bb8c093b | 5970 | struct iwl3945_host_cmd cmd = { |
b481de9c | 5971 | .id = REPLY_SCAN_CMD, |
bb8c093b | 5972 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
5973 | .meta.flags = CMD_SIZE_HUGE, |
5974 | }; | |
5975 | int rc = 0; | |
bb8c093b | 5976 | struct iwl3945_scan_cmd *scan; |
b481de9c | 5977 | struct ieee80211_conf *conf = NULL; |
f9340520 | 5978 | u8 n_probes = 2; |
8318d78a | 5979 | enum ieee80211_band band; |
9387b7ca | 5980 | DECLARE_SSID_BUF(ssid); |
b481de9c ZY |
5981 | |
5982 | conf = ieee80211_get_hw_conf(priv->hw); | |
5983 | ||
5984 | mutex_lock(&priv->mutex); | |
5985 | ||
bb8c093b | 5986 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
5987 | IWL_WARNING("request scan called when driver not ready.\n"); |
5988 | goto done; | |
5989 | } | |
5990 | ||
a96a27f9 | 5991 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
5992 | * was given the chance to run... */ |
5993 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
5994 | goto done; | |
5995 | ||
5996 | /* This should never be called or scheduled if there is currently | |
5997 | * a scan active in the hardware. */ | |
5998 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
5999 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
6000 | "Ignoring second request.\n"); | |
6001 | rc = -EIO; | |
6002 | goto done; | |
6003 | } | |
6004 | ||
6005 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6006 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
6007 | goto done; | |
6008 | } | |
6009 | ||
6010 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6011 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
6012 | goto done; | |
6013 | } | |
6014 | ||
bb8c093b | 6015 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6016 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
6017 | goto done; | |
6018 | } | |
6019 | ||
6020 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6021 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
6022 | goto done; | |
6023 | } | |
6024 | ||
6025 | if (!priv->scan_bands) { | |
6026 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
6027 | goto done; | |
6028 | } | |
6029 | ||
f2c7e521 AK |
6030 | if (!priv->scan39) { |
6031 | priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
b481de9c | 6032 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
f2c7e521 | 6033 | if (!priv->scan39) { |
b481de9c ZY |
6034 | rc = -ENOMEM; |
6035 | goto done; | |
6036 | } | |
6037 | } | |
f2c7e521 | 6038 | scan = priv->scan39; |
bb8c093b | 6039 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
6040 | |
6041 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
6042 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
6043 | ||
bb8c093b | 6044 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
6045 | u16 interval = 0; |
6046 | u32 extra; | |
6047 | u32 suspend_time = 100; | |
6048 | u32 scan_suspend_time = 100; | |
6049 | unsigned long flags; | |
6050 | ||
6051 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
6052 | ||
6053 | spin_lock_irqsave(&priv->lock, flags); | |
6054 | interval = priv->beacon_int; | |
6055 | spin_unlock_irqrestore(&priv->lock, flags); | |
6056 | ||
6057 | scan->suspend_time = 0; | |
15e869d8 | 6058 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
6059 | if (!interval) |
6060 | interval = suspend_time; | |
6061 | /* | |
6062 | * suspend time format: | |
6063 | * 0-19: beacon interval in usec (time before exec.) | |
6064 | * 20-23: 0 | |
6065 | * 24-31: number of beacons (suspend between channels) | |
6066 | */ | |
6067 | ||
6068 | extra = (suspend_time / interval) << 24; | |
6069 | scan_suspend_time = 0xFF0FFFFF & | |
6070 | (extra | ((suspend_time % interval) * 1024)); | |
6071 | ||
6072 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
6073 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
6074 | scan_suspend_time, interval); | |
6075 | } | |
6076 | ||
6077 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
6078 | if (priv->one_direct_scan) { | |
6079 | IWL_DEBUG_SCAN | |
6080 | ("Kicking off one direct scan for '%s'\n", | |
9387b7ca JL |
6081 | print_ssid(ssid, priv->direct_ssid, |
6082 | priv->direct_ssid_len)); | |
b481de9c ZY |
6083 | scan->direct_scan[0].id = WLAN_EID_SSID; |
6084 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
6085 | memcpy(scan->direct_scan[0].ssid, | |
6086 | priv->direct_ssid, priv->direct_ssid_len); | |
f9340520 | 6087 | n_probes++; |
f9340520 | 6088 | } else |
786b4557 | 6089 | IWL_DEBUG_SCAN("Kicking off one indirect scan.\n"); |
b481de9c ZY |
6090 | |
6091 | /* We don't build a direct scan probe request; the uCode will do | |
6092 | * that based on the direct_mask added to each channel entry */ | |
6093 | scan->tx_cmd.len = cpu_to_le16( | |
bb8c093b | 6094 | iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data, |
430cfe95 | 6095 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); |
b481de9c | 6096 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 6097 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
6098 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
6099 | ||
6100 | /* flags + rate selection */ | |
6101 | ||
66b5004d | 6102 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
6103 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
6104 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
6105 | scan->good_CRC_th = 0; | |
8318d78a | 6106 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 6107 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c ZY |
6108 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
6109 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 6110 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 6111 | } else { |
b481de9c ZY |
6112 | IWL_WARNING("Invalid scan band count\n"); |
6113 | goto done; | |
6114 | } | |
6115 | ||
6116 | /* select Rx antennas */ | |
6117 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
6118 | ||
05c914fe | 6119 | if (priv->iw_mode == NL80211_IFTYPE_MONITOR) |
b481de9c ZY |
6120 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
6121 | ||
f9340520 AK |
6122 | scan->channel_count = |
6123 | iwl3945_get_channels_for_scan(priv, band, 1, /* active */ | |
6124 | n_probes, | |
6125 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
b481de9c | 6126 | |
14b54336 RC |
6127 | if (scan->channel_count == 0) { |
6128 | IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count); | |
6129 | goto done; | |
6130 | } | |
6131 | ||
b481de9c | 6132 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 6133 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
6134 | cmd.data = scan; |
6135 | scan->len = cpu_to_le16(cmd.len); | |
6136 | ||
6137 | set_bit(STATUS_SCAN_HW, &priv->status); | |
bb8c093b | 6138 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
6139 | if (rc) |
6140 | goto done; | |
6141 | ||
6142 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
6143 | IWL_SCAN_CHECK_WATCHDOG); | |
6144 | ||
6145 | mutex_unlock(&priv->mutex); | |
6146 | return; | |
6147 | ||
6148 | done: | |
2420ebc1 MA |
6149 | /* can not perform scan make sure we clear scanning |
6150 | * bits from status so next scan request can be performed. | |
6151 | * if we dont clear scanning status bit here all next scan | |
6152 | * will fail | |
6153 | */ | |
6154 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
6155 | clear_bit(STATUS_SCANNING, &priv->status); | |
6156 | ||
01ebd063 | 6157 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
6158 | queue_work(priv->workqueue, &priv->scan_completed); |
6159 | mutex_unlock(&priv->mutex); | |
6160 | } | |
6161 | ||
bb8c093b | 6162 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 6163 | { |
4a8a4322 | 6164 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
6165 | |
6166 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6167 | return; | |
6168 | ||
6169 | mutex_lock(&priv->mutex); | |
bb8c093b | 6170 | __iwl3945_up(priv); |
b481de9c | 6171 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 6172 | iwl3945_rfkill_set_hw_state(priv); |
b481de9c ZY |
6173 | } |
6174 | ||
bb8c093b | 6175 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 6176 | { |
4a8a4322 | 6177 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
6178 | |
6179 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6180 | return; | |
6181 | ||
bb8c093b | 6182 | iwl3945_down(priv); |
b481de9c ZY |
6183 | queue_work(priv->workqueue, &priv->up); |
6184 | } | |
6185 | ||
bb8c093b | 6186 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 6187 | { |
4a8a4322 AK |
6188 | struct iwl_priv *priv = |
6189 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
6190 | |
6191 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6192 | return; | |
6193 | ||
6194 | mutex_lock(&priv->mutex); | |
bb8c093b | 6195 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
6196 | mutex_unlock(&priv->mutex); |
6197 | } | |
6198 | ||
7878a5a4 MA |
6199 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
6200 | ||
4a8a4322 | 6201 | static void iwl3945_post_associate(struct iwl_priv *priv) |
b481de9c | 6202 | { |
b481de9c ZY |
6203 | int rc = 0; |
6204 | struct ieee80211_conf *conf = NULL; | |
6205 | ||
05c914fe | 6206 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
3ac7f146 | 6207 | IWL_ERROR("%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
6208 | return; |
6209 | } | |
6210 | ||
6211 | ||
e174961c | 6212 | IWL_DEBUG_ASSOC("Associated as %d to: %pM\n", |
f2c7e521 | 6213 | priv->assoc_id, priv->active39_rxon.bssid_addr); |
b481de9c ZY |
6214 | |
6215 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6216 | return; | |
6217 | ||
322a9811 | 6218 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 6219 | return; |
322a9811 | 6220 | |
bb8c093b | 6221 | iwl3945_scan_cancel_timeout(priv, 200); |
15e869d8 | 6222 | |
b481de9c ZY |
6223 | conf = ieee80211_get_hw_conf(priv->hw); |
6224 | ||
f2c7e521 | 6225 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6226 | iwl3945_commit_rxon(priv); |
b481de9c | 6227 | |
28afaf91 | 6228 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b CH |
6229 | iwl3945_setup_rxon_timing(priv); |
6230 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6231 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6232 | if (rc) | |
6233 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6234 | "Attempting to continue.\n"); | |
6235 | ||
f2c7e521 | 6236 | priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 6237 | |
f2c7e521 | 6238 | priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c ZY |
6239 | |
6240 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6241 | priv->assoc_id, priv->beacon_int); | |
6242 | ||
6243 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
f2c7e521 | 6244 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 6245 | else |
f2c7e521 | 6246 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 6247 | |
f2c7e521 | 6248 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c | 6249 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
f2c7e521 | 6250 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 6251 | else |
f2c7e521 | 6252 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 6253 | |
05c914fe | 6254 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
f2c7e521 | 6255 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
6256 | |
6257 | } | |
6258 | ||
bb8c093b | 6259 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6260 | |
6261 | switch (priv->iw_mode) { | |
05c914fe | 6262 | case NL80211_IFTYPE_STATION: |
bb8c093b | 6263 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6264 | break; |
6265 | ||
05c914fe | 6266 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 6267 | |
ce546fd2 | 6268 | priv->assoc_id = 1; |
bb8c093b | 6269 | iwl3945_add_station(priv, priv->bssid, 0, 0); |
b481de9c | 6270 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 6271 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
6272 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
6273 | CMD_ASYNC); | |
bb8c093b CH |
6274 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
6275 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
6276 | |
6277 | break; | |
6278 | ||
6279 | default: | |
6280 | IWL_ERROR("%s Should not be called in %d mode\n", | |
3ac7f146 | 6281 | __func__, priv->iw_mode); |
b481de9c ZY |
6282 | break; |
6283 | } | |
6284 | ||
bb8c093b | 6285 | iwl3945_activate_qos(priv, 0); |
292ae174 | 6286 | |
7878a5a4 MA |
6287 | /* we have just associated, don't start scan too early */ |
6288 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
6289 | } |
6290 | ||
bb8c093b | 6291 | static void iwl3945_bg_abort_scan(struct work_struct *work) |
b481de9c | 6292 | { |
4a8a4322 | 6293 | struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan); |
b481de9c | 6294 | |
bb8c093b | 6295 | if (!iwl3945_is_ready(priv)) |
b481de9c ZY |
6296 | return; |
6297 | ||
6298 | mutex_lock(&priv->mutex); | |
6299 | ||
6300 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6301 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6302 | |
6303 | mutex_unlock(&priv->mutex); | |
6304 | } | |
6305 | ||
e8975581 | 6306 | static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed); |
76bb77e0 | 6307 | |
bb8c093b | 6308 | static void iwl3945_bg_scan_completed(struct work_struct *work) |
b481de9c | 6309 | { |
4a8a4322 AK |
6310 | struct iwl_priv *priv = |
6311 | container_of(work, struct iwl_priv, scan_completed); | |
b481de9c ZY |
6312 | |
6313 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6314 | ||
6315 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6316 | return; | |
6317 | ||
a0646470 | 6318 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
e8975581 | 6319 | iwl3945_mac_config(priv->hw, 0); |
76bb77e0 | 6320 | |
b481de9c ZY |
6321 | ieee80211_scan_completed(priv->hw); |
6322 | ||
6323 | /* Since setting the TXPOWER may have been deferred while | |
6324 | * performing the scan, fire one off */ | |
6325 | mutex_lock(&priv->mutex); | |
bb8c093b | 6326 | iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
6327 | mutex_unlock(&priv->mutex); |
6328 | } | |
6329 | ||
6330 | /***************************************************************************** | |
6331 | * | |
6332 | * mac80211 entry point functions | |
6333 | * | |
6334 | *****************************************************************************/ | |
6335 | ||
5a66926a ZY |
6336 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6337 | ||
bb8c093b | 6338 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6339 | { |
4a8a4322 | 6340 | struct iwl_priv *priv = hw->priv; |
5a66926a | 6341 | int ret; |
b481de9c ZY |
6342 | |
6343 | IWL_DEBUG_MAC80211("enter\n"); | |
6344 | ||
5a66926a ZY |
6345 | if (pci_enable_device(priv->pci_dev)) { |
6346 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6347 | return -ENODEV; | |
6348 | } | |
6349 | pci_restore_state(priv->pci_dev); | |
6350 | pci_enable_msi(priv->pci_dev); | |
6351 | ||
6352 | ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED, | |
6353 | DRV_NAME, priv); | |
6354 | if (ret) { | |
6355 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6356 | goto out_disable_msi; | |
6357 | } | |
6358 | ||
b481de9c ZY |
6359 | /* we should be verifying the device is ready to be opened */ |
6360 | mutex_lock(&priv->mutex); | |
6361 | ||
f2c7e521 | 6362 | memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd)); |
5a66926a ZY |
6363 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
6364 | * ucode filename and max sizes are card-specific. */ | |
6365 | ||
6366 | if (!priv->ucode_code.len) { | |
6367 | ret = iwl3945_read_ucode(priv); | |
6368 | if (ret) { | |
6369 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6370 | mutex_unlock(&priv->mutex); | |
6371 | goto out_release_irq; | |
6372 | } | |
6373 | } | |
b481de9c | 6374 | |
e655b9f0 | 6375 | ret = __iwl3945_up(priv); |
b481de9c ZY |
6376 | |
6377 | mutex_unlock(&priv->mutex); | |
5a66926a | 6378 | |
80fcc9e2 AG |
6379 | iwl3945_rfkill_set_hw_state(priv); |
6380 | ||
e655b9f0 ZY |
6381 | if (ret) |
6382 | goto out_release_irq; | |
6383 | ||
6384 | IWL_DEBUG_INFO("Start UP work.\n"); | |
6385 | ||
6386 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6387 | return 0; | |
6388 | ||
5a66926a ZY |
6389 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6390 | * mac80211 will not be run successfully. */ | |
6391 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6392 | test_bit(STATUS_READY, &priv->status), | |
6393 | UCODE_READY_TIMEOUT); | |
6394 | if (!ret) { | |
6395 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6396 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6397 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6398 | ret = -ETIMEDOUT; | |
6399 | goto out_release_irq; | |
6400 | } | |
6401 | } | |
6402 | ||
e655b9f0 | 6403 | priv->is_open = 1; |
b481de9c ZY |
6404 | IWL_DEBUG_MAC80211("leave\n"); |
6405 | return 0; | |
5a66926a ZY |
6406 | |
6407 | out_release_irq: | |
6408 | free_irq(priv->pci_dev->irq, priv); | |
6409 | out_disable_msi: | |
6410 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6411 | pci_disable_device(priv->pci_dev); |
6412 | priv->is_open = 0; | |
6413 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6414 | return ret; |
b481de9c ZY |
6415 | } |
6416 | ||
bb8c093b | 6417 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6418 | { |
4a8a4322 | 6419 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6420 | |
6421 | IWL_DEBUG_MAC80211("enter\n"); | |
6ef89d0a | 6422 | |
e655b9f0 ZY |
6423 | if (!priv->is_open) { |
6424 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6425 | return; | |
6426 | } | |
6427 | ||
b481de9c | 6428 | priv->is_open = 0; |
5a66926a ZY |
6429 | |
6430 | if (iwl3945_is_ready_rf(priv)) { | |
e655b9f0 ZY |
6431 | /* stop mac, cancel any scan request and clear |
6432 | * RXON_FILTER_ASSOC_MSK BIT | |
6433 | */ | |
5a66926a ZY |
6434 | mutex_lock(&priv->mutex); |
6435 | iwl3945_scan_cancel_timeout(priv, 100); | |
fde3571f | 6436 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6437 | } |
6438 | ||
5a66926a ZY |
6439 | iwl3945_down(priv); |
6440 | ||
6441 | flush_workqueue(priv->workqueue); | |
6442 | free_irq(priv->pci_dev->irq, priv); | |
6443 | pci_disable_msi(priv->pci_dev); | |
6444 | pci_save_state(priv->pci_dev); | |
6445 | pci_disable_device(priv->pci_dev); | |
6ef89d0a | 6446 | |
b481de9c | 6447 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6448 | } |
6449 | ||
e039fa4a | 6450 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 6451 | { |
4a8a4322 | 6452 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6453 | |
6454 | IWL_DEBUG_MAC80211("enter\n"); | |
6455 | ||
b481de9c | 6456 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 6457 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 6458 | |
e039fa4a | 6459 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
6460 | dev_kfree_skb_any(skb); |
6461 | ||
6462 | IWL_DEBUG_MAC80211("leave\n"); | |
637f8837 | 6463 | return NETDEV_TX_OK; |
b481de9c ZY |
6464 | } |
6465 | ||
bb8c093b | 6466 | static int iwl3945_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6467 | struct ieee80211_if_init_conf *conf) |
6468 | { | |
4a8a4322 | 6469 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6470 | unsigned long flags; |
6471 | ||
32bfd35d | 6472 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6473 | |
32bfd35d JB |
6474 | if (priv->vif) { |
6475 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
864792e3 | 6476 | return -EOPNOTSUPP; |
b481de9c ZY |
6477 | } |
6478 | ||
6479 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6480 | priv->vif = conf->vif; |
60294de3 | 6481 | priv->iw_mode = conf->type; |
b481de9c ZY |
6482 | |
6483 | spin_unlock_irqrestore(&priv->lock, flags); | |
6484 | ||
6485 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6486 | |
6487 | if (conf->mac_addr) { | |
e174961c | 6488 | IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr); |
864792e3 TW |
6489 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); |
6490 | } | |
6491 | ||
5a66926a ZY |
6492 | if (iwl3945_is_ready(priv)) |
6493 | iwl3945_set_mode(priv, conf->type); | |
b481de9c | 6494 | |
b481de9c ZY |
6495 | mutex_unlock(&priv->mutex); |
6496 | ||
5a66926a | 6497 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6498 | return 0; |
6499 | } | |
6500 | ||
6501 | /** | |
bb8c093b | 6502 | * iwl3945_mac_config - mac80211 config callback |
b481de9c ZY |
6503 | * |
6504 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6505 | * be set inappropriately and the driver currently sets the hardware up to | |
6506 | * use it whenever needed. | |
6507 | */ | |
e8975581 | 6508 | static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed) |
b481de9c | 6509 | { |
4a8a4322 | 6510 | struct iwl_priv *priv = hw->priv; |
d20b3c65 | 6511 | const struct iwl_channel_info *ch_info; |
e8975581 | 6512 | struct ieee80211_conf *conf = &hw->conf; |
b481de9c | 6513 | unsigned long flags; |
76bb77e0 | 6514 | int ret = 0; |
b481de9c ZY |
6515 | |
6516 | mutex_lock(&priv->mutex); | |
8318d78a | 6517 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6518 | |
bb8c093b | 6519 | if (!iwl3945_is_ready(priv)) { |
b481de9c | 6520 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6521 | ret = -EIO; |
6522 | goto out; | |
b481de9c ZY |
6523 | } |
6524 | ||
bb8c093b | 6525 | if (unlikely(!iwl3945_param_disable_hw_scan && |
b481de9c | 6526 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6527 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6528 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6529 | mutex_unlock(&priv->mutex); |
a0646470 | 6530 | return 0; |
b481de9c ZY |
6531 | } |
6532 | ||
6533 | spin_lock_irqsave(&priv->lock, flags); | |
6534 | ||
8318d78a JB |
6535 | ch_info = iwl3945_get_channel_info(priv, conf->channel->band, |
6536 | conf->channel->hw_value); | |
b481de9c | 6537 | if (!is_channel_valid(ch_info)) { |
66b5004d | 6538 | IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n", |
8318d78a | 6539 | conf->channel->hw_value, conf->channel->band); |
b481de9c ZY |
6540 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6541 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6542 | ret = -EINVAL; |
6543 | goto out; | |
b481de9c ZY |
6544 | } |
6545 | ||
8318d78a | 6546 | iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value); |
b481de9c | 6547 | |
8318d78a | 6548 | iwl3945_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6549 | |
6550 | /* The list of supported rates and rate mask can be different | |
6551 | * for each phymode; since the phymode may have changed, reset | |
6552 | * the rate mask to what mac80211 lists */ | |
bb8c093b | 6553 | iwl3945_set_rate(priv); |
b481de9c ZY |
6554 | |
6555 | spin_unlock_irqrestore(&priv->lock, flags); | |
6556 | ||
6557 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6558 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6559 | iwl3945_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6560 | goto out; |
b481de9c ZY |
6561 | } |
6562 | #endif | |
6563 | ||
bb8c093b | 6564 | iwl3945_radio_kill_sw(priv, !conf->radio_enabled); |
b481de9c ZY |
6565 | |
6566 | if (!conf->radio_enabled) { | |
6567 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6568 | goto out; |
b481de9c ZY |
6569 | } |
6570 | ||
bb8c093b | 6571 | if (iwl3945_is_rfkill(priv)) { |
b481de9c | 6572 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6573 | ret = -EIO; |
6574 | goto out; | |
b481de9c ZY |
6575 | } |
6576 | ||
bb8c093b | 6577 | iwl3945_set_rate(priv); |
b481de9c | 6578 | |
f2c7e521 AK |
6579 | if (memcmp(&priv->active39_rxon, |
6580 | &priv->staging39_rxon, sizeof(priv->staging39_rxon))) | |
bb8c093b | 6581 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6582 | else |
6583 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6584 | ||
6585 | IWL_DEBUG_MAC80211("leave\n"); | |
6586 | ||
76bb77e0 | 6587 | out: |
a0646470 | 6588 | clear_bit(STATUS_CONF_PENDING, &priv->status); |
b481de9c | 6589 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6590 | return ret; |
b481de9c ZY |
6591 | } |
6592 | ||
4a8a4322 | 6593 | static void iwl3945_config_ap(struct iwl_priv *priv) |
b481de9c ZY |
6594 | { |
6595 | int rc = 0; | |
6596 | ||
d986bcd1 | 6597 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6598 | return; |
6599 | ||
6600 | /* The following should be done only at AP bring up */ | |
5d1e2325 | 6601 | if (!(iwl3945_is_associated(priv))) { |
b481de9c ZY |
6602 | |
6603 | /* RXON - unassoc (to set timing command) */ | |
f2c7e521 | 6604 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6605 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6606 | |
6607 | /* RXON Timing */ | |
28afaf91 | 6608 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b CH |
6609 | iwl3945_setup_rxon_timing(priv); |
6610 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6611 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6612 | if (rc) | |
6613 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6614 | "Attempting to continue.\n"); | |
6615 | ||
6616 | /* FIXME: what should be the assoc_id for AP? */ | |
f2c7e521 | 6617 | priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 6618 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
f2c7e521 | 6619 | priv->staging39_rxon.flags |= |
b481de9c ZY |
6620 | RXON_FLG_SHORT_PREAMBLE_MSK; |
6621 | else | |
f2c7e521 | 6622 | priv->staging39_rxon.flags &= |
b481de9c ZY |
6623 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
6624 | ||
f2c7e521 | 6625 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c ZY |
6626 | if (priv->assoc_capability & |
6627 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
f2c7e521 | 6628 | priv->staging39_rxon.flags |= |
b481de9c ZY |
6629 | RXON_FLG_SHORT_SLOT_MSK; |
6630 | else | |
f2c7e521 | 6631 | priv->staging39_rxon.flags &= |
b481de9c ZY |
6632 | ~RXON_FLG_SHORT_SLOT_MSK; |
6633 | ||
05c914fe | 6634 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
f2c7e521 | 6635 | priv->staging39_rxon.flags &= |
b481de9c ZY |
6636 | ~RXON_FLG_SHORT_SLOT_MSK; |
6637 | } | |
6638 | /* restore RXON assoc */ | |
f2c7e521 | 6639 | priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6640 | iwl3945_commit_rxon(priv); |
b5323d36 | 6641 | iwl3945_add_station(priv, iwl_bcast_addr, 0, 0); |
556f8db7 | 6642 | } |
bb8c093b | 6643 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
6644 | |
6645 | /* FIXME - we need to add code here to detect a totally new | |
6646 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6647 | * clear sta table, add BCAST sta... */ | |
6648 | } | |
6649 | ||
32bfd35d JB |
6650 | static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, |
6651 | struct ieee80211_vif *vif, | |
4a8a4322 | 6652 | struct ieee80211_if_conf *conf) |
b481de9c | 6653 | { |
4a8a4322 | 6654 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6655 | int rc; |
6656 | ||
6657 | if (conf == NULL) | |
6658 | return -EIO; | |
6659 | ||
b716bb91 EG |
6660 | if (priv->vif != vif) { |
6661 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
b716bb91 EG |
6662 | return 0; |
6663 | } | |
6664 | ||
9d139c81 | 6665 | /* handle this temporarily here */ |
05c914fe | 6666 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
9d139c81 JB |
6667 | conf->changed & IEEE80211_IFCC_BEACON) { |
6668 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); | |
6669 | if (!beacon) | |
6670 | return -ENOMEM; | |
9bdf5eca | 6671 | mutex_lock(&priv->mutex); |
9d139c81 | 6672 | rc = iwl3945_mac_beacon_update(hw, beacon); |
9bdf5eca | 6673 | mutex_unlock(&priv->mutex); |
9d139c81 JB |
6674 | if (rc) |
6675 | return rc; | |
6676 | } | |
6677 | ||
5a66926a ZY |
6678 | if (!iwl3945_is_alive(priv)) |
6679 | return -EAGAIN; | |
6680 | ||
b481de9c ZY |
6681 | mutex_lock(&priv->mutex); |
6682 | ||
b481de9c | 6683 | if (conf->bssid) |
e174961c | 6684 | IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid); |
b481de9c | 6685 | |
4150c572 JB |
6686 | /* |
6687 | * very dubious code was here; the probe filtering flag is never set: | |
6688 | * | |
b481de9c ZY |
6689 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6690 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6691 | */ |
b481de9c | 6692 | |
05c914fe | 6693 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
b481de9c ZY |
6694 | if (!conf->bssid) { |
6695 | conf->bssid = priv->mac_addr; | |
6696 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
e174961c JB |
6697 | IWL_DEBUG_MAC80211("bssid was set to: %pM\n", |
6698 | conf->bssid); | |
b481de9c ZY |
6699 | } |
6700 | if (priv->ibss_beacon) | |
6701 | dev_kfree_skb(priv->ibss_beacon); | |
6702 | ||
9d139c81 | 6703 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); |
b481de9c ZY |
6704 | } |
6705 | ||
fde3571f MA |
6706 | if (iwl3945_is_rfkill(priv)) |
6707 | goto done; | |
6708 | ||
b481de9c ZY |
6709 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6710 | !is_multicast_ether_addr(conf->bssid)) { | |
6711 | /* If there is currently a HW scan going on in the background | |
6712 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 6713 | if (iwl3945_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
6714 | IWL_WARNING("Aborted scan still in progress " |
6715 | "after 100ms\n"); | |
6716 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6717 | mutex_unlock(&priv->mutex); | |
6718 | return -EAGAIN; | |
6719 | } | |
f2c7e521 | 6720 | memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN); |
b481de9c ZY |
6721 | |
6722 | /* TODO: Audit driver for usage of these members and see | |
6723 | * if mac80211 deprecates them (priv->bssid looks like it | |
6724 | * shouldn't be there, but I haven't scanned the IBSS code | |
6725 | * to verify) - jpk */ | |
6726 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6727 | ||
05c914fe | 6728 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
bb8c093b | 6729 | iwl3945_config_ap(priv); |
b481de9c | 6730 | else { |
bb8c093b | 6731 | rc = iwl3945_commit_rxon(priv); |
05c914fe | 6732 | if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc) |
bb8c093b | 6733 | iwl3945_add_station(priv, |
f2c7e521 | 6734 | priv->active39_rxon.bssid_addr, 1, 0); |
b481de9c ZY |
6735 | } |
6736 | ||
6737 | } else { | |
bb8c093b | 6738 | iwl3945_scan_cancel_timeout(priv, 100); |
f2c7e521 | 6739 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6740 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6741 | } |
6742 | ||
fde3571f | 6743 | done: |
b481de9c ZY |
6744 | IWL_DEBUG_MAC80211("leave\n"); |
6745 | mutex_unlock(&priv->mutex); | |
6746 | ||
6747 | return 0; | |
6748 | } | |
6749 | ||
bb8c093b | 6750 | static void iwl3945_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
6751 | unsigned int changed_flags, |
6752 | unsigned int *total_flags, | |
6753 | int mc_count, struct dev_addr_list *mc_list) | |
6754 | { | |
4a8a4322 | 6755 | struct iwl_priv *priv = hw->priv; |
f2c7e521 | 6756 | __le32 *filter_flags = &priv->staging39_rxon.filter_flags; |
25b3f57c | 6757 | |
352bc8de ZY |
6758 | IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", |
6759 | changed_flags, *total_flags); | |
6760 | ||
6761 | if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) { | |
6762 | if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) | |
6763 | *filter_flags |= RXON_FILTER_PROMISC_MSK; | |
6764 | else | |
6765 | *filter_flags &= ~RXON_FILTER_PROMISC_MSK; | |
6766 | } | |
6767 | if (changed_flags & FIF_ALLMULTI) { | |
6768 | if (*total_flags & FIF_ALLMULTI) | |
6769 | *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK; | |
6770 | else | |
6771 | *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK; | |
6772 | } | |
6773 | if (changed_flags & FIF_CONTROL) { | |
6774 | if (*total_flags & FIF_CONTROL) | |
6775 | *filter_flags |= RXON_FILTER_CTL2HOST_MSK; | |
6776 | else | |
6777 | *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK; | |
5ec03976 | 6778 | } |
352bc8de ZY |
6779 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
6780 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
6781 | *filter_flags |= RXON_FILTER_BCON_AWARE_MSK; | |
6782 | else | |
6783 | *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK; | |
6784 | } | |
6785 | ||
6786 | /* We avoid iwl_commit_rxon here to commit the new filter flags | |
6787 | * since mac80211 will call ieee80211_hw_config immediately. | |
6788 | * (mc_list is not supported at this time). Otherwise, we need to | |
6789 | * queue a background iwl_commit_rxon work. | |
6790 | */ | |
6791 | ||
6792 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
25b3f57c | 6793 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; |
4150c572 JB |
6794 | } |
6795 | ||
bb8c093b | 6796 | static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6797 | struct ieee80211_if_init_conf *conf) |
6798 | { | |
4a8a4322 | 6799 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6800 | |
6801 | IWL_DEBUG_MAC80211("enter\n"); | |
6802 | ||
6803 | mutex_lock(&priv->mutex); | |
6ef89d0a | 6804 | |
fde3571f MA |
6805 | if (iwl3945_is_ready_rf(priv)) { |
6806 | iwl3945_scan_cancel_timeout(priv, 100); | |
f2c7e521 | 6807 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
fde3571f MA |
6808 | iwl3945_commit_rxon(priv); |
6809 | } | |
32bfd35d JB |
6810 | if (priv->vif == conf->vif) { |
6811 | priv->vif = NULL; | |
b481de9c | 6812 | memset(priv->bssid, 0, ETH_ALEN); |
b481de9c ZY |
6813 | } |
6814 | mutex_unlock(&priv->mutex); | |
6815 | ||
6816 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
6817 | } |
6818 | ||
cd56d331 AK |
6819 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
6820 | ||
6821 | static void iwl3945_bss_info_changed(struct ieee80211_hw *hw, | |
6822 | struct ieee80211_vif *vif, | |
6823 | struct ieee80211_bss_conf *bss_conf, | |
6824 | u32 changes) | |
6825 | { | |
4a8a4322 | 6826 | struct iwl_priv *priv = hw->priv; |
cd56d331 AK |
6827 | |
6828 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); | |
6829 | ||
6830 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { | |
6831 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", | |
6832 | bss_conf->use_short_preamble); | |
6833 | if (bss_conf->use_short_preamble) | |
f2c7e521 | 6834 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
cd56d331 | 6835 | else |
f2c7e521 | 6836 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
cd56d331 AK |
6837 | } |
6838 | ||
6839 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
6840 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); | |
6841 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) | |
f2c7e521 | 6842 | priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
cd56d331 | 6843 | else |
f2c7e521 | 6844 | priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; |
cd56d331 AK |
6845 | } |
6846 | ||
6847 | if (changes & BSS_CHANGED_ASSOC) { | |
6848 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); | |
6849 | /* This should never happen as this function should | |
6850 | * never be called from interrupt context. */ | |
6851 | if (WARN_ON_ONCE(in_interrupt())) | |
6852 | return; | |
6853 | if (bss_conf->assoc) { | |
6854 | priv->assoc_id = bss_conf->aid; | |
6855 | priv->beacon_int = bss_conf->beacon_int; | |
28afaf91 | 6856 | priv->timestamp = bss_conf->timestamp; |
cd56d331 AK |
6857 | priv->assoc_capability = bss_conf->assoc_capability; |
6858 | priv->next_scan_jiffies = jiffies + | |
6859 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
6860 | mutex_lock(&priv->mutex); | |
6861 | iwl3945_post_associate(priv); | |
6862 | mutex_unlock(&priv->mutex); | |
6863 | } else { | |
6864 | priv->assoc_id = 0; | |
6865 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
6866 | } | |
6867 | } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) { | |
6868 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
6869 | iwl3945_send_rxon_assoc(priv); | |
6870 | } | |
6871 | ||
6872 | } | |
6873 | ||
bb8c093b | 6874 | static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
6875 | { |
6876 | int rc = 0; | |
6877 | unsigned long flags; | |
4a8a4322 | 6878 | struct iwl_priv *priv = hw->priv; |
9387b7ca | 6879 | DECLARE_SSID_BUF(ssid_buf); |
b481de9c ZY |
6880 | |
6881 | IWL_DEBUG_MAC80211("enter\n"); | |
6882 | ||
15e869d8 | 6883 | mutex_lock(&priv->mutex); |
b481de9c ZY |
6884 | spin_lock_irqsave(&priv->lock, flags); |
6885 | ||
bb8c093b | 6886 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
6887 | rc = -EIO; |
6888 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
6889 | goto out_unlock; | |
6890 | } | |
6891 | ||
7878a5a4 MA |
6892 | /* we don't schedule scan within next_scan_jiffies period */ |
6893 | if (priv->next_scan_jiffies && | |
6894 | time_after(priv->next_scan_jiffies, jiffies)) { | |
6895 | rc = -EAGAIN; | |
6896 | goto out_unlock; | |
6897 | } | |
15dbf1b7 BM |
6898 | /* if we just finished scan ask for delay for a broadcast scan */ |
6899 | if ((len == 0) && priv->last_scan_jiffies && | |
6900 | time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN, | |
6901 | jiffies)) { | |
b481de9c ZY |
6902 | rc = -EAGAIN; |
6903 | goto out_unlock; | |
6904 | } | |
6905 | if (len) { | |
7878a5a4 | 6906 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
9387b7ca | 6907 | print_ssid(ssid_buf, ssid, len), (int)len); |
b481de9c ZY |
6908 | |
6909 | priv->one_direct_scan = 1; | |
6910 | priv->direct_ssid_len = (u8) | |
6911 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
6912 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
6ef89d0a MA |
6913 | } else |
6914 | priv->one_direct_scan = 0; | |
b481de9c | 6915 | |
bb8c093b | 6916 | rc = iwl3945_scan_initiate(priv); |
b481de9c ZY |
6917 | |
6918 | IWL_DEBUG_MAC80211("leave\n"); | |
6919 | ||
6920 | out_unlock: | |
6921 | spin_unlock_irqrestore(&priv->lock, flags); | |
15e869d8 | 6922 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
6923 | |
6924 | return rc; | |
6925 | } | |
6926 | ||
bb8c093b | 6927 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
6928 | const u8 *local_addr, const u8 *addr, |
6929 | struct ieee80211_key_conf *key) | |
6930 | { | |
4a8a4322 | 6931 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6932 | int rc = 0; |
6933 | u8 sta_id; | |
6934 | ||
6935 | IWL_DEBUG_MAC80211("enter\n"); | |
6936 | ||
bb8c093b | 6937 | if (!iwl3945_param_hwcrypto) { |
b481de9c ZY |
6938 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
6939 | return -EOPNOTSUPP; | |
6940 | } | |
6941 | ||
6942 | if (is_zero_ether_addr(addr)) | |
6943 | /* only support pairwise keys */ | |
6944 | return -EOPNOTSUPP; | |
6945 | ||
bb8c093b | 6946 | sta_id = iwl3945_hw_find_station(priv, addr); |
b481de9c | 6947 | if (sta_id == IWL_INVALID_STATION) { |
e174961c JB |
6948 | IWL_DEBUG_MAC80211("leave - %pM not in station map.\n", |
6949 | addr); | |
b481de9c ZY |
6950 | return -EINVAL; |
6951 | } | |
6952 | ||
6953 | mutex_lock(&priv->mutex); | |
6954 | ||
bb8c093b | 6955 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 6956 | |
b481de9c ZY |
6957 | switch (cmd) { |
6958 | case SET_KEY: | |
bb8c093b | 6959 | rc = iwl3945_update_sta_key_info(priv, key, sta_id); |
b481de9c | 6960 | if (!rc) { |
bb8c093b CH |
6961 | iwl3945_set_rxon_hwcrypto(priv, 1); |
6962 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
6963 | key->hw_key_idx = sta_id; |
6964 | IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n"); | |
6965 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
6966 | } | |
6967 | break; | |
6968 | case DISABLE_KEY: | |
bb8c093b | 6969 | rc = iwl3945_clear_sta_key_info(priv, sta_id); |
b481de9c | 6970 | if (!rc) { |
bb8c093b CH |
6971 | iwl3945_set_rxon_hwcrypto(priv, 0); |
6972 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
6973 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); |
6974 | } | |
6975 | break; | |
6976 | default: | |
6977 | rc = -EINVAL; | |
6978 | } | |
6979 | ||
6980 | IWL_DEBUG_MAC80211("leave\n"); | |
6981 | mutex_unlock(&priv->mutex); | |
6982 | ||
6983 | return rc; | |
6984 | } | |
6985 | ||
e100bb64 | 6986 | static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
b481de9c ZY |
6987 | const struct ieee80211_tx_queue_params *params) |
6988 | { | |
4a8a4322 | 6989 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6990 | unsigned long flags; |
6991 | int q; | |
b481de9c ZY |
6992 | |
6993 | IWL_DEBUG_MAC80211("enter\n"); | |
6994 | ||
bb8c093b | 6995 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
6996 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
6997 | return -EIO; | |
6998 | } | |
6999 | ||
7000 | if (queue >= AC_NUM) { | |
7001 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
7002 | return 0; | |
7003 | } | |
7004 | ||
b481de9c ZY |
7005 | q = AC_NUM - 1 - queue; |
7006 | ||
7007 | spin_lock_irqsave(&priv->lock, flags); | |
7008 | ||
7009 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
7010 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
7011 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
7012 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 7013 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
7014 | |
7015 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
7016 | priv->qos_data.qos_active = 1; | |
7017 | ||
7018 | spin_unlock_irqrestore(&priv->lock, flags); | |
7019 | ||
7020 | mutex_lock(&priv->mutex); | |
05c914fe | 7021 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
bb8c093b CH |
7022 | iwl3945_activate_qos(priv, 1); |
7023 | else if (priv->assoc_id && iwl3945_is_associated(priv)) | |
7024 | iwl3945_activate_qos(priv, 0); | |
b481de9c ZY |
7025 | |
7026 | mutex_unlock(&priv->mutex); | |
7027 | ||
b481de9c ZY |
7028 | IWL_DEBUG_MAC80211("leave\n"); |
7029 | return 0; | |
7030 | } | |
7031 | ||
bb8c093b | 7032 | static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7033 | struct ieee80211_tx_queue_stats *stats) |
7034 | { | |
4a8a4322 | 7035 | struct iwl_priv *priv = hw->priv; |
b481de9c | 7036 | int i, avail; |
bb8c093b | 7037 | struct iwl3945_tx_queue *txq; |
d20b3c65 | 7038 | struct iwl_queue *q; |
b481de9c ZY |
7039 | unsigned long flags; |
7040 | ||
7041 | IWL_DEBUG_MAC80211("enter\n"); | |
7042 | ||
bb8c093b | 7043 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7044 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7045 | return -EIO; | |
7046 | } | |
7047 | ||
7048 | spin_lock_irqsave(&priv->lock, flags); | |
7049 | ||
7050 | for (i = 0; i < AC_NUM; i++) { | |
f2c7e521 | 7051 | txq = &priv->txq39[i]; |
b481de9c | 7052 | q = &txq->q; |
d20b3c65 | 7053 | avail = iwl_queue_space(q); |
b481de9c | 7054 | |
57ffc589 JB |
7055 | stats[i].len = q->n_window - avail; |
7056 | stats[i].limit = q->n_window - q->high_mark; | |
7057 | stats[i].count = q->n_window; | |
b481de9c ZY |
7058 | |
7059 | } | |
7060 | spin_unlock_irqrestore(&priv->lock, flags); | |
7061 | ||
7062 | IWL_DEBUG_MAC80211("leave\n"); | |
7063 | ||
7064 | return 0; | |
7065 | } | |
7066 | ||
bb8c093b | 7067 | static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7068 | { |
4a8a4322 | 7069 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7070 | unsigned long flags; |
7071 | ||
7072 | mutex_lock(&priv->mutex); | |
7073 | IWL_DEBUG_MAC80211("enter\n"); | |
7074 | ||
bb8c093b | 7075 | iwl3945_reset_qos(priv); |
292ae174 | 7076 | |
b481de9c ZY |
7077 | spin_lock_irqsave(&priv->lock, flags); |
7078 | priv->assoc_id = 0; | |
7079 | priv->assoc_capability = 0; | |
7080 | priv->call_post_assoc_from_beacon = 0; | |
7081 | ||
7082 | /* new association get rid of ibss beacon skb */ | |
7083 | if (priv->ibss_beacon) | |
7084 | dev_kfree_skb(priv->ibss_beacon); | |
7085 | ||
7086 | priv->ibss_beacon = NULL; | |
7087 | ||
7088 | priv->beacon_int = priv->hw->conf.beacon_int; | |
28afaf91 | 7089 | priv->timestamp = 0; |
05c914fe | 7090 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) |
b481de9c ZY |
7091 | priv->beacon_int = 0; |
7092 | ||
7093 | spin_unlock_irqrestore(&priv->lock, flags); | |
7094 | ||
fde3571f MA |
7095 | if (!iwl3945_is_ready_rf(priv)) { |
7096 | IWL_DEBUG_MAC80211("leave - not ready\n"); | |
7097 | mutex_unlock(&priv->mutex); | |
7098 | return; | |
7099 | } | |
7100 | ||
15e869d8 MA |
7101 | /* we are restarting association process |
7102 | * clear RXON_FILTER_ASSOC_MSK bit | |
7103 | */ | |
05c914fe | 7104 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
bb8c093b | 7105 | iwl3945_scan_cancel_timeout(priv, 100); |
f2c7e521 | 7106 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7107 | iwl3945_commit_rxon(priv); |
15e869d8 MA |
7108 | } |
7109 | ||
b481de9c | 7110 | /* Per mac80211.h: This is only used in IBSS mode... */ |
05c914fe | 7111 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
15e869d8 | 7112 | |
b481de9c ZY |
7113 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7114 | mutex_unlock(&priv->mutex); | |
7115 | return; | |
b481de9c ZY |
7116 | } |
7117 | ||
bb8c093b | 7118 | iwl3945_set_rate(priv); |
b481de9c ZY |
7119 | |
7120 | mutex_unlock(&priv->mutex); | |
7121 | ||
7122 | IWL_DEBUG_MAC80211("leave\n"); | |
7123 | ||
7124 | } | |
7125 | ||
e039fa4a | 7126 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 7127 | { |
4a8a4322 | 7128 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7129 | unsigned long flags; |
7130 | ||
b481de9c ZY |
7131 | IWL_DEBUG_MAC80211("enter\n"); |
7132 | ||
bb8c093b | 7133 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c | 7134 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
b481de9c ZY |
7135 | return -EIO; |
7136 | } | |
7137 | ||
05c914fe | 7138 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
b481de9c | 7139 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); |
b481de9c ZY |
7140 | return -EIO; |
7141 | } | |
7142 | ||
7143 | spin_lock_irqsave(&priv->lock, flags); | |
7144 | ||
7145 | if (priv->ibss_beacon) | |
7146 | dev_kfree_skb(priv->ibss_beacon); | |
7147 | ||
7148 | priv->ibss_beacon = skb; | |
7149 | ||
7150 | priv->assoc_id = 0; | |
7151 | ||
7152 | IWL_DEBUG_MAC80211("leave\n"); | |
7153 | spin_unlock_irqrestore(&priv->lock, flags); | |
7154 | ||
bb8c093b | 7155 | iwl3945_reset_qos(priv); |
b481de9c | 7156 | |
dc4b1e7d | 7157 | iwl3945_post_associate(priv); |
b481de9c | 7158 | |
b481de9c ZY |
7159 | |
7160 | return 0; | |
7161 | } | |
7162 | ||
7163 | /***************************************************************************** | |
7164 | * | |
7165 | * sysfs attributes | |
7166 | * | |
7167 | *****************************************************************************/ | |
7168 | ||
c8b0e6e1 | 7169 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
7170 | |
7171 | /* | |
7172 | * The following adds a new attribute to the sysfs representation | |
7173 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7174 | * used for controlling the debug level. | |
7175 | * | |
7176 | * See the level definitions in iwl for details. | |
7177 | */ | |
40b8ec0b SO |
7178 | static ssize_t show_debug_level(struct device *d, |
7179 | struct device_attribute *attr, char *buf) | |
b481de9c | 7180 | { |
4a8a4322 | 7181 | struct iwl_priv *priv = d->driver_data; |
40b8ec0b SO |
7182 | |
7183 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 7184 | } |
40b8ec0b SO |
7185 | static ssize_t store_debug_level(struct device *d, |
7186 | struct device_attribute *attr, | |
b481de9c ZY |
7187 | const char *buf, size_t count) |
7188 | { | |
4a8a4322 | 7189 | struct iwl_priv *priv = d->driver_data; |
40b8ec0b SO |
7190 | unsigned long val; |
7191 | int ret; | |
b481de9c | 7192 | |
40b8ec0b SO |
7193 | ret = strict_strtoul(buf, 0, &val); |
7194 | if (ret) | |
b481de9c ZY |
7195 | printk(KERN_INFO DRV_NAME |
7196 | ": %s is not in hex or decimal form.\n", buf); | |
7197 | else | |
40b8ec0b | 7198 | priv->debug_level = val; |
b481de9c ZY |
7199 | |
7200 | return strnlen(buf, count); | |
7201 | } | |
7202 | ||
40b8ec0b SO |
7203 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
7204 | show_debug_level, store_debug_level); | |
b481de9c | 7205 | |
c8b0e6e1 | 7206 | #endif /* CONFIG_IWL3945_DEBUG */ |
b481de9c | 7207 | |
b481de9c ZY |
7208 | static ssize_t show_temperature(struct device *d, |
7209 | struct device_attribute *attr, char *buf) | |
7210 | { | |
4a8a4322 | 7211 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 7212 | |
bb8c093b | 7213 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7214 | return -EAGAIN; |
7215 | ||
bb8c093b | 7216 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
7217 | } |
7218 | ||
7219 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7220 | ||
b481de9c ZY |
7221 | static ssize_t show_tx_power(struct device *d, |
7222 | struct device_attribute *attr, char *buf) | |
7223 | { | |
4a8a4322 | 7224 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7225 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7226 | } | |
7227 | ||
7228 | static ssize_t store_tx_power(struct device *d, | |
7229 | struct device_attribute *attr, | |
7230 | const char *buf, size_t count) | |
7231 | { | |
4a8a4322 | 7232 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7233 | char *p = (char *)buf; |
7234 | u32 val; | |
7235 | ||
7236 | val = simple_strtoul(p, &p, 10); | |
7237 | if (p == buf) | |
7238 | printk(KERN_INFO DRV_NAME | |
7239 | ": %s is not in decimal form.\n", buf); | |
7240 | else | |
bb8c093b | 7241 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7242 | |
7243 | return count; | |
7244 | } | |
7245 | ||
7246 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7247 | ||
7248 | static ssize_t show_flags(struct device *d, | |
7249 | struct device_attribute *attr, char *buf) | |
7250 | { | |
4a8a4322 | 7251 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 7252 | |
f2c7e521 | 7253 | return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags); |
b481de9c ZY |
7254 | } |
7255 | ||
7256 | static ssize_t store_flags(struct device *d, | |
7257 | struct device_attribute *attr, | |
7258 | const char *buf, size_t count) | |
7259 | { | |
4a8a4322 | 7260 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7261 | u32 flags = simple_strtoul(buf, NULL, 0); |
7262 | ||
7263 | mutex_lock(&priv->mutex); | |
f2c7e521 | 7264 | if (le32_to_cpu(priv->staging39_rxon.flags) != flags) { |
b481de9c | 7265 | /* Cancel any currently running scans... */ |
bb8c093b | 7266 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7267 | IWL_WARNING("Could not cancel scan.\n"); |
7268 | else { | |
7269 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7270 | flags); | |
f2c7e521 | 7271 | priv->staging39_rxon.flags = cpu_to_le32(flags); |
bb8c093b | 7272 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7273 | } |
7274 | } | |
7275 | mutex_unlock(&priv->mutex); | |
7276 | ||
7277 | return count; | |
7278 | } | |
7279 | ||
7280 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7281 | ||
7282 | static ssize_t show_filter_flags(struct device *d, | |
7283 | struct device_attribute *attr, char *buf) | |
7284 | { | |
4a8a4322 | 7285 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7286 | |
7287 | return sprintf(buf, "0x%04X\n", | |
f2c7e521 | 7288 | le32_to_cpu(priv->active39_rxon.filter_flags)); |
b481de9c ZY |
7289 | } |
7290 | ||
7291 | static ssize_t store_filter_flags(struct device *d, | |
7292 | struct device_attribute *attr, | |
7293 | const char *buf, size_t count) | |
7294 | { | |
4a8a4322 | 7295 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7296 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7297 | ||
7298 | mutex_lock(&priv->mutex); | |
f2c7e521 | 7299 | if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) { |
b481de9c | 7300 | /* Cancel any currently running scans... */ |
bb8c093b | 7301 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7302 | IWL_WARNING("Could not cancel scan.\n"); |
7303 | else { | |
7304 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7305 | "0x%04X\n", filter_flags); | |
f2c7e521 | 7306 | priv->staging39_rxon.filter_flags = |
b481de9c | 7307 | cpu_to_le32(filter_flags); |
bb8c093b | 7308 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7309 | } |
7310 | } | |
7311 | mutex_unlock(&priv->mutex); | |
7312 | ||
7313 | return count; | |
7314 | } | |
7315 | ||
7316 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7317 | store_filter_flags); | |
7318 | ||
c8b0e6e1 | 7319 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7320 | |
7321 | static ssize_t show_measurement(struct device *d, | |
7322 | struct device_attribute *attr, char *buf) | |
7323 | { | |
4a8a4322 | 7324 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 7325 | struct iwl_spectrum_notification measure_report; |
b481de9c | 7326 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 7327 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
7328 | unsigned long flags; |
7329 | ||
7330 | spin_lock_irqsave(&priv->lock, flags); | |
7331 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7332 | spin_unlock_irqrestore(&priv->lock, flags); | |
7333 | return 0; | |
7334 | } | |
7335 | memcpy(&measure_report, &priv->measure_report, size); | |
7336 | priv->measurement_status = 0; | |
7337 | spin_unlock_irqrestore(&priv->lock, flags); | |
7338 | ||
7339 | while (size && (PAGE_SIZE - len)) { | |
7340 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7341 | PAGE_SIZE - len, 1); | |
7342 | len = strlen(buf); | |
7343 | if (PAGE_SIZE - len) | |
7344 | buf[len++] = '\n'; | |
7345 | ||
7346 | ofs += 16; | |
7347 | size -= min(size, 16U); | |
7348 | } | |
7349 | ||
7350 | return len; | |
7351 | } | |
7352 | ||
7353 | static ssize_t store_measurement(struct device *d, | |
7354 | struct device_attribute *attr, | |
7355 | const char *buf, size_t count) | |
7356 | { | |
4a8a4322 | 7357 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 7358 | struct ieee80211_measurement_params params = { |
f2c7e521 | 7359 | .channel = le16_to_cpu(priv->active39_rxon.channel), |
b481de9c ZY |
7360 | .start_time = cpu_to_le64(priv->last_tsf), |
7361 | .duration = cpu_to_le16(1), | |
7362 | }; | |
7363 | u8 type = IWL_MEASURE_BASIC; | |
7364 | u8 buffer[32]; | |
7365 | u8 channel; | |
7366 | ||
7367 | if (count) { | |
7368 | char *p = buffer; | |
7369 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7370 | channel = simple_strtoul(p, NULL, 0); | |
7371 | if (channel) | |
7372 | params.channel = channel; | |
7373 | ||
7374 | p = buffer; | |
7375 | while (*p && *p != ' ') | |
7376 | p++; | |
7377 | if (*p) | |
7378 | type = simple_strtoul(p + 1, NULL, 0); | |
7379 | } | |
7380 | ||
7381 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7382 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7383 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7384 | |
7385 | return count; | |
7386 | } | |
7387 | ||
7388 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7389 | show_measurement, store_measurement); | |
c8b0e6e1 | 7390 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 7391 | |
b481de9c ZY |
7392 | static ssize_t store_retry_rate(struct device *d, |
7393 | struct device_attribute *attr, | |
7394 | const char *buf, size_t count) | |
7395 | { | |
4a8a4322 | 7396 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7397 | |
7398 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7399 | if (priv->retry_rate <= 0) | |
7400 | priv->retry_rate = 1; | |
7401 | ||
7402 | return count; | |
7403 | } | |
7404 | ||
7405 | static ssize_t show_retry_rate(struct device *d, | |
7406 | struct device_attribute *attr, char *buf) | |
7407 | { | |
4a8a4322 | 7408 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7409 | return sprintf(buf, "%d", priv->retry_rate); |
7410 | } | |
7411 | ||
7412 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7413 | store_retry_rate); | |
7414 | ||
7415 | static ssize_t store_power_level(struct device *d, | |
7416 | struct device_attribute *attr, | |
7417 | const char *buf, size_t count) | |
7418 | { | |
4a8a4322 | 7419 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7420 | int rc; |
7421 | int mode; | |
7422 | ||
7423 | mode = simple_strtoul(buf, NULL, 0); | |
7424 | mutex_lock(&priv->mutex); | |
7425 | ||
bb8c093b | 7426 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
7427 | rc = -EAGAIN; |
7428 | goto out; | |
7429 | } | |
7430 | ||
1125eff3 SO |
7431 | if ((mode < 1) || (mode > IWL39_POWER_LIMIT) || |
7432 | (mode == IWL39_POWER_AC)) | |
7433 | mode = IWL39_POWER_AC; | |
b481de9c ZY |
7434 | else |
7435 | mode |= IWL_POWER_ENABLED; | |
7436 | ||
7437 | if (mode != priv->power_mode) { | |
bb8c093b | 7438 | rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7439 | if (rc) { |
7440 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7441 | goto out; | |
7442 | } | |
7443 | priv->power_mode = mode; | |
7444 | } | |
7445 | ||
7446 | rc = count; | |
7447 | ||
7448 | out: | |
7449 | mutex_unlock(&priv->mutex); | |
7450 | return rc; | |
7451 | } | |
7452 | ||
7453 | #define MAX_WX_STRING 80 | |
7454 | ||
7455 | /* Values are in microsecond */ | |
7456 | static const s32 timeout_duration[] = { | |
7457 | 350000, | |
7458 | 250000, | |
7459 | 75000, | |
7460 | 37000, | |
7461 | 25000, | |
7462 | }; | |
7463 | static const s32 period_duration[] = { | |
7464 | 400000, | |
7465 | 700000, | |
7466 | 1000000, | |
7467 | 1000000, | |
7468 | 1000000 | |
7469 | }; | |
7470 | ||
7471 | static ssize_t show_power_level(struct device *d, | |
7472 | struct device_attribute *attr, char *buf) | |
7473 | { | |
4a8a4322 | 7474 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7475 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7476 | char *p = buf; | |
7477 | ||
7478 | p += sprintf(p, "%d ", level); | |
7479 | switch (level) { | |
7480 | case IWL_POWER_MODE_CAM: | |
1125eff3 | 7481 | case IWL39_POWER_AC: |
b481de9c ZY |
7482 | p += sprintf(p, "(AC)"); |
7483 | break; | |
1125eff3 | 7484 | case IWL39_POWER_BATTERY: |
b481de9c ZY |
7485 | p += sprintf(p, "(BATTERY)"); |
7486 | break; | |
7487 | default: | |
7488 | p += sprintf(p, | |
7489 | "(Timeout %dms, Period %dms)", | |
7490 | timeout_duration[level - 1] / 1000, | |
7491 | period_duration[level - 1] / 1000); | |
7492 | } | |
7493 | ||
7494 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7495 | p += sprintf(p, " OFF\n"); | |
7496 | else | |
7497 | p += sprintf(p, " \n"); | |
7498 | ||
3ac7f146 | 7499 | return p - buf + 1; |
b481de9c ZY |
7500 | |
7501 | } | |
7502 | ||
7503 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7504 | store_power_level); | |
7505 | ||
7506 | static ssize_t show_channels(struct device *d, | |
7507 | struct device_attribute *attr, char *buf) | |
7508 | { | |
8318d78a JB |
7509 | /* all this shit doesn't belong into sysfs anyway */ |
7510 | return 0; | |
b481de9c ZY |
7511 | } |
7512 | ||
7513 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7514 | ||
7515 | static ssize_t show_statistics(struct device *d, | |
7516 | struct device_attribute *attr, char *buf) | |
7517 | { | |
4a8a4322 | 7518 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7519 | u32 size = sizeof(struct iwl3945_notif_statistics); |
b481de9c | 7520 | u32 len = 0, ofs = 0; |
f2c7e521 | 7521 | u8 *data = (u8 *)&priv->statistics_39; |
b481de9c ZY |
7522 | int rc = 0; |
7523 | ||
bb8c093b | 7524 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7525 | return -EAGAIN; |
7526 | ||
7527 | mutex_lock(&priv->mutex); | |
bb8c093b | 7528 | rc = iwl3945_send_statistics_request(priv); |
b481de9c ZY |
7529 | mutex_unlock(&priv->mutex); |
7530 | ||
7531 | if (rc) { | |
7532 | len = sprintf(buf, | |
7533 | "Error sending statistics request: 0x%08X\n", rc); | |
7534 | return len; | |
7535 | } | |
7536 | ||
7537 | while (size && (PAGE_SIZE - len)) { | |
7538 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7539 | PAGE_SIZE - len, 1); | |
7540 | len = strlen(buf); | |
7541 | if (PAGE_SIZE - len) | |
7542 | buf[len++] = '\n'; | |
7543 | ||
7544 | ofs += 16; | |
7545 | size -= min(size, 16U); | |
7546 | } | |
7547 | ||
7548 | return len; | |
7549 | } | |
7550 | ||
7551 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7552 | ||
7553 | static ssize_t show_antenna(struct device *d, | |
7554 | struct device_attribute *attr, char *buf) | |
7555 | { | |
4a8a4322 | 7556 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 7557 | |
bb8c093b | 7558 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7559 | return -EAGAIN; |
7560 | ||
7561 | return sprintf(buf, "%d\n", priv->antenna); | |
7562 | } | |
7563 | ||
7564 | static ssize_t store_antenna(struct device *d, | |
7565 | struct device_attribute *attr, | |
7566 | const char *buf, size_t count) | |
7567 | { | |
7568 | int ant; | |
4a8a4322 | 7569 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7570 | |
7571 | if (count == 0) | |
7572 | return 0; | |
7573 | ||
7574 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7575 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7576 | return count; | |
7577 | } | |
7578 | ||
7579 | if ((ant >= 0) && (ant <= 2)) { | |
7580 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7581 | priv->antenna = (enum iwl3945_antenna)ant; |
b481de9c ZY |
7582 | } else |
7583 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7584 | ||
7585 | ||
7586 | return count; | |
7587 | } | |
7588 | ||
7589 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7590 | ||
7591 | static ssize_t show_status(struct device *d, | |
7592 | struct device_attribute *attr, char *buf) | |
7593 | { | |
4a8a4322 | 7594 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
bb8c093b | 7595 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7596 | return -EAGAIN; |
7597 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7598 | } | |
7599 | ||
7600 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7601 | ||
7602 | static ssize_t dump_error_log(struct device *d, | |
7603 | struct device_attribute *attr, | |
7604 | const char *buf, size_t count) | |
7605 | { | |
7606 | char *p = (char *)buf; | |
7607 | ||
7608 | if (p[0] == '1') | |
4a8a4322 | 7609 | iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7610 | |
7611 | return strnlen(buf, count); | |
7612 | } | |
7613 | ||
7614 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7615 | ||
7616 | static ssize_t dump_event_log(struct device *d, | |
7617 | struct device_attribute *attr, | |
7618 | const char *buf, size_t count) | |
7619 | { | |
7620 | char *p = (char *)buf; | |
7621 | ||
7622 | if (p[0] == '1') | |
4a8a4322 | 7623 | iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7624 | |
7625 | return strnlen(buf, count); | |
7626 | } | |
7627 | ||
7628 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7629 | ||
7630 | /***************************************************************************** | |
7631 | * | |
a96a27f9 | 7632 | * driver setup and tear down |
b481de9c ZY |
7633 | * |
7634 | *****************************************************************************/ | |
7635 | ||
4a8a4322 | 7636 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
7637 | { |
7638 | priv->workqueue = create_workqueue(DRV_NAME); | |
7639 | ||
7640 | init_waitqueue_head(&priv->wait_command_queue); | |
7641 | ||
bb8c093b CH |
7642 | INIT_WORK(&priv->up, iwl3945_bg_up); |
7643 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
7644 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
7645 | INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed); | |
7646 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
7647 | INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan); | |
7648 | INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill); | |
7649 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); | |
bb8c093b CH |
7650 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
7651 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
7652 | INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check); | |
7653 | ||
7654 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7655 | |
7656 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7657 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7658 | } |
7659 | ||
4a8a4322 | 7660 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 7661 | { |
bb8c093b | 7662 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 7663 | |
e47eb6ad | 7664 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7665 | cancel_delayed_work(&priv->scan_check); |
7666 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
7667 | cancel_work_sync(&priv->beacon_update); |
7668 | } | |
7669 | ||
bb8c093b | 7670 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
7671 | &dev_attr_antenna.attr, |
7672 | &dev_attr_channels.attr, | |
7673 | &dev_attr_dump_errors.attr, | |
7674 | &dev_attr_dump_events.attr, | |
7675 | &dev_attr_flags.attr, | |
7676 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7677 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7678 | &dev_attr_measurement.attr, |
7679 | #endif | |
7680 | &dev_attr_power_level.attr, | |
b481de9c | 7681 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
7682 | &dev_attr_statistics.attr, |
7683 | &dev_attr_status.attr, | |
7684 | &dev_attr_temperature.attr, | |
b481de9c | 7685 | &dev_attr_tx_power.attr, |
40b8ec0b SO |
7686 | #ifdef CONFIG_IWL3945_DEBUG |
7687 | &dev_attr_debug_level.attr, | |
7688 | #endif | |
b481de9c ZY |
7689 | NULL |
7690 | }; | |
7691 | ||
bb8c093b | 7692 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 7693 | .name = NULL, /* put in device directory */ |
bb8c093b | 7694 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
7695 | }; |
7696 | ||
bb8c093b CH |
7697 | static struct ieee80211_ops iwl3945_hw_ops = { |
7698 | .tx = iwl3945_mac_tx, | |
7699 | .start = iwl3945_mac_start, | |
7700 | .stop = iwl3945_mac_stop, | |
7701 | .add_interface = iwl3945_mac_add_interface, | |
7702 | .remove_interface = iwl3945_mac_remove_interface, | |
7703 | .config = iwl3945_mac_config, | |
7704 | .config_interface = iwl3945_mac_config_interface, | |
7705 | .configure_filter = iwl3945_configure_filter, | |
7706 | .set_key = iwl3945_mac_set_key, | |
bb8c093b CH |
7707 | .get_tx_stats = iwl3945_mac_get_tx_stats, |
7708 | .conf_tx = iwl3945_mac_conf_tx, | |
bb8c093b | 7709 | .reset_tsf = iwl3945_mac_reset_tsf, |
cd56d331 | 7710 | .bss_info_changed = iwl3945_bss_info_changed, |
bb8c093b | 7711 | .hw_scan = iwl3945_mac_hw_scan |
b481de9c ZY |
7712 | }; |
7713 | ||
bb8c093b | 7714 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7715 | { |
7716 | int err = 0; | |
4a8a4322 | 7717 | struct iwl_priv *priv; |
b481de9c | 7718 | struct ieee80211_hw *hw; |
c0f20d91 | 7719 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 7720 | unsigned long flags; |
b481de9c | 7721 | |
cee53ddb KA |
7722 | /*********************** |
7723 | * 1. Allocating HW data | |
7724 | * ********************/ | |
7725 | ||
b481de9c ZY |
7726 | /* mac80211 allocates memory for this device instance, including |
7727 | * space for this driver's private structure */ | |
4a8a4322 | 7728 | hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwl3945_hw_ops); |
b481de9c | 7729 | if (hw == NULL) { |
a3139c59 | 7730 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
7731 | err = -ENOMEM; |
7732 | goto out; | |
7733 | } | |
b481de9c | 7734 | |
cee53ddb | 7735 | SET_IEEE80211_DEV(hw, &pdev->dev); |
f51359a8 | 7736 | |
b481de9c ZY |
7737 | priv = hw->priv; |
7738 | priv->hw = hw; | |
b481de9c | 7739 | priv->pci_dev = pdev; |
82b9a121 | 7740 | priv->cfg = cfg; |
6440adb5 | 7741 | |
a3139c59 SO |
7742 | if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) || |
7743 | (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) { | |
7744 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", | |
7745 | IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES); | |
7746 | err = -EINVAL; | |
7747 | goto out; | |
7748 | } | |
7749 | ||
40b8ec0b SO |
7750 | /* Disabling hardware scan means that mac80211 will perform scans |
7751 | * "the hard way", rather than using device's scan. */ | |
7752 | if (iwl3945_param_disable_hw_scan) { | |
7753 | IWL_DEBUG_INFO("Disabling hw_scan\n"); | |
7754 | iwl3945_hw_ops.hw_scan = NULL; | |
7755 | } | |
7756 | ||
cee53ddb KA |
7757 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); |
7758 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
7759 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
7760 | ||
6440adb5 | 7761 | /* Select antenna (may be helpful if only one antenna is connected) */ |
bb8c093b | 7762 | priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna; |
c8b0e6e1 | 7763 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 7764 | priv->debug_level = iwl3945_param_debug; |
b481de9c ZY |
7765 | atomic_set(&priv->restrict_refcnt, 0); |
7766 | #endif | |
b481de9c | 7767 | |
566bfe5a | 7768 | /* Tell mac80211 our characteristics */ |
605a0bd6 | 7769 | hw->flags = IEEE80211_HW_SIGNAL_DBM | |
566bfe5a | 7770 | IEEE80211_HW_NOISE_DBM; |
b481de9c | 7771 | |
f59ac048 | 7772 | hw->wiphy->interface_modes = |
f59ac048 LR |
7773 | BIT(NL80211_IFTYPE_STATION) | |
7774 | BIT(NL80211_IFTYPE_ADHOC); | |
7775 | ||
ea4a82dc LR |
7776 | hw->wiphy->fw_handles_regulatory = true; |
7777 | ||
6440adb5 | 7778 | /* 4 EDCA QOS priorities */ |
b481de9c ZY |
7779 | hw->queues = 4; |
7780 | ||
cee53ddb KA |
7781 | /*************************** |
7782 | * 2. Initializing PCI bus | |
7783 | * *************************/ | |
b481de9c ZY |
7784 | if (pci_enable_device(pdev)) { |
7785 | err = -ENODEV; | |
7786 | goto out_ieee80211_free_hw; | |
7787 | } | |
7788 | ||
7789 | pci_set_master(pdev); | |
7790 | ||
b481de9c ZY |
7791 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
7792 | if (!err) | |
7793 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
7794 | if (err) { | |
7795 | printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n"); | |
7796 | goto out_pci_disable_device; | |
7797 | } | |
7798 | ||
7799 | pci_set_drvdata(pdev, priv); | |
7800 | err = pci_request_regions(pdev, DRV_NAME); | |
7801 | if (err) | |
7802 | goto out_pci_disable_device; | |
6440adb5 | 7803 | |
cee53ddb KA |
7804 | /*********************** |
7805 | * 3. Read REV Register | |
7806 | * ********************/ | |
b481de9c ZY |
7807 | priv->hw_base = pci_iomap(pdev, 0, 0); |
7808 | if (!priv->hw_base) { | |
7809 | err = -ENODEV; | |
7810 | goto out_pci_release_regions; | |
7811 | } | |
7812 | ||
7813 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
7814 | (unsigned long long) pci_resource_len(pdev, 0)); | |
7815 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
7816 | ||
cee53ddb KA |
7817 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
7818 | * PCI Tx retries from interfering with C3 CPU state */ | |
7819 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 7820 | |
cee53ddb | 7821 | /* nic init */ |
5d49f498 | 7822 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
cee53ddb | 7823 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
b481de9c | 7824 | |
5d49f498 AK |
7825 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
7826 | err = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, | |
73d7b5ac | 7827 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
cee53ddb KA |
7828 | if (err < 0) { |
7829 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
7830 | goto out_remove_sysfs; | |
7831 | } | |
b481de9c | 7832 | |
cee53ddb KA |
7833 | /*********************** |
7834 | * 4. Read EEPROM | |
7835 | * ********************/ | |
7836 | /* Read the EEPROM */ | |
7837 | err = iwl3945_eeprom_init(priv); | |
7838 | if (err) { | |
7839 | IWL_ERROR("Unable to init EEPROM\n"); | |
7840 | goto out_remove_sysfs; | |
7841 | } | |
7842 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
7843 | get_eeprom_mac(priv, priv->mac_addr); | |
7844 | IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr); | |
7845 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
b481de9c | 7846 | |
cee53ddb KA |
7847 | /*********************** |
7848 | * 5. Setup HW Constants | |
7849 | * ********************/ | |
b481de9c | 7850 | /* Device-specific setup */ |
3832ec9d | 7851 | if (iwl3945_hw_set_hw_params(priv)) { |
b481de9c | 7852 | IWL_ERROR("failed to set hw settings\n"); |
b481de9c ZY |
7853 | goto out_iounmap; |
7854 | } | |
7855 | ||
cee53ddb KA |
7856 | /*********************** |
7857 | * 6. Setup priv | |
7858 | * ********************/ | |
7859 | priv->retry_rate = 1; | |
7860 | priv->ibss_beacon = NULL; | |
7861 | ||
7862 | spin_lock_init(&priv->lock); | |
f2c7e521 | 7863 | spin_lock_init(&priv->power_data_39.lock); |
cee53ddb KA |
7864 | spin_lock_init(&priv->sta_lock); |
7865 | spin_lock_init(&priv->hcmd_lock); | |
7866 | ||
7867 | INIT_LIST_HEAD(&priv->free_frames); | |
7868 | mutex_init(&priv->mutex); | |
7869 | ||
7870 | /* Clear the driver's (not device's) station table */ | |
7871 | iwl3945_clear_stations_table(priv); | |
7872 | ||
7873 | priv->data_retry_limit = -1; | |
7874 | priv->ieee_channels = NULL; | |
7875 | priv->ieee_rates = NULL; | |
7876 | priv->band = IEEE80211_BAND_2GHZ; | |
7877 | ||
7878 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
7879 | ||
bb8c093b | 7880 | iwl3945_reset_qos(priv); |
b481de9c ZY |
7881 | |
7882 | priv->qos_data.qos_active = 0; | |
7883 | priv->qos_data.qos_cap.val = 0; | |
b481de9c | 7884 | |
b481de9c ZY |
7885 | |
7886 | priv->rates_mask = IWL_RATES_MASK; | |
7887 | /* If power management is turned on, default to AC mode */ | |
1125eff3 | 7888 | priv->power_mode = IWL39_POWER_AC; |
b481de9c ZY |
7889 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; |
7890 | ||
cee53ddb | 7891 | err = iwl3945_init_channel_map(priv); |
b481de9c | 7892 | if (err) { |
cee53ddb | 7893 | IWL_ERROR("initializing regulatory failed: %d\n", err); |
b481de9c ZY |
7894 | goto out_release_irq; |
7895 | } | |
7896 | ||
cee53ddb | 7897 | err = iwl3945_init_geos(priv); |
b481de9c | 7898 | if (err) { |
cee53ddb KA |
7899 | IWL_ERROR("initializing geos failed: %d\n", err); |
7900 | goto out_free_channel_map; | |
b481de9c ZY |
7901 | } |
7902 | ||
cee53ddb KA |
7903 | printk(KERN_INFO DRV_NAME |
7904 | ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); | |
7905 | ||
7906 | /*********************************** | |
7907 | * 7. Initialize Module Parameters | |
7908 | * **********************************/ | |
7909 | ||
7910 | /* Initialize module parameter values here */ | |
7911 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
7912 | if (iwl3945_param_disable) { | |
7913 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
7914 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
849e0dce RC |
7915 | } |
7916 | ||
cee53ddb KA |
7917 | |
7918 | /*********************** | |
7919 | * 8. Setup Services | |
7920 | * ********************/ | |
7921 | ||
7922 | spin_lock_irqsave(&priv->lock, flags); | |
7923 | iwl3945_disable_interrupts(priv); | |
7924 | spin_unlock_irqrestore(&priv->lock, flags); | |
7925 | ||
7926 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); | |
849e0dce | 7927 | if (err) { |
cee53ddb KA |
7928 | IWL_ERROR("failed to create sysfs device attributes\n"); |
7929 | goto out_free_geos; | |
849e0dce | 7930 | } |
849e0dce | 7931 | |
cee53ddb KA |
7932 | iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); |
7933 | iwl3945_setup_deferred_work(priv); | |
7934 | iwl3945_setup_rx_handlers(priv); | |
7935 | ||
7936 | /*********************** | |
7937 | * 9. Conclude | |
7938 | * ********************/ | |
7939 | pci_save_state(pdev); | |
7940 | pci_disable_device(pdev); | |
7941 | ||
7942 | /********************************* | |
7943 | * 10. Setup and Register mac80211 | |
7944 | * *******************************/ | |
7945 | ||
5a66926a ZY |
7946 | err = ieee80211_register_hw(priv->hw); |
7947 | if (err) { | |
7948 | IWL_ERROR("Failed to register network device (error %d)\n", err); | |
cee53ddb | 7949 | goto out_remove_sysfs; |
5a66926a | 7950 | } |
b481de9c | 7951 | |
5a66926a ZY |
7952 | priv->hw->conf.beacon_int = 100; |
7953 | priv->mac80211_registered = 1; | |
cee53ddb | 7954 | |
b481de9c | 7955 | |
ebef2008 AK |
7956 | err = iwl3945_rfkill_init(priv); |
7957 | if (err) | |
7958 | IWL_ERROR("Unable to initialize RFKILL system. " | |
7959 | "Ignoring error: %d\n", err); | |
7960 | ||
b481de9c ZY |
7961 | return 0; |
7962 | ||
cee53ddb KA |
7963 | out_remove_sysfs: |
7964 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); | |
849e0dce RC |
7965 | out_free_geos: |
7966 | iwl3945_free_geos(priv); | |
7967 | out_free_channel_map: | |
7968 | iwl3945_free_channel_map(priv); | |
cee53ddb | 7969 | |
b481de9c ZY |
7970 | |
7971 | out_release_irq: | |
b481de9c ZY |
7972 | destroy_workqueue(priv->workqueue); |
7973 | priv->workqueue = NULL; | |
3832ec9d | 7974 | iwl3945_unset_hw_params(priv); |
b481de9c ZY |
7975 | |
7976 | out_iounmap: | |
7977 | pci_iounmap(pdev, priv->hw_base); | |
7978 | out_pci_release_regions: | |
7979 | pci_release_regions(pdev); | |
7980 | out_pci_disable_device: | |
7981 | pci_disable_device(pdev); | |
7982 | pci_set_drvdata(pdev, NULL); | |
7983 | out_ieee80211_free_hw: | |
7984 | ieee80211_free_hw(priv->hw); | |
7985 | out: | |
7986 | return err; | |
7987 | } | |
7988 | ||
c83dbf68 | 7989 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 7990 | { |
4a8a4322 | 7991 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 7992 | unsigned long flags; |
b481de9c ZY |
7993 | |
7994 | if (!priv) | |
7995 | return; | |
7996 | ||
7997 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
7998 | ||
b481de9c | 7999 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 8000 | |
bb8c093b | 8001 | iwl3945_down(priv); |
b481de9c | 8002 | |
0359facc MA |
8003 | /* make sure we flush any pending irq or |
8004 | * tasklet for the driver | |
8005 | */ | |
8006 | spin_lock_irqsave(&priv->lock, flags); | |
8007 | iwl3945_disable_interrupts(priv); | |
8008 | spin_unlock_irqrestore(&priv->lock, flags); | |
8009 | ||
8010 | iwl_synchronize_irq(priv); | |
8011 | ||
bb8c093b | 8012 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 8013 | |
ebef2008 | 8014 | iwl3945_rfkill_unregister(priv); |
bb8c093b | 8015 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
8016 | |
8017 | if (priv->rxq.bd) | |
bb8c093b CH |
8018 | iwl3945_rx_queue_free(priv, &priv->rxq); |
8019 | iwl3945_hw_txq_ctx_free(priv); | |
b481de9c | 8020 | |
3832ec9d | 8021 | iwl3945_unset_hw_params(priv); |
bb8c093b | 8022 | iwl3945_clear_stations_table(priv); |
b481de9c | 8023 | |
3ac7f146 | 8024 | if (priv->mac80211_registered) |
b481de9c | 8025 | ieee80211_unregister_hw(priv->hw); |
b481de9c | 8026 | |
6ef89d0a MA |
8027 | /*netif_stop_queue(dev); */ |
8028 | flush_workqueue(priv->workqueue); | |
8029 | ||
bb8c093b | 8030 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
8031 | * priv->workqueue... so we can't take down the workqueue |
8032 | * until now... */ | |
8033 | destroy_workqueue(priv->workqueue); | |
8034 | priv->workqueue = NULL; | |
8035 | ||
b481de9c ZY |
8036 | pci_iounmap(pdev, priv->hw_base); |
8037 | pci_release_regions(pdev); | |
8038 | pci_disable_device(pdev); | |
8039 | pci_set_drvdata(pdev, NULL); | |
8040 | ||
849e0dce RC |
8041 | iwl3945_free_channel_map(priv); |
8042 | iwl3945_free_geos(priv); | |
f2c7e521 | 8043 | kfree(priv->scan39); |
b481de9c ZY |
8044 | if (priv->ibss_beacon) |
8045 | dev_kfree_skb(priv->ibss_beacon); | |
8046 | ||
8047 | ieee80211_free_hw(priv->hw); | |
8048 | } | |
8049 | ||
8050 | #ifdef CONFIG_PM | |
8051 | ||
bb8c093b | 8052 | static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 8053 | { |
4a8a4322 | 8054 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8055 | |
e655b9f0 ZY |
8056 | if (priv->is_open) { |
8057 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
8058 | iwl3945_mac_stop(priv->hw); | |
8059 | priv->is_open = 1; | |
8060 | } | |
b481de9c | 8061 | |
b481de9c ZY |
8062 | pci_set_power_state(pdev, PCI_D3hot); |
8063 | ||
b481de9c ZY |
8064 | return 0; |
8065 | } | |
8066 | ||
bb8c093b | 8067 | static int iwl3945_pci_resume(struct pci_dev *pdev) |
b481de9c | 8068 | { |
4a8a4322 | 8069 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8070 | |
b481de9c | 8071 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8072 | |
e655b9f0 ZY |
8073 | if (priv->is_open) |
8074 | iwl3945_mac_start(priv->hw); | |
b481de9c | 8075 | |
e655b9f0 | 8076 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8077 | return 0; |
8078 | } | |
8079 | ||
8080 | #endif /* CONFIG_PM */ | |
8081 | ||
ebef2008 | 8082 | /*************** RFKILL FUNCTIONS **********/ |
80fcc9e2 | 8083 | #ifdef CONFIG_IWL3945_RFKILL |
ebef2008 AK |
8084 | /* software rf-kill from user */ |
8085 | static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state) | |
8086 | { | |
4a8a4322 | 8087 | struct iwl_priv *priv = data; |
ebef2008 AK |
8088 | int err = 0; |
8089 | ||
80fcc9e2 | 8090 | if (!priv->rfkill) |
ebef2008 AK |
8091 | return 0; |
8092 | ||
8093 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
8094 | return 0; | |
8095 | ||
a96a27f9 | 8096 | IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state); |
ebef2008 AK |
8097 | mutex_lock(&priv->mutex); |
8098 | ||
8099 | switch (state) { | |
acdfe9b4 | 8100 | case RFKILL_STATE_UNBLOCKED: |
80fcc9e2 | 8101 | if (iwl3945_is_rfkill_hw(priv)) { |
ebef2008 | 8102 | err = -EBUSY; |
80fcc9e2 AG |
8103 | goto out_unlock; |
8104 | } | |
8105 | iwl3945_radio_kill_sw(priv, 0); | |
ebef2008 | 8106 | break; |
acdfe9b4 | 8107 | case RFKILL_STATE_SOFT_BLOCKED: |
ebef2008 | 8108 | iwl3945_radio_kill_sw(priv, 1); |
ebef2008 | 8109 | break; |
acdfe9b4 | 8110 | default: |
a96a27f9 | 8111 | IWL_WARNING("we received unexpected RFKILL state %d\n", state); |
acdfe9b4 | 8112 | break; |
ebef2008 | 8113 | } |
80fcc9e2 | 8114 | out_unlock: |
ebef2008 AK |
8115 | mutex_unlock(&priv->mutex); |
8116 | ||
8117 | return err; | |
8118 | } | |
8119 | ||
4a8a4322 | 8120 | int iwl3945_rfkill_init(struct iwl_priv *priv) |
ebef2008 AK |
8121 | { |
8122 | struct device *device = wiphy_dev(priv->hw->wiphy); | |
8123 | int ret = 0; | |
8124 | ||
8125 | BUG_ON(device == NULL); | |
8126 | ||
8127 | IWL_DEBUG_RF_KILL("Initializing RFKILL.\n"); | |
80fcc9e2 AG |
8128 | priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN); |
8129 | if (!priv->rfkill) { | |
ebef2008 AK |
8130 | IWL_ERROR("Unable to allocate rfkill device.\n"); |
8131 | ret = -ENOMEM; | |
8132 | goto error; | |
8133 | } | |
8134 | ||
80fcc9e2 AG |
8135 | priv->rfkill->name = priv->cfg->name; |
8136 | priv->rfkill->data = priv; | |
8137 | priv->rfkill->state = RFKILL_STATE_UNBLOCKED; | |
8138 | priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill; | |
8139 | priv->rfkill->user_claim_unsupported = 1; | |
ebef2008 | 8140 | |
80fcc9e2 AG |
8141 | priv->rfkill->dev.class->suspend = NULL; |
8142 | priv->rfkill->dev.class->resume = NULL; | |
ebef2008 | 8143 | |
80fcc9e2 | 8144 | ret = rfkill_register(priv->rfkill); |
ebef2008 AK |
8145 | if (ret) { |
8146 | IWL_ERROR("Unable to register rfkill: %d\n", ret); | |
80fcc9e2 | 8147 | goto freed_rfkill; |
ebef2008 AK |
8148 | } |
8149 | ||
8150 | IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); | |
8151 | return ret; | |
8152 | ||
ebef2008 | 8153 | freed_rfkill: |
80fcc9e2 AG |
8154 | if (priv->rfkill != NULL) |
8155 | rfkill_free(priv->rfkill); | |
8156 | priv->rfkill = NULL; | |
ebef2008 AK |
8157 | |
8158 | error: | |
8159 | IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); | |
8160 | return ret; | |
8161 | } | |
8162 | ||
4a8a4322 | 8163 | void iwl3945_rfkill_unregister(struct iwl_priv *priv) |
ebef2008 | 8164 | { |
80fcc9e2 AG |
8165 | if (priv->rfkill) |
8166 | rfkill_unregister(priv->rfkill); | |
ebef2008 | 8167 | |
80fcc9e2 | 8168 | priv->rfkill = NULL; |
ebef2008 AK |
8169 | } |
8170 | ||
8171 | /* set rf-kill to the right state. */ | |
4a8a4322 | 8172 | void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv) |
ebef2008 AK |
8173 | { |
8174 | ||
80fcc9e2 AG |
8175 | if (!priv->rfkill) |
8176 | return; | |
8177 | ||
8178 | if (iwl3945_is_rfkill_hw(priv)) { | |
8179 | rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED); | |
ebef2008 | 8180 | return; |
80fcc9e2 | 8181 | } |
ebef2008 | 8182 | |
80fcc9e2 AG |
8183 | if (!iwl3945_is_rfkill_sw(priv)) |
8184 | rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED); | |
ebef2008 | 8185 | else |
80fcc9e2 | 8186 | rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED); |
ebef2008 AK |
8187 | } |
8188 | #endif | |
8189 | ||
b481de9c ZY |
8190 | /***************************************************************************** |
8191 | * | |
8192 | * driver and module entry point | |
8193 | * | |
8194 | *****************************************************************************/ | |
8195 | ||
bb8c093b | 8196 | static struct pci_driver iwl3945_driver = { |
b481de9c | 8197 | .name = DRV_NAME, |
bb8c093b CH |
8198 | .id_table = iwl3945_hw_card_ids, |
8199 | .probe = iwl3945_pci_probe, | |
8200 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 8201 | #ifdef CONFIG_PM |
bb8c093b CH |
8202 | .suspend = iwl3945_pci_suspend, |
8203 | .resume = iwl3945_pci_resume, | |
b481de9c ZY |
8204 | #endif |
8205 | }; | |
8206 | ||
bb8c093b | 8207 | static int __init iwl3945_init(void) |
b481de9c ZY |
8208 | { |
8209 | ||
8210 | int ret; | |
8211 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8212 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
8213 | |
8214 | ret = iwl3945_rate_control_register(); | |
8215 | if (ret) { | |
a3139c59 SO |
8216 | printk(KERN_ERR DRV_NAME |
8217 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
8218 | return ret; |
8219 | } | |
8220 | ||
bb8c093b | 8221 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 8222 | if (ret) { |
a3139c59 | 8223 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 8224 | goto error_register; |
b481de9c | 8225 | } |
b481de9c ZY |
8226 | |
8227 | return ret; | |
897e1cf2 | 8228 | |
897e1cf2 RC |
8229 | error_register: |
8230 | iwl3945_rate_control_unregister(); | |
8231 | return ret; | |
b481de9c ZY |
8232 | } |
8233 | ||
bb8c093b | 8234 | static void __exit iwl3945_exit(void) |
b481de9c | 8235 | { |
bb8c093b | 8236 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 8237 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
8238 | } |
8239 | ||
a0987a8d | 8240 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 8241 | |
bb8c093b | 8242 | module_param_named(antenna, iwl3945_param_antenna, int, 0444); |
b481de9c | 8243 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
bb8c093b | 8244 | module_param_named(disable, iwl3945_param_disable, int, 0444); |
b481de9c | 8245 | MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])"); |
bb8c093b | 8246 | module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444); |
b481de9c ZY |
8247 | MODULE_PARM_DESC(hwcrypto, |
8248 | "using hardware crypto engine (default 0 [software])\n"); | |
95aa194a | 8249 | module_param_named(debug, iwl3945_param_debug, uint, 0444); |
b481de9c | 8250 | MODULE_PARM_DESC(debug, "debug output mask"); |
bb8c093b | 8251 | module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444); |
b481de9c ZY |
8252 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
8253 | ||
bb8c093b | 8254 | module_param_named(queues_num, iwl3945_param_queues_num, int, 0444); |
b481de9c ZY |
8255 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
8256 | ||
bb8c093b CH |
8257 | module_exit(iwl3945_exit); |
8258 | module_init(iwl3945_init); |