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iwlwifi: removing unused priv->config
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
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30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
b481de9c
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49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
c8b0e6e1 52#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 53u32 iwl3945_debug_level;
b481de9c
ZY
54#endif
55
bb8c093b
CH
56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
416e1438 58
b481de9c
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59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65/* module parameters */
6440adb5
BC
66static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
67static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
68static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 69static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
BC
70int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
71static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
72int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
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73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
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83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
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89#define VS "s"
90#else
91#define VS
92#endif
93
b9e0b449 94#define IWLWIFI_VERSION "1.2.26k" VD VS
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95#define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
96#define DRV_VERSION IWLWIFI_VERSION
97
98/* Change firmware file name, using "-" and incrementing number,
99 * *only* when uCode interface or architecture changes so that it
100 * is not compatible with earlier drivers.
101 * This number will also appear in << 8 position of 1st dword of uCode file */
102#define IWL3945_UCODE_API "-1"
103
104MODULE_DESCRIPTION(DRV_DESCRIPTION);
105MODULE_VERSION(DRV_VERSION);
106MODULE_AUTHOR(DRV_COPYRIGHT);
107MODULE_LICENSE("GPL");
108
416e1438 109static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
b481de9c
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110{
111 u16 fc = le16_to_cpu(hdr->frame_control);
112 int hdr_len = ieee80211_get_hdrlen(fc);
113
114 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
115 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
116 return NULL;
117}
118
8318d78a
JB
119static const struct ieee80211_supported_band *iwl3945_get_band(
120 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 121{
8318d78a 122 return priv->hw->wiphy->bands[band];
b481de9c
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123}
124
bb8c093b 125static int iwl3945_is_empty_essid(const char *essid, int essid_len)
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126{
127 /* Single white space is for Linksys APs */
128 if (essid_len == 1 && essid[0] == ' ')
129 return 1;
130
131 /* Otherwise, if the entire essid is 0, we assume it is hidden */
132 while (essid_len) {
133 essid_len--;
134 if (essid[essid_len] != '\0')
135 return 0;
136 }
137
138 return 1;
139}
140
bb8c093b 141static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
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142{
143 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
144 const char *s = essid;
145 char *d = escaped;
146
bb8c093b 147 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
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148 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
149 return escaped;
150 }
151
152 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
153 while (essid_len--) {
154 if (*s == '\0') {
155 *d++ = '\\';
156 *d++ = '0';
157 s++;
158 } else
159 *d++ = *s++;
160 }
161 *d = '\0';
162 return escaped;
163}
164
bb8c093b 165static void iwl3945_print_hex_dump(int level, void *p, u32 len)
b481de9c 166{
c8b0e6e1 167#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 168 if (!(iwl3945_debug_level & level))
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169 return;
170
171 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
172 p, len, 1);
173#endif
174}
175
176/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
177 * DMA services
178 *
179 * Theory of operation
180 *
6440adb5
BC
181 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
182 * of buffer descriptors, each of which points to one or more data buffers for
183 * the device to read from or fill. Driver and device exchange status of each
184 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
185 * entries in each circular buffer, to protect against confusing empty and full
186 * queue states.
187 *
188 * The device reads or writes the data in the queues via the device's several
189 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
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190 *
191 * For Tx queue, there are low mark and high mark limits. If, after queuing
192 * the packet for Tx, free space become < low mark, Tx queue stopped. When
193 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
194 * Tx queue resumed.
195 *
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196 * The 3945 operates with six queues: One receive queue, one transmit queue
197 * (#4) for sending commands to the device firmware, and four transmit queues
198 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
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199 ***************************************************/
200
bb8c093b 201static int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 202{
fc4b6853 203 int s = q->read_ptr - q->write_ptr;
b481de9c 204
fc4b6853 205 if (q->read_ptr > q->write_ptr)
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206 s -= q->n_bd;
207
208 if (s <= 0)
209 s += q->n_window;
210 /* keep some reserve to not confuse empty and full situations */
211 s -= 2;
212 if (s < 0)
213 s = 0;
214 return s;
215}
216
6440adb5
BC
217/**
218 * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
219 * @index -- current index
220 * @n_bd -- total number of entries in queue (must be power of 2)
221 */
bb8c093b 222static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
b481de9c
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223{
224 return ++index & (n_bd - 1);
225}
226
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227/**
228 * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
229 * @index -- current index
230 * @n_bd -- total number of entries in queue (must be power of 2)
231 */
bb8c093b 232static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
b481de9c
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233{
234 return --index & (n_bd - 1);
235}
236
bb8c093b 237static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 238{
fc4b6853
TW
239 return q->write_ptr > q->read_ptr ?
240 (i >= q->read_ptr && i < q->write_ptr) :
241 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
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242}
243
bb8c093b 244static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 245{
6440adb5 246 /* This is for scan command, the big buffer at end of command array */
b481de9c 247 if (is_huge)
6440adb5 248 return q->n_window; /* must be power of 2 */
b481de9c 249
6440adb5 250 /* Otherwise, use normal size buffers */
b481de9c
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251 return index & (q->n_window - 1);
252}
253
6440adb5
BC
254/**
255 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
256 */
bb8c093b 257static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
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258 int count, int slots_num, u32 id)
259{
260 q->n_bd = count;
261 q->n_window = slots_num;
262 q->id = id;
263
bb8c093b
CH
264 /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
265 * and iwl3945_queue_dec_wrap are broken. */
b481de9c
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266 BUG_ON(!is_power_of_2(count));
267
268 /* slots_num must be power-of-two size, otherwise
269 * get_cmd_index is broken. */
270 BUG_ON(!is_power_of_2(slots_num));
271
272 q->low_mark = q->n_window / 4;
273 if (q->low_mark < 4)
274 q->low_mark = 4;
275
276 q->high_mark = q->n_window / 8;
277 if (q->high_mark < 2)
278 q->high_mark = 2;
279
fc4b6853 280 q->write_ptr = q->read_ptr = 0;
b481de9c
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281
282 return 0;
283}
284
6440adb5
BC
285/**
286 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
287 */
bb8c093b
CH
288static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
289 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
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290{
291 struct pci_dev *dev = priv->pci_dev;
292
6440adb5
BC
293 /* Driver private data, only for Tx (not command) queues,
294 * not shared with device. */
b481de9c
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295 if (id != IWL_CMD_QUEUE_NUM) {
296 txq->txb = kmalloc(sizeof(txq->txb[0]) *
297 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
298 if (!txq->txb) {
01ebd063 299 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
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300 "structures failed\n");
301 goto error;
302 }
303 } else
304 txq->txb = NULL;
305
6440adb5
BC
306 /* Circular buffer of transmit frame descriptors (TFDs),
307 * shared with device */
b481de9c
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308 txq->bd = pci_alloc_consistent(dev,
309 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
310 &txq->q.dma_addr);
311
312 if (!txq->bd) {
313 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
314 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
315 goto error;
316 }
317 txq->q.id = id;
318
319 return 0;
320
321 error:
322 if (txq->txb) {
323 kfree(txq->txb);
324 txq->txb = NULL;
325 }
326
327 return -ENOMEM;
328}
329
6440adb5
BC
330/**
331 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
332 */
bb8c093b
CH
333int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
334 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY
335{
336 struct pci_dev *dev = priv->pci_dev;
337 int len;
338 int rc = 0;
339
6440adb5
BC
340 /*
341 * Alloc buffer array for commands (Tx or other types of commands).
342 * For the command queue (#4), allocate command space + one big
343 * command for scan, since scan command is very huge; the system will
344 * not have two scans at the same time, so only one is needed.
345 * For data Tx queues (all other queues), no super-size command
346 * space is needed.
347 */
bb8c093b 348 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY
349 if (txq_id == IWL_CMD_QUEUE_NUM)
350 len += IWL_MAX_SCAN_SIZE;
351 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
352 if (!txq->cmd)
353 return -ENOMEM;
354
6440adb5 355 /* Alloc driver data array and TFD circular buffer */
bb8c093b 356 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY
357 if (rc) {
358 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
359
360 return -ENOMEM;
361 }
362 txq->need_update = 0;
363
364 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
bb8c093b 365 * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
b481de9c 366 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
BC
367
368 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 369 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 370
6440adb5 371 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 372 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
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373
374 return 0;
375}
376
377/**
bb8c093b 378 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
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379 * @txq: Transmit queue to deallocate.
380 *
381 * Empty queue by removing and destroying all BD's.
6440adb5
BC
382 * Free all buffers.
383 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 384 */
bb8c093b 385void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 386{
bb8c093b 387 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY
388 struct pci_dev *dev = priv->pci_dev;
389 int len;
390
391 if (q->n_bd == 0)
392 return;
393
394 /* first, empty all BD's */
fc4b6853 395 for (; q->write_ptr != q->read_ptr;
bb8c093b
CH
396 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
397 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 398
bb8c093b 399 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY
400 if (q->id == IWL_CMD_QUEUE_NUM)
401 len += IWL_MAX_SCAN_SIZE;
402
6440adb5 403 /* De-alloc array of command/tx buffers */
b481de9c
ZY
404 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
405
6440adb5 406 /* De-alloc circular buffer of TFDs */
b481de9c 407 if (txq->q.n_bd)
bb8c093b 408 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
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409 txq->q.n_bd, txq->bd, txq->q.dma_addr);
410
6440adb5 411 /* De-alloc array of per-TFD driver data */
b481de9c
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412 if (txq->txb) {
413 kfree(txq->txb);
414 txq->txb = NULL;
415 }
416
6440adb5 417 /* 0-fill queue descriptor structure */
b481de9c
ZY
418 memset(txq, 0, sizeof(*txq));
419}
420
bb8c093b 421const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
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422
423/*************** STATION TABLE MANAGEMENT ****
9fbab516 424 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
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425 * the functionality provided here
426 */
427
428/**************************************************************/
01ebd063 429#if 0 /* temporary disable till we add real remove station */
6440adb5
BC
430/**
431 * iwl3945_remove_station - Remove driver's knowledge of station.
432 *
433 * NOTE: This does not remove station from device's station table.
434 */
bb8c093b 435static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY
436{
437 int index = IWL_INVALID_STATION;
438 int i;
439 unsigned long flags;
440
441 spin_lock_irqsave(&priv->sta_lock, flags);
442
443 if (is_ap)
444 index = IWL_AP_ID;
445 else if (is_broadcast_ether_addr(addr))
446 index = priv->hw_setting.bcast_sta_id;
447 else
448 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
449 if (priv->stations[i].used &&
450 !compare_ether_addr(priv->stations[i].sta.sta.addr,
451 addr)) {
452 index = i;
453 break;
454 }
455
456 if (unlikely(index == IWL_INVALID_STATION))
457 goto out;
458
459 if (priv->stations[index].used) {
460 priv->stations[index].used = 0;
461 priv->num_stations--;
462 }
463
464 BUG_ON(priv->num_stations < 0);
465
466out:
467 spin_unlock_irqrestore(&priv->sta_lock, flags);
468 return 0;
469}
556f8db7 470#endif
6440adb5
BC
471
472/**
473 * iwl3945_clear_stations_table - Clear the driver's station table
474 *
475 * NOTE: This does not clear or otherwise alter the device's station table.
476 */
bb8c093b 477static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY
478{
479 unsigned long flags;
480
481 spin_lock_irqsave(&priv->sta_lock, flags);
482
483 priv->num_stations = 0;
484 memset(priv->stations, 0, sizeof(priv->stations));
485
486 spin_unlock_irqrestore(&priv->sta_lock, flags);
487}
488
6440adb5
BC
489/**
490 * iwl3945_add_station - Add station to station tables in driver and device
491 */
bb8c093b 492u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY
493{
494 int i;
495 int index = IWL_INVALID_STATION;
bb8c093b 496 struct iwl3945_station_entry *station;
b481de9c 497 unsigned long flags_spin;
0795af57 498 DECLARE_MAC_BUF(mac);
c14c521e 499 u8 rate;
b481de9c
ZY
500
501 spin_lock_irqsave(&priv->sta_lock, flags_spin);
502 if (is_ap)
503 index = IWL_AP_ID;
504 else if (is_broadcast_ether_addr(addr))
505 index = priv->hw_setting.bcast_sta_id;
506 else
507 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
508 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
509 addr)) {
510 index = i;
511 break;
512 }
513
514 if (!priv->stations[i].used &&
515 index == IWL_INVALID_STATION)
516 index = i;
517 }
518
01ebd063 519 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY
520 since they have different meaning */
521 if (unlikely(index == IWL_INVALID_STATION)) {
522 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
523 return index;
524 }
525
526 if (priv->stations[index].used &&
527 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
528 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
529 return index;
530 }
531
0795af57 532 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY
533 station = &priv->stations[index];
534 station->used = 1;
535 priv->num_stations++;
536
6440adb5 537 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 538 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY
539 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
540 station->sta.mode = 0;
541 station->sta.sta.sta_id = index;
542 station->sta.station_flags = 0;
543
8318d78a 544 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW
545 rate = IWL_RATE_6M_PLCP;
546 else
547 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY
548
549 /* Turn on both antennas for the station... */
550 station->sta.rate_n_flags =
bb8c093b 551 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY
552 station->current_rate.rate_n_flags =
553 le16_to_cpu(station->sta.rate_n_flags);
554
b481de9c 555 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
BC
556
557 /* Add station to device's station table */
bb8c093b 558 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY
559 return index;
560
561}
562
563/*************** DRIVER STATUS FUNCTIONS *****/
564
bb8c093b 565static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY
566{
567 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
568 * set but EXIT_PENDING is not */
569 return test_bit(STATUS_READY, &priv->status) &&
570 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
571 !test_bit(STATUS_EXIT_PENDING, &priv->status);
572}
573
bb8c093b 574static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY
575{
576 return test_bit(STATUS_ALIVE, &priv->status);
577}
578
bb8c093b 579static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY
580{
581 return test_bit(STATUS_INIT, &priv->status);
582}
583
bb8c093b 584static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY
585{
586 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
587 test_bit(STATUS_RF_KILL_SW, &priv->status);
588}
589
bb8c093b 590static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY
591{
592
bb8c093b 593 if (iwl3945_is_rfkill(priv))
b481de9c
ZY
594 return 0;
595
bb8c093b 596 return iwl3945_is_ready(priv);
b481de9c
ZY
597}
598
599/*************** HOST COMMAND QUEUE FUNCTIONS *****/
600
601#define IWL_CMD(x) case x : return #x
602
603static const char *get_cmd_string(u8 cmd)
604{
605 switch (cmd) {
606 IWL_CMD(REPLY_ALIVE);
607 IWL_CMD(REPLY_ERROR);
608 IWL_CMD(REPLY_RXON);
609 IWL_CMD(REPLY_RXON_ASSOC);
610 IWL_CMD(REPLY_QOS_PARAM);
611 IWL_CMD(REPLY_RXON_TIMING);
612 IWL_CMD(REPLY_ADD_STA);
613 IWL_CMD(REPLY_REMOVE_STA);
614 IWL_CMD(REPLY_REMOVE_ALL_STA);
615 IWL_CMD(REPLY_3945_RX);
616 IWL_CMD(REPLY_TX);
617 IWL_CMD(REPLY_RATE_SCALE);
618 IWL_CMD(REPLY_LEDS_CMD);
619 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
620 IWL_CMD(RADAR_NOTIFICATION);
621 IWL_CMD(REPLY_QUIET_CMD);
622 IWL_CMD(REPLY_CHANNEL_SWITCH);
623 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
624 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
625 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
626 IWL_CMD(POWER_TABLE_CMD);
627 IWL_CMD(PM_SLEEP_NOTIFICATION);
628 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
629 IWL_CMD(REPLY_SCAN_CMD);
630 IWL_CMD(REPLY_SCAN_ABORT_CMD);
631 IWL_CMD(SCAN_START_NOTIFICATION);
632 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
633 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
634 IWL_CMD(BEACON_NOTIFICATION);
635 IWL_CMD(REPLY_TX_BEACON);
636 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
637 IWL_CMD(QUIET_NOTIFICATION);
638 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
639 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
640 IWL_CMD(REPLY_BT_CONFIG);
641 IWL_CMD(REPLY_STATISTICS_CMD);
642 IWL_CMD(STATISTICS_NOTIFICATION);
643 IWL_CMD(REPLY_CARD_STATE_CMD);
644 IWL_CMD(CARD_STATE_NOTIFICATION);
645 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
646 default:
647 return "UNKNOWN";
648
649 }
650}
651
652#define HOST_COMPLETE_TIMEOUT (HZ / 2)
653
654/**
bb8c093b 655 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY
656 * @priv: device private data point
657 * @cmd: a point to the ucode command structure
658 *
659 * The function returns < 0 values to indicate the operation is
660 * failed. On success, it turns the index (> 0) of command in the
661 * command queue.
662 */
bb8c093b 663static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 664{
bb8c093b
CH
665 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
666 struct iwl3945_queue *q = &txq->q;
667 struct iwl3945_tfd_frame *tfd;
b481de9c 668 u32 *control_flags;
bb8c093b 669 struct iwl3945_cmd *out_cmd;
b481de9c
ZY
670 u32 idx;
671 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
672 dma_addr_t phys_addr;
673 int pad;
674 u16 count;
675 int ret;
676 unsigned long flags;
677
678 /* If any of the command structures end up being larger than
679 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
680 * we will need to increase the size of the TFD entries */
681 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
682 !(cmd->meta.flags & CMD_SIZE_HUGE));
683
c342a1b9
GG
684
685 if (iwl3945_is_rfkill(priv)) {
686 IWL_DEBUG_INFO("Not sending command - RF KILL");
687 return -EIO;
688 }
689
bb8c093b 690 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY
691 IWL_ERROR("No space for Tx\n");
692 return -ENOSPC;
693 }
694
695 spin_lock_irqsave(&priv->hcmd_lock, flags);
696
fc4b6853 697 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
698 memset(tfd, 0, sizeof(*tfd));
699
700 control_flags = (u32 *) tfd;
701
fc4b6853 702 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY
703 out_cmd = &txq->cmd[idx];
704
705 out_cmd->hdr.cmd = cmd->id;
706 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
707 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
708
709 /* At this point, the out_cmd now has all of the incoming cmd
710 * information */
711
712 out_cmd->hdr.flags = 0;
713 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 714 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY
715 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
716 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
717
718 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH
719 offsetof(struct iwl3945_cmd, hdr);
720 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY
721
722 pad = U32_PAD(cmd->len);
723 count = TFD_CTL_COUNT_GET(*control_flags);
724 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
725
726 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
727 "%d bytes at %d[%d]:%d\n",
728 get_cmd_string(out_cmd->hdr.cmd),
729 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 730 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY
731
732 txq->need_update = 1;
6440adb5
BC
733
734 /* Increment and update queue's write index */
bb8c093b
CH
735 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
736 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
737
738 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
739 return ret ? ret : idx;
740}
741
bb8c093b 742static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY
743{
744 int ret;
745
746 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
747
748 /* An asynchronous command can not expect an SKB to be set. */
749 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
750
751 /* An asynchronous command MUST have a callback. */
752 BUG_ON(!cmd->meta.u.callback);
753
754 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
755 return -EBUSY;
756
bb8c093b 757 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 758 if (ret < 0) {
bb8c093b 759 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY
760 get_cmd_string(cmd->id), ret);
761 return ret;
762 }
763 return 0;
764}
765
bb8c093b 766static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY
767{
768 int cmd_idx;
769 int ret;
770 static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
771
772 BUG_ON(cmd->meta.flags & CMD_ASYNC);
773
774 /* A synchronous command can not have a callback set. */
775 BUG_ON(cmd->meta.u.callback != NULL);
776
777 if (atomic_xchg(&entry, 1)) {
778 IWL_ERROR("Error sending %s: Already sending a host command\n",
779 get_cmd_string(cmd->id));
780 return -EBUSY;
781 }
782
783 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
784
785 if (cmd->meta.flags & CMD_WANT_SKB)
786 cmd->meta.source = &cmd->meta;
787
bb8c093b 788 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY
789 if (cmd_idx < 0) {
790 ret = cmd_idx;
bb8c093b 791 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY
792 get_cmd_string(cmd->id), ret);
793 goto out;
794 }
795
796 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
797 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
798 HOST_COMPLETE_TIMEOUT);
799 if (!ret) {
800 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
801 IWL_ERROR("Error sending %s: time out after %dms.\n",
802 get_cmd_string(cmd->id),
803 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
804
805 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
806 ret = -ETIMEDOUT;
807 goto cancel;
808 }
809 }
810
811 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
812 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
813 get_cmd_string(cmd->id));
814 ret = -ECANCELED;
815 goto fail;
816 }
817 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
818 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
819 get_cmd_string(cmd->id));
820 ret = -EIO;
821 goto fail;
822 }
823 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
824 IWL_ERROR("Error: Response NULL in '%s'\n",
825 get_cmd_string(cmd->id));
826 ret = -EIO;
827 goto out;
828 }
829
830 ret = 0;
831 goto out;
832
833cancel:
834 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 835 struct iwl3945_cmd *qcmd;
b481de9c
ZY
836
837 /* Cancel the CMD_WANT_SKB flag for the cmd in the
838 * TX cmd queue. Otherwise in case the cmd comes
839 * in later, it will possibly set an invalid
840 * address (cmd->meta.source). */
841 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
842 qcmd->meta.flags &= ~CMD_WANT_SKB;
843 }
844fail:
845 if (cmd->meta.u.skb) {
846 dev_kfree_skb_any(cmd->meta.u.skb);
847 cmd->meta.u.skb = NULL;
848 }
849out:
850 atomic_set(&entry, 0);
851 return ret;
852}
853
bb8c093b 854int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 855{
b481de9c 856 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 857 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 858
bb8c093b 859 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY
860}
861
bb8c093b 862int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 863{
bb8c093b 864 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
865 .id = id,
866 .len = len,
867 .data = data,
868 };
869
bb8c093b 870 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
871}
872
bb8c093b 873static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 874{
bb8c093b 875 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
876 .id = id,
877 .len = sizeof(val),
878 .data = &val,
879 };
880
bb8c093b 881 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
882}
883
bb8c093b 884int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 885{
bb8c093b 886 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY
887}
888
b481de9c 889/**
bb8c093b 890 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB
891 * @band: 2.4 or 5 GHz band
892 * @channel: Any channel valid for the requested band
b481de9c 893
8318d78a 894 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY
895 *
896 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 897 * in the staging RXON flag structure based on the band
b481de9c 898 */
8318d78a
JB
899static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
900 enum ieee80211_band band,
901 u16 channel)
b481de9c 902{
8318d78a 903 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 904 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 905 channel, band);
b481de9c
ZY
906 return -EINVAL;
907 }
908
909 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 910 (priv->band == band))
b481de9c
ZY
911 return 0;
912
913 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 914 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
915 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
916 else
917 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
918
8318d78a 919 priv->band = band;
b481de9c 920
8318d78a 921 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY
922
923 return 0;
924}
925
926/**
bb8c093b 927 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY
928 *
929 * NOTE: This is really only useful during development and can eventually
930 * be #ifdef'd out once the driver is stable and folks aren't actively
931 * making changes
932 */
bb8c093b 933static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY
934{
935 int error = 0;
936 int counter = 1;
937
938 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
939 error |= le32_to_cpu(rxon->flags &
940 (RXON_FLG_TGJ_NARROW_BAND_MSK |
941 RXON_FLG_RADAR_DETECT_MSK));
942 if (error)
943 IWL_WARNING("check 24G fields %d | %d\n",
944 counter++, error);
945 } else {
946 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
947 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
948 if (error)
949 IWL_WARNING("check 52 fields %d | %d\n",
950 counter++, error);
951 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
952 if (error)
953 IWL_WARNING("check 52 CCK %d | %d\n",
954 counter++, error);
955 }
956 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
957 if (error)
958 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
959
960 /* make sure basic rates 6Mbps and 1Mbps are supported */
961 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
962 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
963 if (error)
964 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
965
966 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
967 if (error)
968 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
969
970 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
971 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
972 if (error)
973 IWL_WARNING("check CCK and short slot %d | %d\n",
974 counter++, error);
975
976 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
977 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
978 if (error)
979 IWL_WARNING("check CCK & auto detect %d | %d\n",
980 counter++, error);
981
982 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
983 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
984 if (error)
985 IWL_WARNING("check TGG and auto detect %d | %d\n",
986 counter++, error);
987
988 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
989 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
990 RXON_FLG_ANT_A_MSK)) == 0);
991 if (error)
992 IWL_WARNING("check antenna %d %d\n", counter++, error);
993
994 if (error)
995 IWL_WARNING("Tuning to channel %d\n",
996 le16_to_cpu(rxon->channel));
997
998 if (error) {
bb8c093b 999 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY
1000 return -1;
1001 }
1002 return 0;
1003}
1004
1005/**
9fbab516 1006 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 1007 * @priv: staging_rxon is compared to active_rxon
b481de9c 1008 *
9fbab516
BC
1009 * If the RXON structure is changing enough to require a new tune,
1010 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
1011 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 1012 */
bb8c093b 1013static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY
1014{
1015
1016 /* These items are only settable from the full RXON command */
1017 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
1018 compare_ether_addr(priv->staging_rxon.bssid_addr,
1019 priv->active_rxon.bssid_addr) ||
1020 compare_ether_addr(priv->staging_rxon.node_addr,
1021 priv->active_rxon.node_addr) ||
1022 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
1023 priv->active_rxon.wlap_bssid_addr) ||
1024 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
1025 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
1026 (priv->staging_rxon.air_propagation !=
1027 priv->active_rxon.air_propagation) ||
1028 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
1029 return 1;
1030
1031 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
1032 * be updated with the RXON_ASSOC command -- however only some
1033 * flag transitions are allowed using RXON_ASSOC */
1034
1035 /* Check if we are not switching bands */
1036 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1037 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1038 return 1;
1039
1040 /* Check if we are switching association toggle */
1041 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1042 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1043 return 1;
1044
1045 return 0;
1046}
1047
bb8c093b 1048static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY
1049{
1050 int rc = 0;
bb8c093b
CH
1051 struct iwl3945_rx_packet *res = NULL;
1052 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1053 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1054 .id = REPLY_RXON_ASSOC,
1055 .len = sizeof(rxon_assoc),
1056 .meta.flags = CMD_WANT_SKB,
1057 .data = &rxon_assoc,
1058 };
bb8c093b
CH
1059 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1060 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY
1061
1062 if ((rxon1->flags == rxon2->flags) &&
1063 (rxon1->filter_flags == rxon2->filter_flags) &&
1064 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1065 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1066 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1067 return 0;
1068 }
1069
1070 rxon_assoc.flags = priv->staging_rxon.flags;
1071 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1072 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1073 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1074 rxon_assoc.reserved = 0;
1075
bb8c093b 1076 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1077 if (rc)
1078 return rc;
1079
bb8c093b 1080 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1081 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1082 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1083 rc = -EIO;
1084 }
1085
1086 priv->alloc_rxb_skb--;
1087 dev_kfree_skb_any(cmd.meta.u.skb);
1088
1089 return rc;
1090}
1091
1092/**
bb8c093b 1093 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1094 *
01ebd063 1095 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY
1096 * the active_rxon structure is updated with the new data. This
1097 * function correctly transitions out of the RXON_ASSOC_MSK state if
1098 * a HW tune is required based on the RXON structure changes.
1099 */
bb8c093b 1100static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY
1101{
1102 /* cast away the const for active_rxon in this function */
bb8c093b 1103 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1104 int rc = 0;
0795af57 1105 DECLARE_MAC_BUF(mac);
b481de9c 1106
bb8c093b 1107 if (!iwl3945_is_alive(priv))
b481de9c
ZY
1108 return -1;
1109
1110 /* always get timestamp with Rx frame */
1111 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1112
1113 /* select antenna */
1114 priv->staging_rxon.flags &=
1115 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1116 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1117
bb8c093b 1118 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY
1119 if (rc) {
1120 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1121 return -EINVAL;
1122 }
1123
1124 /* If we don't need to send a full RXON, we can use
bb8c093b 1125 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1126 * and other flags for the current radio configuration. */
bb8c093b
CH
1127 if (!iwl3945_full_rxon_required(priv)) {
1128 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY
1129 if (rc) {
1130 IWL_ERROR("Error setting RXON_ASSOC "
1131 "configuration (%d).\n", rc);
1132 return rc;
1133 }
1134
1135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1136
1137 return 0;
1138 }
1139
1140 /* If we are currently associated and the new config requires
1141 * an RXON_ASSOC and the new config wants the associated mask enabled,
1142 * we must clear the associated from the active configuration
1143 * before we apply the new config */
bb8c093b 1144 if (iwl3945_is_associated(priv) &&
b481de9c
ZY
1145 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1146 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1147 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1148
bb8c093b
CH
1149 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1150 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY
1151 &priv->active_rxon);
1152
1153 /* If the mask clearing failed then we set
1154 * active_rxon back to what it was previously */
1155 if (rc) {
1156 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1157 IWL_ERROR("Error clearing ASSOC_MSK on current "
1158 "configuration (%d).\n", rc);
1159 return rc;
1160 }
b481de9c
ZY
1161 }
1162
1163 IWL_DEBUG_INFO("Sending RXON\n"
1164 "* with%s RXON_FILTER_ASSOC_MSK\n"
1165 "* channel = %d\n"
0795af57 1166 "* bssid = %s\n",
b481de9c
ZY
1167 ((priv->staging_rxon.filter_flags &
1168 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1169 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1170 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY
1171
1172 /* Apply the new configuration */
bb8c093b
CH
1173 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1174 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY
1175 if (rc) {
1176 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1177 return rc;
1178 }
1179
1180 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1181
bb8c093b 1182 iwl3945_clear_stations_table(priv);
556f8db7 1183
b481de9c
ZY
1184 /* If we issue a new RXON command which required a tune then we must
1185 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1186 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
1187 if (rc) {
1188 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1189 return rc;
1190 }
1191
1192 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1193 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY
1194 IWL_INVALID_STATION) {
1195 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1196 return -EIO;
1197 }
1198
1199 /* If we have set the ASSOC_MSK and we are in BSS mode then
1200 * add the IWL_AP_ID to the station rate table */
bb8c093b 1201 if (iwl3945_is_associated(priv) &&
b481de9c 1202 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1203 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY
1204 == IWL_INVALID_STATION) {
1205 IWL_ERROR("Error adding AP address for transmit.\n");
1206 return -EIO;
1207 }
1208
8318d78a 1209 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY
1210 rc = iwl3945_init_hw_rate_table(priv);
1211 if (rc) {
1212 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1213 return -EIO;
1214 }
1215
1216 return 0;
1217}
1218
bb8c093b 1219static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1220{
bb8c093b 1221 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY
1222 .flags = 3,
1223 .lead_time = 0xAA,
1224 .max_kill = 1,
1225 .kill_ack_mask = 0,
1226 .kill_cts_mask = 0,
1227 };
1228
bb8c093b
CH
1229 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1230 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY
1231}
1232
bb8c093b 1233static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY
1234{
1235 int rc = 0;
bb8c093b
CH
1236 struct iwl3945_rx_packet *res;
1237 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1238 .id = REPLY_SCAN_ABORT_CMD,
1239 .meta.flags = CMD_WANT_SKB,
1240 };
1241
1242 /* If there isn't a scan actively going on in the hardware
1243 * then we are in between scan bands and not actually
1244 * actively scanning, so don't send the abort command */
1245 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1246 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1247 return 0;
1248 }
1249
bb8c093b 1250 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1251 if (rc) {
1252 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1253 return rc;
1254 }
1255
bb8c093b 1256 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1257 if (res->u.status != CAN_ABORT_STATUS) {
1258 /* The scan abort will return 1 for success or
1259 * 2 for "failure". A failure condition can be
1260 * due to simply not being in an active scan which
1261 * can occur if we send the scan abort before we
1262 * the microcode has notified us that a scan is
1263 * completed. */
1264 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1265 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1266 clear_bit(STATUS_SCAN_HW, &priv->status);
1267 }
1268
1269 dev_kfree_skb_any(cmd.meta.u.skb);
1270
1271 return rc;
1272}
1273
bb8c093b
CH
1274static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1275 struct iwl3945_cmd *cmd,
b481de9c
ZY
1276 struct sk_buff *skb)
1277{
1278 return 1;
1279}
1280
1281/*
1282 * CARD_STATE_CMD
1283 *
9fbab516 1284 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY
1285 *
1286 * When in the 'enable' state the card operates as normal.
1287 * When in the 'disable' state, the card enters into a low power mode.
1288 * When in the 'halt' state, the card is shut down and must be fully
1289 * restarted to come back on.
1290 */
bb8c093b 1291static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1292{
bb8c093b 1293 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1294 .id = REPLY_CARD_STATE_CMD,
1295 .len = sizeof(u32),
1296 .data = &flags,
1297 .meta.flags = meta_flag,
1298 };
1299
1300 if (meta_flag & CMD_ASYNC)
bb8c093b 1301 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1302
bb8c093b 1303 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1304}
1305
bb8c093b
CH
1306static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1307 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1308{
bb8c093b 1309 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY
1310
1311 if (!skb) {
1312 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1313 return 1;
1314 }
1315
bb8c093b 1316 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY
1317 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1318 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1319 res->hdr.flags);
1320 return 1;
1321 }
1322
1323 switch (res->u.add_sta.status) {
1324 case ADD_STA_SUCCESS_MSK:
1325 break;
1326 default:
1327 break;
1328 }
1329
1330 /* We didn't cache the SKB; let the caller free it */
1331 return 1;
1332}
1333
bb8c093b
CH
1334int iwl3945_send_add_station(struct iwl3945_priv *priv,
1335 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1336{
bb8c093b 1337 struct iwl3945_rx_packet *res = NULL;
b481de9c 1338 int rc = 0;
bb8c093b 1339 struct iwl3945_host_cmd cmd = {
b481de9c 1340 .id = REPLY_ADD_STA,
bb8c093b 1341 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY
1342 .meta.flags = flags,
1343 .data = sta,
1344 };
1345
1346 if (flags & CMD_ASYNC)
bb8c093b 1347 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY
1348 else
1349 cmd.meta.flags |= CMD_WANT_SKB;
1350
bb8c093b 1351 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1352
1353 if (rc || (flags & CMD_ASYNC))
1354 return rc;
1355
bb8c093b 1356 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1357 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1358 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1359 res->hdr.flags);
1360 rc = -EIO;
1361 }
1362
1363 if (rc == 0) {
1364 switch (res->u.add_sta.status) {
1365 case ADD_STA_SUCCESS_MSK:
1366 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1367 break;
1368 default:
1369 rc = -EIO;
1370 IWL_WARNING("REPLY_ADD_STA failed\n");
1371 break;
1372 }
1373 }
1374
1375 priv->alloc_rxb_skb--;
1376 dev_kfree_skb_any(cmd.meta.u.skb);
1377
1378 return rc;
1379}
1380
bb8c093b 1381static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY
1382 struct ieee80211_key_conf *keyconf,
1383 u8 sta_id)
1384{
1385 unsigned long flags;
1386 __le16 key_flags = 0;
1387
1388 switch (keyconf->alg) {
1389 case ALG_CCMP:
1390 key_flags |= STA_KEY_FLG_CCMP;
1391 key_flags |= cpu_to_le16(
1392 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1393 key_flags &= ~STA_KEY_FLG_INVALID;
1394 break;
1395 case ALG_TKIP:
1396 case ALG_WEP:
b481de9c
ZY
1397 default:
1398 return -EINVAL;
1399 }
1400 spin_lock_irqsave(&priv->sta_lock, flags);
1401 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1402 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1403 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1404 keyconf->keylen);
1405
1406 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1407 keyconf->keylen);
1408 priv->stations[sta_id].sta.key.key_flags = key_flags;
1409 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1410 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1411
1412 spin_unlock_irqrestore(&priv->sta_lock, flags);
1413
1414 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1415 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1416 return 0;
1417}
1418
bb8c093b 1419static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY
1420{
1421 unsigned long flags;
1422
1423 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH
1424 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1425 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY
1426 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1427 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1428 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1429 spin_unlock_irqrestore(&priv->sta_lock, flags);
1430
1431 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1432 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1433 return 0;
1434}
1435
bb8c093b 1436static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY
1437{
1438 struct list_head *element;
1439
1440 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1441 priv->frames_count);
1442
1443 while (!list_empty(&priv->free_frames)) {
1444 element = priv->free_frames.next;
1445 list_del(element);
bb8c093b 1446 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY
1447 priv->frames_count--;
1448 }
1449
1450 if (priv->frames_count) {
1451 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1452 priv->frames_count);
1453 priv->frames_count = 0;
1454 }
1455}
1456
bb8c093b 1457static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1458{
bb8c093b 1459 struct iwl3945_frame *frame;
b481de9c
ZY
1460 struct list_head *element;
1461 if (list_empty(&priv->free_frames)) {
1462 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1463 if (!frame) {
1464 IWL_ERROR("Could not allocate frame!\n");
1465 return NULL;
1466 }
1467
1468 priv->frames_count++;
1469 return frame;
1470 }
1471
1472 element = priv->free_frames.next;
1473 list_del(element);
bb8c093b 1474 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
1475}
1476
bb8c093b 1477static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY
1478{
1479 memset(frame, 0, sizeof(*frame));
1480 list_add(&frame->list, &priv->free_frames);
1481}
1482
bb8c093b 1483unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY
1484 struct ieee80211_hdr *hdr,
1485 const u8 *dest, int left)
1486{
1487
bb8c093b 1488 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY
1489 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1490 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1491 return 0;
1492
1493 if (priv->ibss_beacon->len > left)
1494 return 0;
1495
1496 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1497
1498 return priv->ibss_beacon->len;
1499}
1500
bb8c093b 1501static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY
1502{
1503 u8 i;
1504
1505 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1506 i = iwl3945_rates[i].next_ieee) {
b481de9c 1507 if (rate_mask & (1 << i))
bb8c093b 1508 return iwl3945_rates[i].plcp;
b481de9c
ZY
1509 }
1510
1511 return IWL_RATE_INVALID;
1512}
1513
bb8c093b 1514static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1515{
bb8c093b 1516 struct iwl3945_frame *frame;
b481de9c
ZY
1517 unsigned int frame_size;
1518 int rc;
1519 u8 rate;
1520
bb8c093b 1521 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
1522
1523 if (!frame) {
1524 IWL_ERROR("Could not obtain free frame buffer for beacon "
1525 "command.\n");
1526 return -ENOMEM;
1527 }
1528
1529 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1530 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY
1531 0xFF0);
1532 if (rate == IWL_INVALID_RATE)
1533 rate = IWL_RATE_6M_PLCP;
1534 } else {
bb8c093b 1535 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY
1536 if (rate == IWL_INVALID_RATE)
1537 rate = IWL_RATE_1M_PLCP;
1538 }
1539
bb8c093b 1540 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1541
bb8c093b 1542 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
1543 &frame->u.cmd[0]);
1544
bb8c093b 1545 iwl3945_free_frame(priv, frame);
b481de9c
ZY
1546
1547 return rc;
1548}
1549
1550/******************************************************************************
1551 *
1552 * EEPROM related functions
1553 *
1554 ******************************************************************************/
1555
bb8c093b 1556static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY
1557{
1558 memcpy(mac, priv->eeprom.mac_address, 6);
1559}
1560
74a3a250
RC
1561/*
1562 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1563 * embedded controller) as EEPROM reader; each read is a series of pulses
1564 * to/from the EEPROM chip, not a single event, so even reads could conflict
1565 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1566 * simply claims ownership, which should be safe when this function is called
1567 * (i.e. before loading uCode!).
1568 */
1569static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1570{
1571 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1572 return 0;
1573}
1574
b481de9c 1575/**
bb8c093b 1576 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1577 *
6440adb5 1578 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY
1579 *
1580 * NOTE: This routine uses the non-debug IO access functions.
1581 */
bb8c093b 1582int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1583{
58ff6d4d 1584 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1585 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY
1586 u32 r;
1587 int sz = sizeof(priv->eeprom);
1588 int rc;
1589 int i;
1590 u16 addr;
1591
1592 /* The EEPROM structure has several padding buffers within it
1593 * and when adding new EEPROM maps is subject to programmer errors
1594 * which may be very difficult to identify without explicitly
1595 * checking the resulting size of the eeprom map. */
1596 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1597
1598 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1599 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1600 return -ENOENT;
1601 }
1602
6440adb5 1603 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1604 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1605 if (rc < 0) {
91e17473 1606 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY
1607 return -ENOENT;
1608 }
1609
1610 /* eeprom is an array of 16bit values */
1611 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH
1612 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1613 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY
1614
1615 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1616 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1617 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY
1618 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1619 break;
1620 udelay(IWL_EEPROM_ACCESS_DELAY);
1621 }
1622
1623 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1624 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1625 return -ETIMEDOUT;
1626 }
58ff6d4d 1627 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY
1628 }
1629
1630 return 0;
1631}
1632
1633/******************************************************************************
1634 *
1635 * Misc. internal state and helper functions
1636 *
1637 ******************************************************************************/
c8b0e6e1 1638#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
1639
1640/**
bb8c093b 1641 * iwl3945_report_frame - dump frame to syslog during debug sessions
b481de9c 1642 *
9fbab516 1643 * You may hack this function to show different aspects of received frames,
b481de9c
ZY
1644 * including selective frame dumps.
1645 * group100 parameter selects whether to show 1 out of 100 good frames.
b481de9c 1646 */
bb8c093b
CH
1647void iwl3945_report_frame(struct iwl3945_priv *priv,
1648 struct iwl3945_rx_packet *pkt,
b481de9c
ZY
1649 struct ieee80211_hdr *header, int group100)
1650{
1651 u32 to_us;
1652 u32 print_summary = 0;
1653 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
1654 u32 hundred = 0;
1655 u32 dataframe = 0;
1656 u16 fc;
1657 u16 seq_ctl;
1658 u16 channel;
1659 u16 phy_flags;
1660 int rate_sym;
1661 u16 length;
1662 u16 status;
1663 u16 bcn_tmr;
1664 u32 tsf_low;
1665 u64 tsf;
1666 u8 rssi;
1667 u8 agc;
1668 u16 sig_avg;
1669 u16 noise_diff;
bb8c093b
CH
1670 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
1671 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
1672 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY
1673 u8 *data = IWL_RX_DATA(pkt);
1674
1675 /* MAC header */
1676 fc = le16_to_cpu(header->frame_control);
1677 seq_ctl = le16_to_cpu(header->seq_ctrl);
1678
1679 /* metadata */
1680 channel = le16_to_cpu(rx_hdr->channel);
1681 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
1682 rate_sym = rx_hdr->rate;
1683 length = le16_to_cpu(rx_hdr->len);
1684
1685 /* end-of-frame status and timestamp */
1686 status = le32_to_cpu(rx_end->status);
1687 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
1688 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
1689 tsf = le64_to_cpu(rx_end->timestamp);
1690
1691 /* signal statistics */
1692 rssi = rx_stats->rssi;
1693 agc = rx_stats->agc;
1694 sig_avg = le16_to_cpu(rx_stats->sig_avg);
1695 noise_diff = le16_to_cpu(rx_stats->noise_diff);
1696
1697 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
1698
1699 /* if data frame is to us and all is good,
1700 * (optionally) print summary for only 1 out of every 100 */
1701 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
1702 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
1703 dataframe = 1;
1704 if (!group100)
1705 print_summary = 1; /* print each frame */
1706 else if (priv->framecnt_to_us < 100) {
1707 priv->framecnt_to_us++;
1708 print_summary = 0;
1709 } else {
1710 priv->framecnt_to_us = 0;
1711 print_summary = 1;
1712 hundred = 1;
1713 }
1714 } else {
1715 /* print summary for all other frames */
1716 print_summary = 1;
1717 }
1718
1719 if (print_summary) {
1720 char *title;
1721 u32 rate;
1722
1723 if (hundred)
1724 title = "100Frames";
1725 else if (fc & IEEE80211_FCTL_RETRY)
1726 title = "Retry";
1727 else if (ieee80211_is_assoc_response(fc))
1728 title = "AscRsp";
1729 else if (ieee80211_is_reassoc_response(fc))
1730 title = "RasRsp";
1731 else if (ieee80211_is_probe_response(fc)) {
1732 title = "PrbRsp";
1733 print_dump = 1; /* dump frame contents */
1734 } else if (ieee80211_is_beacon(fc)) {
1735 title = "Beacon";
1736 print_dump = 1; /* dump frame contents */
1737 } else if (ieee80211_is_atim(fc))
1738 title = "ATIM";
1739 else if (ieee80211_is_auth(fc))
1740 title = "Auth";
1741 else if (ieee80211_is_deauth(fc))
1742 title = "DeAuth";
1743 else if (ieee80211_is_disassoc(fc))
1744 title = "DisAssoc";
1745 else
1746 title = "Frame";
1747
bb8c093b 1748 rate = iwl3945_rate_index_from_plcp(rate_sym);
b481de9c
ZY
1749 if (rate == -1)
1750 rate = 0;
1751 else
bb8c093b 1752 rate = iwl3945_rates[rate].ieee / 2;
b481de9c
ZY
1753
1754 /* print frame summary.
1755 * MAC addresses show just the last byte (for brevity),
1756 * but you can hack it to show more, if you'd like to. */
1757 if (dataframe)
1758 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
1759 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
1760 title, fc, header->addr1[5],
1761 length, rssi, channel, rate);
1762 else {
1763 /* src/dst addresses assume managed mode */
1764 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
1765 "src=0x%02x, rssi=%u, tim=%lu usec, "
1766 "phy=0x%02x, chnl=%d\n",
1767 title, fc, header->addr1[5],
1768 header->addr3[5], rssi,
1769 tsf_low - priv->scan_start_tsf,
1770 phy_flags, channel);
1771 }
1772 }
1773 if (print_dump)
bb8c093b 1774 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
b481de9c
ZY
1775}
1776#endif
1777
bb8c093b 1778static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY
1779{
1780 if (priv->hw_setting.shared_virt)
1781 pci_free_consistent(priv->pci_dev,
bb8c093b 1782 sizeof(struct iwl3945_shared),
b481de9c
ZY
1783 priv->hw_setting.shared_virt,
1784 priv->hw_setting.shared_phys);
1785}
1786
1787/**
bb8c093b 1788 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY
1789 *
1790 * return : set the bit for each supported rate insert in ie
1791 */
bb8c093b 1792static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1793 u16 basic_rate, int *left)
b481de9c
ZY
1794{
1795 u16 ret_rates = 0, bit;
1796 int i;
c7c46676
TW
1797 u8 *cnt = ie;
1798 u8 *rates = ie + 1;
b481de9c
ZY
1799
1800 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1801 if (bit & supported_rate) {
1802 ret_rates |= bit;
bb8c093b 1803 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW
1804 ((bit & basic_rate) ? 0x80 : 0x00);
1805 (*cnt)++;
1806 (*left)--;
1807 if ((*left <= 0) ||
1808 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY
1809 break;
1810 }
1811 }
1812
1813 return ret_rates;
1814}
1815
1816/**
bb8c093b 1817 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1818 */
bb8c093b 1819static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY
1820 struct ieee80211_mgmt *frame,
1821 int left, int is_direct)
1822{
1823 int len = 0;
1824 u8 *pos = NULL;
c7c46676 1825 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY
1826
1827 /* Make sure there is enough space for the probe request,
1828 * two mandatory IEs and the data */
1829 left -= 24;
1830 if (left < 0)
1831 return 0;
1832 len += 24;
1833
1834 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1835 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1836 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1837 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY
1838 frame->seq_ctrl = 0;
1839
1840 /* fill in our indirect SSID IE */
1841 /* ...next IE... */
1842
1843 left -= 2;
1844 if (left < 0)
1845 return 0;
1846 len += 2;
1847 pos = &(frame->u.probe_req.variable[0]);
1848 *pos++ = WLAN_EID_SSID;
1849 *pos++ = 0;
1850
1851 /* fill in our direct SSID IE... */
1852 if (is_direct) {
1853 /* ...next IE... */
1854 left -= 2 + priv->essid_len;
1855 if (left < 0)
1856 return 0;
1857 /* ... fill it in... */
1858 *pos++ = WLAN_EID_SSID;
1859 *pos++ = priv->essid_len;
1860 memcpy(pos, priv->essid, priv->essid_len);
1861 pos += priv->essid_len;
1862 len += 2 + priv->essid_len;
1863 }
1864
1865 /* fill in supported rate */
1866 /* ...next IE... */
1867 left -= 2;
1868 if (left < 0)
1869 return 0;
c7c46676 1870
b481de9c
ZY
1871 /* ... fill it in... */
1872 *pos++ = WLAN_EID_SUPP_RATES;
1873 *pos = 0;
c7c46676
TW
1874
1875 priv->active_rate = priv->rates_mask;
1876 active_rates = priv->active_rate;
b481de9c
ZY
1877 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1878
c7c46676 1879 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1880 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW
1881 priv->active_rate_basic, &left);
1882 active_rates &= ~ret_rates;
1883
bb8c093b 1884 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW
1885 priv->active_rate_basic, &left);
1886 active_rates &= ~ret_rates;
1887
b481de9c
ZY
1888 len += 2 + *pos;
1889 pos += (*pos) + 1;
c7c46676 1890 if (active_rates == 0)
b481de9c
ZY
1891 goto fill_end;
1892
1893 /* fill in supported extended rate */
1894 /* ...next IE... */
1895 left -= 2;
1896 if (left < 0)
1897 return 0;
1898 /* ... fill it in... */
1899 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1900 *pos = 0;
bb8c093b 1901 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1902 priv->active_rate_basic, &left);
b481de9c
ZY
1903 if (*pos > 0)
1904 len += 2 + *pos;
1905
1906 fill_end:
1907 return (u16)len;
1908}
1909
1910/*
1911 * QoS support
1912*/
bb8c093b
CH
1913static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1914 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY
1915{
1916
bb8c093b
CH
1917 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1918 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY
1919}
1920
bb8c093b 1921static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY
1922{
1923 u16 cw_min = 15;
1924 u16 cw_max = 1023;
1925 u8 aifs = 2;
1926 u8 is_legacy = 0;
1927 unsigned long flags;
1928 int i;
1929
1930 spin_lock_irqsave(&priv->lock, flags);
1931 priv->qos_data.qos_active = 0;
1932
1933 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1934 if (priv->qos_data.qos_enable)
1935 priv->qos_data.qos_active = 1;
1936 if (!(priv->active_rate & 0xfff0)) {
1937 cw_min = 31;
1938 is_legacy = 1;
1939 }
1940 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1941 if (priv->qos_data.qos_enable)
1942 priv->qos_data.qos_active = 1;
1943 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1944 cw_min = 31;
1945 is_legacy = 1;
1946 }
1947
1948 if (priv->qos_data.qos_active)
1949 aifs = 3;
1950
1951 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1952 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1953 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1954 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1955 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1956
1957 if (priv->qos_data.qos_active) {
1958 i = 1;
1959 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1960 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1961 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1962 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1963 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1964
1965 i = 2;
1966 priv->qos_data.def_qos_parm.ac[i].cw_min =
1967 cpu_to_le16((cw_min + 1) / 2 - 1);
1968 priv->qos_data.def_qos_parm.ac[i].cw_max =
1969 cpu_to_le16(cw_max);
1970 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1971 if (is_legacy)
1972 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1973 cpu_to_le16(6016);
1974 else
1975 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1976 cpu_to_le16(3008);
1977 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1978
1979 i = 3;
1980 priv->qos_data.def_qos_parm.ac[i].cw_min =
1981 cpu_to_le16((cw_min + 1) / 4 - 1);
1982 priv->qos_data.def_qos_parm.ac[i].cw_max =
1983 cpu_to_le16((cw_max + 1) / 2 - 1);
1984 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1985 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1986 if (is_legacy)
1987 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1988 cpu_to_le16(3264);
1989 else
1990 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1991 cpu_to_le16(1504);
1992 } else {
1993 for (i = 1; i < 4; i++) {
1994 priv->qos_data.def_qos_parm.ac[i].cw_min =
1995 cpu_to_le16(cw_min);
1996 priv->qos_data.def_qos_parm.ac[i].cw_max =
1997 cpu_to_le16(cw_max);
1998 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1999 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
2000 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
2001 }
2002 }
2003 IWL_DEBUG_QOS("set QoS to default \n");
2004
2005 spin_unlock_irqrestore(&priv->lock, flags);
2006}
2007
bb8c093b 2008static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY
2009{
2010 unsigned long flags;
2011
b481de9c
ZY
2012 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2013 return;
2014
2015 if (!priv->qos_data.qos_enable)
2016 return;
2017
2018 spin_lock_irqsave(&priv->lock, flags);
2019 priv->qos_data.def_qos_parm.qos_flags = 0;
2020
2021 if (priv->qos_data.qos_cap.q_AP.queue_request &&
2022 !priv->qos_data.qos_cap.q_AP.txop_request)
2023 priv->qos_data.def_qos_parm.qos_flags |=
2024 QOS_PARAM_FLG_TXOP_TYPE_MSK;
2025
2026 if (priv->qos_data.qos_active)
2027 priv->qos_data.def_qos_parm.qos_flags |=
2028 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
2029
2030 spin_unlock_irqrestore(&priv->lock, flags);
2031
bb8c093b 2032 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY
2033 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
2034 priv->qos_data.qos_active);
2035
bb8c093b 2036 iwl3945_send_qos_params_command(priv,
b481de9c
ZY
2037 &(priv->qos_data.def_qos_parm));
2038 }
2039}
2040
b481de9c
ZY
2041/*
2042 * Power management (not Tx power!) functions
2043 */
2044#define MSEC_TO_USEC 1024
2045
2046#define NOSLP __constant_cpu_to_le32(0)
2047#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
2048#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
2049#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
2050 __constant_cpu_to_le32(X1), \
2051 __constant_cpu_to_le32(X2), \
2052 __constant_cpu_to_le32(X3), \
2053 __constant_cpu_to_le32(X4)}
2054
2055
2056/* default power management (not Tx power) table values */
2057/* for tim 0-10 */
bb8c093b 2058static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY
2059 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2060 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
2061 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
2062 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
2063 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
2064 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
2065};
2066
2067/* for tim > 10 */
bb8c093b 2068static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY
2069 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2070 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
2071 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
2072 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
2073 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
2074 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
2075 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
2076 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
2077 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
2078 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
2079};
2080
bb8c093b 2081int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY
2082{
2083 int rc = 0, i;
bb8c093b
CH
2084 struct iwl3945_power_mgr *pow_data;
2085 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY
2086 u16 pci_pm;
2087
2088 IWL_DEBUG_POWER("Initialize power \n");
2089
2090 pow_data = &(priv->power_data);
2091
2092 memset(pow_data, 0, sizeof(*pow_data));
2093
2094 pow_data->active_index = IWL_POWER_RANGE_0;
2095 pow_data->dtim_val = 0xffff;
2096
2097 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
2098 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
2099
2100 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
2101 if (rc != 0)
2102 return 0;
2103 else {
bb8c093b 2104 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY
2105
2106 IWL_DEBUG_POWER("adjust power command flags\n");
2107
2108 for (i = 0; i < IWL_POWER_AC; i++) {
2109 cmd = &pow_data->pwr_range_0[i].cmd;
2110
2111 if (pci_pm & 0x1)
2112 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
2113 else
2114 cmd->flags |= IWL_POWER_PCI_PM_MSK;
2115 }
2116 }
2117 return rc;
2118}
2119
bb8c093b
CH
2120static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
2121 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY
2122{
2123 int rc = 0, i;
2124 u8 skip;
2125 u32 max_sleep = 0;
bb8c093b 2126 struct iwl3945_power_vec_entry *range;
b481de9c 2127 u8 period = 0;
bb8c093b 2128 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY
2129
2130 if (mode > IWL_POWER_INDEX_5) {
2131 IWL_DEBUG_POWER("Error invalid power mode \n");
2132 return -1;
2133 }
2134 pow_data = &(priv->power_data);
2135
2136 if (pow_data->active_index == IWL_POWER_RANGE_0)
2137 range = &pow_data->pwr_range_0[0];
2138 else
2139 range = &pow_data->pwr_range_1[1];
2140
bb8c093b 2141 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY
2142
2143#ifdef IWL_MAC80211_DISABLE
2144 if (priv->assoc_network != NULL) {
2145 unsigned long flags;
2146
2147 period = priv->assoc_network->tim.tim_period;
2148 }
2149#endif /*IWL_MAC80211_DISABLE */
2150 skip = range[mode].no_dtim;
2151
2152 if (period == 0) {
2153 period = 1;
2154 skip = 0;
2155 }
2156
2157 if (skip == 0) {
2158 max_sleep = period;
2159 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
2160 } else {
2161 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
2162 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
2163 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
2164 }
2165
2166 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
2167 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
2168 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
2169 }
2170
2171 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
2172 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
2173 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
2174 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
2175 le32_to_cpu(cmd->sleep_interval[0]),
2176 le32_to_cpu(cmd->sleep_interval[1]),
2177 le32_to_cpu(cmd->sleep_interval[2]),
2178 le32_to_cpu(cmd->sleep_interval[3]),
2179 le32_to_cpu(cmd->sleep_interval[4]));
2180
2181 return rc;
2182}
2183
bb8c093b 2184static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 2185{
9a62f73b 2186 u32 uninitialized_var(final_mode);
b481de9c 2187 int rc;
bb8c093b 2188 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY
2189
2190 /* If on battery, set to 3,
01ebd063 2191 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY
2192 * else user level */
2193 switch (mode) {
2194 case IWL_POWER_BATTERY:
2195 final_mode = IWL_POWER_INDEX_3;
2196 break;
2197 case IWL_POWER_AC:
2198 final_mode = IWL_POWER_MODE_CAM;
2199 break;
2200 default:
2201 final_mode = mode;
2202 break;
2203 }
2204
bb8c093b 2205 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2206
bb8c093b 2207 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY
2208
2209 if (final_mode == IWL_POWER_MODE_CAM)
2210 clear_bit(STATUS_POWER_PMI, &priv->status);
2211 else
2212 set_bit(STATUS_POWER_PMI, &priv->status);
2213
2214 return rc;
2215}
2216
bb8c093b 2217int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY
2218{
2219 /* Filter incoming packets to determine if they are targeted toward
2220 * this network, discarding packets coming from ourselves */
2221 switch (priv->iw_mode) {
2222 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2223 /* packets from our adapter are dropped (echo) */
2224 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2225 return 0;
2226 /* {broad,multi}cast packets to our IBSS go through */
2227 if (is_multicast_ether_addr(header->addr1))
2228 return !compare_ether_addr(header->addr3, priv->bssid);
2229 /* packets to our adapter go through */
2230 return !compare_ether_addr(header->addr1, priv->mac_addr);
2231 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2232 /* packets from our adapter are dropped (echo) */
2233 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2234 return 0;
2235 /* {broad,multi}cast packets to our BSS go through */
2236 if (is_multicast_ether_addr(header->addr1))
2237 return !compare_ether_addr(header->addr2, priv->bssid);
2238 /* packets to our adapter go through */
2239 return !compare_ether_addr(header->addr1, priv->mac_addr);
2240 }
2241
2242 return 1;
2243}
2244
2245#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2246
bb8c093b 2247static const char *iwl3945_get_tx_fail_reason(u32 status)
b481de9c
ZY
2248{
2249 switch (status & TX_STATUS_MSK) {
2250 case TX_STATUS_SUCCESS:
2251 return "SUCCESS";
2252 TX_STATUS_ENTRY(SHORT_LIMIT);
2253 TX_STATUS_ENTRY(LONG_LIMIT);
2254 TX_STATUS_ENTRY(FIFO_UNDERRUN);
2255 TX_STATUS_ENTRY(MGMNT_ABORT);
2256 TX_STATUS_ENTRY(NEXT_FRAG);
2257 TX_STATUS_ENTRY(LIFE_EXPIRE);
2258 TX_STATUS_ENTRY(DEST_PS);
2259 TX_STATUS_ENTRY(ABORTED);
2260 TX_STATUS_ENTRY(BT_RETRY);
2261 TX_STATUS_ENTRY(STA_INVALID);
2262 TX_STATUS_ENTRY(FRAG_DROPPED);
2263 TX_STATUS_ENTRY(TID_DISABLE);
2264 TX_STATUS_ENTRY(FRAME_FLUSHED);
2265 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
2266 TX_STATUS_ENTRY(TX_LOCKED);
2267 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
2268 }
2269
2270 return "UNKNOWN";
2271}
2272
2273/**
bb8c093b 2274 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY
2275 *
2276 * NOTE: priv->mutex is not required before calling this function
2277 */
bb8c093b 2278static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY
2279{
2280 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2281 clear_bit(STATUS_SCANNING, &priv->status);
2282 return 0;
2283 }
2284
2285 if (test_bit(STATUS_SCANNING, &priv->status)) {
2286 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2287 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2288 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2289 queue_work(priv->workqueue, &priv->abort_scan);
2290
2291 } else
2292 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2293
2294 return test_bit(STATUS_SCANNING, &priv->status);
2295 }
2296
2297 return 0;
2298}
2299
2300/**
bb8c093b 2301 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY
2302 * @ms: amount of time to wait (in milliseconds) for scan to abort
2303 *
2304 * NOTE: priv->mutex must be held before calling this function
2305 */
bb8c093b 2306static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY
2307{
2308 unsigned long now = jiffies;
2309 int ret;
2310
bb8c093b 2311 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY
2312 if (ret && ms) {
2313 mutex_unlock(&priv->mutex);
2314 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2315 test_bit(STATUS_SCANNING, &priv->status))
2316 msleep(1);
2317 mutex_lock(&priv->mutex);
2318
2319 return test_bit(STATUS_SCANNING, &priv->status);
2320 }
2321
2322 return ret;
2323}
2324
bb8c093b 2325static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY
2326{
2327 /* Reset ieee stats */
2328
2329 /* We don't reset the net_device_stats (ieee->stats) on
2330 * re-association */
2331
2332 priv->last_seq_num = -1;
2333 priv->last_frag_num = -1;
2334 priv->last_packet_time = 0;
2335
bb8c093b 2336 iwl3945_scan_cancel(priv);
b481de9c
ZY
2337}
2338
2339#define MAX_UCODE_BEACON_INTERVAL 1024
2340#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2341
bb8c093b 2342static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
2343{
2344 u16 new_val = 0;
2345 u16 beacon_factor = 0;
2346
2347 beacon_factor =
2348 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2349 / MAX_UCODE_BEACON_INTERVAL;
2350 new_val = beacon_val / beacon_factor;
2351
2352 return cpu_to_le16(new_val);
2353}
2354
bb8c093b 2355static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY
2356{
2357 u64 interval_tm_unit;
2358 u64 tsf, result;
2359 unsigned long flags;
2360 struct ieee80211_conf *conf = NULL;
2361 u16 beacon_int = 0;
2362
2363 conf = ieee80211_get_hw_conf(priv->hw);
2364
2365 spin_lock_irqsave(&priv->lock, flags);
2366 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2367 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2368
2369 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2370
2371 tsf = priv->timestamp1;
2372 tsf = ((tsf << 32) | priv->timestamp0);
2373
2374 beacon_int = priv->beacon_int;
2375 spin_unlock_irqrestore(&priv->lock, flags);
2376
2377 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2378 if (beacon_int == 0) {
2379 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2380 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2381 } else {
2382 priv->rxon_timing.beacon_interval =
2383 cpu_to_le16(beacon_int);
2384 priv->rxon_timing.beacon_interval =
bb8c093b 2385 iwl3945_adjust_beacon_interval(
b481de9c
ZY
2386 le16_to_cpu(priv->rxon_timing.beacon_interval));
2387 }
2388
2389 priv->rxon_timing.atim_window = 0;
2390 } else {
2391 priv->rxon_timing.beacon_interval =
bb8c093b 2392 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY
2393 /* TODO: we need to get atim_window from upper stack
2394 * for now we set to 0 */
2395 priv->rxon_timing.atim_window = 0;
2396 }
2397
2398 interval_tm_unit =
2399 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2400 result = do_div(tsf, interval_tm_unit);
2401 priv->rxon_timing.beacon_init_val =
2402 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2403
2404 IWL_DEBUG_ASSOC
2405 ("beacon interval %d beacon timer %d beacon tim %d\n",
2406 le16_to_cpu(priv->rxon_timing.beacon_interval),
2407 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2408 le16_to_cpu(priv->rxon_timing.atim_window));
2409}
2410
bb8c093b 2411static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY
2412{
2413 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2414 IWL_ERROR("APs don't scan.\n");
2415 return 0;
2416 }
2417
bb8c093b 2418 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
2419 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2420 return -EIO;
2421 }
2422
2423 if (test_bit(STATUS_SCANNING, &priv->status)) {
2424 IWL_DEBUG_SCAN("Scan already in progress.\n");
2425 return -EAGAIN;
2426 }
2427
2428 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2429 IWL_DEBUG_SCAN("Scan request while abort pending. "
2430 "Queuing.\n");
2431 return -EAGAIN;
2432 }
2433
2434 IWL_DEBUG_INFO("Starting scan...\n");
2435 priv->scan_bands = 2;
2436 set_bit(STATUS_SCANNING, &priv->status);
2437 priv->scan_start = jiffies;
2438 priv->scan_pass_start = priv->scan_start;
2439
2440 queue_work(priv->workqueue, &priv->request_scan);
2441
2442 return 0;
2443}
2444
bb8c093b 2445static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2446{
bb8c093b 2447 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY
2448
2449 if (hw_decrypt)
2450 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2451 else
2452 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2453
2454 return 0;
2455}
2456
8318d78a
JB
2457static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2458 enum ieee80211_band band)
b481de9c 2459{
8318d78a 2460 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY
2461 priv->staging_rxon.flags &=
2462 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2463 | RXON_FLG_CCK_MSK);
2464 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2465 } else {
bb8c093b 2466 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY
2467 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2468 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2469 else
2470 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2471
2472 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2473 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2474
2475 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2476 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2477 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2478 }
2479}
2480
2481/*
01ebd063 2482 * initialize rxon structure with default values from eeprom
b481de9c 2483 */
bb8c093b 2484static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2485{
bb8c093b 2486 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY
2487
2488 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2489
2490 switch (priv->iw_mode) {
2491 case IEEE80211_IF_TYPE_AP:
2492 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2493 break;
2494
2495 case IEEE80211_IF_TYPE_STA:
2496 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2497 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2498 break;
2499
2500 case IEEE80211_IF_TYPE_IBSS:
2501 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2502 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2503 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2504 RXON_FILTER_ACCEPT_GRP_MSK;
2505 break;
2506
2507 case IEEE80211_IF_TYPE_MNTR:
2508 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2509 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2510 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2511 break;
2512 }
2513
2514#if 0
2515 /* TODO: Figure out when short_preamble would be set and cache from
2516 * that */
2517 if (!hw_to_local(priv->hw)->short_preamble)
2518 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2519 else
2520 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2521#endif
2522
8318d78a 2523 ch_info = iwl3945_get_channel_info(priv, priv->band,
b481de9c
ZY
2524 le16_to_cpu(priv->staging_rxon.channel));
2525
2526 if (!ch_info)
2527 ch_info = &priv->channel_info[0];
2528
2529 /*
2530 * in some case A channels are all non IBSS
2531 * in this case force B/G channel
2532 */
2533 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2534 !(is_channel_ibss(ch_info)))
2535 ch_info = &priv->channel_info[0];
2536
2537 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2538 if (is_channel_a_band(ch_info))
8318d78a 2539 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2540 else
8318d78a 2541 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2542
8318d78a 2543 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY
2544
2545 priv->staging_rxon.ofdm_basic_rates =
2546 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2547 priv->staging_rxon.cck_basic_rates =
2548 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2549}
2550
bb8c093b 2551static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2552{
b481de9c 2553 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2554 const struct iwl3945_channel_info *ch_info;
b481de9c 2555
bb8c093b 2556 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2557 priv->band,
b481de9c
ZY
2558 le16_to_cpu(priv->staging_rxon.channel));
2559
2560 if (!ch_info || !is_channel_ibss(ch_info)) {
2561 IWL_ERROR("channel %d not IBSS channel\n",
2562 le16_to_cpu(priv->staging_rxon.channel));
2563 return -EINVAL;
2564 }
2565 }
2566
b481de9c
ZY
2567 priv->iw_mode = mode;
2568
bb8c093b 2569 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY
2570 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2571
bb8c093b 2572 iwl3945_clear_stations_table(priv);
b481de9c 2573
fde3571f
MA
2574 /* dont commit rxon if rf-kill is on*/
2575 if (!iwl3945_is_ready_rf(priv))
2576 return -EAGAIN;
2577
2578 cancel_delayed_work(&priv->scan_check);
2579 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2580 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2581 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2582 return -EAGAIN;
2583 }
2584
bb8c093b 2585 iwl3945_commit_rxon(priv);
b481de9c
ZY
2586
2587 return 0;
2588}
2589
bb8c093b 2590static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
b481de9c 2591 struct ieee80211_tx_control *ctl,
bb8c093b 2592 struct iwl3945_cmd *cmd,
b481de9c
ZY
2593 struct sk_buff *skb_frag,
2594 int last_frag)
2595{
bb8c093b 2596 struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY
2597
2598 switch (keyinfo->alg) {
2599 case ALG_CCMP:
2600 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2601 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2602 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2603 break;
2604
2605 case ALG_TKIP:
2606#if 0
2607 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2608
2609 if (last_frag)
2610 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2611 8);
2612 else
2613 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2614#endif
2615 break;
2616
2617 case ALG_WEP:
2618 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2619 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2620
2621 if (keyinfo->keylen == 13)
2622 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2623
2624 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2625
2626 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2627 "with key %d\n", ctl->key_idx);
2628 break;
2629
b481de9c
ZY
2630 default:
2631 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2632 break;
2633 }
2634}
2635
2636/*
2637 * handle build REPLY_TX command notification.
2638 */
bb8c093b
CH
2639static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2640 struct iwl3945_cmd *cmd,
b481de9c
ZY
2641 struct ieee80211_tx_control *ctrl,
2642 struct ieee80211_hdr *hdr,
2643 int is_unicast, u8 std_id)
2644{
2645 __le16 *qc;
2646 u16 fc = le16_to_cpu(hdr->frame_control);
2647 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2648
2649 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2650 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2651 tx_flags |= TX_CMD_FLG_ACK_MSK;
2652 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2653 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2654 if (ieee80211_is_probe_response(fc) &&
2655 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2656 tx_flags |= TX_CMD_FLG_TSF_MSK;
2657 } else {
2658 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2659 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2660 }
2661
2662 cmd->cmd.tx.sta_id = std_id;
2663 if (ieee80211_get_morefrag(hdr))
2664 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2665
2666 qc = ieee80211_get_qos_ctrl(hdr);
2667 if (qc) {
2668 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2669 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2670 } else
2671 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2672
2673 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2674 tx_flags |= TX_CMD_FLG_RTS_MSK;
2675 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2676 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2677 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2678 tx_flags |= TX_CMD_FLG_CTS_MSK;
2679 }
2680
2681 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2682 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2683
2684 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2685 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2686 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2687 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2688 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2689 else
bc434dd2 2690 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
b481de9c
ZY
2691 } else
2692 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2693
2694 cmd->cmd.tx.driver_txop = 0;
2695 cmd->cmd.tx.tx_flags = tx_flags;
2696 cmd->cmd.tx.next_frame_len = 0;
2697}
2698
6440adb5
BC
2699/**
2700 * iwl3945_get_sta_id - Find station's index within station table
2701 */
bb8c093b 2702static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY
2703{
2704 int sta_id;
2705 u16 fc = le16_to_cpu(hdr->frame_control);
2706
6440adb5 2707 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY
2708 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2709 is_multicast_ether_addr(hdr->addr1))
2710 return priv->hw_setting.bcast_sta_id;
2711
2712 switch (priv->iw_mode) {
2713
6440adb5
BC
2714 /* If we are a client station in a BSS network, use the special
2715 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY
2716 case IEEE80211_IF_TYPE_STA:
2717 return IWL_AP_ID;
2718
2719 /* If we are an AP, then find the station, or use BCAST */
2720 case IEEE80211_IF_TYPE_AP:
bb8c093b 2721 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2722 if (sta_id != IWL_INVALID_STATION)
2723 return sta_id;
2724 return priv->hw_setting.bcast_sta_id;
2725
6440adb5
BC
2726 /* If this frame is going out to an IBSS network, find the station,
2727 * or create a new station table entry */
0795af57
JP
2728 case IEEE80211_IF_TYPE_IBSS: {
2729 DECLARE_MAC_BUF(mac);
2730
6440adb5 2731 /* Create new station table entry */
bb8c093b 2732 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2733 if (sta_id != IWL_INVALID_STATION)
2734 return sta_id;
2735
bb8c093b 2736 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY
2737
2738 if (sta_id != IWL_INVALID_STATION)
2739 return sta_id;
2740
0795af57 2741 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2742 "Defaulting to broadcast...\n",
0795af57 2743 print_mac(mac, hdr->addr1));
bb8c093b 2744 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2745 return priv->hw_setting.bcast_sta_id;
0795af57 2746 }
b481de9c 2747 default:
01ebd063 2748 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY
2749 return priv->hw_setting.bcast_sta_id;
2750 }
2751}
2752
2753/*
2754 * start REPLY_TX command process
2755 */
bb8c093b 2756static int iwl3945_tx_skb(struct iwl3945_priv *priv,
b481de9c
ZY
2757 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2758{
2759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2760 struct iwl3945_tfd_frame *tfd;
b481de9c
ZY
2761 u32 *control_flags;
2762 int txq_id = ctl->queue;
bb8c093b
CH
2763 struct iwl3945_tx_queue *txq = NULL;
2764 struct iwl3945_queue *q = NULL;
b481de9c
ZY
2765 dma_addr_t phys_addr;
2766 dma_addr_t txcmd_phys;
bb8c093b 2767 struct iwl3945_cmd *out_cmd = NULL;
b481de9c
ZY
2768 u16 len, idx, len_org;
2769 u8 id, hdr_len, unicast;
2770 u8 sta_id;
2771 u16 seq_number = 0;
2772 u16 fc;
2773 __le16 *qc;
2774 u8 wait_write_ptr = 0;
2775 unsigned long flags;
2776 int rc;
2777
2778 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2779 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY
2780 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2781 goto drop_unlock;
2782 }
2783
32bfd35d
JB
2784 if (!priv->vif) {
2785 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY
2786 goto drop_unlock;
2787 }
2788
8318d78a 2789 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY
2790 IWL_ERROR("ERROR: No TX rate available.\n");
2791 goto drop_unlock;
2792 }
2793
2794 unicast = !is_multicast_ether_addr(hdr->addr1);
2795 id = 0;
2796
2797 fc = le16_to_cpu(hdr->frame_control);
2798
c8b0e6e1 2799#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
2800 if (ieee80211_is_auth(fc))
2801 IWL_DEBUG_TX("Sending AUTH frame\n");
2802 else if (ieee80211_is_assoc_request(fc))
2803 IWL_DEBUG_TX("Sending ASSOC frame\n");
2804 else if (ieee80211_is_reassoc_request(fc))
2805 IWL_DEBUG_TX("Sending REASSOC frame\n");
2806#endif
2807
7878a5a4 2808 /* drop all data frame if we are not associated */
a6477249
RC
2809 if ((!iwl3945_is_associated(priv) ||
2810 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
b481de9c 2811 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2812 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY
2813 goto drop_unlock;
2814 }
2815
2816 spin_unlock_irqrestore(&priv->lock, flags);
2817
2818 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
BC
2819
2820 /* Find (or create) index into station table for destination station */
bb8c093b 2821 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2822 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP
2823 DECLARE_MAC_BUF(mac);
2824
2825 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2826 print_mac(mac, hdr->addr1));
b481de9c
ZY
2827 goto drop;
2828 }
2829
2830 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2831
2832 qc = ieee80211_get_qos_ctrl(hdr);
2833 if (qc) {
2834 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2835 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2836 IEEE80211_SCTL_SEQ;
2837 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2838 (hdr->seq_ctrl &
2839 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2840 seq_number += 0x10;
2841 }
6440adb5
BC
2842
2843 /* Descriptor for chosen Tx queue */
b481de9c
ZY
2844 txq = &priv->txq[txq_id];
2845 q = &txq->q;
2846
2847 spin_lock_irqsave(&priv->lock, flags);
2848
6440adb5 2849 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2850 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
2851 memset(tfd, 0, sizeof(*tfd));
2852 control_flags = (u32 *) tfd;
fc4b6853 2853 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2854
6440adb5 2855 /* Set up driver data for this TFD */
bb8c093b 2856 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853
TW
2857 txq->txb[q->write_ptr].skb[0] = skb;
2858 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2859 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
BC
2860
2861 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY
2862 out_cmd = &txq->cmd[idx];
2863 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2864 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
BC
2865
2866 /*
2867 * Set up the Tx-command (not MAC!) header.
2868 * Store the chosen Tx queue and TFD index within the sequence field;
2869 * after Tx, uCode's Tx response will return this value so driver can
2870 * locate the frame within the tx queue and do post-tx processing.
2871 */
b481de9c
ZY
2872 out_cmd->hdr.cmd = REPLY_TX;
2873 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2874 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
2875
2876 /* Copy MAC header from skb into command buffer */
b481de9c
ZY
2877 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2878
6440adb5
BC
2879 /*
2880 * Use the first empty entry in this queue's command buffer array
2881 * to contain the Tx command and MAC header concatenated together
2882 * (payload data will be in another buffer).
2883 * Size of this varies, due to varying MAC header length.
2884 * If end is not dword aligned, we'll have 2 extra bytes at the end
2885 * of the MAC header (device reads on dword boundaries).
2886 * We'll tell device about this padding later.
2887 */
b481de9c 2888 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2889 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY
2890
2891 len_org = len;
2892 len = (len + 3) & ~3;
2893
2894 if (len_org != len)
2895 len_org = 1;
2896 else
2897 len_org = 0;
2898
6440adb5
BC
2899 /* Physical address of this Tx command's header (not MAC header!),
2900 * within command buffer array. */
bb8c093b
CH
2901 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2902 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2903
6440adb5
BC
2904 /* Add buffer containing Tx command and MAC(!) header to TFD's
2905 * first entry */
bb8c093b 2906 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY
2907
2908 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2909 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2910
6440adb5
BC
2911 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2912 * if any (802.11 null frames have no payload). */
b481de9c
ZY
2913 len = skb->len - hdr_len;
2914 if (len) {
2915 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2916 len, PCI_DMA_TODEVICE);
bb8c093b 2917 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY
2918 }
2919
b481de9c 2920 if (!len)
6440adb5 2921 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY
2922 *control_flags = TFD_CTL_COUNT_SET(1);
2923 else
6440adb5
BC
2924 /* Else use 2 buffers.
2925 * Tell 3945 about any padding after MAC header */
b481de9c
ZY
2926 *control_flags = TFD_CTL_COUNT_SET(2) |
2927 TFD_CTL_PAD_SET(U32_PAD(len));
2928
6440adb5 2929 /* Total # bytes to be transmitted */
b481de9c
ZY
2930 len = (u16)skb->len;
2931 out_cmd->cmd.tx.len = cpu_to_le16(len);
2932
2933 /* TODO need this for burst mode later on */
bb8c093b 2934 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY
2935
2936 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2937 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c
ZY
2938
2939 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2940 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2941
2942 if (!ieee80211_get_morefrag(hdr)) {
2943 txq->need_update = 1;
2944 if (qc) {
2945 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2946 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2947 }
2948 } else {
2949 wait_write_ptr = 1;
2950 txq->need_update = 0;
2951 }
2952
bb8c093b 2953 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY
2954 sizeof(out_cmd->cmd.tx));
2955
bb8c093b 2956 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY
2957 ieee80211_get_hdrlen(fc));
2958
6440adb5 2959 /* Tell device the write index *just past* this latest filled TFD */
bb8c093b
CH
2960 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
2961 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2962 spin_unlock_irqrestore(&priv->lock, flags);
2963
2964 if (rc)
2965 return rc;
2966
bb8c093b 2967 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY
2968 && priv->mac80211_registered) {
2969 if (wait_write_ptr) {
2970 spin_lock_irqsave(&priv->lock, flags);
2971 txq->need_update = 1;
bb8c093b 2972 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2973 spin_unlock_irqrestore(&priv->lock, flags);
2974 }
2975
2976 ieee80211_stop_queue(priv->hw, ctl->queue);
2977 }
2978
2979 return 0;
2980
2981drop_unlock:
2982 spin_unlock_irqrestore(&priv->lock, flags);
2983drop:
2984 return -1;
2985}
2986
bb8c093b 2987static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2988{
8318d78a 2989 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY
2990 struct ieee80211_rate *rate;
2991 int i;
2992
8318d78a
JB
2993 sband = iwl3945_get_band(priv, priv->band);
2994 if (!sband) {
c4ba9621
SA
2995 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2996 return;
2997 }
b481de9c
ZY
2998
2999 priv->active_rate = 0;
3000 priv->active_rate_basic = 0;
3001
8318d78a
JB
3002 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
3003 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
3004
3005 for (i = 0; i < sband->n_bitrates; i++) {
3006 rate = &sband->bitrates[i];
3007 if ((rate->hw_value < IWL_RATE_COUNT) &&
3008 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
3009 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
3010 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
3011 priv->active_rate |= (1 << rate->hw_value);
3012 }
b481de9c
ZY
3013 }
3014
3015 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
3016 priv->active_rate, priv->active_rate_basic);
3017
3018 /*
3019 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
3020 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
3021 * OFDM
3022 */
3023 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
3024 priv->staging_rxon.cck_basic_rates =
3025 ((priv->active_rate_basic &
3026 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
3027 else
3028 priv->staging_rxon.cck_basic_rates =
3029 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
3030
3031 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
3032 priv->staging_rxon.ofdm_basic_rates =
3033 ((priv->active_rate_basic &
3034 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
3035 IWL_FIRST_OFDM_RATE) & 0xFF;
3036 else
3037 priv->staging_rxon.ofdm_basic_rates =
3038 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
3039}
3040
bb8c093b 3041static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY
3042{
3043 unsigned long flags;
3044
3045 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
3046 return;
3047
3048 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
3049 disable_radio ? "OFF" : "ON");
3050
3051 if (disable_radio) {
bb8c093b 3052 iwl3945_scan_cancel(priv);
b481de9c
ZY
3053 /* FIXME: This is a workaround for AP */
3054 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
3055 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3056 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3057 CSR_UCODE_SW_BIT_RFKILL);
3058 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 3059 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY
3060 set_bit(STATUS_RF_KILL_SW, &priv->status);
3061 }
3062 return;
3063 }
3064
3065 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3066 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
3067
3068 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3069 spin_unlock_irqrestore(&priv->lock, flags);
3070
3071 /* wake up ucode */
3072 msleep(10);
3073
3074 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
3075 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3076 if (!iwl3945_grab_nic_access(priv))
3077 iwl3945_release_nic_access(priv);
b481de9c
ZY
3078 spin_unlock_irqrestore(&priv->lock, flags);
3079
3080 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
3081 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
3082 "disabled by HW switch\n");
3083 return;
3084 }
3085
3086 queue_work(priv->workqueue, &priv->restart);
3087 return;
3088}
3089
bb8c093b 3090void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY
3091 u32 decrypt_res, struct ieee80211_rx_status *stats)
3092{
3093 u16 fc =
3094 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
3095
3096 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
3097 return;
3098
3099 if (!(fc & IEEE80211_FCTL_PROTECTED))
3100 return;
3101
3102 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
3103 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
3104 case RX_RES_STATUS_SEC_TYPE_TKIP:
3105 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3106 RX_RES_STATUS_BAD_ICV_MIC)
3107 stats->flag |= RX_FLAG_MMIC_ERROR;
3108 case RX_RES_STATUS_SEC_TYPE_WEP:
3109 case RX_RES_STATUS_SEC_TYPE_CCMP:
3110 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3111 RX_RES_STATUS_DECRYPT_OK) {
3112 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
3113 stats->flag |= RX_FLAG_DECRYPTED;
3114 }
3115 break;
3116
3117 default:
3118 break;
3119 }
3120}
3121
b481de9c
ZY
3122#define IWL_PACKET_RETRY_TIME HZ
3123
bb8c093b 3124int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY
3125{
3126 u16 sc = le16_to_cpu(header->seq_ctrl);
3127 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
3128 u16 frag = sc & IEEE80211_SCTL_FRAG;
3129 u16 *last_seq, *last_frag;
3130 unsigned long *last_time;
3131
3132 switch (priv->iw_mode) {
3133 case IEEE80211_IF_TYPE_IBSS:{
3134 struct list_head *p;
bb8c093b 3135 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY
3136 u8 *mac = header->addr2;
3137 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
3138
3139 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 3140 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY
3141 if (!compare_ether_addr(entry->mac, mac))
3142 break;
3143 }
3144 if (p == &priv->ibss_mac_hash[index]) {
3145 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
3146 if (!entry) {
bc434dd2 3147 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY
3148 return 0;
3149 }
3150 memcpy(entry->mac, mac, ETH_ALEN);
3151 entry->seq_num = seq;
3152 entry->frag_num = frag;
3153 entry->packet_time = jiffies;
bc434dd2 3154 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY
3155 return 0;
3156 }
3157 last_seq = &entry->seq_num;
3158 last_frag = &entry->frag_num;
3159 last_time = &entry->packet_time;
3160 break;
3161 }
3162 case IEEE80211_IF_TYPE_STA:
3163 last_seq = &priv->last_seq_num;
3164 last_frag = &priv->last_frag_num;
3165 last_time = &priv->last_packet_time;
3166 break;
3167 default:
3168 return 0;
3169 }
3170 if ((*last_seq == seq) &&
3171 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
3172 if (*last_frag == frag)
3173 goto drop;
3174 if (*last_frag + 1 != frag)
3175 /* out-of-order fragment */
3176 goto drop;
3177 } else
3178 *last_seq = seq;
3179
3180 *last_frag = frag;
3181 *last_time = jiffies;
3182 return 0;
3183
3184 drop:
3185 return 1;
3186}
3187
c8b0e6e1 3188#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3189
3190#include "iwl-spectrum.h"
3191
3192#define BEACON_TIME_MASK_LOW 0x00FFFFFF
3193#define BEACON_TIME_MASK_HIGH 0xFF000000
3194#define TIME_UNIT 1024
3195
3196/*
3197 * extended beacon time format
3198 * time in usec will be changed into a 32-bit value in 8:24 format
3199 * the high 1 byte is the beacon counts
3200 * the lower 3 bytes is the time in usec within one beacon interval
3201 */
3202
bb8c093b 3203static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
3204{
3205 u32 quot;
3206 u32 rem;
3207 u32 interval = beacon_interval * 1024;
3208
3209 if (!interval || !usec)
3210 return 0;
3211
3212 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3213 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3214
3215 return (quot << 24) + rem;
3216}
3217
3218/* base is usually what we get from ucode with each received frame,
3219 * the same as HW timer counter counting down
3220 */
3221
bb8c093b 3222static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
3223{
3224 u32 base_low = base & BEACON_TIME_MASK_LOW;
3225 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3226 u32 interval = beacon_interval * TIME_UNIT;
3227 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3228 (addon & BEACON_TIME_MASK_HIGH);
3229
3230 if (base_low > addon_low)
3231 res += base_low - addon_low;
3232 else if (base_low < addon_low) {
3233 res += interval + base_low - addon_low;
3234 res += (1 << 24);
3235 } else
3236 res += (1 << 24);
3237
3238 return cpu_to_le32(res);
3239}
3240
bb8c093b 3241static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY
3242 struct ieee80211_measurement_params *params,
3243 u8 type)
3244{
bb8c093b
CH
3245 struct iwl3945_spectrum_cmd spectrum;
3246 struct iwl3945_rx_packet *res;
3247 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
3248 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3249 .data = (void *)&spectrum,
3250 .meta.flags = CMD_WANT_SKB,
3251 };
3252 u32 add_time = le64_to_cpu(params->start_time);
3253 int rc;
3254 int spectrum_resp_status;
3255 int duration = le16_to_cpu(params->duration);
3256
bb8c093b 3257 if (iwl3945_is_associated(priv))
b481de9c 3258 add_time =
bb8c093b 3259 iwl3945_usecs_to_beacons(
b481de9c
ZY
3260 le64_to_cpu(params->start_time) - priv->last_tsf,
3261 le16_to_cpu(priv->rxon_timing.beacon_interval));
3262
3263 memset(&spectrum, 0, sizeof(spectrum));
3264
3265 spectrum.channel_count = cpu_to_le16(1);
3266 spectrum.flags =
3267 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3268 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3269 cmd.len = sizeof(spectrum);
3270 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3271
bb8c093b 3272 if (iwl3945_is_associated(priv))
b481de9c 3273 spectrum.start_time =
bb8c093b 3274 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
3275 add_time,
3276 le16_to_cpu(priv->rxon_timing.beacon_interval));
3277 else
3278 spectrum.start_time = 0;
3279
3280 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3281 spectrum.channels[0].channel = params->channel;
3282 spectrum.channels[0].type = type;
3283 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3284 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3285 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3286
bb8c093b 3287 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3288 if (rc)
3289 return rc;
3290
bb8c093b 3291 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
3292 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3293 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3294 rc = -EIO;
3295 }
3296
3297 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3298 switch (spectrum_resp_status) {
3299 case 0: /* Command will be handled */
3300 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS
3301 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3302 res->u.spectrum.id);
b481de9c
ZY
3303 priv->measurement_status &= ~MEASUREMENT_READY;
3304 }
3305 priv->measurement_status |= MEASUREMENT_ACTIVE;
3306 rc = 0;
3307 break;
3308
3309 case 1: /* Command will not be handled */
3310 rc = -EAGAIN;
3311 break;
3312 }
3313
3314 dev_kfree_skb_any(cmd.meta.u.skb);
3315
3316 return rc;
3317}
3318#endif
3319
bb8c093b
CH
3320static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
3321 struct iwl3945_tx_info *tx_sta)
b481de9c
ZY
3322{
3323
3324 tx_sta->status.ack_signal = 0;
3325 tx_sta->status.excessive_retries = 0;
3326 tx_sta->status.queue_length = 0;
3327 tx_sta->status.queue_number = 0;
3328
3329 if (in_interrupt())
3330 ieee80211_tx_status_irqsafe(priv->hw,
3331 tx_sta->skb[0], &(tx_sta->status));
3332 else
3333 ieee80211_tx_status(priv->hw,
3334 tx_sta->skb[0], &(tx_sta->status));
3335
3336 tx_sta->skb[0] = NULL;
3337}
3338
3339/**
6440adb5 3340 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 3341 *
6440adb5
BC
3342 * When FW advances 'R' index, all entries between old and new 'R' index
3343 * need to be reclaimed. As result, some free space forms. If there is
3344 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 3345 */
bb8c093b 3346static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
b481de9c 3347{
bb8c093b
CH
3348 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3349 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY
3350 int nfreed = 0;
3351
3352 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
3353 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3354 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 3355 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY
3356 return 0;
3357 }
3358
bb8c093b 3359 for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
fc4b6853 3360 q->read_ptr != index;
bb8c093b 3361 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 3362 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 3363 iwl3945_txstatus_to_ieee(priv,
fc4b6853 3364 &(txq->txb[txq->q.read_ptr]));
bb8c093b 3365 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c
ZY
3366 } else if (nfreed > 1) {
3367 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 3368 q->write_ptr, q->read_ptr);
b481de9c
ZY
3369 queue_work(priv->workqueue, &priv->restart);
3370 }
3371 nfreed++;
3372 }
3373
bb8c093b 3374 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY
3375 (txq_id != IWL_CMD_QUEUE_NUM) &&
3376 priv->mac80211_registered)
3377 ieee80211_wake_queue(priv->hw, txq_id);
3378
3379
3380 return nfreed;
3381}
3382
bb8c093b 3383static int iwl3945_is_tx_success(u32 status)
b481de9c
ZY
3384{
3385 return (status & 0xFF) == 0x1;
3386}
3387
3388/******************************************************************************
3389 *
3390 * Generic RX handler implementations
3391 *
3392 ******************************************************************************/
6440adb5
BC
3393/**
3394 * iwl3945_rx_reply_tx - Handle Tx response
3395 */
bb8c093b
CH
3396static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
3397 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3398{
bb8c093b 3399 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3400 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3401 int txq_id = SEQ_TO_QUEUE(sequence);
3402 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3403 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3404 struct ieee80211_tx_status *tx_status;
bb8c093b 3405 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c
ZY
3406 u32 status = le32_to_cpu(tx_resp->status);
3407
3408 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3409 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3410 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW
3411 index, txq->q.n_bd, txq->q.write_ptr,
3412 txq->q.read_ptr);
b481de9c
ZY
3413 return;
3414 }
3415
fc4b6853 3416 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY
3417
3418 tx_status->retry_count = tx_resp->failure_frame;
3419 tx_status->queue_number = status;
3420 tx_status->queue_length = tx_resp->bt_kill_count;
3421 tx_status->queue_length |= tx_resp->failure_rts;
3422
3423 tx_status->flags =
bb8c093b 3424 iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
b481de9c 3425
b481de9c 3426 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
bb8c093b 3427 txq_id, iwl3945_get_tx_fail_reason(status), status,
b481de9c
ZY
3428 tx_resp->rate, tx_resp->failure_frame);
3429
3430 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3431 if (index != -1)
bb8c093b 3432 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3433
3434 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3435 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3436}
3437
3438
bb8c093b
CH
3439static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3440 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3441{
bb8c093b
CH
3442 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3443 struct iwl3945_alive_resp *palive;
b481de9c
ZY
3444 struct delayed_work *pwork;
3445
3446 palive = &pkt->u.alive_frame;
3447
3448 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3449 "0x%01X 0x%01X\n",
3450 palive->is_valid, palive->ver_type,
3451 palive->ver_subtype);
3452
3453 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3454 IWL_DEBUG_INFO("Initialization Alive received.\n");
3455 memcpy(&priv->card_alive_init,
3456 &pkt->u.alive_frame,
bb8c093b 3457 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY
3458 pwork = &priv->init_alive_start;
3459 } else {
3460 IWL_DEBUG_INFO("Runtime Alive received.\n");
3461 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3462 sizeof(struct iwl3945_alive_resp));
b481de9c 3463 pwork = &priv->alive_start;
bb8c093b 3464 iwl3945_disable_events(priv);
b481de9c
ZY
3465 }
3466
3467 /* We delay the ALIVE response by 5ms to
3468 * give the HW RF Kill time to activate... */
3469 if (palive->is_valid == UCODE_VALID_OK)
3470 queue_delayed_work(priv->workqueue, pwork,
3471 msecs_to_jiffies(5));
3472 else
3473 IWL_WARNING("uCode did not respond OK.\n");
3474}
3475
bb8c093b
CH
3476static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3477 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3478{
bb8c093b 3479 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3480
3481 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3482 return;
3483}
3484
bb8c093b
CH
3485static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3486 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3487{
bb8c093b 3488 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3489
3490 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3491 "seq 0x%04X ser 0x%08X\n",
3492 le32_to_cpu(pkt->u.err_resp.error_type),
3493 get_cmd_string(pkt->u.err_resp.cmd_id),
3494 pkt->u.err_resp.cmd_id,
3495 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3496 le32_to_cpu(pkt->u.err_resp.error_info));
3497}
3498
3499#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3500
bb8c093b 3501static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3502{
bb8c093b
CH
3503 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3504 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3505 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY
3506 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3507 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3508 rxon->channel = csa->channel;
3509 priv->staging_rxon.channel = csa->channel;
3510}
3511
bb8c093b
CH
3512static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3513 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3514{
c8b0e6e1 3515#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH
3516 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3517 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY
3518
3519 if (!report->state) {
3520 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3521 "Spectrum Measure Notification: Start\n");
3522 return;
3523 }
3524
3525 memcpy(&priv->measure_report, report, sizeof(*report));
3526 priv->measurement_status |= MEASUREMENT_READY;
3527#endif
3528}
3529
bb8c093b
CH
3530static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3531 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3532{
c8b0e6e1 3533#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
3534 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3535 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY
3536 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3537 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3538#endif
3539}
3540
bb8c093b
CH
3541static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3542 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3543{
bb8c093b 3544 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3545 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3546 "notification for %s:\n",
3547 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3548 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY
3549}
3550
bb8c093b 3551static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3552{
bb8c093b
CH
3553 struct iwl3945_priv *priv =
3554 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY
3555 struct sk_buff *beacon;
3556
3557 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3558 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY
3559
3560 if (!beacon) {
3561 IWL_ERROR("update beacon failed\n");
3562 return;
3563 }
3564
3565 mutex_lock(&priv->mutex);
3566 /* new beacon skb is allocated every time; dispose previous.*/
3567 if (priv->ibss_beacon)
3568 dev_kfree_skb(priv->ibss_beacon);
3569
3570 priv->ibss_beacon = beacon;
3571 mutex_unlock(&priv->mutex);
3572
bb8c093b 3573 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3574}
3575
bb8c093b
CH
3576static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3577 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3578{
c8b0e6e1 3579#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
3580 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3581 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
3582 u8 rate = beacon->beacon_notify_hdr.rate;
3583
3584 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3585 "tsf %d %d rate %d\n",
3586 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3587 beacon->beacon_notify_hdr.failure_frame,
3588 le32_to_cpu(beacon->ibss_mgr_status),
3589 le32_to_cpu(beacon->high_tsf),
3590 le32_to_cpu(beacon->low_tsf), rate);
3591#endif
3592
3593 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3594 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3595 queue_work(priv->workqueue, &priv->beacon_update);
3596}
3597
3598/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH
3599static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3600 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3601{
c8b0e6e1 3602#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
3603 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3604 struct iwl3945_scanreq_notification *notif =
3605 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY
3606
3607 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3608#endif
3609}
3610
3611/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH
3612static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3613 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3614{
bb8c093b
CH
3615 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3616 struct iwl3945_scanstart_notification *notif =
3617 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY
3618 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3619 IWL_DEBUG_SCAN("Scan start: "
3620 "%d [802.11%s] "
3621 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3622 notif->channel,
3623 notif->band ? "bg" : "a",
3624 notif->tsf_high,
3625 notif->tsf_low, notif->status, notif->beacon_timer);
3626}
3627
3628/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH
3629static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3630 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3631{
bb8c093b
CH
3632 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3633 struct iwl3945_scanresults_notification *notif =
3634 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY
3635
3636 IWL_DEBUG_SCAN("Scan ch.res: "
3637 "%d [802.11%s] "
3638 "(TSF: 0x%08X:%08X) - %d "
3639 "elapsed=%lu usec (%dms since last)\n",
3640 notif->channel,
3641 notif->band ? "bg" : "a",
3642 le32_to_cpu(notif->tsf_high),
3643 le32_to_cpu(notif->tsf_low),
3644 le32_to_cpu(notif->statistics[0]),
3645 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3646 jiffies_to_msecs(elapsed_jiffies
3647 (priv->last_scan_jiffies, jiffies)));
3648
3649 priv->last_scan_jiffies = jiffies;
7878a5a4 3650 priv->next_scan_jiffies = 0;
b481de9c
ZY
3651}
3652
3653/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH
3654static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3655 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3656{
bb8c093b
CH
3657 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3658 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY
3659
3660 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3661 scan_notif->scanned_channels,
3662 scan_notif->tsf_low,
3663 scan_notif->tsf_high, scan_notif->status);
3664
3665 /* The HW is no longer scanning */
3666 clear_bit(STATUS_SCAN_HW, &priv->status);
3667
3668 /* The scan completion notification came in, so kill that timer... */
3669 cancel_delayed_work(&priv->scan_check);
3670
3671 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3672 (priv->scan_bands == 2) ? "2.4" : "5.2",
3673 jiffies_to_msecs(elapsed_jiffies
3674 (priv->scan_pass_start, jiffies)));
3675
3676 /* Remove this scanned band from the list
3677 * of pending bands to scan */
3678 priv->scan_bands--;
3679
3680 /* If a request to abort was given, or the scan did not succeed
3681 * then we reset the scan state machine and terminate,
3682 * re-queuing another scan if one has been requested */
3683 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3684 IWL_DEBUG_INFO("Aborted scan completed.\n");
3685 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3686 } else {
3687 /* If there are more bands on this scan pass reschedule */
3688 if (priv->scan_bands > 0)
3689 goto reschedule;
3690 }
3691
3692 priv->last_scan_jiffies = jiffies;
7878a5a4 3693 priv->next_scan_jiffies = 0;
b481de9c
ZY
3694 IWL_DEBUG_INFO("Setting scan to off\n");
3695
3696 clear_bit(STATUS_SCANNING, &priv->status);
3697
3698 IWL_DEBUG_INFO("Scan took %dms\n",
3699 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3700
3701 queue_work(priv->workqueue, &priv->scan_completed);
3702
3703 return;
3704
3705reschedule:
3706 priv->scan_pass_start = jiffies;
3707 queue_work(priv->workqueue, &priv->request_scan);
3708}
3709
3710/* Handle notification from uCode that card's power state is changing
3711 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH
3712static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3713 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3714{
bb8c093b 3715 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3716 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3717 unsigned long status = priv->status;
3718
3719 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3720 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3721 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3722
bb8c093b 3723 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3724 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3725
3726 if (flags & HW_CARD_DISABLED)
3727 set_bit(STATUS_RF_KILL_HW, &priv->status);
3728 else
3729 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3730
3731
3732 if (flags & SW_CARD_DISABLED)
3733 set_bit(STATUS_RF_KILL_SW, &priv->status);
3734 else
3735 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3736
bb8c093b 3737 iwl3945_scan_cancel(priv);
b481de9c
ZY
3738
3739 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3740 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3741 (test_bit(STATUS_RF_KILL_SW, &status) !=
3742 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3743 queue_work(priv->workqueue, &priv->rf_kill);
3744 else
3745 wake_up_interruptible(&priv->wait_command_queue);
3746}
3747
3748/**
bb8c093b 3749 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
3750 *
3751 * Setup the RX handlers for each of the reply types sent from the uCode
3752 * to the host.
3753 *
3754 * This function chains into the hardware specific files for them to setup
3755 * any hardware specific handlers as well.
3756 */
bb8c093b 3757static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3758{
bb8c093b
CH
3759 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3760 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3761 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3762 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3763 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH
3764 iwl3945_rx_spectrum_measure_notif;
3765 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3766 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH
3767 iwl3945_rx_pm_debug_statistics_notif;
3768 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3769
9fbab516
BC
3770 /*
3771 * The same handler is used for both the REPLY to a discrete
3772 * statistics request from the host as well as for the periodic
3773 * statistics notifications (after received beacons) from the uCode.
b481de9c 3774 */
bb8c093b
CH
3775 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3776 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3777
bb8c093b
CH
3778 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3779 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3780 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3781 iwl3945_rx_scan_results_notif;
b481de9c 3782 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH
3783 iwl3945_rx_scan_complete_notif;
3784 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
3785 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c 3786
9fbab516 3787 /* Set up hardware specific Rx handlers */
bb8c093b 3788 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
3789}
3790
3791/**
bb8c093b 3792 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY
3793 * @rxb: Rx buffer to reclaim
3794 *
3795 * If an Rx buffer has an async callback associated with it the callback
3796 * will be executed. The attached skb (if present) will only be freed
3797 * if the callback returns 1
3798 */
bb8c093b
CH
3799static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3800 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3801{
bb8c093b 3802 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY
3803 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3804 int txq_id = SEQ_TO_QUEUE(sequence);
3805 int index = SEQ_TO_INDEX(sequence);
3806 int huge = sequence & SEQ_HUGE_FRAME;
3807 int cmd_index;
bb8c093b 3808 struct iwl3945_cmd *cmd;
b481de9c
ZY
3809
3810 /* If a Tx command is being handled and it isn't in the actual
3811 * command queue then there a command routing bug has been introduced
3812 * in the queue management code. */
3813 if (txq_id != IWL_CMD_QUEUE_NUM)
3814 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
3815 txq_id, pkt->hdr.cmd);
3816 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3817
3818 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3819 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3820
3821 /* Input error checking is done when commands are added to queue. */
3822 if (cmd->meta.flags & CMD_WANT_SKB) {
3823 cmd->meta.source->u.skb = rxb->skb;
3824 rxb->skb = NULL;
3825 } else if (cmd->meta.u.callback &&
3826 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3827 rxb->skb = NULL;
3828
bb8c093b 3829 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3830
3831 if (!(cmd->meta.flags & CMD_ASYNC)) {
3832 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3833 wake_up_interruptible(&priv->wait_command_queue);
3834 }
3835}
3836
3837/************************** RX-FUNCTIONS ****************************/
3838/*
3839 * Rx theory of operation
3840 *
3841 * The host allocates 32 DMA target addresses and passes the host address
3842 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3843 * 0 to 31
3844 *
3845 * Rx Queue Indexes
3846 * The host/firmware share two index registers for managing the Rx buffers.
3847 *
3848 * The READ index maps to the first position that the firmware may be writing
3849 * to -- the driver can read up to (but not including) this position and get
3850 * good data.
3851 * The READ index is managed by the firmware once the card is enabled.
3852 *
3853 * The WRITE index maps to the last position the driver has read from -- the
3854 * position preceding WRITE is the last slot the firmware can place a packet.
3855 *
3856 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3857 * WRITE = READ.
3858 *
9fbab516 3859 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
3860 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3861 *
9fbab516 3862 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
3863 * and fire the RX interrupt. The driver can then query the READ index and
3864 * process as many packets as possible, moving the WRITE index forward as it
3865 * resets the Rx queue buffers with new memory.
3866 *
3867 * The management in the driver is as follows:
3868 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3869 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3870 * to replenish the iwl->rxq->rx_free.
bb8c093b 3871 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
3872 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3873 * 'processed' and 'read' driver indexes as well)
3874 * + A received packet is processed and handed to the kernel network stack,
3875 * detached from the iwl->rxq. The driver 'processed' index is updated.
3876 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3877 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3878 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3879 * were enough free buffers and RX_STALLED is set it is cleared.
3880 *
3881 *
3882 * Driver sequence:
3883 *
9fbab516
BC
3884 * iwl3945_rx_queue_alloc() Allocates rx_free
3885 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3886 * iwl3945_rx_queue_restock
9fbab516 3887 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
3888 * queue, updates firmware pointers, and updates
3889 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3890 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
3891 *
3892 * -- enable interrupts --
9fbab516 3893 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY
3894 * READ INDEX, detaching the SKB from the pool.
3895 * Moves the packet buffer from queue to rx_used.
bb8c093b 3896 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
3897 * slots.
3898 * ...
3899 *
3900 */
3901
3902/**
bb8c093b 3903 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3904 */
bb8c093b 3905static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY
3906{
3907 int s = q->read - q->write;
3908 if (s <= 0)
3909 s += RX_QUEUE_SIZE;
3910 /* keep some buffer to not confuse full and empty queue */
3911 s -= 2;
3912 if (s < 0)
3913 s = 0;
3914 return s;
3915}
3916
3917/**
bb8c093b 3918 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3919 */
bb8c093b 3920int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY
3921{
3922 u32 reg = 0;
3923 int rc = 0;
3924 unsigned long flags;
3925
3926 spin_lock_irqsave(&q->lock, flags);
3927
3928 if (q->need_update == 0)
3929 goto exit_unlock;
3930
6440adb5 3931 /* If power-saving is in use, make sure device is awake */
b481de9c 3932 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3933 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3934
3935 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3936 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3937 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3938 goto exit_unlock;
3939 }
3940
bb8c093b 3941 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
3942 if (rc)
3943 goto exit_unlock;
3944
6440adb5 3945 /* Device expects a multiple of 8 */
bb8c093b 3946 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3947 q->write & ~0x7);
bb8c093b 3948 iwl3945_release_nic_access(priv);
6440adb5
BC
3949
3950 /* Else device is assumed to be awake */
b481de9c 3951 } else
6440adb5 3952 /* Device expects a multiple of 8 */
bb8c093b 3953 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY
3954
3955
3956 q->need_update = 0;
3957
3958 exit_unlock:
3959 spin_unlock_irqrestore(&q->lock, flags);
3960 return rc;
3961}
3962
3963/**
9fbab516 3964 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3965 */
bb8c093b 3966static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY
3967 dma_addr_t dma_addr)
3968{
3969 return cpu_to_le32((u32)dma_addr);
3970}
3971
3972/**
bb8c093b 3973 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3974 *
9fbab516 3975 * If there are slots in the RX queue that need to be restocked,
b481de9c 3976 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3977 * as we can, pulling from rx_free.
b481de9c
ZY
3978 *
3979 * This moves the 'write' index forward to catch up with 'processed', and
3980 * also updates the memory address in the firmware to reference the new
3981 * target buffer.
3982 */
bb8c093b 3983static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3984{
bb8c093b 3985 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3986 struct list_head *element;
bb8c093b 3987 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY
3988 unsigned long flags;
3989 int write, rc;
3990
3991 spin_lock_irqsave(&rxq->lock, flags);
3992 write = rxq->write & ~0x7;
bb8c093b 3993 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3994 /* Get next free Rx buffer, remove from free list */
b481de9c 3995 element = rxq->rx_free.next;
bb8c093b 3996 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3997 list_del(element);
6440adb5
BC
3998
3999 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 4000 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY
4001 rxq->queue[rxq->write] = rxb;
4002 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
4003 rxq->free_count--;
4004 }
4005 spin_unlock_irqrestore(&rxq->lock, flags);
4006 /* If the pre-allocated buffer pool is dropping low, schedule to
4007 * refill it */
4008 if (rxq->free_count <= RX_LOW_WATERMARK)
4009 queue_work(priv->workqueue, &priv->rx_replenish);
4010
4011
6440adb5
BC
4012 /* If we've added more space for the firmware to place data, tell it.
4013 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
4014 if ((write != (rxq->write & ~0x7))
4015 || (abs(rxq->write - rxq->read) > 7)) {
4016 spin_lock_irqsave(&rxq->lock, flags);
4017 rxq->need_update = 1;
4018 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 4019 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
4020 if (rc)
4021 return rc;
4022 }
4023
4024 return 0;
4025}
4026
4027/**
bb8c093b 4028 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
4029 *
4030 * When moving to rx_free an SKB is allocated for the slot.
4031 *
bb8c093b 4032 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 4033 * This is called as a scheduled work item (except for during initialization)
b481de9c 4034 */
5c0eef96 4035static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 4036{
bb8c093b 4037 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 4038 struct list_head *element;
bb8c093b 4039 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY
4040 unsigned long flags;
4041 spin_lock_irqsave(&rxq->lock, flags);
4042 while (!list_empty(&rxq->rx_used)) {
4043 element = rxq->rx_used.next;
bb8c093b 4044 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
BC
4045
4046 /* Alloc a new receive buffer */
b481de9c
ZY
4047 rxb->skb =
4048 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
4049 if (!rxb->skb) {
4050 if (net_ratelimit())
4051 printk(KERN_CRIT DRV_NAME
4052 ": Can not allocate SKB buffers\n");
4053 /* We don't reschedule replenish work here -- we will
4054 * call the restock method and if it still needs
4055 * more buffers it will schedule replenish */
4056 break;
4057 }
12342c47
ZY
4058
4059 /* If radiotap head is required, reserve some headroom here.
4060 * The physical head count is a variable rx_stats->phy_count.
4061 * We reserve 4 bytes here. Plus these extra bytes, the
4062 * headroom of the physical head should be enough for the
4063 * radiotap head that iwl3945 supported. See iwl3945_rt.
4064 */
4065 skb_reserve(rxb->skb, 4);
4066
b481de9c
ZY
4067 priv->alloc_rxb_skb++;
4068 list_del(element);
6440adb5
BC
4069
4070 /* Get physical address of RB/SKB */
b481de9c
ZY
4071 rxb->dma_addr =
4072 pci_map_single(priv->pci_dev, rxb->skb->data,
4073 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4074 list_add_tail(&rxb->list, &rxq->rx_free);
4075 rxq->free_count++;
4076 }
4077 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA
4078}
4079
4080/*
4081 * this should be called while priv->lock is locked
4082 */
4fd1f841 4083static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA
4084{
4085 struct iwl3945_priv *priv = data;
4086
4087 iwl3945_rx_allocate(priv);
4088 iwl3945_rx_queue_restock(priv);
4089}
4090
4091
4092void iwl3945_rx_replenish(void *data)
4093{
4094 struct iwl3945_priv *priv = data;
4095 unsigned long flags;
4096
4097 iwl3945_rx_allocate(priv);
b481de9c
ZY
4098
4099 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4100 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
4101 spin_unlock_irqrestore(&priv->lock, flags);
4102}
4103
4104/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 4105 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY
4106 * This free routine walks the list of POOL entries and if SKB is set to
4107 * non NULL it is unmapped and freed
4108 */
bb8c093b 4109static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY
4110{
4111 int i;
4112 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
4113 if (rxq->pool[i].skb != NULL) {
4114 pci_unmap_single(priv->pci_dev,
4115 rxq->pool[i].dma_addr,
4116 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4117 dev_kfree_skb(rxq->pool[i].skb);
4118 }
4119 }
4120
4121 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4122 rxq->dma_addr);
4123 rxq->bd = NULL;
4124}
4125
bb8c093b 4126int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 4127{
bb8c093b 4128 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
4129 struct pci_dev *dev = priv->pci_dev;
4130 int i;
4131
4132 spin_lock_init(&rxq->lock);
4133 INIT_LIST_HEAD(&rxq->rx_free);
4134 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
BC
4135
4136 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY
4137 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
4138 if (!rxq->bd)
4139 return -ENOMEM;
6440adb5 4140
b481de9c
ZY
4141 /* Fill the rx_used queue with _all_ of the Rx buffers */
4142 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
4143 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 4144
b481de9c
ZY
4145 /* Set us so that we have processed and used all buffers, but have
4146 * not restocked the Rx queue with fresh buffers */
4147 rxq->read = rxq->write = 0;
4148 rxq->free_count = 0;
4149 rxq->need_update = 0;
4150 return 0;
4151}
4152
bb8c093b 4153void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY
4154{
4155 unsigned long flags;
4156 int i;
4157 spin_lock_irqsave(&rxq->lock, flags);
4158 INIT_LIST_HEAD(&rxq->rx_free);
4159 INIT_LIST_HEAD(&rxq->rx_used);
4160 /* Fill the rx_used queue with _all_ of the Rx buffers */
4161 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
4162 /* In the reset function, these buffers may have been allocated
4163 * to an SKB, so we need to unmap and free potential storage */
4164 if (rxq->pool[i].skb != NULL) {
4165 pci_unmap_single(priv->pci_dev,
4166 rxq->pool[i].dma_addr,
4167 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4168 priv->alloc_rxb_skb--;
4169 dev_kfree_skb(rxq->pool[i].skb);
4170 rxq->pool[i].skb = NULL;
4171 }
4172 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4173 }
4174
4175 /* Set us so that we have processed and used all buffers, but have
4176 * not restocked the Rx queue with fresh buffers */
4177 rxq->read = rxq->write = 0;
4178 rxq->free_count = 0;
4179 spin_unlock_irqrestore(&rxq->lock, flags);
4180}
4181
4182/* Convert linear signal-to-noise ratio into dB */
4183static u8 ratio2dB[100] = {
4184/* 0 1 2 3 4 5 6 7 8 9 */
4185 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4186 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4187 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4188 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4189 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4190 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4191 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4192 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4193 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4194 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4195};
4196
4197/* Calculates a relative dB value from a ratio of linear
4198 * (i.e. not dB) signal levels.
4199 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4200int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 4201{
221c80cf
AB
4202 /* 1000:1 or higher just report as 60 dB */
4203 if (sig_ratio >= 1000)
b481de9c
ZY
4204 return 60;
4205
221c80cf 4206 /* 100:1 or higher, divide by 10 and use table,
b481de9c 4207 * add 20 dB to make up for divide by 10 */
221c80cf 4208 if (sig_ratio >= 100)
b481de9c
ZY
4209 return (20 + (int)ratio2dB[sig_ratio/10]);
4210
4211 /* We shouldn't see this */
4212 if (sig_ratio < 1)
4213 return 0;
4214
4215 /* Use table for ratios 1:1 - 99:1 */
4216 return (int)ratio2dB[sig_ratio];
4217}
4218
4219#define PERFECT_RSSI (-20) /* dBm */
4220#define WORST_RSSI (-95) /* dBm */
4221#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4222
4223/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4224 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4225 * about formulas used below. */
bb8c093b 4226int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
4227{
4228 int sig_qual;
4229 int degradation = PERFECT_RSSI - rssi_dbm;
4230
4231 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4232 * as indicator; formula is (signal dbm - noise dbm).
4233 * SNR at or above 40 is a great signal (100%).
4234 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4235 * Weakest usable signal is usually 10 - 15 dB SNR. */
4236 if (noise_dbm) {
4237 if (rssi_dbm - noise_dbm >= 40)
4238 return 100;
4239 else if (rssi_dbm < noise_dbm)
4240 return 0;
4241 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4242
4243 /* Else use just the signal level.
4244 * This formula is a least squares fit of data points collected and
4245 * compared with a reference system that had a percentage (%) display
4246 * for signal quality. */
4247 } else
4248 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4249 (15 * RSSI_RANGE + 62 * degradation)) /
4250 (RSSI_RANGE * RSSI_RANGE);
4251
4252 if (sig_qual > 100)
4253 sig_qual = 100;
4254 else if (sig_qual < 1)
4255 sig_qual = 0;
4256
4257 return sig_qual;
4258}
4259
4260/**
9fbab516 4261 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
4262 *
4263 * Uses the priv->rx_handlers callback function array to invoke
4264 * the appropriate handlers, including command responses,
4265 * frame-received notifications, and other notifications.
4266 */
bb8c093b 4267static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 4268{
bb8c093b
CH
4269 struct iwl3945_rx_mem_buffer *rxb;
4270 struct iwl3945_rx_packet *pkt;
4271 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
4272 u32 r, i;
4273 int reclaim;
4274 unsigned long flags;
5c0eef96 4275 u8 fill_rx = 0;
d68ab680 4276 u32 count = 8;
b481de9c 4277
6440adb5
BC
4278 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4279 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4280 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY
4281 i = rxq->read;
4282
5c0eef96
MA
4283 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4284 fill_rx = 1;
b481de9c
ZY
4285 /* Rx interrupt, but nothing sent from uCode */
4286 if (i == r)
4287 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4288
4289 while (i != r) {
4290 rxb = rxq->queue[i];
4291
9fbab516 4292 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
4293 * then a bug has been introduced in the queue refilling
4294 * routines -- catch it here */
4295 BUG_ON(rxb == NULL);
4296
4297 rxq->queue[i] = NULL;
4298
4299 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4300 IWL_RX_BUF_SIZE,
4301 PCI_DMA_FROMDEVICE);
bb8c093b 4302 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY
4303
4304 /* Reclaim a command buffer only if this packet is a response
4305 * to a (driver-originated) command.
4306 * If the packet (e.g. Rx frame) originated from uCode,
4307 * there is no command buffer to reclaim.
4308 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4309 * but apparently a few don't get set; catch them here. */
4310 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4311 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4312 (pkt->hdr.cmd != REPLY_TX);
4313
4314 /* Based on type of command response or notification,
4315 * handle those that need handling via function in
bb8c093b 4316 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY
4317 if (priv->rx_handlers[pkt->hdr.cmd]) {
4318 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4319 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4320 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4321 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4322 } else {
4323 /* No handling needed */
4324 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4325 "r %d i %d No handler needed for %s, 0x%02x\n",
4326 r, i, get_cmd_string(pkt->hdr.cmd),
4327 pkt->hdr.cmd);
4328 }
4329
4330 if (reclaim) {
9fbab516
BC
4331 /* Invoke any callbacks, transfer the skb to caller, and
4332 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY
4333 * as we reclaim the driver command queue */
4334 if (rxb && rxb->skb)
bb8c093b 4335 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY
4336 else
4337 IWL_WARNING("Claim null rxb?\n");
4338 }
4339
4340 /* For now we just don't re-use anything. We can tweak this
4341 * later to try and re-use notification packets and SKBs that
4342 * fail to Rx correctly */
4343 if (rxb->skb != NULL) {
4344 priv->alloc_rxb_skb--;
4345 dev_kfree_skb_any(rxb->skb);
4346 rxb->skb = NULL;
4347 }
4348
4349 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4350 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4351 spin_lock_irqsave(&rxq->lock, flags);
4352 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4353 spin_unlock_irqrestore(&rxq->lock, flags);
4354 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
4355 /* If there are a lot of unused frames,
4356 * restock the Rx queue so ucode won't assert. */
4357 if (fill_rx) {
4358 count++;
4359 if (count >= 8) {
4360 priv->rxq.read = i;
4361 __iwl3945_rx_replenish(priv);
4362 count = 0;
4363 }
4364 }
b481de9c
ZY
4365 }
4366
4367 /* Backtrack one entry */
4368 priv->rxq.read = i;
bb8c093b 4369 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
4370}
4371
6440adb5
BC
4372/**
4373 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4374 */
bb8c093b
CH
4375static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4376 struct iwl3945_tx_queue *txq)
b481de9c
ZY
4377{
4378 u32 reg = 0;
4379 int rc = 0;
4380 int txq_id = txq->q.id;
4381
4382 if (txq->need_update == 0)
4383 return rc;
4384
4385 /* if we're trying to save power */
4386 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4387 /* wake up nic if it's powered down ...
4388 * uCode will wake up, and interrupt us again, so next
4389 * time we'll skip this part. */
bb8c093b 4390 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
4391
4392 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4393 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4394 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
4395 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4396 return rc;
4397 }
4398
4399 /* restore this queue's parameters in nic hardware. */
bb8c093b 4400 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4401 if (rc)
4402 return rc;
bb8c093b 4403 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4404 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4405 iwl3945_release_nic_access(priv);
b481de9c
ZY
4406
4407 /* else not in power-save mode, uCode will never sleep when we're
4408 * trying to tx (during RFKILL, we're not trying to tx). */
4409 } else
bb8c093b 4410 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4411 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY
4412
4413 txq->need_update = 0;
4414
4415 return rc;
4416}
4417
c8b0e6e1 4418#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4419static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4420{
0795af57
JP
4421 DECLARE_MAC_BUF(mac);
4422
b481de9c 4423 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4424 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY
4425 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4426 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4427 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4428 le32_to_cpu(rxon->filter_flags));
4429 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4430 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4431 rxon->ofdm_basic_rates);
4432 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP
4433 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4434 print_mac(mac, rxon->node_addr));
4435 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4436 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY
4437 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4438}
4439#endif
4440
bb8c093b 4441static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY
4442{
4443 IWL_DEBUG_ISR("Enabling interrupts\n");
4444 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4445 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY
4446}
4447
bb8c093b 4448static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY
4449{
4450 clear_bit(STATUS_INT_ENABLED, &priv->status);
4451
4452 /* disable interrupts from uCode/NIC to host */
bb8c093b 4453 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4454
4455 /* acknowledge/clear/reset any interrupts still pending
4456 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH
4457 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4458 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY
4459 IWL_DEBUG_ISR("Disabled interrupts\n");
4460}
4461
4462static const char *desc_lookup(int i)
4463{
4464 switch (i) {
4465 case 1:
4466 return "FAIL";
4467 case 2:
4468 return "BAD_PARAM";
4469 case 3:
4470 return "BAD_CHECKSUM";
4471 case 4:
4472 return "NMI_INTERRUPT";
4473 case 5:
4474 return "SYSASSERT";
4475 case 6:
4476 return "FATAL_ERROR";
4477 }
4478
4479 return "UNKNOWN";
4480}
4481
4482#define ERROR_START_OFFSET (1 * sizeof(u32))
4483#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4484
bb8c093b 4485static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY
4486{
4487 u32 i;
4488 u32 desc, time, count, base, data1;
4489 u32 blink1, blink2, ilink1, ilink2;
4490 int rc;
4491
4492 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4493
bb8c093b 4494 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4495 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4496 return;
4497 }
4498
bb8c093b 4499 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4500 if (rc) {
4501 IWL_WARNING("Can not read from adapter at this time.\n");
4502 return;
4503 }
4504
bb8c093b 4505 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY
4506
4507 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4508 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4509 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY
4510 }
4511
4512 IWL_ERROR("Desc Time asrtPC blink2 "
4513 "ilink1 nmiPC Line\n");
4514 for (i = ERROR_START_OFFSET;
4515 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4516 i += ERROR_ELEM_SIZE) {
bb8c093b 4517 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4518 time =
bb8c093b 4519 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4520 blink1 =
bb8c093b 4521 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4522 blink2 =
bb8c093b 4523 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4524 ilink1 =
bb8c093b 4525 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4526 ilink2 =
bb8c093b 4527 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4528 data1 =
bb8c093b 4529 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY
4530
4531 IWL_ERROR
4532 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4533 desc_lookup(desc), desc, time, blink1, blink2,
4534 ilink1, ilink2, data1);
4535 }
4536
bb8c093b 4537 iwl3945_release_nic_access(priv);
b481de9c
ZY
4538
4539}
4540
f58177b9 4541#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
4542
4543/**
bb8c093b 4544 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4545 *
bb8c093b 4546 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4547 */
bb8c093b 4548static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY
4549 u32 num_events, u32 mode)
4550{
4551 u32 i;
4552 u32 base; /* SRAM byte address of event log header */
4553 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4554 u32 ptr; /* SRAM byte address of log data */
4555 u32 ev, time, data; /* event log data */
4556
4557 if (num_events == 0)
4558 return;
4559
4560 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4561
4562 if (mode == 0)
4563 event_size = 2 * sizeof(u32);
4564 else
4565 event_size = 3 * sizeof(u32);
4566
4567 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4568
4569 /* "time" is actually "data" for mode 0 (no timestamp).
4570 * place event id # at far right for easier visual parsing. */
4571 for (i = 0; i < num_events; i++) {
bb8c093b 4572 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4573 ptr += sizeof(u32);
bb8c093b 4574 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY
4575 ptr += sizeof(u32);
4576 if (mode == 0)
4577 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4578 else {
bb8c093b 4579 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY
4580 ptr += sizeof(u32);
4581 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4582 }
4583 }
4584}
4585
bb8c093b 4586static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY
4587{
4588 int rc;
4589 u32 base; /* SRAM byte address of event log header */
4590 u32 capacity; /* event log capacity in # entries */
4591 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4592 u32 num_wraps; /* # times uCode wrapped to top of log */
4593 u32 next_entry; /* index of next entry to be written by uCode */
4594 u32 size; /* # entries that we'll print */
4595
4596 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4597 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4598 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4599 return;
4600 }
4601
bb8c093b 4602 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4603 if (rc) {
4604 IWL_WARNING("Can not read from adapter at this time.\n");
4605 return;
4606 }
4607
4608 /* event log header */
bb8c093b
CH
4609 capacity = iwl3945_read_targ_mem(priv, base);
4610 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4611 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4612 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
4613
4614 size = num_wraps ? capacity : next_entry;
4615
4616 /* bail out if nothing in log */
4617 if (size == 0) {
583fab37 4618 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4619 iwl3945_release_nic_access(priv);
b481de9c
ZY
4620 return;
4621 }
4622
583fab37 4623 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
4624 size, num_wraps);
4625
4626 /* if uCode has wrapped back to top of log, start at the oldest entry,
4627 * i.e the next one that uCode would fill. */
4628 if (num_wraps)
bb8c093b 4629 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
4630 capacity - next_entry, mode);
4631
4632 /* (then/else) start at top of log */
bb8c093b 4633 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4634
bb8c093b 4635 iwl3945_release_nic_access(priv);
b481de9c
ZY
4636}
4637
4638/**
bb8c093b 4639 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4640 */
bb8c093b 4641static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4642{
bb8c093b 4643 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY
4644 set_bit(STATUS_FW_ERROR, &priv->status);
4645
4646 /* Cancel currently queued command. */
4647 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4648
c8b0e6e1 4649#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
4650 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4651 iwl3945_dump_nic_error_log(priv);
4652 iwl3945_dump_nic_event_log(priv);
4653 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY
4654 }
4655#endif
4656
4657 wake_up_interruptible(&priv->wait_command_queue);
4658
4659 /* Keep the restart process from trying to send host
4660 * commands by clearing the INIT status bit */
4661 clear_bit(STATUS_READY, &priv->status);
4662
4663 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4664 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4665 "Restarting adapter due to uCode error.\n");
4666
bb8c093b 4667 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
4668 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4669 sizeof(priv->recovery_rxon));
4670 priv->error_recovering = 1;
4671 }
4672 queue_work(priv->workqueue, &priv->restart);
4673 }
4674}
4675
bb8c093b 4676static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY
4677{
4678 unsigned long flags;
4679
4680 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4681 sizeof(priv->staging_rxon));
4682 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4683 iwl3945_commit_rxon(priv);
b481de9c 4684
bb8c093b 4685 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY
4686
4687 spin_lock_irqsave(&priv->lock, flags);
4688 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4689 priv->error_recovering = 0;
4690 spin_unlock_irqrestore(&priv->lock, flags);
4691}
4692
bb8c093b 4693static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY
4694{
4695 u32 inta, handled = 0;
4696 u32 inta_fh;
4697 unsigned long flags;
c8b0e6e1 4698#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
4699 u32 inta_mask;
4700#endif
4701
4702 spin_lock_irqsave(&priv->lock, flags);
4703
4704 /* Ack/clear/reset pending uCode interrupts.
4705 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4706 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH
4707 inta = iwl3945_read32(priv, CSR_INT);
4708 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY
4709
4710 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4711 * Any new interrupts that happen after this, either while we're
4712 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH
4713 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4714 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4715
c8b0e6e1 4716#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4717 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC
4718 /* just for debug */
4719 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY
4720 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4721 inta, inta_mask, inta_fh);
4722 }
4723#endif
4724
4725 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4726 * atomic, make sure that inta covers all the interrupts that
4727 * we've discovered, even if FH interrupt came in just after
4728 * reading CSR_INT. */
4729 if (inta_fh & CSR_FH_INT_RX_MASK)
4730 inta |= CSR_INT_BIT_FH_RX;
4731 if (inta_fh & CSR_FH_INT_TX_MASK)
4732 inta |= CSR_INT_BIT_FH_TX;
4733
4734 /* Now service all interrupt bits discovered above. */
4735 if (inta & CSR_INT_BIT_HW_ERR) {
4736 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4737
4738 /* Tell the device to stop sending interrupts */
bb8c093b 4739 iwl3945_disable_interrupts(priv);
b481de9c 4740
bb8c093b 4741 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4742
4743 handled |= CSR_INT_BIT_HW_ERR;
4744
4745 spin_unlock_irqrestore(&priv->lock, flags);
4746
4747 return;
4748 }
4749
c8b0e6e1 4750#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4751 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4752 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP
4753 if (inta & CSR_INT_BIT_SCD)
4754 IWL_DEBUG_ISR("Scheduler finished to transmit "
4755 "the frame/frames.\n");
b481de9c
ZY
4756
4757 /* Alive notification via Rx interrupt will do the real work */
4758 if (inta & CSR_INT_BIT_ALIVE)
4759 IWL_DEBUG_ISR("Alive interrupt\n");
4760 }
4761#endif
4762 /* Safely ignore these bits for debug checks below */
25c03d8e 4763 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY
4764
4765 /* HW RF KILL switch toggled (4965 only) */
4766 if (inta & CSR_INT_BIT_RF_KILL) {
4767 int hw_rf_kill = 0;
bb8c093b 4768 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
4769 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4770 hw_rf_kill = 1;
4771
4772 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4773 "RF_KILL bit toggled to %s.\n",
4774 hw_rf_kill ? "disable radio":"enable radio");
4775
4776 /* Queue restart only if RF_KILL switch was set to "kill"
4777 * when we loaded driver, and is now set to "enable".
4778 * After we're Alive, RF_KILL gets handled by
3230455d 4779 * iwl3945_rx_card_state_notif() */
53e49093
ZY
4780 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4781 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4782 queue_work(priv->workqueue, &priv->restart);
53e49093 4783 }
b481de9c
ZY
4784
4785 handled |= CSR_INT_BIT_RF_KILL;
4786 }
4787
4788 /* Chip got too hot and stopped itself (4965 only) */
4789 if (inta & CSR_INT_BIT_CT_KILL) {
4790 IWL_ERROR("Microcode CT kill error detected.\n");
4791 handled |= CSR_INT_BIT_CT_KILL;
4792 }
4793
4794 /* Error detected by uCode */
4795 if (inta & CSR_INT_BIT_SW_ERR) {
4796 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4797 inta);
bb8c093b 4798 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4799 handled |= CSR_INT_BIT_SW_ERR;
4800 }
4801
4802 /* uCode wakes up after power-down sleep */
4803 if (inta & CSR_INT_BIT_WAKEUP) {
4804 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH
4805 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4806 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4807 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4808 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4809 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4810 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4811 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
4812
4813 handled |= CSR_INT_BIT_WAKEUP;
4814 }
4815
4816 /* All uCode command responses, including Tx command responses,
4817 * Rx "responses" (frame-received notification), and other
4818 * notifications from uCode come through here*/
4819 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4820 iwl3945_rx_handle(priv);
b481de9c
ZY
4821 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4822 }
4823
4824 if (inta & CSR_INT_BIT_FH_TX) {
4825 IWL_DEBUG_ISR("Tx interrupt\n");
4826
bb8c093b
CH
4827 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4828 if (!iwl3945_grab_nic_access(priv)) {
4829 iwl3945_write_direct32(priv,
b481de9c
ZY
4830 FH_TCSR_CREDIT
4831 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4832 iwl3945_release_nic_access(priv);
b481de9c
ZY
4833 }
4834 handled |= CSR_INT_BIT_FH_TX;
4835 }
4836
4837 if (inta & ~handled)
4838 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4839
4840 if (inta & ~CSR_INI_SET_MASK) {
4841 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4842 inta & ~CSR_INI_SET_MASK);
4843 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4844 }
4845
4846 /* Re-enable all interrupts */
bb8c093b 4847 iwl3945_enable_interrupts(priv);
b481de9c 4848
c8b0e6e1 4849#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
4850 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4851 inta = iwl3945_read32(priv, CSR_INT);
4852 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4853 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4854 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4855 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4856 }
4857#endif
4858 spin_unlock_irqrestore(&priv->lock, flags);
4859}
4860
bb8c093b 4861static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4862{
bb8c093b 4863 struct iwl3945_priv *priv = data;
b481de9c
ZY
4864 u32 inta, inta_mask;
4865 u32 inta_fh;
4866 if (!priv)
4867 return IRQ_NONE;
4868
4869 spin_lock(&priv->lock);
4870
4871 /* Disable (but don't clear!) interrupts here to avoid
4872 * back-to-back ISRs and sporadic interrupts from our NIC.
4873 * If we have something to service, the tasklet will re-enable ints.
4874 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH
4875 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4876 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4877
4878 /* Discover which interrupts are active/pending */
bb8c093b
CH
4879 inta = iwl3945_read32(priv, CSR_INT);
4880 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4881
4882 /* Ignore interrupt if there's nothing in NIC to service.
4883 * This may be due to IRQ shared with another device,
4884 * or due to sporadic interrupts thrown from our NIC. */
4885 if (!inta && !inta_fh) {
4886 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4887 goto none;
4888 }
4889
4890 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4891 /* Hardware disappeared */
4892 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4893 goto unplugged;
b481de9c
ZY
4894 }
4895
4896 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4897 inta, inta_mask, inta_fh);
4898
25c03d8e
JP
4899 inta &= ~CSR_INT_BIT_SCD;
4900
bb8c093b 4901 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP
4902 if (likely(inta || inta_fh))
4903 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4904unplugged:
b481de9c
ZY
4905 spin_unlock(&priv->lock);
4906
4907 return IRQ_HANDLED;
4908
4909 none:
4910 /* re-enable interrupts here since we don't have anything to service. */
bb8c093b 4911 iwl3945_enable_interrupts(priv);
b481de9c
ZY
4912 spin_unlock(&priv->lock);
4913 return IRQ_NONE;
4914}
4915
4916/************************** EEPROM BANDS ****************************
4917 *
bb8c093b 4918 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY
4919 * EEPROM contents to the specific channel number supported for each
4920 * band.
4921 *
bb8c093b 4922 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY
4923 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4924 * The specific geography and calibration information for that channel
4925 * is contained in the eeprom map itself.
4926 *
4927 * During init, we copy the eeprom information and channel map
4928 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4929 *
4930 * channel_map_24/52 provides the index in the channel_info array for a
4931 * given channel. We have to have two separate maps as there is channel
4932 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4933 * band_2
4934 *
4935 * A value of 0xff stored in the channel_map indicates that the channel
4936 * is not supported by the hardware at all.
4937 *
4938 * A value of 0xfe in the channel_map indicates that the channel is not
4939 * valid for Tx with the current hardware. This means that
4940 * while the system can tune and receive on a given channel, it may not
4941 * be able to associate or transmit any frames on that
4942 * channel. There is no corresponding channel information for that
4943 * entry.
4944 *
4945 *********************************************************************/
4946
4947/* 2.4 GHz */
bb8c093b 4948static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY
4949 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4950};
4951
4952/* 5.2 GHz bands */
9fbab516 4953static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY
4954 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4955};
4956
9fbab516 4957static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY
4958 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4959};
4960
bb8c093b 4961static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY
4962 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4963};
4964
bb8c093b 4965static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY
4966 145, 149, 153, 157, 161, 165
4967};
4968
bb8c093b 4969static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4970 int *eeprom_ch_count,
bb8c093b 4971 const struct iwl3945_eeprom_channel
b481de9c
ZY
4972 **eeprom_ch_info,
4973 const u8 **eeprom_ch_index)
4974{
4975 switch (band) {
4976 case 1: /* 2.4GHz band */
bb8c093b 4977 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4978 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4979 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4980 break;
9fbab516 4981 case 2: /* 4.9GHz band */
bb8c093b 4982 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4983 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4984 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY
4985 break;
4986 case 3: /* 5.2GHz band */
bb8c093b 4987 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4988 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4989 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4990 break;
9fbab516 4991 case 4: /* 5.5GHz band */
bb8c093b 4992 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4993 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4994 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4995 break;
9fbab516 4996 case 5: /* 5.7GHz band */
bb8c093b 4997 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4998 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4999 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY
5000 break;
5001 default:
5002 BUG();
5003 return;
5004 }
5005}
5006
6440adb5
BC
5007/**
5008 * iwl3945_get_channel_info - Find driver's private channel info
5009 *
5010 * Based on band and channel number.
5011 */
bb8c093b 5012const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 5013 enum ieee80211_band band, u16 channel)
b481de9c
ZY
5014{
5015 int i;
5016
8318d78a
JB
5017 switch (band) {
5018 case IEEE80211_BAND_5GHZ:
b481de9c
ZY
5019 for (i = 14; i < priv->channel_count; i++) {
5020 if (priv->channel_info[i].channel == channel)
5021 return &priv->channel_info[i];
5022 }
5023 break;
5024
8318d78a 5025 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
5026 if (channel >= 1 && channel <= 14)
5027 return &priv->channel_info[channel - 1];
5028 break;
8318d78a
JB
5029 case IEEE80211_NUM_BANDS:
5030 WARN_ON(1);
b481de9c
ZY
5031 }
5032
5033 return NULL;
5034}
5035
5036#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
5037 ? # x " " : "")
5038
6440adb5
BC
5039/**
5040 * iwl3945_init_channel_map - Set up driver's info for all possible channels
5041 */
bb8c093b 5042static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY
5043{
5044 int eeprom_ch_count = 0;
5045 const u8 *eeprom_ch_index = NULL;
bb8c093b 5046 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 5047 int band, ch;
bb8c093b 5048 struct iwl3945_channel_info *ch_info;
b481de9c
ZY
5049
5050 if (priv->channel_count) {
5051 IWL_DEBUG_INFO("Channel map already initialized.\n");
5052 return 0;
5053 }
5054
5055 if (priv->eeprom.version < 0x2f) {
5056 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
5057 priv->eeprom.version);
5058 return -EINVAL;
5059 }
5060
5061 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
5062
5063 priv->channel_count =
bb8c093b
CH
5064 ARRAY_SIZE(iwl3945_eeprom_band_1) +
5065 ARRAY_SIZE(iwl3945_eeprom_band_2) +
5066 ARRAY_SIZE(iwl3945_eeprom_band_3) +
5067 ARRAY_SIZE(iwl3945_eeprom_band_4) +
5068 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY
5069
5070 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
5071
bb8c093b 5072 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY
5073 priv->channel_count, GFP_KERNEL);
5074 if (!priv->channel_info) {
5075 IWL_ERROR("Could not allocate channel_info\n");
5076 priv->channel_count = 0;
5077 return -ENOMEM;
5078 }
5079
5080 ch_info = priv->channel_info;
5081
5082 /* Loop through the 5 EEPROM bands adding them in order to the
5083 * channel map we maintain (that contains additional information than
5084 * what just in the EEPROM) */
5085 for (band = 1; band <= 5; band++) {
5086
bb8c093b 5087 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
5088 &eeprom_ch_info, &eeprom_ch_index);
5089
5090 /* Loop through each band adding each of the channels */
5091 for (ch = 0; ch < eeprom_ch_count; ch++) {
5092 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB
5093 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
5094 IEEE80211_BAND_5GHZ;
b481de9c
ZY
5095
5096 /* permanently store EEPROM's channel regulatory flags
5097 * and max power in channel info database. */
5098 ch_info->eeprom = eeprom_ch_info[ch];
5099
5100 /* Copy the run-time flags so they are there even on
5101 * invalid channels */
5102 ch_info->flags = eeprom_ch_info[ch].flags;
5103
5104 if (!(is_channel_valid(ch_info))) {
5105 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
5106 "No traffic\n",
5107 ch_info->channel,
5108 ch_info->flags,
5109 is_channel_a_band(ch_info) ?
5110 "5.2" : "2.4");
5111 ch_info++;
5112 continue;
5113 }
5114
5115 /* Initialize regulatory-based run-time data */
5116 ch_info->max_power_avg = ch_info->curr_txpow =
5117 eeprom_ch_info[ch].max_power_avg;
5118 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
5119 ch_info->min_power = 0;
5120
5121 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
5122 " %ddBm): Ad-Hoc %ssupported\n",
5123 ch_info->channel,
5124 is_channel_a_band(ch_info) ?
5125 "5.2" : "2.4",
5126 CHECK_AND_PRINT(IBSS),
5127 CHECK_AND_PRINT(ACTIVE),
5128 CHECK_AND_PRINT(RADAR),
5129 CHECK_AND_PRINT(WIDE),
5130 CHECK_AND_PRINT(NARROW),
5131 CHECK_AND_PRINT(DFS),
5132 eeprom_ch_info[ch].flags,
5133 eeprom_ch_info[ch].max_power_avg,
5134 ((eeprom_ch_info[ch].
5135 flags & EEPROM_CHANNEL_IBSS)
5136 && !(eeprom_ch_info[ch].
5137 flags & EEPROM_CHANNEL_RADAR))
5138 ? "" : "not ");
5139
5140 /* Set the user_txpower_limit to the highest power
5141 * supported by any channel */
5142 if (eeprom_ch_info[ch].max_power_avg >
5143 priv->user_txpower_limit)
5144 priv->user_txpower_limit =
5145 eeprom_ch_info[ch].max_power_avg;
5146
5147 ch_info++;
5148 }
5149 }
5150
6440adb5 5151 /* Set up txpower settings in driver for all channels */
b481de9c
ZY
5152 if (iwl3945_txpower_set_from_eeprom(priv))
5153 return -EIO;
5154
5155 return 0;
5156}
5157
849e0dce
RC
5158/*
5159 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
5160 */
5161static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
5162{
5163 kfree(priv->channel_info);
5164 priv->channel_count = 0;
5165}
5166
b481de9c
ZY
5167/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
5168 * sending probe req. This should be set long enough to hear probe responses
5169 * from more than one AP. */
5170#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
5171#define IWL_ACTIVE_DWELL_TIME_52 (10)
5172
5173/* For faster active scanning, scan will move to the next channel if fewer than
5174 * PLCP_QUIET_THRESH packets are heard on this channel within
5175 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
5176 * time if it's a quiet channel (nothing responded to our probe, and there's
5177 * no other traffic).
5178 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
5179#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
5180#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
5181
5182/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
5183 * Must be set longer than active dwell time.
5184 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
5185#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
5186#define IWL_PASSIVE_DWELL_TIME_52 (10)
5187#define IWL_PASSIVE_DWELL_BASE (100)
5188#define IWL_CHANNEL_TUNE_TIME 5
5189
8318d78a
JB
5190static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
5191 enum ieee80211_band band)
b481de9c 5192{
8318d78a 5193 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
5194 return IWL_ACTIVE_DWELL_TIME_52;
5195 else
5196 return IWL_ACTIVE_DWELL_TIME_24;
5197}
5198
8318d78a
JB
5199static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
5200 enum ieee80211_band band)
b481de9c 5201{
8318d78a
JB
5202 u16 active = iwl3945_get_active_dwell_time(priv, band);
5203 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY
5204 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
5205 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
5206
bb8c093b 5207 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
5208 /* If we're associated, we clamp the maximum passive
5209 * dwell time to be 98% of the beacon interval (minus
5210 * 2 * channel tune time) */
5211 passive = priv->beacon_int;
5212 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
5213 passive = IWL_PASSIVE_DWELL_BASE;
5214 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
5215 }
5216
5217 if (passive <= active)
5218 passive = active + 1;
5219
5220 return passive;
5221}
5222
8318d78a
JB
5223static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
5224 enum ieee80211_band band,
b481de9c 5225 u8 is_active, u8 direct_mask,
bb8c093b 5226 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
5227{
5228 const struct ieee80211_channel *channels = NULL;
8318d78a 5229 const struct ieee80211_supported_band *sband;
bb8c093b 5230 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY
5231 u16 passive_dwell = 0;
5232 u16 active_dwell = 0;
5233 int added, i;
5234
8318d78a
JB
5235 sband = iwl3945_get_band(priv, band);
5236 if (!sband)
b481de9c
ZY
5237 return 0;
5238
8318d78a 5239 channels = sband->channels;
b481de9c 5240
8318d78a
JB
5241 active_dwell = iwl3945_get_active_dwell_time(priv, band);
5242 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 5243
8318d78a
JB
5244 for (i = 0, added = 0; i < sband->n_channels; i++) {
5245 if (channels[i].hw_value ==
b481de9c 5246 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 5247 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
5248 IWL_DEBUG_SCAN
5249 ("Skipping current channel %d\n",
5250 le16_to_cpu(priv->active_rxon.channel));
5251 continue;
5252 }
5253 } else if (priv->only_active_channel)
5254 continue;
5255
8318d78a 5256 scan_ch->channel = channels[i].hw_value;
b481de9c 5257
8318d78a 5258 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c
ZY
5259 if (!is_channel_valid(ch_info)) {
5260 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
5261 scan_ch->channel);
5262 continue;
5263 }
5264
5265 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 5266 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY
5267 scan_ch->type = 0; /* passive */
5268 else
5269 scan_ch->type = 1; /* active */
5270
5271 if (scan_ch->type & 1)
5272 scan_ch->type |= (direct_mask << 1);
5273
5274 if (is_channel_narrow(ch_info))
5275 scan_ch->type |= (1 << 7);
5276
5277 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5278 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5279
9fbab516 5280 /* Set txpower levels to defaults */
b481de9c
ZY
5281 scan_ch->tpc.dsp_atten = 110;
5282 /* scan_pwr_info->tpc.dsp_atten; */
5283
5284 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 5285 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
5286 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5287 else {
5288 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5289 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5290 * power level:
8a1b0245 5291 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
5292 */
5293 }
5294
5295 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5296 scan_ch->channel,
5297 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5298 (scan_ch->type & 1) ?
5299 active_dwell : passive_dwell);
5300
5301 scan_ch++;
5302 added++;
5303 }
5304
5305 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5306 return added;
5307}
5308
bb8c093b 5309static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY
5310 struct ieee80211_rate *rates)
5311{
5312 int i;
5313
5314 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
5315 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5316 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5317 rates[i].hw_value_short = i;
5318 rates[i].flags = 0;
5319 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5320 /*
8318d78a 5321 * If CCK != 1M then set short preamble rate flag.
b481de9c 5322 */
bb8c093b 5323 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5324 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5325 }
b481de9c
ZY
5326 }
5327}
5328
5329/**
bb8c093b 5330 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5331 */
bb8c093b 5332static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5333{
bb8c093b 5334 struct iwl3945_channel_info *ch;
8318d78a 5335 struct ieee80211_supported_band *band;
b481de9c
ZY
5336 struct ieee80211_channel *channels;
5337 struct ieee80211_channel *geo_ch;
5338 struct ieee80211_rate *rates;
5339 int i = 0;
b481de9c 5340
8318d78a
JB
5341 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5342 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY
5343 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5344 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5345 return 0;
5346 }
5347
b481de9c
ZY
5348 channels = kzalloc(sizeof(struct ieee80211_channel) *
5349 priv->channel_count, GFP_KERNEL);
8318d78a 5350 if (!channels)
b481de9c 5351 return -ENOMEM;
b481de9c
ZY
5352
5353 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
5354 GFP_KERNEL);
5355 if (!rates) {
b481de9c
ZY
5356 kfree(channels);
5357 return -ENOMEM;
5358 }
5359
b481de9c 5360 /* 5.2GHz channels start after the 2.4GHz channels */
8318d78a
JB
5361 band = &priv->bands[IEEE80211_BAND_5GHZ];
5362 band->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5363 band->bitrates = &rates[4];
5364 band->n_bitrates = 8; /* just OFDM */
5365
5366 band = &priv->bands[IEEE80211_BAND_2GHZ];
5367 band->channels = channels;
5368 band->bitrates = rates;
5369 band->n_bitrates = 12; /* OFDM & CCK */
b481de9c
ZY
5370
5371 priv->ieee_channels = channels;
5372 priv->ieee_rates = rates;
5373
bb8c093b 5374 iwl3945_init_hw_rates(priv, rates);
b481de9c
ZY
5375
5376 for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
5377 ch = &priv->channel_info[i];
5378
5379 if (!is_channel_valid(ch)) {
5380 IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
5381 "skipping.\n",
5382 ch->channel, is_channel_a_band(ch) ?
5383 "5.2" : "2.4");
5384 continue;
5385 }
5386
5387 if (is_channel_a_band(ch))
8318d78a
JB
5388 geo_ch = &priv->bands[IEEE80211_BAND_5GHZ].channels[priv->bands[IEEE80211_BAND_5GHZ].n_channels++];
5389 else
5390 geo_ch = &priv->bands[IEEE80211_BAND_2GHZ].channels[priv->bands[IEEE80211_BAND_2GHZ].n_channels++];
b481de9c 5391
8318d78a
JB
5392 geo_ch->center_freq = ieee80211chan2mhz(ch->channel);
5393 geo_ch->max_power = ch->max_power_avg;
5394 geo_ch->max_antenna_gain = 0xff;
7b72304d 5395 geo_ch->hw_value = ch->channel;
b481de9c
ZY
5396
5397 if (is_channel_valid(ch)) {
8318d78a
JB
5398 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5399 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5400
8318d78a
JB
5401 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5402 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY
5403
5404 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5405 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY
5406
5407 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5408 priv->max_channel_txpower_limit =
5409 ch->max_power_avg;
8318d78a
JB
5410 } else
5411 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
b481de9c
ZY
5412 }
5413
8318d78a 5414 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) {
b481de9c
ZY
5415 printk(KERN_INFO DRV_NAME
5416 ": Incorrectly detected BG card as ABG. Please send "
5417 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5418 priv->pci_dev->device, priv->pci_dev->subsystem_device);
5419 priv->is_abg = 0;
5420 }
5421
5422 printk(KERN_INFO DRV_NAME
5423 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB
5424 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5425 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5426
8318d78a
JB
5427 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
5428 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5429
b481de9c
ZY
5430 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5431
5432 return 0;
5433}
5434
849e0dce
RC
5435/*
5436 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5437 */
5438static void iwl3945_free_geos(struct iwl3945_priv *priv)
5439{
849e0dce
RC
5440 kfree(priv->ieee_channels);
5441 kfree(priv->ieee_rates);
5442 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5443}
5444
b481de9c
ZY
5445/******************************************************************************
5446 *
5447 * uCode download functions
5448 *
5449 ******************************************************************************/
5450
bb8c093b 5451static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5452{
98c92211
TW
5453 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5454 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5455 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5456 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5457 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5458 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
5459}
5460
5461/**
bb8c093b 5462 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
5463 * looking at all data.
5464 */
bb8c093b 5465static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY
5466{
5467 u32 val;
5468 u32 save_len = len;
5469 int rc = 0;
5470 u32 errcnt;
5471
5472 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5473
bb8c093b 5474 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5475 if (rc)
5476 return rc;
5477
bb8c093b 5478 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY
5479
5480 errcnt = 0;
5481 for (; len > 0; len -= sizeof(u32), image++) {
5482 /* read data comes through single port, auto-incr addr */
5483 /* NOTE: Use the debugless read so we don't flood kernel log
5484 * if IWL_DL_IO is set */
bb8c093b 5485 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5486 if (val != le32_to_cpu(*image)) {
5487 IWL_ERROR("uCode INST section is invalid at "
5488 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5489 save_len - len, val, le32_to_cpu(*image));
5490 rc = -EIO;
5491 errcnt++;
5492 if (errcnt >= 20)
5493 break;
5494 }
5495 }
5496
bb8c093b 5497 iwl3945_release_nic_access(priv);
b481de9c
ZY
5498
5499 if (!errcnt)
bc434dd2 5500 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
5501
5502 return rc;
5503}
5504
5505
5506/**
bb8c093b 5507 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
5508 * using sample data 100 bytes apart. If these sample points are good,
5509 * it's a pretty good bet that everything between them is good, too.
5510 */
bb8c093b 5511static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
5512{
5513 u32 val;
5514 int rc = 0;
5515 u32 errcnt = 0;
5516 u32 i;
5517
5518 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5519
bb8c093b 5520 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5521 if (rc)
5522 return rc;
5523
5524 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5525 /* read data comes through single port, auto-incr addr */
5526 /* NOTE: Use the debugless read so we don't flood kernel log
5527 * if IWL_DL_IO is set */
bb8c093b 5528 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5529 i + RTC_INST_LOWER_BOUND);
bb8c093b 5530 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5531 if (val != le32_to_cpu(*image)) {
5532#if 0 /* Enable this if you want to see details */
5533 IWL_ERROR("uCode INST section is invalid at "
5534 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5535 i, val, *image);
5536#endif
5537 rc = -EIO;
5538 errcnt++;
5539 if (errcnt >= 3)
5540 break;
5541 }
5542 }
5543
bb8c093b 5544 iwl3945_release_nic_access(priv);
b481de9c
ZY
5545
5546 return rc;
5547}
5548
5549
5550/**
bb8c093b 5551 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
5552 * and verify its contents
5553 */
bb8c093b 5554static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY
5555{
5556 __le32 *image;
5557 u32 len;
5558 int rc = 0;
5559
5560 /* Try bootstrap */
5561 image = (__le32 *)priv->ucode_boot.v_addr;
5562 len = priv->ucode_boot.len;
bb8c093b 5563 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5564 if (rc == 0) {
5565 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5566 return 0;
5567 }
5568
5569 /* Try initialize */
5570 image = (__le32 *)priv->ucode_init.v_addr;
5571 len = priv->ucode_init.len;
bb8c093b 5572 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5573 if (rc == 0) {
5574 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5575 return 0;
5576 }
5577
5578 /* Try runtime/protocol */
5579 image = (__le32 *)priv->ucode_code.v_addr;
5580 len = priv->ucode_code.len;
bb8c093b 5581 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5582 if (rc == 0) {
5583 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5584 return 0;
5585 }
5586
5587 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5588
9fbab516
BC
5589 /* Since nothing seems to match, show first several data entries in
5590 * instruction SRAM, so maybe visual inspection will give a clue.
5591 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
5592 image = (__le32 *)priv->ucode_boot.v_addr;
5593 len = priv->ucode_boot.len;
bb8c093b 5594 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
5595
5596 return rc;
5597}
5598
5599
5600/* check contents of special bootstrap uCode SRAM */
bb8c093b 5601static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY
5602{
5603 __le32 *image = priv->ucode_boot.v_addr;
5604 u32 len = priv->ucode_boot.len;
5605 u32 reg;
5606 u32 val;
5607
5608 IWL_DEBUG_INFO("Begin verify bsm\n");
5609
5610 /* verify BSM SRAM contents */
bb8c093b 5611 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY
5612 for (reg = BSM_SRAM_LOWER_BOUND;
5613 reg < BSM_SRAM_LOWER_BOUND + len;
5614 reg += sizeof(u32), image ++) {
bb8c093b 5615 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY
5616 if (val != le32_to_cpu(*image)) {
5617 IWL_ERROR("BSM uCode verification failed at "
5618 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5619 BSM_SRAM_LOWER_BOUND,
5620 reg - BSM_SRAM_LOWER_BOUND, len,
5621 val, le32_to_cpu(*image));
5622 return -EIO;
5623 }
5624 }
5625
5626 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5627
5628 return 0;
5629}
5630
5631/**
bb8c093b 5632 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY
5633 *
5634 * BSM operation:
5635 *
5636 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5637 * in special SRAM that does not power down during RFKILL. When powering back
5638 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5639 * the bootstrap program into the on-board processor, and starts it.
5640 *
5641 * The bootstrap program loads (via DMA) instructions and data for a new
5642 * program from host DRAM locations indicated by the host driver in the
5643 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5644 * automatically.
5645 *
5646 * When initializing the NIC, the host driver points the BSM to the
5647 * "initialize" uCode image. This uCode sets up some internal data, then
5648 * notifies host via "initialize alive" that it is complete.
5649 *
5650 * The host then replaces the BSM_DRAM_* pointer values to point to the
5651 * normal runtime uCode instructions and a backup uCode data cache buffer
5652 * (filled initially with starting data values for the on-board processor),
5653 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5654 * which begins normal operation.
5655 *
5656 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5657 * the backup data cache in DRAM before SRAM is powered down.
5658 *
5659 * When powering back up, the BSM loads the bootstrap program. This reloads
5660 * the runtime uCode instructions and the backup data cache into SRAM,
5661 * and re-launches the runtime uCode from where it left off.
5662 */
bb8c093b 5663static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY
5664{
5665 __le32 *image = priv->ucode_boot.v_addr;
5666 u32 len = priv->ucode_boot.len;
5667 dma_addr_t pinst;
5668 dma_addr_t pdata;
5669 u32 inst_len;
5670 u32 data_len;
5671 int rc;
5672 int i;
5673 u32 done;
5674 u32 reg_offset;
5675
5676 IWL_DEBUG_INFO("Begin load bsm\n");
5677
5678 /* make sure bootstrap program is no larger than BSM's SRAM size */
5679 if (len > IWL_MAX_BSM_SIZE)
5680 return -EINVAL;
5681
5682 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5683 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5684 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY
5685 * after the "initialize" uCode has run, to point to
5686 * runtime/protocol instructions and backup data cache. */
5687 pinst = priv->ucode_init.p_addr;
5688 pdata = priv->ucode_init_data.p_addr;
5689 inst_len = priv->ucode_init.len;
5690 data_len = priv->ucode_init_data.len;
5691
bb8c093b 5692 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5693 if (rc)
5694 return rc;
5695
bb8c093b
CH
5696 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5697 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5698 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5699 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY
5700
5701 /* Fill BSM memory with bootstrap instructions */
5702 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5703 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5704 reg_offset += sizeof(u32), image++)
bb8c093b 5705 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY
5706 le32_to_cpu(*image));
5707
bb8c093b 5708 rc = iwl3945_verify_bsm(priv);
b481de9c 5709 if (rc) {
bb8c093b 5710 iwl3945_release_nic_access(priv);
b481de9c
ZY
5711 return rc;
5712 }
5713
5714 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH
5715 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5716 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5717 RTC_INST_LOWER_BOUND);
bb8c093b 5718 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY
5719
5720 /* Load bootstrap code into instruction SRAM now,
5721 * to prepare to load "initialize" uCode */
bb8c093b 5722 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5723 BSM_WR_CTRL_REG_BIT_START);
5724
5725 /* Wait for load of bootstrap uCode to finish */
5726 for (i = 0; i < 100; i++) {
bb8c093b 5727 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY
5728 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5729 break;
5730 udelay(10);
5731 }
5732 if (i < 100)
5733 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5734 else {
5735 IWL_ERROR("BSM write did not complete!\n");
5736 return -EIO;
5737 }
5738
5739 /* Enable future boot loads whenever power management unit triggers it
5740 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5741 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5742 BSM_WR_CTRL_REG_BIT_START_EN);
5743
bb8c093b 5744 iwl3945_release_nic_access(priv);
b481de9c
ZY
5745
5746 return 0;
5747}
5748
bb8c093b 5749static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY
5750{
5751 /* Remove all resets to allow NIC to operate */
bb8c093b 5752 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY
5753}
5754
5755/**
bb8c093b 5756 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
5757 *
5758 * Copy into buffers for card to fetch via bus-mastering
5759 */
bb8c093b 5760static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5761{
bb8c093b 5762 struct iwl3945_ucode *ucode;
90e759d1 5763 int ret = 0;
b481de9c
ZY
5764 const struct firmware *ucode_raw;
5765 /* firmware file name contains uCode/driver compatibility version */
5766 const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
5767 u8 *src;
5768 size_t len;
5769 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5770
5771 /* Ask kernel firmware_class module to get the boot firmware off disk.
5772 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW
5773 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5774 if (ret < 0) {
5775 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5776 name, ret);
b481de9c
ZY
5777 goto error;
5778 }
5779
5780 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5781 name, ucode_raw->size);
5782
5783 /* Make sure that we got at least our header! */
5784 if (ucode_raw->size < sizeof(*ucode)) {
5785 IWL_ERROR("File size way too small!\n");
90e759d1 5786 ret = -EINVAL;
b481de9c
ZY
5787 goto err_release;
5788 }
5789
5790 /* Data from ucode file: header followed by uCode images */
5791 ucode = (void *)ucode_raw->data;
5792
5793 ver = le32_to_cpu(ucode->ver);
5794 inst_size = le32_to_cpu(ucode->inst_size);
5795 data_size = le32_to_cpu(ucode->data_size);
5796 init_size = le32_to_cpu(ucode->init_size);
5797 init_data_size = le32_to_cpu(ucode->init_data_size);
5798 boot_size = le32_to_cpu(ucode->boot_size);
5799
5800 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS
5801 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5802 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5803 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5804 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5805 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY
5806
5807 /* Verify size of file vs. image size info in file's header */
5808 if (ucode_raw->size < sizeof(*ucode) +
5809 inst_size + data_size + init_size +
5810 init_data_size + boot_size) {
5811
5812 IWL_DEBUG_INFO("uCode file size %d too small\n",
5813 (int)ucode_raw->size);
90e759d1 5814 ret = -EINVAL;
b481de9c
ZY
5815 goto err_release;
5816 }
5817
5818 /* Verify that uCode images will fit in card's SRAM */
5819 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
5820 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5821 inst_size);
5822 ret = -EINVAL;
b481de9c
ZY
5823 goto err_release;
5824 }
5825
5826 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
5827 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5828 data_size);
5829 ret = -EINVAL;
b481de9c
ZY
5830 goto err_release;
5831 }
5832 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
5833 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5834 init_size);
5835 ret = -EINVAL;
b481de9c
ZY
5836 goto err_release;
5837 }
5838 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
5839 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5840 init_data_size);
5841 ret = -EINVAL;
b481de9c
ZY
5842 goto err_release;
5843 }
5844 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW
5845 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5846 boot_size);
5847 ret = -EINVAL;
b481de9c
ZY
5848 goto err_release;
5849 }
5850
5851 /* Allocate ucode buffers for card's bus-master loading ... */
5852
5853 /* Runtime instructions and 2 copies of data:
5854 * 1) unmodified from disk
5855 * 2) backup cache for save/restore during power-downs */
5856 priv->ucode_code.len = inst_size;
98c92211 5857 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
5858
5859 priv->ucode_data.len = data_size;
98c92211 5860 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
5861
5862 priv->ucode_data_backup.len = data_size;
98c92211 5863 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5864
90e759d1
TW
5865 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5866 !priv->ucode_data_backup.v_addr)
5867 goto err_pci_alloc;
b481de9c
ZY
5868
5869 /* Initialization instructions and data */
90e759d1
TW
5870 if (init_size && init_data_size) {
5871 priv->ucode_init.len = init_size;
98c92211 5872 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
5873
5874 priv->ucode_init_data.len = init_data_size;
98c92211 5875 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
5876
5877 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5878 goto err_pci_alloc;
5879 }
b481de9c
ZY
5880
5881 /* Bootstrap (instructions only, no data) */
90e759d1
TW
5882 if (boot_size) {
5883 priv->ucode_boot.len = boot_size;
98c92211 5884 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5885
90e759d1
TW
5886 if (!priv->ucode_boot.v_addr)
5887 goto err_pci_alloc;
5888 }
b481de9c
ZY
5889
5890 /* Copy images into buffers for card's bus-master reads ... */
5891
5892 /* Runtime instructions (first block of data in file) */
5893 src = &ucode->data[0];
5894 len = priv->ucode_code.len;
90e759d1 5895 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY
5896 memcpy(priv->ucode_code.v_addr, src, len);
5897 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5898 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5899
5900 /* Runtime data (2nd block)
bb8c093b 5901 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
5902 src = &ucode->data[inst_size];
5903 len = priv->ucode_data.len;
90e759d1 5904 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
5905 memcpy(priv->ucode_data.v_addr, src, len);
5906 memcpy(priv->ucode_data_backup.v_addr, src, len);
5907
5908 /* Initialization instructions (3rd block) */
5909 if (init_size) {
5910 src = &ucode->data[inst_size + data_size];
5911 len = priv->ucode_init.len;
90e759d1
TW
5912 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5913 len);
b481de9c
ZY
5914 memcpy(priv->ucode_init.v_addr, src, len);
5915 }
5916
5917 /* Initialization data (4th block) */
5918 if (init_data_size) {
5919 src = &ucode->data[inst_size + data_size + init_size];
5920 len = priv->ucode_init_data.len;
5921 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5922 (int)len);
5923 memcpy(priv->ucode_init_data.v_addr, src, len);
5924 }
5925
5926 /* Bootstrap instructions (5th block) */
5927 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5928 len = priv->ucode_boot.len;
5929 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5930 (int)len);
5931 memcpy(priv->ucode_boot.v_addr, src, len);
5932
5933 /* We have our copies now, allow OS release its copies */
5934 release_firmware(ucode_raw);
5935 return 0;
5936
5937 err_pci_alloc:
5938 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5939 ret = -ENOMEM;
bb8c093b 5940 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
5941
5942 err_release:
5943 release_firmware(ucode_raw);
5944
5945 error:
90e759d1 5946 return ret;
b481de9c
ZY
5947}
5948
5949
5950/**
bb8c093b 5951 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
5952 *
5953 * Tell initialization uCode where to find runtime uCode.
5954 *
5955 * BSM registers initially contain pointers to initialization uCode.
5956 * We need to replace them to load runtime uCode inst and data,
5957 * and to save runtime data when powering down.
5958 */
bb8c093b 5959static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY
5960{
5961 dma_addr_t pinst;
5962 dma_addr_t pdata;
5963 int rc = 0;
5964 unsigned long flags;
5965
5966 /* bits 31:0 for 3945 */
5967 pinst = priv->ucode_code.p_addr;
5968 pdata = priv->ucode_data_backup.p_addr;
5969
5970 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5971 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5972 if (rc) {
5973 spin_unlock_irqrestore(&priv->lock, flags);
5974 return rc;
5975 }
5976
5977 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH
5978 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5979 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5980 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
5981 priv->ucode_data.len);
5982
5983 /* Inst bytecount must be last to set up, bit 31 signals uCode
5984 * that all new ptr/size info is in place */
bb8c093b 5985 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
5986 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5987
bb8c093b 5988 iwl3945_release_nic_access(priv);
b481de9c
ZY
5989
5990 spin_unlock_irqrestore(&priv->lock, flags);
5991
5992 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5993
5994 return rc;
5995}
5996
5997/**
bb8c093b 5998 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
5999 *
6000 * Called after REPLY_ALIVE notification received from "initialize" uCode.
6001 *
b481de9c 6002 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 6003 */
bb8c093b 6004static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY
6005{
6006 /* Check alive response for "valid" sign from uCode */
6007 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
6008 /* We had an error bringing up the hardware, so take it
6009 * all the way back down so we can try again */
6010 IWL_DEBUG_INFO("Initialize Alive failed.\n");
6011 goto restart;
6012 }
6013
6014 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
6015 * This is a paranoid check, because we would not have gotten the
6016 * "initialize" alive if code weren't properly loaded. */
bb8c093b 6017 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
6018 /* Runtime instruction load was bad;
6019 * take it all the way back down so we can try again */
6020 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
6021 goto restart;
6022 }
6023
6024 /* Send pointers to protocol/runtime uCode image ... init code will
6025 * load and launch runtime uCode, which will send us another "Alive"
6026 * notification. */
6027 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 6028 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
6029 /* Runtime instruction load won't happen;
6030 * take it all the way back down so we can try again */
6031 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
6032 goto restart;
6033 }
6034 return;
6035
6036 restart:
6037 queue_work(priv->workqueue, &priv->restart);
6038}
6039
6040
6041/**
bb8c093b 6042 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 6043 * from protocol/runtime uCode (initialization uCode's
bb8c093b 6044 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 6045 */
bb8c093b 6046static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY
6047{
6048 int rc = 0;
6049 int thermal_spin = 0;
6050 u32 rfkill;
6051
6052 IWL_DEBUG_INFO("Runtime Alive received.\n");
6053
6054 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
6055 /* We had an error bringing up the hardware, so take it
6056 * all the way back down so we can try again */
6057 IWL_DEBUG_INFO("Alive failed.\n");
6058 goto restart;
6059 }
6060
6061 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
6062 * This is a paranoid check, because we would not have gotten the
6063 * "runtime" alive if code weren't properly loaded. */
bb8c093b 6064 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
6065 /* Runtime instruction load was bad;
6066 * take it all the way back down so we can try again */
6067 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
6068 goto restart;
6069 }
6070
bb8c093b 6071 iwl3945_clear_stations_table(priv);
b481de9c 6072
bb8c093b 6073 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
6074 if (rc) {
6075 IWL_WARNING("Can not read rfkill status from adapter\n");
6076 return;
6077 }
6078
bb8c093b 6079 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 6080 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 6081 iwl3945_release_nic_access(priv);
b481de9c
ZY
6082
6083 if (rfkill & 0x1) {
6084 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6085 /* if rfkill is not on, then wait for thermal
6086 * sensor in adapter to kick in */
bb8c093b 6087 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
6088 thermal_spin++;
6089 udelay(10);
6090 }
6091
6092 if (thermal_spin)
6093 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
6094 thermal_spin * 10);
6095 } else
6096 set_bit(STATUS_RF_KILL_HW, &priv->status);
6097
9fbab516 6098 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
6099 set_bit(STATUS_ALIVE, &priv->status);
6100
6101 /* Clear out the uCode error bit if it is set */
6102 clear_bit(STATUS_FW_ERROR, &priv->status);
6103
bb8c093b 6104 if (iwl3945_is_rfkill(priv))
b481de9c
ZY
6105 return;
6106
5a66926a 6107 ieee80211_start_queues(priv->hw);
b481de9c
ZY
6108
6109 priv->active_rate = priv->rates_mask;
6110 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
6111
bb8c093b 6112 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 6113
bb8c093b
CH
6114 if (iwl3945_is_associated(priv)) {
6115 struct iwl3945_rxon_cmd *active_rxon =
6116 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY
6117
6118 memcpy(&priv->staging_rxon, &priv->active_rxon,
6119 sizeof(priv->staging_rxon));
6120 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6121 } else {
6122 /* Initialize our rx_config data */
bb8c093b 6123 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY
6124 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
6125 }
6126
9fbab516 6127 /* Configure Bluetooth device coexistence support */
bb8c093b 6128 iwl3945_send_bt_config(priv);
b481de9c
ZY
6129
6130 /* Configure the adapter for unassociated operation */
bb8c093b 6131 iwl3945_commit_rxon(priv);
b481de9c
ZY
6132
6133 /* At this point, the NIC is initialized and operational */
6134 priv->notif_missed_beacons = 0;
6135 set_bit(STATUS_READY, &priv->status);
6136
6137 iwl3945_reg_txpower_periodic(priv);
6138
6139 IWL_DEBUG_INFO("ALIVE processing complete.\n");
5a66926a 6140 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
6141
6142 if (priv->error_recovering)
bb8c093b 6143 iwl3945_error_recovery(priv);
b481de9c
ZY
6144
6145 return;
6146
6147 restart:
6148 queue_work(priv->workqueue, &priv->restart);
6149}
6150
bb8c093b 6151static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 6152
bb8c093b 6153static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY
6154{
6155 unsigned long flags;
6156 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
6157 struct ieee80211_conf *conf = NULL;
6158
6159 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
6160
6161 conf = ieee80211_get_hw_conf(priv->hw);
6162
6163 if (!exit_pending)
6164 set_bit(STATUS_EXIT_PENDING, &priv->status);
6165
bb8c093b 6166 iwl3945_clear_stations_table(priv);
b481de9c
ZY
6167
6168 /* Unblock any waiting calls */
6169 wake_up_interruptible_all(&priv->wait_command_queue);
6170
b481de9c
ZY
6171 /* Wipe out the EXIT_PENDING status bit if we are not actually
6172 * exiting the module */
6173 if (!exit_pending)
6174 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6175
6176 /* stop and reset the on-board processor */
bb8c093b 6177 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
6178
6179 /* tell the device to stop sending interrupts */
bb8c093b 6180 iwl3945_disable_interrupts(priv);
b481de9c
ZY
6181
6182 if (priv->mac80211_registered)
6183 ieee80211_stop_queues(priv->hw);
6184
bb8c093b 6185 /* If we have not previously called iwl3945_init() then
b481de9c 6186 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 6187 if (!iwl3945_is_init(priv)) {
b481de9c
ZY
6188 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6189 STATUS_RF_KILL_HW |
6190 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6191 STATUS_RF_KILL_SW |
9788864e
RC
6192 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
6193 STATUS_GEO_CONFIGURED |
b481de9c
ZY
6194 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6195 STATUS_IN_SUSPEND;
6196 goto exit;
6197 }
6198
6199 /* ...otherwise clear out all the status bits but the RF Kill and
6200 * SUSPEND bits and continue taking the NIC down. */
6201 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6202 STATUS_RF_KILL_HW |
6203 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6204 STATUS_RF_KILL_SW |
9788864e
RC
6205 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
6206 STATUS_GEO_CONFIGURED |
b481de9c
ZY
6207 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6208 STATUS_IN_SUSPEND |
6209 test_bit(STATUS_FW_ERROR, &priv->status) <<
6210 STATUS_FW_ERROR;
6211
6212 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6213 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
6214 spin_unlock_irqrestore(&priv->lock, flags);
6215
bb8c093b
CH
6216 iwl3945_hw_txq_ctx_stop(priv);
6217 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY
6218
6219 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
6220 if (!iwl3945_grab_nic_access(priv)) {
6221 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 6222 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 6223 iwl3945_release_nic_access(priv);
b481de9c
ZY
6224 }
6225 spin_unlock_irqrestore(&priv->lock, flags);
6226
6227 udelay(5);
6228
bb8c093b
CH
6229 iwl3945_hw_nic_stop_master(priv);
6230 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
6231 iwl3945_hw_nic_reset(priv);
b481de9c
ZY
6232
6233 exit:
bb8c093b 6234 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY
6235
6236 if (priv->ibss_beacon)
6237 dev_kfree_skb(priv->ibss_beacon);
6238 priv->ibss_beacon = NULL;
6239
6240 /* clear out any free frames */
bb8c093b 6241 iwl3945_clear_free_frames(priv);
b481de9c
ZY
6242}
6243
bb8c093b 6244static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY
6245{
6246 mutex_lock(&priv->mutex);
bb8c093b 6247 __iwl3945_down(priv);
b481de9c 6248 mutex_unlock(&priv->mutex);
b24d22b1 6249
bb8c093b 6250 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
6251}
6252
6253#define MAX_HW_RESTARTS 5
6254
bb8c093b 6255static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY
6256{
6257 int rc, i;
6258
6259 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6260 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6261 return -EIO;
6262 }
6263
6264 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6265 IWL_WARNING("Radio disabled by SW RF kill (module "
6266 "parameter)\n");
e655b9f0
ZY
6267 return -ENODEV;
6268 }
6269
e903fbd4
RC
6270 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6271 IWL_ERROR("ucode not available for device bringup\n");
6272 return -EIO;
6273 }
6274
e655b9f0
ZY
6275 /* If platform's RF_KILL switch is NOT set to KILL */
6276 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6277 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6278 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6279 else {
6280 set_bit(STATUS_RF_KILL_HW, &priv->status);
6281 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6282 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6283 return -ENODEV;
6284 }
b481de9c
ZY
6285 }
6286
bb8c093b 6287 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6288
bb8c093b 6289 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY
6290 if (rc) {
6291 IWL_ERROR("Unable to int nic\n");
6292 return rc;
6293 }
6294
6295 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH
6296 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6297 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
6298 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6299
6300 /* clear (again), then enable host interrupts */
bb8c093b
CH
6301 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6302 iwl3945_enable_interrupts(priv);
b481de9c
ZY
6303
6304 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH
6305 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6306 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
6307
6308 /* Copy original ucode data image from disk into backup cache.
6309 * This will be used to initialize the on-board processor's
6310 * data SRAM for a clean start when the runtime program first loads. */
6311 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6312 priv->ucode_data.len);
b481de9c 6313
e655b9f0
ZY
6314 /* We return success when we resume from suspend and rf_kill is on. */
6315 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6316 return 0;
6317
b481de9c
ZY
6318 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6319
bb8c093b 6320 iwl3945_clear_stations_table(priv);
b481de9c
ZY
6321
6322 /* load bootstrap state machine,
6323 * load bootstrap program into processor's memory,
6324 * prepare to load the "initialize" uCode */
bb8c093b 6325 rc = iwl3945_load_bsm(priv);
b481de9c
ZY
6326
6327 if (rc) {
6328 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6329 continue;
6330 }
6331
6332 /* start card; "initialize" will load runtime ucode */
bb8c093b 6333 iwl3945_nic_start(priv);
b481de9c 6334
b481de9c
ZY
6335 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6336
6337 return 0;
6338 }
6339
6340 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6341 __iwl3945_down(priv);
b481de9c
ZY
6342
6343 /* tried to restart and config the device for as long as our
6344 * patience could withstand */
6345 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6346 return -EIO;
6347}
6348
6349
6350/*****************************************************************************
6351 *
6352 * Workqueue callbacks
6353 *
6354 *****************************************************************************/
6355
bb8c093b 6356static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6357{
bb8c093b
CH
6358 struct iwl3945_priv *priv =
6359 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY
6360
6361 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6362 return;
6363
6364 mutex_lock(&priv->mutex);
bb8c093b 6365 iwl3945_init_alive_start(priv);
b481de9c
ZY
6366 mutex_unlock(&priv->mutex);
6367}
6368
bb8c093b 6369static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6370{
bb8c093b
CH
6371 struct iwl3945_priv *priv =
6372 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY
6373
6374 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6375 return;
6376
6377 mutex_lock(&priv->mutex);
bb8c093b 6378 iwl3945_alive_start(priv);
b481de9c
ZY
6379 mutex_unlock(&priv->mutex);
6380}
6381
bb8c093b 6382static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6383{
bb8c093b 6384 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY
6385
6386 wake_up_interruptible(&priv->wait_command_queue);
6387
6388 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6389 return;
6390
6391 mutex_lock(&priv->mutex);
6392
bb8c093b 6393 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY
6394 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6395 "HW and/or SW RF Kill no longer active, restarting "
6396 "device\n");
6397 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6398 queue_work(priv->workqueue, &priv->restart);
6399 } else {
6400
6401 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6402 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6403 "disabled by SW switch\n");
6404 else
6405 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6406 "Kill switch must be turned off for "
6407 "wireless networking to work.\n");
6408 }
6409 mutex_unlock(&priv->mutex);
6410}
6411
6412#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6413
bb8c093b 6414static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6415{
bb8c093b
CH
6416 struct iwl3945_priv *priv =
6417 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY
6418
6419 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6420 return;
6421
6422 mutex_lock(&priv->mutex);
6423 if (test_bit(STATUS_SCANNING, &priv->status) ||
6424 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6425 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6426 "Scan completion watchdog resetting adapter (%dms)\n",
6427 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6428
b481de9c 6429 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6430 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6431 }
6432 mutex_unlock(&priv->mutex);
6433}
6434
bb8c093b 6435static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6436{
bb8c093b
CH
6437 struct iwl3945_priv *priv =
6438 container_of(data, struct iwl3945_priv, request_scan);
6439 struct iwl3945_host_cmd cmd = {
b481de9c 6440 .id = REPLY_SCAN_CMD,
bb8c093b 6441 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
6442 .meta.flags = CMD_SIZE_HUGE,
6443 };
6444 int rc = 0;
bb8c093b 6445 struct iwl3945_scan_cmd *scan;
b481de9c
ZY
6446 struct ieee80211_conf *conf = NULL;
6447 u8 direct_mask;
8318d78a 6448 enum ieee80211_band band;
b481de9c
ZY
6449
6450 conf = ieee80211_get_hw_conf(priv->hw);
6451
6452 mutex_lock(&priv->mutex);
6453
bb8c093b 6454 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY
6455 IWL_WARNING("request scan called when driver not ready.\n");
6456 goto done;
6457 }
6458
6459 /* Make sure the scan wasn't cancelled before this queued work
6460 * was given the chance to run... */
6461 if (!test_bit(STATUS_SCANNING, &priv->status))
6462 goto done;
6463
6464 /* This should never be called or scheduled if there is currently
6465 * a scan active in the hardware. */
6466 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6467 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6468 "Ignoring second request.\n");
6469 rc = -EIO;
6470 goto done;
6471 }
6472
6473 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6474 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6475 goto done;
6476 }
6477
6478 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6479 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6480 goto done;
6481 }
6482
bb8c093b 6483 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY
6484 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6485 goto done;
6486 }
6487
6488 if (!test_bit(STATUS_READY, &priv->status)) {
6489 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6490 goto done;
6491 }
6492
6493 if (!priv->scan_bands) {
6494 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6495 goto done;
6496 }
6497
6498 if (!priv->scan) {
bb8c093b 6499 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY
6500 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6501 if (!priv->scan) {
6502 rc = -ENOMEM;
6503 goto done;
6504 }
6505 }
6506 scan = priv->scan;
bb8c093b 6507 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
6508
6509 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6510 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6511
bb8c093b 6512 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
6513 u16 interval = 0;
6514 u32 extra;
6515 u32 suspend_time = 100;
6516 u32 scan_suspend_time = 100;
6517 unsigned long flags;
6518
6519 IWL_DEBUG_INFO("Scanning while associated...\n");
6520
6521 spin_lock_irqsave(&priv->lock, flags);
6522 interval = priv->beacon_int;
6523 spin_unlock_irqrestore(&priv->lock, flags);
6524
6525 scan->suspend_time = 0;
15e869d8 6526 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
6527 if (!interval)
6528 interval = suspend_time;
6529 /*
6530 * suspend time format:
6531 * 0-19: beacon interval in usec (time before exec.)
6532 * 20-23: 0
6533 * 24-31: number of beacons (suspend between channels)
6534 */
6535
6536 extra = (suspend_time / interval) << 24;
6537 scan_suspend_time = 0xFF0FFFFF &
6538 (extra | ((suspend_time % interval) * 1024));
6539
6540 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6541 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6542 scan_suspend_time, interval);
6543 }
6544
6545 /* We should add the ability for user to lock to PASSIVE ONLY */
6546 if (priv->one_direct_scan) {
6547 IWL_DEBUG_SCAN
6548 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6549 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY
6550 priv->direct_ssid_len));
6551 scan->direct_scan[0].id = WLAN_EID_SSID;
6552 scan->direct_scan[0].len = priv->direct_ssid_len;
6553 memcpy(scan->direct_scan[0].ssid,
6554 priv->direct_ssid, priv->direct_ssid_len);
6555 direct_mask = 1;
bb8c093b 6556 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
b481de9c
ZY
6557 scan->direct_scan[0].id = WLAN_EID_SSID;
6558 scan->direct_scan[0].len = priv->essid_len;
6559 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6560 direct_mask = 1;
6561 } else
6562 direct_mask = 0;
6563
6564 /* We don't build a direct scan probe request; the uCode will do
6565 * that based on the direct_mask added to each channel entry */
6566 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6567 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6568 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY
6569 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6570 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6571 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6572
6573 /* flags + rate selection */
6574
6575 switch (priv->scan_bands) {
6576 case 2:
6577 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6578 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6579 scan->good_CRC_th = 0;
8318d78a 6580 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY
6581 break;
6582
6583 case 1:
6584 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6585 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6586 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY
6587 break;
6588
6589 default:
6590 IWL_WARNING("Invalid scan band count\n");
6591 goto done;
6592 }
6593
6594 /* select Rx antennas */
6595 scan->flags |= iwl3945_get_antenna_flags(priv);
6596
6597 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6598 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6599
6600 if (direct_mask)
6601 IWL_DEBUG_SCAN
6602 ("Initiating direct scan for %s.\n",
bb8c093b 6603 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY
6604 else
6605 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
6606
6607 scan->channel_count =
bb8c093b 6608 iwl3945_get_channels_for_scan(
8318d78a 6609 priv, band, 1, /* active */
b481de9c
ZY
6610 direct_mask,
6611 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6612
6613 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6614 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
6615 cmd.data = scan;
6616 scan->len = cpu_to_le16(cmd.len);
6617
6618 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6619 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
6620 if (rc)
6621 goto done;
6622
6623 queue_delayed_work(priv->workqueue, &priv->scan_check,
6624 IWL_SCAN_CHECK_WATCHDOG);
6625
6626 mutex_unlock(&priv->mutex);
6627 return;
6628
6629 done:
01ebd063 6630 /* inform mac80211 scan aborted */
b481de9c
ZY
6631 queue_work(priv->workqueue, &priv->scan_completed);
6632 mutex_unlock(&priv->mutex);
6633}
6634
bb8c093b 6635static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6636{
bb8c093b 6637 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY
6638
6639 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6640 return;
6641
6642 mutex_lock(&priv->mutex);
bb8c093b 6643 __iwl3945_up(priv);
b481de9c
ZY
6644 mutex_unlock(&priv->mutex);
6645}
6646
bb8c093b 6647static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6648{
bb8c093b 6649 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY
6650
6651 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6652 return;
6653
bb8c093b 6654 iwl3945_down(priv);
b481de9c
ZY
6655 queue_work(priv->workqueue, &priv->up);
6656}
6657
bb8c093b 6658static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6659{
bb8c093b
CH
6660 struct iwl3945_priv *priv =
6661 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY
6662
6663 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6664 return;
6665
6666 mutex_lock(&priv->mutex);
bb8c093b 6667 iwl3945_rx_replenish(priv);
b481de9c
ZY
6668 mutex_unlock(&priv->mutex);
6669}
6670
7878a5a4
MA
6671#define IWL_DELAY_NEXT_SCAN (HZ*2)
6672
bb8c093b 6673static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6674{
bb8c093b 6675 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY
6676 post_associate.work);
6677
6678 int rc = 0;
6679 struct ieee80211_conf *conf = NULL;
0795af57 6680 DECLARE_MAC_BUF(mac);
b481de9c
ZY
6681
6682 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6683 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6684 return;
6685 }
6686
6687
0795af57
JP
6688 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6689 priv->assoc_id,
6690 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY
6691
6692 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6693 return;
6694
6695 mutex_lock(&priv->mutex);
6696
32bfd35d 6697 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA
6698 mutex_unlock(&priv->mutex);
6699 return;
6700 }
bb8c093b 6701 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6702
b481de9c
ZY
6703 conf = ieee80211_get_hw_conf(priv->hw);
6704
6705 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6706 iwl3945_commit_rxon(priv);
b481de9c 6707
bb8c093b
CH
6708 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6709 iwl3945_setup_rxon_timing(priv);
6710 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6711 sizeof(priv->rxon_timing), &priv->rxon_timing);
6712 if (rc)
6713 IWL_WARNING("REPLY_RXON_TIMING failed - "
6714 "Attempting to continue.\n");
6715
6716 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6717
6718 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6719
6720 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6721 priv->assoc_id, priv->beacon_int);
6722
6723 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6724 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6725 else
6726 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6727
6728 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6729 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6730 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6731 else
6732 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6733
6734 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6735 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6736
6737 }
6738
bb8c093b 6739 iwl3945_commit_rxon(priv);
b481de9c
ZY
6740
6741 switch (priv->iw_mode) {
6742 case IEEE80211_IF_TYPE_STA:
bb8c093b 6743 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
6744 break;
6745
6746 case IEEE80211_IF_TYPE_IBSS:
6747
6748 /* clear out the station table */
bb8c093b 6749 iwl3945_clear_stations_table(priv);
b481de9c 6750
bb8c093b
CH
6751 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6752 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6753 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6754 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
6755 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6756 CMD_ASYNC);
bb8c093b
CH
6757 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6758 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
6759
6760 break;
6761
6762 default:
6763 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6764 __FUNCTION__, priv->iw_mode);
b481de9c
ZY
6765 break;
6766 }
6767
bb8c093b 6768 iwl3945_sequence_reset(priv);
b481de9c 6769
bb8c093b 6770 iwl3945_activate_qos(priv, 0);
292ae174 6771
7878a5a4
MA
6772 /* we have just associated, don't start scan too early */
6773 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY
6774 mutex_unlock(&priv->mutex);
6775}
6776
bb8c093b 6777static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6778{
bb8c093b 6779 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6780
bb8c093b 6781 if (!iwl3945_is_ready(priv))
b481de9c
ZY
6782 return;
6783
6784 mutex_lock(&priv->mutex);
6785
6786 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6787 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6788
6789 mutex_unlock(&priv->mutex);
6790}
6791
76bb77e0
ZY
6792static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6793
bb8c093b 6794static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6795{
bb8c093b
CH
6796 struct iwl3945_priv *priv =
6797 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY
6798
6799 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6800
6801 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6802 return;
6803
a0646470
ZY
6804 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6805 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6806
b481de9c
ZY
6807 ieee80211_scan_completed(priv->hw);
6808
6809 /* Since setting the TXPOWER may have been deferred while
6810 * performing the scan, fire one off */
6811 mutex_lock(&priv->mutex);
bb8c093b 6812 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
6813 mutex_unlock(&priv->mutex);
6814}
6815
6816/*****************************************************************************
6817 *
6818 * mac80211 entry point functions
6819 *
6820 *****************************************************************************/
6821
5a66926a
ZY
6822#define UCODE_READY_TIMEOUT (2 * HZ)
6823
bb8c093b 6824static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6825{
bb8c093b 6826 struct iwl3945_priv *priv = hw->priv;
5a66926a 6827 int ret;
b481de9c
ZY
6828
6829 IWL_DEBUG_MAC80211("enter\n");
6830
5a66926a
ZY
6831 if (pci_enable_device(priv->pci_dev)) {
6832 IWL_ERROR("Fail to pci_enable_device\n");
6833 return -ENODEV;
6834 }
6835 pci_restore_state(priv->pci_dev);
6836 pci_enable_msi(priv->pci_dev);
6837
6838 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6839 DRV_NAME, priv);
6840 if (ret) {
6841 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6842 goto out_disable_msi;
6843 }
6844
b481de9c
ZY
6845 /* we should be verifying the device is ready to be opened */
6846 mutex_lock(&priv->mutex);
6847
5a66926a
ZY
6848 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6849 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6850 * ucode filename and max sizes are card-specific. */
6851
6852 if (!priv->ucode_code.len) {
6853 ret = iwl3945_read_ucode(priv);
6854 if (ret) {
6855 IWL_ERROR("Could not read microcode: %d\n", ret);
6856 mutex_unlock(&priv->mutex);
6857 goto out_release_irq;
6858 }
6859 }
b481de9c 6860
e655b9f0 6861 ret = __iwl3945_up(priv);
b481de9c
ZY
6862
6863 mutex_unlock(&priv->mutex);
5a66926a 6864
e655b9f0
ZY
6865 if (ret)
6866 goto out_release_irq;
6867
6868 IWL_DEBUG_INFO("Start UP work.\n");
6869
6870 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6871 return 0;
6872
5a66926a
ZY
6873 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6874 * mac80211 will not be run successfully. */
6875 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6876 test_bit(STATUS_READY, &priv->status),
6877 UCODE_READY_TIMEOUT);
6878 if (!ret) {
6879 if (!test_bit(STATUS_READY, &priv->status)) {
6880 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6881 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6882 ret = -ETIMEDOUT;
6883 goto out_release_irq;
6884 }
6885 }
6886
e655b9f0 6887 priv->is_open = 1;
b481de9c
ZY
6888 IWL_DEBUG_MAC80211("leave\n");
6889 return 0;
5a66926a
ZY
6890
6891out_release_irq:
6892 free_irq(priv->pci_dev->irq, priv);
6893out_disable_msi:
6894 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY
6895 pci_disable_device(priv->pci_dev);
6896 priv->is_open = 0;
6897 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6898 return ret;
b481de9c
ZY
6899}
6900
bb8c093b 6901static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6902{
bb8c093b 6903 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6904
6905 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6906
e655b9f0
ZY
6907 if (!priv->is_open) {
6908 IWL_DEBUG_MAC80211("leave - skip\n");
6909 return;
6910 }
6911
b481de9c 6912 priv->is_open = 0;
5a66926a
ZY
6913
6914 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY
6915 /* stop mac, cancel any scan request and clear
6916 * RXON_FILTER_ASSOC_MSK BIT
6917 */
5a66926a
ZY
6918 mutex_lock(&priv->mutex);
6919 iwl3945_scan_cancel_timeout(priv, 100);
6920 cancel_delayed_work(&priv->post_associate);
fde3571f 6921 mutex_unlock(&priv->mutex);
fde3571f
MA
6922 }
6923
5a66926a
ZY
6924 iwl3945_down(priv);
6925
6926 flush_workqueue(priv->workqueue);
6927 free_irq(priv->pci_dev->irq, priv);
6928 pci_disable_msi(priv->pci_dev);
6929 pci_save_state(priv->pci_dev);
6930 pci_disable_device(priv->pci_dev);
6ef89d0a 6931
b481de9c 6932 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6933}
6934
bb8c093b 6935static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY
6936 struct ieee80211_tx_control *ctl)
6937{
bb8c093b 6938 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6939
6940 IWL_DEBUG_MAC80211("enter\n");
6941
6942 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6943 IWL_DEBUG_MAC80211("leave - monitor\n");
6944 return -1;
6945 }
6946
6947 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
8318d78a 6948 ctl->tx_rate->bitrate);
b481de9c 6949
bb8c093b 6950 if (iwl3945_tx_skb(priv, skb, ctl))
b481de9c
ZY
6951 dev_kfree_skb_any(skb);
6952
6953 IWL_DEBUG_MAC80211("leave\n");
6954 return 0;
6955}
6956
bb8c093b 6957static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6958 struct ieee80211_if_init_conf *conf)
6959{
bb8c093b 6960 struct iwl3945_priv *priv = hw->priv;
b481de9c 6961 unsigned long flags;
0795af57 6962 DECLARE_MAC_BUF(mac);
b481de9c 6963
32bfd35d 6964 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6965
32bfd35d
JB
6966 if (priv->vif) {
6967 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6968 return -EOPNOTSUPP;
b481de9c
ZY
6969 }
6970
6971 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6972 priv->vif = conf->vif;
b481de9c
ZY
6973
6974 spin_unlock_irqrestore(&priv->lock, flags);
6975
6976 mutex_lock(&priv->mutex);
864792e3
TW
6977
6978 if (conf->mac_addr) {
6979 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6980 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6981 }
6982
5a66926a
ZY
6983 if (iwl3945_is_ready(priv))
6984 iwl3945_set_mode(priv, conf->type);
b481de9c 6985
b481de9c
ZY
6986 mutex_unlock(&priv->mutex);
6987
5a66926a 6988 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6989 return 0;
6990}
6991
6992/**
bb8c093b 6993 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY
6994 *
6995 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6996 * be set inappropriately and the driver currently sets the hardware up to
6997 * use it whenever needed.
6998 */
bb8c093b 6999static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 7000{
bb8c093b
CH
7001 struct iwl3945_priv *priv = hw->priv;
7002 const struct iwl3945_channel_info *ch_info;
b481de9c 7003 unsigned long flags;
76bb77e0 7004 int ret = 0;
b481de9c
ZY
7005
7006 mutex_lock(&priv->mutex);
8318d78a 7007 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 7008
12342c47
ZY
7009 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
7010
bb8c093b 7011 if (!iwl3945_is_ready(priv)) {
b481de9c 7012 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY
7013 ret = -EIO;
7014 goto out;
b481de9c
ZY
7015 }
7016
bb8c093b 7017 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 7018 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY
7019 IWL_DEBUG_MAC80211("leave - scanning\n");
7020 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7021 mutex_unlock(&priv->mutex);
a0646470 7022 return 0;
b481de9c
ZY
7023 }
7024
7025 spin_lock_irqsave(&priv->lock, flags);
7026
8318d78a
JB
7027 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
7028 conf->channel->hw_value);
b481de9c
ZY
7029 if (!is_channel_valid(ch_info)) {
7030 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
8318d78a 7031 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY
7032 IWL_DEBUG_MAC80211("leave - invalid channel\n");
7033 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY
7034 ret = -EINVAL;
7035 goto out;
b481de9c
ZY
7036 }
7037
8318d78a 7038 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 7039
8318d78a 7040 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY
7041
7042 /* The list of supported rates and rate mask can be different
7043 * for each phymode; since the phymode may have changed, reset
7044 * the rate mask to what mac80211 lists */
bb8c093b 7045 iwl3945_set_rate(priv);
b481de9c
ZY
7046
7047 spin_unlock_irqrestore(&priv->lock, flags);
7048
7049#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7050 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 7051 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 7052 goto out;
b481de9c
ZY
7053 }
7054#endif
7055
bb8c093b 7056 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY
7057
7058 if (!conf->radio_enabled) {
7059 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 7060 goto out;
b481de9c
ZY
7061 }
7062
bb8c093b 7063 if (iwl3945_is_rfkill(priv)) {
b481de9c 7064 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY
7065 ret = -EIO;
7066 goto out;
b481de9c
ZY
7067 }
7068
bb8c093b 7069 iwl3945_set_rate(priv);
b481de9c
ZY
7070
7071 if (memcmp(&priv->active_rxon,
7072 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 7073 iwl3945_commit_rxon(priv);
b481de9c
ZY
7074 else
7075 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
7076
7077 IWL_DEBUG_MAC80211("leave\n");
7078
76bb77e0 7079out:
a0646470 7080 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 7081 mutex_unlock(&priv->mutex);
76bb77e0 7082 return ret;
b481de9c
ZY
7083}
7084
bb8c093b 7085static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY
7086{
7087 int rc = 0;
7088
d986bcd1 7089 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
7090 return;
7091
7092 /* The following should be done only at AP bring up */
7093 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
7094
7095 /* RXON - unassoc (to set timing command) */
7096 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7097 iwl3945_commit_rxon(priv);
b481de9c
ZY
7098
7099 /* RXON Timing */
bb8c093b
CH
7100 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
7101 iwl3945_setup_rxon_timing(priv);
7102 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
7103 sizeof(priv->rxon_timing), &priv->rxon_timing);
7104 if (rc)
7105 IWL_WARNING("REPLY_RXON_TIMING failed - "
7106 "Attempting to continue.\n");
7107
7108 /* FIXME: what should be the assoc_id for AP? */
7109 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7110 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7111 priv->staging_rxon.flags |=
7112 RXON_FLG_SHORT_PREAMBLE_MSK;
7113 else
7114 priv->staging_rxon.flags &=
7115 ~RXON_FLG_SHORT_PREAMBLE_MSK;
7116
7117 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7118 if (priv->assoc_capability &
7119 WLAN_CAPABILITY_SHORT_SLOT_TIME)
7120 priv->staging_rxon.flags |=
7121 RXON_FLG_SHORT_SLOT_MSK;
7122 else
7123 priv->staging_rxon.flags &=
7124 ~RXON_FLG_SHORT_SLOT_MSK;
7125
7126 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7127 priv->staging_rxon.flags &=
7128 ~RXON_FLG_SHORT_SLOT_MSK;
7129 }
7130 /* restore RXON assoc */
7131 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH
7132 iwl3945_commit_rxon(priv);
7133 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 7134 }
bb8c093b 7135 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
7136
7137 /* FIXME - we need to add code here to detect a totally new
7138 * configuration, reset the AP, unassoc, rxon timing, assoc,
7139 * clear sta table, add BCAST sta... */
7140}
7141
32bfd35d
JB
7142static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
7143 struct ieee80211_vif *vif,
b481de9c
ZY
7144 struct ieee80211_if_conf *conf)
7145{
bb8c093b 7146 struct iwl3945_priv *priv = hw->priv;
0795af57 7147 DECLARE_MAC_BUF(mac);
b481de9c
ZY
7148 unsigned long flags;
7149 int rc;
7150
7151 if (conf == NULL)
7152 return -EIO;
7153
4150c572
JB
7154 /* XXX: this MUST use conf->mac_addr */
7155
b481de9c
ZY
7156 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
7157 (!conf->beacon || !conf->ssid_len)) {
7158 IWL_DEBUG_MAC80211
7159 ("Leaving in AP mode because HostAPD is not ready.\n");
7160 return 0;
7161 }
7162
5a66926a
ZY
7163 if (!iwl3945_is_alive(priv))
7164 return -EAGAIN;
7165
b481de9c
ZY
7166 mutex_lock(&priv->mutex);
7167
b481de9c 7168 if (conf->bssid)
0795af57
JP
7169 IWL_DEBUG_MAC80211("bssid: %s\n",
7170 print_mac(mac, conf->bssid));
b481de9c 7171
4150c572
JB
7172/*
7173 * very dubious code was here; the probe filtering flag is never set:
7174 *
b481de9c
ZY
7175 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
7176 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572
JB
7177 */
7178 if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
b481de9c
ZY
7179 IWL_DEBUG_MAC80211("leave - scanning\n");
7180 mutex_unlock(&priv->mutex);
7181 return 0;
7182 }
7183
32bfd35d
JB
7184 if (priv->vif != vif) {
7185 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b481de9c
ZY
7186 mutex_unlock(&priv->mutex);
7187 return 0;
7188 }
7189
7190 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7191 if (!conf->bssid) {
7192 conf->bssid = priv->mac_addr;
7193 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP
7194 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
7195 print_mac(mac, conf->bssid));
b481de9c
ZY
7196 }
7197 if (priv->ibss_beacon)
7198 dev_kfree_skb(priv->ibss_beacon);
7199
7200 priv->ibss_beacon = conf->beacon;
7201 }
7202
fde3571f
MA
7203 if (iwl3945_is_rfkill(priv))
7204 goto done;
7205
b481de9c
ZY
7206 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
7207 !is_multicast_ether_addr(conf->bssid)) {
7208 /* If there is currently a HW scan going on in the background
7209 * then we need to cancel it else the RXON below will fail. */
bb8c093b 7210 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY
7211 IWL_WARNING("Aborted scan still in progress "
7212 "after 100ms\n");
7213 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
7214 mutex_unlock(&priv->mutex);
7215 return -EAGAIN;
7216 }
7217 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
7218
7219 /* TODO: Audit driver for usage of these members and see
7220 * if mac80211 deprecates them (priv->bssid looks like it
7221 * shouldn't be there, but I haven't scanned the IBSS code
7222 * to verify) - jpk */
7223 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
7224
7225 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7226 iwl3945_config_ap(priv);
b481de9c 7227 else {
bb8c093b 7228 rc = iwl3945_commit_rxon(priv);
b481de9c 7229 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 7230 iwl3945_add_station(priv,
556f8db7 7231 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY
7232 }
7233
7234 } else {
bb8c093b 7235 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 7236 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7237 iwl3945_commit_rxon(priv);
b481de9c
ZY
7238 }
7239
fde3571f 7240 done:
b481de9c
ZY
7241 spin_lock_irqsave(&priv->lock, flags);
7242 if (!conf->ssid_len)
7243 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7244 else
7245 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7246
7247 priv->essid_len = conf->ssid_len;
7248 spin_unlock_irqrestore(&priv->lock, flags);
7249
7250 IWL_DEBUG_MAC80211("leave\n");
7251 mutex_unlock(&priv->mutex);
7252
7253 return 0;
7254}
7255
bb8c093b 7256static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB
7257 unsigned int changed_flags,
7258 unsigned int *total_flags,
7259 int mc_count, struct dev_addr_list *mc_list)
7260{
7261 /*
7262 * XXX: dummy
bb8c093b 7263 * see also iwl3945_connection_init_rx_config
4150c572
JB
7264 */
7265 *total_flags = 0;
7266}
7267
bb8c093b 7268static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
7269 struct ieee80211_if_init_conf *conf)
7270{
bb8c093b 7271 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7272
7273 IWL_DEBUG_MAC80211("enter\n");
7274
7275 mutex_lock(&priv->mutex);
6ef89d0a 7276
fde3571f
MA
7277 if (iwl3945_is_ready_rf(priv)) {
7278 iwl3945_scan_cancel_timeout(priv, 100);
7279 cancel_delayed_work(&priv->post_associate);
7280 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7281 iwl3945_commit_rxon(priv);
7282 }
32bfd35d
JB
7283 if (priv->vif == conf->vif) {
7284 priv->vif = NULL;
b481de9c
ZY
7285 memset(priv->bssid, 0, ETH_ALEN);
7286 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7287 priv->essid_len = 0;
7288 }
7289 mutex_unlock(&priv->mutex);
7290
7291 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
7292}
7293
bb8c093b 7294static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY
7295{
7296 int rc = 0;
7297 unsigned long flags;
bb8c093b 7298 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7299
7300 IWL_DEBUG_MAC80211("enter\n");
7301
15e869d8 7302 mutex_lock(&priv->mutex);
b481de9c
ZY
7303 spin_lock_irqsave(&priv->lock, flags);
7304
bb8c093b 7305 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7306 rc = -EIO;
7307 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7308 goto out_unlock;
7309 }
7310
7311 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7312 rc = -EIO;
7313 IWL_ERROR("ERROR: APs don't scan\n");
7314 goto out_unlock;
7315 }
7316
7878a5a4
MA
7317 /* we don't schedule scan within next_scan_jiffies period */
7318 if (priv->next_scan_jiffies &&
7319 time_after(priv->next_scan_jiffies, jiffies)) {
7320 rc = -EAGAIN;
7321 goto out_unlock;
7322 }
b481de9c 7323 /* if we just finished scan ask for delay */
7878a5a4
MA
7324 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7325 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY
7326 rc = -EAGAIN;
7327 goto out_unlock;
7328 }
7329 if (len) {
7878a5a4 7330 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7331 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY
7332
7333 priv->one_direct_scan = 1;
7334 priv->direct_ssid_len = (u8)
7335 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7336 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA
7337 } else
7338 priv->one_direct_scan = 0;
b481de9c 7339
bb8c093b 7340 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY
7341
7342 IWL_DEBUG_MAC80211("leave\n");
7343
7344out_unlock:
7345 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7346 mutex_unlock(&priv->mutex);
b481de9c
ZY
7347
7348 return rc;
7349}
7350
bb8c093b 7351static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY
7352 const u8 *local_addr, const u8 *addr,
7353 struct ieee80211_key_conf *key)
7354{
bb8c093b 7355 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7356 int rc = 0;
7357 u8 sta_id;
7358
7359 IWL_DEBUG_MAC80211("enter\n");
7360
bb8c093b 7361 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY
7362 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7363 return -EOPNOTSUPP;
7364 }
7365
7366 if (is_zero_ether_addr(addr))
7367 /* only support pairwise keys */
7368 return -EOPNOTSUPP;
7369
bb8c093b 7370 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7371 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP
7372 DECLARE_MAC_BUF(mac);
7373
7374 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7375 print_mac(mac, addr));
b481de9c
ZY
7376 return -EINVAL;
7377 }
7378
7379 mutex_lock(&priv->mutex);
7380
bb8c093b 7381 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7382
b481de9c
ZY
7383 switch (cmd) {
7384 case SET_KEY:
bb8c093b 7385 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7386 if (!rc) {
bb8c093b
CH
7387 iwl3945_set_rxon_hwcrypto(priv, 1);
7388 iwl3945_commit_rxon(priv);
b481de9c
ZY
7389 key->hw_key_idx = sta_id;
7390 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7391 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7392 }
7393 break;
7394 case DISABLE_KEY:
bb8c093b 7395 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7396 if (!rc) {
bb8c093b
CH
7397 iwl3945_set_rxon_hwcrypto(priv, 0);
7398 iwl3945_commit_rxon(priv);
b481de9c
ZY
7399 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7400 }
7401 break;
7402 default:
7403 rc = -EINVAL;
7404 }
7405
7406 IWL_DEBUG_MAC80211("leave\n");
7407 mutex_unlock(&priv->mutex);
7408
7409 return rc;
7410}
7411
bb8c093b 7412static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY
7413 const struct ieee80211_tx_queue_params *params)
7414{
bb8c093b 7415 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7416 unsigned long flags;
7417 int q;
b481de9c
ZY
7418
7419 IWL_DEBUG_MAC80211("enter\n");
7420
bb8c093b 7421 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7422 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7423 return -EIO;
7424 }
7425
7426 if (queue >= AC_NUM) {
7427 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7428 return 0;
7429 }
7430
b481de9c
ZY
7431 if (!priv->qos_data.qos_enable) {
7432 priv->qos_data.qos_active = 0;
7433 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7434 return 0;
7435 }
7436 q = AC_NUM - 1 - queue;
7437
7438 spin_lock_irqsave(&priv->lock, flags);
7439
7440 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7441 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7442 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7443 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7444 cpu_to_le16((params->txop * 32));
b481de9c
ZY
7445
7446 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7447 priv->qos_data.qos_active = 1;
7448
7449 spin_unlock_irqrestore(&priv->lock, flags);
7450
7451 mutex_lock(&priv->mutex);
7452 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH
7453 iwl3945_activate_qos(priv, 1);
7454 else if (priv->assoc_id && iwl3945_is_associated(priv))
7455 iwl3945_activate_qos(priv, 0);
b481de9c
ZY
7456
7457 mutex_unlock(&priv->mutex);
7458
b481de9c
ZY
7459 IWL_DEBUG_MAC80211("leave\n");
7460 return 0;
7461}
7462
bb8c093b 7463static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7464 struct ieee80211_tx_queue_stats *stats)
7465{
bb8c093b 7466 struct iwl3945_priv *priv = hw->priv;
b481de9c 7467 int i, avail;
bb8c093b
CH
7468 struct iwl3945_tx_queue *txq;
7469 struct iwl3945_queue *q;
b481de9c
ZY
7470 unsigned long flags;
7471
7472 IWL_DEBUG_MAC80211("enter\n");
7473
bb8c093b 7474 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7475 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7476 return -EIO;
7477 }
7478
7479 spin_lock_irqsave(&priv->lock, flags);
7480
7481 for (i = 0; i < AC_NUM; i++) {
7482 txq = &priv->txq[i];
7483 q = &txq->q;
bb8c093b 7484 avail = iwl3945_queue_space(q);
b481de9c
ZY
7485
7486 stats->data[i].len = q->n_window - avail;
7487 stats->data[i].limit = q->n_window - q->high_mark;
7488 stats->data[i].count = q->n_window;
7489
7490 }
7491 spin_unlock_irqrestore(&priv->lock, flags);
7492
7493 IWL_DEBUG_MAC80211("leave\n");
7494
7495 return 0;
7496}
7497
bb8c093b 7498static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7499 struct ieee80211_low_level_stats *stats)
7500{
7501 IWL_DEBUG_MAC80211("enter\n");
7502 IWL_DEBUG_MAC80211("leave\n");
7503
7504 return 0;
7505}
7506
bb8c093b 7507static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY
7508{
7509 IWL_DEBUG_MAC80211("enter\n");
7510 IWL_DEBUG_MAC80211("leave\n");
7511
7512 return 0;
7513}
7514
bb8c093b 7515static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7516{
bb8c093b 7517 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7518 unsigned long flags;
7519
7520 mutex_lock(&priv->mutex);
7521 IWL_DEBUG_MAC80211("enter\n");
7522
bb8c093b 7523 iwl3945_reset_qos(priv);
292ae174 7524
b481de9c
ZY
7525 cancel_delayed_work(&priv->post_associate);
7526
7527 spin_lock_irqsave(&priv->lock, flags);
7528 priv->assoc_id = 0;
7529 priv->assoc_capability = 0;
7530 priv->call_post_assoc_from_beacon = 0;
7531
7532 /* new association get rid of ibss beacon skb */
7533 if (priv->ibss_beacon)
7534 dev_kfree_skb(priv->ibss_beacon);
7535
7536 priv->ibss_beacon = NULL;
7537
7538 priv->beacon_int = priv->hw->conf.beacon_int;
7539 priv->timestamp1 = 0;
7540 priv->timestamp0 = 0;
7541 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7542 priv->beacon_int = 0;
7543
7544 spin_unlock_irqrestore(&priv->lock, flags);
7545
fde3571f
MA
7546 if (!iwl3945_is_ready_rf(priv)) {
7547 IWL_DEBUG_MAC80211("leave - not ready\n");
7548 mutex_unlock(&priv->mutex);
7549 return;
7550 }
7551
15e869d8
MA
7552 /* we are restarting association process
7553 * clear RXON_FILTER_ASSOC_MSK bit
7554 */
7555 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7556 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7557 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7558 iwl3945_commit_rxon(priv);
15e869d8
MA
7559 }
7560
b481de9c
ZY
7561 /* Per mac80211.h: This is only used in IBSS mode... */
7562 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7563
b481de9c
ZY
7564 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7565 mutex_unlock(&priv->mutex);
7566 return;
b481de9c
ZY
7567 }
7568
7569 priv->only_active_channel = 0;
7570
bb8c093b 7571 iwl3945_set_rate(priv);
b481de9c
ZY
7572
7573 mutex_unlock(&priv->mutex);
7574
7575 IWL_DEBUG_MAC80211("leave\n");
7576
7577}
7578
bb8c093b 7579static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY
7580 struct ieee80211_tx_control *control)
7581{
bb8c093b 7582 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7583 unsigned long flags;
7584
7585 mutex_lock(&priv->mutex);
7586 IWL_DEBUG_MAC80211("enter\n");
7587
bb8c093b 7588 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7589 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7590 mutex_unlock(&priv->mutex);
7591 return -EIO;
7592 }
7593
7594 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7595 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7596 mutex_unlock(&priv->mutex);
7597 return -EIO;
7598 }
7599
7600 spin_lock_irqsave(&priv->lock, flags);
7601
7602 if (priv->ibss_beacon)
7603 dev_kfree_skb(priv->ibss_beacon);
7604
7605 priv->ibss_beacon = skb;
7606
7607 priv->assoc_id = 0;
7608
7609 IWL_DEBUG_MAC80211("leave\n");
7610 spin_unlock_irqrestore(&priv->lock, flags);
7611
bb8c093b 7612 iwl3945_reset_qos(priv);
b481de9c
ZY
7613
7614 queue_work(priv->workqueue, &priv->post_associate.work);
7615
7616 mutex_unlock(&priv->mutex);
7617
7618 return 0;
7619}
7620
7621/*****************************************************************************
7622 *
7623 * sysfs attributes
7624 *
7625 *****************************************************************************/
7626
c8b0e6e1 7627#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
7628
7629/*
7630 * The following adds a new attribute to the sysfs representation
7631 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7632 * used for controlling the debug level.
7633 *
7634 * See the level definitions in iwl for details.
7635 */
7636
7637static ssize_t show_debug_level(struct device_driver *d, char *buf)
7638{
bb8c093b 7639 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY
7640}
7641static ssize_t store_debug_level(struct device_driver *d,
7642 const char *buf, size_t count)
7643{
7644 char *p = (char *)buf;
7645 u32 val;
7646
7647 val = simple_strtoul(p, &p, 0);
7648 if (p == buf)
7649 printk(KERN_INFO DRV_NAME
7650 ": %s is not in hex or decimal form.\n", buf);
7651 else
bb8c093b 7652 iwl3945_debug_level = val;
b481de9c
ZY
7653
7654 return strnlen(buf, count);
7655}
7656
7657static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7658 show_debug_level, store_debug_level);
7659
c8b0e6e1 7660#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY
7661
7662static ssize_t show_rf_kill(struct device *d,
7663 struct device_attribute *attr, char *buf)
7664{
7665 /*
7666 * 0 - RF kill not enabled
7667 * 1 - SW based RF kill active (sysfs)
7668 * 2 - HW based RF kill active
7669 * 3 - Both HW and SW based RF kill active
7670 */
bb8c093b 7671 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7672 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7673 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7674
7675 return sprintf(buf, "%i\n", val);
7676}
7677
7678static ssize_t store_rf_kill(struct device *d,
7679 struct device_attribute *attr,
7680 const char *buf, size_t count)
7681{
bb8c093b 7682 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7683
7684 mutex_lock(&priv->mutex);
bb8c093b 7685 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY
7686 mutex_unlock(&priv->mutex);
7687
7688 return count;
7689}
7690
7691static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7692
7693static ssize_t show_temperature(struct device *d,
7694 struct device_attribute *attr, char *buf)
7695{
bb8c093b 7696 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7697
bb8c093b 7698 if (!iwl3945_is_alive(priv))
b481de9c
ZY
7699 return -EAGAIN;
7700
bb8c093b 7701 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
7702}
7703
7704static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7705
7706static ssize_t show_rs_window(struct device *d,
7707 struct device_attribute *attr,
7708 char *buf)
7709{
bb8c093b
CH
7710 struct iwl3945_priv *priv = d->driver_data;
7711 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY
7712}
7713static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7714
7715static ssize_t show_tx_power(struct device *d,
7716 struct device_attribute *attr, char *buf)
7717{
bb8c093b 7718 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7719 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7720}
7721
7722static ssize_t store_tx_power(struct device *d,
7723 struct device_attribute *attr,
7724 const char *buf, size_t count)
7725{
bb8c093b 7726 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7727 char *p = (char *)buf;
7728 u32 val;
7729
7730 val = simple_strtoul(p, &p, 10);
7731 if (p == buf)
7732 printk(KERN_INFO DRV_NAME
7733 ": %s is not in decimal form.\n", buf);
7734 else
bb8c093b 7735 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
7736
7737 return count;
7738}
7739
7740static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7741
7742static ssize_t show_flags(struct device *d,
7743 struct device_attribute *attr, char *buf)
7744{
bb8c093b 7745 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7746
7747 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7748}
7749
7750static ssize_t store_flags(struct device *d,
7751 struct device_attribute *attr,
7752 const char *buf, size_t count)
7753{
bb8c093b 7754 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7755 u32 flags = simple_strtoul(buf, NULL, 0);
7756
7757 mutex_lock(&priv->mutex);
7758 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7759 /* Cancel any currently running scans... */
bb8c093b 7760 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7761 IWL_WARNING("Could not cancel scan.\n");
7762 else {
7763 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7764 flags);
7765 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7766 iwl3945_commit_rxon(priv);
b481de9c
ZY
7767 }
7768 }
7769 mutex_unlock(&priv->mutex);
7770
7771 return count;
7772}
7773
7774static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7775
7776static ssize_t show_filter_flags(struct device *d,
7777 struct device_attribute *attr, char *buf)
7778{
bb8c093b 7779 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7780
7781 return sprintf(buf, "0x%04X\n",
7782 le32_to_cpu(priv->active_rxon.filter_flags));
7783}
7784
7785static ssize_t store_filter_flags(struct device *d,
7786 struct device_attribute *attr,
7787 const char *buf, size_t count)
7788{
bb8c093b 7789 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7790 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7791
7792 mutex_lock(&priv->mutex);
7793 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7794 /* Cancel any currently running scans... */
bb8c093b 7795 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7796 IWL_WARNING("Could not cancel scan.\n");
7797 else {
7798 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7799 "0x%04X\n", filter_flags);
7800 priv->staging_rxon.filter_flags =
7801 cpu_to_le32(filter_flags);
bb8c093b 7802 iwl3945_commit_rxon(priv);
b481de9c
ZY
7803 }
7804 }
7805 mutex_unlock(&priv->mutex);
7806
7807 return count;
7808}
7809
7810static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7811 store_filter_flags);
7812
c8b0e6e1 7813#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7814
7815static ssize_t show_measurement(struct device *d,
7816 struct device_attribute *attr, char *buf)
7817{
bb8c093b
CH
7818 struct iwl3945_priv *priv = dev_get_drvdata(d);
7819 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY
7820 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7821 u8 *data = (u8 *) & measure_report;
7822 unsigned long flags;
7823
7824 spin_lock_irqsave(&priv->lock, flags);
7825 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7826 spin_unlock_irqrestore(&priv->lock, flags);
7827 return 0;
7828 }
7829 memcpy(&measure_report, &priv->measure_report, size);
7830 priv->measurement_status = 0;
7831 spin_unlock_irqrestore(&priv->lock, flags);
7832
7833 while (size && (PAGE_SIZE - len)) {
7834 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7835 PAGE_SIZE - len, 1);
7836 len = strlen(buf);
7837 if (PAGE_SIZE - len)
7838 buf[len++] = '\n';
7839
7840 ofs += 16;
7841 size -= min(size, 16U);
7842 }
7843
7844 return len;
7845}
7846
7847static ssize_t store_measurement(struct device *d,
7848 struct device_attribute *attr,
7849 const char *buf, size_t count)
7850{
bb8c093b 7851 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7852 struct ieee80211_measurement_params params = {
7853 .channel = le16_to_cpu(priv->active_rxon.channel),
7854 .start_time = cpu_to_le64(priv->last_tsf),
7855 .duration = cpu_to_le16(1),
7856 };
7857 u8 type = IWL_MEASURE_BASIC;
7858 u8 buffer[32];
7859 u8 channel;
7860
7861 if (count) {
7862 char *p = buffer;
7863 strncpy(buffer, buf, min(sizeof(buffer), count));
7864 channel = simple_strtoul(p, NULL, 0);
7865 if (channel)
7866 params.channel = channel;
7867
7868 p = buffer;
7869 while (*p && *p != ' ')
7870 p++;
7871 if (*p)
7872 type = simple_strtoul(p + 1, NULL, 0);
7873 }
7874
7875 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7876 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7877 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
7878
7879 return count;
7880}
7881
7882static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7883 show_measurement, store_measurement);
c8b0e6e1 7884#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c
ZY
7885
7886static ssize_t show_rate(struct device *d,
7887 struct device_attribute *attr, char *buf)
7888{
bb8c093b 7889 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7890 unsigned long flags;
7891 int i;
7892
7893 spin_lock_irqsave(&priv->sta_lock, flags);
7894 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
7895 i = priv->stations[IWL_AP_ID].current_rate.s.rate;
7896 else
7897 i = priv->stations[IWL_STA_ID].current_rate.s.rate;
7898 spin_unlock_irqrestore(&priv->sta_lock, flags);
7899
bb8c093b 7900 i = iwl3945_rate_index_from_plcp(i);
b481de9c
ZY
7901 if (i == -1)
7902 return sprintf(buf, "0\n");
7903
7904 return sprintf(buf, "%d%s\n",
bb8c093b
CH
7905 (iwl3945_rates[i].ieee >> 1),
7906 (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
b481de9c
ZY
7907}
7908
7909static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
7910
7911static ssize_t store_retry_rate(struct device *d,
7912 struct device_attribute *attr,
7913 const char *buf, size_t count)
7914{
bb8c093b 7915 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7916
7917 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7918 if (priv->retry_rate <= 0)
7919 priv->retry_rate = 1;
7920
7921 return count;
7922}
7923
7924static ssize_t show_retry_rate(struct device *d,
7925 struct device_attribute *attr, char *buf)
7926{
bb8c093b 7927 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7928 return sprintf(buf, "%d", priv->retry_rate);
7929}
7930
7931static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7932 store_retry_rate);
7933
7934static ssize_t store_power_level(struct device *d,
7935 struct device_attribute *attr,
7936 const char *buf, size_t count)
7937{
bb8c093b 7938 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7939 int rc;
7940 int mode;
7941
7942 mode = simple_strtoul(buf, NULL, 0);
7943 mutex_lock(&priv->mutex);
7944
bb8c093b 7945 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY
7946 rc = -EAGAIN;
7947 goto out;
7948 }
7949
7950 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7951 mode = IWL_POWER_AC;
7952 else
7953 mode |= IWL_POWER_ENABLED;
7954
7955 if (mode != priv->power_mode) {
bb8c093b 7956 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY
7957 if (rc) {
7958 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7959 goto out;
7960 }
7961 priv->power_mode = mode;
7962 }
7963
7964 rc = count;
7965
7966 out:
7967 mutex_unlock(&priv->mutex);
7968 return rc;
7969}
7970
7971#define MAX_WX_STRING 80
7972
7973/* Values are in microsecond */
7974static const s32 timeout_duration[] = {
7975 350000,
7976 250000,
7977 75000,
7978 37000,
7979 25000,
7980};
7981static const s32 period_duration[] = {
7982 400000,
7983 700000,
7984 1000000,
7985 1000000,
7986 1000000
7987};
7988
7989static ssize_t show_power_level(struct device *d,
7990 struct device_attribute *attr, char *buf)
7991{
bb8c093b 7992 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7993 int level = IWL_POWER_LEVEL(priv->power_mode);
7994 char *p = buf;
7995
7996 p += sprintf(p, "%d ", level);
7997 switch (level) {
7998 case IWL_POWER_MODE_CAM:
7999 case IWL_POWER_AC:
8000 p += sprintf(p, "(AC)");
8001 break;
8002 case IWL_POWER_BATTERY:
8003 p += sprintf(p, "(BATTERY)");
8004 break;
8005 default:
8006 p += sprintf(p,
8007 "(Timeout %dms, Period %dms)",
8008 timeout_duration[level - 1] / 1000,
8009 period_duration[level - 1] / 1000);
8010 }
8011
8012 if (!(priv->power_mode & IWL_POWER_ENABLED))
8013 p += sprintf(p, " OFF\n");
8014 else
8015 p += sprintf(p, " \n");
8016
8017 return (p - buf + 1);
8018
8019}
8020
8021static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
8022 store_power_level);
8023
8024static ssize_t show_channels(struct device *d,
8025 struct device_attribute *attr, char *buf)
8026{
8318d78a
JB
8027 /* all this shit doesn't belong into sysfs anyway */
8028 return 0;
b481de9c
ZY
8029}
8030
8031static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
8032
8033static ssize_t show_statistics(struct device *d,
8034 struct device_attribute *attr, char *buf)
8035{
bb8c093b
CH
8036 struct iwl3945_priv *priv = dev_get_drvdata(d);
8037 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY
8038 u32 len = 0, ofs = 0;
8039 u8 *data = (u8 *) & priv->statistics;
8040 int rc = 0;
8041
bb8c093b 8042 if (!iwl3945_is_alive(priv))
b481de9c
ZY
8043 return -EAGAIN;
8044
8045 mutex_lock(&priv->mutex);
bb8c093b 8046 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY
8047 mutex_unlock(&priv->mutex);
8048
8049 if (rc) {
8050 len = sprintf(buf,
8051 "Error sending statistics request: 0x%08X\n", rc);
8052 return len;
8053 }
8054
8055 while (size && (PAGE_SIZE - len)) {
8056 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8057 PAGE_SIZE - len, 1);
8058 len = strlen(buf);
8059 if (PAGE_SIZE - len)
8060 buf[len++] = '\n';
8061
8062 ofs += 16;
8063 size -= min(size, 16U);
8064 }
8065
8066 return len;
8067}
8068
8069static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
8070
8071static ssize_t show_antenna(struct device *d,
8072 struct device_attribute *attr, char *buf)
8073{
bb8c093b 8074 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 8075
bb8c093b 8076 if (!iwl3945_is_alive(priv))
b481de9c
ZY
8077 return -EAGAIN;
8078
8079 return sprintf(buf, "%d\n", priv->antenna);
8080}
8081
8082static ssize_t store_antenna(struct device *d,
8083 struct device_attribute *attr,
8084 const char *buf, size_t count)
8085{
8086 int ant;
bb8c093b 8087 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
8088
8089 if (count == 0)
8090 return 0;
8091
8092 if (sscanf(buf, "%1i", &ant) != 1) {
8093 IWL_DEBUG_INFO("not in hex or decimal form.\n");
8094 return count;
8095 }
8096
8097 if ((ant >= 0) && (ant <= 2)) {
8098 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 8099 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY
8100 } else
8101 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
8102
8103
8104 return count;
8105}
8106
8107static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
8108
8109static ssize_t show_status(struct device *d,
8110 struct device_attribute *attr, char *buf)
8111{
bb8c093b
CH
8112 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
8113 if (!iwl3945_is_alive(priv))
b481de9c
ZY
8114 return -EAGAIN;
8115 return sprintf(buf, "0x%08x\n", (int)priv->status);
8116}
8117
8118static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
8119
8120static ssize_t dump_error_log(struct device *d,
8121 struct device_attribute *attr,
8122 const char *buf, size_t count)
8123{
8124 char *p = (char *)buf;
8125
8126 if (p[0] == '1')
bb8c093b 8127 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY
8128
8129 return strnlen(buf, count);
8130}
8131
8132static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
8133
8134static ssize_t dump_event_log(struct device *d,
8135 struct device_attribute *attr,
8136 const char *buf, size_t count)
8137{
8138 char *p = (char *)buf;
8139
8140 if (p[0] == '1')
bb8c093b 8141 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY
8142
8143 return strnlen(buf, count);
8144}
8145
8146static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
8147
8148/*****************************************************************************
8149 *
8150 * driver setup and teardown
8151 *
8152 *****************************************************************************/
8153
bb8c093b 8154static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY
8155{
8156 priv->workqueue = create_workqueue(DRV_NAME);
8157
8158 init_waitqueue_head(&priv->wait_command_queue);
8159
bb8c093b
CH
8160 INIT_WORK(&priv->up, iwl3945_bg_up);
8161 INIT_WORK(&priv->restart, iwl3945_bg_restart);
8162 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
8163 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
8164 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
8165 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
8166 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
8167 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
8168 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
8169 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
8170 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
8171 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
8172
8173 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
8174
8175 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 8176 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
8177}
8178
bb8c093b 8179static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 8180{
bb8c093b 8181 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 8182
e47eb6ad 8183 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
8184 cancel_delayed_work(&priv->scan_check);
8185 cancel_delayed_work(&priv->alive_start);
8186 cancel_delayed_work(&priv->post_associate);
8187 cancel_work_sync(&priv->beacon_update);
8188}
8189
bb8c093b 8190static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
8191 &dev_attr_antenna.attr,
8192 &dev_attr_channels.attr,
8193 &dev_attr_dump_errors.attr,
8194 &dev_attr_dump_events.attr,
8195 &dev_attr_flags.attr,
8196 &dev_attr_filter_flags.attr,
c8b0e6e1 8197#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
8198 &dev_attr_measurement.attr,
8199#endif
8200 &dev_attr_power_level.attr,
8201 &dev_attr_rate.attr,
8202 &dev_attr_retry_rate.attr,
8203 &dev_attr_rf_kill.attr,
8204 &dev_attr_rs_window.attr,
8205 &dev_attr_statistics.attr,
8206 &dev_attr_status.attr,
8207 &dev_attr_temperature.attr,
b481de9c
ZY
8208 &dev_attr_tx_power.attr,
8209
8210 NULL
8211};
8212
bb8c093b 8213static struct attribute_group iwl3945_attribute_group = {
b481de9c 8214 .name = NULL, /* put in device directory */
bb8c093b 8215 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
8216};
8217
bb8c093b
CH
8218static struct ieee80211_ops iwl3945_hw_ops = {
8219 .tx = iwl3945_mac_tx,
8220 .start = iwl3945_mac_start,
8221 .stop = iwl3945_mac_stop,
8222 .add_interface = iwl3945_mac_add_interface,
8223 .remove_interface = iwl3945_mac_remove_interface,
8224 .config = iwl3945_mac_config,
8225 .config_interface = iwl3945_mac_config_interface,
8226 .configure_filter = iwl3945_configure_filter,
8227 .set_key = iwl3945_mac_set_key,
8228 .get_stats = iwl3945_mac_get_stats,
8229 .get_tx_stats = iwl3945_mac_get_tx_stats,
8230 .conf_tx = iwl3945_mac_conf_tx,
8231 .get_tsf = iwl3945_mac_get_tsf,
8232 .reset_tsf = iwl3945_mac_reset_tsf,
8233 .beacon_update = iwl3945_mac_beacon_update,
8234 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY
8235};
8236
bb8c093b 8237static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
8238{
8239 int err = 0;
8240 u32 pci_id;
bb8c093b 8241 struct iwl3945_priv *priv;
b481de9c
ZY
8242 struct ieee80211_hw *hw;
8243 int i;
5a66926a 8244 DECLARE_MAC_BUF(mac);
b481de9c 8245
6440adb5
BC
8246 /* Disabling hardware scan means that mac80211 will perform scans
8247 * "the hard way", rather than using device's scan. */
bb8c093b 8248 if (iwl3945_param_disable_hw_scan) {
b481de9c 8249 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 8250 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY
8251 }
8252
bb8c093b
CH
8253 if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
8254 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY
8255 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
8256 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
8257 err = -EINVAL;
8258 goto out;
8259 }
8260
8261 /* mac80211 allocates memory for this device instance, including
8262 * space for this driver's private structure */
bb8c093b 8263 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY
8264 if (hw == NULL) {
8265 IWL_ERROR("Can not allocate network device\n");
8266 err = -ENOMEM;
8267 goto out;
8268 }
8269 SET_IEEE80211_DEV(hw, &pdev->dev);
8270
f51359a8
JB
8271 hw->rate_control_algorithm = "iwl-3945-rs";
8272
b481de9c
ZY
8273 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8274 priv = hw->priv;
8275 priv->hw = hw;
8276
8277 priv->pci_dev = pdev;
6440adb5
BC
8278
8279 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8280 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8281#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8282 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY
8283 atomic_set(&priv->restrict_refcnt, 0);
8284#endif
8285 priv->retry_rate = 1;
8286
8287 priv->ibss_beacon = NULL;
8288
8289 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
8290 * the range of signal quality values that we'll provide.
8291 * Negative values for level/noise indicate that we'll provide dBm.
8292 * For WE, at least, non-0 values here *enable* display of values
8293 * in app (iwconfig). */
8294 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8295 hw->max_noise = -20; /* noise level, negative indicates dBm */
8296 hw->max_signal = 100; /* link quality indication (%) */
8297
8298 /* Tell mac80211 our Tx characteristics */
8299 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8300
6440adb5 8301 /* 4 EDCA QOS priorities */
b481de9c
ZY
8302 hw->queues = 4;
8303
8304 spin_lock_init(&priv->lock);
8305 spin_lock_init(&priv->power_data.lock);
8306 spin_lock_init(&priv->sta_lock);
8307 spin_lock_init(&priv->hcmd_lock);
8308
8309 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8310 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8311
8312 INIT_LIST_HEAD(&priv->free_frames);
8313
8314 mutex_init(&priv->mutex);
8315 if (pci_enable_device(pdev)) {
8316 err = -ENODEV;
8317 goto out_ieee80211_free_hw;
8318 }
8319
8320 pci_set_master(pdev);
8321
6440adb5 8322 /* Clear the driver's (not device's) station table */
bb8c093b 8323 iwl3945_clear_stations_table(priv);
b481de9c
ZY
8324
8325 priv->data_retry_limit = -1;
8326 priv->ieee_channels = NULL;
8327 priv->ieee_rates = NULL;
8318d78a 8328 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY
8329
8330 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8331 if (!err)
8332 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8333 if (err) {
8334 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8335 goto out_pci_disable_device;
8336 }
8337
8338 pci_set_drvdata(pdev, priv);
8339 err = pci_request_regions(pdev, DRV_NAME);
8340 if (err)
8341 goto out_pci_disable_device;
6440adb5 8342
b481de9c
ZY
8343 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8344 * PCI Tx retries from interfering with C3 CPU state */
8345 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8346
b481de9c
ZY
8347 priv->hw_base = pci_iomap(pdev, 0, 0);
8348 if (!priv->hw_base) {
8349 err = -ENODEV;
8350 goto out_pci_release_regions;
8351 }
8352
8353 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8354 (unsigned long long) pci_resource_len(pdev, 0));
8355 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8356
8357 /* Initialize module parameter values here */
8358
6440adb5 8359 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8360 if (iwl3945_param_disable) {
b481de9c
ZY
8361 set_bit(STATUS_RF_KILL_SW, &priv->status);
8362 IWL_DEBUG_INFO("Radio disabled.\n");
8363 }
8364
8365 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8366
8367 pci_id =
8368 (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
8369
8370 switch (pci_id) {
8371 case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
8372 case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
8373 case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
8374 case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
8375 priv->is_abg = 0;
8376 break;
8377
8378 /*
8379 * Rest are assumed ABG SKU -- if this is not the
8380 * case then the card will get the wrong 'Detected'
8381 * line in the kernel log however the code that
8382 * initializes the GEO table will detect no A-band
8383 * channels and remove the is_abg mask.
8384 */
8385 default:
8386 priv->is_abg = 1;
8387 break;
8388 }
8389
8390 printk(KERN_INFO DRV_NAME
8391 ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
8392 priv->is_abg ? "A" : "");
8393
8394 /* Device-specific setup */
bb8c093b 8395 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8396 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY
8397 goto out_iounmap;
8398 }
8399
bb8c093b 8400 if (iwl3945_param_qos_enable)
b481de9c
ZY
8401 priv->qos_data.qos_enable = 1;
8402
bb8c093b 8403 iwl3945_reset_qos(priv);
b481de9c
ZY
8404
8405 priv->qos_data.qos_active = 0;
8406 priv->qos_data.qos_cap.val = 0;
b481de9c 8407
8318d78a 8408 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH
8409 iwl3945_setup_deferred_work(priv);
8410 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY
8411
8412 priv->rates_mask = IWL_RATES_MASK;
8413 /* If power management is turned on, default to AC mode */
8414 priv->power_mode = IWL_POWER_AC;
8415 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8416
bb8c093b 8417 iwl3945_disable_interrupts(priv);
49df2b33 8418
bb8c093b 8419 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY
8420 if (err) {
8421 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY
8422 goto out_release_irq;
8423 }
8424
5a66926a
ZY
8425 /* nic init */
8426 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8427 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8428
8429 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8430 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8431 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8432 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8433 if (err < 0) {
8434 IWL_DEBUG_INFO("Failed to init the card\n");
8435 goto out_remove_sysfs;
8436 }
8437 /* Read the EEPROM */
8438 err = iwl3945_eeprom_init(priv);
b481de9c 8439 if (err) {
5a66926a
ZY
8440 IWL_ERROR("Unable to init EEPROM\n");
8441 goto out_remove_sysfs;
b481de9c 8442 }
5a66926a
ZY
8443 /* MAC Address location in EEPROM same for 3945/4965 */
8444 get_eeprom_mac(priv, priv->mac_addr);
8445 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8446 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8447
849e0dce
RC
8448 err = iwl3945_init_channel_map(priv);
8449 if (err) {
8450 IWL_ERROR("initializing regulatory failed: %d\n", err);
8451 goto out_remove_sysfs;
8452 }
8453
8454 err = iwl3945_init_geos(priv);
8455 if (err) {
8456 IWL_ERROR("initializing geos failed: %d\n", err);
8457 goto out_free_channel_map;
8458 }
849e0dce 8459
5a66926a
ZY
8460 iwl3945_rate_control_register(priv->hw);
8461 err = ieee80211_register_hw(priv->hw);
8462 if (err) {
8463 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8464 goto out_free_geos;
5a66926a 8465 }
b481de9c 8466
5a66926a
ZY
8467 priv->hw->conf.beacon_int = 100;
8468 priv->mac80211_registered = 1;
8469 pci_save_state(pdev);
8470 pci_disable_device(pdev);
b481de9c
ZY
8471
8472 return 0;
8473
849e0dce
RC
8474 out_free_geos:
8475 iwl3945_free_geos(priv);
8476 out_free_channel_map:
8477 iwl3945_free_channel_map(priv);
5a66926a 8478 out_remove_sysfs:
bb8c093b 8479 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY
8480
8481 out_release_irq:
b481de9c
ZY
8482 destroy_workqueue(priv->workqueue);
8483 priv->workqueue = NULL;
bb8c093b 8484 iwl3945_unset_hw_setting(priv);
b481de9c
ZY
8485
8486 out_iounmap:
8487 pci_iounmap(pdev, priv->hw_base);
8488 out_pci_release_regions:
8489 pci_release_regions(pdev);
8490 out_pci_disable_device:
8491 pci_disable_device(pdev);
8492 pci_set_drvdata(pdev, NULL);
8493 out_ieee80211_free_hw:
8494 ieee80211_free_hw(priv->hw);
8495 out:
8496 return err;
8497}
8498
bb8c093b 8499static void iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8500{
bb8c093b 8501 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY
8502 struct list_head *p, *q;
8503 int i;
8504
8505 if (!priv)
8506 return;
8507
8508 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8509
b481de9c 8510 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8511
bb8c093b 8512 iwl3945_down(priv);
b481de9c
ZY
8513
8514 /* Free MAC hash list for ADHOC */
8515 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8516 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8517 list_del(p);
bb8c093b 8518 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY
8519 }
8520 }
8521
bb8c093b 8522 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8523
bb8c093b 8524 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
8525
8526 if (priv->rxq.bd)
bb8c093b
CH
8527 iwl3945_rx_queue_free(priv, &priv->rxq);
8528 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8529
bb8c093b
CH
8530 iwl3945_unset_hw_setting(priv);
8531 iwl3945_clear_stations_table(priv);
b481de9c
ZY
8532
8533 if (priv->mac80211_registered) {
8534 ieee80211_unregister_hw(priv->hw);
bb8c093b 8535 iwl3945_rate_control_unregister(priv->hw);
b481de9c
ZY
8536 }
8537
6ef89d0a
MA
8538 /*netif_stop_queue(dev); */
8539 flush_workqueue(priv->workqueue);
8540
bb8c093b 8541 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
8542 * priv->workqueue... so we can't take down the workqueue
8543 * until now... */
8544 destroy_workqueue(priv->workqueue);
8545 priv->workqueue = NULL;
8546
b481de9c
ZY
8547 pci_iounmap(pdev, priv->hw_base);
8548 pci_release_regions(pdev);
8549 pci_disable_device(pdev);
8550 pci_set_drvdata(pdev, NULL);
8551
849e0dce
RC
8552 iwl3945_free_channel_map(priv);
8553 iwl3945_free_geos(priv);
b481de9c
ZY
8554
8555 if (priv->ibss_beacon)
8556 dev_kfree_skb(priv->ibss_beacon);
8557
8558 ieee80211_free_hw(priv->hw);
8559}
8560
8561#ifdef CONFIG_PM
8562
bb8c093b 8563static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8564{
bb8c093b 8565 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8566
e655b9f0
ZY
8567 if (priv->is_open) {
8568 set_bit(STATUS_IN_SUSPEND, &priv->status);
8569 iwl3945_mac_stop(priv->hw);
8570 priv->is_open = 1;
8571 }
b481de9c 8572
b481de9c
ZY
8573 pci_set_power_state(pdev, PCI_D3hot);
8574
b481de9c
ZY
8575 return 0;
8576}
8577
bb8c093b 8578static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8579{
bb8c093b 8580 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8581
b481de9c 8582 pci_set_power_state(pdev, PCI_D0);
b481de9c 8583
e655b9f0
ZY
8584 if (priv->is_open)
8585 iwl3945_mac_start(priv->hw);
b481de9c 8586
e655b9f0 8587 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY
8588 return 0;
8589}
8590
8591#endif /* CONFIG_PM */
8592
8593/*****************************************************************************
8594 *
8595 * driver and module entry point
8596 *
8597 *****************************************************************************/
8598
bb8c093b 8599static struct pci_driver iwl3945_driver = {
b481de9c 8600 .name = DRV_NAME,
bb8c093b
CH
8601 .id_table = iwl3945_hw_card_ids,
8602 .probe = iwl3945_pci_probe,
8603 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8604#ifdef CONFIG_PM
bb8c093b
CH
8605 .suspend = iwl3945_pci_suspend,
8606 .resume = iwl3945_pci_resume,
b481de9c
ZY
8607#endif
8608};
8609
bb8c093b 8610static int __init iwl3945_init(void)
b481de9c
ZY
8611{
8612
8613 int ret;
8614 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8615 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
bb8c093b 8616 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY
8617 if (ret) {
8618 IWL_ERROR("Unable to initialize PCI module\n");
8619 return ret;
8620 }
c8b0e6e1 8621#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8622 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY
8623 if (ret) {
8624 IWL_ERROR("Unable to create driver sysfs file\n");
bb8c093b 8625 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY
8626 return ret;
8627 }
8628#endif
8629
8630 return ret;
8631}
8632
bb8c093b 8633static void __exit iwl3945_exit(void)
b481de9c 8634{
c8b0e6e1 8635#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8636 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8637#endif
bb8c093b 8638 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY
8639}
8640
bb8c093b 8641module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8642MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8643module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8644MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8645module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY
8646MODULE_PARM_DESC(hwcrypto,
8647 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8648module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8649MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8650module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY
8651MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8652
bb8c093b 8653module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY
8654MODULE_PARM_DESC(queues_num, "number of hw queues.");
8655
8656/* QoS */
bb8c093b 8657module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY
8658MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8659
bb8c093b
CH
8660module_exit(iwl3945_exit);
8661module_init(iwl3945_init);