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iwlwifi: 3945 remove iwl-3945-commands.h
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CommitLineData
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1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
600c0e11 50#include "iwl-commands.h"
b481de9c 51#include "iwl-3945.h"
bddadf86 52#include "iwl-3945-fh.h"
b481de9c
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53#include "iwl-helpers.h"
54
c8b0e6e1 55#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 56u32 iwl3945_debug_level;
b481de9c
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57#endif
58
bb8c093b
CH
59static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
60 struct iwl3945_tx_queue *txq);
416e1438 61
b481de9c
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62/******************************************************************************
63 *
64 * module boiler plate
65 *
66 ******************************************************************************/
67
68/* module parameters */
6440adb5 69static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
95aa194a 70static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
6440adb5 71static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 72static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5 73int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
dfe7d458 74int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
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75
76/*
77 * module name, copyright, version, etc.
78 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
79 */
80
81#define DRV_DESCRIPTION \
82"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
83
c8b0e6e1 84#ifdef CONFIG_IWL3945_DEBUG
b481de9c
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85#define VD "d"
86#else
87#define VD
88#endif
89
c8b0e6e1 90#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
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91#define VS "s"
92#else
93#define VS
94#endif
95
b9e0b449 96#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 97#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
a7b75207 98#define DRV_AUTHOR "<ilw@linux.intel.com>"
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99#define DRV_VERSION IWLWIFI_VERSION
100
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101
102MODULE_DESCRIPTION(DRV_DESCRIPTION);
103MODULE_VERSION(DRV_VERSION);
a7b75207 104MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
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105MODULE_LICENSE("GPL");
106
8318d78a
JB
107static const struct ieee80211_supported_band *iwl3945_get_band(
108 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 109{
8318d78a 110 return priv->hw->wiphy->bands[band];
b481de9c
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111}
112
b481de9c
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113/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
114 * DMA services
115 *
116 * Theory of operation
117 *
6440adb5
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118 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
119 * of buffer descriptors, each of which points to one or more data buffers for
120 * the device to read from or fill. Driver and device exchange status of each
121 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
122 * entries in each circular buffer, to protect against confusing empty and full
123 * queue states.
124 *
125 * The device reads or writes the data in the queues via the device's several
126 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
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127 *
128 * For Tx queue, there are low mark and high mark limits. If, after queuing
129 * the packet for Tx, free space become < low mark, Tx queue stopped. When
130 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
131 * Tx queue resumed.
132 *
6440adb5
BC
133 * The 3945 operates with six queues: One receive queue, one transmit queue
134 * (#4) for sending commands to the device firmware, and four transmit queues
135 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
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136 ***************************************************/
137
c54b679d 138int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 139{
fc4b6853 140 int s = q->read_ptr - q->write_ptr;
b481de9c 141
fc4b6853 142 if (q->read_ptr > q->write_ptr)
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143 s -= q->n_bd;
144
145 if (s <= 0)
146 s += q->n_window;
147 /* keep some reserve to not confuse empty and full situations */
148 s -= 2;
149 if (s < 0)
150 s = 0;
151 return s;
152}
153
c54b679d 154int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 155{
fc4b6853
TW
156 return q->write_ptr > q->read_ptr ?
157 (i >= q->read_ptr && i < q->write_ptr) :
158 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
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159}
160
c54b679d 161
bb8c093b 162static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 163{
6440adb5 164 /* This is for scan command, the big buffer at end of command array */
b481de9c 165 if (is_huge)
6440adb5 166 return q->n_window; /* must be power of 2 */
b481de9c 167
6440adb5 168 /* Otherwise, use normal size buffers */
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169 return index & (q->n_window - 1);
170}
171
6440adb5
BC
172/**
173 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
174 */
bb8c093b 175static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
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176 int count, int slots_num, u32 id)
177{
178 q->n_bd = count;
179 q->n_window = slots_num;
180 q->id = id;
181
c54b679d
TW
182 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
183 * and iwl_queue_dec_wrap are broken. */
b481de9c
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184 BUG_ON(!is_power_of_2(count));
185
186 /* slots_num must be power-of-two size, otherwise
187 * get_cmd_index is broken. */
188 BUG_ON(!is_power_of_2(slots_num));
189
190 q->low_mark = q->n_window / 4;
191 if (q->low_mark < 4)
192 q->low_mark = 4;
193
194 q->high_mark = q->n_window / 8;
195 if (q->high_mark < 2)
196 q->high_mark = 2;
197
fc4b6853 198 q->write_ptr = q->read_ptr = 0;
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199
200 return 0;
201}
202
6440adb5
BC
203/**
204 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
205 */
bb8c093b
CH
206static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
207 struct iwl3945_tx_queue *txq, u32 id)
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208{
209 struct pci_dev *dev = priv->pci_dev;
210
6440adb5
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211 /* Driver private data, only for Tx (not command) queues,
212 * not shared with device. */
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213 if (id != IWL_CMD_QUEUE_NUM) {
214 txq->txb = kmalloc(sizeof(txq->txb[0]) *
215 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
216 if (!txq->txb) {
01ebd063 217 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
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218 "structures failed\n");
219 goto error;
220 }
221 } else
222 txq->txb = NULL;
223
6440adb5
BC
224 /* Circular buffer of transmit frame descriptors (TFDs),
225 * shared with device */
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226 txq->bd = pci_alloc_consistent(dev,
227 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
228 &txq->q.dma_addr);
229
230 if (!txq->bd) {
231 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
232 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
233 goto error;
234 }
235 txq->q.id = id;
236
237 return 0;
238
239 error:
3ac7f146
TW
240 kfree(txq->txb);
241 txq->txb = NULL;
b481de9c
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242
243 return -ENOMEM;
244}
245
6440adb5
BC
246/**
247 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
248 */
bb8c093b
CH
249int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
250 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
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251{
252 struct pci_dev *dev = priv->pci_dev;
253 int len;
254 int rc = 0;
255
6440adb5
BC
256 /*
257 * Alloc buffer array for commands (Tx or other types of commands).
258 * For the command queue (#4), allocate command space + one big
259 * command for scan, since scan command is very huge; the system will
260 * not have two scans at the same time, so only one is needed.
261 * For data Tx queues (all other queues), no super-size command
262 * space is needed.
263 */
bb8c093b 264 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
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265 if (txq_id == IWL_CMD_QUEUE_NUM)
266 len += IWL_MAX_SCAN_SIZE;
267 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
268 if (!txq->cmd)
269 return -ENOMEM;
270
6440adb5 271 /* Alloc driver data array and TFD circular buffer */
bb8c093b 272 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
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273 if (rc) {
274 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
275
276 return -ENOMEM;
277 }
278 txq->need_update = 0;
279
280 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 281 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 282 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
BC
283
284 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 285 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 286
6440adb5 287 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 288 iwl3945_hw_tx_queue_init(priv, txq);
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289
290 return 0;
291}
292
293/**
bb8c093b 294 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
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295 * @txq: Transmit queue to deallocate.
296 *
297 * Empty queue by removing and destroying all BD's.
6440adb5
BC
298 * Free all buffers.
299 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 300 */
bb8c093b 301void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 302{
bb8c093b 303 struct iwl3945_queue *q = &txq->q;
b481de9c
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304 struct pci_dev *dev = priv->pci_dev;
305 int len;
306
307 if (q->n_bd == 0)
308 return;
309
310 /* first, empty all BD's */
fc4b6853 311 for (; q->write_ptr != q->read_ptr;
c54b679d 312 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 313 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 314
bb8c093b 315 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
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316 if (q->id == IWL_CMD_QUEUE_NUM)
317 len += IWL_MAX_SCAN_SIZE;
318
6440adb5 319 /* De-alloc array of command/tx buffers */
b481de9c
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320 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
321
6440adb5 322 /* De-alloc circular buffer of TFDs */
b481de9c 323 if (txq->q.n_bd)
bb8c093b 324 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
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325 txq->q.n_bd, txq->bd, txq->q.dma_addr);
326
6440adb5 327 /* De-alloc array of per-TFD driver data */
3ac7f146
TW
328 kfree(txq->txb);
329 txq->txb = NULL;
b481de9c 330
6440adb5 331 /* 0-fill queue descriptor structure */
b481de9c
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332 memset(txq, 0, sizeof(*txq));
333}
334
bb8c093b 335const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
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336
337/*************** STATION TABLE MANAGEMENT ****
9fbab516 338 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
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339 * the functionality provided here
340 */
341
342/**************************************************************/
01ebd063 343#if 0 /* temporary disable till we add real remove station */
6440adb5
BC
344/**
345 * iwl3945_remove_station - Remove driver's knowledge of station.
346 *
347 * NOTE: This does not remove station from device's station table.
348 */
bb8c093b 349static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY
350{
351 int index = IWL_INVALID_STATION;
352 int i;
353 unsigned long flags;
354
355 spin_lock_irqsave(&priv->sta_lock, flags);
356
357 if (is_ap)
358 index = IWL_AP_ID;
359 else if (is_broadcast_ether_addr(addr))
360 index = priv->hw_setting.bcast_sta_id;
361 else
362 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
363 if (priv->stations[i].used &&
364 !compare_ether_addr(priv->stations[i].sta.sta.addr,
365 addr)) {
366 index = i;
367 break;
368 }
369
370 if (unlikely(index == IWL_INVALID_STATION))
371 goto out;
372
373 if (priv->stations[index].used) {
374 priv->stations[index].used = 0;
375 priv->num_stations--;
376 }
377
378 BUG_ON(priv->num_stations < 0);
379
380out:
381 spin_unlock_irqrestore(&priv->sta_lock, flags);
382 return 0;
383}
556f8db7 384#endif
6440adb5
BC
385
386/**
387 * iwl3945_clear_stations_table - Clear the driver's station table
388 *
389 * NOTE: This does not clear or otherwise alter the device's station table.
390 */
bb8c093b 391static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY
392{
393 unsigned long flags;
394
395 spin_lock_irqsave(&priv->sta_lock, flags);
396
397 priv->num_stations = 0;
398 memset(priv->stations, 0, sizeof(priv->stations));
399
400 spin_unlock_irqrestore(&priv->sta_lock, flags);
401}
402
6440adb5
BC
403/**
404 * iwl3945_add_station - Add station to station tables in driver and device
405 */
bb8c093b 406u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
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407{
408 int i;
409 int index = IWL_INVALID_STATION;
bb8c093b 410 struct iwl3945_station_entry *station;
b481de9c 411 unsigned long flags_spin;
c14c521e 412 u8 rate;
b481de9c
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413
414 spin_lock_irqsave(&priv->sta_lock, flags_spin);
415 if (is_ap)
416 index = IWL_AP_ID;
417 else if (is_broadcast_ether_addr(addr))
418 index = priv->hw_setting.bcast_sta_id;
419 else
420 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
421 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
422 addr)) {
423 index = i;
424 break;
425 }
426
427 if (!priv->stations[i].used &&
428 index == IWL_INVALID_STATION)
429 index = i;
430 }
431
01ebd063 432 /* These two conditions has the same outcome but keep them separate
b481de9c
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433 since they have different meaning */
434 if (unlikely(index == IWL_INVALID_STATION)) {
435 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
436 return index;
437 }
438
439 if (priv->stations[index].used &&
440 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
441 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
442 return index;
443 }
444
e174961c 445 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
b481de9c
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446 station = &priv->stations[index];
447 station->used = 1;
448 priv->num_stations++;
449
6440adb5 450 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 451 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
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452 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
453 station->sta.mode = 0;
454 station->sta.sta.sta_id = index;
455 station->sta.station_flags = 0;
456
8318d78a 457 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW
458 rate = IWL_RATE_6M_PLCP;
459 else
460 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY
461
462 /* Turn on both antennas for the station... */
463 station->sta.rate_n_flags =
bb8c093b 464 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e 465
b481de9c 466 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
BC
467
468 /* Add station to device's station table */
bb8c093b 469 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY
470 return index;
471
472}
473
474/*************** DRIVER STATUS FUNCTIONS *****/
475
bb8c093b 476static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY
477{
478 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
479 * set but EXIT_PENDING is not */
480 return test_bit(STATUS_READY, &priv->status) &&
481 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
482 !test_bit(STATUS_EXIT_PENDING, &priv->status);
483}
484
bb8c093b 485static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
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486{
487 return test_bit(STATUS_ALIVE, &priv->status);
488}
489
bb8c093b 490static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY
491{
492 return test_bit(STATUS_INIT, &priv->status);
493}
494
80fcc9e2
AG
495static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
496{
497 return test_bit(STATUS_RF_KILL_SW, &priv->status);
498}
499
500static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
501{
502 return test_bit(STATUS_RF_KILL_HW, &priv->status);
503}
504
bb8c093b 505static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 506{
80fcc9e2
AG
507 return iwl3945_is_rfkill_hw(priv) ||
508 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY
509}
510
bb8c093b 511static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY
512{
513
bb8c093b 514 if (iwl3945_is_rfkill(priv))
b481de9c
ZY
515 return 0;
516
bb8c093b 517 return iwl3945_is_ready(priv);
b481de9c
ZY
518}
519
520/*************** HOST COMMAND QUEUE FUNCTIONS *****/
521
c3056065 522#define IWL_CMD(x) case x: return #x
b481de9c
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523
524static const char *get_cmd_string(u8 cmd)
525{
526 switch (cmd) {
527 IWL_CMD(REPLY_ALIVE);
528 IWL_CMD(REPLY_ERROR);
529 IWL_CMD(REPLY_RXON);
530 IWL_CMD(REPLY_RXON_ASSOC);
531 IWL_CMD(REPLY_QOS_PARAM);
532 IWL_CMD(REPLY_RXON_TIMING);
533 IWL_CMD(REPLY_ADD_STA);
534 IWL_CMD(REPLY_REMOVE_STA);
535 IWL_CMD(REPLY_REMOVE_ALL_STA);
536 IWL_CMD(REPLY_3945_RX);
537 IWL_CMD(REPLY_TX);
538 IWL_CMD(REPLY_RATE_SCALE);
539 IWL_CMD(REPLY_LEDS_CMD);
540 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
541 IWL_CMD(RADAR_NOTIFICATION);
542 IWL_CMD(REPLY_QUIET_CMD);
543 IWL_CMD(REPLY_CHANNEL_SWITCH);
544 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
545 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
546 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
547 IWL_CMD(POWER_TABLE_CMD);
548 IWL_CMD(PM_SLEEP_NOTIFICATION);
549 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
550 IWL_CMD(REPLY_SCAN_CMD);
551 IWL_CMD(REPLY_SCAN_ABORT_CMD);
552 IWL_CMD(SCAN_START_NOTIFICATION);
553 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
554 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
555 IWL_CMD(BEACON_NOTIFICATION);
556 IWL_CMD(REPLY_TX_BEACON);
557 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
558 IWL_CMD(QUIET_NOTIFICATION);
559 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
560 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
561 IWL_CMD(REPLY_BT_CONFIG);
562 IWL_CMD(REPLY_STATISTICS_CMD);
563 IWL_CMD(STATISTICS_NOTIFICATION);
564 IWL_CMD(REPLY_CARD_STATE_CMD);
565 IWL_CMD(CARD_STATE_NOTIFICATION);
566 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
567 default:
568 return "UNKNOWN";
569
570 }
571}
572
573#define HOST_COMPLETE_TIMEOUT (HZ / 2)
574
575/**
bb8c093b 576 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY
577 * @priv: device private data point
578 * @cmd: a point to the ucode command structure
579 *
580 * The function returns < 0 values to indicate the operation is
581 * failed. On success, it turns the index (> 0) of command in the
582 * command queue.
583 */
bb8c093b 584static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 585{
bb8c093b
CH
586 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
587 struct iwl3945_queue *q = &txq->q;
588 struct iwl3945_tfd_frame *tfd;
b481de9c 589 u32 *control_flags;
bb8c093b 590 struct iwl3945_cmd *out_cmd;
b481de9c
ZY
591 u32 idx;
592 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
593 dma_addr_t phys_addr;
594 int pad;
595 u16 count;
596 int ret;
597 unsigned long flags;
598
599 /* If any of the command structures end up being larger than
600 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
601 * we will need to increase the size of the TFD entries */
602 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
603 !(cmd->meta.flags & CMD_SIZE_HUGE));
604
c342a1b9
GG
605
606 if (iwl3945_is_rfkill(priv)) {
607 IWL_DEBUG_INFO("Not sending command - RF KILL");
608 return -EIO;
609 }
610
bb8c093b 611 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY
612 IWL_ERROR("No space for Tx\n");
613 return -ENOSPC;
614 }
615
616 spin_lock_irqsave(&priv->hcmd_lock, flags);
617
fc4b6853 618 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
619 memset(tfd, 0, sizeof(*tfd));
620
621 control_flags = (u32 *) tfd;
622
fc4b6853 623 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY
624 out_cmd = &txq->cmd[idx];
625
626 out_cmd->hdr.cmd = cmd->id;
627 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
628 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
629
630 /* At this point, the out_cmd now has all of the incoming cmd
631 * information */
632
633 out_cmd->hdr.flags = 0;
634 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 635 INDEX_TO_SEQ(q->write_ptr));
b481de9c 636 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
600c0e11 637 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
b481de9c
ZY
638
639 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH
640 offsetof(struct iwl3945_cmd, hdr);
641 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY
642
643 pad = U32_PAD(cmd->len);
644 count = TFD_CTL_COUNT_GET(*control_flags);
645 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
646
647 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
648 "%d bytes at %d[%d]:%d\n",
649 get_cmd_string(out_cmd->hdr.cmd),
650 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 651 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY
652
653 txq->need_update = 1;
6440adb5
BC
654
655 /* Increment and update queue's write index */
c54b679d 656 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 657 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
658
659 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
660 return ret ? ret : idx;
661}
662
bb8c093b 663static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY
664{
665 int ret;
666
667 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
668
669 /* An asynchronous command can not expect an SKB to be set. */
670 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
671
672 /* An asynchronous command MUST have a callback. */
673 BUG_ON(!cmd->meta.u.callback);
674
675 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
676 return -EBUSY;
677
bb8c093b 678 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 679 if (ret < 0) {
bb8c093b 680 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY
681 get_cmd_string(cmd->id), ret);
682 return ret;
683 }
684 return 0;
685}
686
bb8c093b 687static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY
688{
689 int cmd_idx;
690 int ret;
b481de9c
ZY
691
692 BUG_ON(cmd->meta.flags & CMD_ASYNC);
693
694 /* A synchronous command can not have a callback set. */
695 BUG_ON(cmd->meta.u.callback != NULL);
696
e5472978 697 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY
698 IWL_ERROR("Error sending %s: Already sending a host command\n",
699 get_cmd_string(cmd->id));
e5472978
TW
700 ret = -EBUSY;
701 goto out;
b481de9c
ZY
702 }
703
704 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
705
706 if (cmd->meta.flags & CMD_WANT_SKB)
707 cmd->meta.source = &cmd->meta;
708
bb8c093b 709 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY
710 if (cmd_idx < 0) {
711 ret = cmd_idx;
bb8c093b 712 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY
713 get_cmd_string(cmd->id), ret);
714 goto out;
715 }
716
717 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
718 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
719 HOST_COMPLETE_TIMEOUT);
720 if (!ret) {
721 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
722 IWL_ERROR("Error sending %s: time out after %dms.\n",
723 get_cmd_string(cmd->id),
724 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
725
726 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
727 ret = -ETIMEDOUT;
728 goto cancel;
729 }
730 }
731
732 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
733 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
734 get_cmd_string(cmd->id));
735 ret = -ECANCELED;
736 goto fail;
737 }
738 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
739 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
740 get_cmd_string(cmd->id));
741 ret = -EIO;
742 goto fail;
743 }
744 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
745 IWL_ERROR("Error: Response NULL in '%s'\n",
746 get_cmd_string(cmd->id));
747 ret = -EIO;
73e1a65d 748 goto cancel;
b481de9c
ZY
749 }
750
751 ret = 0;
752 goto out;
753
754cancel:
755 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 756 struct iwl3945_cmd *qcmd;
b481de9c
ZY
757
758 /* Cancel the CMD_WANT_SKB flag for the cmd in the
759 * TX cmd queue. Otherwise in case the cmd comes
760 * in later, it will possibly set an invalid
761 * address (cmd->meta.source). */
762 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
763 qcmd->meta.flags &= ~CMD_WANT_SKB;
764 }
765fail:
766 if (cmd->meta.u.skb) {
767 dev_kfree_skb_any(cmd->meta.u.skb);
768 cmd->meta.u.skb = NULL;
769 }
770out:
e5472978 771 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY
772 return ret;
773}
774
bb8c093b 775int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 776{
b481de9c 777 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 778 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 779
bb8c093b 780 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY
781}
782
bb8c093b 783int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 784{
bb8c093b 785 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
786 .id = id,
787 .len = len,
788 .data = data,
789 };
790
bb8c093b 791 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
792}
793
bb8c093b 794static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 795{
bb8c093b 796 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
797 .id = id,
798 .len = sizeof(val),
799 .data = &val,
800 };
801
bb8c093b 802 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
803}
804
bb8c093b 805int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 806{
bb8c093b 807 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY
808}
809
b481de9c 810/**
bb8c093b 811 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB
812 * @band: 2.4 or 5 GHz band
813 * @channel: Any channel valid for the requested band
b481de9c 814
8318d78a 815 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY
816 *
817 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 818 * in the staging RXON flag structure based on the band
b481de9c 819 */
8318d78a
JB
820static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
821 enum ieee80211_band band,
822 u16 channel)
b481de9c 823{
8318d78a 824 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 825 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 826 channel, band);
b481de9c
ZY
827 return -EINVAL;
828 }
829
830 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 831 (priv->band == band))
b481de9c
ZY
832 return 0;
833
834 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 835 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
836 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
837 else
838 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
839
8318d78a 840 priv->band = band;
b481de9c 841
8318d78a 842 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY
843
844 return 0;
845}
846
847/**
bb8c093b 848 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY
849 *
850 * NOTE: This is really only useful during development and can eventually
851 * be #ifdef'd out once the driver is stable and folks aren't actively
852 * making changes
853 */
bb8c093b 854static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY
855{
856 int error = 0;
857 int counter = 1;
858
859 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
860 error |= le32_to_cpu(rxon->flags &
861 (RXON_FLG_TGJ_NARROW_BAND_MSK |
862 RXON_FLG_RADAR_DETECT_MSK));
863 if (error)
864 IWL_WARNING("check 24G fields %d | %d\n",
865 counter++, error);
866 } else {
867 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
868 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
869 if (error)
870 IWL_WARNING("check 52 fields %d | %d\n",
871 counter++, error);
872 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
873 if (error)
874 IWL_WARNING("check 52 CCK %d | %d\n",
875 counter++, error);
876 }
877 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
878 if (error)
879 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
880
881 /* make sure basic rates 6Mbps and 1Mbps are supported */
882 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
883 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
884 if (error)
885 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
886
887 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
888 if (error)
889 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
890
891 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
892 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
893 if (error)
894 IWL_WARNING("check CCK and short slot %d | %d\n",
895 counter++, error);
896
897 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
898 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
899 if (error)
900 IWL_WARNING("check CCK & auto detect %d | %d\n",
901 counter++, error);
902
903 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
904 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
905 if (error)
906 IWL_WARNING("check TGG and auto detect %d | %d\n",
907 counter++, error);
908
909 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
910 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
911 RXON_FLG_ANT_A_MSK)) == 0);
912 if (error)
913 IWL_WARNING("check antenna %d %d\n", counter++, error);
914
915 if (error)
916 IWL_WARNING("Tuning to channel %d\n",
917 le16_to_cpu(rxon->channel));
918
919 if (error) {
bb8c093b 920 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY
921 return -1;
922 }
923 return 0;
924}
925
926/**
9fbab516 927 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 928 * @priv: staging_rxon is compared to active_rxon
b481de9c 929 *
9fbab516
BC
930 * If the RXON structure is changing enough to require a new tune,
931 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
932 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 933 */
bb8c093b 934static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY
935{
936
937 /* These items are only settable from the full RXON command */
5d1e2325 938 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY
939 compare_ether_addr(priv->staging_rxon.bssid_addr,
940 priv->active_rxon.bssid_addr) ||
941 compare_ether_addr(priv->staging_rxon.node_addr,
942 priv->active_rxon.node_addr) ||
943 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
944 priv->active_rxon.wlap_bssid_addr) ||
945 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
946 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
947 (priv->staging_rxon.air_propagation !=
948 priv->active_rxon.air_propagation) ||
949 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
950 return 1;
951
952 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
953 * be updated with the RXON_ASSOC command -- however only some
954 * flag transitions are allowed using RXON_ASSOC */
955
956 /* Check if we are not switching bands */
957 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
958 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
959 return 1;
960
961 /* Check if we are switching association toggle */
962 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
963 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
964 return 1;
965
966 return 0;
967}
968
bb8c093b 969static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY
970{
971 int rc = 0;
3d24a9f7 972 struct iwl_rx_packet *res = NULL;
bb8c093b
CH
973 struct iwl3945_rxon_assoc_cmd rxon_assoc;
974 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
975 .id = REPLY_RXON_ASSOC,
976 .len = sizeof(rxon_assoc),
977 .meta.flags = CMD_WANT_SKB,
978 .data = &rxon_assoc,
979 };
bb8c093b
CH
980 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
981 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY
982
983 if ((rxon1->flags == rxon2->flags) &&
984 (rxon1->filter_flags == rxon2->filter_flags) &&
985 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
986 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
987 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
988 return 0;
989 }
990
991 rxon_assoc.flags = priv->staging_rxon.flags;
992 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
993 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
994 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
995 rxon_assoc.reserved = 0;
996
bb8c093b 997 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
998 if (rc)
999 return rc;
1000
3d24a9f7 1001 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1002 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1003 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1004 rc = -EIO;
1005 }
1006
1007 priv->alloc_rxb_skb--;
1008 dev_kfree_skb_any(cmd.meta.u.skb);
1009
1010 return rc;
1011}
1012
1013/**
bb8c093b 1014 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1015 *
01ebd063 1016 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY
1017 * the active_rxon structure is updated with the new data. This
1018 * function correctly transitions out of the RXON_ASSOC_MSK state if
1019 * a HW tune is required based on the RXON structure changes.
1020 */
bb8c093b 1021static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY
1022{
1023 /* cast away the const for active_rxon in this function */
bb8c093b 1024 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c
ZY
1025 int rc = 0;
1026
bb8c093b 1027 if (!iwl3945_is_alive(priv))
b481de9c
ZY
1028 return -1;
1029
1030 /* always get timestamp with Rx frame */
1031 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1032
1033 /* select antenna */
1034 priv->staging_rxon.flags &=
1035 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1036 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1037
bb8c093b 1038 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY
1039 if (rc) {
1040 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1041 return -EINVAL;
1042 }
1043
1044 /* If we don't need to send a full RXON, we can use
bb8c093b 1045 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1046 * and other flags for the current radio configuration. */
bb8c093b
CH
1047 if (!iwl3945_full_rxon_required(priv)) {
1048 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY
1049 if (rc) {
1050 IWL_ERROR("Error setting RXON_ASSOC "
1051 "configuration (%d).\n", rc);
1052 return rc;
1053 }
1054
1055 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1056
1057 return 0;
1058 }
1059
1060 /* If we are currently associated and the new config requires
1061 * an RXON_ASSOC and the new config wants the associated mask enabled,
1062 * we must clear the associated from the active configuration
1063 * before we apply the new config */
bb8c093b 1064 if (iwl3945_is_associated(priv) &&
b481de9c
ZY
1065 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1066 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1067 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1068
bb8c093b
CH
1069 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1070 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY
1071 &priv->active_rxon);
1072
1073 /* If the mask clearing failed then we set
1074 * active_rxon back to what it was previously */
1075 if (rc) {
1076 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1077 IWL_ERROR("Error clearing ASSOC_MSK on current "
1078 "configuration (%d).\n", rc);
1079 return rc;
1080 }
b481de9c
ZY
1081 }
1082
1083 IWL_DEBUG_INFO("Sending RXON\n"
1084 "* with%s RXON_FILTER_ASSOC_MSK\n"
1085 "* channel = %d\n"
e174961c 1086 "* bssid = %pM\n",
b481de9c
ZY
1087 ((priv->staging_rxon.filter_flags &
1088 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1089 le16_to_cpu(priv->staging_rxon.channel),
e174961c 1090 priv->staging_rxon.bssid_addr);
b481de9c
ZY
1091
1092 /* Apply the new configuration */
bb8c093b
CH
1093 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1094 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY
1095 if (rc) {
1096 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1097 return rc;
1098 }
1099
1100 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1101
bb8c093b 1102 iwl3945_clear_stations_table(priv);
556f8db7 1103
b481de9c
ZY
1104 /* If we issue a new RXON command which required a tune then we must
1105 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1106 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
1107 if (rc) {
1108 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1109 return rc;
1110 }
1111
1112 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1113 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY
1114 IWL_INVALID_STATION) {
1115 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1116 return -EIO;
1117 }
1118
1119 /* If we have set the ASSOC_MSK and we are in BSS mode then
1120 * add the IWL_AP_ID to the station rate table */
bb8c093b 1121 if (iwl3945_is_associated(priv) &&
05c914fe 1122 (priv->iw_mode == NL80211_IFTYPE_STATION))
bb8c093b 1123 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY
1124 == IWL_INVALID_STATION) {
1125 IWL_ERROR("Error adding AP address for transmit.\n");
1126 return -EIO;
1127 }
1128
8318d78a 1129 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY
1130 rc = iwl3945_init_hw_rate_table(priv);
1131 if (rc) {
1132 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1133 return -EIO;
1134 }
1135
1136 return 0;
1137}
1138
bb8c093b 1139static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1140{
4c897253 1141 struct iwl_bt_cmd bt_cmd = {
b481de9c
ZY
1142 .flags = 3,
1143 .lead_time = 0xAA,
1144 .max_kill = 1,
1145 .kill_ack_mask = 0,
1146 .kill_cts_mask = 0,
1147 };
1148
bb8c093b 1149 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
4c897253 1150 sizeof(bt_cmd), &bt_cmd);
b481de9c
ZY
1151}
1152
bb8c093b 1153static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY
1154{
1155 int rc = 0;
3d24a9f7 1156 struct iwl_rx_packet *res;
bb8c093b 1157 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1158 .id = REPLY_SCAN_ABORT_CMD,
1159 .meta.flags = CMD_WANT_SKB,
1160 };
1161
1162 /* If there isn't a scan actively going on in the hardware
1163 * then we are in between scan bands and not actually
1164 * actively scanning, so don't send the abort command */
1165 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1166 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1167 return 0;
1168 }
1169
bb8c093b 1170 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1171 if (rc) {
1172 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1173 return rc;
1174 }
1175
3d24a9f7 1176 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1177 if (res->u.status != CAN_ABORT_STATUS) {
1178 /* The scan abort will return 1 for success or
1179 * 2 for "failure". A failure condition can be
1180 * due to simply not being in an active scan which
1181 * can occur if we send the scan abort before we
1182 * the microcode has notified us that a scan is
1183 * completed. */
1184 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1185 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1186 clear_bit(STATUS_SCAN_HW, &priv->status);
1187 }
1188
1189 dev_kfree_skb_any(cmd.meta.u.skb);
1190
1191 return rc;
1192}
1193
bb8c093b
CH
1194static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1195 struct iwl3945_cmd *cmd,
b481de9c
ZY
1196 struct sk_buff *skb)
1197{
1198 return 1;
1199}
1200
1201/*
1202 * CARD_STATE_CMD
1203 *
9fbab516 1204 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY
1205 *
1206 * When in the 'enable' state the card operates as normal.
1207 * When in the 'disable' state, the card enters into a low power mode.
1208 * When in the 'halt' state, the card is shut down and must be fully
1209 * restarted to come back on.
1210 */
bb8c093b 1211static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1212{
bb8c093b 1213 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
1214 .id = REPLY_CARD_STATE_CMD,
1215 .len = sizeof(u32),
1216 .data = &flags,
1217 .meta.flags = meta_flag,
1218 };
1219
1220 if (meta_flag & CMD_ASYNC)
bb8c093b 1221 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1222
bb8c093b 1223 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1224}
1225
bb8c093b
CH
1226static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1227 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1228{
3d24a9f7 1229 struct iwl_rx_packet *res = NULL;
b481de9c
ZY
1230
1231 if (!skb) {
1232 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1233 return 1;
1234 }
1235
3d24a9f7 1236 res = (struct iwl_rx_packet *)skb->data;
b481de9c
ZY
1237 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1238 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1239 res->hdr.flags);
1240 return 1;
1241 }
1242
1243 switch (res->u.add_sta.status) {
1244 case ADD_STA_SUCCESS_MSK:
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 /* We didn't cache the SKB; let the caller free it */
1251 return 1;
1252}
1253
bb8c093b
CH
1254int iwl3945_send_add_station(struct iwl3945_priv *priv,
1255 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1256{
3d24a9f7 1257 struct iwl_rx_packet *res = NULL;
b481de9c 1258 int rc = 0;
bb8c093b 1259 struct iwl3945_host_cmd cmd = {
b481de9c 1260 .id = REPLY_ADD_STA,
bb8c093b 1261 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY
1262 .meta.flags = flags,
1263 .data = sta,
1264 };
1265
1266 if (flags & CMD_ASYNC)
bb8c093b 1267 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY
1268 else
1269 cmd.meta.flags |= CMD_WANT_SKB;
1270
bb8c093b 1271 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1272
1273 if (rc || (flags & CMD_ASYNC))
1274 return rc;
1275
3d24a9f7 1276 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1277 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1278 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1279 res->hdr.flags);
1280 rc = -EIO;
1281 }
1282
1283 if (rc == 0) {
1284 switch (res->u.add_sta.status) {
1285 case ADD_STA_SUCCESS_MSK:
1286 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1287 break;
1288 default:
1289 rc = -EIO;
1290 IWL_WARNING("REPLY_ADD_STA failed\n");
1291 break;
1292 }
1293 }
1294
1295 priv->alloc_rxb_skb--;
1296 dev_kfree_skb_any(cmd.meta.u.skb);
1297
1298 return rc;
1299}
1300
bb8c093b 1301static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY
1302 struct ieee80211_key_conf *keyconf,
1303 u8 sta_id)
1304{
1305 unsigned long flags;
1306 __le16 key_flags = 0;
1307
1308 switch (keyconf->alg) {
1309 case ALG_CCMP:
1310 key_flags |= STA_KEY_FLG_CCMP;
1311 key_flags |= cpu_to_le16(
1312 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1313 key_flags &= ~STA_KEY_FLG_INVALID;
1314 break;
1315 case ALG_TKIP:
1316 case ALG_WEP:
b481de9c
ZY
1317 default:
1318 return -EINVAL;
1319 }
1320 spin_lock_irqsave(&priv->sta_lock, flags);
1321 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1322 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1323 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1324 keyconf->keylen);
1325
1326 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1327 keyconf->keylen);
1328 priv->stations[sta_id].sta.key.key_flags = key_flags;
1329 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1330 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1331
1332 spin_unlock_irqrestore(&priv->sta_lock, flags);
1333
1334 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1335 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1336 return 0;
1337}
1338
bb8c093b 1339static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY
1340{
1341 unsigned long flags;
1342
1343 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b 1344 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
4c897253
TW
1345 memset(&priv->stations[sta_id].sta.key, 0,
1346 sizeof(struct iwl4965_keyinfo));
b481de9c
ZY
1347 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1348 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1349 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1350 spin_unlock_irqrestore(&priv->sta_lock, flags);
1351
1352 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1353 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
1354 return 0;
1355}
1356
bb8c093b 1357static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY
1358{
1359 struct list_head *element;
1360
1361 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1362 priv->frames_count);
1363
1364 while (!list_empty(&priv->free_frames)) {
1365 element = priv->free_frames.next;
1366 list_del(element);
bb8c093b 1367 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY
1368 priv->frames_count--;
1369 }
1370
1371 if (priv->frames_count) {
1372 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1373 priv->frames_count);
1374 priv->frames_count = 0;
1375 }
1376}
1377
bb8c093b 1378static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1379{
bb8c093b 1380 struct iwl3945_frame *frame;
b481de9c
ZY
1381 struct list_head *element;
1382 if (list_empty(&priv->free_frames)) {
1383 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1384 if (!frame) {
1385 IWL_ERROR("Could not allocate frame!\n");
1386 return NULL;
1387 }
1388
1389 priv->frames_count++;
1390 return frame;
1391 }
1392
1393 element = priv->free_frames.next;
1394 list_del(element);
bb8c093b 1395 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
1396}
1397
bb8c093b 1398static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY
1399{
1400 memset(frame, 0, sizeof(*frame));
1401 list_add(&frame->list, &priv->free_frames);
1402}
1403
bb8c093b 1404unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c 1405 struct ieee80211_hdr *hdr,
73ec1cc2 1406 int left)
b481de9c
ZY
1407{
1408
bb8c093b 1409 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
1410 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1411 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
1412 return 0;
1413
1414 if (priv->ibss_beacon->len > left)
1415 return 0;
1416
1417 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1418
1419 return priv->ibss_beacon->len;
1420}
1421
c24f0817 1422static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
b481de9c
ZY
1423{
1424 u8 i;
c24f0817
KA
1425 int rate_mask;
1426
1427 /* Set rate mask*/
1428 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
dbce56a4 1429 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
c24f0817 1430 else
dbce56a4 1431 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
b481de9c
ZY
1432
1433 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1434 i = iwl3945_rates[i].next_ieee) {
b481de9c 1435 if (rate_mask & (1 << i))
bb8c093b 1436 return iwl3945_rates[i].plcp;
b481de9c
ZY
1437 }
1438
c24f0817
KA
1439 /* No valid rate was found. Assign the lowest one */
1440 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
1441 return IWL_RATE_1M_PLCP;
1442 else
1443 return IWL_RATE_6M_PLCP;
b481de9c
ZY
1444}
1445
bb8c093b 1446static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1447{
bb8c093b 1448 struct iwl3945_frame *frame;
b481de9c
ZY
1449 unsigned int frame_size;
1450 int rc;
1451 u8 rate;
1452
bb8c093b 1453 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
1454
1455 if (!frame) {
1456 IWL_ERROR("Could not obtain free frame buffer for beacon "
1457 "command.\n");
1458 return -ENOMEM;
1459 }
1460
c24f0817 1461 rate = iwl3945_rate_get_lowest_plcp(priv);
b481de9c 1462
bb8c093b 1463 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1464
bb8c093b 1465 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
1466 &frame->u.cmd[0]);
1467
bb8c093b 1468 iwl3945_free_frame(priv, frame);
b481de9c
ZY
1469
1470 return rc;
1471}
1472
1473/******************************************************************************
1474 *
1475 * EEPROM related functions
1476 *
1477 ******************************************************************************/
1478
bb8c093b 1479static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY
1480{
1481 memcpy(mac, priv->eeprom.mac_address, 6);
1482}
1483
74a3a250
RC
1484/*
1485 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1486 * embedded controller) as EEPROM reader; each read is a series of pulses
1487 * to/from the EEPROM chip, not a single event, so even reads could conflict
1488 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1489 * simply claims ownership, which should be safe when this function is called
1490 * (i.e. before loading uCode!).
1491 */
1492static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1493{
1494 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1495 return 0;
1496}
1497
b481de9c 1498/**
bb8c093b 1499 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1500 *
6440adb5 1501 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY
1502 *
1503 * NOTE: This routine uses the non-debug IO access functions.
1504 */
bb8c093b 1505int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1506{
58ff6d4d 1507 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1508 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c 1509 int sz = sizeof(priv->eeprom);
3d5717ad 1510 int ret;
b481de9c
ZY
1511 u16 addr;
1512
1513 /* The EEPROM structure has several padding buffers within it
1514 * and when adding new EEPROM maps is subject to programmer errors
1515 * which may be very difficult to identify without explicitly
1516 * checking the resulting size of the eeprom map. */
1517 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1518
1519 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
6f147926 1520 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY
1521 return -ENOENT;
1522 }
1523
6440adb5 1524 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
3d5717ad
ZY
1525 ret = iwl3945_eeprom_acquire_semaphore(priv);
1526 if (ret < 0) {
91e17473 1527 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY
1528 return -ENOENT;
1529 }
1530
1531 /* eeprom is an array of 16bit values */
1532 for (addr = 0; addr < sz; addr += sizeof(u16)) {
3d5717ad 1533 u32 r;
b481de9c 1534
3d5717ad
ZY
1535 _iwl3945_write32(priv, CSR_EEPROM_REG,
1536 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
1537 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1538 ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
1539 CSR_EEPROM_REG_READ_VALID_MSK,
1540 IWL_EEPROM_ACCESS_TIMEOUT);
1541 if (ret < 0) {
6f147926 1542 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
3d5717ad 1543 return ret;
b481de9c 1544 }
3d5717ad
ZY
1545
1546 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
58ff6d4d 1547 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY
1548 }
1549
1550 return 0;
1551}
1552
bb8c093b 1553static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY
1554{
1555 if (priv->hw_setting.shared_virt)
1556 pci_free_consistent(priv->pci_dev,
bb8c093b 1557 sizeof(struct iwl3945_shared),
b481de9c
ZY
1558 priv->hw_setting.shared_virt,
1559 priv->hw_setting.shared_phys);
1560}
1561
1562/**
bb8c093b 1563 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY
1564 *
1565 * return : set the bit for each supported rate insert in ie
1566 */
bb8c093b 1567static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1568 u16 basic_rate, int *left)
b481de9c
ZY
1569{
1570 u16 ret_rates = 0, bit;
1571 int i;
c7c46676
TW
1572 u8 *cnt = ie;
1573 u8 *rates = ie + 1;
b481de9c
ZY
1574
1575 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1576 if (bit & supported_rate) {
1577 ret_rates |= bit;
bb8c093b 1578 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW
1579 ((bit & basic_rate) ? 0x80 : 0x00);
1580 (*cnt)++;
1581 (*left)--;
1582 if ((*left <= 0) ||
1583 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY
1584 break;
1585 }
1586 }
1587
1588 return ret_rates;
1589}
1590
1591/**
bb8c093b 1592 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1593 */
bb8c093b 1594static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c 1595 struct ieee80211_mgmt *frame,
430cfe95 1596 int left)
b481de9c
ZY
1597{
1598 int len = 0;
1599 u8 *pos = NULL;
c7c46676 1600 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY
1601
1602 /* Make sure there is enough space for the probe request,
1603 * two mandatory IEs and the data */
1604 left -= 24;
1605 if (left < 0)
1606 return 0;
1607 len += 24;
1608
1609 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1610 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1611 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1612 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY
1613 frame->seq_ctrl = 0;
1614
1615 /* fill in our indirect SSID IE */
1616 /* ...next IE... */
1617
1618 left -= 2;
1619 if (left < 0)
1620 return 0;
1621 len += 2;
1622 pos = &(frame->u.probe_req.variable[0]);
1623 *pos++ = WLAN_EID_SSID;
1624 *pos++ = 0;
1625
b481de9c
ZY
1626 /* fill in supported rate */
1627 /* ...next IE... */
1628 left -= 2;
1629 if (left < 0)
1630 return 0;
c7c46676 1631
b481de9c
ZY
1632 /* ... fill it in... */
1633 *pos++ = WLAN_EID_SUPP_RATES;
1634 *pos = 0;
c7c46676
TW
1635
1636 priv->active_rate = priv->rates_mask;
1637 active_rates = priv->active_rate;
b481de9c
ZY
1638 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1639
c7c46676 1640 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1641 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW
1642 priv->active_rate_basic, &left);
1643 active_rates &= ~ret_rates;
1644
bb8c093b 1645 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW
1646 priv->active_rate_basic, &left);
1647 active_rates &= ~ret_rates;
1648
b481de9c
ZY
1649 len += 2 + *pos;
1650 pos += (*pos) + 1;
c7c46676 1651 if (active_rates == 0)
b481de9c
ZY
1652 goto fill_end;
1653
1654 /* fill in supported extended rate */
1655 /* ...next IE... */
1656 left -= 2;
1657 if (left < 0)
1658 return 0;
1659 /* ... fill it in... */
1660 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1661 *pos = 0;
bb8c093b 1662 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1663 priv->active_rate_basic, &left);
b481de9c
ZY
1664 if (*pos > 0)
1665 len += 2 + *pos;
1666
1667 fill_end:
1668 return (u16)len;
1669}
1670
1671/*
1672 * QoS support
1673*/
bb8c093b 1674static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
4c897253 1675 struct iwl_qosparam_cmd *qos)
b481de9c
ZY
1676{
1677
bb8c093b 1678 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
4c897253 1679 sizeof(struct iwl_qosparam_cmd), qos);
b481de9c
ZY
1680}
1681
bb8c093b 1682static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY
1683{
1684 u16 cw_min = 15;
1685 u16 cw_max = 1023;
1686 u8 aifs = 2;
1687 u8 is_legacy = 0;
1688 unsigned long flags;
1689 int i;
1690
1691 spin_lock_irqsave(&priv->lock, flags);
1692 priv->qos_data.qos_active = 0;
1693
6d1ef1a3
WT
1694 /* QoS always active in AP and ADHOC mode
1695 * In STA mode wait for association
1696 */
1697 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
1698 priv->iw_mode == NL80211_IFTYPE_AP)
1699 priv->qos_data.qos_active = 1;
1700 else
1701 priv->qos_data.qos_active = 0;
1702
1703
1704 /* check for legacy mode */
1705 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
1706 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
1707 (priv->iw_mode == NL80211_IFTYPE_STATION &&
1708 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
b481de9c
ZY
1709 cw_min = 31;
1710 is_legacy = 1;
1711 }
1712
1713 if (priv->qos_data.qos_active)
1714 aifs = 3;
1715
1716 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1717 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1718 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1719 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1720 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1721
1722 if (priv->qos_data.qos_active) {
1723 i = 1;
1724 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1725 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1726 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1727 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1728 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1729
1730 i = 2;
1731 priv->qos_data.def_qos_parm.ac[i].cw_min =
1732 cpu_to_le16((cw_min + 1) / 2 - 1);
1733 priv->qos_data.def_qos_parm.ac[i].cw_max =
1734 cpu_to_le16(cw_max);
1735 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1736 if (is_legacy)
1737 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1738 cpu_to_le16(6016);
1739 else
1740 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1741 cpu_to_le16(3008);
1742 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1743
1744 i = 3;
1745 priv->qos_data.def_qos_parm.ac[i].cw_min =
1746 cpu_to_le16((cw_min + 1) / 4 - 1);
1747 priv->qos_data.def_qos_parm.ac[i].cw_max =
1748 cpu_to_le16((cw_max + 1) / 2 - 1);
1749 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1750 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1751 if (is_legacy)
1752 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1753 cpu_to_le16(3264);
1754 else
1755 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1756 cpu_to_le16(1504);
1757 } else {
1758 for (i = 1; i < 4; i++) {
1759 priv->qos_data.def_qos_parm.ac[i].cw_min =
1760 cpu_to_le16(cw_min);
1761 priv->qos_data.def_qos_parm.ac[i].cw_max =
1762 cpu_to_le16(cw_max);
1763 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1764 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1765 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1766 }
1767 }
1768 IWL_DEBUG_QOS("set QoS to default \n");
1769
1770 spin_unlock_irqrestore(&priv->lock, flags);
1771}
1772
bb8c093b 1773static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY
1774{
1775 unsigned long flags;
1776
b481de9c
ZY
1777 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1778 return;
1779
b481de9c
ZY
1780 spin_lock_irqsave(&priv->lock, flags);
1781 priv->qos_data.def_qos_parm.qos_flags = 0;
1782
1783 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1784 !priv->qos_data.qos_cap.q_AP.txop_request)
1785 priv->qos_data.def_qos_parm.qos_flags |=
1786 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1787
1788 if (priv->qos_data.qos_active)
1789 priv->qos_data.def_qos_parm.qos_flags |=
1790 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1791
1792 spin_unlock_irqrestore(&priv->lock, flags);
1793
bb8c093b 1794 if (force || iwl3945_is_associated(priv)) {
a96a27f9 1795 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
b481de9c
ZY
1796 priv->qos_data.qos_active);
1797
bb8c093b 1798 iwl3945_send_qos_params_command(priv,
b481de9c
ZY
1799 &(priv->qos_data.def_qos_parm));
1800 }
1801}
1802
b481de9c
ZY
1803/*
1804 * Power management (not Tx power!) functions
1805 */
1806#define MSEC_TO_USEC 1024
1807
600c0e11
TW
1808
1809#define NOSLP __constant_cpu_to_le16(0), 0, 0
1810#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
b481de9c
ZY
1811#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1812#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1813 __constant_cpu_to_le32(X1), \
1814 __constant_cpu_to_le32(X2), \
1815 __constant_cpu_to_le32(X3), \
1816 __constant_cpu_to_le32(X4)}
1817
b481de9c 1818/* default power management (not Tx power) table values */
a96a27f9 1819/* for TIM 0-10 */
bb8c093b 1820static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY
1821 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1822 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1823 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1824 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1825 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1826 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1827};
1828
a96a27f9 1829/* for TIM > 10 */
bb8c093b 1830static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY
1831 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1832 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1833 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1834 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1835 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1836 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1837 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1838 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1839 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1840 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1841};
1842
bb8c093b 1843int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY
1844{
1845 int rc = 0, i;
bb8c093b
CH
1846 struct iwl3945_power_mgr *pow_data;
1847 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY
1848 u16 pci_pm;
1849
1850 IWL_DEBUG_POWER("Initialize power \n");
1851
1852 pow_data = &(priv->power_data);
1853
1854 memset(pow_data, 0, sizeof(*pow_data));
1855
1856 pow_data->active_index = IWL_POWER_RANGE_0;
1857 pow_data->dtim_val = 0xffff;
1858
1859 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1860 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1861
1862 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1863 if (rc != 0)
1864 return 0;
1865 else {
600c0e11 1866 struct iwl_powertable_cmd *cmd;
b481de9c
ZY
1867
1868 IWL_DEBUG_POWER("adjust power command flags\n");
1869
1870 for (i = 0; i < IWL_POWER_AC; i++) {
1871 cmd = &pow_data->pwr_range_0[i].cmd;
1872
1873 if (pci_pm & 0x1)
1874 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1875 else
1876 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1877 }
1878 }
1879 return rc;
1880}
1881
bb8c093b 1882static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
600c0e11 1883 struct iwl_powertable_cmd *cmd, u32 mode)
b481de9c
ZY
1884{
1885 int rc = 0, i;
1886 u8 skip;
1887 u32 max_sleep = 0;
bb8c093b 1888 struct iwl3945_power_vec_entry *range;
b481de9c 1889 u8 period = 0;
bb8c093b 1890 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY
1891
1892 if (mode > IWL_POWER_INDEX_5) {
1893 IWL_DEBUG_POWER("Error invalid power mode \n");
1894 return -1;
1895 }
1896 pow_data = &(priv->power_data);
1897
1898 if (pow_data->active_index == IWL_POWER_RANGE_0)
1899 range = &pow_data->pwr_range_0[0];
1900 else
1901 range = &pow_data->pwr_range_1[1];
1902
bb8c093b 1903 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY
1904
1905#ifdef IWL_MAC80211_DISABLE
1906 if (priv->assoc_network != NULL) {
1907 unsigned long flags;
1908
1909 period = priv->assoc_network->tim.tim_period;
1910 }
1911#endif /*IWL_MAC80211_DISABLE */
1912 skip = range[mode].no_dtim;
1913
1914 if (period == 0) {
1915 period = 1;
1916 skip = 0;
1917 }
1918
1919 if (skip == 0) {
1920 max_sleep = period;
1921 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1922 } else {
1923 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1924 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1925 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1926 }
1927
1928 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1929 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1930 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1931 }
1932
1933 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1934 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1935 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1936 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1937 le32_to_cpu(cmd->sleep_interval[0]),
1938 le32_to_cpu(cmd->sleep_interval[1]),
1939 le32_to_cpu(cmd->sleep_interval[2]),
1940 le32_to_cpu(cmd->sleep_interval[3]),
1941 le32_to_cpu(cmd->sleep_interval[4]));
1942
1943 return rc;
1944}
1945
bb8c093b 1946static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1947{
9a62f73b 1948 u32 uninitialized_var(final_mode);
b481de9c 1949 int rc;
600c0e11 1950 struct iwl_powertable_cmd cmd;
b481de9c
ZY
1951
1952 /* If on battery, set to 3,
01ebd063 1953 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY
1954 * else user level */
1955 switch (mode) {
1956 case IWL_POWER_BATTERY:
1957 final_mode = IWL_POWER_INDEX_3;
1958 break;
1959 case IWL_POWER_AC:
1960 final_mode = IWL_POWER_MODE_CAM;
1961 break;
1962 default:
1963 final_mode = mode;
1964 break;
1965 }
1966
bb8c093b 1967 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1968
600c0e11
TW
1969 /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
1970 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
1971 sizeof(struct iwl3945_powertable_cmd), &cmd);
b481de9c
ZY
1972
1973 if (final_mode == IWL_POWER_MODE_CAM)
1974 clear_bit(STATUS_POWER_PMI, &priv->status);
1975 else
1976 set_bit(STATUS_POWER_PMI, &priv->status);
1977
1978 return rc;
1979}
1980
b481de9c 1981/**
bb8c093b 1982 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY
1983 *
1984 * NOTE: priv->mutex is not required before calling this function
1985 */
bb8c093b 1986static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY
1987{
1988 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1989 clear_bit(STATUS_SCANNING, &priv->status);
1990 return 0;
1991 }
1992
1993 if (test_bit(STATUS_SCANNING, &priv->status)) {
1994 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1995 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1996 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1997 queue_work(priv->workqueue, &priv->abort_scan);
1998
1999 } else
2000 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2001
2002 return test_bit(STATUS_SCANNING, &priv->status);
2003 }
2004
2005 return 0;
2006}
2007
2008/**
bb8c093b 2009 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY
2010 * @ms: amount of time to wait (in milliseconds) for scan to abort
2011 *
2012 * NOTE: priv->mutex must be held before calling this function
2013 */
bb8c093b 2014static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY
2015{
2016 unsigned long now = jiffies;
2017 int ret;
2018
bb8c093b 2019 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY
2020 if (ret && ms) {
2021 mutex_unlock(&priv->mutex);
2022 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2023 test_bit(STATUS_SCANNING, &priv->status))
2024 msleep(1);
2025 mutex_lock(&priv->mutex);
2026
2027 return test_bit(STATUS_SCANNING, &priv->status);
2028 }
2029
2030 return ret;
2031}
2032
b481de9c
ZY
2033#define MAX_UCODE_BEACON_INTERVAL 1024
2034#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2035
bb8c093b 2036static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
2037{
2038 u16 new_val = 0;
2039 u16 beacon_factor = 0;
2040
2041 beacon_factor =
2042 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2043 / MAX_UCODE_BEACON_INTERVAL;
2044 new_val = beacon_val / beacon_factor;
2045
2046 return cpu_to_le16(new_val);
2047}
2048
bb8c093b 2049static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY
2050{
2051 u64 interval_tm_unit;
2052 u64 tsf, result;
2053 unsigned long flags;
2054 struct ieee80211_conf *conf = NULL;
2055 u16 beacon_int = 0;
2056
2057 conf = ieee80211_get_hw_conf(priv->hw);
2058
2059 spin_lock_irqsave(&priv->lock, flags);
28afaf91 2060 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b481de9c
ZY
2061 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2062
28afaf91 2063 tsf = priv->timestamp;
b481de9c
ZY
2064
2065 beacon_int = priv->beacon_int;
2066 spin_unlock_irqrestore(&priv->lock, flags);
2067
05c914fe 2068 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY
2069 if (beacon_int == 0) {
2070 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2071 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2072 } else {
2073 priv->rxon_timing.beacon_interval =
2074 cpu_to_le16(beacon_int);
2075 priv->rxon_timing.beacon_interval =
bb8c093b 2076 iwl3945_adjust_beacon_interval(
b481de9c
ZY
2077 le16_to_cpu(priv->rxon_timing.beacon_interval));
2078 }
2079
2080 priv->rxon_timing.atim_window = 0;
2081 } else {
2082 priv->rxon_timing.beacon_interval =
bb8c093b 2083 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY
2084 /* TODO: we need to get atim_window from upper stack
2085 * for now we set to 0 */
2086 priv->rxon_timing.atim_window = 0;
2087 }
2088
2089 interval_tm_unit =
2090 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2091 result = do_div(tsf, interval_tm_unit);
2092 priv->rxon_timing.beacon_init_val =
2093 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2094
2095 IWL_DEBUG_ASSOC
2096 ("beacon interval %d beacon timer %d beacon tim %d\n",
2097 le16_to_cpu(priv->rxon_timing.beacon_interval),
2098 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2099 le16_to_cpu(priv->rxon_timing.atim_window));
2100}
2101
bb8c093b 2102static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c 2103{
bb8c093b 2104 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
2105 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2106 return -EIO;
2107 }
2108
2109 if (test_bit(STATUS_SCANNING, &priv->status)) {
2110 IWL_DEBUG_SCAN("Scan already in progress.\n");
2111 return -EAGAIN;
2112 }
2113
2114 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2115 IWL_DEBUG_SCAN("Scan request while abort pending. "
2116 "Queuing.\n");
2117 return -EAGAIN;
2118 }
2119
2120 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR
2121 if (priv->cfg->sku & IWL_SKU_G)
2122 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2123 if (priv->cfg->sku & IWL_SKU_A)
2124 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY
2125 set_bit(STATUS_SCANNING, &priv->status);
2126 priv->scan_start = jiffies;
2127 priv->scan_pass_start = priv->scan_start;
2128
2129 queue_work(priv->workqueue, &priv->request_scan);
2130
2131 return 0;
2132}
2133
bb8c093b 2134static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2135{
bb8c093b 2136 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY
2137
2138 if (hw_decrypt)
2139 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2140 else
2141 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2142
2143 return 0;
2144}
2145
8318d78a
JB
2146static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2147 enum ieee80211_band band)
b481de9c 2148{
8318d78a 2149 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY
2150 priv->staging_rxon.flags &=
2151 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2152 | RXON_FLG_CCK_MSK);
2153 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2154 } else {
bb8c093b 2155 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY
2156 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2157 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2158 else
2159 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2160
05c914fe 2161 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2162 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2163
2164 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2165 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2166 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2167 }
2168}
2169
2170/*
01ebd063 2171 * initialize rxon structure with default values from eeprom
b481de9c 2172 */
60294de3
ZY
2173static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
2174 int mode)
b481de9c 2175{
bb8c093b 2176 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY
2177
2178 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2179
60294de3 2180 switch (mode) {
05c914fe 2181 case NL80211_IFTYPE_AP:
b481de9c
ZY
2182 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2183 break;
2184
05c914fe 2185 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2186 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2187 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2188 break;
2189
05c914fe 2190 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY
2191 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2192 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2193 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2194 RXON_FILTER_ACCEPT_GRP_MSK;
2195 break;
2196
05c914fe 2197 case NL80211_IFTYPE_MONITOR:
b481de9c
ZY
2198 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2199 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2200 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2201 break;
69dc5d9d 2202 default:
60294de3 2203 IWL_ERROR("Unsupported interface type %d\n", mode);
69dc5d9d 2204 break;
b481de9c
ZY
2205 }
2206
2207#if 0
2208 /* TODO: Figure out when short_preamble would be set and cache from
2209 * that */
2210 if (!hw_to_local(priv->hw)->short_preamble)
2211 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2212 else
2213 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2214#endif
2215
8318d78a 2216 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2217 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY
2218
2219 if (!ch_info)
2220 ch_info = &priv->channel_info[0];
2221
2222 /*
2223 * in some case A channels are all non IBSS
2224 * in this case force B/G channel
2225 */
60294de3 2226 if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
b481de9c
ZY
2227 ch_info = &priv->channel_info[0];
2228
2229 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2230 if (is_channel_a_band(ch_info))
8318d78a 2231 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2232 else
8318d78a 2233 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2234
8318d78a 2235 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY
2236
2237 priv->staging_rxon.ofdm_basic_rates =
2238 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2239 priv->staging_rxon.cck_basic_rates =
2240 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2241}
2242
bb8c093b 2243static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2244{
05c914fe 2245 if (mode == NL80211_IFTYPE_ADHOC) {
bb8c093b 2246 const struct iwl3945_channel_info *ch_info;
b481de9c 2247
bb8c093b 2248 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2249 priv->band,
b481de9c
ZY
2250 le16_to_cpu(priv->staging_rxon.channel));
2251
2252 if (!ch_info || !is_channel_ibss(ch_info)) {
2253 IWL_ERROR("channel %d not IBSS channel\n",
2254 le16_to_cpu(priv->staging_rxon.channel));
2255 return -EINVAL;
2256 }
2257 }
2258
60294de3 2259 iwl3945_connection_init_rx_config(priv, mode);
b481de9c
ZY
2260 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2261
bb8c093b 2262 iwl3945_clear_stations_table(priv);
b481de9c 2263
a96a27f9 2264 /* don't commit rxon if rf-kill is on*/
fde3571f
MA
2265 if (!iwl3945_is_ready_rf(priv))
2266 return -EAGAIN;
2267
2268 cancel_delayed_work(&priv->scan_check);
2269 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2270 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2271 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2272 return -EAGAIN;
2273 }
2274
bb8c093b 2275 iwl3945_commit_rxon(priv);
b481de9c
ZY
2276
2277 return 0;
2278}
2279
bb8c093b 2280static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2281 struct ieee80211_tx_info *info,
bb8c093b 2282 struct iwl3945_cmd *cmd,
b481de9c
ZY
2283 struct sk_buff *skb_frag,
2284 int last_frag)
2285{
1c014420 2286 struct iwl3945_hw_key *keyinfo =
e039fa4a 2287 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY
2288
2289 switch (keyinfo->alg) {
2290 case ALG_CCMP:
2291 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2292 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
a96a27f9 2293 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
b481de9c
ZY
2294 break;
2295
2296 case ALG_TKIP:
2297#if 0
2298 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2299
2300 if (last_frag)
2301 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2302 8);
2303 else
2304 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2305#endif
2306 break;
2307
2308 case ALG_WEP:
2309 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2310 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
2311
2312 if (keyinfo->keylen == 13)
2313 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2314
2315 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2316
2317 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2318 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
2319 break;
2320
b481de9c
ZY
2321 default:
2322 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2323 break;
2324 }
2325}
2326
2327/*
2328 * handle build REPLY_TX command notification.
2329 */
bb8c093b
CH
2330static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2331 struct iwl3945_cmd *cmd,
e039fa4a 2332 struct ieee80211_tx_info *info,
b481de9c
ZY
2333 struct ieee80211_hdr *hdr,
2334 int is_unicast, u8 std_id)
2335{
fd7c8a40 2336 __le16 fc = hdr->frame_control;
b481de9c 2337 __le32 tx_flags = cmd->cmd.tx.tx_flags;
e6a9854b 2338 u8 rc_flags = info->control.rates[0].flags;
b481de9c
ZY
2339
2340 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2341 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2342 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2343 if (ieee80211_is_mgmt(fc))
b481de9c 2344 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2345 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
2346 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2347 tx_flags |= TX_CMD_FLG_TSF_MSK;
2348 } else {
2349 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2350 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2351 }
2352
2353 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2354 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
2355 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2356
fd7c8a40
HH
2357 if (ieee80211_is_data_qos(fc)) {
2358 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2359 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2360 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2361 } else {
b481de9c 2362 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2363 }
b481de9c 2364
e6a9854b 2365 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
2366 tx_flags |= TX_CMD_FLG_RTS_MSK;
2367 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2368 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY
2369 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2370 tx_flags |= TX_CMD_FLG_CTS_MSK;
2371 }
2372
2373 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2374 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2375
2376 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
2377 if (ieee80211_is_mgmt(fc)) {
2378 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2379 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2380 else
bc434dd2 2381 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2382 } else {
b481de9c 2383 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA
2384#ifdef CONFIG_IWL3945_LEDS
2385 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2386#endif
2387 }
b481de9c
ZY
2388
2389 cmd->cmd.tx.driver_txop = 0;
2390 cmd->cmd.tx.tx_flags = tx_flags;
2391 cmd->cmd.tx.next_frame_len = 0;
2392}
2393
6440adb5
BC
2394/**
2395 * iwl3945_get_sta_id - Find station's index within station table
2396 */
bb8c093b 2397static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY
2398{
2399 int sta_id;
2400 u16 fc = le16_to_cpu(hdr->frame_control);
2401
6440adb5 2402 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY
2403 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2404 is_multicast_ether_addr(hdr->addr1))
2405 return priv->hw_setting.bcast_sta_id;
2406
2407 switch (priv->iw_mode) {
2408
6440adb5
BC
2409 /* If we are a client station in a BSS network, use the special
2410 * AP station entry (that's the only station we communicate with) */
05c914fe 2411 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2412 return IWL_AP_ID;
2413
2414 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2415 case NL80211_IFTYPE_AP:
bb8c093b 2416 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2417 if (sta_id != IWL_INVALID_STATION)
2418 return sta_id;
2419 return priv->hw_setting.bcast_sta_id;
2420
6440adb5
BC
2421 /* If this frame is going out to an IBSS network, find the station,
2422 * or create a new station table entry */
05c914fe 2423 case NL80211_IFTYPE_ADHOC: {
6440adb5 2424 /* Create new station table entry */
bb8c093b 2425 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2426 if (sta_id != IWL_INVALID_STATION)
2427 return sta_id;
2428
bb8c093b 2429 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY
2430
2431 if (sta_id != IWL_INVALID_STATION)
2432 return sta_id;
2433
e174961c 2434 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2435 "Defaulting to broadcast...\n",
e174961c 2436 hdr->addr1);
bb8c093b 2437 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2438 return priv->hw_setting.bcast_sta_id;
0795af57 2439 }
914233d6
SG
2440 /* If we are in monitor mode, use BCAST. This is required for
2441 * packet injection. */
05c914fe 2442 case NL80211_IFTYPE_MONITOR:
914233d6
SG
2443 return priv->hw_setting.bcast_sta_id;
2444
b481de9c 2445 default:
6f147926 2446 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
b481de9c
ZY
2447 return priv->hw_setting.bcast_sta_id;
2448 }
2449}
2450
2451/*
2452 * start REPLY_TX command process
2453 */
e039fa4a 2454static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY
2455{
2456 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2457 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2458 struct iwl3945_tfd_frame *tfd;
b481de9c 2459 u32 *control_flags;
e2530083 2460 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH
2461 struct iwl3945_tx_queue *txq = NULL;
2462 struct iwl3945_queue *q = NULL;
b481de9c
ZY
2463 dma_addr_t phys_addr;
2464 dma_addr_t txcmd_phys;
bb8c093b 2465 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW
2466 u16 len, idx, len_org, hdr_len;
2467 u8 id;
2468 u8 unicast;
b481de9c 2469 u8 sta_id;
54dbb525 2470 u8 tid = 0;
b481de9c 2471 u16 seq_number = 0;
fd7c8a40 2472 __le16 fc;
b481de9c 2473 u8 wait_write_ptr = 0;
54dbb525 2474 u8 *qc = NULL;
b481de9c
ZY
2475 unsigned long flags;
2476 int rc;
2477
2478 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2479 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY
2480 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2481 goto drop_unlock;
2482 }
2483
e039fa4a 2484 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY
2485 IWL_ERROR("ERROR: No TX rate available.\n");
2486 goto drop_unlock;
2487 }
2488
2489 unicast = !is_multicast_ether_addr(hdr->addr1);
2490 id = 0;
2491
fd7c8a40 2492 fc = hdr->frame_control;
b481de9c 2493
c8b0e6e1 2494#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
2495 if (ieee80211_is_auth(fc))
2496 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2497 else if (ieee80211_is_assoc_req(fc))
b481de9c 2498 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2499 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY
2500 IWL_DEBUG_TX("Sending REASSOC frame\n");
2501#endif
2502
7878a5a4 2503 /* drop all data frame if we are not associated */
914233d6 2504 if (ieee80211_is_data(fc) &&
05c914fe 2505 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2506 (!iwl3945_is_associated(priv) ||
05c914fe 2507 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2508 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY
2509 goto drop_unlock;
2510 }
2511
2512 spin_unlock_irqrestore(&priv->lock, flags);
2513
7294ec95 2514 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
2515
2516 /* Find (or create) index into station table for destination station */
bb8c093b 2517 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2518 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB
2519 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2520 hdr->addr1);
b481de9c
ZY
2521 goto drop;
2522 }
2523
2524 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2525
fd7c8a40
HH
2526 if (ieee80211_is_data_qos(fc)) {
2527 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2528 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
b481de9c
ZY
2529 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2530 IEEE80211_SCTL_SEQ;
2531 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2532 (hdr->seq_ctrl &
2533 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2534 seq_number += 0x10;
2535 }
6440adb5
BC
2536
2537 /* Descriptor for chosen Tx queue */
b481de9c
ZY
2538 txq = &priv->txq[txq_id];
2539 q = &txq->q;
2540
2541 spin_lock_irqsave(&priv->lock, flags);
2542
6440adb5 2543 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2544 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY
2545 memset(tfd, 0, sizeof(*tfd));
2546 control_flags = (u32 *) tfd;
fc4b6853 2547 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2548
6440adb5 2549 /* Set up driver data for this TFD */
bb8c093b 2550 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2551 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
2552
2553 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY
2554 out_cmd = &txq->cmd[idx];
2555 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2556 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
BC
2557
2558 /*
2559 * Set up the Tx-command (not MAC!) header.
2560 * Store the chosen Tx queue and TFD index within the sequence field;
2561 * after Tx, uCode's Tx response will return this value so driver can
2562 * locate the frame within the tx queue and do post-tx processing.
2563 */
b481de9c
ZY
2564 out_cmd->hdr.cmd = REPLY_TX;
2565 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2566 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
2567
2568 /* Copy MAC header from skb into command buffer */
b481de9c
ZY
2569 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2570
6440adb5
BC
2571 /*
2572 * Use the first empty entry in this queue's command buffer array
2573 * to contain the Tx command and MAC header concatenated together
2574 * (payload data will be in another buffer).
2575 * Size of this varies, due to varying MAC header length.
2576 * If end is not dword aligned, we'll have 2 extra bytes at the end
2577 * of the MAC header (device reads on dword boundaries).
2578 * We'll tell device about this padding later.
2579 */
b481de9c 2580 len = priv->hw_setting.tx_cmd_len +
4c897253 2581 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
2582
2583 len_org = len;
2584 len = (len + 3) & ~3;
2585
2586 if (len_org != len)
2587 len_org = 1;
2588 else
2589 len_org = 0;
2590
6440adb5
BC
2591 /* Physical address of this Tx command's header (not MAC header!),
2592 * within command buffer array. */
bb8c093b
CH
2593 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2594 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2595
6440adb5
BC
2596 /* Add buffer containing Tx command and MAC(!) header to TFD's
2597 * first entry */
bb8c093b 2598 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2599
d0f09804 2600 if (info->control.hw_key)
e039fa4a 2601 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2602
6440adb5
BC
2603 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2604 * if any (802.11 null frames have no payload). */
b481de9c
ZY
2605 len = skb->len - hdr_len;
2606 if (len) {
2607 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2608 len, PCI_DMA_TODEVICE);
bb8c093b 2609 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY
2610 }
2611
b481de9c 2612 if (!len)
6440adb5 2613 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY
2614 *control_flags = TFD_CTL_COUNT_SET(1);
2615 else
6440adb5
BC
2616 /* Else use 2 buffers.
2617 * Tell 3945 about any padding after MAC header */
b481de9c
ZY
2618 *control_flags = TFD_CTL_COUNT_SET(2) |
2619 TFD_CTL_PAD_SET(U32_PAD(len));
2620
6440adb5 2621 /* Total # bytes to be transmitted */
b481de9c
ZY
2622 len = (u16)skb->len;
2623 out_cmd->cmd.tx.len = cpu_to_le16(len);
2624
2625 /* TODO need this for burst mode later on */
e039fa4a 2626 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY
2627
2628 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2629 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY
2630
2631 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2632 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2633
8b7b1e05 2634 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2635 txq->need_update = 1;
3ac7f146 2636 if (qc)
b481de9c 2637 priv->stations[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY
2638 } else {
2639 wait_write_ptr = 1;
2640 txq->need_update = 0;
2641 }
2642
bb8c093b 2643 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY
2644 sizeof(out_cmd->cmd.tx));
2645
bb8c093b 2646 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
7294ec95 2647 ieee80211_hdrlen(fc));
b481de9c 2648
6440adb5 2649 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2650 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2651 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2652 spin_unlock_irqrestore(&priv->lock, flags);
2653
2654 if (rc)
2655 return rc;
2656
bb8c093b 2657 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY
2658 && priv->mac80211_registered) {
2659 if (wait_write_ptr) {
2660 spin_lock_irqsave(&priv->lock, flags);
2661 txq->need_update = 1;
bb8c093b 2662 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2663 spin_unlock_irqrestore(&priv->lock, flags);
2664 }
2665
e2530083 2666 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY
2667 }
2668
2669 return 0;
2670
2671drop_unlock:
2672 spin_unlock_irqrestore(&priv->lock, flags);
2673drop:
2674 return -1;
2675}
2676
bb8c093b 2677static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2678{
8318d78a 2679 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY
2680 struct ieee80211_rate *rate;
2681 int i;
2682
8318d78a
JB
2683 sband = iwl3945_get_band(priv, priv->band);
2684 if (!sband) {
c4ba9621
SA
2685 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2686 return;
2687 }
b481de9c
ZY
2688
2689 priv->active_rate = 0;
2690 priv->active_rate_basic = 0;
2691
8318d78a
JB
2692 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2693 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2694
2695 for (i = 0; i < sband->n_bitrates; i++) {
2696 rate = &sband->bitrates[i];
2697 if ((rate->hw_value < IWL_RATE_COUNT) &&
2698 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2699 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2700 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2701 priv->active_rate |= (1 << rate->hw_value);
2702 }
b481de9c
ZY
2703 }
2704
2705 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2706 priv->active_rate, priv->active_rate_basic);
2707
2708 /*
2709 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2710 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2711 * OFDM
2712 */
2713 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2714 priv->staging_rxon.cck_basic_rates =
2715 ((priv->active_rate_basic &
2716 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2717 else
2718 priv->staging_rxon.cck_basic_rates =
2719 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2720
2721 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2722 priv->staging_rxon.ofdm_basic_rates =
2723 ((priv->active_rate_basic &
2724 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2725 IWL_FIRST_OFDM_RATE) & 0xFF;
2726 else
2727 priv->staging_rxon.ofdm_basic_rates =
2728 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2729}
2730
bb8c093b 2731static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY
2732{
2733 unsigned long flags;
2734
2735 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2736 return;
2737
2738 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2739 disable_radio ? "OFF" : "ON");
2740
2741 if (disable_radio) {
bb8c093b 2742 iwl3945_scan_cancel(priv);
b481de9c 2743 /* FIXME: This is a workaround for AP */
05c914fe 2744 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2745 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2746 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
2747 CSR_UCODE_SW_BIT_RFKILL);
2748 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2749 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY
2750 set_bit(STATUS_RF_KILL_SW, &priv->status);
2751 }
2752 return;
2753 }
2754
2755 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2756 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2757
2758 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2759 spin_unlock_irqrestore(&priv->lock, flags);
2760
2761 /* wake up ucode */
2762 msleep(10);
2763
2764 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
2765 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2766 if (!iwl3945_grab_nic_access(priv))
2767 iwl3945_release_nic_access(priv);
b481de9c
ZY
2768 spin_unlock_irqrestore(&priv->lock, flags);
2769
2770 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2771 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2772 "disabled by HW switch\n");
2773 return;
2774 }
2775
808e72a0
ZY
2776 if (priv->is_open)
2777 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY
2778 return;
2779}
2780
bb8c093b 2781void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY
2782 u32 decrypt_res, struct ieee80211_rx_status *stats)
2783{
2784 u16 fc =
2785 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2786
2787 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2788 return;
2789
2790 if (!(fc & IEEE80211_FCTL_PROTECTED))
2791 return;
2792
2793 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2794 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2795 case RX_RES_STATUS_SEC_TYPE_TKIP:
2796 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2797 RX_RES_STATUS_BAD_ICV_MIC)
2798 stats->flag |= RX_FLAG_MMIC_ERROR;
2799 case RX_RES_STATUS_SEC_TYPE_WEP:
2800 case RX_RES_STATUS_SEC_TYPE_CCMP:
2801 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2802 RX_RES_STATUS_DECRYPT_OK) {
2803 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2804 stats->flag |= RX_FLAG_DECRYPTED;
2805 }
2806 break;
2807
2808 default:
2809 break;
2810 }
2811}
2812
c8b0e6e1 2813#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
2814
2815#include "iwl-spectrum.h"
2816
2817#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2818#define BEACON_TIME_MASK_HIGH 0xFF000000
2819#define TIME_UNIT 1024
2820
2821/*
2822 * extended beacon time format
2823 * time in usec will be changed into a 32-bit value in 8:24 format
2824 * the high 1 byte is the beacon counts
2825 * the lower 3 bytes is the time in usec within one beacon interval
2826 */
2827
bb8c093b 2828static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
2829{
2830 u32 quot;
2831 u32 rem;
2832 u32 interval = beacon_interval * 1024;
2833
2834 if (!interval || !usec)
2835 return 0;
2836
2837 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2838 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2839
2840 return (quot << 24) + rem;
2841}
2842
2843/* base is usually what we get from ucode with each received frame,
2844 * the same as HW timer counter counting down
2845 */
2846
bb8c093b 2847static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
2848{
2849 u32 base_low = base & BEACON_TIME_MASK_LOW;
2850 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2851 u32 interval = beacon_interval * TIME_UNIT;
2852 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2853 (addon & BEACON_TIME_MASK_HIGH);
2854
2855 if (base_low > addon_low)
2856 res += base_low - addon_low;
2857 else if (base_low < addon_low) {
2858 res += interval + base_low - addon_low;
2859 res += (1 << 24);
2860 } else
2861 res += (1 << 24);
2862
2863 return cpu_to_le32(res);
2864}
2865
bb8c093b 2866static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY
2867 struct ieee80211_measurement_params *params,
2868 u8 type)
2869{
600c0e11 2870 struct iwl_spectrum_cmd spectrum;
3d24a9f7 2871 struct iwl_rx_packet *res;
bb8c093b 2872 struct iwl3945_host_cmd cmd = {
b481de9c
ZY
2873 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2874 .data = (void *)&spectrum,
2875 .meta.flags = CMD_WANT_SKB,
2876 };
2877 u32 add_time = le64_to_cpu(params->start_time);
2878 int rc;
2879 int spectrum_resp_status;
2880 int duration = le16_to_cpu(params->duration);
2881
bb8c093b 2882 if (iwl3945_is_associated(priv))
b481de9c 2883 add_time =
bb8c093b 2884 iwl3945_usecs_to_beacons(
b481de9c
ZY
2885 le64_to_cpu(params->start_time) - priv->last_tsf,
2886 le16_to_cpu(priv->rxon_timing.beacon_interval));
2887
2888 memset(&spectrum, 0, sizeof(spectrum));
2889
2890 spectrum.channel_count = cpu_to_le16(1);
2891 spectrum.flags =
2892 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2893 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2894 cmd.len = sizeof(spectrum);
2895 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2896
bb8c093b 2897 if (iwl3945_is_associated(priv))
b481de9c 2898 spectrum.start_time =
bb8c093b 2899 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
2900 add_time,
2901 le16_to_cpu(priv->rxon_timing.beacon_interval));
2902 else
2903 spectrum.start_time = 0;
2904
2905 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2906 spectrum.channels[0].channel = params->channel;
2907 spectrum.channels[0].type = type;
2908 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2909 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2910 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2911
bb8c093b 2912 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2913 if (rc)
2914 return rc;
2915
3d24a9f7 2916 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
2917 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2918 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2919 rc = -EIO;
2920 }
2921
2922 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2923 switch (spectrum_resp_status) {
2924 case 0: /* Command will be handled */
2925 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS
2926 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2927 res->u.spectrum.id);
b481de9c
ZY
2928 priv->measurement_status &= ~MEASUREMENT_READY;
2929 }
2930 priv->measurement_status |= MEASUREMENT_ACTIVE;
2931 rc = 0;
2932 break;
2933
2934 case 1: /* Command will not be handled */
2935 rc = -EAGAIN;
2936 break;
2937 }
2938
2939 dev_kfree_skb_any(cmd.meta.u.skb);
2940
2941 return rc;
2942}
2943#endif
2944
bb8c093b
CH
2945static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
2946 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2947{
3d24a9f7
TW
2948 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
2949 struct iwl_alive_resp *palive;
b481de9c
ZY
2950 struct delayed_work *pwork;
2951
2952 palive = &pkt->u.alive_frame;
2953
2954 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2955 "0x%01X 0x%01X\n",
2956 palive->is_valid, palive->ver_type,
2957 palive->ver_subtype);
2958
2959 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2960 IWL_DEBUG_INFO("Initialization Alive received.\n");
3d24a9f7
TW
2961 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
2962 sizeof(struct iwl_alive_resp));
b481de9c
ZY
2963 pwork = &priv->init_alive_start;
2964 } else {
2965 IWL_DEBUG_INFO("Runtime Alive received.\n");
2966 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 2967 sizeof(struct iwl_alive_resp));
b481de9c 2968 pwork = &priv->alive_start;
bb8c093b 2969 iwl3945_disable_events(priv);
b481de9c
ZY
2970 }
2971
2972 /* We delay the ALIVE response by 5ms to
2973 * give the HW RF Kill time to activate... */
2974 if (palive->is_valid == UCODE_VALID_OK)
2975 queue_delayed_work(priv->workqueue, pwork,
2976 msecs_to_jiffies(5));
2977 else
2978 IWL_WARNING("uCode did not respond OK.\n");
2979}
2980
bb8c093b
CH
2981static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
2982 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2983{
3d24a9f7 2984 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2985
2986 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2987 return;
2988}
2989
bb8c093b
CH
2990static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
2991 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2992{
3d24a9f7 2993 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2994
2995 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
2996 "seq 0x%04X ser 0x%08X\n",
2997 le32_to_cpu(pkt->u.err_resp.error_type),
2998 get_cmd_string(pkt->u.err_resp.cmd_id),
2999 pkt->u.err_resp.cmd_id,
3000 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3001 le32_to_cpu(pkt->u.err_resp.error_info));
3002}
3003
3004#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3005
bb8c093b 3006static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3007{
3d24a9f7 3008 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 3009 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
600c0e11 3010 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY
3011 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3012 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3013 rxon->channel = csa->channel;
3014 priv->staging_rxon.channel = csa->channel;
3015}
3016
bb8c093b
CH
3017static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3018 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3019{
c8b0e6e1 3020#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3d24a9f7 3021 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 3022 struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY
3023
3024 if (!report->state) {
3025 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3026 "Spectrum Measure Notification: Start\n");
3027 return;
3028 }
3029
3030 memcpy(&priv->measure_report, report, sizeof(*report));
3031 priv->measurement_status |= MEASUREMENT_READY;
3032#endif
3033}
3034
bb8c093b
CH
3035static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3036 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3037{
c8b0e6e1 3038#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 3039 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 3040 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY
3041 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3042 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3043#endif
3044}
3045
bb8c093b
CH
3046static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3047 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3048{
3d24a9f7 3049 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3050 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3051 "notification for %s:\n",
3052 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3053 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY
3054}
3055
bb8c093b 3056static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3057{
bb8c093b
CH
3058 struct iwl3945_priv *priv =
3059 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY
3060 struct sk_buff *beacon;
3061
3062 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3063 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
3064
3065 if (!beacon) {
3066 IWL_ERROR("update beacon failed\n");
3067 return;
3068 }
3069
3070 mutex_lock(&priv->mutex);
3071 /* new beacon skb is allocated every time; dispose previous.*/
3072 if (priv->ibss_beacon)
3073 dev_kfree_skb(priv->ibss_beacon);
3074
3075 priv->ibss_beacon = beacon;
3076 mutex_unlock(&priv->mutex);
3077
bb8c093b 3078 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3079}
3080
bb8c093b
CH
3081static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3082 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3083{
c8b0e6e1 3084#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 3085 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 3086 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
3087 u8 rate = beacon->beacon_notify_hdr.rate;
3088
3089 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3090 "tsf %d %d rate %d\n",
3091 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3092 beacon->beacon_notify_hdr.failure_frame,
3093 le32_to_cpu(beacon->ibss_mgr_status),
3094 le32_to_cpu(beacon->high_tsf),
3095 le32_to_cpu(beacon->low_tsf), rate);
3096#endif
3097
05c914fe 3098 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
3099 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3100 queue_work(priv->workqueue, &priv->beacon_update);
3101}
3102
3103/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH
3104static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3105 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3106{
c8b0e6e1 3107#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 3108 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
3109 struct iwl_scanreq_notification *notif =
3110 (struct iwl_scanreq_notification *)pkt->u.raw;
b481de9c
ZY
3111
3112 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3113#endif
3114}
3115
3116/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH
3117static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3118 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3119{
3d24a9f7 3120 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
3121 struct iwl_scanstart_notification *notif =
3122 (struct iwl_scanstart_notification *)pkt->u.raw;
b481de9c
ZY
3123 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3124 IWL_DEBUG_SCAN("Scan start: "
3125 "%d [802.11%s] "
3126 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3127 notif->channel,
3128 notif->band ? "bg" : "a",
3129 notif->tsf_high,
3130 notif->tsf_low, notif->status, notif->beacon_timer);
3131}
3132
3133/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH
3134static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3135 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3136{
3d24a9f7 3137 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
3138 struct iwl_scanresults_notification *notif =
3139 (struct iwl_scanresults_notification *)pkt->u.raw;
b481de9c
ZY
3140
3141 IWL_DEBUG_SCAN("Scan ch.res: "
3142 "%d [802.11%s] "
3143 "(TSF: 0x%08X:%08X) - %d "
3144 "elapsed=%lu usec (%dms since last)\n",
3145 notif->channel,
3146 notif->band ? "bg" : "a",
3147 le32_to_cpu(notif->tsf_high),
3148 le32_to_cpu(notif->tsf_low),
3149 le32_to_cpu(notif->statistics[0]),
3150 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3151 jiffies_to_msecs(elapsed_jiffies
3152 (priv->last_scan_jiffies, jiffies)));
3153
3154 priv->last_scan_jiffies = jiffies;
7878a5a4 3155 priv->next_scan_jiffies = 0;
b481de9c
ZY
3156}
3157
3158/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH
3159static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3160 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3161{
3d24a9f7 3162 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253 3163 struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY
3164
3165 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3166 scan_notif->scanned_channels,
3167 scan_notif->tsf_low,
3168 scan_notif->tsf_high, scan_notif->status);
3169
3170 /* The HW is no longer scanning */
3171 clear_bit(STATUS_SCAN_HW, &priv->status);
3172
3173 /* The scan completion notification came in, so kill that timer... */
3174 cancel_delayed_work(&priv->scan_check);
3175
3176 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR
3177 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3178 "2.4" : "5.2",
b481de9c
ZY
3179 jiffies_to_msecs(elapsed_jiffies
3180 (priv->scan_pass_start, jiffies)));
3181
66b5004d
RR
3182 /* Remove this scanned band from the list of pending
3183 * bands to scan, band G precedes A in order of scanning
3184 * as seen in iwl3945_bg_request_scan */
3185 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3186 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3187 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3188 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY
3189
3190 /* If a request to abort was given, or the scan did not succeed
3191 * then we reset the scan state machine and terminate,
3192 * re-queuing another scan if one has been requested */
3193 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3194 IWL_DEBUG_INFO("Aborted scan completed.\n");
3195 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3196 } else {
3197 /* If there are more bands on this scan pass reschedule */
3198 if (priv->scan_bands > 0)
3199 goto reschedule;
3200 }
3201
3202 priv->last_scan_jiffies = jiffies;
7878a5a4 3203 priv->next_scan_jiffies = 0;
b481de9c
ZY
3204 IWL_DEBUG_INFO("Setting scan to off\n");
3205
3206 clear_bit(STATUS_SCANNING, &priv->status);
3207
3208 IWL_DEBUG_INFO("Scan took %dms\n",
3209 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3210
3211 queue_work(priv->workqueue, &priv->scan_completed);
3212
3213 return;
3214
3215reschedule:
3216 priv->scan_pass_start = jiffies;
3217 queue_work(priv->workqueue, &priv->request_scan);
3218}
3219
3220/* Handle notification from uCode that card's power state is changing
3221 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH
3222static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3223 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3224{
3d24a9f7 3225 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
3226 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3227 unsigned long status = priv->status;
3228
3229 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3230 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3231 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3232
bb8c093b 3233 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3234 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3235
3236 if (flags & HW_CARD_DISABLED)
3237 set_bit(STATUS_RF_KILL_HW, &priv->status);
3238 else
3239 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3240
3241
3242 if (flags & SW_CARD_DISABLED)
3243 set_bit(STATUS_RF_KILL_SW, &priv->status);
3244 else
3245 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3246
bb8c093b 3247 iwl3945_scan_cancel(priv);
b481de9c
ZY
3248
3249 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3250 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3251 (test_bit(STATUS_RF_KILL_SW, &status) !=
3252 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3253 queue_work(priv->workqueue, &priv->rf_kill);
3254 else
3255 wake_up_interruptible(&priv->wait_command_queue);
3256}
3257
3258/**
bb8c093b 3259 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
3260 *
3261 * Setup the RX handlers for each of the reply types sent from the uCode
3262 * to the host.
3263 *
3264 * This function chains into the hardware specific files for them to setup
3265 * any hardware specific handlers as well.
3266 */
bb8c093b 3267static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3268{
bb8c093b
CH
3269 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3270 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3271 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3272 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3273 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH
3274 iwl3945_rx_spectrum_measure_notif;
3275 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3276 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH
3277 iwl3945_rx_pm_debug_statistics_notif;
3278 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3279
9fbab516
BC
3280 /*
3281 * The same handler is used for both the REPLY to a discrete
3282 * statistics request from the host as well as for the periodic
3283 * statistics notifications (after received beacons) from the uCode.
b481de9c 3284 */
bb8c093b
CH
3285 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3286 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3287
bb8c093b
CH
3288 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3289 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3290 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3291 iwl3945_rx_scan_results_notif;
b481de9c 3292 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH
3293 iwl3945_rx_scan_complete_notif;
3294 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3295
9fbab516 3296 /* Set up hardware specific Rx handlers */
bb8c093b 3297 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
3298}
3299
91c066f2
TW
3300/**
3301 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3302 * When FW advances 'R' index, all entries between old and new 'R' index
3303 * need to be reclaimed.
3304 */
3305static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3306 int txq_id, int index)
3307{
3308 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3309 struct iwl3945_queue *q = &txq->q;
3310 int nfreed = 0;
3311
3312 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3313 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3314 "is out of range [0-%d] %d %d.\n", txq_id,
3315 index, q->n_bd, q->write_ptr, q->read_ptr);
3316 return;
3317 }
3318
3319 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3320 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3321 if (nfreed > 1) {
3322 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3323 q->write_ptr, q->read_ptr);
3324 queue_work(priv->workqueue, &priv->restart);
3325 break;
3326 }
3327 nfreed++;
3328 }
3329}
3330
3331
b481de9c 3332/**
bb8c093b 3333 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY
3334 * @rxb: Rx buffer to reclaim
3335 *
3336 * If an Rx buffer has an async callback associated with it the callback
3337 * will be executed. The attached skb (if present) will only be freed
3338 * if the callback returns 1
3339 */
bb8c093b
CH
3340static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3341 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3342{
3d24a9f7 3343 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
3344 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3345 int txq_id = SEQ_TO_QUEUE(sequence);
3346 int index = SEQ_TO_INDEX(sequence);
600c0e11 3347 int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
b481de9c 3348 int cmd_index;
bb8c093b 3349 struct iwl3945_cmd *cmd;
b481de9c 3350
b481de9c
ZY
3351 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3352
3353 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3354 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3355
3356 /* Input error checking is done when commands are added to queue. */
3357 if (cmd->meta.flags & CMD_WANT_SKB) {
3358 cmd->meta.source->u.skb = rxb->skb;
3359 rxb->skb = NULL;
3360 } else if (cmd->meta.u.callback &&
3361 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3362 rxb->skb = NULL;
3363
91c066f2 3364 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3365
3366 if (!(cmd->meta.flags & CMD_ASYNC)) {
3367 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3368 wake_up_interruptible(&priv->wait_command_queue);
3369 }
3370}
3371
3372/************************** RX-FUNCTIONS ****************************/
3373/*
3374 * Rx theory of operation
3375 *
3376 * The host allocates 32 DMA target addresses and passes the host address
3377 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3378 * 0 to 31
3379 *
3380 * Rx Queue Indexes
3381 * The host/firmware share two index registers for managing the Rx buffers.
3382 *
3383 * The READ index maps to the first position that the firmware may be writing
3384 * to -- the driver can read up to (but not including) this position and get
3385 * good data.
3386 * The READ index is managed by the firmware once the card is enabled.
3387 *
3388 * The WRITE index maps to the last position the driver has read from -- the
3389 * position preceding WRITE is the last slot the firmware can place a packet.
3390 *
3391 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3392 * WRITE = READ.
3393 *
9fbab516 3394 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
3395 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3396 *
9fbab516 3397 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
3398 * and fire the RX interrupt. The driver can then query the READ index and
3399 * process as many packets as possible, moving the WRITE index forward as it
3400 * resets the Rx queue buffers with new memory.
3401 *
3402 * The management in the driver is as follows:
3403 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3404 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3405 * to replenish the iwl->rxq->rx_free.
bb8c093b 3406 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
3407 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3408 * 'processed' and 'read' driver indexes as well)
3409 * + A received packet is processed and handed to the kernel network stack,
3410 * detached from the iwl->rxq. The driver 'processed' index is updated.
3411 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3412 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3413 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3414 * were enough free buffers and RX_STALLED is set it is cleared.
3415 *
3416 *
3417 * Driver sequence:
3418 *
9fbab516
BC
3419 * iwl3945_rx_queue_alloc() Allocates rx_free
3420 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3421 * iwl3945_rx_queue_restock
9fbab516 3422 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
3423 * queue, updates firmware pointers, and updates
3424 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3425 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
3426 *
3427 * -- enable interrupts --
9fbab516 3428 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY
3429 * READ INDEX, detaching the SKB from the pool.
3430 * Moves the packet buffer from queue to rx_used.
bb8c093b 3431 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
3432 * slots.
3433 * ...
3434 *
3435 */
3436
3437/**
bb8c093b 3438 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3439 */
bb8c093b 3440static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY
3441{
3442 int s = q->read - q->write;
3443 if (s <= 0)
3444 s += RX_QUEUE_SIZE;
3445 /* keep some buffer to not confuse full and empty queue */
3446 s -= 2;
3447 if (s < 0)
3448 s = 0;
3449 return s;
3450}
3451
3452/**
bb8c093b 3453 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3454 */
bb8c093b 3455int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY
3456{
3457 u32 reg = 0;
3458 int rc = 0;
3459 unsigned long flags;
3460
3461 spin_lock_irqsave(&q->lock, flags);
3462
3463 if (q->need_update == 0)
3464 goto exit_unlock;
3465
6440adb5 3466 /* If power-saving is in use, make sure device is awake */
b481de9c 3467 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3468 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3469
3470 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3471 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3472 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3473 goto exit_unlock;
3474 }
3475
bb8c093b 3476 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
3477 if (rc)
3478 goto exit_unlock;
3479
6440adb5 3480 /* Device expects a multiple of 8 */
bddadf86 3481 iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
b481de9c 3482 q->write & ~0x7);
bb8c093b 3483 iwl3945_release_nic_access(priv);
6440adb5
BC
3484
3485 /* Else device is assumed to be awake */
b481de9c 3486 } else
6440adb5 3487 /* Device expects a multiple of 8 */
bddadf86 3488 iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY
3489
3490
3491 q->need_update = 0;
3492
3493 exit_unlock:
3494 spin_unlock_irqrestore(&q->lock, flags);
3495 return rc;
3496}
3497
3498/**
9fbab516 3499 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3500 */
bb8c093b 3501static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY
3502 dma_addr_t dma_addr)
3503{
3504 return cpu_to_le32((u32)dma_addr);
3505}
3506
3507/**
bb8c093b 3508 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3509 *
9fbab516 3510 * If there are slots in the RX queue that need to be restocked,
b481de9c 3511 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3512 * as we can, pulling from rx_free.
b481de9c
ZY
3513 *
3514 * This moves the 'write' index forward to catch up with 'processed', and
3515 * also updates the memory address in the firmware to reference the new
3516 * target buffer.
3517 */
bb8c093b 3518static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3519{
bb8c093b 3520 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3521 struct list_head *element;
bb8c093b 3522 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY
3523 unsigned long flags;
3524 int write, rc;
3525
3526 spin_lock_irqsave(&rxq->lock, flags);
3527 write = rxq->write & ~0x7;
bb8c093b 3528 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3529 /* Get next free Rx buffer, remove from free list */
b481de9c 3530 element = rxq->rx_free.next;
bb8c093b 3531 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3532 list_del(element);
6440adb5
BC
3533
3534 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3535 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY
3536 rxq->queue[rxq->write] = rxb;
3537 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3538 rxq->free_count--;
3539 }
3540 spin_unlock_irqrestore(&rxq->lock, flags);
3541 /* If the pre-allocated buffer pool is dropping low, schedule to
3542 * refill it */
3543 if (rxq->free_count <= RX_LOW_WATERMARK)
3544 queue_work(priv->workqueue, &priv->rx_replenish);
3545
3546
6440adb5
BC
3547 /* If we've added more space for the firmware to place data, tell it.
3548 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
3549 if ((write != (rxq->write & ~0x7))
3550 || (abs(rxq->write - rxq->read) > 7)) {
3551 spin_lock_irqsave(&rxq->lock, flags);
3552 rxq->need_update = 1;
3553 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3554 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
3555 if (rc)
3556 return rc;
3557 }
3558
3559 return 0;
3560}
3561
3562/**
bb8c093b 3563 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
3564 *
3565 * When moving to rx_free an SKB is allocated for the slot.
3566 *
bb8c093b 3567 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3568 * This is called as a scheduled work item (except for during initialization)
b481de9c 3569 */
5c0eef96 3570static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3571{
bb8c093b 3572 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3573 struct list_head *element;
bb8c093b 3574 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY
3575 unsigned long flags;
3576 spin_lock_irqsave(&rxq->lock, flags);
3577 while (!list_empty(&rxq->rx_used)) {
3578 element = rxq->rx_used.next;
bb8c093b 3579 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
BC
3580
3581 /* Alloc a new receive buffer */
b481de9c
ZY
3582 rxb->skb =
3583 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3584 if (!rxb->skb) {
3585 if (net_ratelimit())
3586 printk(KERN_CRIT DRV_NAME
3587 ": Can not allocate SKB buffers\n");
3588 /* We don't reschedule replenish work here -- we will
3589 * call the restock method and if it still needs
3590 * more buffers it will schedule replenish */
3591 break;
3592 }
12342c47
ZY
3593
3594 /* If radiotap head is required, reserve some headroom here.
3595 * The physical head count is a variable rx_stats->phy_count.
3596 * We reserve 4 bytes here. Plus these extra bytes, the
3597 * headroom of the physical head should be enough for the
3598 * radiotap head that iwl3945 supported. See iwl3945_rt.
3599 */
3600 skb_reserve(rxb->skb, 4);
3601
b481de9c
ZY
3602 priv->alloc_rxb_skb++;
3603 list_del(element);
6440adb5
BC
3604
3605 /* Get physical address of RB/SKB */
b481de9c
ZY
3606 rxb->dma_addr =
3607 pci_map_single(priv->pci_dev, rxb->skb->data,
3608 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3609 list_add_tail(&rxb->list, &rxq->rx_free);
3610 rxq->free_count++;
3611 }
3612 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA
3613}
3614
3615/*
3616 * this should be called while priv->lock is locked
3617 */
4fd1f841 3618static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA
3619{
3620 struct iwl3945_priv *priv = data;
3621
3622 iwl3945_rx_allocate(priv);
3623 iwl3945_rx_queue_restock(priv);
3624}
3625
3626
3627void iwl3945_rx_replenish(void *data)
3628{
3629 struct iwl3945_priv *priv = data;
3630 unsigned long flags;
3631
3632 iwl3945_rx_allocate(priv);
b481de9c
ZY
3633
3634 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3635 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
3636 spin_unlock_irqrestore(&priv->lock, flags);
3637}
3638
3639/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3640 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY
3641 * This free routine walks the list of POOL entries and if SKB is set to
3642 * non NULL it is unmapped and freed
3643 */
bb8c093b 3644static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY
3645{
3646 int i;
3647 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3648 if (rxq->pool[i].skb != NULL) {
3649 pci_unmap_single(priv->pci_dev,
3650 rxq->pool[i].dma_addr,
3651 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3652 dev_kfree_skb(rxq->pool[i].skb);
3653 }
3654 }
3655
3656 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3657 rxq->dma_addr);
3658 rxq->bd = NULL;
3659}
3660
bb8c093b 3661int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3662{
bb8c093b 3663 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
3664 struct pci_dev *dev = priv->pci_dev;
3665 int i;
3666
3667 spin_lock_init(&rxq->lock);
3668 INIT_LIST_HEAD(&rxq->rx_free);
3669 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
BC
3670
3671 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY
3672 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3673 if (!rxq->bd)
3674 return -ENOMEM;
6440adb5 3675
b481de9c
ZY
3676 /* Fill the rx_used queue with _all_ of the Rx buffers */
3677 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3678 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3679
b481de9c
ZY
3680 /* Set us so that we have processed and used all buffers, but have
3681 * not restocked the Rx queue with fresh buffers */
3682 rxq->read = rxq->write = 0;
3683 rxq->free_count = 0;
3684 rxq->need_update = 0;
3685 return 0;
3686}
3687
bb8c093b 3688void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY
3689{
3690 unsigned long flags;
3691 int i;
3692 spin_lock_irqsave(&rxq->lock, flags);
3693 INIT_LIST_HEAD(&rxq->rx_free);
3694 INIT_LIST_HEAD(&rxq->rx_used);
3695 /* Fill the rx_used queue with _all_ of the Rx buffers */
3696 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3697 /* In the reset function, these buffers may have been allocated
3698 * to an SKB, so we need to unmap and free potential storage */
3699 if (rxq->pool[i].skb != NULL) {
3700 pci_unmap_single(priv->pci_dev,
3701 rxq->pool[i].dma_addr,
3702 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3703 priv->alloc_rxb_skb--;
3704 dev_kfree_skb(rxq->pool[i].skb);
3705 rxq->pool[i].skb = NULL;
3706 }
3707 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3708 }
3709
3710 /* Set us so that we have processed and used all buffers, but have
3711 * not restocked the Rx queue with fresh buffers */
3712 rxq->read = rxq->write = 0;
3713 rxq->free_count = 0;
3714 spin_unlock_irqrestore(&rxq->lock, flags);
3715}
3716
3717/* Convert linear signal-to-noise ratio into dB */
3718static u8 ratio2dB[100] = {
3719/* 0 1 2 3 4 5 6 7 8 9 */
3720 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3721 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3722 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3723 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3724 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3725 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3726 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3727 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3728 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3729 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3730};
3731
3732/* Calculates a relative dB value from a ratio of linear
3733 * (i.e. not dB) signal levels.
3734 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3735int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3736{
221c80cf
AB
3737 /* 1000:1 or higher just report as 60 dB */
3738 if (sig_ratio >= 1000)
b481de9c
ZY
3739 return 60;
3740
221c80cf 3741 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3742 * add 20 dB to make up for divide by 10 */
221c80cf 3743 if (sig_ratio >= 100)
3ac7f146 3744 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
3745
3746 /* We shouldn't see this */
3747 if (sig_ratio < 1)
3748 return 0;
3749
3750 /* Use table for ratios 1:1 - 99:1 */
3751 return (int)ratio2dB[sig_ratio];
3752}
3753
3754#define PERFECT_RSSI (-20) /* dBm */
3755#define WORST_RSSI (-95) /* dBm */
3756#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3757
3758/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3759 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3760 * about formulas used below. */
bb8c093b 3761int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
3762{
3763 int sig_qual;
3764 int degradation = PERFECT_RSSI - rssi_dbm;
3765
3766 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3767 * as indicator; formula is (signal dbm - noise dbm).
3768 * SNR at or above 40 is a great signal (100%).
3769 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3770 * Weakest usable signal is usually 10 - 15 dB SNR. */
3771 if (noise_dbm) {
3772 if (rssi_dbm - noise_dbm >= 40)
3773 return 100;
3774 else if (rssi_dbm < noise_dbm)
3775 return 0;
3776 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3777
3778 /* Else use just the signal level.
3779 * This formula is a least squares fit of data points collected and
3780 * compared with a reference system that had a percentage (%) display
3781 * for signal quality. */
3782 } else
3783 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3784 (15 * RSSI_RANGE + 62 * degradation)) /
3785 (RSSI_RANGE * RSSI_RANGE);
3786
3787 if (sig_qual > 100)
3788 sig_qual = 100;
3789 else if (sig_qual < 1)
3790 sig_qual = 0;
3791
3792 return sig_qual;
3793}
3794
3795/**
9fbab516 3796 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
3797 *
3798 * Uses the priv->rx_handlers callback function array to invoke
3799 * the appropriate handlers, including command responses,
3800 * frame-received notifications, and other notifications.
3801 */
bb8c093b 3802static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3803{
bb8c093b 3804 struct iwl3945_rx_mem_buffer *rxb;
3d24a9f7 3805 struct iwl_rx_packet *pkt;
bb8c093b 3806 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
3807 u32 r, i;
3808 int reclaim;
3809 unsigned long flags;
5c0eef96 3810 u8 fill_rx = 0;
d68ab680 3811 u32 count = 8;
b481de9c 3812
6440adb5
BC
3813 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3814 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3815 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY
3816 i = rxq->read;
3817
5c0eef96
MA
3818 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3819 fill_rx = 1;
b481de9c
ZY
3820 /* Rx interrupt, but nothing sent from uCode */
3821 if (i == r)
3822 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3823
3824 while (i != r) {
3825 rxb = rxq->queue[i];
3826
9fbab516 3827 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
3828 * then a bug has been introduced in the queue refilling
3829 * routines -- catch it here */
3830 BUG_ON(rxb == NULL);
3831
3832 rxq->queue[i] = NULL;
3833
3834 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3835 IWL_RX_BUF_SIZE,
3836 PCI_DMA_FROMDEVICE);
3d24a9f7 3837 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
3838
3839 /* Reclaim a command buffer only if this packet is a response
3840 * to a (driver-originated) command.
3841 * If the packet (e.g. Rx frame) originated from uCode,
3842 * there is no command buffer to reclaim.
3843 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3844 * but apparently a few don't get set; catch them here. */
3845 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3846 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3847 (pkt->hdr.cmd != REPLY_TX);
3848
3849 /* Based on type of command response or notification,
3850 * handle those that need handling via function in
bb8c093b 3851 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY
3852 if (priv->rx_handlers[pkt->hdr.cmd]) {
3853 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3854 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3855 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3856 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3857 } else {
3858 /* No handling needed */
3859 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3860 "r %d i %d No handler needed for %s, 0x%02x\n",
3861 r, i, get_cmd_string(pkt->hdr.cmd),
3862 pkt->hdr.cmd);
3863 }
3864
3865 if (reclaim) {
9fbab516
BC
3866 /* Invoke any callbacks, transfer the skb to caller, and
3867 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY
3868 * as we reclaim the driver command queue */
3869 if (rxb && rxb->skb)
bb8c093b 3870 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY
3871 else
3872 IWL_WARNING("Claim null rxb?\n");
3873 }
3874
3875 /* For now we just don't re-use anything. We can tweak this
3876 * later to try and re-use notification packets and SKBs that
3877 * fail to Rx correctly */
3878 if (rxb->skb != NULL) {
3879 priv->alloc_rxb_skb--;
3880 dev_kfree_skb_any(rxb->skb);
3881 rxb->skb = NULL;
3882 }
3883
3884 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3885 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3886 spin_lock_irqsave(&rxq->lock, flags);
3887 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3888 spin_unlock_irqrestore(&rxq->lock, flags);
3889 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
3890 /* If there are a lot of unused frames,
3891 * restock the Rx queue so ucode won't assert. */
3892 if (fill_rx) {
3893 count++;
3894 if (count >= 8) {
3895 priv->rxq.read = i;
3896 __iwl3945_rx_replenish(priv);
3897 count = 0;
3898 }
3899 }
b481de9c
ZY
3900 }
3901
3902 /* Backtrack one entry */
3903 priv->rxq.read = i;
bb8c093b 3904 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
3905}
3906
6440adb5
BC
3907/**
3908 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3909 */
bb8c093b
CH
3910static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3911 struct iwl3945_tx_queue *txq)
b481de9c
ZY
3912{
3913 u32 reg = 0;
3914 int rc = 0;
3915 int txq_id = txq->q.id;
3916
3917 if (txq->need_update == 0)
3918 return rc;
3919
3920 /* if we're trying to save power */
3921 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3922 /* wake up nic if it's powered down ...
3923 * uCode will wake up, and interrupt us again, so next
3924 * time we'll skip this part. */
bb8c093b 3925 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3926
3927 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3928 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 3929 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3930 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3931 return rc;
3932 }
3933
3934 /* restore this queue's parameters in nic hardware. */
bb8c093b 3935 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
3936 if (rc)
3937 return rc;
bb8c093b 3938 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3939 txq->q.write_ptr | (txq_id << 8));
bb8c093b 3940 iwl3945_release_nic_access(priv);
b481de9c
ZY
3941
3942 /* else not in power-save mode, uCode will never sleep when we're
3943 * trying to tx (during RFKILL, we're not trying to tx). */
3944 } else
bb8c093b 3945 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3946 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY
3947
3948 txq->need_update = 0;
3949
3950 return rc;
3951}
3952
c8b0e6e1 3953#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 3954static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY
3955{
3956 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 3957 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY
3958 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3959 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3960 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3961 le32_to_cpu(rxon->filter_flags));
3962 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3963 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3964 rxon->ofdm_basic_rates);
3965 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB
3966 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3967 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY
3968 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3969}
3970#endif
3971
bb8c093b 3972static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY
3973{
3974 IWL_DEBUG_ISR("Enabling interrupts\n");
3975 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 3976 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY
3977}
3978
0359facc
MA
3979
3980/* call this function to flush any scheduled tasklet */
3981static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
3982{
a96a27f9 3983 /* wait to make sure we flush pending tasklet*/
0359facc
MA
3984 synchronize_irq(priv->pci_dev->irq);
3985 tasklet_kill(&priv->irq_tasklet);
3986}
3987
3988
bb8c093b 3989static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY
3990{
3991 clear_bit(STATUS_INT_ENABLED, &priv->status);
3992
3993 /* disable interrupts from uCode/NIC to host */
bb8c093b 3994 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
3995
3996 /* acknowledge/clear/reset any interrupts still pending
3997 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH
3998 iwl3945_write32(priv, CSR_INT, 0xffffffff);
3999 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY
4000 IWL_DEBUG_ISR("Disabled interrupts\n");
4001}
4002
4003static const char *desc_lookup(int i)
4004{
4005 switch (i) {
4006 case 1:
4007 return "FAIL";
4008 case 2:
4009 return "BAD_PARAM";
4010 case 3:
4011 return "BAD_CHECKSUM";
4012 case 4:
4013 return "NMI_INTERRUPT";
4014 case 5:
4015 return "SYSASSERT";
4016 case 6:
4017 return "FATAL_ERROR";
4018 }
4019
4020 return "UNKNOWN";
4021}
4022
4023#define ERROR_START_OFFSET (1 * sizeof(u32))
4024#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4025
bb8c093b 4026static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY
4027{
4028 u32 i;
4029 u32 desc, time, count, base, data1;
4030 u32 blink1, blink2, ilink1, ilink2;
4031 int rc;
4032
4033 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4034
bb8c093b 4035 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4036 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4037 return;
4038 }
4039
bb8c093b 4040 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4041 if (rc) {
4042 IWL_WARNING("Can not read from adapter at this time.\n");
4043 return;
4044 }
4045
bb8c093b 4046 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY
4047
4048 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4049 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4050 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY
4051 }
4052
4053 IWL_ERROR("Desc Time asrtPC blink2 "
4054 "ilink1 nmiPC Line\n");
4055 for (i = ERROR_START_OFFSET;
4056 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4057 i += ERROR_ELEM_SIZE) {
bb8c093b 4058 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4059 time =
bb8c093b 4060 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4061 blink1 =
bb8c093b 4062 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4063 blink2 =
bb8c093b 4064 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4065 ilink1 =
bb8c093b 4066 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4067 ilink2 =
bb8c093b 4068 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4069 data1 =
bb8c093b 4070 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY
4071
4072 IWL_ERROR
4073 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4074 desc_lookup(desc), desc, time, blink1, blink2,
4075 ilink1, ilink2, data1);
4076 }
4077
bb8c093b 4078 iwl3945_release_nic_access(priv);
b481de9c
ZY
4079
4080}
4081
f58177b9 4082#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
4083
4084/**
bb8c093b 4085 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4086 *
bb8c093b 4087 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4088 */
bb8c093b 4089static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY
4090 u32 num_events, u32 mode)
4091{
4092 u32 i;
4093 u32 base; /* SRAM byte address of event log header */
4094 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4095 u32 ptr; /* SRAM byte address of log data */
4096 u32 ev, time, data; /* event log data */
4097
4098 if (num_events == 0)
4099 return;
4100
4101 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4102
4103 if (mode == 0)
4104 event_size = 2 * sizeof(u32);
4105 else
4106 event_size = 3 * sizeof(u32);
4107
4108 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4109
4110 /* "time" is actually "data" for mode 0 (no timestamp).
4111 * place event id # at far right for easier visual parsing. */
4112 for (i = 0; i < num_events; i++) {
bb8c093b 4113 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4114 ptr += sizeof(u32);
bb8c093b 4115 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY
4116 ptr += sizeof(u32);
4117 if (mode == 0)
4118 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4119 else {
bb8c093b 4120 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY
4121 ptr += sizeof(u32);
4122 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4123 }
4124 }
4125}
4126
bb8c093b 4127static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY
4128{
4129 int rc;
4130 u32 base; /* SRAM byte address of event log header */
4131 u32 capacity; /* event log capacity in # entries */
4132 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4133 u32 num_wraps; /* # times uCode wrapped to top of log */
4134 u32 next_entry; /* index of next entry to be written by uCode */
4135 u32 size; /* # entries that we'll print */
4136
4137 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4138 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY
4139 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4140 return;
4141 }
4142
bb8c093b 4143 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
4144 if (rc) {
4145 IWL_WARNING("Can not read from adapter at this time.\n");
4146 return;
4147 }
4148
4149 /* event log header */
bb8c093b
CH
4150 capacity = iwl3945_read_targ_mem(priv, base);
4151 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4152 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4153 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
4154
4155 size = num_wraps ? capacity : next_entry;
4156
4157 /* bail out if nothing in log */
4158 if (size == 0) {
583fab37 4159 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4160 iwl3945_release_nic_access(priv);
b481de9c
ZY
4161 return;
4162 }
4163
583fab37 4164 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
4165 size, num_wraps);
4166
4167 /* if uCode has wrapped back to top of log, start at the oldest entry,
4168 * i.e the next one that uCode would fill. */
4169 if (num_wraps)
bb8c093b 4170 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
4171 capacity - next_entry, mode);
4172
4173 /* (then/else) start at top of log */
bb8c093b 4174 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4175
bb8c093b 4176 iwl3945_release_nic_access(priv);
b481de9c
ZY
4177}
4178
4179/**
bb8c093b 4180 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4181 */
bb8c093b 4182static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4183{
bb8c093b 4184 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY
4185 set_bit(STATUS_FW_ERROR, &priv->status);
4186
4187 /* Cancel currently queued command. */
4188 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4189
c8b0e6e1 4190#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
4191 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4192 iwl3945_dump_nic_error_log(priv);
4193 iwl3945_dump_nic_event_log(priv);
4194 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY
4195 }
4196#endif
4197
4198 wake_up_interruptible(&priv->wait_command_queue);
4199
4200 /* Keep the restart process from trying to send host
4201 * commands by clearing the INIT status bit */
4202 clear_bit(STATUS_READY, &priv->status);
4203
4204 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4205 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4206 "Restarting adapter due to uCode error.\n");
4207
bb8c093b 4208 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
4209 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4210 sizeof(priv->recovery_rxon));
4211 priv->error_recovering = 1;
4212 }
4213 queue_work(priv->workqueue, &priv->restart);
4214 }
4215}
4216
bb8c093b 4217static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY
4218{
4219 unsigned long flags;
4220
4221 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4222 sizeof(priv->staging_rxon));
4223 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4224 iwl3945_commit_rxon(priv);
b481de9c 4225
bb8c093b 4226 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY
4227
4228 spin_lock_irqsave(&priv->lock, flags);
4229 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4230 priv->error_recovering = 0;
4231 spin_unlock_irqrestore(&priv->lock, flags);
4232}
4233
bb8c093b 4234static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY
4235{
4236 u32 inta, handled = 0;
4237 u32 inta_fh;
4238 unsigned long flags;
c8b0e6e1 4239#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
4240 u32 inta_mask;
4241#endif
4242
4243 spin_lock_irqsave(&priv->lock, flags);
4244
4245 /* Ack/clear/reset pending uCode interrupts.
4246 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4247 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH
4248 inta = iwl3945_read32(priv, CSR_INT);
4249 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY
4250
4251 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4252 * Any new interrupts that happen after this, either while we're
4253 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH
4254 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4255 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4256
c8b0e6e1 4257#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4258 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC
4259 /* just for debug */
4260 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY
4261 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4262 inta, inta_mask, inta_fh);
4263 }
4264#endif
4265
4266 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4267 * atomic, make sure that inta covers all the interrupts that
4268 * we've discovered, even if FH interrupt came in just after
4269 * reading CSR_INT. */
6f83eaa1 4270 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4271 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4272 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
4273 inta |= CSR_INT_BIT_FH_TX;
4274
4275 /* Now service all interrupt bits discovered above. */
4276 if (inta & CSR_INT_BIT_HW_ERR) {
4277 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4278
4279 /* Tell the device to stop sending interrupts */
bb8c093b 4280 iwl3945_disable_interrupts(priv);
b481de9c 4281
bb8c093b 4282 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4283
4284 handled |= CSR_INT_BIT_HW_ERR;
4285
4286 spin_unlock_irqrestore(&priv->lock, flags);
4287
4288 return;
4289 }
4290
c8b0e6e1 4291#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4292 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4293 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP
4294 if (inta & CSR_INT_BIT_SCD)
4295 IWL_DEBUG_ISR("Scheduler finished to transmit "
4296 "the frame/frames.\n");
b481de9c
ZY
4297
4298 /* Alive notification via Rx interrupt will do the real work */
4299 if (inta & CSR_INT_BIT_ALIVE)
4300 IWL_DEBUG_ISR("Alive interrupt\n");
4301 }
4302#endif
4303 /* Safely ignore these bits for debug checks below */
25c03d8e 4304 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 4305
b481de9c
ZY
4306 /* Error detected by uCode */
4307 if (inta & CSR_INT_BIT_SW_ERR) {
4308 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4309 inta);
bb8c093b 4310 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4311 handled |= CSR_INT_BIT_SW_ERR;
4312 }
4313
4314 /* uCode wakes up after power-down sleep */
4315 if (inta & CSR_INT_BIT_WAKEUP) {
4316 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH
4317 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4318 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4319 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4320 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4321 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4322 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4323 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
4324
4325 handled |= CSR_INT_BIT_WAKEUP;
4326 }
4327
4328 /* All uCode command responses, including Tx command responses,
4329 * Rx "responses" (frame-received notification), and other
4330 * notifications from uCode come through here*/
4331 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4332 iwl3945_rx_handle(priv);
b481de9c
ZY
4333 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4334 }
4335
4336 if (inta & CSR_INT_BIT_FH_TX) {
4337 IWL_DEBUG_ISR("Tx interrupt\n");
4338
bb8c093b
CH
4339 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4340 if (!iwl3945_grab_nic_access(priv)) {
bddadf86
TW
4341 iwl3945_write_direct32(priv, FH39_TCSR_CREDIT
4342 (FH39_SRVC_CHNL), 0x0);
bb8c093b 4343 iwl3945_release_nic_access(priv);
b481de9c
ZY
4344 }
4345 handled |= CSR_INT_BIT_FH_TX;
4346 }
4347
4348 if (inta & ~handled)
4349 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4350
4351 if (inta & ~CSR_INI_SET_MASK) {
4352 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4353 inta & ~CSR_INI_SET_MASK);
4354 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4355 }
4356
4357 /* Re-enable all interrupts */
0359facc
MA
4358 /* only Re-enable if disabled by irq */
4359 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4360 iwl3945_enable_interrupts(priv);
b481de9c 4361
c8b0e6e1 4362#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH
4363 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4364 inta = iwl3945_read32(priv, CSR_INT);
4365 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4366 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4367 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4368 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4369 }
4370#endif
4371 spin_unlock_irqrestore(&priv->lock, flags);
4372}
4373
bb8c093b 4374static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4375{
bb8c093b 4376 struct iwl3945_priv *priv = data;
b481de9c
ZY
4377 u32 inta, inta_mask;
4378 u32 inta_fh;
4379 if (!priv)
4380 return IRQ_NONE;
4381
4382 spin_lock(&priv->lock);
4383
4384 /* Disable (but don't clear!) interrupts here to avoid
4385 * back-to-back ISRs and sporadic interrupts from our NIC.
4386 * If we have something to service, the tasklet will re-enable ints.
4387 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH
4388 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4389 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4390
4391 /* Discover which interrupts are active/pending */
bb8c093b
CH
4392 inta = iwl3945_read32(priv, CSR_INT);
4393 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4394
4395 /* Ignore interrupt if there's nothing in NIC to service.
4396 * This may be due to IRQ shared with another device,
4397 * or due to sporadic interrupts thrown from our NIC. */
4398 if (!inta && !inta_fh) {
4399 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4400 goto none;
4401 }
4402
4403 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4404 /* Hardware disappeared */
99df630c 4405 IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
cb4da1a3 4406 goto unplugged;
b481de9c
ZY
4407 }
4408
4409 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4410 inta, inta_mask, inta_fh);
4411
25c03d8e
JP
4412 inta &= ~CSR_INT_BIT_SCD;
4413
bb8c093b 4414 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP
4415 if (likely(inta || inta_fh))
4416 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4417unplugged:
b481de9c
ZY
4418 spin_unlock(&priv->lock);
4419
4420 return IRQ_HANDLED;
4421
4422 none:
4423 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA
4424 /* only Re-enable if disabled by irq */
4425 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4426 iwl3945_enable_interrupts(priv);
b481de9c
ZY
4427 spin_unlock(&priv->lock);
4428 return IRQ_NONE;
4429}
4430
4431/************************** EEPROM BANDS ****************************
4432 *
bb8c093b 4433 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY
4434 * EEPROM contents to the specific channel number supported for each
4435 * band.
4436 *
bb8c093b 4437 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY
4438 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4439 * The specific geography and calibration information for that channel
4440 * is contained in the eeprom map itself.
4441 *
4442 * During init, we copy the eeprom information and channel map
4443 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4444 *
4445 * channel_map_24/52 provides the index in the channel_info array for a
4446 * given channel. We have to have two separate maps as there is channel
4447 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4448 * band_2
4449 *
4450 * A value of 0xff stored in the channel_map indicates that the channel
4451 * is not supported by the hardware at all.
4452 *
4453 * A value of 0xfe in the channel_map indicates that the channel is not
4454 * valid for Tx with the current hardware. This means that
4455 * while the system can tune and receive on a given channel, it may not
4456 * be able to associate or transmit any frames on that
4457 * channel. There is no corresponding channel information for that
4458 * entry.
4459 *
4460 *********************************************************************/
4461
4462/* 2.4 GHz */
bb8c093b 4463static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY
4464 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4465};
4466
4467/* 5.2 GHz bands */
9fbab516 4468static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY
4469 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4470};
4471
9fbab516 4472static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY
4473 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4474};
4475
bb8c093b 4476static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY
4477 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4478};
4479
bb8c093b 4480static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY
4481 145, 149, 153, 157, 161, 165
4482};
4483
bb8c093b 4484static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4485 int *eeprom_ch_count,
bb8c093b 4486 const struct iwl3945_eeprom_channel
b481de9c
ZY
4487 **eeprom_ch_info,
4488 const u8 **eeprom_ch_index)
4489{
4490 switch (band) {
4491 case 1: /* 2.4GHz band */
bb8c093b 4492 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4493 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4494 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4495 break;
9fbab516 4496 case 2: /* 4.9GHz band */
bb8c093b 4497 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4498 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4499 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY
4500 break;
4501 case 3: /* 5.2GHz band */
bb8c093b 4502 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4503 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4504 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4505 break;
9fbab516 4506 case 4: /* 5.5GHz band */
bb8c093b 4507 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4508 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4509 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4510 break;
9fbab516 4511 case 5: /* 5.7GHz band */
bb8c093b 4512 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4513 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4514 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY
4515 break;
4516 default:
4517 BUG();
4518 return;
4519 }
4520}
4521
6440adb5
BC
4522/**
4523 * iwl3945_get_channel_info - Find driver's private channel info
4524 *
4525 * Based on band and channel number.
4526 */
bb8c093b 4527const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4528 enum ieee80211_band band, u16 channel)
b481de9c
ZY
4529{
4530 int i;
4531
8318d78a
JB
4532 switch (band) {
4533 case IEEE80211_BAND_5GHZ:
b481de9c
ZY
4534 for (i = 14; i < priv->channel_count; i++) {
4535 if (priv->channel_info[i].channel == channel)
4536 return &priv->channel_info[i];
4537 }
4538 break;
4539
8318d78a 4540 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
4541 if (channel >= 1 && channel <= 14)
4542 return &priv->channel_info[channel - 1];
4543 break;
8318d78a
JB
4544 case IEEE80211_NUM_BANDS:
4545 WARN_ON(1);
b481de9c
ZY
4546 }
4547
4548 return NULL;
4549}
4550
4551#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4552 ? # x " " : "")
4553
6440adb5
BC
4554/**
4555 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4556 */
bb8c093b 4557static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY
4558{
4559 int eeprom_ch_count = 0;
4560 const u8 *eeprom_ch_index = NULL;
bb8c093b 4561 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4562 int band, ch;
bb8c093b 4563 struct iwl3945_channel_info *ch_info;
b481de9c
ZY
4564
4565 if (priv->channel_count) {
4566 IWL_DEBUG_INFO("Channel map already initialized.\n");
4567 return 0;
4568 }
4569
4570 if (priv->eeprom.version < 0x2f) {
4571 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4572 priv->eeprom.version);
4573 return -EINVAL;
4574 }
4575
4576 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4577
4578 priv->channel_count =
bb8c093b
CH
4579 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4580 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4581 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4582 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4583 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY
4584
4585 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4586
bb8c093b 4587 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY
4588 priv->channel_count, GFP_KERNEL);
4589 if (!priv->channel_info) {
4590 IWL_ERROR("Could not allocate channel_info\n");
4591 priv->channel_count = 0;
4592 return -ENOMEM;
4593 }
4594
4595 ch_info = priv->channel_info;
4596
4597 /* Loop through the 5 EEPROM bands adding them in order to the
4598 * channel map we maintain (that contains additional information than
4599 * what just in the EEPROM) */
4600 for (band = 1; band <= 5; band++) {
4601
bb8c093b 4602 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
4603 &eeprom_ch_info, &eeprom_ch_index);
4604
4605 /* Loop through each band adding each of the channels */
4606 for (ch = 0; ch < eeprom_ch_count; ch++) {
4607 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB
4608 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4609 IEEE80211_BAND_5GHZ;
b481de9c
ZY
4610
4611 /* permanently store EEPROM's channel regulatory flags
4612 * and max power in channel info database. */
4613 ch_info->eeprom = eeprom_ch_info[ch];
4614
4615 /* Copy the run-time flags so they are there even on
4616 * invalid channels */
4617 ch_info->flags = eeprom_ch_info[ch].flags;
4618
4619 if (!(is_channel_valid(ch_info))) {
4620 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4621 "No traffic\n",
4622 ch_info->channel,
4623 ch_info->flags,
4624 is_channel_a_band(ch_info) ?
4625 "5.2" : "2.4");
4626 ch_info++;
4627 continue;
4628 }
4629
4630 /* Initialize regulatory-based run-time data */
4631 ch_info->max_power_avg = ch_info->curr_txpow =
4632 eeprom_ch_info[ch].max_power_avg;
4633 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4634 ch_info->min_power = 0;
4635
fe7c4040 4636 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY
4637 " %ddBm): Ad-Hoc %ssupported\n",
4638 ch_info->channel,
4639 is_channel_a_band(ch_info) ?
4640 "5.2" : "2.4",
8211ef78 4641 CHECK_AND_PRINT(VALID),
b481de9c
ZY
4642 CHECK_AND_PRINT(IBSS),
4643 CHECK_AND_PRINT(ACTIVE),
4644 CHECK_AND_PRINT(RADAR),
4645 CHECK_AND_PRINT(WIDE),
b481de9c
ZY
4646 CHECK_AND_PRINT(DFS),
4647 eeprom_ch_info[ch].flags,
4648 eeprom_ch_info[ch].max_power_avg,
4649 ((eeprom_ch_info[ch].
4650 flags & EEPROM_CHANNEL_IBSS)
4651 && !(eeprom_ch_info[ch].
4652 flags & EEPROM_CHANNEL_RADAR))
4653 ? "" : "not ");
4654
4655 /* Set the user_txpower_limit to the highest power
4656 * supported by any channel */
4657 if (eeprom_ch_info[ch].max_power_avg >
4658 priv->user_txpower_limit)
4659 priv->user_txpower_limit =
4660 eeprom_ch_info[ch].max_power_avg;
4661
4662 ch_info++;
4663 }
4664 }
4665
6440adb5 4666 /* Set up txpower settings in driver for all channels */
b481de9c
ZY
4667 if (iwl3945_txpower_set_from_eeprom(priv))
4668 return -EIO;
4669
4670 return 0;
4671}
4672
849e0dce
RC
4673/*
4674 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4675 */
4676static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4677{
4678 kfree(priv->channel_info);
4679 priv->channel_count = 0;
4680}
4681
b481de9c
ZY
4682/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4683 * sending probe req. This should be set long enough to hear probe responses
4684 * from more than one AP. */
f9340520
AK
4685#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4686#define IWL_ACTIVE_DWELL_TIME_52 (20)
4687
4688#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4689#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY
4690
4691/* For faster active scanning, scan will move to the next channel if fewer than
4692 * PLCP_QUIET_THRESH packets are heard on this channel within
4693 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4694 * time if it's a quiet channel (nothing responded to our probe, and there's
4695 * no other traffic).
4696 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4697#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4698#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY
4699
4700/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4701 * Must be set longer than active dwell time.
4702 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4703#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4704#define IWL_PASSIVE_DWELL_TIME_52 (10)
4705#define IWL_PASSIVE_DWELL_BASE (100)
4706#define IWL_CHANNEL_TUNE_TIME 5
4707
e720ce9d 4708#define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
f9340520 4709
8318d78a 4710static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
f9340520
AK
4711 enum ieee80211_band band,
4712 u8 n_probes)
b481de9c 4713{
8318d78a 4714 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK
4715 return IWL_ACTIVE_DWELL_TIME_52 +
4716 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4717 else
f9340520
AK
4718 return IWL_ACTIVE_DWELL_TIME_24 +
4719 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY
4720}
4721
8318d78a
JB
4722static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4723 enum ieee80211_band band)
b481de9c 4724{
8318d78a 4725 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY
4726 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4727 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4728
bb8c093b 4729 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
4730 /* If we're associated, we clamp the maximum passive
4731 * dwell time to be 98% of the beacon interval (minus
4732 * 2 * channel tune time) */
4733 passive = priv->beacon_int;
4734 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4735 passive = IWL_PASSIVE_DWELL_BASE;
4736 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4737 }
4738
b481de9c
ZY
4739 return passive;
4740}
4741
8318d78a
JB
4742static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4743 enum ieee80211_band band,
f9340520 4744 u8 is_active, u8 n_probes,
bb8c093b 4745 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
4746{
4747 const struct ieee80211_channel *channels = NULL;
8318d78a 4748 const struct ieee80211_supported_band *sband;
bb8c093b 4749 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY
4750 u16 passive_dwell = 0;
4751 u16 active_dwell = 0;
4752 int added, i;
4753
8318d78a
JB
4754 sband = iwl3945_get_band(priv, band);
4755 if (!sband)
b481de9c
ZY
4756 return 0;
4757
8318d78a 4758 channels = sband->channels;
b481de9c 4759
f9340520 4760 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4761 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4762
8f4807a1
AK
4763 if (passive_dwell <= active_dwell)
4764 passive_dwell = active_dwell + 1;
4765
8318d78a 4766 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB
4767 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4768 continue;
4769
8318d78a 4770 scan_ch->channel = channels[i].hw_value;
b481de9c 4771
8318d78a 4772 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4773 if (!is_channel_valid(ch_info)) {
66b5004d 4774 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY
4775 scan_ch->channel);
4776 continue;
4777 }
4778
011a0330
AK
4779 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4780 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4781 /* If passive , set up for auto-switch
4782 * and use long active_dwell time.
4783 */
b481de9c 4784 if (!is_active || is_channel_passive(ch_info) ||
011a0330 4785 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 4786 scan_ch->type = 0; /* passive */
011a0330
AK
4787 if (IWL_UCODE_API(priv->ucode_ver) == 1)
4788 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
4789 } else {
b481de9c 4790 scan_ch->type = 1; /* active */
011a0330 4791 }
b481de9c 4792
011a0330
AK
4793 /* Set direct probe bits. These may be used both for active
4794 * scan channels (probes gets sent right away),
4795 * or for passive channels (probes get se sent only after
4796 * hearing clear Rx packet).*/
4797 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
4798 if (n_probes)
4799 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4800 } else {
4801 /* uCode v1 does not allow setting direct probe bits on
4802 * passive channel. */
4803 if ((scan_ch->type & 1) && n_probes)
4804 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4805 }
b481de9c 4806
9fbab516 4807 /* Set txpower levels to defaults */
b481de9c
ZY
4808 scan_ch->tpc.dsp_atten = 110;
4809 /* scan_pwr_info->tpc.dsp_atten; */
4810
4811 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4812 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
4813 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4814 else {
4815 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4816 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4817 * power level:
8a1b0245 4818 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
4819 */
4820 }
4821
4822 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4823 scan_ch->channel,
4824 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4825 (scan_ch->type & 1) ?
4826 active_dwell : passive_dwell);
4827
4828 scan_ch++;
4829 added++;
4830 }
4831
4832 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4833 return added;
4834}
4835
bb8c093b 4836static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY
4837 struct ieee80211_rate *rates)
4838{
4839 int i;
4840
4841 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
4842 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4843 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4844 rates[i].hw_value_short = i;
4845 rates[i].flags = 0;
4846 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4847 /*
8318d78a 4848 * If CCK != 1M then set short preamble rate flag.
b481de9c 4849 */
bb8c093b 4850 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4851 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4852 }
b481de9c
ZY
4853 }
4854}
4855
4856/**
bb8c093b 4857 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4858 */
bb8c093b 4859static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 4860{
bb8c093b 4861 struct iwl3945_channel_info *ch;
8211ef78 4862 struct ieee80211_supported_band *sband;
b481de9c
ZY
4863 struct ieee80211_channel *channels;
4864 struct ieee80211_channel *geo_ch;
4865 struct ieee80211_rate *rates;
4866 int i = 0;
b481de9c 4867
8318d78a
JB
4868 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4869 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY
4870 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4871 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4872 return 0;
4873 }
4874
b481de9c
ZY
4875 channels = kzalloc(sizeof(struct ieee80211_channel) *
4876 priv->channel_count, GFP_KERNEL);
8318d78a 4877 if (!channels)
b481de9c 4878 return -ENOMEM;
b481de9c 4879
8211ef78 4880 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY
4881 GFP_KERNEL);
4882 if (!rates) {
b481de9c
ZY
4883 kfree(channels);
4884 return -ENOMEM;
4885 }
4886
b481de9c 4887 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW
4888 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4889 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4890 /* just OFDM */
4891 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4892 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4893
4894 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4895 sband->channels = channels;
4896 /* OFDM & CCK */
4897 sband->bitrates = rates;
4898 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY
4899
4900 priv->ieee_channels = channels;
4901 priv->ieee_rates = rates;
4902
bb8c093b 4903 iwl3945_init_hw_rates(priv, rates);
b481de9c 4904
8211ef78 4905 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY
4906 ch = &priv->channel_info[i];
4907
8211ef78
TW
4908 /* FIXME: might be removed if scan is OK*/
4909 if (!is_channel_valid(ch))
b481de9c 4910 continue;
b481de9c
ZY
4911
4912 if (is_channel_a_band(ch))
8211ef78 4913 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4914 else
8211ef78 4915 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4916
8211ef78
TW
4917 geo_ch = &sband->channels[sband->n_channels++];
4918
4919 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB
4920 geo_ch->max_power = ch->max_power_avg;
4921 geo_ch->max_antenna_gain = 0xff;
7b72304d 4922 geo_ch->hw_value = ch->channel;
b481de9c
ZY
4923
4924 if (is_channel_valid(ch)) {
8318d78a
JB
4925 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4926 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4927
8318d78a
JB
4928 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4929 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY
4930
4931 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4932 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY
4933
4934 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4935 priv->max_channel_txpower_limit =
4936 ch->max_power_avg;
8211ef78 4937 } else {
8318d78a 4938 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW
4939 }
4940
4941 /* Save flags for reg domain usage */
4942 geo_ch->orig_flags = geo_ch->flags;
4943
4944 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4945 ch->channel, geo_ch->center_freq,
4946 is_channel_a_band(ch) ? "5.2" : "2.4",
4947 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4948 "restricted" : "valid",
4949 geo_ch->flags);
b481de9c
ZY
4950 }
4951
82b9a121
TW
4952 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4953 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY
4954 printk(KERN_INFO DRV_NAME
4955 ": Incorrectly detected BG card as ABG. Please send "
4956 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
4957 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4958 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY
4959 }
4960
4961 printk(KERN_INFO DRV_NAME
4962 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB
4963 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4964 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 4965
e0e0a67e
JL
4966 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4967 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4968 &priv->bands[IEEE80211_BAND_2GHZ];
4969 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4970 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4971 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 4972
b481de9c
ZY
4973 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4974
4975 return 0;
4976}
4977
849e0dce
RC
4978/*
4979 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
4980 */
4981static void iwl3945_free_geos(struct iwl3945_priv *priv)
4982{
849e0dce
RC
4983 kfree(priv->ieee_channels);
4984 kfree(priv->ieee_rates);
4985 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4986}
4987
b481de9c
ZY
4988/******************************************************************************
4989 *
4990 * uCode download functions
4991 *
4992 ******************************************************************************/
4993
bb8c093b 4994static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 4995{
98c92211
TW
4996 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
4997 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
4998 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
4999 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5000 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5001 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
5002}
5003
5004/**
bb8c093b 5005 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
5006 * looking at all data.
5007 */
3ac7f146 5008static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
5009{
5010 u32 val;
5011 u32 save_len = len;
5012 int rc = 0;
5013 u32 errcnt;
5014
5015 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5016
bb8c093b 5017 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5018 if (rc)
5019 return rc;
5020
bb8c093b 5021 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY
5022
5023 errcnt = 0;
5024 for (; len > 0; len -= sizeof(u32), image++) {
5025 /* read data comes through single port, auto-incr addr */
5026 /* NOTE: Use the debugless read so we don't flood kernel log
5027 * if IWL_DL_IO is set */
bb8c093b 5028 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5029 if (val != le32_to_cpu(*image)) {
5030 IWL_ERROR("uCode INST section is invalid at "
5031 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5032 save_len - len, val, le32_to_cpu(*image));
5033 rc = -EIO;
5034 errcnt++;
5035 if (errcnt >= 20)
5036 break;
5037 }
5038 }
5039
bb8c093b 5040 iwl3945_release_nic_access(priv);
b481de9c
ZY
5041
5042 if (!errcnt)
bc434dd2 5043 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
5044
5045 return rc;
5046}
5047
5048
5049/**
bb8c093b 5050 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
5051 * using sample data 100 bytes apart. If these sample points are good,
5052 * it's a pretty good bet that everything between them is good, too.
5053 */
bb8c093b 5054static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
5055{
5056 u32 val;
5057 int rc = 0;
5058 u32 errcnt = 0;
5059 u32 i;
5060
5061 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5062
bb8c093b 5063 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5064 if (rc)
5065 return rc;
5066
5067 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5068 /* read data comes through single port, auto-incr addr */
5069 /* NOTE: Use the debugless read so we don't flood kernel log
5070 * if IWL_DL_IO is set */
bb8c093b 5071 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5072 i + RTC_INST_LOWER_BOUND);
bb8c093b 5073 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
5074 if (val != le32_to_cpu(*image)) {
5075#if 0 /* Enable this if you want to see details */
5076 IWL_ERROR("uCode INST section is invalid at "
5077 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5078 i, val, *image);
5079#endif
5080 rc = -EIO;
5081 errcnt++;
5082 if (errcnt >= 3)
5083 break;
5084 }
5085 }
5086
bb8c093b 5087 iwl3945_release_nic_access(priv);
b481de9c
ZY
5088
5089 return rc;
5090}
5091
5092
5093/**
bb8c093b 5094 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
5095 * and verify its contents
5096 */
bb8c093b 5097static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY
5098{
5099 __le32 *image;
5100 u32 len;
5101 int rc = 0;
5102
5103 /* Try bootstrap */
5104 image = (__le32 *)priv->ucode_boot.v_addr;
5105 len = priv->ucode_boot.len;
bb8c093b 5106 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5107 if (rc == 0) {
5108 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5109 return 0;
5110 }
5111
5112 /* Try initialize */
5113 image = (__le32 *)priv->ucode_init.v_addr;
5114 len = priv->ucode_init.len;
bb8c093b 5115 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5116 if (rc == 0) {
5117 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5118 return 0;
5119 }
5120
5121 /* Try runtime/protocol */
5122 image = (__le32 *)priv->ucode_code.v_addr;
5123 len = priv->ucode_code.len;
bb8c093b 5124 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
5125 if (rc == 0) {
5126 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5127 return 0;
5128 }
5129
5130 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5131
9fbab516
BC
5132 /* Since nothing seems to match, show first several data entries in
5133 * instruction SRAM, so maybe visual inspection will give a clue.
5134 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
5135 image = (__le32 *)priv->ucode_boot.v_addr;
5136 len = priv->ucode_boot.len;
bb8c093b 5137 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
5138
5139 return rc;
5140}
5141
5142
5143/* check contents of special bootstrap uCode SRAM */
bb8c093b 5144static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY
5145{
5146 __le32 *image = priv->ucode_boot.v_addr;
5147 u32 len = priv->ucode_boot.len;
5148 u32 reg;
5149 u32 val;
5150
5151 IWL_DEBUG_INFO("Begin verify bsm\n");
5152
5153 /* verify BSM SRAM contents */
bb8c093b 5154 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY
5155 for (reg = BSM_SRAM_LOWER_BOUND;
5156 reg < BSM_SRAM_LOWER_BOUND + len;
3ac7f146 5157 reg += sizeof(u32), image++) {
bb8c093b 5158 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY
5159 if (val != le32_to_cpu(*image)) {
5160 IWL_ERROR("BSM uCode verification failed at "
5161 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5162 BSM_SRAM_LOWER_BOUND,
5163 reg - BSM_SRAM_LOWER_BOUND, len,
5164 val, le32_to_cpu(*image));
5165 return -EIO;
5166 }
5167 }
5168
5169 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5170
5171 return 0;
5172}
5173
5174/**
bb8c093b 5175 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY
5176 *
5177 * BSM operation:
5178 *
5179 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5180 * in special SRAM that does not power down during RFKILL. When powering back
5181 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5182 * the bootstrap program into the on-board processor, and starts it.
5183 *
5184 * The bootstrap program loads (via DMA) instructions and data for a new
5185 * program from host DRAM locations indicated by the host driver in the
5186 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5187 * automatically.
5188 *
5189 * When initializing the NIC, the host driver points the BSM to the
5190 * "initialize" uCode image. This uCode sets up some internal data, then
5191 * notifies host via "initialize alive" that it is complete.
5192 *
5193 * The host then replaces the BSM_DRAM_* pointer values to point to the
5194 * normal runtime uCode instructions and a backup uCode data cache buffer
5195 * (filled initially with starting data values for the on-board processor),
5196 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5197 * which begins normal operation.
5198 *
5199 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5200 * the backup data cache in DRAM before SRAM is powered down.
5201 *
5202 * When powering back up, the BSM loads the bootstrap program. This reloads
5203 * the runtime uCode instructions and the backup data cache into SRAM,
5204 * and re-launches the runtime uCode from where it left off.
5205 */
bb8c093b 5206static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY
5207{
5208 __le32 *image = priv->ucode_boot.v_addr;
5209 u32 len = priv->ucode_boot.len;
5210 dma_addr_t pinst;
5211 dma_addr_t pdata;
5212 u32 inst_len;
5213 u32 data_len;
5214 int rc;
5215 int i;
5216 u32 done;
5217 u32 reg_offset;
5218
5219 IWL_DEBUG_INFO("Begin load bsm\n");
5220
5221 /* make sure bootstrap program is no larger than BSM's SRAM size */
5222 if (len > IWL_MAX_BSM_SIZE)
5223 return -EINVAL;
5224
5225 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5226 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5227 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY
5228 * after the "initialize" uCode has run, to point to
5229 * runtime/protocol instructions and backup data cache. */
5230 pinst = priv->ucode_init.p_addr;
5231 pdata = priv->ucode_init_data.p_addr;
5232 inst_len = priv->ucode_init.len;
5233 data_len = priv->ucode_init_data.len;
5234
bb8c093b 5235 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5236 if (rc)
5237 return rc;
5238
bb8c093b
CH
5239 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5240 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5241 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5242 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY
5243
5244 /* Fill BSM memory with bootstrap instructions */
5245 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5246 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5247 reg_offset += sizeof(u32), image++)
bb8c093b 5248 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY
5249 le32_to_cpu(*image));
5250
bb8c093b 5251 rc = iwl3945_verify_bsm(priv);
b481de9c 5252 if (rc) {
bb8c093b 5253 iwl3945_release_nic_access(priv);
b481de9c
ZY
5254 return rc;
5255 }
5256
5257 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH
5258 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5259 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5260 RTC_INST_LOWER_BOUND);
bb8c093b 5261 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY
5262
5263 /* Load bootstrap code into instruction SRAM now,
5264 * to prepare to load "initialize" uCode */
bb8c093b 5265 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5266 BSM_WR_CTRL_REG_BIT_START);
5267
5268 /* Wait for load of bootstrap uCode to finish */
5269 for (i = 0; i < 100; i++) {
bb8c093b 5270 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY
5271 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5272 break;
5273 udelay(10);
5274 }
5275 if (i < 100)
5276 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5277 else {
5278 IWL_ERROR("BSM write did not complete!\n");
5279 return -EIO;
5280 }
5281
5282 /* Enable future boot loads whenever power management unit triggers it
5283 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5284 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY
5285 BSM_WR_CTRL_REG_BIT_START_EN);
5286
bb8c093b 5287 iwl3945_release_nic_access(priv);
b481de9c
ZY
5288
5289 return 0;
5290}
5291
bb8c093b 5292static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY
5293{
5294 /* Remove all resets to allow NIC to operate */
bb8c093b 5295 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY
5296}
5297
5298/**
bb8c093b 5299 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
5300 *
5301 * Copy into buffers for card to fetch via bus-mastering
5302 */
bb8c093b 5303static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5304{
bb8c093b 5305 struct iwl3945_ucode *ucode;
a0987a8d 5306 int ret = -EINVAL, index;
b481de9c
ZY
5307 const struct firmware *ucode_raw;
5308 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
5309 const char *name_pre = priv->cfg->fw_name_pre;
5310 const unsigned int api_max = priv->cfg->ucode_api_max;
5311 const unsigned int api_min = priv->cfg->ucode_api_min;
5312 char buf[25];
b481de9c
ZY
5313 u8 *src;
5314 size_t len;
a0987a8d 5315 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
5316
5317 /* Ask kernel firmware_class module to get the boot firmware off disk.
5318 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
5319 for (index = api_max; index >= api_min; index--) {
5320 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
5321 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
5322 if (ret < 0) {
5323 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5324 buf, ret);
5325 if (ret == -ENOENT)
5326 continue;
5327 else
5328 goto error;
5329 } else {
5330 if (index < api_max)
5331 IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
5332 buf, api_max);
5333 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5334 buf, ucode_raw->size);
5335 break;
5336 }
b481de9c
ZY
5337 }
5338
a0987a8d
RC
5339 if (ret < 0)
5340 goto error;
b481de9c
ZY
5341
5342 /* Make sure that we got at least our header! */
5343 if (ucode_raw->size < sizeof(*ucode)) {
5344 IWL_ERROR("File size way too small!\n");
90e759d1 5345 ret = -EINVAL;
b481de9c
ZY
5346 goto err_release;
5347 }
5348
5349 /* Data from ucode file: header followed by uCode images */
5350 ucode = (void *)ucode_raw->data;
5351
c02b3acd 5352 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 5353 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
5354 inst_size = le32_to_cpu(ucode->inst_size);
5355 data_size = le32_to_cpu(ucode->data_size);
5356 init_size = le32_to_cpu(ucode->init_size);
5357 init_data_size = le32_to_cpu(ucode->init_data_size);
5358 boot_size = le32_to_cpu(ucode->boot_size);
5359
a0987a8d
RC
5360 /* api_ver should match the api version forming part of the
5361 * firmware filename ... but we don't check for that and only rely
5362 * on the API version read from firware header from here on forward */
5363
5364 if (api_ver < api_min || api_ver > api_max) {
5365 IWL_ERROR("Driver unable to support your firmware API. "
5366 "Driver supports v%u, firmware is v%u.\n",
5367 api_max, api_ver);
5368 priv->ucode_ver = 0;
5369 ret = -EINVAL;
5370 goto err_release;
5371 }
5372 if (api_ver != api_max)
5373 IWL_ERROR("Firmware has old API version. Expected %u, "
5374 "got %u. New firmware can be obtained "
5375 "from http://www.intellinuxwireless.org.\n",
5376 api_max, api_ver);
5377
5378 printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
c02b3acd
CR
5379 IWL_UCODE_MAJOR(priv->ucode_ver),
5380 IWL_UCODE_MINOR(priv->ucode_ver),
5381 IWL_UCODE_API(priv->ucode_ver),
5382 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d
RC
5383 IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
5384 priv->ucode_ver);
bc434dd2
IS
5385 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5386 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5387 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5388 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5389 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c 5390
a0987a8d 5391
b481de9c
ZY
5392 /* Verify size of file vs. image size info in file's header */
5393 if (ucode_raw->size < sizeof(*ucode) +
5394 inst_size + data_size + init_size +
5395 init_data_size + boot_size) {
5396
5397 IWL_DEBUG_INFO("uCode file size %d too small\n",
5398 (int)ucode_raw->size);
90e759d1 5399 ret = -EINVAL;
b481de9c
ZY
5400 goto err_release;
5401 }
5402
5403 /* Verify that uCode images will fit in card's SRAM */
5404 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
5405 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5406 inst_size);
5407 ret = -EINVAL;
b481de9c
ZY
5408 goto err_release;
5409 }
5410
5411 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
5412 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5413 data_size);
5414 ret = -EINVAL;
b481de9c
ZY
5415 goto err_release;
5416 }
5417 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW
5418 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5419 init_size);
5420 ret = -EINVAL;
b481de9c
ZY
5421 goto err_release;
5422 }
5423 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW
5424 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5425 init_data_size);
5426 ret = -EINVAL;
b481de9c
ZY
5427 goto err_release;
5428 }
5429 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW
5430 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5431 boot_size);
5432 ret = -EINVAL;
b481de9c
ZY
5433 goto err_release;
5434 }
5435
5436 /* Allocate ucode buffers for card's bus-master loading ... */
5437
5438 /* Runtime instructions and 2 copies of data:
5439 * 1) unmodified from disk
5440 * 2) backup cache for save/restore during power-downs */
5441 priv->ucode_code.len = inst_size;
98c92211 5442 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
5443
5444 priv->ucode_data.len = data_size;
98c92211 5445 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
5446
5447 priv->ucode_data_backup.len = data_size;
98c92211 5448 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5449
90e759d1
TW
5450 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5451 !priv->ucode_data_backup.v_addr)
5452 goto err_pci_alloc;
b481de9c
ZY
5453
5454 /* Initialization instructions and data */
90e759d1
TW
5455 if (init_size && init_data_size) {
5456 priv->ucode_init.len = init_size;
98c92211 5457 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
5458
5459 priv->ucode_init_data.len = init_data_size;
98c92211 5460 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
5461
5462 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5463 goto err_pci_alloc;
5464 }
b481de9c
ZY
5465
5466 /* Bootstrap (instructions only, no data) */
90e759d1
TW
5467 if (boot_size) {
5468 priv->ucode_boot.len = boot_size;
98c92211 5469 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5470
90e759d1
TW
5471 if (!priv->ucode_boot.v_addr)
5472 goto err_pci_alloc;
5473 }
b481de9c
ZY
5474
5475 /* Copy images into buffers for card's bus-master reads ... */
5476
5477 /* Runtime instructions (first block of data in file) */
5478 src = &ucode->data[0];
5479 len = priv->ucode_code.len;
90e759d1 5480 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY
5481 memcpy(priv->ucode_code.v_addr, src, len);
5482 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5483 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5484
5485 /* Runtime data (2nd block)
bb8c093b 5486 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
5487 src = &ucode->data[inst_size];
5488 len = priv->ucode_data.len;
90e759d1 5489 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
5490 memcpy(priv->ucode_data.v_addr, src, len);
5491 memcpy(priv->ucode_data_backup.v_addr, src, len);
5492
5493 /* Initialization instructions (3rd block) */
5494 if (init_size) {
5495 src = &ucode->data[inst_size + data_size];
5496 len = priv->ucode_init.len;
90e759d1
TW
5497 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5498 len);
b481de9c
ZY
5499 memcpy(priv->ucode_init.v_addr, src, len);
5500 }
5501
5502 /* Initialization data (4th block) */
5503 if (init_data_size) {
5504 src = &ucode->data[inst_size + data_size + init_size];
5505 len = priv->ucode_init_data.len;
5506 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5507 (int)len);
5508 memcpy(priv->ucode_init_data.v_addr, src, len);
5509 }
5510
5511 /* Bootstrap instructions (5th block) */
5512 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5513 len = priv->ucode_boot.len;
5514 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5515 (int)len);
5516 memcpy(priv->ucode_boot.v_addr, src, len);
5517
5518 /* We have our copies now, allow OS release its copies */
5519 release_firmware(ucode_raw);
5520 return 0;
5521
5522 err_pci_alloc:
5523 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5524 ret = -ENOMEM;
bb8c093b 5525 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
5526
5527 err_release:
5528 release_firmware(ucode_raw);
5529
5530 error:
90e759d1 5531 return ret;
b481de9c
ZY
5532}
5533
5534
5535/**
bb8c093b 5536 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
5537 *
5538 * Tell initialization uCode where to find runtime uCode.
5539 *
5540 * BSM registers initially contain pointers to initialization uCode.
5541 * We need to replace them to load runtime uCode inst and data,
5542 * and to save runtime data when powering down.
5543 */
bb8c093b 5544static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY
5545{
5546 dma_addr_t pinst;
5547 dma_addr_t pdata;
5548 int rc = 0;
5549 unsigned long flags;
5550
5551 /* bits 31:0 for 3945 */
5552 pinst = priv->ucode_code.p_addr;
5553 pdata = priv->ucode_data_backup.p_addr;
5554
5555 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5556 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY
5557 if (rc) {
5558 spin_unlock_irqrestore(&priv->lock, flags);
5559 return rc;
5560 }
5561
5562 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH
5563 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5564 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5565 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
5566 priv->ucode_data.len);
5567
a96a27f9 5568 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 5569 * that all new ptr/size info is in place */
bb8c093b 5570 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
5571 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5572
bb8c093b 5573 iwl3945_release_nic_access(priv);
b481de9c
ZY
5574
5575 spin_unlock_irqrestore(&priv->lock, flags);
5576
5577 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5578
5579 return rc;
5580}
5581
5582/**
bb8c093b 5583 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
5584 *
5585 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5586 *
b481de9c 5587 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5588 */
bb8c093b 5589static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY
5590{
5591 /* Check alive response for "valid" sign from uCode */
5592 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5593 /* We had an error bringing up the hardware, so take it
5594 * all the way back down so we can try again */
5595 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5596 goto restart;
5597 }
5598
5599 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5600 * This is a paranoid check, because we would not have gotten the
5601 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5602 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
5603 /* Runtime instruction load was bad;
5604 * take it all the way back down so we can try again */
5605 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5606 goto restart;
5607 }
5608
5609 /* Send pointers to protocol/runtime uCode image ... init code will
5610 * load and launch runtime uCode, which will send us another "Alive"
5611 * notification. */
5612 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5613 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
5614 /* Runtime instruction load won't happen;
5615 * take it all the way back down so we can try again */
5616 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5617 goto restart;
5618 }
5619 return;
5620
5621 restart:
5622 queue_work(priv->workqueue, &priv->restart);
5623}
5624
5625
9bdf5eca
MA
5626/* temporary */
5627static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
5628 struct sk_buff *skb);
5629
b481de9c 5630/**
bb8c093b 5631 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5632 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5633 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5634 */
bb8c093b 5635static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY
5636{
5637 int rc = 0;
5638 int thermal_spin = 0;
5639 u32 rfkill;
5640
5641 IWL_DEBUG_INFO("Runtime Alive received.\n");
5642
5643 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5644 /* We had an error bringing up the hardware, so take it
5645 * all the way back down so we can try again */
5646 IWL_DEBUG_INFO("Alive failed.\n");
5647 goto restart;
5648 }
5649
5650 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5651 * This is a paranoid check, because we would not have gotten the
5652 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5653 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
5654 /* Runtime instruction load was bad;
5655 * take it all the way back down so we can try again */
5656 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5657 goto restart;
5658 }
5659
bb8c093b 5660 iwl3945_clear_stations_table(priv);
b481de9c 5661
bb8c093b 5662 rc = iwl3945_grab_nic_access(priv);
b481de9c 5663 if (rc) {
a96a27f9 5664 IWL_WARNING("Can not read RFKILL status from adapter\n");
b481de9c
ZY
5665 return;
5666 }
5667
bb8c093b 5668 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5669 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5670 iwl3945_release_nic_access(priv);
b481de9c
ZY
5671
5672 if (rfkill & 0x1) {
5673 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 5674 /* if RFKILL is not on, then wait for thermal
b481de9c 5675 * sensor in adapter to kick in */
bb8c093b 5676 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
5677 thermal_spin++;
5678 udelay(10);
5679 }
5680
5681 if (thermal_spin)
5682 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5683 thermal_spin * 10);
5684 } else
5685 set_bit(STATUS_RF_KILL_HW, &priv->status);
5686
9fbab516 5687 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
5688 set_bit(STATUS_ALIVE, &priv->status);
5689
5690 /* Clear out the uCode error bit if it is set */
5691 clear_bit(STATUS_FW_ERROR, &priv->status);
5692
bb8c093b 5693 if (iwl3945_is_rfkill(priv))
b481de9c
ZY
5694 return;
5695
36d6825b 5696 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
5697
5698 priv->active_rate = priv->rates_mask;
5699 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5700
bb8c093b 5701 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5702
bb8c093b
CH
5703 if (iwl3945_is_associated(priv)) {
5704 struct iwl3945_rxon_cmd *active_rxon =
5705 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY
5706
5707 memcpy(&priv->staging_rxon, &priv->active_rxon,
5708 sizeof(priv->staging_rxon));
5709 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5710 } else {
5711 /* Initialize our rx_config data */
60294de3 5712 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
5713 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5714 }
5715
9fbab516 5716 /* Configure Bluetooth device coexistence support */
bb8c093b 5717 iwl3945_send_bt_config(priv);
b481de9c
ZY
5718
5719 /* Configure the adapter for unassociated operation */
bb8c093b 5720 iwl3945_commit_rxon(priv);
b481de9c 5721
b481de9c
ZY
5722 iwl3945_reg_txpower_periodic(priv);
5723
fe00b5a5
RC
5724 iwl3945_led_register(priv);
5725
b481de9c 5726 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5727 set_bit(STATUS_READY, &priv->status);
5a66926a 5728 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
5729
5730 if (priv->error_recovering)
bb8c093b 5731 iwl3945_error_recovery(priv);
b481de9c 5732
9bdf5eca
MA
5733 /* reassociate for ADHOC mode */
5734 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
5735 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
5736 priv->vif);
5737 if (beacon)
5738 iwl3945_mac_beacon_update(priv->hw, beacon);
5739 }
5740
b481de9c
ZY
5741 return;
5742
5743 restart:
5744 queue_work(priv->workqueue, &priv->restart);
5745}
5746
bb8c093b 5747static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5748
bb8c093b 5749static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY
5750{
5751 unsigned long flags;
5752 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5753 struct ieee80211_conf *conf = NULL;
5754
5755 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5756
5757 conf = ieee80211_get_hw_conf(priv->hw);
5758
5759 if (!exit_pending)
5760 set_bit(STATUS_EXIT_PENDING, &priv->status);
5761
ab53d8af 5762 iwl3945_led_unregister(priv);
bb8c093b 5763 iwl3945_clear_stations_table(priv);
b481de9c
ZY
5764
5765 /* Unblock any waiting calls */
5766 wake_up_interruptible_all(&priv->wait_command_queue);
5767
b481de9c
ZY
5768 /* Wipe out the EXIT_PENDING status bit if we are not actually
5769 * exiting the module */
5770 if (!exit_pending)
5771 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5772
5773 /* stop and reset the on-board processor */
bb8c093b 5774 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
5775
5776 /* tell the device to stop sending interrupts */
0359facc 5777 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5778 iwl3945_disable_interrupts(priv);
0359facc
MA
5779 spin_unlock_irqrestore(&priv->lock, flags);
5780 iwl_synchronize_irq(priv);
b481de9c
ZY
5781
5782 if (priv->mac80211_registered)
5783 ieee80211_stop_queues(priv->hw);
5784
bb8c093b 5785 /* If we have not previously called iwl3945_init() then
b481de9c 5786 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5787 if (!iwl3945_is_init(priv)) {
b481de9c
ZY
5788 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5789 STATUS_RF_KILL_HW |
5790 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5791 STATUS_RF_KILL_SW |
9788864e
RC
5792 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5793 STATUS_GEO_CONFIGURED |
b481de9c 5794 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK
5795 STATUS_IN_SUSPEND |
5796 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5797 STATUS_EXIT_PENDING;
b481de9c
ZY
5798 goto exit;
5799 }
5800
5801 /* ...otherwise clear out all the status bits but the RF Kill and
5802 * SUSPEND bits and continue taking the NIC down. */
5803 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5804 STATUS_RF_KILL_HW |
5805 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5806 STATUS_RF_KILL_SW |
9788864e
RC
5807 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5808 STATUS_GEO_CONFIGURED |
b481de9c
ZY
5809 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5810 STATUS_IN_SUSPEND |
5811 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
5812 STATUS_FW_ERROR |
5813 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5814 STATUS_EXIT_PENDING;
b481de9c
ZY
5815
5816 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5817 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
5818 spin_unlock_irqrestore(&priv->lock, flags);
5819
bb8c093b
CH
5820 iwl3945_hw_txq_ctx_stop(priv);
5821 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY
5822
5823 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH
5824 if (!iwl3945_grab_nic_access(priv)) {
5825 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5826 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5827 iwl3945_release_nic_access(priv);
b481de9c
ZY
5828 }
5829 spin_unlock_irqrestore(&priv->lock, flags);
5830
5831 udelay(5);
5832
bb8c093b
CH
5833 iwl3945_hw_nic_stop_master(priv);
5834 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5835 iwl3945_hw_nic_reset(priv);
b481de9c
ZY
5836
5837 exit:
3d24a9f7 5838 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
5839
5840 if (priv->ibss_beacon)
5841 dev_kfree_skb(priv->ibss_beacon);
5842 priv->ibss_beacon = NULL;
5843
5844 /* clear out any free frames */
bb8c093b 5845 iwl3945_clear_free_frames(priv);
b481de9c
ZY
5846}
5847
bb8c093b 5848static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY
5849{
5850 mutex_lock(&priv->mutex);
bb8c093b 5851 __iwl3945_down(priv);
b481de9c 5852 mutex_unlock(&priv->mutex);
b24d22b1 5853
bb8c093b 5854 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
5855}
5856
5857#define MAX_HW_RESTARTS 5
5858
bb8c093b 5859static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY
5860{
5861 int rc, i;
5862
5863 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5864 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5865 return -EIO;
5866 }
5867
5868 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5869 IWL_WARNING("Radio disabled by SW RF kill (module "
5870 "parameter)\n");
e655b9f0
ZY
5871 return -ENODEV;
5872 }
5873
e903fbd4 5874 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
a96a27f9 5875 IWL_ERROR("ucode not available for device bring up\n");
e903fbd4
RC
5876 return -EIO;
5877 }
5878
e655b9f0
ZY
5879 /* If platform's RF_KILL switch is NOT set to KILL */
5880 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5881 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5882 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5883 else {
5884 set_bit(STATUS_RF_KILL_HW, &priv->status);
5885 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5886 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5887 return -ENODEV;
5888 }
b481de9c 5889 }
80fcc9e2 5890
bb8c093b 5891 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5892
bb8c093b 5893 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY
5894 if (rc) {
5895 IWL_ERROR("Unable to int nic\n");
5896 return rc;
5897 }
5898
5899 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH
5900 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5901 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
5902 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5903
5904 /* clear (again), then enable host interrupts */
bb8c093b
CH
5905 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5906 iwl3945_enable_interrupts(priv);
b481de9c
ZY
5907
5908 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH
5909 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5910 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
5911
5912 /* Copy original ucode data image from disk into backup cache.
5913 * This will be used to initialize the on-board processor's
5914 * data SRAM for a clean start when the runtime program first loads. */
5915 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5916 priv->ucode_data.len);
b481de9c 5917
e655b9f0
ZY
5918 /* We return success when we resume from suspend and rf_kill is on. */
5919 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5920 return 0;
5921
b481de9c
ZY
5922 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5923
bb8c093b 5924 iwl3945_clear_stations_table(priv);
b481de9c
ZY
5925
5926 /* load bootstrap state machine,
5927 * load bootstrap program into processor's memory,
5928 * prepare to load the "initialize" uCode */
bb8c093b 5929 rc = iwl3945_load_bsm(priv);
b481de9c
ZY
5930
5931 if (rc) {
5932 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5933 continue;
5934 }
5935
5936 /* start card; "initialize" will load runtime ucode */
bb8c093b 5937 iwl3945_nic_start(priv);
b481de9c 5938
b481de9c
ZY
5939 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5940
5941 return 0;
5942 }
5943
5944 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5945 __iwl3945_down(priv);
ebef2008 5946 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
5947
5948 /* tried to restart and config the device for as long as our
5949 * patience could withstand */
5950 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5951 return -EIO;
5952}
5953
5954
5955/*****************************************************************************
5956 *
5957 * Workqueue callbacks
5958 *
5959 *****************************************************************************/
5960
bb8c093b 5961static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5962{
bb8c093b
CH
5963 struct iwl3945_priv *priv =
5964 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY
5965
5966 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5967 return;
5968
5969 mutex_lock(&priv->mutex);
bb8c093b 5970 iwl3945_init_alive_start(priv);
b481de9c
ZY
5971 mutex_unlock(&priv->mutex);
5972}
5973
bb8c093b 5974static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5975{
bb8c093b
CH
5976 struct iwl3945_priv *priv =
5977 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY
5978
5979 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5980 return;
5981
5982 mutex_lock(&priv->mutex);
bb8c093b 5983 iwl3945_alive_start(priv);
b481de9c
ZY
5984 mutex_unlock(&priv->mutex);
5985}
5986
bb8c093b 5987static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5988{
bb8c093b 5989 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY
5990
5991 wake_up_interruptible(&priv->wait_command_queue);
5992
5993 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5994 return;
5995
5996 mutex_lock(&priv->mutex);
5997
bb8c093b 5998 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY
5999 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6000 "HW and/or SW RF Kill no longer active, restarting "
6001 "device\n");
6002 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6003 queue_work(priv->workqueue, &priv->restart);
6004 } else {
6005
6006 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6007 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6008 "disabled by SW switch\n");
6009 else
6010 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6011 "Kill switch must be turned off for "
6012 "wireless networking to work.\n");
6013 }
ebef2008 6014
b481de9c 6015 mutex_unlock(&priv->mutex);
80fcc9e2 6016 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY
6017}
6018
6019#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6020
bb8c093b 6021static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6022{
bb8c093b
CH
6023 struct iwl3945_priv *priv =
6024 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY
6025
6026 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6027 return;
6028
6029 mutex_lock(&priv->mutex);
6030 if (test_bit(STATUS_SCANNING, &priv->status) ||
6031 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6032 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6033 "Scan completion watchdog resetting adapter (%dms)\n",
6034 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6035
b481de9c 6036 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6037 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6038 }
6039 mutex_unlock(&priv->mutex);
6040}
6041
bb8c093b 6042static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6043{
bb8c093b
CH
6044 struct iwl3945_priv *priv =
6045 container_of(data, struct iwl3945_priv, request_scan);
6046 struct iwl3945_host_cmd cmd = {
b481de9c 6047 .id = REPLY_SCAN_CMD,
bb8c093b 6048 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
6049 .meta.flags = CMD_SIZE_HUGE,
6050 };
6051 int rc = 0;
bb8c093b 6052 struct iwl3945_scan_cmd *scan;
b481de9c 6053 struct ieee80211_conf *conf = NULL;
f9340520 6054 u8 n_probes = 2;
8318d78a 6055 enum ieee80211_band band;
9387b7ca 6056 DECLARE_SSID_BUF(ssid);
b481de9c
ZY
6057
6058 conf = ieee80211_get_hw_conf(priv->hw);
6059
6060 mutex_lock(&priv->mutex);
6061
bb8c093b 6062 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY
6063 IWL_WARNING("request scan called when driver not ready.\n");
6064 goto done;
6065 }
6066
a96a27f9 6067 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
6068 * was given the chance to run... */
6069 if (!test_bit(STATUS_SCANNING, &priv->status))
6070 goto done;
6071
6072 /* This should never be called or scheduled if there is currently
6073 * a scan active in the hardware. */
6074 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6075 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6076 "Ignoring second request.\n");
6077 rc = -EIO;
6078 goto done;
6079 }
6080
6081 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6082 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6083 goto done;
6084 }
6085
6086 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6087 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6088 goto done;
6089 }
6090
bb8c093b 6091 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY
6092 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6093 goto done;
6094 }
6095
6096 if (!test_bit(STATUS_READY, &priv->status)) {
6097 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6098 goto done;
6099 }
6100
6101 if (!priv->scan_bands) {
6102 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6103 goto done;
6104 }
6105
6106 if (!priv->scan) {
bb8c093b 6107 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY
6108 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6109 if (!priv->scan) {
6110 rc = -ENOMEM;
6111 goto done;
6112 }
6113 }
6114 scan = priv->scan;
bb8c093b 6115 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
6116
6117 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6118 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6119
bb8c093b 6120 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
6121 u16 interval = 0;
6122 u32 extra;
6123 u32 suspend_time = 100;
6124 u32 scan_suspend_time = 100;
6125 unsigned long flags;
6126
6127 IWL_DEBUG_INFO("Scanning while associated...\n");
6128
6129 spin_lock_irqsave(&priv->lock, flags);
6130 interval = priv->beacon_int;
6131 spin_unlock_irqrestore(&priv->lock, flags);
6132
6133 scan->suspend_time = 0;
15e869d8 6134 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
6135 if (!interval)
6136 interval = suspend_time;
6137 /*
6138 * suspend time format:
6139 * 0-19: beacon interval in usec (time before exec.)
6140 * 20-23: 0
6141 * 24-31: number of beacons (suspend between channels)
6142 */
6143
6144 extra = (suspend_time / interval) << 24;
6145 scan_suspend_time = 0xFF0FFFFF &
6146 (extra | ((suspend_time % interval) * 1024));
6147
6148 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6149 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6150 scan_suspend_time, interval);
6151 }
6152
6153 /* We should add the ability for user to lock to PASSIVE ONLY */
6154 if (priv->one_direct_scan) {
6155 IWL_DEBUG_SCAN
6156 ("Kicking off one direct scan for '%s'\n",
9387b7ca
JL
6157 print_ssid(ssid, priv->direct_ssid,
6158 priv->direct_ssid_len));
b481de9c
ZY
6159 scan->direct_scan[0].id = WLAN_EID_SSID;
6160 scan->direct_scan[0].len = priv->direct_ssid_len;
6161 memcpy(scan->direct_scan[0].ssid,
6162 priv->direct_ssid, priv->direct_ssid_len);
f9340520 6163 n_probes++;
f9340520 6164 } else
786b4557 6165 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY
6166
6167 /* We don't build a direct scan probe request; the uCode will do
6168 * that based on the direct_mask added to each channel entry */
6169 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6170 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
430cfe95 6171 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
b481de9c
ZY
6172 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6173 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6174 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6175
6176 /* flags + rate selection */
6177
66b5004d 6178 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
6179 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6180 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6181 scan->good_CRC_th = 0;
8318d78a 6182 band = IEEE80211_BAND_2GHZ;
66b5004d 6183 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY
6184 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6185 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6186 band = IEEE80211_BAND_5GHZ;
66b5004d 6187 } else {
b481de9c
ZY
6188 IWL_WARNING("Invalid scan band count\n");
6189 goto done;
6190 }
6191
6192 /* select Rx antennas */
6193 scan->flags |= iwl3945_get_antenna_flags(priv);
6194
05c914fe 6195 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY
6196 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6197
f9340520
AK
6198 scan->channel_count =
6199 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
6200 n_probes,
6201 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 6202
14b54336
RC
6203 if (scan->channel_count == 0) {
6204 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
6205 goto done;
6206 }
6207
b481de9c 6208 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6209 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
6210 cmd.data = scan;
6211 scan->len = cpu_to_le16(cmd.len);
6212
6213 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6214 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
6215 if (rc)
6216 goto done;
6217
6218 queue_delayed_work(priv->workqueue, &priv->scan_check,
6219 IWL_SCAN_CHECK_WATCHDOG);
6220
6221 mutex_unlock(&priv->mutex);
6222 return;
6223
6224 done:
2420ebc1
MA
6225 /* can not perform scan make sure we clear scanning
6226 * bits from status so next scan request can be performed.
6227 * if we dont clear scanning status bit here all next scan
6228 * will fail
6229 */
6230 clear_bit(STATUS_SCAN_HW, &priv->status);
6231 clear_bit(STATUS_SCANNING, &priv->status);
6232
01ebd063 6233 /* inform mac80211 scan aborted */
b481de9c
ZY
6234 queue_work(priv->workqueue, &priv->scan_completed);
6235 mutex_unlock(&priv->mutex);
6236}
6237
bb8c093b 6238static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6239{
bb8c093b 6240 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY
6241
6242 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6243 return;
6244
6245 mutex_lock(&priv->mutex);
bb8c093b 6246 __iwl3945_up(priv);
b481de9c 6247 mutex_unlock(&priv->mutex);
80fcc9e2 6248 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY
6249}
6250
bb8c093b 6251static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6252{
bb8c093b 6253 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY
6254
6255 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6256 return;
6257
bb8c093b 6258 iwl3945_down(priv);
b481de9c
ZY
6259 queue_work(priv->workqueue, &priv->up);
6260}
6261
bb8c093b 6262static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6263{
bb8c093b
CH
6264 struct iwl3945_priv *priv =
6265 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY
6266
6267 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6268 return;
6269
6270 mutex_lock(&priv->mutex);
bb8c093b 6271 iwl3945_rx_replenish(priv);
b481de9c
ZY
6272 mutex_unlock(&priv->mutex);
6273}
6274
7878a5a4
MA
6275#define IWL_DELAY_NEXT_SCAN (HZ*2)
6276
cd56d331 6277static void iwl3945_post_associate(struct iwl3945_priv *priv)
b481de9c 6278{
b481de9c
ZY
6279 int rc = 0;
6280 struct ieee80211_conf *conf = NULL;
6281
05c914fe 6282 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3ac7f146 6283 IWL_ERROR("%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
6284 return;
6285 }
6286
6287
e174961c
JB
6288 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
6289 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
6290
6291 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6292 return;
6293
322a9811 6294 if (!priv->vif || !priv->is_open)
6ef89d0a 6295 return;
322a9811 6296
bb8c093b 6297 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6298
b481de9c
ZY
6299 conf = ieee80211_get_hw_conf(priv->hw);
6300
6301 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6302 iwl3945_commit_rxon(priv);
b481de9c 6303
28afaf91 6304 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH
6305 iwl3945_setup_rxon_timing(priv);
6306 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6307 sizeof(priv->rxon_timing), &priv->rxon_timing);
6308 if (rc)
6309 IWL_WARNING("REPLY_RXON_TIMING failed - "
6310 "Attempting to continue.\n");
6311
6312 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6313
6314 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6315
6316 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6317 priv->assoc_id, priv->beacon_int);
6318
6319 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6320 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6321 else
6322 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6323
6324 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6325 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6326 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6327 else
6328 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6329
05c914fe 6330 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
6331 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6332
6333 }
6334
bb8c093b 6335 iwl3945_commit_rxon(priv);
b481de9c
ZY
6336
6337 switch (priv->iw_mode) {
05c914fe 6338 case NL80211_IFTYPE_STATION:
bb8c093b 6339 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
6340 break;
6341
05c914fe 6342 case NL80211_IFTYPE_ADHOC:
b481de9c 6343
ce546fd2 6344 priv->assoc_id = 1;
bb8c093b 6345 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6346 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6347 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
6348 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6349 CMD_ASYNC);
bb8c093b
CH
6350 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6351 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
6352
6353 break;
6354
6355 default:
6356 IWL_ERROR("%s Should not be called in %d mode\n",
3ac7f146 6357 __func__, priv->iw_mode);
b481de9c
ZY
6358 break;
6359 }
6360
bb8c093b 6361 iwl3945_activate_qos(priv, 0);
292ae174 6362
7878a5a4
MA
6363 /* we have just associated, don't start scan too early */
6364 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
6365}
6366
bb8c093b 6367static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6368{
bb8c093b 6369 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6370
bb8c093b 6371 if (!iwl3945_is_ready(priv))
b481de9c
ZY
6372 return;
6373
6374 mutex_lock(&priv->mutex);
6375
6376 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6377 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6378
6379 mutex_unlock(&priv->mutex);
6380}
6381
e8975581 6382static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6383
bb8c093b 6384static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6385{
bb8c093b
CH
6386 struct iwl3945_priv *priv =
6387 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY
6388
6389 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6390
6391 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6392 return;
6393
a0646470 6394 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6395 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6396
b481de9c
ZY
6397 ieee80211_scan_completed(priv->hw);
6398
6399 /* Since setting the TXPOWER may have been deferred while
6400 * performing the scan, fire one off */
6401 mutex_lock(&priv->mutex);
bb8c093b 6402 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
6403 mutex_unlock(&priv->mutex);
6404}
6405
6406/*****************************************************************************
6407 *
6408 * mac80211 entry point functions
6409 *
6410 *****************************************************************************/
6411
5a66926a
ZY
6412#define UCODE_READY_TIMEOUT (2 * HZ)
6413
bb8c093b 6414static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6415{
bb8c093b 6416 struct iwl3945_priv *priv = hw->priv;
5a66926a 6417 int ret;
b481de9c
ZY
6418
6419 IWL_DEBUG_MAC80211("enter\n");
6420
5a66926a
ZY
6421 if (pci_enable_device(priv->pci_dev)) {
6422 IWL_ERROR("Fail to pci_enable_device\n");
6423 return -ENODEV;
6424 }
6425 pci_restore_state(priv->pci_dev);
6426 pci_enable_msi(priv->pci_dev);
6427
6428 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6429 DRV_NAME, priv);
6430 if (ret) {
6431 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6432 goto out_disable_msi;
6433 }
6434
b481de9c
ZY
6435 /* we should be verifying the device is ready to be opened */
6436 mutex_lock(&priv->mutex);
6437
5a66926a
ZY
6438 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6439 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6440 * ucode filename and max sizes are card-specific. */
6441
6442 if (!priv->ucode_code.len) {
6443 ret = iwl3945_read_ucode(priv);
6444 if (ret) {
6445 IWL_ERROR("Could not read microcode: %d\n", ret);
6446 mutex_unlock(&priv->mutex);
6447 goto out_release_irq;
6448 }
6449 }
b481de9c 6450
e655b9f0 6451 ret = __iwl3945_up(priv);
b481de9c
ZY
6452
6453 mutex_unlock(&priv->mutex);
5a66926a 6454
80fcc9e2
AG
6455 iwl3945_rfkill_set_hw_state(priv);
6456
e655b9f0
ZY
6457 if (ret)
6458 goto out_release_irq;
6459
6460 IWL_DEBUG_INFO("Start UP work.\n");
6461
6462 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6463 return 0;
6464
5a66926a
ZY
6465 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6466 * mac80211 will not be run successfully. */
6467 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6468 test_bit(STATUS_READY, &priv->status),
6469 UCODE_READY_TIMEOUT);
6470 if (!ret) {
6471 if (!test_bit(STATUS_READY, &priv->status)) {
6472 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6473 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6474 ret = -ETIMEDOUT;
6475 goto out_release_irq;
6476 }
6477 }
6478
e655b9f0 6479 priv->is_open = 1;
b481de9c
ZY
6480 IWL_DEBUG_MAC80211("leave\n");
6481 return 0;
5a66926a
ZY
6482
6483out_release_irq:
6484 free_irq(priv->pci_dev->irq, priv);
6485out_disable_msi:
6486 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY
6487 pci_disable_device(priv->pci_dev);
6488 priv->is_open = 0;
6489 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6490 return ret;
b481de9c
ZY
6491}
6492
bb8c093b 6493static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6494{
bb8c093b 6495 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6496
6497 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6498
e655b9f0
ZY
6499 if (!priv->is_open) {
6500 IWL_DEBUG_MAC80211("leave - skip\n");
6501 return;
6502 }
6503
b481de9c 6504 priv->is_open = 0;
5a66926a
ZY
6505
6506 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY
6507 /* stop mac, cancel any scan request and clear
6508 * RXON_FILTER_ASSOC_MSK BIT
6509 */
5a66926a
ZY
6510 mutex_lock(&priv->mutex);
6511 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6512 mutex_unlock(&priv->mutex);
fde3571f
MA
6513 }
6514
5a66926a
ZY
6515 iwl3945_down(priv);
6516
6517 flush_workqueue(priv->workqueue);
6518 free_irq(priv->pci_dev->irq, priv);
6519 pci_disable_msi(priv->pci_dev);
6520 pci_save_state(priv->pci_dev);
6521 pci_disable_device(priv->pci_dev);
6ef89d0a 6522
b481de9c 6523 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6524}
6525
e039fa4a 6526static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6527{
bb8c093b 6528 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6529
6530 IWL_DEBUG_MAC80211("enter\n");
6531
b481de9c 6532 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6533 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6534
e039fa4a 6535 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
6536 dev_kfree_skb_any(skb);
6537
6538 IWL_DEBUG_MAC80211("leave\n");
637f8837 6539 return NETDEV_TX_OK;
b481de9c
ZY
6540}
6541
bb8c093b 6542static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6543 struct ieee80211_if_init_conf *conf)
6544{
bb8c093b 6545 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6546 unsigned long flags;
6547
32bfd35d 6548 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6549
32bfd35d
JB
6550 if (priv->vif) {
6551 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6552 return -EOPNOTSUPP;
b481de9c
ZY
6553 }
6554
6555 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6556 priv->vif = conf->vif;
60294de3 6557 priv->iw_mode = conf->type;
b481de9c
ZY
6558
6559 spin_unlock_irqrestore(&priv->lock, flags);
6560
6561 mutex_lock(&priv->mutex);
864792e3
TW
6562
6563 if (conf->mac_addr) {
e174961c 6564 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW
6565 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6566 }
6567
5a66926a
ZY
6568 if (iwl3945_is_ready(priv))
6569 iwl3945_set_mode(priv, conf->type);
b481de9c 6570
b481de9c
ZY
6571 mutex_unlock(&priv->mutex);
6572
5a66926a 6573 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6574 return 0;
6575}
6576
6577/**
bb8c093b 6578 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY
6579 *
6580 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6581 * be set inappropriately and the driver currently sets the hardware up to
6582 * use it whenever needed.
6583 */
e8975581 6584static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6585{
bb8c093b
CH
6586 struct iwl3945_priv *priv = hw->priv;
6587 const struct iwl3945_channel_info *ch_info;
e8975581 6588 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6589 unsigned long flags;
76bb77e0 6590 int ret = 0;
b481de9c
ZY
6591
6592 mutex_lock(&priv->mutex);
8318d78a 6593 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6594
bb8c093b 6595 if (!iwl3945_is_ready(priv)) {
b481de9c 6596 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY
6597 ret = -EIO;
6598 goto out;
b481de9c
ZY
6599 }
6600
bb8c093b 6601 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6602 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY
6603 IWL_DEBUG_MAC80211("leave - scanning\n");
6604 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6605 mutex_unlock(&priv->mutex);
a0646470 6606 return 0;
b481de9c
ZY
6607 }
6608
6609 spin_lock_irqsave(&priv->lock, flags);
6610
8318d78a
JB
6611 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6612 conf->channel->hw_value);
b481de9c 6613 if (!is_channel_valid(ch_info)) {
66b5004d 6614 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6615 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY
6616 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6617 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY
6618 ret = -EINVAL;
6619 goto out;
b481de9c
ZY
6620 }
6621
8318d78a 6622 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6623
8318d78a 6624 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY
6625
6626 /* The list of supported rates and rate mask can be different
6627 * for each phymode; since the phymode may have changed, reset
6628 * the rate mask to what mac80211 lists */
bb8c093b 6629 iwl3945_set_rate(priv);
b481de9c
ZY
6630
6631 spin_unlock_irqrestore(&priv->lock, flags);
6632
6633#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6634 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6635 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6636 goto out;
b481de9c
ZY
6637 }
6638#endif
6639
bb8c093b 6640 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY
6641
6642 if (!conf->radio_enabled) {
6643 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6644 goto out;
b481de9c
ZY
6645 }
6646
bb8c093b 6647 if (iwl3945_is_rfkill(priv)) {
b481de9c 6648 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY
6649 ret = -EIO;
6650 goto out;
b481de9c
ZY
6651 }
6652
bb8c093b 6653 iwl3945_set_rate(priv);
b481de9c
ZY
6654
6655 if (memcmp(&priv->active_rxon,
6656 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6657 iwl3945_commit_rxon(priv);
b481de9c
ZY
6658 else
6659 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6660
6661 IWL_DEBUG_MAC80211("leave\n");
6662
76bb77e0 6663out:
a0646470 6664 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6665 mutex_unlock(&priv->mutex);
76bb77e0 6666 return ret;
b481de9c
ZY
6667}
6668
bb8c093b 6669static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY
6670{
6671 int rc = 0;
6672
d986bcd1 6673 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
6674 return;
6675
6676 /* The following should be done only at AP bring up */
5d1e2325 6677 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY
6678
6679 /* RXON - unassoc (to set timing command) */
6680 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6681 iwl3945_commit_rxon(priv);
b481de9c
ZY
6682
6683 /* RXON Timing */
28afaf91 6684 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH
6685 iwl3945_setup_rxon_timing(priv);
6686 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6687 sizeof(priv->rxon_timing), &priv->rxon_timing);
6688 if (rc)
6689 IWL_WARNING("REPLY_RXON_TIMING failed - "
6690 "Attempting to continue.\n");
6691
6692 /* FIXME: what should be the assoc_id for AP? */
6693 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6694 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6695 priv->staging_rxon.flags |=
6696 RXON_FLG_SHORT_PREAMBLE_MSK;
6697 else
6698 priv->staging_rxon.flags &=
6699 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6700
6701 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6702 if (priv->assoc_capability &
6703 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6704 priv->staging_rxon.flags |=
6705 RXON_FLG_SHORT_SLOT_MSK;
6706 else
6707 priv->staging_rxon.flags &=
6708 ~RXON_FLG_SHORT_SLOT_MSK;
6709
05c914fe 6710 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
6711 priv->staging_rxon.flags &=
6712 ~RXON_FLG_SHORT_SLOT_MSK;
6713 }
6714 /* restore RXON assoc */
6715 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH
6716 iwl3945_commit_rxon(priv);
6717 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6718 }
bb8c093b 6719 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
6720
6721 /* FIXME - we need to add code here to detect a totally new
6722 * configuration, reset the AP, unassoc, rxon timing, assoc,
6723 * clear sta table, add BCAST sta... */
6724}
6725
32bfd35d
JB
6726static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6727 struct ieee80211_vif *vif,
b481de9c
ZY
6728 struct ieee80211_if_conf *conf)
6729{
bb8c093b 6730 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6731 int rc;
6732
6733 if (conf == NULL)
6734 return -EIO;
6735
b716bb91
EG
6736 if (priv->vif != vif) {
6737 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG
6738 return 0;
6739 }
6740
9d139c81 6741 /* handle this temporarily here */
05c914fe 6742 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB
6743 conf->changed & IEEE80211_IFCC_BEACON) {
6744 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6745 if (!beacon)
6746 return -ENOMEM;
9bdf5eca 6747 mutex_lock(&priv->mutex);
9d139c81 6748 rc = iwl3945_mac_beacon_update(hw, beacon);
9bdf5eca 6749 mutex_unlock(&priv->mutex);
9d139c81
JB
6750 if (rc)
6751 return rc;
6752 }
6753
5a66926a
ZY
6754 if (!iwl3945_is_alive(priv))
6755 return -EAGAIN;
6756
b481de9c
ZY
6757 mutex_lock(&priv->mutex);
6758
b481de9c 6759 if (conf->bssid)
e174961c 6760 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6761
4150c572
JB
6762/*
6763 * very dubious code was here; the probe filtering flag is never set:
6764 *
b481de9c
ZY
6765 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6766 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6767 */
b481de9c 6768
05c914fe 6769 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY
6770 if (!conf->bssid) {
6771 conf->bssid = priv->mac_addr;
6772 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB
6773 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6774 conf->bssid);
b481de9c
ZY
6775 }
6776 if (priv->ibss_beacon)
6777 dev_kfree_skb(priv->ibss_beacon);
6778
9d139c81 6779 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY
6780 }
6781
fde3571f
MA
6782 if (iwl3945_is_rfkill(priv))
6783 goto done;
6784
b481de9c
ZY
6785 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6786 !is_multicast_ether_addr(conf->bssid)) {
6787 /* If there is currently a HW scan going on in the background
6788 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6789 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY
6790 IWL_WARNING("Aborted scan still in progress "
6791 "after 100ms\n");
6792 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6793 mutex_unlock(&priv->mutex);
6794 return -EAGAIN;
6795 }
6796 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6797
6798 /* TODO: Audit driver for usage of these members and see
6799 * if mac80211 deprecates them (priv->bssid looks like it
6800 * shouldn't be there, but I haven't scanned the IBSS code
6801 * to verify) - jpk */
6802 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6803
05c914fe 6804 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6805 iwl3945_config_ap(priv);
b481de9c 6806 else {
bb8c093b 6807 rc = iwl3945_commit_rxon(priv);
05c914fe 6808 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6809 iwl3945_add_station(priv,
556f8db7 6810 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY
6811 }
6812
6813 } else {
bb8c093b 6814 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6815 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6816 iwl3945_commit_rxon(priv);
b481de9c
ZY
6817 }
6818
fde3571f 6819 done:
b481de9c
ZY
6820 IWL_DEBUG_MAC80211("leave\n");
6821 mutex_unlock(&priv->mutex);
6822
6823 return 0;
6824}
6825
bb8c093b 6826static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB
6827 unsigned int changed_flags,
6828 unsigned int *total_flags,
6829 int mc_count, struct dev_addr_list *mc_list)
6830{
5ec03976 6831 struct iwl3945_priv *priv = hw->priv;
352bc8de 6832 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
25b3f57c 6833
352bc8de
ZY
6834 IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
6835 changed_flags, *total_flags);
6836
6837 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
6838 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
6839 *filter_flags |= RXON_FILTER_PROMISC_MSK;
6840 else
6841 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
6842 }
6843 if (changed_flags & FIF_ALLMULTI) {
6844 if (*total_flags & FIF_ALLMULTI)
6845 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
6846 else
6847 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
6848 }
6849 if (changed_flags & FIF_CONTROL) {
6850 if (*total_flags & FIF_CONTROL)
6851 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
6852 else
6853 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
5ec03976 6854 }
352bc8de
ZY
6855 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
6856 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6857 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
6858 else
6859 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
6860 }
6861
6862 /* We avoid iwl_commit_rxon here to commit the new filter flags
6863 * since mac80211 will call ieee80211_hw_config immediately.
6864 * (mc_list is not supported at this time). Otherwise, we need to
6865 * queue a background iwl_commit_rxon work.
6866 */
6867
6868 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
25b3f57c 6869 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB
6870}
6871
bb8c093b 6872static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6873 struct ieee80211_if_init_conf *conf)
6874{
bb8c093b 6875 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
6876
6877 IWL_DEBUG_MAC80211("enter\n");
6878
6879 mutex_lock(&priv->mutex);
6ef89d0a 6880
fde3571f
MA
6881 if (iwl3945_is_ready_rf(priv)) {
6882 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f
MA
6883 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6884 iwl3945_commit_rxon(priv);
6885 }
32bfd35d
JB
6886 if (priv->vif == conf->vif) {
6887 priv->vif = NULL;
b481de9c 6888 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY
6889 }
6890 mutex_unlock(&priv->mutex);
6891
6892 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6893}
6894
cd56d331
AK
6895#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6896
6897static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6898 struct ieee80211_vif *vif,
6899 struct ieee80211_bss_conf *bss_conf,
6900 u32 changes)
6901{
6902 struct iwl3945_priv *priv = hw->priv;
6903
6904 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6905
6906 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6907 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6908 bss_conf->use_short_preamble);
6909 if (bss_conf->use_short_preamble)
6910 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6911 else
6912 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6913 }
6914
6915 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6916 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6917 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
6918 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
6919 else
6920 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
6921 }
6922
6923 if (changes & BSS_CHANGED_ASSOC) {
6924 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6925 /* This should never happen as this function should
6926 * never be called from interrupt context. */
6927 if (WARN_ON_ONCE(in_interrupt()))
6928 return;
6929 if (bss_conf->assoc) {
6930 priv->assoc_id = bss_conf->aid;
6931 priv->beacon_int = bss_conf->beacon_int;
28afaf91 6932 priv->timestamp = bss_conf->timestamp;
cd56d331
AK
6933 priv->assoc_capability = bss_conf->assoc_capability;
6934 priv->next_scan_jiffies = jiffies +
6935 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6936 mutex_lock(&priv->mutex);
6937 iwl3945_post_associate(priv);
6938 mutex_unlock(&priv->mutex);
6939 } else {
6940 priv->assoc_id = 0;
6941 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6942 }
6943 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6944 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6945 iwl3945_send_rxon_assoc(priv);
6946 }
6947
6948}
6949
bb8c093b 6950static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY
6951{
6952 int rc = 0;
6953 unsigned long flags;
bb8c093b 6954 struct iwl3945_priv *priv = hw->priv;
9387b7ca 6955 DECLARE_SSID_BUF(ssid_buf);
b481de9c
ZY
6956
6957 IWL_DEBUG_MAC80211("enter\n");
6958
15e869d8 6959 mutex_lock(&priv->mutex);
b481de9c
ZY
6960 spin_lock_irqsave(&priv->lock, flags);
6961
bb8c093b 6962 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
6963 rc = -EIO;
6964 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6965 goto out_unlock;
6966 }
6967
7878a5a4
MA
6968 /* we don't schedule scan within next_scan_jiffies period */
6969 if (priv->next_scan_jiffies &&
6970 time_after(priv->next_scan_jiffies, jiffies)) {
6971 rc = -EAGAIN;
6972 goto out_unlock;
6973 }
15dbf1b7
BM
6974 /* if we just finished scan ask for delay for a broadcast scan */
6975 if ((len == 0) && priv->last_scan_jiffies &&
6976 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6977 jiffies)) {
b481de9c
ZY
6978 rc = -EAGAIN;
6979 goto out_unlock;
6980 }
6981 if (len) {
7878a5a4 6982 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
9387b7ca 6983 print_ssid(ssid_buf, ssid, len), (int)len);
b481de9c
ZY
6984
6985 priv->one_direct_scan = 1;
6986 priv->direct_ssid_len = (u8)
6987 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6988 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA
6989 } else
6990 priv->one_direct_scan = 0;
b481de9c 6991
bb8c093b 6992 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY
6993
6994 IWL_DEBUG_MAC80211("leave\n");
6995
6996out_unlock:
6997 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 6998 mutex_unlock(&priv->mutex);
b481de9c
ZY
6999
7000 return rc;
7001}
7002
bb8c093b 7003static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY
7004 const u8 *local_addr, const u8 *addr,
7005 struct ieee80211_key_conf *key)
7006{
bb8c093b 7007 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7008 int rc = 0;
7009 u8 sta_id;
7010
7011 IWL_DEBUG_MAC80211("enter\n");
7012
bb8c093b 7013 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY
7014 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7015 return -EOPNOTSUPP;
7016 }
7017
7018 if (is_zero_ether_addr(addr))
7019 /* only support pairwise keys */
7020 return -EOPNOTSUPP;
7021
bb8c093b 7022 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7023 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB
7024 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
7025 addr);
b481de9c
ZY
7026 return -EINVAL;
7027 }
7028
7029 mutex_lock(&priv->mutex);
7030
bb8c093b 7031 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7032
b481de9c
ZY
7033 switch (cmd) {
7034 case SET_KEY:
bb8c093b 7035 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7036 if (!rc) {
bb8c093b
CH
7037 iwl3945_set_rxon_hwcrypto(priv, 1);
7038 iwl3945_commit_rxon(priv);
b481de9c
ZY
7039 key->hw_key_idx = sta_id;
7040 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7041 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7042 }
7043 break;
7044 case DISABLE_KEY:
bb8c093b 7045 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7046 if (!rc) {
bb8c093b
CH
7047 iwl3945_set_rxon_hwcrypto(priv, 0);
7048 iwl3945_commit_rxon(priv);
b481de9c
ZY
7049 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7050 }
7051 break;
7052 default:
7053 rc = -EINVAL;
7054 }
7055
7056 IWL_DEBUG_MAC80211("leave\n");
7057 mutex_unlock(&priv->mutex);
7058
7059 return rc;
7060}
7061
e100bb64 7062static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY
7063 const struct ieee80211_tx_queue_params *params)
7064{
bb8c093b 7065 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7066 unsigned long flags;
7067 int q;
b481de9c
ZY
7068
7069 IWL_DEBUG_MAC80211("enter\n");
7070
bb8c093b 7071 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7072 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7073 return -EIO;
7074 }
7075
7076 if (queue >= AC_NUM) {
7077 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7078 return 0;
7079 }
7080
b481de9c
ZY
7081 q = AC_NUM - 1 - queue;
7082
7083 spin_lock_irqsave(&priv->lock, flags);
7084
7085 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7086 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7087 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7088 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7089 cpu_to_le16((params->txop * 32));
b481de9c
ZY
7090
7091 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7092 priv->qos_data.qos_active = 1;
7093
7094 spin_unlock_irqrestore(&priv->lock, flags);
7095
7096 mutex_lock(&priv->mutex);
05c914fe 7097 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH
7098 iwl3945_activate_qos(priv, 1);
7099 else if (priv->assoc_id && iwl3945_is_associated(priv))
7100 iwl3945_activate_qos(priv, 0);
b481de9c
ZY
7101
7102 mutex_unlock(&priv->mutex);
7103
b481de9c
ZY
7104 IWL_DEBUG_MAC80211("leave\n");
7105 return 0;
7106}
7107
bb8c093b 7108static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7109 struct ieee80211_tx_queue_stats *stats)
7110{
bb8c093b 7111 struct iwl3945_priv *priv = hw->priv;
b481de9c 7112 int i, avail;
bb8c093b
CH
7113 struct iwl3945_tx_queue *txq;
7114 struct iwl3945_queue *q;
b481de9c
ZY
7115 unsigned long flags;
7116
7117 IWL_DEBUG_MAC80211("enter\n");
7118
bb8c093b 7119 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY
7120 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7121 return -EIO;
7122 }
7123
7124 spin_lock_irqsave(&priv->lock, flags);
7125
7126 for (i = 0; i < AC_NUM; i++) {
7127 txq = &priv->txq[i];
7128 q = &txq->q;
bb8c093b 7129 avail = iwl3945_queue_space(q);
b481de9c 7130
57ffc589
JB
7131 stats[i].len = q->n_window - avail;
7132 stats[i].limit = q->n_window - q->high_mark;
7133 stats[i].count = q->n_window;
b481de9c
ZY
7134
7135 }
7136 spin_unlock_irqrestore(&priv->lock, flags);
7137
7138 IWL_DEBUG_MAC80211("leave\n");
7139
7140 return 0;
7141}
7142
bb8c093b 7143static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
7144 struct ieee80211_low_level_stats *stats)
7145{
7146 IWL_DEBUG_MAC80211("enter\n");
7147 IWL_DEBUG_MAC80211("leave\n");
7148
7149 return 0;
7150}
7151
bb8c093b 7152static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7153{
bb8c093b 7154 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7155 unsigned long flags;
7156
7157 mutex_lock(&priv->mutex);
7158 IWL_DEBUG_MAC80211("enter\n");
7159
bb8c093b 7160 iwl3945_reset_qos(priv);
292ae174 7161
b481de9c
ZY
7162 spin_lock_irqsave(&priv->lock, flags);
7163 priv->assoc_id = 0;
7164 priv->assoc_capability = 0;
7165 priv->call_post_assoc_from_beacon = 0;
7166
7167 /* new association get rid of ibss beacon skb */
7168 if (priv->ibss_beacon)
7169 dev_kfree_skb(priv->ibss_beacon);
7170
7171 priv->ibss_beacon = NULL;
7172
7173 priv->beacon_int = priv->hw->conf.beacon_int;
28afaf91 7174 priv->timestamp = 0;
05c914fe 7175 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY
7176 priv->beacon_int = 0;
7177
7178 spin_unlock_irqrestore(&priv->lock, flags);
7179
fde3571f
MA
7180 if (!iwl3945_is_ready_rf(priv)) {
7181 IWL_DEBUG_MAC80211("leave - not ready\n");
7182 mutex_unlock(&priv->mutex);
7183 return;
7184 }
7185
15e869d8
MA
7186 /* we are restarting association process
7187 * clear RXON_FILTER_ASSOC_MSK bit
7188 */
05c914fe 7189 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 7190 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7191 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7192 iwl3945_commit_rxon(priv);
15e869d8
MA
7193 }
7194
b481de9c 7195 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 7196 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 7197
b481de9c
ZY
7198 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7199 mutex_unlock(&priv->mutex);
7200 return;
b481de9c
ZY
7201 }
7202
bb8c093b 7203 iwl3945_set_rate(priv);
b481de9c
ZY
7204
7205 mutex_unlock(&priv->mutex);
7206
7207 IWL_DEBUG_MAC80211("leave\n");
7208
7209}
7210
e039fa4a 7211static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7212{
bb8c093b 7213 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY
7214 unsigned long flags;
7215
b481de9c
ZY
7216 IWL_DEBUG_MAC80211("enter\n");
7217
bb8c093b 7218 if (!iwl3945_is_ready_rf(priv)) {
b481de9c 7219 IWL_DEBUG_MAC80211("leave - RF not ready\n");
b481de9c
ZY
7220 return -EIO;
7221 }
7222
05c914fe 7223 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c 7224 IWL_DEBUG_MAC80211("leave - not IBSS\n");
b481de9c
ZY
7225 return -EIO;
7226 }
7227
7228 spin_lock_irqsave(&priv->lock, flags);
7229
7230 if (priv->ibss_beacon)
7231 dev_kfree_skb(priv->ibss_beacon);
7232
7233 priv->ibss_beacon = skb;
7234
7235 priv->assoc_id = 0;
7236
7237 IWL_DEBUG_MAC80211("leave\n");
7238 spin_unlock_irqrestore(&priv->lock, flags);
7239
bb8c093b 7240 iwl3945_reset_qos(priv);
b481de9c 7241
dc4b1e7d 7242 iwl3945_post_associate(priv);
b481de9c 7243
b481de9c
ZY
7244
7245 return 0;
7246}
7247
7248/*****************************************************************************
7249 *
7250 * sysfs attributes
7251 *
7252 *****************************************************************************/
7253
c8b0e6e1 7254#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
7255
7256/*
7257 * The following adds a new attribute to the sysfs representation
7258 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7259 * used for controlling the debug level.
7260 *
7261 * See the level definitions in iwl for details.
7262 */
7263
7264static ssize_t show_debug_level(struct device_driver *d, char *buf)
7265{
bb8c093b 7266 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY
7267}
7268static ssize_t store_debug_level(struct device_driver *d,
7269 const char *buf, size_t count)
7270{
7271 char *p = (char *)buf;
7272 u32 val;
7273
7274 val = simple_strtoul(p, &p, 0);
7275 if (p == buf)
7276 printk(KERN_INFO DRV_NAME
7277 ": %s is not in hex or decimal form.\n", buf);
7278 else
bb8c093b 7279 iwl3945_debug_level = val;
b481de9c
ZY
7280
7281 return strnlen(buf, count);
7282}
7283
7284static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7285 show_debug_level, store_debug_level);
7286
c8b0e6e1 7287#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7288
b481de9c
ZY
7289static ssize_t show_temperature(struct device *d,
7290 struct device_attribute *attr, char *buf)
7291{
bb8c093b 7292 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7293
bb8c093b 7294 if (!iwl3945_is_alive(priv))
b481de9c
ZY
7295 return -EAGAIN;
7296
bb8c093b 7297 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
7298}
7299
7300static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7301
b481de9c
ZY
7302static ssize_t show_tx_power(struct device *d,
7303 struct device_attribute *attr, char *buf)
7304{
bb8c093b 7305 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7306 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7307}
7308
7309static ssize_t store_tx_power(struct device *d,
7310 struct device_attribute *attr,
7311 const char *buf, size_t count)
7312{
bb8c093b 7313 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7314 char *p = (char *)buf;
7315 u32 val;
7316
7317 val = simple_strtoul(p, &p, 10);
7318 if (p == buf)
7319 printk(KERN_INFO DRV_NAME
7320 ": %s is not in decimal form.\n", buf);
7321 else
bb8c093b 7322 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
7323
7324 return count;
7325}
7326
7327static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7328
7329static ssize_t show_flags(struct device *d,
7330 struct device_attribute *attr, char *buf)
7331{
bb8c093b 7332 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7333
7334 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7335}
7336
7337static ssize_t store_flags(struct device *d,
7338 struct device_attribute *attr,
7339 const char *buf, size_t count)
7340{
bb8c093b 7341 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7342 u32 flags = simple_strtoul(buf, NULL, 0);
7343
7344 mutex_lock(&priv->mutex);
7345 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7346 /* Cancel any currently running scans... */
bb8c093b 7347 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7348 IWL_WARNING("Could not cancel scan.\n");
7349 else {
7350 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7351 flags);
7352 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7353 iwl3945_commit_rxon(priv);
b481de9c
ZY
7354 }
7355 }
7356 mutex_unlock(&priv->mutex);
7357
7358 return count;
7359}
7360
7361static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7362
7363static ssize_t show_filter_flags(struct device *d,
7364 struct device_attribute *attr, char *buf)
7365{
bb8c093b 7366 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7367
7368 return sprintf(buf, "0x%04X\n",
7369 le32_to_cpu(priv->active_rxon.filter_flags));
7370}
7371
7372static ssize_t store_filter_flags(struct device *d,
7373 struct device_attribute *attr,
7374 const char *buf, size_t count)
7375{
bb8c093b 7376 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY
7377 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7378
7379 mutex_lock(&priv->mutex);
7380 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7381 /* Cancel any currently running scans... */
bb8c093b 7382 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY
7383 IWL_WARNING("Could not cancel scan.\n");
7384 else {
7385 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7386 "0x%04X\n", filter_flags);
7387 priv->staging_rxon.filter_flags =
7388 cpu_to_le32(filter_flags);
bb8c093b 7389 iwl3945_commit_rxon(priv);
b481de9c
ZY
7390 }
7391 }
7392 mutex_unlock(&priv->mutex);
7393
7394 return count;
7395}
7396
7397static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7398 store_filter_flags);
7399
c8b0e6e1 7400#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7401
7402static ssize_t show_measurement(struct device *d,
7403 struct device_attribute *attr, char *buf)
7404{
bb8c093b 7405 struct iwl3945_priv *priv = dev_get_drvdata(d);
600c0e11 7406 struct iwl_spectrum_notification measure_report;
b481de9c 7407 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7408 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
7409 unsigned long flags;
7410
7411 spin_lock_irqsave(&priv->lock, flags);
7412 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7413 spin_unlock_irqrestore(&priv->lock, flags);
7414 return 0;
7415 }
7416 memcpy(&measure_report, &priv->measure_report, size);
7417 priv->measurement_status = 0;
7418 spin_unlock_irqrestore(&priv->lock, flags);
7419
7420 while (size && (PAGE_SIZE - len)) {
7421 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7422 PAGE_SIZE - len, 1);
7423 len = strlen(buf);
7424 if (PAGE_SIZE - len)
7425 buf[len++] = '\n';
7426
7427 ofs += 16;
7428 size -= min(size, 16U);
7429 }
7430
7431 return len;
7432}
7433
7434static ssize_t store_measurement(struct device *d,
7435 struct device_attribute *attr,
7436 const char *buf, size_t count)
7437{
bb8c093b 7438 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7439 struct ieee80211_measurement_params params = {
7440 .channel = le16_to_cpu(priv->active_rxon.channel),
7441 .start_time = cpu_to_le64(priv->last_tsf),
7442 .duration = cpu_to_le16(1),
7443 };
7444 u8 type = IWL_MEASURE_BASIC;
7445 u8 buffer[32];
7446 u8 channel;
7447
7448 if (count) {
7449 char *p = buffer;
7450 strncpy(buffer, buf, min(sizeof(buffer), count));
7451 channel = simple_strtoul(p, NULL, 0);
7452 if (channel)
7453 params.channel = channel;
7454
7455 p = buffer;
7456 while (*p && *p != ' ')
7457 p++;
7458 if (*p)
7459 type = simple_strtoul(p + 1, NULL, 0);
7460 }
7461
7462 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7463 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7464 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
7465
7466 return count;
7467}
7468
7469static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7470 show_measurement, store_measurement);
c8b0e6e1 7471#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7472
b481de9c
ZY
7473static ssize_t store_retry_rate(struct device *d,
7474 struct device_attribute *attr,
7475 const char *buf, size_t count)
7476{
bb8c093b 7477 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7478
7479 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7480 if (priv->retry_rate <= 0)
7481 priv->retry_rate = 1;
7482
7483 return count;
7484}
7485
7486static ssize_t show_retry_rate(struct device *d,
7487 struct device_attribute *attr, char *buf)
7488{
bb8c093b 7489 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7490 return sprintf(buf, "%d", priv->retry_rate);
7491}
7492
7493static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7494 store_retry_rate);
7495
7496static ssize_t store_power_level(struct device *d,
7497 struct device_attribute *attr,
7498 const char *buf, size_t count)
7499{
bb8c093b 7500 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7501 int rc;
7502 int mode;
7503
7504 mode = simple_strtoul(buf, NULL, 0);
7505 mutex_lock(&priv->mutex);
7506
bb8c093b 7507 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY
7508 rc = -EAGAIN;
7509 goto out;
7510 }
7511
7512 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7513 mode = IWL_POWER_AC;
7514 else
7515 mode |= IWL_POWER_ENABLED;
7516
7517 if (mode != priv->power_mode) {
bb8c093b 7518 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY
7519 if (rc) {
7520 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7521 goto out;
7522 }
7523 priv->power_mode = mode;
7524 }
7525
7526 rc = count;
7527
7528 out:
7529 mutex_unlock(&priv->mutex);
7530 return rc;
7531}
7532
7533#define MAX_WX_STRING 80
7534
7535/* Values are in microsecond */
7536static const s32 timeout_duration[] = {
7537 350000,
7538 250000,
7539 75000,
7540 37000,
7541 25000,
7542};
7543static const s32 period_duration[] = {
7544 400000,
7545 700000,
7546 1000000,
7547 1000000,
7548 1000000
7549};
7550
7551static ssize_t show_power_level(struct device *d,
7552 struct device_attribute *attr, char *buf)
7553{
bb8c093b 7554 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7555 int level = IWL_POWER_LEVEL(priv->power_mode);
7556 char *p = buf;
7557
7558 p += sprintf(p, "%d ", level);
7559 switch (level) {
7560 case IWL_POWER_MODE_CAM:
7561 case IWL_POWER_AC:
7562 p += sprintf(p, "(AC)");
7563 break;
7564 case IWL_POWER_BATTERY:
7565 p += sprintf(p, "(BATTERY)");
7566 break;
7567 default:
7568 p += sprintf(p,
7569 "(Timeout %dms, Period %dms)",
7570 timeout_duration[level - 1] / 1000,
7571 period_duration[level - 1] / 1000);
7572 }
7573
7574 if (!(priv->power_mode & IWL_POWER_ENABLED))
7575 p += sprintf(p, " OFF\n");
7576 else
7577 p += sprintf(p, " \n");
7578
3ac7f146 7579 return p - buf + 1;
b481de9c
ZY
7580
7581}
7582
7583static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7584 store_power_level);
7585
7586static ssize_t show_channels(struct device *d,
7587 struct device_attribute *attr, char *buf)
7588{
8318d78a
JB
7589 /* all this shit doesn't belong into sysfs anyway */
7590 return 0;
b481de9c
ZY
7591}
7592
7593static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7594
7595static ssize_t show_statistics(struct device *d,
7596 struct device_attribute *attr, char *buf)
7597{
bb8c093b
CH
7598 struct iwl3945_priv *priv = dev_get_drvdata(d);
7599 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7600 u32 len = 0, ofs = 0;
3ac7f146 7601 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
7602 int rc = 0;
7603
bb8c093b 7604 if (!iwl3945_is_alive(priv))
b481de9c
ZY
7605 return -EAGAIN;
7606
7607 mutex_lock(&priv->mutex);
bb8c093b 7608 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY
7609 mutex_unlock(&priv->mutex);
7610
7611 if (rc) {
7612 len = sprintf(buf,
7613 "Error sending statistics request: 0x%08X\n", rc);
7614 return len;
7615 }
7616
7617 while (size && (PAGE_SIZE - len)) {
7618 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7619 PAGE_SIZE - len, 1);
7620 len = strlen(buf);
7621 if (PAGE_SIZE - len)
7622 buf[len++] = '\n';
7623
7624 ofs += 16;
7625 size -= min(size, 16U);
7626 }
7627
7628 return len;
7629}
7630
7631static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7632
7633static ssize_t show_antenna(struct device *d,
7634 struct device_attribute *attr, char *buf)
7635{
bb8c093b 7636 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7637
bb8c093b 7638 if (!iwl3945_is_alive(priv))
b481de9c
ZY
7639 return -EAGAIN;
7640
7641 return sprintf(buf, "%d\n", priv->antenna);
7642}
7643
7644static ssize_t store_antenna(struct device *d,
7645 struct device_attribute *attr,
7646 const char *buf, size_t count)
7647{
7648 int ant;
bb8c093b 7649 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7650
7651 if (count == 0)
7652 return 0;
7653
7654 if (sscanf(buf, "%1i", &ant) != 1) {
7655 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7656 return count;
7657 }
7658
7659 if ((ant >= 0) && (ant <= 2)) {
7660 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7661 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY
7662 } else
7663 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7664
7665
7666 return count;
7667}
7668
7669static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7670
7671static ssize_t show_status(struct device *d,
7672 struct device_attribute *attr, char *buf)
7673{
bb8c093b
CH
7674 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7675 if (!iwl3945_is_alive(priv))
b481de9c
ZY
7676 return -EAGAIN;
7677 return sprintf(buf, "0x%08x\n", (int)priv->status);
7678}
7679
7680static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7681
7682static ssize_t dump_error_log(struct device *d,
7683 struct device_attribute *attr,
7684 const char *buf, size_t count)
7685{
7686 char *p = (char *)buf;
7687
7688 if (p[0] == '1')
bb8c093b 7689 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY
7690
7691 return strnlen(buf, count);
7692}
7693
7694static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7695
7696static ssize_t dump_event_log(struct device *d,
7697 struct device_attribute *attr,
7698 const char *buf, size_t count)
7699{
7700 char *p = (char *)buf;
7701
7702 if (p[0] == '1')
bb8c093b 7703 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY
7704
7705 return strnlen(buf, count);
7706}
7707
7708static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7709
7710/*****************************************************************************
7711 *
a96a27f9 7712 * driver setup and tear down
b481de9c
ZY
7713 *
7714 *****************************************************************************/
7715
bb8c093b 7716static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY
7717{
7718 priv->workqueue = create_workqueue(DRV_NAME);
7719
7720 init_waitqueue_head(&priv->wait_command_queue);
7721
bb8c093b
CH
7722 INIT_WORK(&priv->up, iwl3945_bg_up);
7723 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7724 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7725 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7726 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7727 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7728 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7729 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
7730 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7731 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7732 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7733
7734 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
7735
7736 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7737 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
7738}
7739
bb8c093b 7740static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7741{
bb8c093b 7742 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7743
e47eb6ad 7744 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
7745 cancel_delayed_work(&priv->scan_check);
7746 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
7747 cancel_work_sync(&priv->beacon_update);
7748}
7749
bb8c093b 7750static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
7751 &dev_attr_antenna.attr,
7752 &dev_attr_channels.attr,
7753 &dev_attr_dump_errors.attr,
7754 &dev_attr_dump_events.attr,
7755 &dev_attr_flags.attr,
7756 &dev_attr_filter_flags.attr,
c8b0e6e1 7757#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7758 &dev_attr_measurement.attr,
7759#endif
7760 &dev_attr_power_level.attr,
b481de9c 7761 &dev_attr_retry_rate.attr,
b481de9c
ZY
7762 &dev_attr_statistics.attr,
7763 &dev_attr_status.attr,
7764 &dev_attr_temperature.attr,
b481de9c
ZY
7765 &dev_attr_tx_power.attr,
7766
7767 NULL
7768};
7769
bb8c093b 7770static struct attribute_group iwl3945_attribute_group = {
b481de9c 7771 .name = NULL, /* put in device directory */
bb8c093b 7772 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
7773};
7774
bb8c093b
CH
7775static struct ieee80211_ops iwl3945_hw_ops = {
7776 .tx = iwl3945_mac_tx,
7777 .start = iwl3945_mac_start,
7778 .stop = iwl3945_mac_stop,
7779 .add_interface = iwl3945_mac_add_interface,
7780 .remove_interface = iwl3945_mac_remove_interface,
7781 .config = iwl3945_mac_config,
7782 .config_interface = iwl3945_mac_config_interface,
7783 .configure_filter = iwl3945_configure_filter,
7784 .set_key = iwl3945_mac_set_key,
7785 .get_stats = iwl3945_mac_get_stats,
7786 .get_tx_stats = iwl3945_mac_get_tx_stats,
7787 .conf_tx = iwl3945_mac_conf_tx,
bb8c093b 7788 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7789 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7790 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY
7791};
7792
bb8c093b 7793static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
7794{
7795 int err = 0;
bb8c093b 7796 struct iwl3945_priv *priv;
b481de9c 7797 struct ieee80211_hw *hw;
82b9a121 7798 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
0359facc 7799 unsigned long flags;
b481de9c 7800
cee53ddb
KA
7801 /***********************
7802 * 1. Allocating HW data
7803 * ********************/
7804
6440adb5
BC
7805 /* Disabling hardware scan means that mac80211 will perform scans
7806 * "the hard way", rather than using device's scan. */
bb8c093b 7807 if (iwl3945_param_disable_hw_scan) {
b481de9c 7808 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7809 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY
7810 }
7811
dfe7d458 7812 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7813 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7814 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7815 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY
7816 err = -EINVAL;
7817 goto out;
7818 }
7819
7820 /* mac80211 allocates memory for this device instance, including
7821 * space for this driver's private structure */
bb8c093b 7822 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY
7823 if (hw == NULL) {
7824 IWL_ERROR("Can not allocate network device\n");
7825 err = -ENOMEM;
7826 goto out;
7827 }
b481de9c 7828
cee53ddb 7829 SET_IEEE80211_DEV(hw, &pdev->dev);
f51359a8 7830
b481de9c
ZY
7831 priv = hw->priv;
7832 priv->hw = hw;
b481de9c 7833 priv->pci_dev = pdev;
82b9a121 7834 priv->cfg = cfg;
6440adb5 7835
cee53ddb
KA
7836 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7837 hw->rate_control_algorithm = "iwl-3945-rs";
7838 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
7839
6440adb5 7840 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7841 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7842#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7843 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY
7844 atomic_set(&priv->restrict_refcnt, 0);
7845#endif
b481de9c 7846
566bfe5a 7847 /* Tell mac80211 our characteristics */
605a0bd6 7848 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7849 IEEE80211_HW_NOISE_DBM;
b481de9c 7850
f59ac048 7851 hw->wiphy->interface_modes =
f59ac048
LR
7852 BIT(NL80211_IFTYPE_STATION) |
7853 BIT(NL80211_IFTYPE_ADHOC);
7854
ea4a82dc
LR
7855 hw->wiphy->fw_handles_regulatory = true;
7856
6440adb5 7857 /* 4 EDCA QOS priorities */
b481de9c
ZY
7858 hw->queues = 4;
7859
cee53ddb
KA
7860 /***************************
7861 * 2. Initializing PCI bus
7862 * *************************/
b481de9c
ZY
7863 if (pci_enable_device(pdev)) {
7864 err = -ENODEV;
7865 goto out_ieee80211_free_hw;
7866 }
7867
7868 pci_set_master(pdev);
7869
b481de9c
ZY
7870 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7871 if (!err)
7872 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7873 if (err) {
7874 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
7875 goto out_pci_disable_device;
7876 }
7877
7878 pci_set_drvdata(pdev, priv);
7879 err = pci_request_regions(pdev, DRV_NAME);
7880 if (err)
7881 goto out_pci_disable_device;
6440adb5 7882
cee53ddb
KA
7883 /***********************
7884 * 3. Read REV Register
7885 * ********************/
b481de9c
ZY
7886 priv->hw_base = pci_iomap(pdev, 0, 0);
7887 if (!priv->hw_base) {
7888 err = -ENODEV;
7889 goto out_pci_release_regions;
7890 }
7891
7892 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7893 (unsigned long long) pci_resource_len(pdev, 0));
7894 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7895
cee53ddb
KA
7896 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7897 * PCI Tx retries from interfering with C3 CPU state */
7898 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 7899
cee53ddb
KA
7900 /* nic init */
7901 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
7902 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 7903
cee53ddb 7904 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
73d7b5ac
ZY
7905 err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
7906 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
cee53ddb
KA
7907 if (err < 0) {
7908 IWL_DEBUG_INFO("Failed to init the card\n");
7909 goto out_remove_sysfs;
7910 }
b481de9c 7911
cee53ddb
KA
7912 /***********************
7913 * 4. Read EEPROM
7914 * ********************/
7915 /* Read the EEPROM */
7916 err = iwl3945_eeprom_init(priv);
7917 if (err) {
7918 IWL_ERROR("Unable to init EEPROM\n");
7919 goto out_remove_sysfs;
7920 }
7921 /* MAC Address location in EEPROM same for 3945/4965 */
7922 get_eeprom_mac(priv, priv->mac_addr);
7923 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
7924 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7925
cee53ddb
KA
7926 /***********************
7927 * 5. Setup HW Constants
7928 * ********************/
b481de9c 7929 /* Device-specific setup */
bb8c093b 7930 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 7931 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY
7932 goto out_iounmap;
7933 }
7934
cee53ddb
KA
7935 /***********************
7936 * 6. Setup priv
7937 * ********************/
7938 priv->retry_rate = 1;
7939 priv->ibss_beacon = NULL;
7940
7941 spin_lock_init(&priv->lock);
7942 spin_lock_init(&priv->power_data.lock);
7943 spin_lock_init(&priv->sta_lock);
7944 spin_lock_init(&priv->hcmd_lock);
7945
7946 INIT_LIST_HEAD(&priv->free_frames);
7947 mutex_init(&priv->mutex);
7948
7949 /* Clear the driver's (not device's) station table */
7950 iwl3945_clear_stations_table(priv);
7951
7952 priv->data_retry_limit = -1;
7953 priv->ieee_channels = NULL;
7954 priv->ieee_rates = NULL;
7955 priv->band = IEEE80211_BAND_2GHZ;
7956
7957 priv->iw_mode = NL80211_IFTYPE_STATION;
7958
bb8c093b 7959 iwl3945_reset_qos(priv);
b481de9c
ZY
7960
7961 priv->qos_data.qos_active = 0;
7962 priv->qos_data.qos_cap.val = 0;
b481de9c 7963
b481de9c
ZY
7964
7965 priv->rates_mask = IWL_RATES_MASK;
7966 /* If power management is turned on, default to AC mode */
7967 priv->power_mode = IWL_POWER_AC;
7968 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7969
cee53ddb 7970 err = iwl3945_init_channel_map(priv);
b481de9c 7971 if (err) {
cee53ddb 7972 IWL_ERROR("initializing regulatory failed: %d\n", err);
b481de9c
ZY
7973 goto out_release_irq;
7974 }
7975
cee53ddb 7976 err = iwl3945_init_geos(priv);
b481de9c 7977 if (err) {
cee53ddb
KA
7978 IWL_ERROR("initializing geos failed: %d\n", err);
7979 goto out_free_channel_map;
b481de9c
ZY
7980 }
7981
cee53ddb
KA
7982 printk(KERN_INFO DRV_NAME
7983 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
7984
7985 /***********************************
7986 * 7. Initialize Module Parameters
7987 * **********************************/
7988
7989 /* Initialize module parameter values here */
7990 /* Disable radio (SW RF KILL) via parameter when loading driver */
7991 if (iwl3945_param_disable) {
7992 set_bit(STATUS_RF_KILL_SW, &priv->status);
7993 IWL_DEBUG_INFO("Radio disabled.\n");
849e0dce
RC
7994 }
7995
cee53ddb
KA
7996
7997 /***********************
7998 * 8. Setup Services
7999 * ********************/
8000
8001 spin_lock_irqsave(&priv->lock, flags);
8002 iwl3945_disable_interrupts(priv);
8003 spin_unlock_irqrestore(&priv->lock, flags);
8004
8005 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 8006 if (err) {
cee53ddb
KA
8007 IWL_ERROR("failed to create sysfs device attributes\n");
8008 goto out_free_geos;
849e0dce 8009 }
849e0dce 8010
cee53ddb
KA
8011 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
8012 iwl3945_setup_deferred_work(priv);
8013 iwl3945_setup_rx_handlers(priv);
8014
8015 /***********************
8016 * 9. Conclude
8017 * ********************/
8018 pci_save_state(pdev);
8019 pci_disable_device(pdev);
8020
8021 /*********************************
8022 * 10. Setup and Register mac80211
8023 * *******************************/
8024
5a66926a
ZY
8025 err = ieee80211_register_hw(priv->hw);
8026 if (err) {
8027 IWL_ERROR("Failed to register network device (error %d)\n", err);
cee53ddb 8028 goto out_remove_sysfs;
5a66926a 8029 }
b481de9c 8030
5a66926a
ZY
8031 priv->hw->conf.beacon_int = 100;
8032 priv->mac80211_registered = 1;
cee53ddb 8033
b481de9c 8034
ebef2008
AK
8035 err = iwl3945_rfkill_init(priv);
8036 if (err)
8037 IWL_ERROR("Unable to initialize RFKILL system. "
8038 "Ignoring error: %d\n", err);
8039
b481de9c
ZY
8040 return 0;
8041
cee53ddb
KA
8042 out_remove_sysfs:
8043 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce
RC
8044 out_free_geos:
8045 iwl3945_free_geos(priv);
8046 out_free_channel_map:
8047 iwl3945_free_channel_map(priv);
cee53ddb 8048
b481de9c
ZY
8049
8050 out_release_irq:
b481de9c
ZY
8051 destroy_workqueue(priv->workqueue);
8052 priv->workqueue = NULL;
bb8c093b 8053 iwl3945_unset_hw_setting(priv);
b481de9c
ZY
8054
8055 out_iounmap:
8056 pci_iounmap(pdev, priv->hw_base);
8057 out_pci_release_regions:
8058 pci_release_regions(pdev);
8059 out_pci_disable_device:
8060 pci_disable_device(pdev);
8061 pci_set_drvdata(pdev, NULL);
8062 out_ieee80211_free_hw:
8063 ieee80211_free_hw(priv->hw);
8064 out:
8065 return err;
8066}
8067
c83dbf68 8068static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8069{
bb8c093b 8070 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
0359facc 8071 unsigned long flags;
b481de9c
ZY
8072
8073 if (!priv)
8074 return;
8075
8076 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8077
b481de9c 8078 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8079
bb8c093b 8080 iwl3945_down(priv);
b481de9c 8081
0359facc
MA
8082 /* make sure we flush any pending irq or
8083 * tasklet for the driver
8084 */
8085 spin_lock_irqsave(&priv->lock, flags);
8086 iwl3945_disable_interrupts(priv);
8087 spin_unlock_irqrestore(&priv->lock, flags);
8088
8089 iwl_synchronize_irq(priv);
8090
bb8c093b 8091 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8092
ebef2008 8093 iwl3945_rfkill_unregister(priv);
bb8c093b 8094 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
8095
8096 if (priv->rxq.bd)
bb8c093b
CH
8097 iwl3945_rx_queue_free(priv, &priv->rxq);
8098 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8099
bb8c093b
CH
8100 iwl3945_unset_hw_setting(priv);
8101 iwl3945_clear_stations_table(priv);
b481de9c 8102
3ac7f146 8103 if (priv->mac80211_registered)
b481de9c 8104 ieee80211_unregister_hw(priv->hw);
b481de9c 8105
6ef89d0a
MA
8106 /*netif_stop_queue(dev); */
8107 flush_workqueue(priv->workqueue);
8108
bb8c093b 8109 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
8110 * priv->workqueue... so we can't take down the workqueue
8111 * until now... */
8112 destroy_workqueue(priv->workqueue);
8113 priv->workqueue = NULL;
8114
b481de9c
ZY
8115 pci_iounmap(pdev, priv->hw_base);
8116 pci_release_regions(pdev);
8117 pci_disable_device(pdev);
8118 pci_set_drvdata(pdev, NULL);
8119
849e0dce
RC
8120 iwl3945_free_channel_map(priv);
8121 iwl3945_free_geos(priv);
261415f7 8122 kfree(priv->scan);
b481de9c
ZY
8123 if (priv->ibss_beacon)
8124 dev_kfree_skb(priv->ibss_beacon);
8125
8126 ieee80211_free_hw(priv->hw);
8127}
8128
8129#ifdef CONFIG_PM
8130
bb8c093b 8131static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8132{
bb8c093b 8133 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8134
e655b9f0
ZY
8135 if (priv->is_open) {
8136 set_bit(STATUS_IN_SUSPEND, &priv->status);
8137 iwl3945_mac_stop(priv->hw);
8138 priv->is_open = 1;
8139 }
b481de9c 8140
b481de9c
ZY
8141 pci_set_power_state(pdev, PCI_D3hot);
8142
b481de9c
ZY
8143 return 0;
8144}
8145
bb8c093b 8146static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8147{
bb8c093b 8148 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8149
b481de9c 8150 pci_set_power_state(pdev, PCI_D0);
b481de9c 8151
e655b9f0
ZY
8152 if (priv->is_open)
8153 iwl3945_mac_start(priv->hw);
b481de9c 8154
e655b9f0 8155 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY
8156 return 0;
8157}
8158
8159#endif /* CONFIG_PM */
8160
ebef2008 8161/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8162#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK
8163/* software rf-kill from user */
8164static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8165{
8166 struct iwl3945_priv *priv = data;
8167 int err = 0;
8168
80fcc9e2 8169 if (!priv->rfkill)
ebef2008
AK
8170 return 0;
8171
8172 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8173 return 0;
8174
a96a27f9 8175 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
ebef2008
AK
8176 mutex_lock(&priv->mutex);
8177
8178 switch (state) {
acdfe9b4 8179 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8180 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8181 err = -EBUSY;
80fcc9e2
AG
8182 goto out_unlock;
8183 }
8184 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8185 break;
acdfe9b4 8186 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8187 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8188 break;
acdfe9b4 8189 default:
a96a27f9 8190 IWL_WARNING("we received unexpected RFKILL state %d\n", state);
acdfe9b4 8191 break;
ebef2008 8192 }
80fcc9e2 8193out_unlock:
ebef2008
AK
8194 mutex_unlock(&priv->mutex);
8195
8196 return err;
8197}
8198
8199int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8200{
8201 struct device *device = wiphy_dev(priv->hw->wiphy);
8202 int ret = 0;
8203
8204 BUG_ON(device == NULL);
8205
8206 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG
8207 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8208 if (!priv->rfkill) {
ebef2008
AK
8209 IWL_ERROR("Unable to allocate rfkill device.\n");
8210 ret = -ENOMEM;
8211 goto error;
8212 }
8213
80fcc9e2
AG
8214 priv->rfkill->name = priv->cfg->name;
8215 priv->rfkill->data = priv;
8216 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8217 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8218 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8219
80fcc9e2
AG
8220 priv->rfkill->dev.class->suspend = NULL;
8221 priv->rfkill->dev.class->resume = NULL;
ebef2008 8222
80fcc9e2 8223 ret = rfkill_register(priv->rfkill);
ebef2008
AK
8224 if (ret) {
8225 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8226 goto freed_rfkill;
ebef2008
AK
8227 }
8228
8229 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8230 return ret;
8231
ebef2008 8232freed_rfkill:
80fcc9e2
AG
8233 if (priv->rfkill != NULL)
8234 rfkill_free(priv->rfkill);
8235 priv->rfkill = NULL;
ebef2008
AK
8236
8237error:
8238 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8239 return ret;
8240}
8241
8242void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8243{
80fcc9e2
AG
8244 if (priv->rfkill)
8245 rfkill_unregister(priv->rfkill);
ebef2008 8246
80fcc9e2 8247 priv->rfkill = NULL;
ebef2008
AK
8248}
8249
8250/* set rf-kill to the right state. */
8251void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8252{
8253
80fcc9e2
AG
8254 if (!priv->rfkill)
8255 return;
8256
8257 if (iwl3945_is_rfkill_hw(priv)) {
8258 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8259 return;
80fcc9e2 8260 }
ebef2008 8261
80fcc9e2
AG
8262 if (!iwl3945_is_rfkill_sw(priv))
8263 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8264 else
80fcc9e2 8265 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK
8266}
8267#endif
8268
b481de9c
ZY
8269/*****************************************************************************
8270 *
8271 * driver and module entry point
8272 *
8273 *****************************************************************************/
8274
bb8c093b 8275static struct pci_driver iwl3945_driver = {
b481de9c 8276 .name = DRV_NAME,
bb8c093b
CH
8277 .id_table = iwl3945_hw_card_ids,
8278 .probe = iwl3945_pci_probe,
8279 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8280#ifdef CONFIG_PM
bb8c093b
CH
8281 .suspend = iwl3945_pci_suspend,
8282 .resume = iwl3945_pci_resume,
b481de9c
ZY
8283#endif
8284};
8285
bb8c093b 8286static int __init iwl3945_init(void)
b481de9c
ZY
8287{
8288
8289 int ret;
8290 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8291 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
8292
8293 ret = iwl3945_rate_control_register();
8294 if (ret) {
8295 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8296 return ret;
8297 }
8298
bb8c093b 8299 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY
8300 if (ret) {
8301 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8302 goto error_register;
b481de9c 8303 }
c8b0e6e1 8304#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8305 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY
8306 if (ret) {
8307 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8308 goto error_debug;
b481de9c
ZY
8309 }
8310#endif
8311
8312 return ret;
897e1cf2
RC
8313
8314#ifdef CONFIG_IWL3945_DEBUG
8315error_debug:
8316 pci_unregister_driver(&iwl3945_driver);
8317#endif
8318error_register:
8319 iwl3945_rate_control_unregister();
8320 return ret;
b481de9c
ZY
8321}
8322
bb8c093b 8323static void __exit iwl3945_exit(void)
b481de9c 8324{
c8b0e6e1 8325#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8326 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8327#endif
bb8c093b 8328 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8329 iwl3945_rate_control_unregister();
b481de9c
ZY
8330}
8331
a0987a8d 8332MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 8333
bb8c093b 8334module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8335MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8336module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8337MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8338module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY
8339MODULE_PARM_DESC(hwcrypto,
8340 "using hardware crypto engine (default 0 [software])\n");
95aa194a 8341module_param_named(debug, iwl3945_param_debug, uint, 0444);
b481de9c 8342MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8343module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY
8344MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8345
bb8c093b 8346module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY
8347MODULE_PARM_DESC(queues_num, "number of hw queues.");
8348
bb8c093b
CH
8349module_exit(iwl3945_exit);
8350module_init(iwl3945_init);