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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
d43c36dc | 36 | #include <linux/sched.h> |
b481de9c ZY |
37 | #include <linux/skbuff.h> |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
44 | #include <net/ieee80211_radiotap.h> | |
45 | #include <net/mac80211.h> | |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwl3945" |
50 | ||
dbb6654c WT |
51 | #include "iwl-fh.h" |
52 | #include "iwl-3945-fh.h" | |
600c0e11 | 53 | #include "iwl-commands.h" |
17f841cd | 54 | #include "iwl-sta.h" |
b481de9c ZY |
55 | #include "iwl-3945.h" |
56 | #include "iwl-helpers.h" | |
5747d47f | 57 | #include "iwl-core.h" |
d20b3c65 | 58 | #include "iwl-dev.h" |
b481de9c | 59 | |
b481de9c ZY |
60 | /* |
61 | * module name, copyright, version, etc. | |
b481de9c ZY |
62 | */ |
63 | ||
64 | #define DRV_DESCRIPTION \ | |
65 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
66 | ||
d08853a3 | 67 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
68 | #define VD "d" |
69 | #else | |
70 | #define VD | |
71 | #endif | |
72 | ||
c8b0e6e1 | 73 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
74 | #define VS "s" |
75 | #else | |
76 | #define VS | |
77 | #endif | |
78 | ||
250cce26 | 79 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
1f447808 | 80 | #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation" |
a7b75207 | 81 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
b481de9c ZY |
82 | |
83 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
84 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 85 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
86 | MODULE_LICENSE("GPL"); |
87 | ||
df878d8f KA |
88 | /* module parameters */ |
89 | struct iwl_mod_params iwl3945_mod_params = { | |
9c74d9fb | 90 | .sw_crypto = 1, |
af48d048 | 91 | .restart_fw = 1, |
df878d8f KA |
92 | /* the rest are 0 by default */ |
93 | }; | |
94 | ||
7e4bca5e SO |
95 | /** |
96 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
97 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
98 | * | |
99 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed | |
100 | * iwl3945_mod_params.antenna specifies the antenna diversity mode: | |
101 | * | |
102 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself | |
103 | * IWL_ANTENNA_MAIN - Force MAIN antenna | |
104 | * IWL_ANTENNA_AUX - Force AUX antenna | |
105 | */ | |
106 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |
107 | { | |
108 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; | |
109 | ||
110 | switch (iwl3945_mod_params.antenna) { | |
111 | case IWL_ANTENNA_DIVERSITY: | |
112 | return 0; | |
113 | ||
114 | case IWL_ANTENNA_MAIN: | |
115 | if (eeprom->antenna_switch_type) | |
116 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
117 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
118 | ||
119 | case IWL_ANTENNA_AUX: | |
120 | if (eeprom->antenna_switch_type) | |
121 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
122 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
123 | } | |
124 | ||
125 | /* bad antenna selector value */ | |
126 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", | |
127 | iwl3945_mod_params.antenna); | |
128 | ||
129 | return 0; /* "diversity" is default if error */ | |
130 | } | |
131 | ||
6e21f15c | 132 | static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
133 | struct ieee80211_key_conf *keyconf, |
134 | u8 sta_id) | |
135 | { | |
136 | unsigned long flags; | |
137 | __le16 key_flags = 0; | |
6e21f15c AK |
138 | int ret; |
139 | ||
140 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
141 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
142 | ||
143 | if (sta_id == priv->hw_params.bcast_sta_id) | |
144 | key_flags |= STA_KEY_MULTICAST_MSK; | |
145 | ||
146 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
147 | keyconf->hw_key_idx = keyconf->keyidx; | |
148 | key_flags &= ~STA_KEY_FLG_INVALID; | |
b481de9c | 149 | |
b481de9c | 150 | spin_lock_irqsave(&priv->sta_lock, flags); |
c587de0b TW |
151 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; |
152 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
153 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
154 | keyconf->keylen); |
155 | ||
c587de0b | 156 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, |
b481de9c | 157 | keyconf->keylen); |
6e21f15c | 158 | |
c587de0b | 159 | if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
6e21f15c | 160 | == STA_KEY_FLG_NO_ENC) |
c587de0b | 161 | priv->stations[sta_id].sta.key.key_offset = |
6e21f15c AK |
162 | iwl_get_free_ucode_key_index(priv); |
163 | /* else, we are overriding an existing key => no need to allocated room | |
164 | * in uCode. */ | |
165 | ||
c587de0b | 166 | WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
6e21f15c AK |
167 | "no space for a new key"); |
168 | ||
c587de0b TW |
169 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
170 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
171 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c | 172 | |
6e21f15c AK |
173 | IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n"); |
174 | ||
c587de0b | 175 | ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
6e21f15c | 176 | |
b481de9c ZY |
177 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
178 | ||
6e21f15c AK |
179 | return ret; |
180 | } | |
181 | ||
182 | static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
183 | struct ieee80211_key_conf *keyconf, | |
184 | u8 sta_id) | |
185 | { | |
186 | return -EOPNOTSUPP; | |
187 | } | |
188 | ||
189 | static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv, | |
190 | struct ieee80211_key_conf *keyconf, | |
191 | u8 sta_id) | |
192 | { | |
193 | return -EOPNOTSUPP; | |
b481de9c ZY |
194 | } |
195 | ||
4a8a4322 | 196 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
197 | { |
198 | unsigned long flags; | |
199 | ||
200 | spin_lock_irqsave(&priv->sta_lock, flags); | |
c587de0b TW |
201 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key)); |
202 | memset(&priv->stations[sta_id].sta.key, 0, | |
4c897253 | 203 | sizeof(struct iwl4965_keyinfo)); |
c587de0b TW |
204 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
205 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
206 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
207 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
208 | ||
e1623446 | 209 | IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n"); |
c587de0b | 210 | iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
211 | return 0; |
212 | } | |
213 | ||
fa11d525 | 214 | static int iwl3945_set_dynamic_key(struct iwl_priv *priv, |
6e21f15c AK |
215 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
216 | { | |
217 | int ret = 0; | |
218 | ||
219 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
220 | ||
221 | switch (keyconf->alg) { | |
222 | case ALG_CCMP: | |
223 | ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id); | |
224 | break; | |
225 | case ALG_TKIP: | |
226 | ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id); | |
227 | break; | |
228 | case ALG_WEP: | |
229 | ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id); | |
230 | break; | |
231 | default: | |
1e680233 | 232 | IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg); |
6e21f15c AK |
233 | ret = -EINVAL; |
234 | } | |
235 | ||
236 | IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n", | |
237 | keyconf->alg, keyconf->keylen, keyconf->keyidx, | |
238 | sta_id, ret); | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | static int iwl3945_remove_static_key(struct iwl_priv *priv) | |
244 | { | |
245 | int ret = -EOPNOTSUPP; | |
246 | ||
247 | return ret; | |
248 | } | |
249 | ||
250 | static int iwl3945_set_static_key(struct iwl_priv *priv, | |
251 | struct ieee80211_key_conf *key) | |
252 | { | |
253 | if (key->alg == ALG_WEP) | |
254 | return -EOPNOTSUPP; | |
255 | ||
256 | IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg); | |
257 | return -EINVAL; | |
258 | } | |
259 | ||
4a8a4322 | 260 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
261 | { |
262 | struct list_head *element; | |
263 | ||
e1623446 | 264 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
265 | priv->frames_count); |
266 | ||
267 | while (!list_empty(&priv->free_frames)) { | |
268 | element = priv->free_frames.next; | |
269 | list_del(element); | |
bb8c093b | 270 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
271 | priv->frames_count--; |
272 | } | |
273 | ||
274 | if (priv->frames_count) { | |
39aadf8c | 275 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
276 | priv->frames_count); |
277 | priv->frames_count = 0; | |
278 | } | |
279 | } | |
280 | ||
4a8a4322 | 281 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 282 | { |
bb8c093b | 283 | struct iwl3945_frame *frame; |
b481de9c ZY |
284 | struct list_head *element; |
285 | if (list_empty(&priv->free_frames)) { | |
286 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
287 | if (!frame) { | |
15b1687c | 288 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
289 | return NULL; |
290 | } | |
291 | ||
292 | priv->frames_count++; | |
293 | return frame; | |
294 | } | |
295 | ||
296 | element = priv->free_frames.next; | |
297 | list_del(element); | |
bb8c093b | 298 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
299 | } |
300 | ||
4a8a4322 | 301 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
302 | { |
303 | memset(frame, 0, sizeof(*frame)); | |
304 | list_add(&frame->list, &priv->free_frames); | |
305 | } | |
306 | ||
4a8a4322 | 307 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 308 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 309 | int left) |
b481de9c ZY |
310 | { |
311 | ||
8ccde88a | 312 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
313 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
314 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
315 | return 0; |
316 | ||
317 | if (priv->ibss_beacon->len > left) | |
318 | return 0; | |
319 | ||
320 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
321 | ||
322 | return priv->ibss_beacon->len; | |
323 | } | |
324 | ||
4a8a4322 | 325 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 326 | { |
bb8c093b | 327 | struct iwl3945_frame *frame; |
b481de9c ZY |
328 | unsigned int frame_size; |
329 | int rc; | |
330 | u8 rate; | |
331 | ||
bb8c093b | 332 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
333 | |
334 | if (!frame) { | |
15b1687c | 335 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
336 | "command.\n"); |
337 | return -ENOMEM; | |
338 | } | |
339 | ||
8ccde88a | 340 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 341 | |
bb8c093b | 342 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 343 | |
518099a8 | 344 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
345 | &frame->u.cmd[0]); |
346 | ||
bb8c093b | 347 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
348 | |
349 | return rc; | |
350 | } | |
351 | ||
4a8a4322 | 352 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 353 | { |
3832ec9d | 354 | if (priv->shared_virt) |
b481de9c | 355 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 356 | sizeof(struct iwl3945_shared), |
3832ec9d AK |
357 | priv->shared_virt, |
358 | priv->shared_phys); | |
b481de9c ZY |
359 | } |
360 | ||
4a8a4322 | 361 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 362 | struct ieee80211_tx_info *info, |
c2acea8e | 363 | struct iwl_device_cmd *cmd, |
b481de9c | 364 | struct sk_buff *skb_frag, |
6e21f15c | 365 | int sta_id) |
b481de9c | 366 | { |
9744c91f | 367 | struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
c587de0b | 368 | struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
b481de9c ZY |
369 | |
370 | switch (keyinfo->alg) { | |
371 | case ALG_CCMP: | |
9744c91f AK |
372 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; |
373 | memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen); | |
e1623446 | 374 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
375 | break; |
376 | ||
377 | case ALG_TKIP: | |
b481de9c ZY |
378 | break; |
379 | ||
380 | case ALG_WEP: | |
9744c91f | 381 | tx_cmd->sec_ctl = TX_CMD_SEC_WEP | |
e039fa4a | 382 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
383 | |
384 | if (keyinfo->keylen == 13) | |
9744c91f | 385 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; |
b481de9c | 386 | |
9744c91f | 387 | memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c | 388 | |
e1623446 | 389 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
e039fa4a | 390 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
391 | break; |
392 | ||
b481de9c | 393 | default: |
978785a3 | 394 | IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg); |
b481de9c ZY |
395 | break; |
396 | } | |
397 | } | |
398 | ||
399 | /* | |
400 | * handle build REPLY_TX command notification. | |
401 | */ | |
4a8a4322 | 402 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2acea8e | 403 | struct iwl_device_cmd *cmd, |
e039fa4a | 404 | struct ieee80211_tx_info *info, |
e52119c5 | 405 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 406 | { |
9744c91f AK |
407 | struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
408 | __le32 tx_flags = tx_cmd->tx_flags; | |
fd7c8a40 | 409 | __le16 fc = hdr->frame_control; |
b481de9c | 410 | |
9744c91f | 411 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 412 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 413 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 414 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 415 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 416 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
417 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
418 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
419 | } else { | |
420 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
421 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
422 | } | |
423 | ||
9744c91f | 424 | tx_cmd->sta_id = std_id; |
8b7b1e05 | 425 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
426 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
427 | ||
fd7c8a40 HH |
428 | if (ieee80211_is_data_qos(fc)) { |
429 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
9744c91f | 430 | tx_cmd->tid_tspec = qc[0] & 0xf; |
b481de9c | 431 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 432 | } else { |
b481de9c | 433 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 434 | } |
b481de9c | 435 | |
37dc70fe | 436 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
b481de9c ZY |
437 | |
438 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
439 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
440 | ||
441 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
442 | if (ieee80211_is_mgmt(fc)) { |
443 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
9744c91f | 444 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 445 | else |
9744c91f | 446 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 447 | } else { |
9744c91f | 448 | tx_cmd->timeout.pm_frame_timeout = 0; |
ab53d8af | 449 | } |
b481de9c | 450 | |
9744c91f AK |
451 | tx_cmd->driver_txop = 0; |
452 | tx_cmd->tx_flags = tx_flags; | |
453 | tx_cmd->next_frame_len = 0; | |
b481de9c ZY |
454 | } |
455 | ||
b481de9c ZY |
456 | /* |
457 | * start REPLY_TX command process | |
458 | */ | |
4a8a4322 | 459 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
460 | { |
461 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 462 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
9744c91f | 463 | struct iwl3945_tx_cmd *tx_cmd; |
188cf6c7 | 464 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 465 | struct iwl_queue *q = NULL; |
c2acea8e JB |
466 | struct iwl_device_cmd *out_cmd; |
467 | struct iwl_cmd_meta *out_meta; | |
b481de9c ZY |
468 | dma_addr_t phys_addr; |
469 | dma_addr_t txcmd_phys; | |
e52119c5 | 470 | int txq_id = skb_get_queue_mapping(skb); |
df833b1d | 471 | u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */ |
54dbb525 TW |
472 | u8 id; |
473 | u8 unicast; | |
b481de9c | 474 | u8 sta_id; |
54dbb525 | 475 | u8 tid = 0; |
b481de9c | 476 | u16 seq_number = 0; |
fd7c8a40 | 477 | __le16 fc; |
b481de9c | 478 | u8 wait_write_ptr = 0; |
54dbb525 | 479 | u8 *qc = NULL; |
b481de9c ZY |
480 | unsigned long flags; |
481 | int rc; | |
482 | ||
483 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 484 | if (iwl_is_rfkill(priv)) { |
e1623446 | 485 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
b481de9c ZY |
486 | goto drop_unlock; |
487 | } | |
488 | ||
e039fa4a | 489 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 490 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
491 | goto drop_unlock; |
492 | } | |
493 | ||
494 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
495 | id = 0; | |
496 | ||
fd7c8a40 | 497 | fc = hdr->frame_control; |
b481de9c | 498 | |
d08853a3 | 499 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c | 500 | if (ieee80211_is_auth(fc)) |
e1623446 | 501 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 502 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 503 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 504 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 505 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
b481de9c ZY |
506 | #endif |
507 | ||
aa065263 | 508 | /* drop all non-injected data frame if we are not associated */ |
914233d6 | 509 | if (ieee80211_is_data(fc) && |
aa065263 | 510 | !(info->flags & IEEE80211_TX_CTL_INJECTED) && |
8ccde88a | 511 | (!iwl_is_associated(priv) || |
05c914fe | 512 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
e1623446 | 513 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
514 | goto drop_unlock; |
515 | } | |
516 | ||
517 | spin_unlock_irqrestore(&priv->lock, flags); | |
518 | ||
7294ec95 | 519 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 BC |
520 | |
521 | /* Find (or create) index into station table for destination station */ | |
aa065263 GS |
522 | if (info->flags & IEEE80211_TX_CTL_INJECTED) |
523 | sta_id = priv->hw_params.bcast_sta_id; | |
524 | else | |
525 | sta_id = iwl_get_sta_id(priv, hdr); | |
b481de9c | 526 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 527 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 528 | hdr->addr1); |
b481de9c ZY |
529 | goto drop; |
530 | } | |
531 | ||
e1623446 | 532 | IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id); |
b481de9c | 533 | |
fd7c8a40 HH |
534 | if (ieee80211_is_data_qos(fc)) { |
535 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 536 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
537 | if (unlikely(tid >= MAX_TID_COUNT)) |
538 | goto drop; | |
c587de0b | 539 | seq_number = priv->stations[sta_id].tid[tid].seq_number & |
b481de9c ZY |
540 | IEEE80211_SCTL_SEQ; |
541 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
542 | (hdr->seq_ctrl & | |
c1b4aa3f | 543 | cpu_to_le16(IEEE80211_SCTL_FRAG)); |
b481de9c ZY |
544 | seq_number += 0x10; |
545 | } | |
6440adb5 BC |
546 | |
547 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 548 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
549 | q = &txq->q; |
550 | ||
dc57a303 ZY |
551 | if ((iwl_queue_space(q) < q->high_mark)) |
552 | goto drop; | |
553 | ||
b481de9c ZY |
554 | spin_lock_irqsave(&priv->lock, flags); |
555 | ||
fc4b6853 | 556 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 557 | |
6440adb5 | 558 | /* Set up driver data for this TFD */ |
dbb6654c | 559 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
fc4b6853 | 560 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 BC |
561 | |
562 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 563 | out_cmd = txq->cmd[idx]; |
c2acea8e | 564 | out_meta = &txq->meta[idx]; |
9744c91f | 565 | tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 566 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
9744c91f | 567 | memset(tx_cmd, 0, sizeof(*tx_cmd)); |
6440adb5 BC |
568 | |
569 | /* | |
570 | * Set up the Tx-command (not MAC!) header. | |
571 | * Store the chosen Tx queue and TFD index within the sequence field; | |
572 | * after Tx, uCode's Tx response will return this value so driver can | |
573 | * locate the frame within the tx queue and do post-tx processing. | |
574 | */ | |
b481de9c ZY |
575 | out_cmd->hdr.cmd = REPLY_TX; |
576 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 577 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
578 | |
579 | /* Copy MAC header from skb into command buffer */ | |
9744c91f | 580 | memcpy(tx_cmd->hdr, hdr, hdr_len); |
b481de9c | 581 | |
df833b1d RC |
582 | |
583 | if (info->control.hw_key) | |
584 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id); | |
585 | ||
586 | /* TODO need this for burst mode later on */ | |
587 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); | |
588 | ||
589 | /* set is_hcca to 0; it probably will never be implemented */ | |
590 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); | |
591 | ||
592 | /* Total # bytes to be transmitted */ | |
593 | len = (u16)skb->len; | |
9744c91f | 594 | tx_cmd->len = cpu_to_le16(len); |
df833b1d | 595 | |
20594eb0 | 596 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
22fdf3c9 | 597 | iwl_update_stats(priv, true, fc, len); |
9744c91f AK |
598 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; |
599 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
df833b1d RC |
600 | |
601 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
602 | txq->need_update = 1; | |
603 | if (qc) | |
c587de0b | 604 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
df833b1d RC |
605 | } else { |
606 | wait_write_ptr = 1; | |
607 | txq->need_update = 0; | |
608 | } | |
609 | ||
610 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", | |
611 | le16_to_cpu(out_cmd->hdr.sequence)); | |
9744c91f AK |
612 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags)); |
613 | iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd)); | |
614 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, | |
df833b1d RC |
615 | ieee80211_hdrlen(fc)); |
616 | ||
6440adb5 BC |
617 | /* |
618 | * Use the first empty entry in this queue's command buffer array | |
619 | * to contain the Tx command and MAC header concatenated together | |
620 | * (payload data will be in another buffer). | |
621 | * Size of this varies, due to varying MAC header length. | |
622 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
623 | * of the MAC header (device reads on dword boundaries). | |
624 | * We'll tell device about this padding later. | |
625 | */ | |
3832ec9d | 626 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 627 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
628 | |
629 | len_org = len; | |
630 | len = (len + 3) & ~3; | |
631 | ||
632 | if (len_org != len) | |
633 | len_org = 1; | |
634 | else | |
635 | len_org = 0; | |
636 | ||
6440adb5 BC |
637 | /* Physical address of this Tx command's header (not MAC header!), |
638 | * within command buffer array. */ | |
df833b1d RC |
639 | txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
640 | len, PCI_DMA_TODEVICE); | |
641 | /* we do not map meta data ... so we can safely access address to | |
642 | * provide to unmap command*/ | |
c2acea8e JB |
643 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
644 | pci_unmap_len_set(out_meta, len, len); | |
b481de9c | 645 | |
6440adb5 BC |
646 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
647 | * first entry */ | |
7aaa1d79 SO |
648 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
649 | txcmd_phys, len, 1, 0); | |
b481de9c | 650 | |
b481de9c | 651 | |
6440adb5 BC |
652 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
653 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
654 | len = skb->len - hdr_len; |
655 | if (len) { | |
656 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
657 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
658 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
659 | phys_addr, len, | |
660 | 0, U32_PAD(len)); | |
b481de9c ZY |
661 | } |
662 | ||
b481de9c | 663 | |
6440adb5 | 664 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 665 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
4f3602c8 | 666 | rc = iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
667 | spin_unlock_irqrestore(&priv->lock, flags); |
668 | ||
669 | if (rc) | |
670 | return rc; | |
671 | ||
d20b3c65 | 672 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
673 | && priv->mac80211_registered) { |
674 | if (wait_write_ptr) { | |
675 | spin_lock_irqsave(&priv->lock, flags); | |
676 | txq->need_update = 1; | |
4f3602c8 | 677 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
678 | spin_unlock_irqrestore(&priv->lock, flags); |
679 | } | |
680 | ||
e4e72fb4 | 681 | iwl_stop_queue(priv, skb_get_queue_mapping(skb)); |
b481de9c ZY |
682 | } |
683 | ||
684 | return 0; | |
685 | ||
686 | drop_unlock: | |
687 | spin_unlock_irqrestore(&priv->lock, flags); | |
688 | drop: | |
689 | return -1; | |
690 | } | |
691 | ||
c8b0e6e1 | 692 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
693 | |
694 | #include "iwl-spectrum.h" | |
695 | ||
696 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
697 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
698 | #define TIME_UNIT 1024 | |
699 | ||
700 | /* | |
701 | * extended beacon time format | |
702 | * time in usec will be changed into a 32-bit value in 8:24 format | |
703 | * the high 1 byte is the beacon counts | |
704 | * the lower 3 bytes is the time in usec within one beacon interval | |
705 | */ | |
706 | ||
bb8c093b | 707 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
708 | { |
709 | u32 quot; | |
710 | u32 rem; | |
711 | u32 interval = beacon_interval * 1024; | |
712 | ||
713 | if (!interval || !usec) | |
714 | return 0; | |
715 | ||
716 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
717 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
718 | ||
719 | return (quot << 24) + rem; | |
720 | } | |
721 | ||
722 | /* base is usually what we get from ucode with each received frame, | |
723 | * the same as HW timer counter counting down | |
724 | */ | |
725 | ||
bb8c093b | 726 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
727 | { |
728 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
729 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
730 | u32 interval = beacon_interval * TIME_UNIT; | |
731 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
732 | (addon & BEACON_TIME_MASK_HIGH); | |
733 | ||
734 | if (base_low > addon_low) | |
735 | res += base_low - addon_low; | |
736 | else if (base_low < addon_low) { | |
737 | res += interval + base_low - addon_low; | |
738 | res += (1 << 24); | |
739 | } else | |
740 | res += (1 << 24); | |
741 | ||
742 | return cpu_to_le32(res); | |
743 | } | |
744 | ||
4a8a4322 | 745 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
746 | struct ieee80211_measurement_params *params, |
747 | u8 type) | |
748 | { | |
600c0e11 | 749 | struct iwl_spectrum_cmd spectrum; |
2f301227 | 750 | struct iwl_rx_packet *pkt; |
c2d79b48 | 751 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
752 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
753 | .data = (void *)&spectrum, | |
c2acea8e | 754 | .flags = CMD_WANT_SKB, |
b481de9c ZY |
755 | }; |
756 | u32 add_time = le64_to_cpu(params->start_time); | |
757 | int rc; | |
758 | int spectrum_resp_status; | |
759 | int duration = le16_to_cpu(params->duration); | |
760 | ||
8ccde88a | 761 | if (iwl_is_associated(priv)) |
b481de9c | 762 | add_time = |
bb8c093b | 763 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
764 | le64_to_cpu(params->start_time) - priv->last_tsf, |
765 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
766 | ||
767 | memset(&spectrum, 0, sizeof(spectrum)); | |
768 | ||
769 | spectrum.channel_count = cpu_to_le16(1); | |
770 | spectrum.flags = | |
771 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
772 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
773 | cmd.len = sizeof(spectrum); | |
774 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
775 | ||
8ccde88a | 776 | if (iwl_is_associated(priv)) |
b481de9c | 777 | spectrum.start_time = |
bb8c093b | 778 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
779 | add_time, |
780 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
781 | else | |
782 | spectrum.start_time = 0; | |
783 | ||
784 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
785 | spectrum.channels[0].channel = params->channel; | |
786 | spectrum.channels[0].type = type; | |
8ccde88a | 787 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
788 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
789 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
790 | ||
518099a8 | 791 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
792 | if (rc) |
793 | return rc; | |
794 | ||
2f301227 ZY |
795 | pkt = (struct iwl_rx_packet *)cmd.reply_page; |
796 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
15b1687c | 797 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
798 | rc = -EIO; |
799 | } | |
800 | ||
2f301227 | 801 | spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status); |
b481de9c ZY |
802 | switch (spectrum_resp_status) { |
803 | case 0: /* Command will be handled */ | |
2f301227 | 804 | if (pkt->u.spectrum.id != 0xff) { |
e1623446 | 805 | IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n", |
2f301227 | 806 | pkt->u.spectrum.id); |
b481de9c ZY |
807 | priv->measurement_status &= ~MEASUREMENT_READY; |
808 | } | |
809 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
810 | rc = 0; | |
811 | break; | |
812 | ||
813 | case 1: /* Command will not be handled */ | |
814 | rc = -EAGAIN; | |
815 | break; | |
816 | } | |
817 | ||
64a76b50 | 818 | iwl_free_pages(priv, cmd.reply_page); |
b481de9c ZY |
819 | |
820 | return rc; | |
821 | } | |
822 | #endif | |
823 | ||
4a8a4322 | 824 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 825 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 826 | { |
2f301227 | 827 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
3d24a9f7 | 828 | struct iwl_alive_resp *palive; |
b481de9c ZY |
829 | struct delayed_work *pwork; |
830 | ||
831 | palive = &pkt->u.alive_frame; | |
832 | ||
e1623446 | 833 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
834 | "0x%01X 0x%01X\n", |
835 | palive->is_valid, palive->ver_type, | |
836 | palive->ver_subtype); | |
837 | ||
838 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 839 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
3d24a9f7 TW |
840 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
841 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
842 | pwork = &priv->init_alive_start; |
843 | } else { | |
e1623446 | 844 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 845 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
3d24a9f7 | 846 | sizeof(struct iwl_alive_resp)); |
b481de9c | 847 | pwork = &priv->alive_start; |
bb8c093b | 848 | iwl3945_disable_events(priv); |
b481de9c ZY |
849 | } |
850 | ||
851 | /* We delay the ALIVE response by 5ms to | |
852 | * give the HW RF Kill time to activate... */ | |
853 | if (palive->is_valid == UCODE_VALID_OK) | |
854 | queue_delayed_work(priv->workqueue, pwork, | |
855 | msecs_to_jiffies(5)); | |
856 | else | |
39aadf8c | 857 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
858 | } |
859 | ||
4a8a4322 | 860 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 861 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 862 | { |
c7e035a9 | 863 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 864 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
c7e035a9 | 865 | #endif |
b481de9c | 866 | |
e1623446 | 867 | IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
b481de9c ZY |
868 | return; |
869 | } | |
870 | ||
bb8c093b | 871 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 872 | { |
4a8a4322 AK |
873 | struct iwl_priv *priv = |
874 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
875 | struct sk_buff *beacon; |
876 | ||
877 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 878 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
879 | |
880 | if (!beacon) { | |
15b1687c | 881 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
882 | return; |
883 | } | |
884 | ||
885 | mutex_lock(&priv->mutex); | |
886 | /* new beacon skb is allocated every time; dispose previous.*/ | |
887 | if (priv->ibss_beacon) | |
888 | dev_kfree_skb(priv->ibss_beacon); | |
889 | ||
890 | priv->ibss_beacon = beacon; | |
891 | mutex_unlock(&priv->mutex); | |
892 | ||
bb8c093b | 893 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
894 | } |
895 | ||
4a8a4322 | 896 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 897 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 898 | { |
d08853a3 | 899 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 900 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
bb8c093b | 901 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
902 | u8 rate = beacon->beacon_notify_hdr.rate; |
903 | ||
e1623446 | 904 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c ZY |
905 | "tsf %d %d rate %d\n", |
906 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
907 | beacon->beacon_notify_hdr.failure_frame, | |
908 | le32_to_cpu(beacon->ibss_mgr_status), | |
909 | le32_to_cpu(beacon->high_tsf), | |
910 | le32_to_cpu(beacon->low_tsf), rate); | |
911 | #endif | |
912 | ||
05c914fe | 913 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
914 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
915 | queue_work(priv->workqueue, &priv->beacon_update); | |
916 | } | |
917 | ||
b481de9c ZY |
918 | /* Handle notification from uCode that card's power state is changing |
919 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 920 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 921 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 922 | { |
2f301227 | 923 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
924 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
925 | unsigned long status = priv->status; | |
926 | ||
4c423a2b | 927 | IWL_WARN(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
928 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
929 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
930 | ||
5d49f498 | 931 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
932 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
933 | ||
934 | if (flags & HW_CARD_DISABLED) | |
935 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
936 | else | |
937 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
938 | ||
939 | ||
af0053d6 | 940 | iwl_scan_cancel(priv); |
b481de9c ZY |
941 | |
942 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
943 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
944 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
945 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
946 | else |
947 | wake_up_interruptible(&priv->wait_command_queue); | |
948 | } | |
949 | ||
950 | /** | |
bb8c093b | 951 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
952 | * |
953 | * Setup the RX handlers for each of the reply types sent from the uCode | |
954 | * to the host. | |
955 | * | |
956 | * This function chains into the hardware specific files for them to setup | |
957 | * any hardware specific handlers as well. | |
958 | */ | |
4a8a4322 | 959 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 960 | { |
bb8c093b CH |
961 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
962 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
261b9c33 | 963 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
8ccde88a | 964 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; |
030f05ed | 965 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 966 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
030f05ed | 967 | iwl_rx_pm_debug_statistics_notif; |
bb8c093b | 968 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; |
b481de9c | 969 | |
9fbab516 BC |
970 | /* |
971 | * The same handler is used for both the REPLY to a discrete | |
972 | * statistics request from the host as well as for the periodic | |
973 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 974 | */ |
bb8c093b CH |
975 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
976 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 977 | |
261b9c33 | 978 | iwl_setup_spectrum_handlers(priv); |
cade0eb2 | 979 | iwl_setup_rx_scan_handlers(priv); |
bb8c093b | 980 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; |
b481de9c | 981 | |
9fbab516 | 982 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 983 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
984 | } |
985 | ||
b481de9c ZY |
986 | /************************** RX-FUNCTIONS ****************************/ |
987 | /* | |
988 | * Rx theory of operation | |
989 | * | |
990 | * The host allocates 32 DMA target addresses and passes the host address | |
991 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
992 | * 0 to 31 | |
993 | * | |
994 | * Rx Queue Indexes | |
995 | * The host/firmware share two index registers for managing the Rx buffers. | |
996 | * | |
997 | * The READ index maps to the first position that the firmware may be writing | |
998 | * to -- the driver can read up to (but not including) this position and get | |
999 | * good data. | |
1000 | * The READ index is managed by the firmware once the card is enabled. | |
1001 | * | |
1002 | * The WRITE index maps to the last position the driver has read from -- the | |
1003 | * position preceding WRITE is the last slot the firmware can place a packet. | |
1004 | * | |
1005 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
1006 | * WRITE = READ. | |
1007 | * | |
9fbab516 | 1008 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
1009 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
1010 | * | |
9fbab516 | 1011 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
1012 | * and fire the RX interrupt. The driver can then query the READ index and |
1013 | * process as many packets as possible, moving the WRITE index forward as it | |
1014 | * resets the Rx queue buffers with new memory. | |
1015 | * | |
1016 | * The management in the driver is as follows: | |
1017 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
1018 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 1019 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 1020 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
1021 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
1022 | * 'processed' and 'read' driver indexes as well) | |
1023 | * + A received packet is processed and handed to the kernel network stack, | |
1024 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
1025 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
1026 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
1027 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
1028 | * were enough free buffers and RX_STALLED is set it is cleared. | |
1029 | * | |
1030 | * | |
1031 | * Driver sequence: | |
1032 | * | |
9fbab516 | 1033 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 1034 | * iwl3945_rx_queue_restock |
9fbab516 | 1035 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
1036 | * queue, updates firmware pointers, and updates |
1037 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 1038 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
1039 | * |
1040 | * -- enable interrupts -- | |
6100b588 | 1041 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
1042 | * READ INDEX, detaching the SKB from the pool. |
1043 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 1044 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
1045 | * slots. |
1046 | * ... | |
1047 | * | |
1048 | */ | |
1049 | ||
b481de9c | 1050 | /** |
9fbab516 | 1051 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 1052 | */ |
4a8a4322 | 1053 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
1054 | dma_addr_t dma_addr) |
1055 | { | |
1056 | return cpu_to_le32((u32)dma_addr); | |
1057 | } | |
1058 | ||
1059 | /** | |
bb8c093b | 1060 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 1061 | * |
9fbab516 | 1062 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 1063 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 1064 | * as we can, pulling from rx_free. |
b481de9c ZY |
1065 | * |
1066 | * This moves the 'write' index forward to catch up with 'processed', and | |
1067 | * also updates the memory address in the firmware to reference the new | |
1068 | * target buffer. | |
1069 | */ | |
4a8a4322 | 1070 | static int iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 1071 | { |
cc2f362c | 1072 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1073 | struct list_head *element; |
6100b588 | 1074 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
1075 | unsigned long flags; |
1076 | int write, rc; | |
1077 | ||
1078 | spin_lock_irqsave(&rxq->lock, flags); | |
1079 | write = rxq->write & ~0x7; | |
37d68317 | 1080 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 1081 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 1082 | element = rxq->rx_free.next; |
6100b588 | 1083 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 1084 | list_del(element); |
6440adb5 BC |
1085 | |
1086 | /* Point to Rx buffer via next RBD in circular buffer */ | |
2f301227 | 1087 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma); |
b481de9c ZY |
1088 | rxq->queue[rxq->write] = rxb; |
1089 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
1090 | rxq->free_count--; | |
1091 | } | |
1092 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1093 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
1094 | * refill it */ | |
1095 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1096 | queue_work(priv->workqueue, &priv->rx_replenish); | |
1097 | ||
1098 | ||
6440adb5 BC |
1099 | /* If we've added more space for the firmware to place data, tell it. |
1100 | * Increment device's write pointer in multiples of 8. */ | |
d14d4440 | 1101 | if ((rxq->write_actual != (rxq->write & ~0x7)) |
b481de9c ZY |
1102 | || (abs(rxq->write - rxq->read) > 7)) { |
1103 | spin_lock_irqsave(&rxq->lock, flags); | |
1104 | rxq->need_update = 1; | |
1105 | spin_unlock_irqrestore(&rxq->lock, flags); | |
141c43a3 | 1106 | rc = iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
1107 | if (rc) |
1108 | return rc; | |
1109 | } | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | /** | |
bb8c093b | 1115 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
1116 | * |
1117 | * When moving to rx_free an SKB is allocated for the slot. | |
1118 | * | |
bb8c093b | 1119 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 1120 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 1121 | */ |
d14d4440 | 1122 | static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
b481de9c | 1123 | { |
cc2f362c | 1124 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1125 | struct list_head *element; |
6100b588 | 1126 | struct iwl_rx_mem_buffer *rxb; |
2f301227 | 1127 | struct page *page; |
b481de9c | 1128 | unsigned long flags; |
29b1b268 | 1129 | gfp_t gfp_mask = priority; |
72240498 AK |
1130 | |
1131 | while (1) { | |
1132 | spin_lock_irqsave(&rxq->lock, flags); | |
1133 | ||
1134 | if (list_empty(&rxq->rx_used)) { | |
1135 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1136 | return; | |
1137 | } | |
72240498 | 1138 | spin_unlock_irqrestore(&rxq->lock, flags); |
6440adb5 | 1139 | |
f82a924c | 1140 | if (rxq->free_count > RX_LOW_WATERMARK) |
29b1b268 | 1141 | gfp_mask |= __GFP_NOWARN; |
2f301227 ZY |
1142 | |
1143 | if (priv->hw_params.rx_page_order > 0) | |
29b1b268 | 1144 | gfp_mask |= __GFP_COMP; |
2f301227 | 1145 | |
6440adb5 | 1146 | /* Alloc a new receive buffer */ |
29b1b268 | 1147 | page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); |
2f301227 | 1148 | if (!page) { |
b481de9c | 1149 | if (net_ratelimit()) |
f82a924c RC |
1150 | IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n"); |
1151 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
1152 | net_ratelimit()) | |
1153 | IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n", | |
1154 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", | |
1155 | rxq->free_count); | |
b481de9c ZY |
1156 | /* We don't reschedule replenish work here -- we will |
1157 | * call the restock method and if it still needs | |
1158 | * more buffers it will schedule replenish */ | |
1159 | break; | |
1160 | } | |
12342c47 | 1161 | |
de0bd508 RC |
1162 | spin_lock_irqsave(&rxq->lock, flags); |
1163 | if (list_empty(&rxq->rx_used)) { | |
1164 | spin_unlock_irqrestore(&rxq->lock, flags); | |
2f301227 | 1165 | __free_pages(page, priv->hw_params.rx_page_order); |
de0bd508 RC |
1166 | return; |
1167 | } | |
1168 | element = rxq->rx_used.next; | |
1169 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
1170 | list_del(element); | |
1171 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1172 | ||
2f301227 | 1173 | rxb->page = page; |
6440adb5 | 1174 | /* Get physical address of RB/SKB */ |
2f301227 ZY |
1175 | rxb->page_dma = pci_map_page(priv->pci_dev, page, 0, |
1176 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1177 | PCI_DMA_FROMDEVICE); | |
72240498 AK |
1178 | |
1179 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1180 | |
b481de9c ZY |
1181 | list_add_tail(&rxb->list, &rxq->rx_free); |
1182 | rxq->free_count++; | |
2f301227 ZY |
1183 | priv->alloc_rxb_page++; |
1184 | ||
72240498 | 1185 | spin_unlock_irqrestore(&rxq->lock, flags); |
b481de9c | 1186 | } |
5c0eef96 MA |
1187 | } |
1188 | ||
df833b1d RC |
1189 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
1190 | { | |
1191 | unsigned long flags; | |
1192 | int i; | |
1193 | spin_lock_irqsave(&rxq->lock, flags); | |
1194 | INIT_LIST_HEAD(&rxq->rx_free); | |
1195 | INIT_LIST_HEAD(&rxq->rx_used); | |
1196 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1197 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1198 | /* In the reset function, these buffers may have been allocated | |
1199 | * to an SKB, so we need to unmap and free potential storage */ | |
2f301227 ZY |
1200 | if (rxq->pool[i].page != NULL) { |
1201 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
1202 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1203 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 1204 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 1205 | rxq->pool[i].page = NULL; |
df833b1d RC |
1206 | } |
1207 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1208 | } | |
1209 | ||
1210 | /* Set us so that we have processed and used all buffers, but have | |
1211 | * not restocked the Rx queue with fresh buffers */ | |
1212 | rxq->read = rxq->write = 0; | |
d14d4440 | 1213 | rxq->write_actual = 0; |
2f301227 | 1214 | rxq->free_count = 0; |
df833b1d RC |
1215 | spin_unlock_irqrestore(&rxq->lock, flags); |
1216 | } | |
df833b1d | 1217 | |
5c0eef96 MA |
1218 | void iwl3945_rx_replenish(void *data) |
1219 | { | |
4a8a4322 | 1220 | struct iwl_priv *priv = data; |
5c0eef96 MA |
1221 | unsigned long flags; |
1222 | ||
d14d4440 | 1223 | iwl3945_rx_allocate(priv, GFP_KERNEL); |
b481de9c ZY |
1224 | |
1225 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 1226 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1227 | spin_unlock_irqrestore(&priv->lock, flags); |
1228 | } | |
1229 | ||
d14d4440 AK |
1230 | static void iwl3945_rx_replenish_now(struct iwl_priv *priv) |
1231 | { | |
1232 | iwl3945_rx_allocate(priv, GFP_ATOMIC); | |
1233 | ||
1234 | iwl3945_rx_queue_restock(priv); | |
1235 | } | |
1236 | ||
1237 | ||
df833b1d RC |
1238 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. |
1239 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1240 | * This free routine walks the list of POOL entries and if SKB is set to | |
1241 | * non NULL it is unmapped and freed | |
1242 | */ | |
1243 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
1244 | { | |
1245 | int i; | |
1246 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
2f301227 ZY |
1247 | if (rxq->pool[i].page != NULL) { |
1248 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
1249 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1250 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 1251 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 1252 | rxq->pool[i].page = NULL; |
df833b1d RC |
1253 | } |
1254 | } | |
1255 | ||
1256 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
1257 | rxq->dma_addr); | |
1258 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), | |
1259 | rxq->rb_stts, rxq->rb_stts_dma); | |
1260 | rxq->bd = NULL; | |
1261 | rxq->rb_stts = NULL; | |
1262 | } | |
df833b1d RC |
1263 | |
1264 | ||
b481de9c ZY |
1265 | /* Convert linear signal-to-noise ratio into dB */ |
1266 | static u8 ratio2dB[100] = { | |
1267 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1268 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1269 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1270 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1271 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1272 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1273 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1274 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1275 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1276 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1277 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1278 | }; | |
1279 | ||
1280 | /* Calculates a relative dB value from a ratio of linear | |
1281 | * (i.e. not dB) signal levels. | |
1282 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 1283 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 1284 | { |
221c80cf AB |
1285 | /* 1000:1 or higher just report as 60 dB */ |
1286 | if (sig_ratio >= 1000) | |
b481de9c ZY |
1287 | return 60; |
1288 | ||
221c80cf | 1289 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 1290 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 1291 | if (sig_ratio >= 100) |
3ac7f146 | 1292 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
1293 | |
1294 | /* We shouldn't see this */ | |
1295 | if (sig_ratio < 1) | |
1296 | return 0; | |
1297 | ||
1298 | /* Use table for ratios 1:1 - 99:1 */ | |
1299 | return (int)ratio2dB[sig_ratio]; | |
1300 | } | |
1301 | ||
b481de9c | 1302 | /** |
9fbab516 | 1303 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1304 | * |
1305 | * Uses the priv->rx_handlers callback function array to invoke | |
1306 | * the appropriate handlers, including command responses, | |
1307 | * frame-received notifications, and other notifications. | |
1308 | */ | |
4a8a4322 | 1309 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 1310 | { |
6100b588 | 1311 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 1312 | struct iwl_rx_packet *pkt; |
cc2f362c | 1313 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1314 | u32 r, i; |
1315 | int reclaim; | |
1316 | unsigned long flags; | |
5c0eef96 | 1317 | u8 fill_rx = 0; |
d68ab680 | 1318 | u32 count = 8; |
d14d4440 | 1319 | int total_empty = 0; |
b481de9c | 1320 | |
6440adb5 BC |
1321 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1322 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 1323 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1324 | i = rxq->read; |
1325 | ||
d14d4440 | 1326 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 1327 | total_empty = r - rxq->write_actual; |
d14d4440 AK |
1328 | if (total_empty < 0) |
1329 | total_empty += RX_QUEUE_SIZE; | |
1330 | ||
1331 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 | 1332 | fill_rx = 1; |
b481de9c ZY |
1333 | /* Rx interrupt, but nothing sent from uCode */ |
1334 | if (i == r) | |
af472a95 | 1335 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c ZY |
1336 | |
1337 | while (i != r) { | |
1338 | rxb = rxq->queue[i]; | |
1339 | ||
9fbab516 | 1340 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1341 | * then a bug has been introduced in the queue refilling |
1342 | * routines -- catch it here */ | |
1343 | BUG_ON(rxb == NULL); | |
1344 | ||
1345 | rxq->queue[i] = NULL; | |
1346 | ||
2f301227 ZY |
1347 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
1348 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1349 | PCI_DMA_FROMDEVICE); | |
1350 | pkt = rxb_addr(rxb); | |
b481de9c | 1351 | |
be1a71a1 JB |
1352 | trace_iwlwifi_dev_rx(priv, pkt, |
1353 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
1354 | ||
b481de9c ZY |
1355 | /* Reclaim a command buffer only if this packet is a response |
1356 | * to a (driver-originated) command. | |
1357 | * If the packet (e.g. Rx frame) originated from uCode, | |
1358 | * there is no command buffer to reclaim. | |
1359 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1360 | * but apparently a few don't get set; catch them here. */ | |
1361 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1362 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1363 | (pkt->hdr.cmd != REPLY_TX); | |
1364 | ||
1365 | /* Based on type of command response or notification, | |
1366 | * handle those that need handling via function in | |
bb8c093b | 1367 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 1368 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
af472a95 | 1369 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i, |
b481de9c | 1370 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
86ddbf62 | 1371 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 1372 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
1373 | } else { |
1374 | /* No handling needed */ | |
2f301227 ZY |
1375 | IWL_DEBUG_RX(priv, |
1376 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
b481de9c ZY |
1377 | r, i, get_cmd_string(pkt->hdr.cmd), |
1378 | pkt->hdr.cmd); | |
1379 | } | |
1380 | ||
29b1b268 ZY |
1381 | /* |
1382 | * XXX: After here, we should always check rxb->page | |
1383 | * against NULL before touching it or its virtual | |
1384 | * memory (pkt). Because some rx_handler might have | |
1385 | * already taken or freed the pages. | |
1386 | */ | |
1387 | ||
b481de9c | 1388 | if (reclaim) { |
2f301227 ZY |
1389 | /* Invoke any callbacks, transfer the buffer to caller, |
1390 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 1391 | * as we reclaim the driver command queue */ |
29b1b268 | 1392 | if (rxb->page) |
732587ab | 1393 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1394 | else |
39aadf8c | 1395 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1396 | } |
1397 | ||
7300515d ZY |
1398 | /* Reuse the page if possible. For notification packets and |
1399 | * SKBs that fail to Rx correctly, add them back into the | |
1400 | * rx_free list for reuse later. */ | |
1401 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1402 | if (rxb->page != NULL) { |
7300515d ZY |
1403 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1404 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1405 | PCI_DMA_FROMDEVICE); | |
1406 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1407 | rxq->free_count++; | |
1408 | } else | |
1409 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1410 | |
b481de9c | 1411 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1412 | |
b481de9c | 1413 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1414 | /* If there are a lot of unused frames, |
1415 | * restock the Rx queue so ucode won't assert. */ | |
1416 | if (fill_rx) { | |
1417 | count++; | |
1418 | if (count >= 8) { | |
7300515d | 1419 | rxq->read = i; |
d14d4440 | 1420 | iwl3945_rx_replenish_now(priv); |
5c0eef96 MA |
1421 | count = 0; |
1422 | } | |
1423 | } | |
b481de9c ZY |
1424 | } |
1425 | ||
1426 | /* Backtrack one entry */ | |
7300515d | 1427 | rxq->read = i; |
d14d4440 AK |
1428 | if (fill_rx) |
1429 | iwl3945_rx_replenish_now(priv); | |
1430 | else | |
1431 | iwl3945_rx_queue_restock(priv); | |
b481de9c ZY |
1432 | } |
1433 | ||
0359facc | 1434 | /* call this function to flush any scheduled tasklet */ |
4a8a4322 | 1435 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 1436 | { |
a96a27f9 | 1437 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1438 | synchronize_irq(priv->pci_dev->irq); |
1439 | tasklet_kill(&priv->irq_tasklet); | |
1440 | } | |
1441 | ||
b481de9c ZY |
1442 | static const char *desc_lookup(int i) |
1443 | { | |
1444 | switch (i) { | |
1445 | case 1: | |
1446 | return "FAIL"; | |
1447 | case 2: | |
1448 | return "BAD_PARAM"; | |
1449 | case 3: | |
1450 | return "BAD_CHECKSUM"; | |
1451 | case 4: | |
1452 | return "NMI_INTERRUPT"; | |
1453 | case 5: | |
1454 | return "SYSASSERT"; | |
1455 | case 6: | |
1456 | return "FATAL_ERROR"; | |
1457 | } | |
1458 | ||
1459 | return "UNKNOWN"; | |
1460 | } | |
1461 | ||
1462 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1463 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1464 | ||
b7a79404 | 1465 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
1466 | { |
1467 | u32 i; | |
1468 | u32 desc, time, count, base, data1; | |
1469 | u32 blink1, blink2, ilink1, ilink2; | |
b481de9c ZY |
1470 | |
1471 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1472 | ||
bb8c093b | 1473 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1474 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
1475 | return; |
1476 | } | |
1477 | ||
b481de9c | 1478 | |
5d49f498 | 1479 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
1480 | |
1481 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
1482 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1483 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1484 | priv->status, count); | |
b481de9c ZY |
1485 | } |
1486 | ||
15b1687c | 1487 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
1488 | "ilink1 nmiPC Line\n"); |
1489 | for (i = ERROR_START_OFFSET; | |
1490 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1491 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 1492 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 1493 | time = |
5d49f498 | 1494 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 1495 | blink1 = |
5d49f498 | 1496 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 1497 | blink2 = |
5d49f498 | 1498 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 1499 | ilink1 = |
5d49f498 | 1500 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 1501 | ilink2 = |
5d49f498 | 1502 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 1503 | data1 = |
5d49f498 | 1504 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 1505 | |
15b1687c WT |
1506 | IWL_ERR(priv, |
1507 | "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
1508 | desc_lookup(desc), desc, time, blink1, blink2, | |
1509 | ilink1, ilink2, data1); | |
be1a71a1 JB |
1510 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0, |
1511 | 0, blink1, blink2, ilink1, ilink2); | |
b481de9c | 1512 | } |
b481de9c ZY |
1513 | } |
1514 | ||
f58177b9 | 1515 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
1516 | |
1517 | /** | |
bb8c093b | 1518 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 1519 | * |
b481de9c | 1520 | */ |
b03d7d0f WYG |
1521 | static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1522 | u32 num_events, u32 mode, | |
1523 | int pos, char **buf, size_t bufsz) | |
b481de9c ZY |
1524 | { |
1525 | u32 i; | |
1526 | u32 base; /* SRAM byte address of event log header */ | |
1527 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1528 | u32 ptr; /* SRAM byte address of log data */ | |
1529 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1530 | unsigned long reg_flags; |
b481de9c ZY |
1531 | |
1532 | if (num_events == 0) | |
b03d7d0f | 1533 | return pos; |
b481de9c ZY |
1534 | |
1535 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1536 | ||
1537 | if (mode == 0) | |
1538 | event_size = 2 * sizeof(u32); | |
1539 | else | |
1540 | event_size = 3 * sizeof(u32); | |
1541 | ||
1542 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1543 | ||
e5854471 BC |
1544 | /* Make sure device is powered up for SRAM reads */ |
1545 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1546 | iwl_grab_nic_access(priv); | |
1547 | ||
1548 | /* Set starting address; reads will auto-increment */ | |
1549 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
1550 | rmb(); | |
1551 | ||
b481de9c ZY |
1552 | /* "time" is actually "data" for mode 0 (no timestamp). |
1553 | * place event id # at far right for easier visual parsing. */ | |
1554 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
1555 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1556 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
15b1687c WT |
1557 | if (mode == 0) { |
1558 | /* data, ev */ | |
b03d7d0f WYG |
1559 | if (bufsz) { |
1560 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1561 | "0x%08x:%04u\n", | |
1562 | time, ev); | |
1563 | } else { | |
1564 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
1565 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1566 | time, ev); | |
1567 | } | |
15b1687c | 1568 | } else { |
e5854471 | 1569 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1570 | if (bufsz) { |
1571 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1572 | "%010u:0x%08x:%04u\n", | |
1573 | time, data, ev); | |
1574 | } else { | |
1575 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", | |
1576 | time, data, ev); | |
1577 | trace_iwlwifi_dev_ucode_event(priv, time, | |
1578 | data, ev); | |
1579 | } | |
b481de9c ZY |
1580 | } |
1581 | } | |
e5854471 BC |
1582 | |
1583 | /* Allow device to power down */ | |
1584 | iwl_release_nic_access(priv); | |
1585 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1586 | return pos; |
b481de9c ZY |
1587 | } |
1588 | ||
c341ddb2 WYG |
1589 | /** |
1590 | * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog | |
1591 | */ | |
b03d7d0f | 1592 | static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
c341ddb2 | 1593 | u32 num_wraps, u32 next_entry, |
b03d7d0f WYG |
1594 | u32 size, u32 mode, |
1595 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
1596 | { |
1597 | /* | |
1598 | * display the newest DEFAULT_LOG_ENTRIES entries | |
1599 | * i.e the entries just before the next ont that uCode would fill. | |
1600 | */ | |
1601 | if (num_wraps) { | |
1602 | if (next_entry < size) { | |
b03d7d0f WYG |
1603 | pos = iwl3945_print_event_log(priv, |
1604 | capacity - (size - next_entry), | |
1605 | size - next_entry, mode, | |
1606 | pos, buf, bufsz); | |
1607 | pos = iwl3945_print_event_log(priv, 0, | |
1608 | next_entry, mode, | |
1609 | pos, buf, bufsz); | |
c341ddb2 | 1610 | } else |
b03d7d0f WYG |
1611 | pos = iwl3945_print_event_log(priv, next_entry - size, |
1612 | size, mode, | |
1613 | pos, buf, bufsz); | |
c341ddb2 WYG |
1614 | } else { |
1615 | if (next_entry < size) | |
b03d7d0f WYG |
1616 | pos = iwl3945_print_event_log(priv, 0, |
1617 | next_entry, mode, | |
1618 | pos, buf, bufsz); | |
c341ddb2 | 1619 | else |
b03d7d0f WYG |
1620 | pos = iwl3945_print_event_log(priv, next_entry - size, |
1621 | size, mode, | |
1622 | pos, buf, bufsz); | |
c341ddb2 | 1623 | } |
b03d7d0f | 1624 | return pos; |
c341ddb2 WYG |
1625 | } |
1626 | ||
84c40692 BC |
1627 | /* For sanity check only. Actual size is determined by uCode, typ. 512 */ |
1628 | #define IWL3945_MAX_EVENT_LOG_SIZE (512) | |
1629 | ||
c341ddb2 WYG |
1630 | #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20) |
1631 | ||
b03d7d0f WYG |
1632 | int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
1633 | char **buf, bool display) | |
b481de9c | 1634 | { |
b481de9c ZY |
1635 | u32 base; /* SRAM byte address of event log header */ |
1636 | u32 capacity; /* event log capacity in # entries */ | |
1637 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1638 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1639 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1640 | u32 size; /* # entries that we'll print */ | |
b03d7d0f WYG |
1641 | int pos = 0; |
1642 | size_t bufsz = 0; | |
b481de9c ZY |
1643 | |
1644 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 1645 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1646 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
937c397e | 1647 | return -EINVAL; |
b481de9c ZY |
1648 | } |
1649 | ||
b481de9c | 1650 | /* event log header */ |
5d49f498 AK |
1651 | capacity = iwl_read_targ_mem(priv, base); |
1652 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1653 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1654 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c | 1655 | |
84c40692 BC |
1656 | if (capacity > IWL3945_MAX_EVENT_LOG_SIZE) { |
1657 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", | |
1658 | capacity, IWL3945_MAX_EVENT_LOG_SIZE); | |
1659 | capacity = IWL3945_MAX_EVENT_LOG_SIZE; | |
1660 | } | |
1661 | ||
1662 | if (next_entry > IWL3945_MAX_EVENT_LOG_SIZE) { | |
1663 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", | |
1664 | next_entry, IWL3945_MAX_EVENT_LOG_SIZE); | |
1665 | next_entry = IWL3945_MAX_EVENT_LOG_SIZE; | |
1666 | } | |
1667 | ||
b481de9c ZY |
1668 | size = num_wraps ? capacity : next_entry; |
1669 | ||
1670 | /* bail out if nothing in log */ | |
1671 | if (size == 0) { | |
15b1687c | 1672 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
b03d7d0f | 1673 | return pos; |
b481de9c ZY |
1674 | } |
1675 | ||
c341ddb2 | 1676 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 1677 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
1678 | size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES) |
1679 | ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size; | |
1680 | #else | |
1681 | size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES) | |
1682 | ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size; | |
1683 | #endif | |
1684 | ||
1685 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n", | |
1686 | size); | |
b481de9c | 1687 | |
c341ddb2 | 1688 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
1689 | if (display) { |
1690 | if (full_log) | |
1691 | bufsz = capacity * 48; | |
1692 | else | |
1693 | bufsz = size * 48; | |
1694 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1695 | if (!*buf) | |
937c397e | 1696 | return -ENOMEM; |
b03d7d0f | 1697 | } |
c341ddb2 WYG |
1698 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
1699 | /* if uCode has wrapped back to top of log, | |
1700 | * start at the oldest entry, | |
1701 | * i.e the next one that uCode would fill. | |
1702 | */ | |
1703 | if (num_wraps) | |
b03d7d0f WYG |
1704 | pos = iwl3945_print_event_log(priv, next_entry, |
1705 | capacity - next_entry, mode, | |
1706 | pos, buf, bufsz); | |
c341ddb2 WYG |
1707 | |
1708 | /* (then/else) start at top of log */ | |
b03d7d0f WYG |
1709 | pos = iwl3945_print_event_log(priv, 0, next_entry, mode, |
1710 | pos, buf, bufsz); | |
c341ddb2 | 1711 | } else |
b03d7d0f WYG |
1712 | pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps, |
1713 | next_entry, size, mode, | |
1714 | pos, buf, bufsz); | |
b7a79404 | 1715 | #else |
b03d7d0f WYG |
1716 | pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps, |
1717 | next_entry, size, mode, | |
1718 | pos, buf, bufsz); | |
c341ddb2 | 1719 | #endif |
b03d7d0f | 1720 | return pos; |
b7a79404 RC |
1721 | } |
1722 | ||
4a8a4322 | 1723 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1724 | { |
1725 | u32 inta, handled = 0; | |
1726 | u32 inta_fh; | |
1727 | unsigned long flags; | |
d08853a3 | 1728 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1729 | u32 inta_mask; |
1730 | #endif | |
1731 | ||
1732 | spin_lock_irqsave(&priv->lock, flags); | |
1733 | ||
1734 | /* Ack/clear/reset pending uCode interrupts. | |
1735 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1736 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
1737 | inta = iwl_read32(priv, CSR_INT); |
1738 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1739 | |
1740 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1741 | * Any new interrupts that happen after this, either while we're | |
1742 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
1743 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1744 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1745 | |
d08853a3 | 1746 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1747 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1748 | /* just for debug */ |
5d49f498 | 1749 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1750 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1751 | inta, inta_mask, inta_fh); |
1752 | } | |
1753 | #endif | |
1754 | ||
2f301227 ZY |
1755 | spin_unlock_irqrestore(&priv->lock, flags); |
1756 | ||
b481de9c ZY |
1757 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1758 | * atomic, make sure that inta covers all the interrupts that | |
1759 | * we've discovered, even if FH interrupt came in just after | |
1760 | * reading CSR_INT. */ | |
6f83eaa1 | 1761 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 1762 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1763 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
1764 | inta |= CSR_INT_BIT_FH_TX; |
1765 | ||
1766 | /* Now service all interrupt bits discovered above. */ | |
1767 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1768 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1769 | |
1770 | /* Tell the device to stop sending interrupts */ | |
ed3b932e | 1771 | iwl_disable_interrupts(priv); |
b481de9c | 1772 | |
86ddbf62 | 1773 | priv->isr_stats.hw++; |
8ccde88a | 1774 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1775 | |
1776 | handled |= CSR_INT_BIT_HW_ERR; | |
1777 | ||
b481de9c ZY |
1778 | return; |
1779 | } | |
1780 | ||
d08853a3 | 1781 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1782 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1783 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
86ddbf62 | 1784 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1785 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1786 | "the frame/frames.\n"); |
86ddbf62 AK |
1787 | priv->isr_stats.sch++; |
1788 | } | |
b481de9c ZY |
1789 | |
1790 | /* Alive notification via Rx interrupt will do the real work */ | |
86ddbf62 | 1791 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1792 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
86ddbf62 AK |
1793 | priv->isr_stats.alive++; |
1794 | } | |
b481de9c ZY |
1795 | } |
1796 | #endif | |
1797 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1798 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1799 | |
b481de9c ZY |
1800 | /* Error detected by uCode */ |
1801 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1802 | IWL_ERR(priv, "Microcode SW error detected. " |
1803 | "Restarting 0x%X.\n", inta); | |
86ddbf62 AK |
1804 | priv->isr_stats.sw++; |
1805 | priv->isr_stats.sw_err = inta; | |
8ccde88a | 1806 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1807 | handled |= CSR_INT_BIT_SW_ERR; |
1808 | } | |
1809 | ||
1810 | /* uCode wakes up after power-down sleep */ | |
1811 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1812 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
141c43a3 | 1813 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
1814 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1815 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1816 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1817 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1818 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1819 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1820 | |
86ddbf62 | 1821 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1822 | handled |= CSR_INT_BIT_WAKEUP; |
1823 | } | |
1824 | ||
1825 | /* All uCode command responses, including Tx command responses, | |
1826 | * Rx "responses" (frame-received notification), and other | |
1827 | * notifications from uCode come through here*/ | |
1828 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 1829 | iwl3945_rx_handle(priv); |
86ddbf62 | 1830 | priv->isr_stats.rx++; |
b481de9c ZY |
1831 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1832 | } | |
1833 | ||
1834 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1835 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
86ddbf62 | 1836 | priv->isr_stats.tx++; |
b481de9c | 1837 | |
5d49f498 | 1838 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
a8b50a0a MA |
1839 | iwl_write_direct32(priv, FH39_TCSR_CREDIT |
1840 | (FH39_SRVC_CHNL), 0x0); | |
b481de9c ZY |
1841 | handled |= CSR_INT_BIT_FH_TX; |
1842 | } | |
1843 | ||
86ddbf62 | 1844 | if (inta & ~handled) { |
15b1687c | 1845 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
86ddbf62 AK |
1846 | priv->isr_stats.unhandled++; |
1847 | } | |
b481de9c | 1848 | |
40cefda9 | 1849 | if (inta & ~priv->inta_mask) { |
39aadf8c | 1850 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1851 | inta & ~priv->inta_mask); |
39aadf8c | 1852 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1853 | } |
1854 | ||
1855 | /* Re-enable all interrupts */ | |
0359facc MA |
1856 | /* only Re-enable if disabled by irq */ |
1857 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
ed3b932e | 1858 | iwl_enable_interrupts(priv); |
b481de9c | 1859 | |
d08853a3 | 1860 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1861 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
5d49f498 AK |
1862 | inta = iwl_read32(priv, CSR_INT); |
1863 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1864 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1865 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1866 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1867 | } | |
1868 | #endif | |
b481de9c ZY |
1869 | } |
1870 | ||
4a8a4322 | 1871 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 1872 | enum ieee80211_band band, |
f9340520 | 1873 | u8 is_active, u8 n_probes, |
bb8c093b | 1874 | struct iwl3945_scan_channel *scan_ch) |
b481de9c | 1875 | { |
4e05c234 | 1876 | struct ieee80211_channel *chan; |
8318d78a | 1877 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 1878 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1879 | u16 passive_dwell = 0; |
1880 | u16 active_dwell = 0; | |
1881 | int added, i; | |
1882 | ||
cbba18c6 | 1883 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 1884 | if (!sband) |
b481de9c ZY |
1885 | return 0; |
1886 | ||
77fecfb8 SO |
1887 | active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); |
1888 | passive_dwell = iwl_get_passive_dwell_time(priv, band); | |
b481de9c | 1889 | |
8f4807a1 AK |
1890 | if (passive_dwell <= active_dwell) |
1891 | passive_dwell = active_dwell + 1; | |
1892 | ||
4e05c234 JB |
1893 | for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) { |
1894 | chan = priv->scan_request->channels[i]; | |
1895 | ||
1896 | if (chan->band != band) | |
182e2e66 JB |
1897 | continue; |
1898 | ||
4e05c234 | 1899 | scan_ch->channel = chan->hw_value; |
b481de9c | 1900 | |
e6148917 | 1901 | ch_info = iwl_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 1902 | if (!is_channel_valid(ch_info)) { |
e1623446 | 1903 | IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", |
b481de9c ZY |
1904 | scan_ch->channel); |
1905 | continue; | |
1906 | } | |
1907 | ||
011a0330 AK |
1908 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
1909 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1910 | /* If passive , set up for auto-switch | |
1911 | * and use long active_dwell time. | |
1912 | */ | |
b481de9c | 1913 | if (!is_active || is_channel_passive(ch_info) || |
4e05c234 | 1914 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 1915 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
1916 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
1917 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
1918 | } else { | |
b481de9c | 1919 | scan_ch->type = 1; /* active */ |
011a0330 | 1920 | } |
b481de9c | 1921 | |
011a0330 AK |
1922 | /* Set direct probe bits. These may be used both for active |
1923 | * scan channels (probes gets sent right away), | |
1924 | * or for passive channels (probes get se sent only after | |
1925 | * hearing clear Rx packet).*/ | |
1926 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
1927 | if (n_probes) | |
0d21044e | 1928 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 AK |
1929 | } else { |
1930 | /* uCode v1 does not allow setting direct probe bits on | |
1931 | * passive channel. */ | |
1932 | if ((scan_ch->type & 1) && n_probes) | |
0d21044e | 1933 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 | 1934 | } |
b481de9c | 1935 | |
9fbab516 | 1936 | /* Set txpower levels to defaults */ |
b481de9c ZY |
1937 | scan_ch->tpc.dsp_atten = 110; |
1938 | /* scan_pwr_info->tpc.dsp_atten; */ | |
1939 | ||
1940 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 1941 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
1942 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
1943 | else { | |
1944 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1945 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 1946 | * power level: |
8a1b0245 | 1947 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
1948 | */ |
1949 | } | |
1950 | ||
e1623446 | 1951 | IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n", |
b481de9c ZY |
1952 | scan_ch->channel, |
1953 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
1954 | (scan_ch->type & 1) ? | |
1955 | active_dwell : passive_dwell); | |
1956 | ||
1957 | scan_ch++; | |
1958 | added++; | |
1959 | } | |
1960 | ||
e1623446 | 1961 | IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added); |
b481de9c ZY |
1962 | return added; |
1963 | } | |
1964 | ||
4a8a4322 | 1965 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
1966 | struct ieee80211_rate *rates) |
1967 | { | |
1968 | int i; | |
1969 | ||
1970 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
1971 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
1972 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
1973 | rates[i].hw_value_short = i; | |
1974 | rates[i].flags = 0; | |
d9829a67 | 1975 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 1976 | /* |
8318d78a | 1977 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 1978 | */ |
bb8c093b | 1979 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 1980 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 1981 | } |
b481de9c ZY |
1982 | } |
1983 | } | |
1984 | ||
b481de9c ZY |
1985 | /****************************************************************************** |
1986 | * | |
1987 | * uCode download functions | |
1988 | * | |
1989 | ******************************************************************************/ | |
1990 | ||
4a8a4322 | 1991 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1992 | { |
98c92211 TW |
1993 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1994 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1995 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1996 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1997 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1998 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1999 | } |
2000 | ||
2001 | /** | |
bb8c093b | 2002 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2003 | * looking at all data. |
2004 | */ | |
4a8a4322 | 2005 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2006 | { |
2007 | u32 val; | |
2008 | u32 save_len = len; | |
2009 | int rc = 0; | |
2010 | u32 errcnt; | |
2011 | ||
e1623446 | 2012 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2013 | |
5d49f498 | 2014 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2015 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
2016 | |
2017 | errcnt = 0; | |
2018 | for (; len > 0; len -= sizeof(u32), image++) { | |
2019 | /* read data comes through single port, auto-incr addr */ | |
2020 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2021 | * if IWL_DL_IO is set */ | |
5d49f498 | 2022 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 2023 | if (val != le32_to_cpu(*image)) { |
15b1687c | 2024 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2025 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2026 | save_len - len, val, le32_to_cpu(*image)); | |
2027 | rc = -EIO; | |
2028 | errcnt++; | |
2029 | if (errcnt >= 20) | |
2030 | break; | |
2031 | } | |
2032 | } | |
2033 | ||
b481de9c ZY |
2034 | |
2035 | if (!errcnt) | |
e1623446 TW |
2036 | IWL_DEBUG_INFO(priv, |
2037 | "ucode image in INSTRUCTION memory is good\n"); | |
b481de9c ZY |
2038 | |
2039 | return rc; | |
2040 | } | |
2041 | ||
2042 | ||
2043 | /** | |
bb8c093b | 2044 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2045 | * using sample data 100 bytes apart. If these sample points are good, |
2046 | * it's a pretty good bet that everything between them is good, too. | |
2047 | */ | |
4a8a4322 | 2048 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2049 | { |
2050 | u32 val; | |
2051 | int rc = 0; | |
2052 | u32 errcnt = 0; | |
2053 | u32 i; | |
2054 | ||
e1623446 | 2055 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2056 | |
b481de9c ZY |
2057 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
2058 | /* read data comes through single port, auto-incr addr */ | |
2059 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2060 | * if IWL_DL_IO is set */ | |
5d49f498 | 2061 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2062 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 2063 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
2064 | if (val != le32_to_cpu(*image)) { |
2065 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 2066 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2067 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2068 | i, val, *image); | |
2069 | #endif | |
2070 | rc = -EIO; | |
2071 | errcnt++; | |
2072 | if (errcnt >= 3) | |
2073 | break; | |
2074 | } | |
2075 | } | |
2076 | ||
b481de9c ZY |
2077 | return rc; |
2078 | } | |
2079 | ||
2080 | ||
2081 | /** | |
bb8c093b | 2082 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
2083 | * and verify its contents |
2084 | */ | |
4a8a4322 | 2085 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
2086 | { |
2087 | __le32 *image; | |
2088 | u32 len; | |
2089 | int rc = 0; | |
2090 | ||
2091 | /* Try bootstrap */ | |
2092 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2093 | len = priv->ucode_boot.len; | |
bb8c093b | 2094 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2095 | if (rc == 0) { |
e1623446 | 2096 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b481de9c ZY |
2097 | return 0; |
2098 | } | |
2099 | ||
2100 | /* Try initialize */ | |
2101 | image = (__le32 *)priv->ucode_init.v_addr; | |
2102 | len = priv->ucode_init.len; | |
bb8c093b | 2103 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2104 | if (rc == 0) { |
e1623446 | 2105 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b481de9c ZY |
2106 | return 0; |
2107 | } | |
2108 | ||
2109 | /* Try runtime/protocol */ | |
2110 | image = (__le32 *)priv->ucode_code.v_addr; | |
2111 | len = priv->ucode_code.len; | |
bb8c093b | 2112 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2113 | if (rc == 0) { |
e1623446 | 2114 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b481de9c ZY |
2115 | return 0; |
2116 | } | |
2117 | ||
15b1687c | 2118 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 2119 | |
9fbab516 BC |
2120 | /* Since nothing seems to match, show first several data entries in |
2121 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2122 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
2123 | image = (__le32 *)priv->ucode_boot.v_addr; |
2124 | len = priv->ucode_boot.len; | |
bb8c093b | 2125 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
2126 | |
2127 | return rc; | |
2128 | } | |
2129 | ||
4a8a4322 | 2130 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
2131 | { |
2132 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 2133 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
2134 | } |
2135 | ||
2136 | /** | |
bb8c093b | 2137 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
2138 | * |
2139 | * Copy into buffers for card to fetch via bus-mastering | |
2140 | */ | |
4a8a4322 | 2141 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 2142 | { |
cc0f555d | 2143 | const struct iwl_ucode_header *ucode; |
a0987a8d | 2144 | int ret = -EINVAL, index; |
b481de9c ZY |
2145 | const struct firmware *ucode_raw; |
2146 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
2147 | const char *name_pre = priv->cfg->fw_name_pre; |
2148 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
2149 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
2150 | char buf[25]; | |
b481de9c ZY |
2151 | u8 *src; |
2152 | size_t len; | |
a0987a8d | 2153 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
2154 | |
2155 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
2156 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
2157 | for (index = api_max; index >= api_min; index--) { |
2158 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
2159 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
2160 | if (ret < 0) { | |
15b1687c | 2161 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
2162 | buf, ret); |
2163 | if (ret == -ENOENT) | |
2164 | continue; | |
2165 | else | |
2166 | goto error; | |
2167 | } else { | |
2168 | if (index < api_max) | |
15b1687c WT |
2169 | IWL_ERR(priv, "Loaded firmware %s, " |
2170 | "which is deprecated. " | |
2171 | " Please use API v%u instead.\n", | |
a0987a8d | 2172 | buf, api_max); |
e1623446 TW |
2173 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file " |
2174 | "(%zd bytes) from disk\n", | |
a0987a8d RC |
2175 | buf, ucode_raw->size); |
2176 | break; | |
2177 | } | |
b481de9c ZY |
2178 | } |
2179 | ||
a0987a8d RC |
2180 | if (ret < 0) |
2181 | goto error; | |
b481de9c ZY |
2182 | |
2183 | /* Make sure that we got at least our header! */ | |
cc0f555d | 2184 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { |
15b1687c | 2185 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 2186 | ret = -EINVAL; |
b481de9c ZY |
2187 | goto err_release; |
2188 | } | |
2189 | ||
2190 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 2191 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 2192 | |
c02b3acd | 2193 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 2194 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
2195 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); |
2196 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
2197 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
2198 | init_data_size = | |
2199 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
2200 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
2201 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 2202 | |
a0987a8d RC |
2203 | /* api_ver should match the api version forming part of the |
2204 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 2205 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
2206 | |
2207 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 2208 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2209 | "Driver supports v%u, firmware is v%u.\n", |
2210 | api_max, api_ver); | |
2211 | priv->ucode_ver = 0; | |
2212 | ret = -EINVAL; | |
2213 | goto err_release; | |
2214 | } | |
2215 | if (api_ver != api_max) | |
15b1687c | 2216 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
2217 | "got %u. New firmware can be obtained " |
2218 | "from http://www.intellinuxwireless.org.\n", | |
2219 | api_max, api_ver); | |
2220 | ||
978785a3 TW |
2221 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
2222 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2223 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2224 | IWL_UCODE_API(priv->ucode_ver), | |
2225 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2226 | ||
5ebeb5a6 RC |
2227 | snprintf(priv->hw->wiphy->fw_version, |
2228 | sizeof(priv->hw->wiphy->fw_version), | |
2229 | "%u.%u.%u.%u", | |
2230 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2231 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2232 | IWL_UCODE_API(priv->ucode_ver), | |
2233 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2234 | ||
e1623446 | 2235 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 2236 | priv->ucode_ver); |
e1623446 TW |
2237 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
2238 | inst_size); | |
2239 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", | |
2240 | data_size); | |
2241 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", | |
2242 | init_size); | |
2243 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", | |
2244 | init_data_size); | |
2245 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", | |
2246 | boot_size); | |
b481de9c | 2247 | |
a0987a8d | 2248 | |
b481de9c | 2249 | /* Verify size of file vs. image size info in file's header */ |
cc0f555d | 2250 | if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) + |
b481de9c ZY |
2251 | inst_size + data_size + init_size + |
2252 | init_data_size + boot_size) { | |
2253 | ||
cc0f555d JS |
2254 | IWL_DEBUG_INFO(priv, |
2255 | "uCode file size %zd does not match expected size\n", | |
2256 | ucode_raw->size); | |
90e759d1 | 2257 | ret = -EINVAL; |
b481de9c ZY |
2258 | goto err_release; |
2259 | } | |
2260 | ||
2261 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 2262 | if (inst_size > IWL39_MAX_INST_SIZE) { |
e1623446 | 2263 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
2264 | inst_size); |
2265 | ret = -EINVAL; | |
b481de9c ZY |
2266 | goto err_release; |
2267 | } | |
2268 | ||
250bdd21 | 2269 | if (data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 | 2270 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
2271 | data_size); |
2272 | ret = -EINVAL; | |
b481de9c ZY |
2273 | goto err_release; |
2274 | } | |
250bdd21 | 2275 | if (init_size > IWL39_MAX_INST_SIZE) { |
e1623446 TW |
2276 | IWL_DEBUG_INFO(priv, |
2277 | "uCode init instr len %d too large to fit in\n", | |
90e759d1 TW |
2278 | init_size); |
2279 | ret = -EINVAL; | |
b481de9c ZY |
2280 | goto err_release; |
2281 | } | |
250bdd21 | 2282 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 TW |
2283 | IWL_DEBUG_INFO(priv, |
2284 | "uCode init data len %d too large to fit in\n", | |
90e759d1 TW |
2285 | init_data_size); |
2286 | ret = -EINVAL; | |
b481de9c ZY |
2287 | goto err_release; |
2288 | } | |
250bdd21 | 2289 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
e1623446 TW |
2290 | IWL_DEBUG_INFO(priv, |
2291 | "uCode boot instr len %d too large to fit in\n", | |
90e759d1 TW |
2292 | boot_size); |
2293 | ret = -EINVAL; | |
b481de9c ZY |
2294 | goto err_release; |
2295 | } | |
2296 | ||
2297 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2298 | ||
2299 | /* Runtime instructions and 2 copies of data: | |
2300 | * 1) unmodified from disk | |
2301 | * 2) backup cache for save/restore during power-downs */ | |
2302 | priv->ucode_code.len = inst_size; | |
98c92211 | 2303 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
2304 | |
2305 | priv->ucode_data.len = data_size; | |
98c92211 | 2306 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
2307 | |
2308 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 2309 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2310 | |
90e759d1 TW |
2311 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2312 | !priv->ucode_data_backup.v_addr) | |
2313 | goto err_pci_alloc; | |
b481de9c ZY |
2314 | |
2315 | /* Initialization instructions and data */ | |
90e759d1 TW |
2316 | if (init_size && init_data_size) { |
2317 | priv->ucode_init.len = init_size; | |
98c92211 | 2318 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
2319 | |
2320 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 2321 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2322 | |
2323 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2324 | goto err_pci_alloc; | |
2325 | } | |
b481de9c ZY |
2326 | |
2327 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
2328 | if (boot_size) { |
2329 | priv->ucode_boot.len = boot_size; | |
98c92211 | 2330 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2331 | |
90e759d1 TW |
2332 | if (!priv->ucode_boot.v_addr) |
2333 | goto err_pci_alloc; | |
2334 | } | |
b481de9c ZY |
2335 | |
2336 | /* Copy images into buffers for card's bus-master reads ... */ | |
2337 | ||
2338 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 2339 | len = inst_size; |
e1623446 TW |
2340 | IWL_DEBUG_INFO(priv, |
2341 | "Copying (but not loading) uCode instr len %zd\n", len); | |
b481de9c | 2342 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
2343 | src += len; |
2344 | ||
e1623446 | 2345 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2346 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2347 | ||
2348 | /* Runtime data (2nd block) | |
bb8c093b | 2349 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
cc0f555d | 2350 | len = data_size; |
e1623446 TW |
2351 | IWL_DEBUG_INFO(priv, |
2352 | "Copying (but not loading) uCode data len %zd\n", len); | |
b481de9c ZY |
2353 | memcpy(priv->ucode_data.v_addr, src, len); |
2354 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 2355 | src += len; |
b481de9c ZY |
2356 | |
2357 | /* Initialization instructions (3rd block) */ | |
2358 | if (init_size) { | |
cc0f555d | 2359 | len = init_size; |
e1623446 TW |
2360 | IWL_DEBUG_INFO(priv, |
2361 | "Copying (but not loading) init instr len %zd\n", len); | |
b481de9c | 2362 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 2363 | src += len; |
b481de9c ZY |
2364 | } |
2365 | ||
2366 | /* Initialization data (4th block) */ | |
2367 | if (init_data_size) { | |
cc0f555d | 2368 | len = init_data_size; |
e1623446 TW |
2369 | IWL_DEBUG_INFO(priv, |
2370 | "Copying (but not loading) init data len %zd\n", len); | |
b481de9c | 2371 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 2372 | src += len; |
b481de9c ZY |
2373 | } |
2374 | ||
2375 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 2376 | len = boot_size; |
e1623446 TW |
2377 | IWL_DEBUG_INFO(priv, |
2378 | "Copying (but not loading) boot instr len %zd\n", len); | |
b481de9c ZY |
2379 | memcpy(priv->ucode_boot.v_addr, src, len); |
2380 | ||
2381 | /* We have our copies now, allow OS release its copies */ | |
2382 | release_firmware(ucode_raw); | |
2383 | return 0; | |
2384 | ||
2385 | err_pci_alloc: | |
15b1687c | 2386 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 2387 | ret = -ENOMEM; |
bb8c093b | 2388 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
2389 | |
2390 | err_release: | |
2391 | release_firmware(ucode_raw); | |
2392 | ||
2393 | error: | |
90e759d1 | 2394 | return ret; |
b481de9c ZY |
2395 | } |
2396 | ||
2397 | ||
2398 | /** | |
bb8c093b | 2399 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
2400 | * |
2401 | * Tell initialization uCode where to find runtime uCode. | |
2402 | * | |
2403 | * BSM registers initially contain pointers to initialization uCode. | |
2404 | * We need to replace them to load runtime uCode inst and data, | |
2405 | * and to save runtime data when powering down. | |
2406 | */ | |
4a8a4322 | 2407 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
2408 | { |
2409 | dma_addr_t pinst; | |
2410 | dma_addr_t pdata; | |
b481de9c ZY |
2411 | |
2412 | /* bits 31:0 for 3945 */ | |
2413 | pinst = priv->ucode_code.p_addr; | |
2414 | pdata = priv->ucode_data_backup.p_addr; | |
2415 | ||
b481de9c | 2416 | /* Tell bootstrap uCode where to find image to load */ |
5d49f498 AK |
2417 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
2418 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2419 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
2420 | priv->ucode_data.len); |
2421 | ||
a96a27f9 | 2422 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 2423 | * that all new ptr/size info is in place */ |
5d49f498 | 2424 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
2425 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
2426 | ||
e1623446 | 2427 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
b481de9c | 2428 | |
a8b50a0a | 2429 | return 0; |
b481de9c ZY |
2430 | } |
2431 | ||
2432 | /** | |
bb8c093b | 2433 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
2434 | * |
2435 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2436 | * | |
b481de9c | 2437 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 2438 | */ |
4a8a4322 | 2439 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2440 | { |
2441 | /* Check alive response for "valid" sign from uCode */ | |
2442 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
2443 | /* We had an error bringing up the hardware, so take it | |
2444 | * all the way back down so we can try again */ | |
e1623446 | 2445 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
b481de9c ZY |
2446 | goto restart; |
2447 | } | |
2448 | ||
2449 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2450 | * This is a paranoid check, because we would not have gotten the | |
2451 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 2452 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2453 | /* Runtime instruction load was bad; |
2454 | * take it all the way back down so we can try again */ | |
e1623446 | 2455 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
b481de9c ZY |
2456 | goto restart; |
2457 | } | |
2458 | ||
2459 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2460 | * load and launch runtime uCode, which will send us another "Alive" | |
2461 | * notification. */ | |
e1623446 | 2462 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
bb8c093b | 2463 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
2464 | /* Runtime instruction load won't happen; |
2465 | * take it all the way back down so we can try again */ | |
e1623446 | 2466 | IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n"); |
b481de9c ZY |
2467 | goto restart; |
2468 | } | |
2469 | return; | |
2470 | ||
2471 | restart: | |
2472 | queue_work(priv->workqueue, &priv->restart); | |
2473 | } | |
2474 | ||
b481de9c | 2475 | /** |
bb8c093b | 2476 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2477 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 2478 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 2479 | */ |
4a8a4322 | 2480 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c | 2481 | { |
b481de9c ZY |
2482 | int thermal_spin = 0; |
2483 | u32 rfkill; | |
2484 | ||
e1623446 | 2485 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2486 | |
2487 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2488 | /* We had an error bringing up the hardware, so take it | |
2489 | * all the way back down so we can try again */ | |
e1623446 | 2490 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2491 | goto restart; |
2492 | } | |
2493 | ||
2494 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2495 | * This is a paranoid check, because we would not have gotten the | |
2496 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 2497 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2498 | /* Runtime instruction load was bad; |
2499 | * take it all the way back down so we can try again */ | |
e1623446 | 2500 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2501 | goto restart; |
2502 | } | |
2503 | ||
c587de0b | 2504 | iwl_clear_stations_table(priv); |
b481de9c | 2505 | |
5d49f498 | 2506 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
e1623446 | 2507 | IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); |
b481de9c ZY |
2508 | |
2509 | if (rfkill & 0x1) { | |
2510 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 2511 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 2512 | * sensor in adapter to kick in */ |
bb8c093b | 2513 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
2514 | thermal_spin++; |
2515 | udelay(10); | |
2516 | } | |
2517 | ||
2518 | if (thermal_spin) | |
e1623446 | 2519 | IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n", |
b481de9c ZY |
2520 | thermal_spin * 10); |
2521 | } else | |
2522 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2523 | ||
9fbab516 | 2524 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
2525 | set_bit(STATUS_ALIVE, &priv->status); |
2526 | ||
775a6e27 | 2527 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2528 | return; |
2529 | ||
36d6825b | 2530 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
2531 | |
2532 | priv->active_rate = priv->rates_mask; | |
2533 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
2534 | ||
4d6ccbf5 | 2535 | iwl_power_update_mode(priv, true); |
b481de9c | 2536 | |
8ccde88a | 2537 | if (iwl_is_associated(priv)) { |
bb8c093b | 2538 | struct iwl3945_rxon_cmd *active_rxon = |
8ccde88a | 2539 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); |
b481de9c | 2540 | |
8a9b9926 | 2541 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2542 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2543 | } else { | |
2544 | /* Initialize our rx_config data */ | |
8ccde88a | 2545 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
b481de9c ZY |
2546 | } |
2547 | ||
9fbab516 | 2548 | /* Configure Bluetooth device coexistence support */ |
17f841cd | 2549 | iwl_send_bt_config(priv); |
b481de9c ZY |
2550 | |
2551 | /* Configure the adapter for unassociated operation */ | |
e0158e61 | 2552 | iwlcore_commit_rxon(priv); |
b481de9c | 2553 | |
b481de9c ZY |
2554 | iwl3945_reg_txpower_periodic(priv); |
2555 | ||
e932a609 | 2556 | iwl_leds_init(priv); |
fe00b5a5 | 2557 | |
e1623446 | 2558 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2559 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2560 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2561 | |
9bdf5eca MA |
2562 | /* reassociate for ADHOC mode */ |
2563 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
2564 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
2565 | priv->vif); | |
2566 | if (beacon) | |
9944b938 | 2567 | iwl_mac_beacon_update(priv->hw, beacon); |
9bdf5eca MA |
2568 | } |
2569 | ||
f45c2714 | 2570 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
727882d6 | 2571 | iwl_set_mode(priv, priv->iw_mode); |
f45c2714 | 2572 | |
b481de9c ZY |
2573 | return; |
2574 | ||
2575 | restart: | |
2576 | queue_work(priv->workqueue, &priv->restart); | |
2577 | } | |
2578 | ||
4a8a4322 | 2579 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2580 | |
4a8a4322 | 2581 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2582 | { |
2583 | unsigned long flags; | |
2584 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
2585 | struct ieee80211_conf *conf = NULL; | |
2586 | ||
e1623446 | 2587 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c ZY |
2588 | |
2589 | conf = ieee80211_get_hw_conf(priv->hw); | |
2590 | ||
2591 | if (!exit_pending) | |
2592 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2593 | ||
c587de0b | 2594 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2595 | |
2596 | /* Unblock any waiting calls */ | |
2597 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2598 | ||
b481de9c ZY |
2599 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2600 | * exiting the module */ | |
2601 | if (!exit_pending) | |
2602 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2603 | ||
2604 | /* stop and reset the on-board processor */ | |
5d49f498 | 2605 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2606 | |
2607 | /* tell the device to stop sending interrupts */ | |
0359facc | 2608 | spin_lock_irqsave(&priv->lock, flags); |
ed3b932e | 2609 | iwl_disable_interrupts(priv); |
0359facc MA |
2610 | spin_unlock_irqrestore(&priv->lock, flags); |
2611 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2612 | |
2613 | if (priv->mac80211_registered) | |
2614 | ieee80211_stop_queues(priv->hw); | |
2615 | ||
bb8c093b | 2616 | /* If we have not previously called iwl3945_init() then |
6da3a13e | 2617 | * clear all bits but the RF Kill bits and return */ |
775a6e27 | 2618 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2619 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2620 | STATUS_RF_KILL_HW | | |
9788864e RC |
2621 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2622 | STATUS_GEO_CONFIGURED | | |
ebef2008 AK |
2623 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2624 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2625 | goto exit; |
2626 | } | |
2627 | ||
6da3a13e | 2628 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2629 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2630 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2631 | STATUS_RF_KILL_HW | | |
9788864e RC |
2632 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2633 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2634 | test_bit(STATUS_FW_ERROR, &priv->status) << |
ebef2008 AK |
2635 | STATUS_FW_ERROR | |
2636 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2637 | STATUS_EXIT_PENDING; | |
b481de9c | 2638 | |
bb8c093b CH |
2639 | iwl3945_hw_txq_ctx_stop(priv); |
2640 | iwl3945_hw_rxq_stop(priv); | |
b481de9c | 2641 | |
309e731a BC |
2642 | /* Power-down device's busmaster DMA clocks */ |
2643 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2644 | udelay(5); |
2645 | ||
4d2ccdb9 BC |
2646 | /* Stop the device, and put it in low power state */ |
2647 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
e9414b6b | 2648 | |
b481de9c | 2649 | exit: |
3d24a9f7 | 2650 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2651 | |
2652 | if (priv->ibss_beacon) | |
2653 | dev_kfree_skb(priv->ibss_beacon); | |
2654 | priv->ibss_beacon = NULL; | |
2655 | ||
2656 | /* clear out any free frames */ | |
bb8c093b | 2657 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
2658 | } |
2659 | ||
4a8a4322 | 2660 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2661 | { |
2662 | mutex_lock(&priv->mutex); | |
bb8c093b | 2663 | __iwl3945_down(priv); |
b481de9c | 2664 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2665 | |
bb8c093b | 2666 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
2667 | } |
2668 | ||
2669 | #define MAX_HW_RESTARTS 5 | |
2670 | ||
4a8a4322 | 2671 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
2672 | { |
2673 | int rc, i; | |
2674 | ||
2675 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2676 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2677 | return -EIO; |
2678 | } | |
2679 | ||
e903fbd4 | 2680 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2681 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
2682 | return -EIO; |
2683 | } | |
2684 | ||
e655b9f0 | 2685 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 2686 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
2687 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2688 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2689 | else { | |
2690 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6da3a13e WYG |
2691 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
2692 | return -ENODEV; | |
b481de9c | 2693 | } |
80fcc9e2 | 2694 | |
5d49f498 | 2695 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2696 | |
bb8c093b | 2697 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 2698 | if (rc) { |
15b1687c | 2699 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
2700 | return rc; |
2701 | } | |
2702 | ||
2703 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2704 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2705 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2706 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2707 | ||
2708 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 2709 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
ed3b932e | 2710 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2711 | |
2712 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2713 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2714 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2715 | |
2716 | /* Copy original ucode data image from disk into backup cache. | |
2717 | * This will be used to initialize the on-board processor's | |
2718 | * data SRAM for a clean start when the runtime program first loads. */ | |
2719 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2720 | priv->ucode_data.len); |
b481de9c | 2721 | |
e655b9f0 ZY |
2722 | /* We return success when we resume from suspend and rf_kill is on. */ |
2723 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2724 | return 0; | |
2725 | ||
b481de9c ZY |
2726 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2727 | ||
c587de0b | 2728 | iwl_clear_stations_table(priv); |
b481de9c ZY |
2729 | |
2730 | /* load bootstrap state machine, | |
2731 | * load bootstrap program into processor's memory, | |
2732 | * prepare to load the "initialize" uCode */ | |
0164b9b4 | 2733 | priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
2734 | |
2735 | if (rc) { | |
15b1687c WT |
2736 | IWL_ERR(priv, |
2737 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
2738 | continue; |
2739 | } | |
2740 | ||
2741 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 2742 | iwl3945_nic_start(priv); |
b481de9c | 2743 | |
e1623446 | 2744 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2745 | |
2746 | return 0; | |
2747 | } | |
2748 | ||
2749 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 2750 | __iwl3945_down(priv); |
ebef2008 | 2751 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2752 | |
2753 | /* tried to restart and config the device for as long as our | |
2754 | * patience could withstand */ | |
15b1687c | 2755 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2756 | return -EIO; |
2757 | } | |
2758 | ||
2759 | ||
2760 | /***************************************************************************** | |
2761 | * | |
2762 | * Workqueue callbacks | |
2763 | * | |
2764 | *****************************************************************************/ | |
2765 | ||
bb8c093b | 2766 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2767 | { |
4a8a4322 AK |
2768 | struct iwl_priv *priv = |
2769 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2770 | |
2771 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2772 | return; | |
2773 | ||
2774 | mutex_lock(&priv->mutex); | |
bb8c093b | 2775 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
2776 | mutex_unlock(&priv->mutex); |
2777 | } | |
2778 | ||
bb8c093b | 2779 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 2780 | { |
4a8a4322 AK |
2781 | struct iwl_priv *priv = |
2782 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2783 | |
2784 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2785 | return; | |
2786 | ||
2787 | mutex_lock(&priv->mutex); | |
bb8c093b | 2788 | iwl3945_alive_start(priv); |
b481de9c ZY |
2789 | mutex_unlock(&priv->mutex); |
2790 | } | |
2791 | ||
743cdf1b BC |
2792 | /* |
2793 | * 3945 cannot interrupt driver when hardware rf kill switch toggles; | |
2794 | * driver must poll CSR_GP_CNTRL_REG register for change. This register | |
2795 | * *is* readable even when device has been SW_RESET into low power mode | |
2796 | * (e.g. during RF KILL). | |
2797 | */ | |
2663516d HS |
2798 | static void iwl3945_rfkill_poll(struct work_struct *data) |
2799 | { | |
2800 | struct iwl_priv *priv = | |
2801 | container_of(data, struct iwl_priv, rfkill_poll.work); | |
743cdf1b BC |
2802 | bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status); |
2803 | bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL) | |
2804 | & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
2663516d | 2805 | |
743cdf1b BC |
2806 | if (new_rfkill != old_rfkill) { |
2807 | if (new_rfkill) | |
2808 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2809 | else | |
2810 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2663516d | 2811 | |
743cdf1b BC |
2812 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill); |
2813 | ||
2814 | IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n", | |
2815 | new_rfkill ? "disable radio" : "enable radio"); | |
2816 | } | |
2663516d | 2817 | |
743cdf1b BC |
2818 | /* Keep this running, even if radio now enabled. This will be |
2819 | * cancelled in mac_start() if system decides to start again */ | |
2663516d HS |
2820 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, |
2821 | round_jiffies_relative(2 * HZ)); | |
2822 | ||
2823 | } | |
2824 | ||
b481de9c | 2825 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) |
bb8c093b | 2826 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 2827 | { |
4a8a4322 AK |
2828 | struct iwl_priv *priv = |
2829 | container_of(data, struct iwl_priv, request_scan); | |
c2d79b48 | 2830 | struct iwl_host_cmd cmd = { |
b481de9c | 2831 | .id = REPLY_SCAN_CMD, |
bb8c093b | 2832 | .len = sizeof(struct iwl3945_scan_cmd), |
c2acea8e | 2833 | .flags = CMD_SIZE_HUGE, |
b481de9c ZY |
2834 | }; |
2835 | int rc = 0; | |
bb8c093b | 2836 | struct iwl3945_scan_cmd *scan; |
b481de9c | 2837 | struct ieee80211_conf *conf = NULL; |
1ecf9fc1 | 2838 | u8 n_probes = 0; |
8318d78a | 2839 | enum ieee80211_band band; |
1ecf9fc1 | 2840 | bool is_active = false; |
b481de9c ZY |
2841 | |
2842 | conf = ieee80211_get_hw_conf(priv->hw); | |
2843 | ||
2844 | mutex_lock(&priv->mutex); | |
2845 | ||
fbc9f97b RC |
2846 | cancel_delayed_work(&priv->scan_check); |
2847 | ||
775a6e27 | 2848 | if (!iwl_is_ready(priv)) { |
39aadf8c | 2849 | IWL_WARN(priv, "request scan called when driver not ready.\n"); |
b481de9c ZY |
2850 | goto done; |
2851 | } | |
2852 | ||
a96a27f9 | 2853 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
2854 | * was given the chance to run... */ |
2855 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
2856 | goto done; | |
2857 | ||
2858 | /* This should never be called or scheduled if there is currently | |
2859 | * a scan active in the hardware. */ | |
2860 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
e1623446 TW |
2861 | IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests " |
2862 | "Ignoring second request.\n"); | |
b481de9c ZY |
2863 | rc = -EIO; |
2864 | goto done; | |
2865 | } | |
2866 | ||
2867 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 2868 | IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n"); |
b481de9c ZY |
2869 | goto done; |
2870 | } | |
2871 | ||
2872 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
e1623446 TW |
2873 | IWL_DEBUG_HC(priv, |
2874 | "Scan request while abort pending. Queuing.\n"); | |
b481de9c ZY |
2875 | goto done; |
2876 | } | |
2877 | ||
775a6e27 | 2878 | if (iwl_is_rfkill(priv)) { |
e1623446 | 2879 | IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n"); |
b481de9c ZY |
2880 | goto done; |
2881 | } | |
2882 | ||
2883 | if (!test_bit(STATUS_READY, &priv->status)) { | |
e1623446 TW |
2884 | IWL_DEBUG_HC(priv, |
2885 | "Scan request while uninitialized. Queuing.\n"); | |
b481de9c ZY |
2886 | goto done; |
2887 | } | |
2888 | ||
2889 | if (!priv->scan_bands) { | |
e1623446 | 2890 | IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n"); |
b481de9c ZY |
2891 | goto done; |
2892 | } | |
2893 | ||
805cee5b WT |
2894 | if (!priv->scan) { |
2895 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
b481de9c | 2896 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
805cee5b | 2897 | if (!priv->scan) { |
b481de9c ZY |
2898 | rc = -ENOMEM; |
2899 | goto done; | |
2900 | } | |
2901 | } | |
805cee5b | 2902 | scan = priv->scan; |
bb8c093b | 2903 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
2904 | |
2905 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
2906 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
2907 | ||
8ccde88a | 2908 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
2909 | u16 interval = 0; |
2910 | u32 extra; | |
2911 | u32 suspend_time = 100; | |
2912 | u32 scan_suspend_time = 100; | |
2913 | unsigned long flags; | |
2914 | ||
e1623446 | 2915 | IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); |
b481de9c ZY |
2916 | |
2917 | spin_lock_irqsave(&priv->lock, flags); | |
2918 | interval = priv->beacon_int; | |
2919 | spin_unlock_irqrestore(&priv->lock, flags); | |
2920 | ||
2921 | scan->suspend_time = 0; | |
15e869d8 | 2922 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
2923 | if (!interval) |
2924 | interval = suspend_time; | |
2925 | /* | |
2926 | * suspend time format: | |
2927 | * 0-19: beacon interval in usec (time before exec.) | |
2928 | * 20-23: 0 | |
2929 | * 24-31: number of beacons (suspend between channels) | |
2930 | */ | |
2931 | ||
2932 | extra = (suspend_time / interval) << 24; | |
2933 | scan_suspend_time = 0xFF0FFFFF & | |
2934 | (extra | ((suspend_time % interval) * 1024)); | |
2935 | ||
2936 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
e1623446 | 2937 | IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", |
b481de9c ZY |
2938 | scan_suspend_time, interval); |
2939 | } | |
2940 | ||
1ecf9fc1 JB |
2941 | if (priv->scan_request->n_ssids) { |
2942 | int i, p = 0; | |
2943 | IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); | |
2944 | for (i = 0; i < priv->scan_request->n_ssids; i++) { | |
2945 | /* always does wildcard anyway */ | |
2946 | if (!priv->scan_request->ssids[i].ssid_len) | |
2947 | continue; | |
2948 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
2949 | scan->direct_scan[p].len = | |
2950 | priv->scan_request->ssids[i].ssid_len; | |
2951 | memcpy(scan->direct_scan[p].ssid, | |
2952 | priv->scan_request->ssids[i].ssid, | |
2953 | priv->scan_request->ssids[i].ssid_len); | |
2954 | n_probes++; | |
2955 | p++; | |
2956 | } | |
2957 | is_active = true; | |
f9340520 | 2958 | } else |
1ecf9fc1 | 2959 | IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n"); |
b481de9c ZY |
2960 | |
2961 | /* We don't build a direct scan probe request; the uCode will do | |
2962 | * that based on the direct_mask added to each channel entry */ | |
b481de9c | 2963 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 2964 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2965 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2966 | ||
2967 | /* flags + rate selection */ | |
2968 | ||
66b5004d | 2969 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
2970 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
2971 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
2972 | scan->good_CRC_th = 0; | |
8318d78a | 2973 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 2974 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c | 2975 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
b097ad29 JB |
2976 | /* |
2977 | * If active scaning is requested but a certain channel | |
2978 | * is marked passive, we can do active scanning if we | |
2979 | * detect transmissions. | |
2980 | */ | |
2981 | scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0; | |
8318d78a | 2982 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 2983 | } else { |
39aadf8c | 2984 | IWL_WARN(priv, "Invalid scan band count\n"); |
b481de9c ZY |
2985 | goto done; |
2986 | } | |
2987 | ||
77fecfb8 | 2988 | scan->tx_cmd.len = cpu_to_le16( |
1ecf9fc1 JB |
2989 | iwl_fill_probe_req(priv, |
2990 | (struct ieee80211_mgmt *)scan->data, | |
2991 | priv->scan_request->ie, | |
2992 | priv->scan_request->ie_len, | |
2993 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
77fecfb8 | 2994 | |
b481de9c ZY |
2995 | /* select Rx antennas */ |
2996 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
2997 | ||
279b05d4 | 2998 | if (iwl_is_monitor_mode(priv)) |
b481de9c ZY |
2999 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
3000 | ||
f9340520 | 3001 | scan->channel_count = |
1ecf9fc1 | 3002 | iwl3945_get_channels_for_scan(priv, band, is_active, n_probes, |
f9340520 | 3003 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); |
b481de9c | 3004 | |
14b54336 | 3005 | if (scan->channel_count == 0) { |
e1623446 | 3006 | IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); |
14b54336 RC |
3007 | goto done; |
3008 | } | |
3009 | ||
b481de9c | 3010 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 3011 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
3012 | cmd.data = scan; |
3013 | scan->len = cpu_to_le16(cmd.len); | |
3014 | ||
3015 | set_bit(STATUS_SCAN_HW, &priv->status); | |
518099a8 | 3016 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
3017 | if (rc) |
3018 | goto done; | |
3019 | ||
3020 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
3021 | IWL_SCAN_CHECK_WATCHDOG); | |
3022 | ||
3023 | mutex_unlock(&priv->mutex); | |
3024 | return; | |
3025 | ||
3026 | done: | |
2420ebc1 MA |
3027 | /* can not perform scan make sure we clear scanning |
3028 | * bits from status so next scan request can be performed. | |
3029 | * if we dont clear scanning status bit here all next scan | |
3030 | * will fail | |
3031 | */ | |
3032 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3033 | clear_bit(STATUS_SCANNING, &priv->status); | |
3034 | ||
01ebd063 | 3035 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
3036 | queue_work(priv->workqueue, &priv->scan_completed); |
3037 | mutex_unlock(&priv->mutex); | |
3038 | } | |
3039 | ||
bb8c093b | 3040 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 3041 | { |
4a8a4322 | 3042 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
3043 | |
3044 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3045 | return; | |
3046 | ||
3047 | mutex_lock(&priv->mutex); | |
bb8c093b | 3048 | __iwl3945_up(priv); |
b481de9c ZY |
3049 | mutex_unlock(&priv->mutex); |
3050 | } | |
3051 | ||
bb8c093b | 3052 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 3053 | { |
4a8a4322 | 3054 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3055 | |
3056 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3057 | return; | |
3058 | ||
19cc1087 JB |
3059 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
3060 | mutex_lock(&priv->mutex); | |
3061 | priv->vif = NULL; | |
3062 | priv->is_open = 0; | |
3063 | mutex_unlock(&priv->mutex); | |
3064 | iwl3945_down(priv); | |
3065 | ieee80211_restart_hw(priv->hw); | |
3066 | } else { | |
3067 | iwl3945_down(priv); | |
3068 | queue_work(priv->workqueue, &priv->up); | |
3069 | } | |
b481de9c ZY |
3070 | } |
3071 | ||
bb8c093b | 3072 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3073 | { |
4a8a4322 AK |
3074 | struct iwl_priv *priv = |
3075 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3076 | |
3077 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3078 | return; | |
3079 | ||
3080 | mutex_lock(&priv->mutex); | |
bb8c093b | 3081 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
3082 | mutex_unlock(&priv->mutex); |
3083 | } | |
3084 | ||
7878a5a4 MA |
3085 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
3086 | ||
5bbe233b | 3087 | void iwl3945_post_associate(struct iwl_priv *priv) |
b481de9c | 3088 | { |
b481de9c ZY |
3089 | int rc = 0; |
3090 | struct ieee80211_conf *conf = NULL; | |
3091 | ||
05c914fe | 3092 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 3093 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3094 | return; |
3095 | } | |
3096 | ||
3097 | ||
e1623446 | 3098 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
8ccde88a | 3099 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
3100 | |
3101 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3102 | return; | |
3103 | ||
322a9811 | 3104 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 3105 | return; |
322a9811 | 3106 | |
af0053d6 | 3107 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 3108 | |
b481de9c ZY |
3109 | conf = ieee80211_get_hw_conf(priv->hw); |
3110 | ||
8ccde88a | 3111 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3112 | iwlcore_commit_rxon(priv); |
b481de9c | 3113 | |
28afaf91 | 3114 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
2c2f3b33 | 3115 | iwl_setup_rxon_timing(priv); |
518099a8 | 3116 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c ZY |
3117 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
3118 | if (rc) | |
39aadf8c | 3119 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3120 | "Attempting to continue.\n"); |
3121 | ||
8ccde88a | 3122 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3123 | |
8ccde88a | 3124 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3125 | |
e1623446 | 3126 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
3127 | priv->assoc_id, priv->beacon_int); |
3128 | ||
3129 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
8ccde88a | 3130 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3131 | else |
8ccde88a | 3132 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3133 | |
8ccde88a | 3134 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c | 3135 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
8ccde88a | 3136 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3137 | else |
8ccde88a | 3138 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3139 | |
05c914fe | 3140 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3141 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3142 | |
3143 | } | |
3144 | ||
e0158e61 | 3145 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3146 | |
3147 | switch (priv->iw_mode) { | |
05c914fe | 3148 | case NL80211_IFTYPE_STATION: |
bb8c093b | 3149 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
3150 | break; |
3151 | ||
05c914fe | 3152 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 3153 | |
ce546fd2 | 3154 | priv->assoc_id = 1; |
c587de0b | 3155 | iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL); |
b481de9c | 3156 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 3157 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
3158 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
3159 | CMD_ASYNC); | |
bb8c093b CH |
3160 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
3161 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
3162 | |
3163 | break; | |
3164 | ||
3165 | default: | |
15b1687c | 3166 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 3167 | __func__, priv->iw_mode); |
b481de9c ZY |
3168 | break; |
3169 | } | |
3170 | ||
14d2aac5 | 3171 | iwl_activate_qos(priv, 0); |
292ae174 | 3172 | |
7878a5a4 MA |
3173 | /* we have just associated, don't start scan too early */ |
3174 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
3175 | } |
3176 | ||
b481de9c ZY |
3177 | /***************************************************************************** |
3178 | * | |
3179 | * mac80211 entry point functions | |
3180 | * | |
3181 | *****************************************************************************/ | |
3182 | ||
5a66926a ZY |
3183 | #define UCODE_READY_TIMEOUT (2 * HZ) |
3184 | ||
bb8c093b | 3185 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3186 | { |
4a8a4322 | 3187 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3188 | int ret; |
b481de9c | 3189 | |
e1623446 | 3190 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3191 | |
3192 | /* we should be verifying the device is ready to be opened */ | |
3193 | mutex_lock(&priv->mutex); | |
3194 | ||
5a66926a ZY |
3195 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
3196 | * ucode filename and max sizes are card-specific. */ | |
3197 | ||
3198 | if (!priv->ucode_code.len) { | |
3199 | ret = iwl3945_read_ucode(priv); | |
3200 | if (ret) { | |
15b1687c | 3201 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
3202 | mutex_unlock(&priv->mutex); |
3203 | goto out_release_irq; | |
3204 | } | |
3205 | } | |
b481de9c | 3206 | |
e655b9f0 | 3207 | ret = __iwl3945_up(priv); |
b481de9c ZY |
3208 | |
3209 | mutex_unlock(&priv->mutex); | |
5a66926a | 3210 | |
e655b9f0 ZY |
3211 | if (ret) |
3212 | goto out_release_irq; | |
3213 | ||
e1623446 | 3214 | IWL_DEBUG_INFO(priv, "Start UP work.\n"); |
e655b9f0 | 3215 | |
5a66926a ZY |
3216 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
3217 | * mac80211 will not be run successfully. */ | |
3218 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
3219 | test_bit(STATUS_READY, &priv->status), | |
3220 | UCODE_READY_TIMEOUT); | |
3221 | if (!ret) { | |
3222 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
3223 | IWL_ERR(priv, |
3224 | "Wait for START_ALIVE timeout after %dms.\n", | |
3225 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
3226 | ret = -ETIMEDOUT; |
3227 | goto out_release_irq; | |
3228 | } | |
3229 | } | |
3230 | ||
2663516d HS |
3231 | /* ucode is running and will send rfkill notifications, |
3232 | * no need to poll the killswitch state anymore */ | |
3233 | cancel_delayed_work(&priv->rfkill_poll); | |
3234 | ||
e932a609 JB |
3235 | iwl_led_start(priv); |
3236 | ||
e655b9f0 | 3237 | priv->is_open = 1; |
e1623446 | 3238 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3239 | return 0; |
5a66926a ZY |
3240 | |
3241 | out_release_irq: | |
e655b9f0 | 3242 | priv->is_open = 0; |
e1623446 | 3243 | IWL_DEBUG_MAC80211(priv, "leave - failed\n"); |
5a66926a | 3244 | return ret; |
b481de9c ZY |
3245 | } |
3246 | ||
bb8c093b | 3247 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3248 | { |
4a8a4322 | 3249 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3250 | |
e1623446 | 3251 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
6ef89d0a | 3252 | |
e655b9f0 | 3253 | if (!priv->is_open) { |
e1623446 | 3254 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
3255 | return; |
3256 | } | |
3257 | ||
b481de9c | 3258 | priv->is_open = 0; |
5a66926a | 3259 | |
775a6e27 | 3260 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
3261 | /* stop mac, cancel any scan request and clear |
3262 | * RXON_FILTER_ASSOC_MSK BIT | |
3263 | */ | |
5a66926a | 3264 | mutex_lock(&priv->mutex); |
af0053d6 | 3265 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3266 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3267 | } |
3268 | ||
5a66926a ZY |
3269 | iwl3945_down(priv); |
3270 | ||
3271 | flush_workqueue(priv->workqueue); | |
2663516d HS |
3272 | |
3273 | /* start polling the killswitch state again */ | |
3274 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
3275 | round_jiffies_relative(2 * HZ)); | |
6ef89d0a | 3276 | |
e1623446 | 3277 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3278 | } |
3279 | ||
e039fa4a | 3280 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3281 | { |
4a8a4322 | 3282 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3283 | |
e1623446 | 3284 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3285 | |
e1623446 | 3286 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3287 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3288 | |
e039fa4a | 3289 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
3290 | dev_kfree_skb_any(skb); |
3291 | ||
e1623446 | 3292 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
637f8837 | 3293 | return NETDEV_TX_OK; |
b481de9c ZY |
3294 | } |
3295 | ||
60690a6a | 3296 | void iwl3945_config_ap(struct iwl_priv *priv) |
b481de9c ZY |
3297 | { |
3298 | int rc = 0; | |
3299 | ||
d986bcd1 | 3300 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3301 | return; |
3302 | ||
3303 | /* The following should be done only at AP bring up */ | |
8ccde88a | 3304 | if (!(iwl_is_associated(priv))) { |
b481de9c ZY |
3305 | |
3306 | /* RXON - unassoc (to set timing command) */ | |
8ccde88a | 3307 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3308 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3309 | |
3310 | /* RXON Timing */ | |
28afaf91 | 3311 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
2c2f3b33 | 3312 | iwl_setup_rxon_timing(priv); |
518099a8 SO |
3313 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
3314 | sizeof(priv->rxon_timing), | |
3315 | &priv->rxon_timing); | |
b481de9c | 3316 | if (rc) |
39aadf8c | 3317 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3318 | "Attempting to continue.\n"); |
3319 | ||
3320 | /* FIXME: what should be the assoc_id for AP? */ | |
8ccde88a | 3321 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3322 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
8ccde88a | 3323 | priv->staging_rxon.flags |= |
b481de9c ZY |
3324 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3325 | else | |
8ccde88a | 3326 | priv->staging_rxon.flags &= |
b481de9c ZY |
3327 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3328 | ||
8ccde88a | 3329 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c ZY |
3330 | if (priv->assoc_capability & |
3331 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
8ccde88a | 3332 | priv->staging_rxon.flags |= |
b481de9c ZY |
3333 | RXON_FLG_SHORT_SLOT_MSK; |
3334 | else | |
8ccde88a | 3335 | priv->staging_rxon.flags &= |
b481de9c ZY |
3336 | ~RXON_FLG_SHORT_SLOT_MSK; |
3337 | ||
05c914fe | 3338 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3339 | priv->staging_rxon.flags &= |
b481de9c ZY |
3340 | ~RXON_FLG_SHORT_SLOT_MSK; |
3341 | } | |
3342 | /* restore RXON assoc */ | |
8ccde88a | 3343 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3344 | iwlcore_commit_rxon(priv); |
c587de0b | 3345 | iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL); |
556f8db7 | 3346 | } |
bb8c093b | 3347 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3348 | |
3349 | /* FIXME - we need to add code here to detect a totally new | |
3350 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3351 | * clear sta table, add BCAST sta... */ | |
3352 | } | |
3353 | ||
bb8c093b | 3354 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3355 | struct ieee80211_vif *vif, |
3356 | struct ieee80211_sta *sta, | |
3357 | struct ieee80211_key_conf *key) | |
b481de9c | 3358 | { |
4a8a4322 | 3359 | struct iwl_priv *priv = hw->priv; |
dc822b5d | 3360 | const u8 *addr; |
6e21f15c AK |
3361 | int ret = 0; |
3362 | u8 sta_id = IWL_INVALID_STATION; | |
3363 | u8 static_key; | |
b481de9c | 3364 | |
e1623446 | 3365 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3366 | |
df878d8f | 3367 | if (iwl3945_mod_params.sw_crypto) { |
e1623446 | 3368 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3369 | return -EOPNOTSUPP; |
3370 | } | |
3371 | ||
42986796 | 3372 | addr = sta ? sta->addr : iwl_bcast_addr; |
6e21f15c AK |
3373 | static_key = !iwl_is_associated(priv); |
3374 | ||
3375 | if (!static_key) { | |
c587de0b | 3376 | sta_id = iwl_find_station(priv, addr); |
6e21f15c | 3377 | if (sta_id == IWL_INVALID_STATION) { |
12514396 | 3378 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
6e21f15c AK |
3379 | addr); |
3380 | return -EINVAL; | |
3381 | } | |
b481de9c ZY |
3382 | } |
3383 | ||
3384 | mutex_lock(&priv->mutex); | |
af0053d6 | 3385 | iwl_scan_cancel_timeout(priv, 100); |
6e21f15c | 3386 | mutex_unlock(&priv->mutex); |
15e869d8 | 3387 | |
b481de9c | 3388 | switch (cmd) { |
6e21f15c AK |
3389 | case SET_KEY: |
3390 | if (static_key) | |
3391 | ret = iwl3945_set_static_key(priv, key); | |
3392 | else | |
3393 | ret = iwl3945_set_dynamic_key(priv, key, sta_id); | |
3394 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); | |
b481de9c ZY |
3395 | break; |
3396 | case DISABLE_KEY: | |
6e21f15c AK |
3397 | if (static_key) |
3398 | ret = iwl3945_remove_static_key(priv); | |
3399 | else | |
3400 | ret = iwl3945_clear_sta_key_info(priv, sta_id); | |
3401 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); | |
b481de9c ZY |
3402 | break; |
3403 | default: | |
42986796 | 3404 | ret = -EINVAL; |
b481de9c ZY |
3405 | } |
3406 | ||
e1623446 | 3407 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3408 | |
42986796 | 3409 | return ret; |
b481de9c ZY |
3410 | } |
3411 | ||
b481de9c ZY |
3412 | /***************************************************************************** |
3413 | * | |
3414 | * sysfs attributes | |
3415 | * | |
3416 | *****************************************************************************/ | |
3417 | ||
d08853a3 | 3418 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3419 | |
3420 | /* | |
3421 | * The following adds a new attribute to the sysfs representation | |
3422 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3423 | * used for controlling the debug level. | |
3424 | * | |
3425 | * See the level definitions in iwl for details. | |
a562a9dd | 3426 | * |
3d816c77 RC |
3427 | * The debug_level being managed using sysfs below is a per device debug |
3428 | * level that is used instead of the global debug level if it (the per | |
3429 | * device debug level) is set. | |
b481de9c | 3430 | */ |
40b8ec0b SO |
3431 | static ssize_t show_debug_level(struct device *d, |
3432 | struct device_attribute *attr, char *buf) | |
b481de9c | 3433 | { |
3d816c77 RC |
3434 | struct iwl_priv *priv = dev_get_drvdata(d); |
3435 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3436 | } |
40b8ec0b SO |
3437 | static ssize_t store_debug_level(struct device *d, |
3438 | struct device_attribute *attr, | |
b481de9c ZY |
3439 | const char *buf, size_t count) |
3440 | { | |
928841b1 | 3441 | struct iwl_priv *priv = dev_get_drvdata(d); |
40b8ec0b SO |
3442 | unsigned long val; |
3443 | int ret; | |
b481de9c | 3444 | |
40b8ec0b SO |
3445 | ret = strict_strtoul(buf, 0, &val); |
3446 | if (ret) | |
978785a3 | 3447 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3448 | else { |
3d816c77 | 3449 | priv->debug_level = val; |
20594eb0 WYG |
3450 | if (iwl_alloc_traffic_mem(priv)) |
3451 | IWL_ERR(priv, | |
3452 | "Not enough memory to generate traffic log\n"); | |
3453 | } | |
b481de9c ZY |
3454 | return strnlen(buf, count); |
3455 | } | |
3456 | ||
40b8ec0b SO |
3457 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3458 | show_debug_level, store_debug_level); | |
b481de9c | 3459 | |
d08853a3 | 3460 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3461 | |
b481de9c ZY |
3462 | static ssize_t show_temperature(struct device *d, |
3463 | struct device_attribute *attr, char *buf) | |
3464 | { | |
928841b1 | 3465 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3466 | |
775a6e27 | 3467 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3468 | return -EAGAIN; |
3469 | ||
bb8c093b | 3470 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
3471 | } |
3472 | ||
3473 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3474 | ||
b481de9c ZY |
3475 | static ssize_t show_tx_power(struct device *d, |
3476 | struct device_attribute *attr, char *buf) | |
3477 | { | |
928841b1 | 3478 | struct iwl_priv *priv = dev_get_drvdata(d); |
62ea9c5b | 3479 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); |
b481de9c ZY |
3480 | } |
3481 | ||
3482 | static ssize_t store_tx_power(struct device *d, | |
3483 | struct device_attribute *attr, | |
3484 | const char *buf, size_t count) | |
3485 | { | |
928841b1 | 3486 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3487 | char *p = (char *)buf; |
3488 | u32 val; | |
3489 | ||
3490 | val = simple_strtoul(p, &p, 10); | |
3491 | if (p == buf) | |
978785a3 | 3492 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 3493 | else |
bb8c093b | 3494 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
3495 | |
3496 | return count; | |
3497 | } | |
3498 | ||
3499 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3500 | ||
3501 | static ssize_t show_flags(struct device *d, | |
3502 | struct device_attribute *attr, char *buf) | |
3503 | { | |
928841b1 | 3504 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3505 | |
8ccde88a | 3506 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); |
b481de9c ZY |
3507 | } |
3508 | ||
3509 | static ssize_t store_flags(struct device *d, | |
3510 | struct device_attribute *attr, | |
3511 | const char *buf, size_t count) | |
3512 | { | |
928841b1 | 3513 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3514 | u32 flags = simple_strtoul(buf, NULL, 0); |
3515 | ||
3516 | mutex_lock(&priv->mutex); | |
8ccde88a | 3517 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { |
b481de9c | 3518 | /* Cancel any currently running scans... */ |
af0053d6 | 3519 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3520 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3521 | else { |
e1623446 | 3522 | IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n", |
b481de9c | 3523 | flags); |
8ccde88a | 3524 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 3525 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3526 | } |
3527 | } | |
3528 | mutex_unlock(&priv->mutex); | |
3529 | ||
3530 | return count; | |
3531 | } | |
3532 | ||
3533 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3534 | ||
3535 | static ssize_t show_filter_flags(struct device *d, | |
3536 | struct device_attribute *attr, char *buf) | |
3537 | { | |
928841b1 | 3538 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3539 | |
3540 | return sprintf(buf, "0x%04X\n", | |
8ccde88a | 3541 | le32_to_cpu(priv->active_rxon.filter_flags)); |
b481de9c ZY |
3542 | } |
3543 | ||
3544 | static ssize_t store_filter_flags(struct device *d, | |
3545 | struct device_attribute *attr, | |
3546 | const char *buf, size_t count) | |
3547 | { | |
928841b1 | 3548 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3549 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3550 | ||
3551 | mutex_lock(&priv->mutex); | |
8ccde88a | 3552 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { |
b481de9c | 3553 | /* Cancel any currently running scans... */ |
af0053d6 | 3554 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3555 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3556 | else { |
e1623446 | 3557 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c | 3558 | "0x%04X\n", filter_flags); |
8ccde88a | 3559 | priv->staging_rxon.filter_flags = |
b481de9c | 3560 | cpu_to_le32(filter_flags); |
e0158e61 | 3561 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3562 | } |
3563 | } | |
3564 | mutex_unlock(&priv->mutex); | |
3565 | ||
3566 | return count; | |
3567 | } | |
3568 | ||
3569 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3570 | store_filter_flags); | |
3571 | ||
c8b0e6e1 | 3572 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3573 | |
3574 | static ssize_t show_measurement(struct device *d, | |
3575 | struct device_attribute *attr, char *buf) | |
3576 | { | |
4a8a4322 | 3577 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 3578 | struct iwl_spectrum_notification measure_report; |
b481de9c | 3579 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 3580 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
3581 | unsigned long flags; |
3582 | ||
3583 | spin_lock_irqsave(&priv->lock, flags); | |
3584 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
3585 | spin_unlock_irqrestore(&priv->lock, flags); | |
3586 | return 0; | |
3587 | } | |
3588 | memcpy(&measure_report, &priv->measure_report, size); | |
3589 | priv->measurement_status = 0; | |
3590 | spin_unlock_irqrestore(&priv->lock, flags); | |
3591 | ||
3592 | while (size && (PAGE_SIZE - len)) { | |
3593 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3594 | PAGE_SIZE - len, 1); | |
3595 | len = strlen(buf); | |
3596 | if (PAGE_SIZE - len) | |
3597 | buf[len++] = '\n'; | |
3598 | ||
3599 | ofs += 16; | |
3600 | size -= min(size, 16U); | |
3601 | } | |
3602 | ||
3603 | return len; | |
3604 | } | |
3605 | ||
3606 | static ssize_t store_measurement(struct device *d, | |
3607 | struct device_attribute *attr, | |
3608 | const char *buf, size_t count) | |
3609 | { | |
4a8a4322 | 3610 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3611 | struct ieee80211_measurement_params params = { |
8ccde88a | 3612 | .channel = le16_to_cpu(priv->active_rxon.channel), |
b481de9c ZY |
3613 | .start_time = cpu_to_le64(priv->last_tsf), |
3614 | .duration = cpu_to_le16(1), | |
3615 | }; | |
3616 | u8 type = IWL_MEASURE_BASIC; | |
3617 | u8 buffer[32]; | |
3618 | u8 channel; | |
3619 | ||
3620 | if (count) { | |
3621 | char *p = buffer; | |
3622 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3623 | channel = simple_strtoul(p, NULL, 0); | |
3624 | if (channel) | |
3625 | params.channel = channel; | |
3626 | ||
3627 | p = buffer; | |
3628 | while (*p && *p != ' ') | |
3629 | p++; | |
3630 | if (*p) | |
3631 | type = simple_strtoul(p + 1, NULL, 0); | |
3632 | } | |
3633 | ||
e1623446 | 3634 | IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on " |
b481de9c | 3635 | "channel %d (for '%s')\n", type, params.channel, buf); |
bb8c093b | 3636 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
3637 | |
3638 | return count; | |
3639 | } | |
3640 | ||
3641 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
3642 | show_measurement, store_measurement); | |
c8b0e6e1 | 3643 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 3644 | |
b481de9c ZY |
3645 | static ssize_t store_retry_rate(struct device *d, |
3646 | struct device_attribute *attr, | |
3647 | const char *buf, size_t count) | |
3648 | { | |
4a8a4322 | 3649 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3650 | |
3651 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
3652 | if (priv->retry_rate <= 0) | |
3653 | priv->retry_rate = 1; | |
3654 | ||
3655 | return count; | |
3656 | } | |
3657 | ||
3658 | static ssize_t show_retry_rate(struct device *d, | |
3659 | struct device_attribute *attr, char *buf) | |
3660 | { | |
4a8a4322 | 3661 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3662 | return sprintf(buf, "%d", priv->retry_rate); |
3663 | } | |
3664 | ||
3665 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
3666 | store_retry_rate); | |
3667 | ||
d25aabb0 | 3668 | |
b481de9c ZY |
3669 | static ssize_t show_channels(struct device *d, |
3670 | struct device_attribute *attr, char *buf) | |
3671 | { | |
8318d78a JB |
3672 | /* all this shit doesn't belong into sysfs anyway */ |
3673 | return 0; | |
b481de9c ZY |
3674 | } |
3675 | ||
3676 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
3677 | ||
3678 | static ssize_t show_statistics(struct device *d, | |
3679 | struct device_attribute *attr, char *buf) | |
3680 | { | |
4a8a4322 | 3681 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 3682 | u32 size = sizeof(struct iwl3945_notif_statistics); |
b481de9c | 3683 | u32 len = 0, ofs = 0; |
f2c7e521 | 3684 | u8 *data = (u8 *)&priv->statistics_39; |
b481de9c ZY |
3685 | int rc = 0; |
3686 | ||
775a6e27 | 3687 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3688 | return -EAGAIN; |
3689 | ||
3690 | mutex_lock(&priv->mutex); | |
ef8d5529 | 3691 | rc = iwl_send_statistics_request(priv, CMD_SYNC, false); |
b481de9c ZY |
3692 | mutex_unlock(&priv->mutex); |
3693 | ||
3694 | if (rc) { | |
3695 | len = sprintf(buf, | |
3696 | "Error sending statistics request: 0x%08X\n", rc); | |
3697 | return len; | |
3698 | } | |
3699 | ||
3700 | while (size && (PAGE_SIZE - len)) { | |
3701 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3702 | PAGE_SIZE - len, 1); | |
3703 | len = strlen(buf); | |
3704 | if (PAGE_SIZE - len) | |
3705 | buf[len++] = '\n'; | |
3706 | ||
3707 | ofs += 16; | |
3708 | size -= min(size, 16U); | |
3709 | } | |
3710 | ||
3711 | return len; | |
3712 | } | |
3713 | ||
3714 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3715 | ||
3716 | static ssize_t show_antenna(struct device *d, | |
3717 | struct device_attribute *attr, char *buf) | |
3718 | { | |
4a8a4322 | 3719 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3720 | |
775a6e27 | 3721 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3722 | return -EAGAIN; |
3723 | ||
7e4bca5e | 3724 | return sprintf(buf, "%d\n", iwl3945_mod_params.antenna); |
b481de9c ZY |
3725 | } |
3726 | ||
3727 | static ssize_t store_antenna(struct device *d, | |
3728 | struct device_attribute *attr, | |
3729 | const char *buf, size_t count) | |
3730 | { | |
7530f85f | 3731 | struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d); |
b481de9c | 3732 | int ant; |
b481de9c ZY |
3733 | |
3734 | if (count == 0) | |
3735 | return 0; | |
3736 | ||
3737 | if (sscanf(buf, "%1i", &ant) != 1) { | |
e1623446 | 3738 | IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n"); |
b481de9c ZY |
3739 | return count; |
3740 | } | |
3741 | ||
3742 | if ((ant >= 0) && (ant <= 2)) { | |
e1623446 | 3743 | IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant); |
7e4bca5e | 3744 | iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant; |
b481de9c | 3745 | } else |
e1623446 | 3746 | IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant); |
b481de9c ZY |
3747 | |
3748 | ||
3749 | return count; | |
3750 | } | |
3751 | ||
3752 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
3753 | ||
3754 | static ssize_t show_status(struct device *d, | |
3755 | struct device_attribute *attr, char *buf) | |
3756 | { | |
928841b1 | 3757 | struct iwl_priv *priv = dev_get_drvdata(d); |
775a6e27 | 3758 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3759 | return -EAGAIN; |
3760 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
3761 | } | |
3762 | ||
3763 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
3764 | ||
3765 | static ssize_t dump_error_log(struct device *d, | |
3766 | struct device_attribute *attr, | |
3767 | const char *buf, size_t count) | |
3768 | { | |
928841b1 | 3769 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3770 | char *p = (char *)buf; |
3771 | ||
3772 | if (p[0] == '1') | |
928841b1 | 3773 | iwl3945_dump_nic_error_log(priv); |
b481de9c ZY |
3774 | |
3775 | return strnlen(buf, count); | |
3776 | } | |
3777 | ||
3778 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
3779 | ||
b481de9c ZY |
3780 | /***************************************************************************** |
3781 | * | |
a96a27f9 | 3782 | * driver setup and tear down |
b481de9c ZY |
3783 | * |
3784 | *****************************************************************************/ | |
3785 | ||
4a8a4322 | 3786 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3787 | { |
d21050c7 | 3788 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3789 | |
3790 | init_waitqueue_head(&priv->wait_command_queue); | |
3791 | ||
bb8c093b CH |
3792 | INIT_WORK(&priv->up, iwl3945_bg_up); |
3793 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
3794 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
bb8c093b | 3795 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); |
bb8c093b CH |
3796 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
3797 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
2663516d | 3798 | INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll); |
77fecfb8 SO |
3799 | INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed); |
3800 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
3801 | INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan); | |
3802 | INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check); | |
bb8c093b CH |
3803 | |
3804 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
3805 | |
3806 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 3807 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
3808 | } |
3809 | ||
4a8a4322 | 3810 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3811 | { |
bb8c093b | 3812 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 3813 | |
e47eb6ad | 3814 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
3815 | cancel_delayed_work(&priv->scan_check); |
3816 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
3817 | cancel_work_sync(&priv->beacon_update); |
3818 | } | |
3819 | ||
bb8c093b | 3820 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
3821 | &dev_attr_antenna.attr, |
3822 | &dev_attr_channels.attr, | |
3823 | &dev_attr_dump_errors.attr, | |
b481de9c ZY |
3824 | &dev_attr_flags.attr, |
3825 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 3826 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3827 | &dev_attr_measurement.attr, |
3828 | #endif | |
b481de9c | 3829 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
3830 | &dev_attr_statistics.attr, |
3831 | &dev_attr_status.attr, | |
3832 | &dev_attr_temperature.attr, | |
b481de9c | 3833 | &dev_attr_tx_power.attr, |
d08853a3 | 3834 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b SO |
3835 | &dev_attr_debug_level.attr, |
3836 | #endif | |
b481de9c ZY |
3837 | NULL |
3838 | }; | |
3839 | ||
bb8c093b | 3840 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 3841 | .name = NULL, /* put in device directory */ |
bb8c093b | 3842 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
3843 | }; |
3844 | ||
bb8c093b CH |
3845 | static struct ieee80211_ops iwl3945_hw_ops = { |
3846 | .tx = iwl3945_mac_tx, | |
3847 | .start = iwl3945_mac_start, | |
3848 | .stop = iwl3945_mac_stop, | |
cbb6ab94 | 3849 | .add_interface = iwl_mac_add_interface, |
d8052319 | 3850 | .remove_interface = iwl_mac_remove_interface, |
4808368d | 3851 | .config = iwl_mac_config, |
8ccde88a | 3852 | .configure_filter = iwl_configure_filter, |
bb8c093b | 3853 | .set_key = iwl3945_mac_set_key, |
aa89f31e | 3854 | .get_tx_stats = iwl_mac_get_tx_stats, |
488829f1 | 3855 | .conf_tx = iwl_mac_conf_tx, |
bd564261 | 3856 | .reset_tsf = iwl_mac_reset_tsf, |
5bbe233b | 3857 | .bss_info_changed = iwl_bss_info_changed, |
e9dde6f6 | 3858 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
3859 | }; |
3860 | ||
e52119c5 | 3861 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
3862 | { |
3863 | int ret; | |
e6148917 | 3864 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
90a30a02 KA |
3865 | |
3866 | priv->retry_rate = 1; | |
3867 | priv->ibss_beacon = NULL; | |
3868 | ||
90a30a02 KA |
3869 | spin_lock_init(&priv->sta_lock); |
3870 | spin_lock_init(&priv->hcmd_lock); | |
3871 | ||
3872 | INIT_LIST_HEAD(&priv->free_frames); | |
3873 | ||
3874 | mutex_init(&priv->mutex); | |
3875 | ||
3876 | /* Clear the driver's (not device's) station table */ | |
c587de0b | 3877 | iwl_clear_stations_table(priv); |
90a30a02 | 3878 | |
90a30a02 KA |
3879 | priv->ieee_channels = NULL; |
3880 | priv->ieee_rates = NULL; | |
3881 | priv->band = IEEE80211_BAND_2GHZ; | |
3882 | ||
3883 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
a13d276f | 3884 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
90a30a02 KA |
3885 | |
3886 | iwl_reset_qos(priv); | |
3887 | ||
3888 | priv->qos_data.qos_active = 0; | |
3889 | priv->qos_data.qos_cap.val = 0; | |
3890 | ||
3891 | priv->rates_mask = IWL_RATES_MASK; | |
62ea9c5b | 3892 | priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER; |
90a30a02 | 3893 | |
e6148917 SO |
3894 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
3895 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", | |
3896 | eeprom->version); | |
3897 | ret = -EINVAL; | |
3898 | goto err; | |
3899 | } | |
3900 | ret = iwl_init_channel_map(priv); | |
90a30a02 KA |
3901 | if (ret) { |
3902 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3903 | goto err; | |
3904 | } | |
3905 | ||
e6148917 SO |
3906 | /* Set up txpower settings in driver for all channels */ |
3907 | if (iwl3945_txpower_set_from_eeprom(priv)) { | |
3908 | ret = -EIO; | |
3909 | goto err_free_channel_map; | |
3910 | } | |
3911 | ||
534166de | 3912 | ret = iwlcore_init_geos(priv); |
90a30a02 KA |
3913 | if (ret) { |
3914 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3915 | goto err_free_channel_map; | |
3916 | } | |
534166de SO |
3917 | iwl3945_init_hw_rates(priv, priv->ieee_rates); |
3918 | ||
2a4ddaab AK |
3919 | return 0; |
3920 | ||
3921 | err_free_channel_map: | |
3922 | iwl_free_channel_map(priv); | |
3923 | err: | |
3924 | return ret; | |
3925 | } | |
3926 | ||
3927 | static int iwl3945_setup_mac(struct iwl_priv *priv) | |
3928 | { | |
3929 | int ret; | |
3930 | struct ieee80211_hw *hw = priv->hw; | |
3931 | ||
3932 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
3933 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
3934 | ||
3935 | /* Tell mac80211 our characteristics */ | |
3936 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
b1c6019b | 3937 | IEEE80211_HW_NOISE_DBM | |
bc45a670 RC |
3938 | IEEE80211_HW_SPECTRUM_MGMT; |
3939 | ||
3940 | if (!priv->cfg->broken_powersave) | |
3941 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
3942 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2a4ddaab AK |
3943 | |
3944 | hw->wiphy->interface_modes = | |
3945 | BIT(NL80211_IFTYPE_STATION) | | |
3946 | BIT(NL80211_IFTYPE_ADHOC); | |
3947 | ||
5be83de5 JB |
3948 | hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY | |
3949 | WIPHY_FLAG_DISABLE_BEACON_HINTS; | |
37184244 | 3950 | |
1ecf9fc1 JB |
3951 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; |
3952 | /* we create the 802.11 header and a zero-length SSID element */ | |
3953 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
d60cc91a | 3954 | |
2a4ddaab AK |
3955 | /* Default value; 4 EDCA QOS priorities */ |
3956 | hw->queues = 4; | |
3957 | ||
534166de SO |
3958 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
3959 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3960 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2a4ddaab | 3961 | |
534166de SO |
3962 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
3963 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3964 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
90a30a02 | 3965 | |
2a4ddaab AK |
3966 | ret = ieee80211_register_hw(priv->hw); |
3967 | if (ret) { | |
3968 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3969 | return ret; | |
3970 | } | |
3971 | priv->mac80211_registered = 1; | |
90a30a02 | 3972 | |
2a4ddaab | 3973 | return 0; |
90a30a02 KA |
3974 | } |
3975 | ||
bb8c093b | 3976 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3977 | { |
3978 | int err = 0; | |
4a8a4322 | 3979 | struct iwl_priv *priv; |
b481de9c | 3980 | struct ieee80211_hw *hw; |
c0f20d91 | 3981 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
e6148917 | 3982 | struct iwl3945_eeprom *eeprom; |
0359facc | 3983 | unsigned long flags; |
b481de9c | 3984 | |
cee53ddb KA |
3985 | /*********************** |
3986 | * 1. Allocating HW data | |
3987 | * ********************/ | |
3988 | ||
b481de9c ZY |
3989 | /* mac80211 allocates memory for this device instance, including |
3990 | * space for this driver's private structure */ | |
90a30a02 | 3991 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 3992 | if (hw == NULL) { |
a3139c59 | 3993 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
3994 | err = -ENOMEM; |
3995 | goto out; | |
3996 | } | |
b481de9c | 3997 | priv = hw->priv; |
90a30a02 | 3998 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 3999 | |
90a30a02 KA |
4000 | /* |
4001 | * Disabling hardware scan means that mac80211 will perform scans | |
4002 | * "the hard way", rather than using device's scan. | |
4003 | */ | |
df878d8f | 4004 | if (iwl3945_mod_params.disable_hw_scan) { |
e1623446 | 4005 | IWL_DEBUG_INFO(priv, "Disabling hw_scan\n"); |
40b8ec0b SO |
4006 | iwl3945_hw_ops.hw_scan = NULL; |
4007 | } | |
4008 | ||
90a30a02 | 4009 | |
e1623446 | 4010 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
90a30a02 KA |
4011 | priv->cfg = cfg; |
4012 | priv->pci_dev = pdev; | |
40cefda9 | 4013 | priv->inta_mask = CSR_INI_SET_MASK; |
cee53ddb | 4014 | |
d08853a3 | 4015 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
4016 | atomic_set(&priv->restrict_refcnt, 0); |
4017 | #endif | |
20594eb0 WYG |
4018 | if (iwl_alloc_traffic_mem(priv)) |
4019 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 4020 | |
cee53ddb KA |
4021 | /*************************** |
4022 | * 2. Initializing PCI bus | |
4023 | * *************************/ | |
b481de9c ZY |
4024 | if (pci_enable_device(pdev)) { |
4025 | err = -ENODEV; | |
4026 | goto out_ieee80211_free_hw; | |
4027 | } | |
4028 | ||
4029 | pci_set_master(pdev); | |
4030 | ||
284901a9 | 4031 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4032 | if (!err) |
284901a9 | 4033 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4034 | if (err) { |
978785a3 | 4035 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
4036 | goto out_pci_disable_device; |
4037 | } | |
4038 | ||
4039 | pci_set_drvdata(pdev, priv); | |
4040 | err = pci_request_regions(pdev, DRV_NAME); | |
4041 | if (err) | |
4042 | goto out_pci_disable_device; | |
6440adb5 | 4043 | |
cee53ddb KA |
4044 | /*********************** |
4045 | * 3. Read REV Register | |
4046 | * ********************/ | |
b481de9c ZY |
4047 | priv->hw_base = pci_iomap(pdev, 0, 0); |
4048 | if (!priv->hw_base) { | |
4049 | err = -ENODEV; | |
4050 | goto out_pci_release_regions; | |
4051 | } | |
4052 | ||
e1623446 | 4053 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
b481de9c | 4054 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4055 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
b481de9c | 4056 | |
cee53ddb KA |
4057 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4058 | * PCI Tx retries from interfering with C3 CPU state */ | |
4059 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 4060 | |
731a29b7 | 4061 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
4062 | * we should init now |
4063 | */ | |
4064 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 4065 | spin_lock_init(&priv->lock); |
a8b50a0a | 4066 | |
cee53ddb KA |
4067 | /*********************** |
4068 | * 4. Read EEPROM | |
4069 | * ********************/ | |
90a30a02 | 4070 | |
cee53ddb | 4071 | /* Read the EEPROM */ |
e6148917 | 4072 | err = iwl_eeprom_init(priv); |
cee53ddb | 4073 | if (err) { |
15b1687c | 4074 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
c8f16138 | 4075 | goto out_iounmap; |
cee53ddb KA |
4076 | } |
4077 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
e6148917 SO |
4078 | eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
4079 | memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN); | |
e1623446 | 4080 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
cee53ddb | 4081 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
b481de9c | 4082 | |
cee53ddb KA |
4083 | /*********************** |
4084 | * 5. Setup HW Constants | |
4085 | * ********************/ | |
b481de9c | 4086 | /* Device-specific setup */ |
3832ec9d | 4087 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 4088 | IWL_ERR(priv, "failed to set hw settings\n"); |
c8f16138 | 4089 | goto out_eeprom_free; |
b481de9c ZY |
4090 | } |
4091 | ||
cee53ddb KA |
4092 | /*********************** |
4093 | * 6. Setup priv | |
4094 | * ********************/ | |
cee53ddb | 4095 | |
90a30a02 | 4096 | err = iwl3945_init_drv(priv); |
b481de9c | 4097 | if (err) { |
90a30a02 | 4098 | IWL_ERR(priv, "initializing driver failed\n"); |
c8f16138 | 4099 | goto out_unset_hw_params; |
b481de9c ZY |
4100 | } |
4101 | ||
978785a3 TW |
4102 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
4103 | priv->cfg->name); | |
cee53ddb | 4104 | |
cee53ddb | 4105 | /*********************** |
09f9bf79 | 4106 | * 7. Setup Services |
cee53ddb KA |
4107 | * ********************/ |
4108 | ||
4109 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4110 | iwl_disable_interrupts(priv); |
cee53ddb KA |
4111 | spin_unlock_irqrestore(&priv->lock, flags); |
4112 | ||
2663516d HS |
4113 | pci_enable_msi(priv->pci_dev); |
4114 | ||
ef850d7c MA |
4115 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, |
4116 | IRQF_SHARED, DRV_NAME, priv); | |
2663516d HS |
4117 | if (err) { |
4118 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4119 | goto out_disable_msi; | |
4120 | } | |
4121 | ||
cee53ddb | 4122 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 4123 | if (err) { |
15b1687c | 4124 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 4125 | goto out_release_irq; |
849e0dce | 4126 | } |
849e0dce | 4127 | |
8ccde88a SO |
4128 | iwl_set_rxon_channel(priv, |
4129 | &priv->bands[IEEE80211_BAND_2GHZ].channels[5]); | |
cee53ddb KA |
4130 | iwl3945_setup_deferred_work(priv); |
4131 | iwl3945_setup_rx_handlers(priv); | |
008a9e3e | 4132 | iwl_power_initialize(priv); |
cee53ddb | 4133 | |
cee53ddb | 4134 | /********************************* |
09f9bf79 | 4135 | * 8. Setup and Register mac80211 |
cee53ddb KA |
4136 | * *******************************/ |
4137 | ||
2a4ddaab | 4138 | iwl_enable_interrupts(priv); |
b481de9c | 4139 | |
2a4ddaab AK |
4140 | err = iwl3945_setup_mac(priv); |
4141 | if (err) | |
4142 | goto out_remove_sysfs; | |
cee53ddb | 4143 | |
a75fbe8d AK |
4144 | err = iwl_dbgfs_register(priv, DRV_NAME); |
4145 | if (err) | |
4146 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
4147 | ||
2663516d HS |
4148 | /* Start monitoring the killswitch */ |
4149 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
4150 | 2 * HZ); | |
4151 | ||
b481de9c ZY |
4152 | return 0; |
4153 | ||
cee53ddb | 4154 | out_remove_sysfs: |
c8f16138 RC |
4155 | destroy_workqueue(priv->workqueue); |
4156 | priv->workqueue = NULL; | |
cee53ddb | 4157 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4158 | out_release_irq: |
2663516d | 4159 | free_irq(priv->pci_dev->irq, priv); |
2663516d HS |
4160 | out_disable_msi: |
4161 | pci_disable_msi(priv->pci_dev); | |
c8f16138 RC |
4162 | iwlcore_free_geos(priv); |
4163 | iwl_free_channel_map(priv); | |
4164 | out_unset_hw_params: | |
4165 | iwl3945_unset_hw_params(priv); | |
4166 | out_eeprom_free: | |
4167 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4168 | out_iounmap: |
4169 | pci_iounmap(pdev, priv->hw_base); | |
4170 | out_pci_release_regions: | |
4171 | pci_release_regions(pdev); | |
4172 | out_pci_disable_device: | |
b481de9c | 4173 | pci_set_drvdata(pdev, NULL); |
623d563e | 4174 | pci_disable_device(pdev); |
b481de9c | 4175 | out_ieee80211_free_hw: |
20594eb0 | 4176 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4177 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4178 | out: |
4179 | return err; | |
4180 | } | |
4181 | ||
c83dbf68 | 4182 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 4183 | { |
4a8a4322 | 4184 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4185 | unsigned long flags; |
b481de9c ZY |
4186 | |
4187 | if (!priv) | |
4188 | return; | |
4189 | ||
e1623446 | 4190 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4191 | |
a75fbe8d AK |
4192 | iwl_dbgfs_unregister(priv); |
4193 | ||
b481de9c | 4194 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 4195 | |
d552bfb6 KA |
4196 | if (priv->mac80211_registered) { |
4197 | ieee80211_unregister_hw(priv->hw); | |
4198 | priv->mac80211_registered = 0; | |
4199 | } else { | |
4200 | iwl3945_down(priv); | |
4201 | } | |
b481de9c | 4202 | |
c166b25a BC |
4203 | /* |
4204 | * Make sure device is reset to low power before unloading driver. | |
4205 | * This may be redundant with iwl_down(), but there are paths to | |
4206 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4207 | * paths to avoid running iwl_down() at all before leaving driver. | |
4208 | * This (inexpensive) call *makes sure* device is reset. | |
4209 | */ | |
4210 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
4211 | ||
0359facc MA |
4212 | /* make sure we flush any pending irq or |
4213 | * tasklet for the driver | |
4214 | */ | |
4215 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4216 | iwl_disable_interrupts(priv); |
0359facc MA |
4217 | spin_unlock_irqrestore(&priv->lock, flags); |
4218 | ||
4219 | iwl_synchronize_irq(priv); | |
4220 | ||
bb8c093b | 4221 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4222 | |
71d449b5 | 4223 | cancel_delayed_work_sync(&priv->rfkill_poll); |
2663516d | 4224 | |
bb8c093b | 4225 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4226 | |
4227 | if (priv->rxq.bd) | |
df833b1d | 4228 | iwl3945_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 4229 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 4230 | |
3832ec9d | 4231 | iwl3945_unset_hw_params(priv); |
c587de0b | 4232 | iwl_clear_stations_table(priv); |
b481de9c | 4233 | |
6ef89d0a MA |
4234 | /*netif_stop_queue(dev); */ |
4235 | flush_workqueue(priv->workqueue); | |
4236 | ||
bb8c093b | 4237 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
4238 | * priv->workqueue... so we can't take down the workqueue |
4239 | * until now... */ | |
4240 | destroy_workqueue(priv->workqueue); | |
4241 | priv->workqueue = NULL; | |
20594eb0 | 4242 | iwl_free_traffic_mem(priv); |
b481de9c | 4243 | |
2663516d HS |
4244 | free_irq(pdev->irq, priv); |
4245 | pci_disable_msi(pdev); | |
4246 | ||
b481de9c ZY |
4247 | pci_iounmap(pdev, priv->hw_base); |
4248 | pci_release_regions(pdev); | |
4249 | pci_disable_device(pdev); | |
4250 | pci_set_drvdata(pdev, NULL); | |
4251 | ||
e6148917 | 4252 | iwl_free_channel_map(priv); |
534166de | 4253 | iwlcore_free_geos(priv); |
805cee5b | 4254 | kfree(priv->scan); |
b481de9c ZY |
4255 | if (priv->ibss_beacon) |
4256 | dev_kfree_skb(priv->ibss_beacon); | |
4257 | ||
4258 | ieee80211_free_hw(priv->hw); | |
4259 | } | |
4260 | ||
b481de9c ZY |
4261 | |
4262 | /***************************************************************************** | |
4263 | * | |
4264 | * driver and module entry point | |
4265 | * | |
4266 | *****************************************************************************/ | |
4267 | ||
bb8c093b | 4268 | static struct pci_driver iwl3945_driver = { |
b481de9c | 4269 | .name = DRV_NAME, |
bb8c093b CH |
4270 | .id_table = iwl3945_hw_card_ids, |
4271 | .probe = iwl3945_pci_probe, | |
4272 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 4273 | #ifdef CONFIG_PM |
6da3a13e WYG |
4274 | .suspend = iwl_pci_suspend, |
4275 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4276 | #endif |
4277 | }; | |
4278 | ||
bb8c093b | 4279 | static int __init iwl3945_init(void) |
b481de9c ZY |
4280 | { |
4281 | ||
4282 | int ret; | |
4283 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4284 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
4285 | |
4286 | ret = iwl3945_rate_control_register(); | |
4287 | if (ret) { | |
a3139c59 SO |
4288 | printk(KERN_ERR DRV_NAME |
4289 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4290 | return ret; |
4291 | } | |
4292 | ||
bb8c093b | 4293 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 4294 | if (ret) { |
a3139c59 | 4295 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4296 | goto error_register; |
b481de9c | 4297 | } |
b481de9c ZY |
4298 | |
4299 | return ret; | |
897e1cf2 | 4300 | |
897e1cf2 RC |
4301 | error_register: |
4302 | iwl3945_rate_control_unregister(); | |
4303 | return ret; | |
b481de9c ZY |
4304 | } |
4305 | ||
bb8c093b | 4306 | static void __exit iwl3945_exit(void) |
b481de9c | 4307 | { |
bb8c093b | 4308 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 4309 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
4310 | } |
4311 | ||
a0987a8d | 4312 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 4313 | |
4e30cb69 | 4314 | module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO); |
b481de9c | 4315 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
4e30cb69 | 4316 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO); |
9c74d9fb SO |
4317 | MODULE_PARM_DESC(swcrypto, |
4318 | "using software crypto (default 1 [software])\n"); | |
a562a9dd | 4319 | #ifdef CONFIG_IWLWIFI_DEBUG |
4e30cb69 | 4320 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
b481de9c | 4321 | MODULE_PARM_DESC(debug, "debug output mask"); |
a562a9dd | 4322 | #endif |
4e30cb69 WYG |
4323 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, |
4324 | int, S_IRUGO); | |
b481de9c | 4325 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
4e30cb69 | 4326 | module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO); |
af48d048 SO |
4327 | MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error"); |
4328 | ||
bb8c093b CH |
4329 | module_exit(iwl3945_exit); |
4330 | module_init(iwl3945_init); |