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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
WT
51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
b481de9c
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55#include "iwl-3945.h"
56#include "iwl-helpers.h"
5747d47f 57#include "iwl-core.h"
d20b3c65 58#include "iwl-dev.h"
b481de9c 59
b481de9c
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60/*
61 * module name, copyright, version, etc.
b481de9c
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62 */
63
64#define DRV_DESCRIPTION \
65"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
66
d08853a3 67#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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68#define VD "d"
69#else
70#define VD
71#endif
72
c8b0e6e1 73#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
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74#define VS "s"
75#else
76#define VS
77#endif
78
eaa686c3 79#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 80#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 82#define DRV_VERSION IWL39_VERSION
b481de9c 83
b481de9c
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84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
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88MODULE_LICENSE("GPL");
89
df878d8f
KA
90 /* module parameters */
91struct iwl_mod_params iwl3945_mod_params = {
5905a1aa 92 .num_of_queues = IWL39_NUM_QUEUES, /* Not used */
9c74d9fb 93 .sw_crypto = 1,
af48d048 94 .restart_fw = 1,
df878d8f
KA
95 /* the rest are 0 by default */
96};
97
7e4bca5e
SO
98/**
99 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
100 * @priv: eeprom and antenna fields are used to determine antenna flags
101 *
102 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
103 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
104 *
105 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
106 * IWL_ANTENNA_MAIN - Force MAIN antenna
107 * IWL_ANTENNA_AUX - Force AUX antenna
108 */
109__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
110{
111 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
112
113 switch (iwl3945_mod_params.antenna) {
114 case IWL_ANTENNA_DIVERSITY:
115 return 0;
116
117 case IWL_ANTENNA_MAIN:
118 if (eeprom->antenna_switch_type)
119 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
121
122 case IWL_ANTENNA_AUX:
123 if (eeprom->antenna_switch_type)
124 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
126 }
127
128 /* bad antenna selector value */
129 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
130 iwl3945_mod_params.antenna);
131
132 return 0; /* "diversity" is default if error */
133}
134
6e21f15c 135static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
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136 struct ieee80211_key_conf *keyconf,
137 u8 sta_id)
138{
139 unsigned long flags;
140 __le16 key_flags = 0;
6e21f15c
AK
141 int ret;
142
143 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
144 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
145
146 if (sta_id == priv->hw_params.bcast_sta_id)
147 key_flags |= STA_KEY_MULTICAST_MSK;
148
149 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
150 keyconf->hw_key_idx = keyconf->keyidx;
151 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 152
b481de9c 153 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
154 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
155 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
156 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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157 keyconf->keylen);
158
c587de0b 159 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 160 keyconf->keylen);
6e21f15c 161
c587de0b 162 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 163 == STA_KEY_FLG_NO_ENC)
c587de0b 164 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
165 iwl_get_free_ucode_key_index(priv);
166 /* else, we are overriding an existing key => no need to allocated room
167 * in uCode. */
168
c587de0b 169 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
170 "no space for a new key");
171
c587de0b
TW
172 priv->stations[sta_id].sta.key.key_flags = key_flags;
173 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
174 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 175
6e21f15c
AK
176 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
177
c587de0b 178 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 179
b481de9c
ZY
180 spin_unlock_irqrestore(&priv->sta_lock, flags);
181
6e21f15c
AK
182 return ret;
183}
184
185static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
186 struct ieee80211_key_conf *keyconf,
187 u8 sta_id)
188{
189 return -EOPNOTSUPP;
190}
191
192static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
193 struct ieee80211_key_conf *keyconf,
194 u8 sta_id)
195{
196 return -EOPNOTSUPP;
b481de9c
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197}
198
4a8a4322 199static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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200{
201 unsigned long flags;
202
203 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
204 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
205 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 206 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
207 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
208 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
209 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
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210 spin_unlock_irqrestore(&priv->sta_lock, flags);
211
e1623446 212 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 213 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
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214 return 0;
215}
216
fa11d525 217static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
218 struct ieee80211_key_conf *keyconf, u8 sta_id)
219{
220 int ret = 0;
221
222 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
223
224 switch (keyconf->alg) {
225 case ALG_CCMP:
226 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
227 break;
228 case ALG_TKIP:
229 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
230 break;
231 case ALG_WEP:
232 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
233 break;
234 default:
1e680233 235 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
236 ret = -EINVAL;
237 }
238
239 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
240 keyconf->alg, keyconf->keylen, keyconf->keyidx,
241 sta_id, ret);
242
243 return ret;
244}
245
246static int iwl3945_remove_static_key(struct iwl_priv *priv)
247{
248 int ret = -EOPNOTSUPP;
249
250 return ret;
251}
252
253static int iwl3945_set_static_key(struct iwl_priv *priv,
254 struct ieee80211_key_conf *key)
255{
256 if (key->alg == ALG_WEP)
257 return -EOPNOTSUPP;
258
259 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
260 return -EINVAL;
261}
262
4a8a4322 263static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
264{
265 struct list_head *element;
266
e1623446 267 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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268 priv->frames_count);
269
270 while (!list_empty(&priv->free_frames)) {
271 element = priv->free_frames.next;
272 list_del(element);
bb8c093b 273 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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274 priv->frames_count--;
275 }
276
277 if (priv->frames_count) {
39aadf8c 278 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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279 priv->frames_count);
280 priv->frames_count = 0;
281 }
282}
283
4a8a4322 284static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 285{
bb8c093b 286 struct iwl3945_frame *frame;
b481de9c
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287 struct list_head *element;
288 if (list_empty(&priv->free_frames)) {
289 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
290 if (!frame) {
15b1687c 291 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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292 return NULL;
293 }
294
295 priv->frames_count++;
296 return frame;
297 }
298
299 element = priv->free_frames.next;
300 list_del(element);
bb8c093b 301 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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302}
303
4a8a4322 304static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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305{
306 memset(frame, 0, sizeof(*frame));
307 list_add(&frame->list, &priv->free_frames);
308}
309
4a8a4322 310unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 311 struct ieee80211_hdr *hdr,
73ec1cc2 312 int left)
b481de9c
ZY
313{
314
8ccde88a 315 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
316 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
317 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
318 return 0;
319
320 if (priv->ibss_beacon->len > left)
321 return 0;
322
323 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
324
325 return priv->ibss_beacon->len;
326}
327
4a8a4322 328static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 329{
bb8c093b 330 struct iwl3945_frame *frame;
b481de9c
ZY
331 unsigned int frame_size;
332 int rc;
333 u8 rate;
334
bb8c093b 335 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
336
337 if (!frame) {
15b1687c 338 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
339 "command.\n");
340 return -ENOMEM;
341 }
342
8ccde88a 343 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 344
bb8c093b 345 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 346
518099a8 347 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
348 &frame->u.cmd[0]);
349
bb8c093b 350 iwl3945_free_frame(priv, frame);
b481de9c
ZY
351
352 return rc;
353}
354
4a8a4322 355static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 356{
3832ec9d 357 if (priv->shared_virt)
b481de9c 358 pci_free_consistent(priv->pci_dev,
bb8c093b 359 sizeof(struct iwl3945_shared),
3832ec9d
AK
360 priv->shared_virt,
361 priv->shared_phys);
b481de9c
ZY
362}
363
4a8a4322 364static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 365 struct ieee80211_tx_info *info,
c2acea8e 366 struct iwl_device_cmd *cmd,
b481de9c 367 struct sk_buff *skb_frag,
6e21f15c 368 int sta_id)
b481de9c 369{
e52119c5 370 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 371 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
372
373 switch (keyinfo->alg) {
374 case ALG_CCMP:
e52119c5
WT
375 tx->sec_ctl = TX_CMD_SEC_CCM;
376 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
e1623446 377 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
378 break;
379
380 case ALG_TKIP:
b481de9c
ZY
381 break;
382
383 case ALG_WEP:
e52119c5 384 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 385 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
386
387 if (keyinfo->keylen == 13)
e52119c5 388 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 389
e52119c5 390 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 391
e1623446 392 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 393 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
394 break;
395
b481de9c 396 default:
978785a3 397 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
398 break;
399 }
400}
401
402/*
403 * handle build REPLY_TX command notification.
404 */
4a8a4322 405static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 406 struct iwl_device_cmd *cmd,
e039fa4a 407 struct ieee80211_tx_info *info,
e52119c5 408 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 409{
e52119c5
WT
410 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
411 __le32 tx_flags = tx->tx_flags;
fd7c8a40 412 __le16 fc = hdr->frame_control;
e6a9854b 413 u8 rc_flags = info->control.rates[0].flags;
b481de9c 414
e52119c5 415 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 416 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 417 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 418 if (ieee80211_is_mgmt(fc))
b481de9c 419 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 420 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
421 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
422 tx_flags |= TX_CMD_FLG_TSF_MSK;
423 } else {
424 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
425 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
426 }
427
e52119c5 428 tx->sta_id = std_id;
8b7b1e05 429 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
430 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
431
fd7c8a40
HH
432 if (ieee80211_is_data_qos(fc)) {
433 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 434 tx->tid_tspec = qc[0] & 0xf;
b481de9c 435 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 436 } else {
b481de9c 437 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 438 }
b481de9c 439
e6a9854b 440 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
441 tx_flags |= TX_CMD_FLG_RTS_MSK;
442 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 443 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY
444 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
445 tx_flags |= TX_CMD_FLG_CTS_MSK;
446 }
447
448 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
449 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
450
451 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
452 if (ieee80211_is_mgmt(fc)) {
453 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 454 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 455 else
e52119c5 456 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 457 } else {
e52119c5 458 tx->timeout.pm_frame_timeout = 0;
5c8df2d5 459#ifdef CONFIG_IWLWIFI_LEDS
ab53d8af
MA
460 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
461#endif
462 }
b481de9c 463
e52119c5
WT
464 tx->driver_txop = 0;
465 tx->tx_flags = tx_flags;
466 tx->next_frame_len = 0;
b481de9c
ZY
467}
468
b481de9c
ZY
469/*
470 * start REPLY_TX command process
471 */
4a8a4322 472static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
473{
474 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 475 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e52119c5 476 struct iwl3945_tx_cmd *tx;
188cf6c7 477 struct iwl_tx_queue *txq = NULL;
d20b3c65 478 struct iwl_queue *q = NULL;
c2acea8e
JB
479 struct iwl_device_cmd *out_cmd;
480 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
481 dma_addr_t phys_addr;
482 dma_addr_t txcmd_phys;
e52119c5 483 int txq_id = skb_get_queue_mapping(skb);
df833b1d 484 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
485 u8 id;
486 u8 unicast;
b481de9c 487 u8 sta_id;
54dbb525 488 u8 tid = 0;
b481de9c 489 u16 seq_number = 0;
fd7c8a40 490 __le16 fc;
b481de9c 491 u8 wait_write_ptr = 0;
54dbb525 492 u8 *qc = NULL;
b481de9c
ZY
493 unsigned long flags;
494 int rc;
495
496 spin_lock_irqsave(&priv->lock, flags);
775a6e27 497 if (iwl_is_rfkill(priv)) {
e1623446 498 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
499 goto drop_unlock;
500 }
501
e039fa4a 502 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 503 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
504 goto drop_unlock;
505 }
506
507 unicast = !is_multicast_ether_addr(hdr->addr1);
508 id = 0;
509
fd7c8a40 510 fc = hdr->frame_control;
b481de9c 511
d08853a3 512#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 513 if (ieee80211_is_auth(fc))
e1623446 514 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 515 else if (ieee80211_is_assoc_req(fc))
e1623446 516 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 517 else if (ieee80211_is_reassoc_req(fc))
e1623446 518 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
519#endif
520
aa065263 521 /* drop all non-injected data frame if we are not associated */
914233d6 522 if (ieee80211_is_data(fc) &&
aa065263 523 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
8ccde88a 524 (!iwl_is_associated(priv) ||
05c914fe 525 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 526 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
527 goto drop_unlock;
528 }
529
530 spin_unlock_irqrestore(&priv->lock, flags);
531
7294ec95 532 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
533
534 /* Find (or create) index into station table for destination station */
aa065263
GS
535 if (info->flags & IEEE80211_TX_CTL_INJECTED)
536 sta_id = priv->hw_params.bcast_sta_id;
537 else
538 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 539 if (sta_id == IWL_INVALID_STATION) {
e1623446 540 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 541 hdr->addr1);
b481de9c
ZY
542 goto drop;
543 }
544
e1623446 545 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 546
fd7c8a40
HH
547 if (ieee80211_is_data_qos(fc)) {
548 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 549 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
550 if (unlikely(tid >= MAX_TID_COUNT))
551 goto drop;
c587de0b 552 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
553 IEEE80211_SCTL_SEQ;
554 hdr->seq_ctrl = cpu_to_le16(seq_number) |
555 (hdr->seq_ctrl &
c1b4aa3f 556 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
557 seq_number += 0x10;
558 }
6440adb5
BC
559
560 /* Descriptor for chosen Tx queue */
188cf6c7 561 txq = &priv->txq[txq_id];
b481de9c
ZY
562 q = &txq->q;
563
564 spin_lock_irqsave(&priv->lock, flags);
565
fc4b6853 566 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 567
6440adb5 568 /* Set up driver data for this TFD */
dbb6654c 569 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 570 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
571
572 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 573 out_cmd = txq->cmd[idx];
c2acea8e 574 out_meta = &txq->meta[idx];
e52119c5 575 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 576 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 577 memset(tx, 0, sizeof(*tx));
6440adb5
BC
578
579 /*
580 * Set up the Tx-command (not MAC!) header.
581 * Store the chosen Tx queue and TFD index within the sequence field;
582 * after Tx, uCode's Tx response will return this value so driver can
583 * locate the frame within the tx queue and do post-tx processing.
584 */
b481de9c
ZY
585 out_cmd->hdr.cmd = REPLY_TX;
586 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 587 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
588
589 /* Copy MAC header from skb into command buffer */
e52119c5 590 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 591
df833b1d
RC
592
593 if (info->control.hw_key)
594 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
595
596 /* TODO need this for burst mode later on */
597 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
598
599 /* set is_hcca to 0; it probably will never be implemented */
600 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
601
602 /* Total # bytes to be transmitted */
603 len = (u16)skb->len;
604 tx->len = cpu_to_le16(len);
605
20594eb0 606 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 607 iwl_update_stats(priv, true, fc, len);
df833b1d
RC
608 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
609 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
610
611 if (!ieee80211_has_morefrags(hdr->frame_control)) {
612 txq->need_update = 1;
613 if (qc)
c587de0b 614 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
615 } else {
616 wait_write_ptr = 1;
617 txq->need_update = 0;
618 }
619
620 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
621 le16_to_cpu(out_cmd->hdr.sequence));
622 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags));
3d816c77
RC
623 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
624 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
df833b1d
RC
625 ieee80211_hdrlen(fc));
626
6440adb5
BC
627 /*
628 * Use the first empty entry in this queue's command buffer array
629 * to contain the Tx command and MAC header concatenated together
630 * (payload data will be in another buffer).
631 * Size of this varies, due to varying MAC header length.
632 * If end is not dword aligned, we'll have 2 extra bytes at the end
633 * of the MAC header (device reads on dword boundaries).
634 * We'll tell device about this padding later.
635 */
3832ec9d 636 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 637 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
638
639 len_org = len;
640 len = (len + 3) & ~3;
641
642 if (len_org != len)
643 len_org = 1;
644 else
645 len_org = 0;
646
6440adb5
BC
647 /* Physical address of this Tx command's header (not MAC header!),
648 * within command buffer array. */
df833b1d
RC
649 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
650 len, PCI_DMA_TODEVICE);
651 /* we do not map meta data ... so we can safely access address to
652 * provide to unmap command*/
c2acea8e
JB
653 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
654 pci_unmap_len_set(out_meta, len, len);
b481de9c 655
6440adb5
BC
656 /* Add buffer containing Tx command and MAC(!) header to TFD's
657 * first entry */
7aaa1d79
SO
658 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
659 txcmd_phys, len, 1, 0);
b481de9c 660
b481de9c 661
6440adb5
BC
662 /* Set up TFD's 2nd entry to point directly to remainder of skb,
663 * if any (802.11 null frames have no payload). */
b481de9c
ZY
664 len = skb->len - hdr_len;
665 if (len) {
666 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
667 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
668 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
669 phys_addr, len,
670 0, U32_PAD(len));
b481de9c
ZY
671 }
672
b481de9c 673
6440adb5 674 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 675 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 676 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
677 spin_unlock_irqrestore(&priv->lock, flags);
678
679 if (rc)
680 return rc;
681
d20b3c65 682 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
683 && priv->mac80211_registered) {
684 if (wait_write_ptr) {
685 spin_lock_irqsave(&priv->lock, flags);
686 txq->need_update = 1;
4f3602c8 687 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
688 spin_unlock_irqrestore(&priv->lock, flags);
689 }
690
e4e72fb4 691 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
692 }
693
694 return 0;
695
696drop_unlock:
697 spin_unlock_irqrestore(&priv->lock, flags);
698drop:
699 return -1;
700}
701
c8b0e6e1 702#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
703
704#include "iwl-spectrum.h"
705
706#define BEACON_TIME_MASK_LOW 0x00FFFFFF
707#define BEACON_TIME_MASK_HIGH 0xFF000000
708#define TIME_UNIT 1024
709
710/*
711 * extended beacon time format
712 * time in usec will be changed into a 32-bit value in 8:24 format
713 * the high 1 byte is the beacon counts
714 * the lower 3 bytes is the time in usec within one beacon interval
715 */
716
bb8c093b 717static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
718{
719 u32 quot;
720 u32 rem;
721 u32 interval = beacon_interval * 1024;
722
723 if (!interval || !usec)
724 return 0;
725
726 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
727 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
728
729 return (quot << 24) + rem;
730}
731
732/* base is usually what we get from ucode with each received frame,
733 * the same as HW timer counter counting down
734 */
735
bb8c093b 736static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
737{
738 u32 base_low = base & BEACON_TIME_MASK_LOW;
739 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
740 u32 interval = beacon_interval * TIME_UNIT;
741 u32 res = (base & BEACON_TIME_MASK_HIGH) +
742 (addon & BEACON_TIME_MASK_HIGH);
743
744 if (base_low > addon_low)
745 res += base_low - addon_low;
746 else if (base_low < addon_low) {
747 res += interval + base_low - addon_low;
748 res += (1 << 24);
749 } else
750 res += (1 << 24);
751
752 return cpu_to_le32(res);
753}
754
4a8a4322 755static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
756 struct ieee80211_measurement_params *params,
757 u8 type)
758{
600c0e11 759 struct iwl_spectrum_cmd spectrum;
3d24a9f7 760 struct iwl_rx_packet *res;
c2d79b48 761 struct iwl_host_cmd cmd = {
b481de9c
ZY
762 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
763 .data = (void *)&spectrum,
c2acea8e 764 .flags = CMD_WANT_SKB,
b481de9c
ZY
765 };
766 u32 add_time = le64_to_cpu(params->start_time);
767 int rc;
768 int spectrum_resp_status;
769 int duration = le16_to_cpu(params->duration);
770
8ccde88a 771 if (iwl_is_associated(priv))
b481de9c 772 add_time =
bb8c093b 773 iwl3945_usecs_to_beacons(
b481de9c
ZY
774 le64_to_cpu(params->start_time) - priv->last_tsf,
775 le16_to_cpu(priv->rxon_timing.beacon_interval));
776
777 memset(&spectrum, 0, sizeof(spectrum));
778
779 spectrum.channel_count = cpu_to_le16(1);
780 spectrum.flags =
781 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
782 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
783 cmd.len = sizeof(spectrum);
784 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
785
8ccde88a 786 if (iwl_is_associated(priv))
b481de9c 787 spectrum.start_time =
bb8c093b 788 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
789 add_time,
790 le16_to_cpu(priv->rxon_timing.beacon_interval));
791 else
792 spectrum.start_time = 0;
793
794 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
795 spectrum.channels[0].channel = params->channel;
796 spectrum.channels[0].type = type;
8ccde88a 797 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
798 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
799 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
800
518099a8 801 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
802 if (rc)
803 return rc;
804
c2acea8e 805 res = (struct iwl_rx_packet *)cmd.reply_skb->data;
b481de9c 806 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 807 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
808 rc = -EIO;
809 }
810
811 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
812 switch (spectrum_resp_status) {
813 case 0: /* Command will be handled */
814 if (res->u.spectrum.id != 0xff) {
e1623446 815 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
bc434dd2 816 res->u.spectrum.id);
b481de9c
ZY
817 priv->measurement_status &= ~MEASUREMENT_READY;
818 }
819 priv->measurement_status |= MEASUREMENT_ACTIVE;
820 rc = 0;
821 break;
822
823 case 1: /* Command will not be handled */
824 rc = -EAGAIN;
825 break;
826 }
827
c2acea8e 828 dev_kfree_skb_any(cmd.reply_skb);
b481de9c
ZY
829
830 return rc;
831}
832#endif
833
4a8a4322 834static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 835 struct iwl_rx_mem_buffer *rxb)
b481de9c 836{
3d24a9f7
TW
837 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
838 struct iwl_alive_resp *palive;
b481de9c
ZY
839 struct delayed_work *pwork;
840
841 palive = &pkt->u.alive_frame;
842
e1623446 843 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
844 "0x%01X 0x%01X\n",
845 palive->is_valid, palive->ver_type,
846 palive->ver_subtype);
847
848 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 849 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
850 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
851 sizeof(struct iwl_alive_resp));
b481de9c
ZY
852 pwork = &priv->init_alive_start;
853 } else {
e1623446 854 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 855 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 856 sizeof(struct iwl_alive_resp));
b481de9c 857 pwork = &priv->alive_start;
bb8c093b 858 iwl3945_disable_events(priv);
b481de9c
ZY
859 }
860
861 /* We delay the ALIVE response by 5ms to
862 * give the HW RF Kill time to activate... */
863 if (palive->is_valid == UCODE_VALID_OK)
864 queue_delayed_work(priv->workqueue, pwork,
865 msecs_to_jiffies(5));
866 else
39aadf8c 867 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
868}
869
4a8a4322 870static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 871 struct iwl_rx_mem_buffer *rxb)
b481de9c 872{
c7e035a9 873#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 874 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
c7e035a9 875#endif
b481de9c 876
e1623446 877 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
878 return;
879}
880
bb8c093b 881static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 882{
4a8a4322
AK
883 struct iwl_priv *priv =
884 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
885 struct sk_buff *beacon;
886
887 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 888 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
889
890 if (!beacon) {
15b1687c 891 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
892 return;
893 }
894
895 mutex_lock(&priv->mutex);
896 /* new beacon skb is allocated every time; dispose previous.*/
897 if (priv->ibss_beacon)
898 dev_kfree_skb(priv->ibss_beacon);
899
900 priv->ibss_beacon = beacon;
901 mutex_unlock(&priv->mutex);
902
bb8c093b 903 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
904}
905
4a8a4322 906static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 907 struct iwl_rx_mem_buffer *rxb)
b481de9c 908{
d08853a3 909#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 910 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 911 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
912 u8 rate = beacon->beacon_notify_hdr.rate;
913
e1623446 914 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
915 "tsf %d %d rate %d\n",
916 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
917 beacon->beacon_notify_hdr.failure_frame,
918 le32_to_cpu(beacon->ibss_mgr_status),
919 le32_to_cpu(beacon->high_tsf),
920 le32_to_cpu(beacon->low_tsf), rate);
921#endif
922
05c914fe 923 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
924 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
925 queue_work(priv->workqueue, &priv->beacon_update);
926}
927
b481de9c
ZY
928/* Handle notification from uCode that card's power state is changing
929 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 930static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 931 struct iwl_rx_mem_buffer *rxb)
b481de9c 932{
3d24a9f7 933 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
934 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
935 unsigned long status = priv->status;
936
4c423a2b 937 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
938 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
939 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
940
5d49f498 941 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
942 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
943
944 if (flags & HW_CARD_DISABLED)
945 set_bit(STATUS_RF_KILL_HW, &priv->status);
946 else
947 clear_bit(STATUS_RF_KILL_HW, &priv->status);
948
949
af0053d6 950 iwl_scan_cancel(priv);
b481de9c
ZY
951
952 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
953 test_bit(STATUS_RF_KILL_HW, &priv->status)))
954 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
955 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
956 else
957 wake_up_interruptible(&priv->wait_command_queue);
958}
959
960/**
bb8c093b 961 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
962 *
963 * Setup the RX handlers for each of the reply types sent from the uCode
964 * to the host.
965 *
966 * This function chains into the hardware specific files for them to setup
967 * any hardware specific handlers as well.
968 */
4a8a4322 969static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 970{
bb8c093b
CH
971 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
972 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 973 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 974 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
030f05ed 975 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 976 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 977 iwl_rx_pm_debug_statistics_notif;
bb8c093b 978 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 979
9fbab516
BC
980 /*
981 * The same handler is used for both the REPLY to a discrete
982 * statistics request from the host as well as for the periodic
983 * statistics notifications (after received beacons) from the uCode.
b481de9c 984 */
bb8c093b
CH
985 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
986 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 987
261b9c33 988 iwl_setup_spectrum_handlers(priv);
cade0eb2 989 iwl_setup_rx_scan_handlers(priv);
bb8c093b 990 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 991
9fbab516 992 /* Set up hardware specific Rx handlers */
bb8c093b 993 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
994}
995
b481de9c
ZY
996/************************** RX-FUNCTIONS ****************************/
997/*
998 * Rx theory of operation
999 *
1000 * The host allocates 32 DMA target addresses and passes the host address
1001 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
1002 * 0 to 31
1003 *
1004 * Rx Queue Indexes
1005 * The host/firmware share two index registers for managing the Rx buffers.
1006 *
1007 * The READ index maps to the first position that the firmware may be writing
1008 * to -- the driver can read up to (but not including) this position and get
1009 * good data.
1010 * The READ index is managed by the firmware once the card is enabled.
1011 *
1012 * The WRITE index maps to the last position the driver has read from -- the
1013 * position preceding WRITE is the last slot the firmware can place a packet.
1014 *
1015 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1016 * WRITE = READ.
1017 *
9fbab516 1018 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1019 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1020 *
9fbab516 1021 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1022 * and fire the RX interrupt. The driver can then query the READ index and
1023 * process as many packets as possible, moving the WRITE index forward as it
1024 * resets the Rx queue buffers with new memory.
1025 *
1026 * The management in the driver is as follows:
1027 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1028 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1029 * to replenish the iwl->rxq->rx_free.
bb8c093b 1030 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1031 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1032 * 'processed' and 'read' driver indexes as well)
1033 * + A received packet is processed and handed to the kernel network stack,
1034 * detached from the iwl->rxq. The driver 'processed' index is updated.
1035 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1036 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1037 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1038 * were enough free buffers and RX_STALLED is set it is cleared.
1039 *
1040 *
1041 * Driver sequence:
1042 *
9fbab516 1043 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1044 * iwl3945_rx_queue_restock
9fbab516 1045 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1046 * queue, updates firmware pointers, and updates
1047 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1048 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1049 *
1050 * -- enable interrupts --
6100b588 1051 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1052 * READ INDEX, detaching the SKB from the pool.
1053 * Moves the packet buffer from queue to rx_used.
bb8c093b 1054 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1055 * slots.
1056 * ...
1057 *
1058 */
1059
b481de9c 1060/**
9fbab516 1061 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1062 */
4a8a4322 1063static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1064 dma_addr_t dma_addr)
1065{
1066 return cpu_to_le32((u32)dma_addr);
1067}
1068
1069/**
bb8c093b 1070 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1071 *
9fbab516 1072 * If there are slots in the RX queue that need to be restocked,
b481de9c 1073 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1074 * as we can, pulling from rx_free.
b481de9c
ZY
1075 *
1076 * This moves the 'write' index forward to catch up with 'processed', and
1077 * also updates the memory address in the firmware to reference the new
1078 * target buffer.
1079 */
4a8a4322 1080static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1081{
cc2f362c 1082 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1083 struct list_head *element;
6100b588 1084 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1085 unsigned long flags;
1086 int write, rc;
1087
1088 spin_lock_irqsave(&rxq->lock, flags);
1089 write = rxq->write & ~0x7;
37d68317 1090 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1091 /* Get next free Rx buffer, remove from free list */
b481de9c 1092 element = rxq->rx_free.next;
6100b588 1093 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1094 list_del(element);
6440adb5
BC
1095
1096 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 1097 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
1098 rxq->queue[rxq->write] = rxb;
1099 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1100 rxq->free_count--;
1101 }
1102 spin_unlock_irqrestore(&rxq->lock, flags);
1103 /* If the pre-allocated buffer pool is dropping low, schedule to
1104 * refill it */
1105 if (rxq->free_count <= RX_LOW_WATERMARK)
1106 queue_work(priv->workqueue, &priv->rx_replenish);
1107
1108
6440adb5
BC
1109 /* If we've added more space for the firmware to place data, tell it.
1110 * Increment device's write pointer in multiples of 8. */
d14d4440 1111 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1112 || (abs(rxq->write - rxq->read) > 7)) {
1113 spin_lock_irqsave(&rxq->lock, flags);
1114 rxq->need_update = 1;
1115 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1116 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1117 if (rc)
1118 return rc;
1119 }
1120
1121 return 0;
1122}
1123
1124/**
bb8c093b 1125 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1126 *
1127 * When moving to rx_free an SKB is allocated for the slot.
1128 *
bb8c093b 1129 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1130 * This is called as a scheduled work item (except for during initialization)
b481de9c 1131 */
d14d4440 1132static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1133{
cc2f362c 1134 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1135 struct list_head *element;
6100b588 1136 struct iwl_rx_mem_buffer *rxb;
de0bd508 1137 struct sk_buff *skb;
b481de9c 1138 unsigned long flags;
72240498
AK
1139
1140 while (1) {
1141 spin_lock_irqsave(&rxq->lock, flags);
1142
1143 if (list_empty(&rxq->rx_used)) {
1144 spin_unlock_irqrestore(&rxq->lock, flags);
1145 return;
1146 }
72240498 1147 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1148
f82a924c
RC
1149 if (rxq->free_count > RX_LOW_WATERMARK)
1150 priority |= __GFP_NOWARN;
6440adb5 1151 /* Alloc a new receive buffer */
de0bd508
RC
1152 skb = alloc_skb(priv->hw_params.rx_buf_size, priority);
1153 if (!skb) {
b481de9c 1154 if (net_ratelimit())
f82a924c
RC
1155 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1156 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1157 net_ratelimit())
1158 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1159 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1160 rxq->free_count);
b481de9c
ZY
1161 /* We don't reschedule replenish work here -- we will
1162 * call the restock method and if it still needs
1163 * more buffers it will schedule replenish */
1164 break;
1165 }
12342c47 1166
de0bd508
RC
1167 spin_lock_irqsave(&rxq->lock, flags);
1168 if (list_empty(&rxq->rx_used)) {
1169 spin_unlock_irqrestore(&rxq->lock, flags);
1170 dev_kfree_skb_any(skb);
1171 return;
1172 }
1173 element = rxq->rx_used.next;
1174 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1175 list_del(element);
1176 spin_unlock_irqrestore(&rxq->lock, flags);
1177
1178 rxb->skb = skb;
1179
12342c47
ZY
1180 /* If radiotap head is required, reserve some headroom here.
1181 * The physical head count is a variable rx_stats->phy_count.
1182 * We reserve 4 bytes here. Plus these extra bytes, the
1183 * headroom of the physical head should be enough for the
1184 * radiotap head that iwl3945 supported. See iwl3945_rt.
1185 */
1186 skb_reserve(rxb->skb, 4);
1187
6440adb5 1188 /* Get physical address of RB/SKB */
1e33dc64
WT
1189 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
1190 rxb->skb->data,
1191 priv->hw_params.rx_buf_size,
1192 PCI_DMA_FROMDEVICE);
72240498
AK
1193
1194 spin_lock_irqsave(&rxq->lock, flags);
b481de9c 1195 list_add_tail(&rxb->list, &rxq->rx_free);
72240498 1196 priv->alloc_rxb_skb++;
b481de9c 1197 rxq->free_count++;
72240498 1198 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1199 }
5c0eef96
MA
1200}
1201
df833b1d
RC
1202void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1203{
1204 unsigned long flags;
1205 int i;
1206 spin_lock_irqsave(&rxq->lock, flags);
1207 INIT_LIST_HEAD(&rxq->rx_free);
1208 INIT_LIST_HEAD(&rxq->rx_used);
1209 /* Fill the rx_used queue with _all_ of the Rx buffers */
1210 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1211 /* In the reset function, these buffers may have been allocated
1212 * to an SKB, so we need to unmap and free potential storage */
1213 if (rxq->pool[i].skb != NULL) {
1214 pci_unmap_single(priv->pci_dev,
1215 rxq->pool[i].real_dma_addr,
1216 priv->hw_params.rx_buf_size,
1217 PCI_DMA_FROMDEVICE);
1218 priv->alloc_rxb_skb--;
1219 dev_kfree_skb(rxq->pool[i].skb);
1220 rxq->pool[i].skb = NULL;
1221 }
1222 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1223 }
1224
1225 /* Set us so that we have processed and used all buffers, but have
1226 * not restocked the Rx queue with fresh buffers */
1227 rxq->read = rxq->write = 0;
1228 rxq->free_count = 0;
d14d4440 1229 rxq->write_actual = 0;
df833b1d
RC
1230 spin_unlock_irqrestore(&rxq->lock, flags);
1231}
df833b1d 1232
5c0eef96
MA
1233void iwl3945_rx_replenish(void *data)
1234{
4a8a4322 1235 struct iwl_priv *priv = data;
5c0eef96
MA
1236 unsigned long flags;
1237
d14d4440 1238 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1239
1240 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1241 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1242 spin_unlock_irqrestore(&priv->lock, flags);
1243}
1244
d14d4440
AK
1245static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1246{
1247 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1248
1249 iwl3945_rx_queue_restock(priv);
1250}
1251
1252
df833b1d
RC
1253/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1254 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1255 * This free routine walks the list of POOL entries and if SKB is set to
1256 * non NULL it is unmapped and freed
1257 */
1258static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1259{
1260 int i;
1261 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1262 if (rxq->pool[i].skb != NULL) {
1263 pci_unmap_single(priv->pci_dev,
1264 rxq->pool[i].real_dma_addr,
1265 priv->hw_params.rx_buf_size,
1266 PCI_DMA_FROMDEVICE);
1267 dev_kfree_skb(rxq->pool[i].skb);
1268 }
1269 }
1270
1271 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1272 rxq->dma_addr);
1273 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1274 rxq->rb_stts, rxq->rb_stts_dma);
1275 rxq->bd = NULL;
1276 rxq->rb_stts = NULL;
1277}
df833b1d
RC
1278
1279
b481de9c
ZY
1280/* Convert linear signal-to-noise ratio into dB */
1281static u8 ratio2dB[100] = {
1282/* 0 1 2 3 4 5 6 7 8 9 */
1283 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1284 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1285 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1286 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1287 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1288 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1289 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1290 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1291 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1292 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1293};
1294
1295/* Calculates a relative dB value from a ratio of linear
1296 * (i.e. not dB) signal levels.
1297 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1298int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1299{
221c80cf
AB
1300 /* 1000:1 or higher just report as 60 dB */
1301 if (sig_ratio >= 1000)
b481de9c
ZY
1302 return 60;
1303
221c80cf 1304 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1305 * add 20 dB to make up for divide by 10 */
221c80cf 1306 if (sig_ratio >= 100)
3ac7f146 1307 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1308
1309 /* We shouldn't see this */
1310 if (sig_ratio < 1)
1311 return 0;
1312
1313 /* Use table for ratios 1:1 - 99:1 */
1314 return (int)ratio2dB[sig_ratio];
1315}
1316
1317#define PERFECT_RSSI (-20) /* dBm */
1318#define WORST_RSSI (-95) /* dBm */
1319#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1320
1321/* Calculate an indication of rx signal quality (a percentage, not dBm!).
1322 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
1323 * about formulas used below. */
bb8c093b 1324int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
1325{
1326 int sig_qual;
1327 int degradation = PERFECT_RSSI - rssi_dbm;
1328
1329 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
1330 * as indicator; formula is (signal dbm - noise dbm).
1331 * SNR at or above 40 is a great signal (100%).
1332 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
1333 * Weakest usable signal is usually 10 - 15 dB SNR. */
1334 if (noise_dbm) {
1335 if (rssi_dbm - noise_dbm >= 40)
1336 return 100;
1337 else if (rssi_dbm < noise_dbm)
1338 return 0;
1339 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1340
1341 /* Else use just the signal level.
1342 * This formula is a least squares fit of data points collected and
1343 * compared with a reference system that had a percentage (%) display
1344 * for signal quality. */
1345 } else
1346 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1347 (15 * RSSI_RANGE + 62 * degradation)) /
1348 (RSSI_RANGE * RSSI_RANGE);
1349
1350 if (sig_qual > 100)
1351 sig_qual = 100;
1352 else if (sig_qual < 1)
1353 sig_qual = 0;
1354
1355 return sig_qual;
1356}
1357
1358/**
9fbab516 1359 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1360 *
1361 * Uses the priv->rx_handlers callback function array to invoke
1362 * the appropriate handlers, including command responses,
1363 * frame-received notifications, and other notifications.
1364 */
4a8a4322 1365static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1366{
6100b588 1367 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1368 struct iwl_rx_packet *pkt;
cc2f362c 1369 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1370 u32 r, i;
1371 int reclaim;
1372 unsigned long flags;
5c0eef96 1373 u8 fill_rx = 0;
d68ab680 1374 u32 count = 8;
d14d4440 1375 int total_empty = 0;
b481de9c 1376
6440adb5
BC
1377 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1378 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1379 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1380 i = rxq->read;
1381
d14d4440
AK
1382 /* calculate total frames need to be restock after handling RX */
1383 total_empty = r - priv->rxq.write_actual;
1384 if (total_empty < 0)
1385 total_empty += RX_QUEUE_SIZE;
1386
1387 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1388 fill_rx = 1;
b481de9c
ZY
1389 /* Rx interrupt, but nothing sent from uCode */
1390 if (i == r)
af472a95 1391 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1392
1393 while (i != r) {
1394 rxb = rxq->queue[i];
1395
9fbab516 1396 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1397 * then a bug has been introduced in the queue refilling
1398 * routines -- catch it here */
1399 BUG_ON(rxb == NULL);
1400
1401 rxq->queue[i] = NULL;
1402
df833b1d
RC
1403 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1404 priv->hw_params.rx_buf_size,
1405 PCI_DMA_FROMDEVICE);
3d24a9f7 1406 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
1407
1408 /* Reclaim a command buffer only if this packet is a response
1409 * to a (driver-originated) command.
1410 * If the packet (e.g. Rx frame) originated from uCode,
1411 * there is no command buffer to reclaim.
1412 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1413 * but apparently a few don't get set; catch them here. */
1414 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1415 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1416 (pkt->hdr.cmd != REPLY_TX);
1417
1418 /* Based on type of command response or notification,
1419 * handle those that need handling via function in
bb8c093b 1420 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1421 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1422 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c
ZY
1423 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1424 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
86ddbf62 1425 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
1426 } else {
1427 /* No handling needed */
af472a95 1428 IWL_DEBUG_RX(priv, "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1429 r, i, get_cmd_string(pkt->hdr.cmd),
1430 pkt->hdr.cmd);
1431 }
1432
1433 if (reclaim) {
9fbab516 1434 /* Invoke any callbacks, transfer the skb to caller, and
518099a8 1435 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
1436 * as we reclaim the driver command queue */
1437 if (rxb && rxb->skb)
732587ab 1438 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1439 else
39aadf8c 1440 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1441 }
1442
1443 /* For now we just don't re-use anything. We can tweak this
1444 * later to try and re-use notification packets and SKBs that
1445 * fail to Rx correctly */
1446 if (rxb->skb != NULL) {
1447 priv->alloc_rxb_skb--;
1448 dev_kfree_skb_any(rxb->skb);
1449 rxb->skb = NULL;
1450 }
1451
b481de9c
ZY
1452 spin_lock_irqsave(&rxq->lock, flags);
1453 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1454 spin_unlock_irqrestore(&rxq->lock, flags);
1455 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1456 /* If there are a lot of unused frames,
1457 * restock the Rx queue so ucode won't assert. */
1458 if (fill_rx) {
1459 count++;
1460 if (count >= 8) {
1461 priv->rxq.read = i;
d14d4440 1462 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1463 count = 0;
1464 }
1465 }
b481de9c
ZY
1466 }
1467
1468 /* Backtrack one entry */
1469 priv->rxq.read = i;
d14d4440
AK
1470 if (fill_rx)
1471 iwl3945_rx_replenish_now(priv);
1472 else
1473 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1474}
1475
0359facc 1476/* call this function to flush any scheduled tasklet */
4a8a4322 1477static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1478{
a96a27f9 1479 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1480 synchronize_irq(priv->pci_dev->irq);
1481 tasklet_kill(&priv->irq_tasklet);
1482}
1483
b7a79404 1484#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1485static const char *desc_lookup(int i)
1486{
1487 switch (i) {
1488 case 1:
1489 return "FAIL";
1490 case 2:
1491 return "BAD_PARAM";
1492 case 3:
1493 return "BAD_CHECKSUM";
1494 case 4:
1495 return "NMI_INTERRUPT";
1496 case 5:
1497 return "SYSASSERT";
1498 case 6:
1499 return "FATAL_ERROR";
1500 }
1501
1502 return "UNKNOWN";
1503}
1504
1505#define ERROR_START_OFFSET (1 * sizeof(u32))
1506#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1507
b7a79404 1508void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1509{
1510 u32 i;
1511 u32 desc, time, count, base, data1;
1512 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1513
1514 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1515
bb8c093b 1516 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1517 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1518 return;
1519 }
1520
b481de9c 1521
5d49f498 1522 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1523
1524 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1525 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1526 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1527 priv->status, count);
b481de9c
ZY
1528 }
1529
15b1687c 1530 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1531 "ilink1 nmiPC Line\n");
1532 for (i = ERROR_START_OFFSET;
1533 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1534 i += ERROR_ELEM_SIZE) {
5d49f498 1535 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1536 time =
5d49f498 1537 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1538 blink1 =
5d49f498 1539 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1540 blink2 =
5d49f498 1541 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1542 ilink1 =
5d49f498 1543 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1544 ilink2 =
5d49f498 1545 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1546 data1 =
5d49f498 1547 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1548
15b1687c
WT
1549 IWL_ERR(priv,
1550 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1551 desc_lookup(desc), desc, time, blink1, blink2,
1552 ilink1, ilink2, data1);
b481de9c
ZY
1553 }
1554
b481de9c
ZY
1555}
1556
f58177b9 1557#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1558
1559/**
bb8c093b 1560 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1561 *
b481de9c 1562 */
4a8a4322 1563static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
1564 u32 num_events, u32 mode)
1565{
1566 u32 i;
1567 u32 base; /* SRAM byte address of event log header */
1568 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1569 u32 ptr; /* SRAM byte address of log data */
1570 u32 ev, time, data; /* event log data */
1571
1572 if (num_events == 0)
1573 return;
1574
1575 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1576
1577 if (mode == 0)
1578 event_size = 2 * sizeof(u32);
1579 else
1580 event_size = 3 * sizeof(u32);
1581
1582 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1583
1584 /* "time" is actually "data" for mode 0 (no timestamp).
1585 * place event id # at far right for easier visual parsing. */
1586 for (i = 0; i < num_events; i++) {
5d49f498 1587 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 1588 ptr += sizeof(u32);
5d49f498 1589 time = iwl_read_targ_mem(priv, ptr);
b481de9c 1590 ptr += sizeof(u32);
15b1687c
WT
1591 if (mode == 0) {
1592 /* data, ev */
1593 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1594 } else {
5d49f498 1595 data = iwl_read_targ_mem(priv, ptr);
b481de9c 1596 ptr += sizeof(u32);
15b1687c 1597 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
1598 }
1599 }
1600}
1601
b7a79404 1602void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c 1603{
b481de9c
ZY
1604 u32 base; /* SRAM byte address of event log header */
1605 u32 capacity; /* event log capacity in # entries */
1606 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1607 u32 num_wraps; /* # times uCode wrapped to top of log */
1608 u32 next_entry; /* index of next entry to be written by uCode */
1609 u32 size; /* # entries that we'll print */
1610
1611 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1612 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1613 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
1614 return;
1615 }
1616
b481de9c 1617 /* event log header */
5d49f498
AK
1618 capacity = iwl_read_targ_mem(priv, base);
1619 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1620 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1621 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
1622
1623 size = num_wraps ? capacity : next_entry;
1624
1625 /* bail out if nothing in log */
1626 if (size == 0) {
15b1687c 1627 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b481de9c
ZY
1628 return;
1629 }
1630
15b1687c 1631 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
1632 size, num_wraps);
1633
1634 /* if uCode has wrapped back to top of log, start at the oldest entry,
1635 * i.e the next one that uCode would fill. */
1636 if (num_wraps)
bb8c093b 1637 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
1638 capacity - next_entry, mode);
1639
1640 /* (then/else) start at top of log */
bb8c093b 1641 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 1642
b481de9c 1643}
b7a79404
RC
1644#else
1645void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1646{
1647}
1648
1649void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1650{
1651}
1652
1653#endif
b481de9c 1654
4a8a4322 1655static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1656{
1657 u32 inta, handled = 0;
1658 u32 inta_fh;
1659 unsigned long flags;
d08853a3 1660#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1661 u32 inta_mask;
1662#endif
1663
1664 spin_lock_irqsave(&priv->lock, flags);
1665
1666 /* Ack/clear/reset pending uCode interrupts.
1667 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1668 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1669 inta = iwl_read32(priv, CSR_INT);
1670 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1671
1672 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1673 * Any new interrupts that happen after this, either while we're
1674 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1675 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1676 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1677
d08853a3 1678#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1679 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1680 /* just for debug */
5d49f498 1681 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1682 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1683 inta, inta_mask, inta_fh);
1684 }
1685#endif
1686
1687 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1688 * atomic, make sure that inta covers all the interrupts that
1689 * we've discovered, even if FH interrupt came in just after
1690 * reading CSR_INT. */
6f83eaa1 1691 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1692 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1693 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1694 inta |= CSR_INT_BIT_FH_TX;
1695
1696 /* Now service all interrupt bits discovered above. */
1697 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1698 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1699
1700 /* Tell the device to stop sending interrupts */
ed3b932e 1701 iwl_disable_interrupts(priv);
b481de9c 1702
86ddbf62 1703 priv->isr_stats.hw++;
8ccde88a 1704 iwl_irq_handle_error(priv);
b481de9c
ZY
1705
1706 handled |= CSR_INT_BIT_HW_ERR;
1707
1708 spin_unlock_irqrestore(&priv->lock, flags);
1709
1710 return;
1711 }
1712
d08853a3 1713#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1714 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1715 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1716 if (inta & CSR_INT_BIT_SCD) {
e1623446 1717 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1718 "the frame/frames.\n");
86ddbf62
AK
1719 priv->isr_stats.sch++;
1720 }
b481de9c
ZY
1721
1722 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1723 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1724 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1725 priv->isr_stats.alive++;
1726 }
b481de9c
ZY
1727 }
1728#endif
1729 /* Safely ignore these bits for debug checks below */
25c03d8e 1730 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1731
b481de9c
ZY
1732 /* Error detected by uCode */
1733 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1734 IWL_ERR(priv, "Microcode SW error detected. "
1735 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1736 priv->isr_stats.sw++;
1737 priv->isr_stats.sw_err = inta;
8ccde88a 1738 iwl_irq_handle_error(priv);
b481de9c
ZY
1739 handled |= CSR_INT_BIT_SW_ERR;
1740 }
1741
1742 /* uCode wakes up after power-down sleep */
1743 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1744 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1745 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1746 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1747 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1748 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1749 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1750 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1751 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1752
86ddbf62 1753 priv->isr_stats.wakeup++;
b481de9c
ZY
1754 handled |= CSR_INT_BIT_WAKEUP;
1755 }
1756
1757 /* All uCode command responses, including Tx command responses,
1758 * Rx "responses" (frame-received notification), and other
1759 * notifications from uCode come through here*/
1760 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1761 iwl3945_rx_handle(priv);
86ddbf62 1762 priv->isr_stats.rx++;
b481de9c
ZY
1763 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1764 }
1765
1766 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1767 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1768 priv->isr_stats.tx++;
b481de9c 1769
5d49f498 1770 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1771 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1772 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1773 handled |= CSR_INT_BIT_FH_TX;
1774 }
1775
86ddbf62 1776 if (inta & ~handled) {
15b1687c 1777 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1778 priv->isr_stats.unhandled++;
1779 }
b481de9c 1780
40cefda9 1781 if (inta & ~priv->inta_mask) {
39aadf8c 1782 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1783 inta & ~priv->inta_mask);
39aadf8c 1784 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1785 }
1786
1787 /* Re-enable all interrupts */
0359facc
MA
1788 /* only Re-enable if disabled by irq */
1789 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1790 iwl_enable_interrupts(priv);
b481de9c 1791
d08853a3 1792#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1793 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1794 inta = iwl_read32(priv, CSR_INT);
1795 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1796 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1797 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1798 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1799 }
1800#endif
1801 spin_unlock_irqrestore(&priv->lock, flags);
1802}
1803
4a8a4322 1804static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1805 enum ieee80211_band band,
f9340520 1806 u8 is_active, u8 n_probes,
bb8c093b 1807 struct iwl3945_scan_channel *scan_ch)
b481de9c 1808{
4e05c234 1809 struct ieee80211_channel *chan;
8318d78a 1810 const struct ieee80211_supported_band *sband;
d20b3c65 1811 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1812 u16 passive_dwell = 0;
1813 u16 active_dwell = 0;
1814 int added, i;
1815
cbba18c6 1816 sband = iwl_get_hw_mode(priv, band);
8318d78a 1817 if (!sband)
b481de9c
ZY
1818 return 0;
1819
77fecfb8
SO
1820 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1821 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1822
8f4807a1
AK
1823 if (passive_dwell <= active_dwell)
1824 passive_dwell = active_dwell + 1;
1825
4e05c234
JB
1826 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1827 chan = priv->scan_request->channels[i];
1828
1829 if (chan->band != band)
182e2e66
JB
1830 continue;
1831
4e05c234 1832 scan_ch->channel = chan->hw_value;
b481de9c 1833
e6148917 1834 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1835 if (!is_channel_valid(ch_info)) {
e1623446 1836 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1837 scan_ch->channel);
1838 continue;
1839 }
1840
011a0330
AK
1841 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1842 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1843 /* If passive , set up for auto-switch
1844 * and use long active_dwell time.
1845 */
b481de9c 1846 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1847 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1848 scan_ch->type = 0; /* passive */
011a0330
AK
1849 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1850 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1851 } else {
b481de9c 1852 scan_ch->type = 1; /* active */
011a0330 1853 }
b481de9c 1854
011a0330
AK
1855 /* Set direct probe bits. These may be used both for active
1856 * scan channels (probes gets sent right away),
1857 * or for passive channels (probes get se sent only after
1858 * hearing clear Rx packet).*/
1859 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1860 if (n_probes)
0d21044e 1861 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1862 } else {
1863 /* uCode v1 does not allow setting direct probe bits on
1864 * passive channel. */
1865 if ((scan_ch->type & 1) && n_probes)
0d21044e 1866 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1867 }
b481de9c 1868
9fbab516 1869 /* Set txpower levels to defaults */
b481de9c
ZY
1870 scan_ch->tpc.dsp_atten = 110;
1871 /* scan_pwr_info->tpc.dsp_atten; */
1872
1873 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1874 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1875 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1876 else {
1877 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1878 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1879 * power level:
8a1b0245 1880 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1881 */
1882 }
1883
e1623446 1884 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1885 scan_ch->channel,
1886 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1887 (scan_ch->type & 1) ?
1888 active_dwell : passive_dwell);
1889
1890 scan_ch++;
1891 added++;
1892 }
1893
e1623446 1894 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1895 return added;
1896}
1897
4a8a4322 1898static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1899 struct ieee80211_rate *rates)
1900{
1901 int i;
1902
1903 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1904 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1905 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1906 rates[i].hw_value_short = i;
1907 rates[i].flags = 0;
d9829a67 1908 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1909 /*
8318d78a 1910 * If CCK != 1M then set short preamble rate flag.
b481de9c 1911 */
bb8c093b 1912 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1913 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1914 }
b481de9c
ZY
1915 }
1916}
1917
b481de9c
ZY
1918/******************************************************************************
1919 *
1920 * uCode download functions
1921 *
1922 ******************************************************************************/
1923
4a8a4322 1924static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1925{
98c92211
TW
1926 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1927 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1928 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1929 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1930 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1931 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1932}
1933
1934/**
bb8c093b 1935 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1936 * looking at all data.
1937 */
4a8a4322 1938static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1939{
1940 u32 val;
1941 u32 save_len = len;
1942 int rc = 0;
1943 u32 errcnt;
1944
e1623446 1945 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1946
5d49f498 1947 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1948 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1949
1950 errcnt = 0;
1951 for (; len > 0; len -= sizeof(u32), image++) {
1952 /* read data comes through single port, auto-incr addr */
1953 /* NOTE: Use the debugless read so we don't flood kernel log
1954 * if IWL_DL_IO is set */
5d49f498 1955 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1956 if (val != le32_to_cpu(*image)) {
15b1687c 1957 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1958 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1959 save_len - len, val, le32_to_cpu(*image));
1960 rc = -EIO;
1961 errcnt++;
1962 if (errcnt >= 20)
1963 break;
1964 }
1965 }
1966
b481de9c
ZY
1967
1968 if (!errcnt)
e1623446
TW
1969 IWL_DEBUG_INFO(priv,
1970 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
1971
1972 return rc;
1973}
1974
1975
1976/**
bb8c093b 1977 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
1978 * using sample data 100 bytes apart. If these sample points are good,
1979 * it's a pretty good bet that everything between them is good, too.
1980 */
4a8a4322 1981static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1982{
1983 u32 val;
1984 int rc = 0;
1985 u32 errcnt = 0;
1986 u32 i;
1987
e1623446 1988 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1989
b481de9c
ZY
1990 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1991 /* read data comes through single port, auto-incr addr */
1992 /* NOTE: Use the debugless read so we don't flood kernel log
1993 * if IWL_DL_IO is set */
5d49f498 1994 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1995 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 1996 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
1997 if (val != le32_to_cpu(*image)) {
1998#if 0 /* Enable this if you want to see details */
15b1687c 1999 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2000 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2001 i, val, *image);
2002#endif
2003 rc = -EIO;
2004 errcnt++;
2005 if (errcnt >= 3)
2006 break;
2007 }
2008 }
2009
b481de9c
ZY
2010 return rc;
2011}
2012
2013
2014/**
bb8c093b 2015 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2016 * and verify its contents
2017 */
4a8a4322 2018static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2019{
2020 __le32 *image;
2021 u32 len;
2022 int rc = 0;
2023
2024 /* Try bootstrap */
2025 image = (__le32 *)priv->ucode_boot.v_addr;
2026 len = priv->ucode_boot.len;
bb8c093b 2027 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2028 if (rc == 0) {
e1623446 2029 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2030 return 0;
2031 }
2032
2033 /* Try initialize */
2034 image = (__le32 *)priv->ucode_init.v_addr;
2035 len = priv->ucode_init.len;
bb8c093b 2036 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2037 if (rc == 0) {
e1623446 2038 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2039 return 0;
2040 }
2041
2042 /* Try runtime/protocol */
2043 image = (__le32 *)priv->ucode_code.v_addr;
2044 len = priv->ucode_code.len;
bb8c093b 2045 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2046 if (rc == 0) {
e1623446 2047 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2048 return 0;
2049 }
2050
15b1687c 2051 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2052
9fbab516
BC
2053 /* Since nothing seems to match, show first several data entries in
2054 * instruction SRAM, so maybe visual inspection will give a clue.
2055 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2056 image = (__le32 *)priv->ucode_boot.v_addr;
2057 len = priv->ucode_boot.len;
bb8c093b 2058 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2059
2060 return rc;
2061}
2062
4a8a4322 2063static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2064{
2065 /* Remove all resets to allow NIC to operate */
5d49f498 2066 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2067}
2068
2069/**
bb8c093b 2070 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2071 *
2072 * Copy into buffers for card to fetch via bus-mastering
2073 */
4a8a4322 2074static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2075{
cc0f555d 2076 const struct iwl_ucode_header *ucode;
a0987a8d 2077 int ret = -EINVAL, index;
b481de9c
ZY
2078 const struct firmware *ucode_raw;
2079 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2080 const char *name_pre = priv->cfg->fw_name_pre;
2081 const unsigned int api_max = priv->cfg->ucode_api_max;
2082 const unsigned int api_min = priv->cfg->ucode_api_min;
2083 char buf[25];
b481de9c
ZY
2084 u8 *src;
2085 size_t len;
a0987a8d 2086 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2087
2088 /* Ask kernel firmware_class module to get the boot firmware off disk.
2089 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2090 for (index = api_max; index >= api_min; index--) {
2091 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2092 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2093 if (ret < 0) {
15b1687c 2094 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2095 buf, ret);
2096 if (ret == -ENOENT)
2097 continue;
2098 else
2099 goto error;
2100 } else {
2101 if (index < api_max)
15b1687c
WT
2102 IWL_ERR(priv, "Loaded firmware %s, "
2103 "which is deprecated. "
2104 " Please use API v%u instead.\n",
a0987a8d 2105 buf, api_max);
e1623446
TW
2106 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2107 "(%zd bytes) from disk\n",
a0987a8d
RC
2108 buf, ucode_raw->size);
2109 break;
2110 }
b481de9c
ZY
2111 }
2112
a0987a8d
RC
2113 if (ret < 0)
2114 goto error;
b481de9c
ZY
2115
2116 /* Make sure that we got at least our header! */
cc0f555d 2117 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2118 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2119 ret = -EINVAL;
b481de9c
ZY
2120 goto err_release;
2121 }
2122
2123 /* Data from ucode file: header followed by uCode images */
cc0f555d 2124 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2125
c02b3acd 2126 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2127 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2128 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2129 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2130 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2131 init_data_size =
2132 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2133 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2134 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2135
a0987a8d
RC
2136 /* api_ver should match the api version forming part of the
2137 * firmware filename ... but we don't check for that and only rely
877d0310 2138 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2139
2140 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2141 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2142 "Driver supports v%u, firmware is v%u.\n",
2143 api_max, api_ver);
2144 priv->ucode_ver = 0;
2145 ret = -EINVAL;
2146 goto err_release;
2147 }
2148 if (api_ver != api_max)
15b1687c 2149 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2150 "got %u. New firmware can be obtained "
2151 "from http://www.intellinuxwireless.org.\n",
2152 api_max, api_ver);
2153
978785a3
TW
2154 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2155 IWL_UCODE_MAJOR(priv->ucode_ver),
2156 IWL_UCODE_MINOR(priv->ucode_ver),
2157 IWL_UCODE_API(priv->ucode_ver),
2158 IWL_UCODE_SERIAL(priv->ucode_ver));
2159
e1623446 2160 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2161 priv->ucode_ver);
e1623446
TW
2162 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2163 inst_size);
2164 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2165 data_size);
2166 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2167 init_size);
2168 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2169 init_data_size);
2170 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2171 boot_size);
b481de9c 2172
a0987a8d 2173
b481de9c 2174 /* Verify size of file vs. image size info in file's header */
cc0f555d 2175 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2176 inst_size + data_size + init_size +
2177 init_data_size + boot_size) {
2178
cc0f555d
JS
2179 IWL_DEBUG_INFO(priv,
2180 "uCode file size %zd does not match expected size\n",
2181 ucode_raw->size);
90e759d1 2182 ret = -EINVAL;
b481de9c
ZY
2183 goto err_release;
2184 }
2185
2186 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2187 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2188 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2189 inst_size);
2190 ret = -EINVAL;
b481de9c
ZY
2191 goto err_release;
2192 }
2193
250bdd21 2194 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2195 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2196 data_size);
2197 ret = -EINVAL;
b481de9c
ZY
2198 goto err_release;
2199 }
250bdd21 2200 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2201 IWL_DEBUG_INFO(priv,
2202 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2203 init_size);
2204 ret = -EINVAL;
b481de9c
ZY
2205 goto err_release;
2206 }
250bdd21 2207 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2208 IWL_DEBUG_INFO(priv,
2209 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2210 init_data_size);
2211 ret = -EINVAL;
b481de9c
ZY
2212 goto err_release;
2213 }
250bdd21 2214 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2215 IWL_DEBUG_INFO(priv,
2216 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2217 boot_size);
2218 ret = -EINVAL;
b481de9c
ZY
2219 goto err_release;
2220 }
2221
2222 /* Allocate ucode buffers for card's bus-master loading ... */
2223
2224 /* Runtime instructions and 2 copies of data:
2225 * 1) unmodified from disk
2226 * 2) backup cache for save/restore during power-downs */
2227 priv->ucode_code.len = inst_size;
98c92211 2228 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2229
2230 priv->ucode_data.len = data_size;
98c92211 2231 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2232
2233 priv->ucode_data_backup.len = data_size;
98c92211 2234 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2235
90e759d1
TW
2236 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2237 !priv->ucode_data_backup.v_addr)
2238 goto err_pci_alloc;
b481de9c
ZY
2239
2240 /* Initialization instructions and data */
90e759d1
TW
2241 if (init_size && init_data_size) {
2242 priv->ucode_init.len = init_size;
98c92211 2243 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2244
2245 priv->ucode_init_data.len = init_data_size;
98c92211 2246 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2247
2248 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2249 goto err_pci_alloc;
2250 }
b481de9c
ZY
2251
2252 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2253 if (boot_size) {
2254 priv->ucode_boot.len = boot_size;
98c92211 2255 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2256
90e759d1
TW
2257 if (!priv->ucode_boot.v_addr)
2258 goto err_pci_alloc;
2259 }
b481de9c
ZY
2260
2261 /* Copy images into buffers for card's bus-master reads ... */
2262
2263 /* Runtime instructions (first block of data in file) */
cc0f555d 2264 len = inst_size;
e1623446
TW
2265 IWL_DEBUG_INFO(priv,
2266 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2267 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2268 src += len;
2269
e1623446 2270 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2271 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2272
2273 /* Runtime data (2nd block)
bb8c093b 2274 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2275 len = data_size;
e1623446
TW
2276 IWL_DEBUG_INFO(priv,
2277 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2278 memcpy(priv->ucode_data.v_addr, src, len);
2279 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2280 src += len;
b481de9c
ZY
2281
2282 /* Initialization instructions (3rd block) */
2283 if (init_size) {
cc0f555d 2284 len = init_size;
e1623446
TW
2285 IWL_DEBUG_INFO(priv,
2286 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2287 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2288 src += len;
b481de9c
ZY
2289 }
2290
2291 /* Initialization data (4th block) */
2292 if (init_data_size) {
cc0f555d 2293 len = init_data_size;
e1623446
TW
2294 IWL_DEBUG_INFO(priv,
2295 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2296 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2297 src += len;
b481de9c
ZY
2298 }
2299
2300 /* Bootstrap instructions (5th block) */
cc0f555d 2301 len = boot_size;
e1623446
TW
2302 IWL_DEBUG_INFO(priv,
2303 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2304 memcpy(priv->ucode_boot.v_addr, src, len);
2305
2306 /* We have our copies now, allow OS release its copies */
2307 release_firmware(ucode_raw);
2308 return 0;
2309
2310 err_pci_alloc:
15b1687c 2311 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2312 ret = -ENOMEM;
bb8c093b 2313 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2314
2315 err_release:
2316 release_firmware(ucode_raw);
2317
2318 error:
90e759d1 2319 return ret;
b481de9c
ZY
2320}
2321
2322
2323/**
bb8c093b 2324 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2325 *
2326 * Tell initialization uCode where to find runtime uCode.
2327 *
2328 * BSM registers initially contain pointers to initialization uCode.
2329 * We need to replace them to load runtime uCode inst and data,
2330 * and to save runtime data when powering down.
2331 */
4a8a4322 2332static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2333{
2334 dma_addr_t pinst;
2335 dma_addr_t pdata;
b481de9c
ZY
2336
2337 /* bits 31:0 for 3945 */
2338 pinst = priv->ucode_code.p_addr;
2339 pdata = priv->ucode_data_backup.p_addr;
2340
b481de9c 2341 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2342 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2343 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2344 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2345 priv->ucode_data.len);
2346
a96a27f9 2347 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2348 * that all new ptr/size info is in place */
5d49f498 2349 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2350 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2351
e1623446 2352 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2353
a8b50a0a 2354 return 0;
b481de9c
ZY
2355}
2356
2357/**
bb8c093b 2358 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2359 *
2360 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2361 *
b481de9c 2362 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2363 */
4a8a4322 2364static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2365{
2366 /* Check alive response for "valid" sign from uCode */
2367 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2368 /* We had an error bringing up the hardware, so take it
2369 * all the way back down so we can try again */
e1623446 2370 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2371 goto restart;
2372 }
2373
2374 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2375 * This is a paranoid check, because we would not have gotten the
2376 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2377 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2378 /* Runtime instruction load was bad;
2379 * take it all the way back down so we can try again */
e1623446 2380 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2381 goto restart;
2382 }
2383
2384 /* Send pointers to protocol/runtime uCode image ... init code will
2385 * load and launch runtime uCode, which will send us another "Alive"
2386 * notification. */
e1623446 2387 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2388 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2389 /* Runtime instruction load won't happen;
2390 * take it all the way back down so we can try again */
e1623446 2391 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2392 goto restart;
2393 }
2394 return;
2395
2396 restart:
2397 queue_work(priv->workqueue, &priv->restart);
2398}
2399
b481de9c 2400/**
bb8c093b 2401 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2402 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2403 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2404 */
4a8a4322 2405static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2406{
b481de9c
ZY
2407 int thermal_spin = 0;
2408 u32 rfkill;
2409
e1623446 2410 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2411
2412 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2413 /* We had an error bringing up the hardware, so take it
2414 * all the way back down so we can try again */
e1623446 2415 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2416 goto restart;
2417 }
2418
2419 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2420 * This is a paranoid check, because we would not have gotten the
2421 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2422 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2423 /* Runtime instruction load was bad;
2424 * take it all the way back down so we can try again */
e1623446 2425 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2426 goto restart;
2427 }
2428
c587de0b 2429 iwl_clear_stations_table(priv);
b481de9c 2430
5d49f498 2431 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2432 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2433
2434 if (rfkill & 0x1) {
2435 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2436 /* if RFKILL is not on, then wait for thermal
b481de9c 2437 * sensor in adapter to kick in */
bb8c093b 2438 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2439 thermal_spin++;
2440 udelay(10);
2441 }
2442
2443 if (thermal_spin)
e1623446 2444 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2445 thermal_spin * 10);
2446 } else
2447 set_bit(STATUS_RF_KILL_HW, &priv->status);
2448
9fbab516 2449 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2450 set_bit(STATUS_ALIVE, &priv->status);
2451
775a6e27 2452 if (iwl_is_rfkill(priv))
b481de9c
ZY
2453 return;
2454
36d6825b 2455 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2456
2457 priv->active_rate = priv->rates_mask;
2458 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2459
d25aabb0 2460 iwl_power_update_mode(priv, false);
b481de9c 2461
8ccde88a 2462 if (iwl_is_associated(priv)) {
bb8c093b 2463 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2464 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2465
8a9b9926 2466 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2467 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2468 } else {
2469 /* Initialize our rx_config data */
8ccde88a 2470 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2471 }
2472
9fbab516 2473 /* Configure Bluetooth device coexistence support */
17f841cd 2474 iwl_send_bt_config(priv);
b481de9c
ZY
2475
2476 /* Configure the adapter for unassociated operation */
e0158e61 2477 iwlcore_commit_rxon(priv);
b481de9c 2478
b481de9c
ZY
2479 iwl3945_reg_txpower_periodic(priv);
2480
fe00b5a5
RC
2481 iwl3945_led_register(priv);
2482
e1623446 2483 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2484 set_bit(STATUS_READY, &priv->status);
5a66926a 2485 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2486
9bdf5eca
MA
2487 /* reassociate for ADHOC mode */
2488 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2489 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2490 priv->vif);
2491 if (beacon)
9944b938 2492 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2493 }
2494
f45c2714 2495 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2496 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2497
b481de9c
ZY
2498 return;
2499
2500 restart:
2501 queue_work(priv->workqueue, &priv->restart);
2502}
2503
4a8a4322 2504static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2505
4a8a4322 2506static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2507{
2508 unsigned long flags;
2509 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2510 struct ieee80211_conf *conf = NULL;
2511
e1623446 2512 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2513
2514 conf = ieee80211_get_hw_conf(priv->hw);
2515
2516 if (!exit_pending)
2517 set_bit(STATUS_EXIT_PENDING, &priv->status);
2518
ab53d8af 2519 iwl3945_led_unregister(priv);
c587de0b 2520 iwl_clear_stations_table(priv);
b481de9c
ZY
2521
2522 /* Unblock any waiting calls */
2523 wake_up_interruptible_all(&priv->wait_command_queue);
2524
b481de9c
ZY
2525 /* Wipe out the EXIT_PENDING status bit if we are not actually
2526 * exiting the module */
2527 if (!exit_pending)
2528 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2529
2530 /* stop and reset the on-board processor */
5d49f498 2531 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2532
2533 /* tell the device to stop sending interrupts */
0359facc 2534 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2535 iwl_disable_interrupts(priv);
0359facc
MA
2536 spin_unlock_irqrestore(&priv->lock, flags);
2537 iwl_synchronize_irq(priv);
b481de9c
ZY
2538
2539 if (priv->mac80211_registered)
2540 ieee80211_stop_queues(priv->hw);
2541
bb8c093b 2542 /* If we have not previously called iwl3945_init() then
6da3a13e 2543 * clear all bits but the RF Kill bits and return */
775a6e27 2544 if (!iwl_is_init(priv)) {
b481de9c
ZY
2545 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2546 STATUS_RF_KILL_HW |
9788864e
RC
2547 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2548 STATUS_GEO_CONFIGURED |
ebef2008
AK
2549 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2550 STATUS_EXIT_PENDING;
b481de9c
ZY
2551 goto exit;
2552 }
2553
6da3a13e 2554 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2555 * bit and continue taking the NIC down. */
b481de9c
ZY
2556 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2557 STATUS_RF_KILL_HW |
9788864e
RC
2558 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2559 STATUS_GEO_CONFIGURED |
b481de9c 2560 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2561 STATUS_FW_ERROR |
2562 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2563 STATUS_EXIT_PENDING;
b481de9c 2564
e9414b6b 2565 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 2566 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2567 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
2568 spin_unlock_irqrestore(&priv->lock, flags);
2569
bb8c093b
CH
2570 iwl3945_hw_txq_ctx_stop(priv);
2571 iwl3945_hw_rxq_stop(priv);
b481de9c 2572
a8b50a0a
MA
2573 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2574 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2575
2576 udelay(5);
2577
6da3a13e 2578 if (exit_pending)
e9414b6b
AM
2579 priv->cfg->ops->lib->apm_ops.stop(priv);
2580 else
2581 priv->cfg->ops->lib->apm_ops.reset(priv);
2582
b481de9c 2583 exit:
3d24a9f7 2584 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2585
2586 if (priv->ibss_beacon)
2587 dev_kfree_skb(priv->ibss_beacon);
2588 priv->ibss_beacon = NULL;
2589
2590 /* clear out any free frames */
bb8c093b 2591 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2592}
2593
4a8a4322 2594static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2595{
2596 mutex_lock(&priv->mutex);
bb8c093b 2597 __iwl3945_down(priv);
b481de9c 2598 mutex_unlock(&priv->mutex);
b24d22b1 2599
bb8c093b 2600 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2601}
2602
2603#define MAX_HW_RESTARTS 5
2604
4a8a4322 2605static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2606{
2607 int rc, i;
2608
2609 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2610 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2611 return -EIO;
2612 }
2613
e903fbd4 2614 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2615 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2616 return -EIO;
2617 }
2618
e655b9f0 2619 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2620 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2621 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2622 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2623 else {
2624 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2625 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2626 return -ENODEV;
b481de9c 2627 }
80fcc9e2 2628
5d49f498 2629 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2630
bb8c093b 2631 rc = iwl3945_hw_nic_init(priv);
b481de9c 2632 if (rc) {
15b1687c 2633 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2634 return rc;
2635 }
2636
2637 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2638 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2639 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2640 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2641
2642 /* clear (again), then enable host interrupts */
5d49f498 2643 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2644 iwl_enable_interrupts(priv);
b481de9c
ZY
2645
2646 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2647 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2648 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2649
2650 /* Copy original ucode data image from disk into backup cache.
2651 * This will be used to initialize the on-board processor's
2652 * data SRAM for a clean start when the runtime program first loads. */
2653 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2654 priv->ucode_data.len);
b481de9c 2655
e655b9f0
ZY
2656 /* We return success when we resume from suspend and rf_kill is on. */
2657 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2658 return 0;
2659
b481de9c
ZY
2660 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2661
c587de0b 2662 iwl_clear_stations_table(priv);
b481de9c
ZY
2663
2664 /* load bootstrap state machine,
2665 * load bootstrap program into processor's memory,
2666 * prepare to load the "initialize" uCode */
0164b9b4 2667 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2668
2669 if (rc) {
15b1687c
WT
2670 IWL_ERR(priv,
2671 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2672 continue;
2673 }
2674
2675 /* start card; "initialize" will load runtime ucode */
bb8c093b 2676 iwl3945_nic_start(priv);
b481de9c 2677
e1623446 2678 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2679
2680 return 0;
2681 }
2682
2683 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2684 __iwl3945_down(priv);
ebef2008 2685 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2686
2687 /* tried to restart and config the device for as long as our
2688 * patience could withstand */
15b1687c 2689 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2690 return -EIO;
2691}
2692
2693
2694/*****************************************************************************
2695 *
2696 * Workqueue callbacks
2697 *
2698 *****************************************************************************/
2699
bb8c093b 2700static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2701{
4a8a4322
AK
2702 struct iwl_priv *priv =
2703 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2704
2705 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2706 return;
2707
2708 mutex_lock(&priv->mutex);
bb8c093b 2709 iwl3945_init_alive_start(priv);
b481de9c
ZY
2710 mutex_unlock(&priv->mutex);
2711}
2712
bb8c093b 2713static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2714{
4a8a4322
AK
2715 struct iwl_priv *priv =
2716 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2717
2718 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2719 return;
2720
2721 mutex_lock(&priv->mutex);
bb8c093b 2722 iwl3945_alive_start(priv);
b481de9c
ZY
2723 mutex_unlock(&priv->mutex);
2724}
2725
2663516d
HS
2726static void iwl3945_rfkill_poll(struct work_struct *data)
2727{
2728 struct iwl_priv *priv =
2729 container_of(data, struct iwl_priv, rfkill_poll.work);
2663516d
HS
2730
2731 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2732 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2733 else
2734 set_bit(STATUS_RF_KILL_HW, &priv->status);
2735
a60e77e5
JB
2736 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
2737 test_bit(STATUS_RF_KILL_HW, &priv->status));
2663516d
HS
2738
2739 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2740 round_jiffies_relative(2 * HZ));
2741
2742}
2743
b481de9c 2744#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2745static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2746{
4a8a4322
AK
2747 struct iwl_priv *priv =
2748 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2749 struct iwl_host_cmd cmd = {
b481de9c 2750 .id = REPLY_SCAN_CMD,
bb8c093b 2751 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2752 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2753 };
2754 int rc = 0;
bb8c093b 2755 struct iwl3945_scan_cmd *scan;
b481de9c 2756 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2757 u8 n_probes = 0;
8318d78a 2758 enum ieee80211_band band;
1ecf9fc1 2759 bool is_active = false;
b481de9c
ZY
2760
2761 conf = ieee80211_get_hw_conf(priv->hw);
2762
2763 mutex_lock(&priv->mutex);
2764
fbc9f97b
RC
2765 cancel_delayed_work(&priv->scan_check);
2766
775a6e27 2767 if (!iwl_is_ready(priv)) {
39aadf8c 2768 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2769 goto done;
2770 }
2771
a96a27f9 2772 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2773 * was given the chance to run... */
2774 if (!test_bit(STATUS_SCANNING, &priv->status))
2775 goto done;
2776
2777 /* This should never be called or scheduled if there is currently
2778 * a scan active in the hardware. */
2779 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2780 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2781 "Ignoring second request.\n");
b481de9c
ZY
2782 rc = -EIO;
2783 goto done;
2784 }
2785
2786 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2787 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2788 goto done;
2789 }
2790
2791 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2792 IWL_DEBUG_HC(priv,
2793 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2794 goto done;
2795 }
2796
775a6e27 2797 if (iwl_is_rfkill(priv)) {
e1623446 2798 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2799 goto done;
2800 }
2801
2802 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2803 IWL_DEBUG_HC(priv,
2804 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2805 goto done;
2806 }
2807
2808 if (!priv->scan_bands) {
e1623446 2809 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2810 goto done;
2811 }
2812
805cee5b
WT
2813 if (!priv->scan) {
2814 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2815 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2816 if (!priv->scan) {
b481de9c
ZY
2817 rc = -ENOMEM;
2818 goto done;
2819 }
2820 }
805cee5b 2821 scan = priv->scan;
bb8c093b 2822 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2823
2824 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2825 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2826
8ccde88a 2827 if (iwl_is_associated(priv)) {
b481de9c
ZY
2828 u16 interval = 0;
2829 u32 extra;
2830 u32 suspend_time = 100;
2831 u32 scan_suspend_time = 100;
2832 unsigned long flags;
2833
e1623446 2834 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2835
2836 spin_lock_irqsave(&priv->lock, flags);
2837 interval = priv->beacon_int;
2838 spin_unlock_irqrestore(&priv->lock, flags);
2839
2840 scan->suspend_time = 0;
15e869d8 2841 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2842 if (!interval)
2843 interval = suspend_time;
2844 /*
2845 * suspend time format:
2846 * 0-19: beacon interval in usec (time before exec.)
2847 * 20-23: 0
2848 * 24-31: number of beacons (suspend between channels)
2849 */
2850
2851 extra = (suspend_time / interval) << 24;
2852 scan_suspend_time = 0xFF0FFFFF &
2853 (extra | ((suspend_time % interval) * 1024));
2854
2855 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2856 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2857 scan_suspend_time, interval);
2858 }
2859
1ecf9fc1
JB
2860 if (priv->scan_request->n_ssids) {
2861 int i, p = 0;
2862 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2863 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2864 /* always does wildcard anyway */
2865 if (!priv->scan_request->ssids[i].ssid_len)
2866 continue;
2867 scan->direct_scan[p].id = WLAN_EID_SSID;
2868 scan->direct_scan[p].len =
2869 priv->scan_request->ssids[i].ssid_len;
2870 memcpy(scan->direct_scan[p].ssid,
2871 priv->scan_request->ssids[i].ssid,
2872 priv->scan_request->ssids[i].ssid_len);
2873 n_probes++;
2874 p++;
2875 }
2876 is_active = true;
f9340520 2877 } else
1ecf9fc1 2878 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2879
2880 /* We don't build a direct scan probe request; the uCode will do
2881 * that based on the direct_mask added to each channel entry */
b481de9c 2882 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2883 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2884 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2885
2886 /* flags + rate selection */
2887
66b5004d 2888 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2889 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2890 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2891 scan->good_CRC_th = 0;
8318d78a 2892 band = IEEE80211_BAND_2GHZ;
66b5004d 2893 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2894 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2895 /*
2896 * If active scaning is requested but a certain channel
2897 * is marked passive, we can do active scanning if we
2898 * detect transmissions.
2899 */
2900 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2901 band = IEEE80211_BAND_5GHZ;
66b5004d 2902 } else {
39aadf8c 2903 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2904 goto done;
2905 }
2906
77fecfb8 2907 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2908 iwl_fill_probe_req(priv,
2909 (struct ieee80211_mgmt *)scan->data,
2910 priv->scan_request->ie,
2911 priv->scan_request->ie_len,
2912 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2913
b481de9c
ZY
2914 /* select Rx antennas */
2915 scan->flags |= iwl3945_get_antenna_flags(priv);
2916
279b05d4 2917 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2918 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2919
f9340520 2920 scan->channel_count =
1ecf9fc1 2921 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2922 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2923
14b54336 2924 if (scan->channel_count == 0) {
e1623446 2925 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2926 goto done;
2927 }
2928
b481de9c 2929 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2930 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2931 cmd.data = scan;
2932 scan->len = cpu_to_le16(cmd.len);
2933
2934 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 2935 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2936 if (rc)
2937 goto done;
2938
2939 queue_delayed_work(priv->workqueue, &priv->scan_check,
2940 IWL_SCAN_CHECK_WATCHDOG);
2941
2942 mutex_unlock(&priv->mutex);
2943 return;
2944
2945 done:
2420ebc1
MA
2946 /* can not perform scan make sure we clear scanning
2947 * bits from status so next scan request can be performed.
2948 * if we dont clear scanning status bit here all next scan
2949 * will fail
2950 */
2951 clear_bit(STATUS_SCAN_HW, &priv->status);
2952 clear_bit(STATUS_SCANNING, &priv->status);
2953
01ebd063 2954 /* inform mac80211 scan aborted */
b481de9c
ZY
2955 queue_work(priv->workqueue, &priv->scan_completed);
2956 mutex_unlock(&priv->mutex);
2957}
2958
bb8c093b 2959static void iwl3945_bg_up(struct work_struct *data)
b481de9c 2960{
4a8a4322 2961 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2962
2963 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2964 return;
2965
2966 mutex_lock(&priv->mutex);
bb8c093b 2967 __iwl3945_up(priv);
b481de9c
ZY
2968 mutex_unlock(&priv->mutex);
2969}
2970
bb8c093b 2971static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 2972{
4a8a4322 2973 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2974
2975 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2976 return;
2977
19cc1087
JB
2978 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2979 mutex_lock(&priv->mutex);
2980 priv->vif = NULL;
2981 priv->is_open = 0;
2982 mutex_unlock(&priv->mutex);
2983 iwl3945_down(priv);
2984 ieee80211_restart_hw(priv->hw);
2985 } else {
2986 iwl3945_down(priv);
2987 queue_work(priv->workqueue, &priv->up);
2988 }
b481de9c
ZY
2989}
2990
bb8c093b 2991static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 2992{
4a8a4322
AK
2993 struct iwl_priv *priv =
2994 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2995
2996 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2997 return;
2998
2999 mutex_lock(&priv->mutex);
bb8c093b 3000 iwl3945_rx_replenish(priv);
b481de9c
ZY
3001 mutex_unlock(&priv->mutex);
3002}
3003
7878a5a4
MA
3004#define IWL_DELAY_NEXT_SCAN (HZ*2)
3005
5bbe233b 3006void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3007{
b481de9c
ZY
3008 int rc = 0;
3009 struct ieee80211_conf *conf = NULL;
3010
05c914fe 3011 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3012 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3013 return;
3014 }
3015
3016
e1623446 3017 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3018 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3019
3020 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3021 return;
3022
322a9811 3023 if (!priv->vif || !priv->is_open)
6ef89d0a 3024 return;
322a9811 3025
af0053d6 3026 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3027
b481de9c
ZY
3028 conf = ieee80211_get_hw_conf(priv->hw);
3029
8ccde88a 3030 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3031 iwlcore_commit_rxon(priv);
b481de9c 3032
28afaf91 3033 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3034 iwl_setup_rxon_timing(priv);
518099a8 3035 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3036 sizeof(priv->rxon_timing), &priv->rxon_timing);
3037 if (rc)
39aadf8c 3038 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3039 "Attempting to continue.\n");
3040
8ccde88a 3041 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3042
8ccde88a 3043 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3044
e1623446 3045 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3046 priv->assoc_id, priv->beacon_int);
3047
3048 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3049 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3050 else
8ccde88a 3051 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3052
8ccde88a 3053 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3054 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3055 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3056 else
8ccde88a 3057 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3058
05c914fe 3059 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3060 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3061
3062 }
3063
e0158e61 3064 iwlcore_commit_rxon(priv);
b481de9c
ZY
3065
3066 switch (priv->iw_mode) {
05c914fe 3067 case NL80211_IFTYPE_STATION:
bb8c093b 3068 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3069 break;
3070
05c914fe 3071 case NL80211_IFTYPE_ADHOC:
b481de9c 3072
ce546fd2 3073 priv->assoc_id = 1;
c587de0b 3074 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3075 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3076 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3077 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3078 CMD_ASYNC);
bb8c093b
CH
3079 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3080 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3081
3082 break;
3083
3084 default:
15b1687c 3085 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3086 __func__, priv->iw_mode);
b481de9c
ZY
3087 break;
3088 }
3089
14d2aac5 3090 iwl_activate_qos(priv, 0);
292ae174 3091
7878a5a4
MA
3092 /* we have just associated, don't start scan too early */
3093 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3094}
3095
b481de9c
ZY
3096/*****************************************************************************
3097 *
3098 * mac80211 entry point functions
3099 *
3100 *****************************************************************************/
3101
5a66926a
ZY
3102#define UCODE_READY_TIMEOUT (2 * HZ)
3103
bb8c093b 3104static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3105{
4a8a4322 3106 struct iwl_priv *priv = hw->priv;
5a66926a 3107 int ret;
b481de9c 3108
e1623446 3109 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3110
3111 /* we should be verifying the device is ready to be opened */
3112 mutex_lock(&priv->mutex);
3113
5a66926a
ZY
3114 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3115 * ucode filename and max sizes are card-specific. */
3116
3117 if (!priv->ucode_code.len) {
3118 ret = iwl3945_read_ucode(priv);
3119 if (ret) {
15b1687c 3120 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3121 mutex_unlock(&priv->mutex);
3122 goto out_release_irq;
3123 }
3124 }
b481de9c 3125
e655b9f0 3126 ret = __iwl3945_up(priv);
b481de9c
ZY
3127
3128 mutex_unlock(&priv->mutex);
5a66926a 3129
e655b9f0
ZY
3130 if (ret)
3131 goto out_release_irq;
3132
e1623446 3133 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3134
5a66926a
ZY
3135 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3136 * mac80211 will not be run successfully. */
3137 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3138 test_bit(STATUS_READY, &priv->status),
3139 UCODE_READY_TIMEOUT);
3140 if (!ret) {
3141 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3142 IWL_ERR(priv,
3143 "Wait for START_ALIVE timeout after %dms.\n",
3144 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3145 ret = -ETIMEDOUT;
3146 goto out_release_irq;
3147 }
3148 }
3149
2663516d
HS
3150 /* ucode is running and will send rfkill notifications,
3151 * no need to poll the killswitch state anymore */
3152 cancel_delayed_work(&priv->rfkill_poll);
3153
e655b9f0 3154 priv->is_open = 1;
e1623446 3155 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3156 return 0;
5a66926a
ZY
3157
3158out_release_irq:
e655b9f0 3159 priv->is_open = 0;
e1623446 3160 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3161 return ret;
b481de9c
ZY
3162}
3163
bb8c093b 3164static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3165{
4a8a4322 3166 struct iwl_priv *priv = hw->priv;
b481de9c 3167
e1623446 3168 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3169
e655b9f0 3170 if (!priv->is_open) {
e1623446 3171 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3172 return;
3173 }
3174
b481de9c 3175 priv->is_open = 0;
5a66926a 3176
775a6e27 3177 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3178 /* stop mac, cancel any scan request and clear
3179 * RXON_FILTER_ASSOC_MSK BIT
3180 */
5a66926a 3181 mutex_lock(&priv->mutex);
af0053d6 3182 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3183 mutex_unlock(&priv->mutex);
fde3571f
MA
3184 }
3185
5a66926a
ZY
3186 iwl3945_down(priv);
3187
3188 flush_workqueue(priv->workqueue);
2663516d
HS
3189
3190 /* start polling the killswitch state again */
3191 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3192 round_jiffies_relative(2 * HZ));
6ef89d0a 3193
e1623446 3194 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3195}
3196
e039fa4a 3197static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3198{
4a8a4322 3199 struct iwl_priv *priv = hw->priv;
b481de9c 3200
e1623446 3201 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3202
e1623446 3203 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3204 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3205
e039fa4a 3206 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3207 dev_kfree_skb_any(skb);
3208
e1623446 3209 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3210 return NETDEV_TX_OK;
b481de9c
ZY
3211}
3212
60690a6a 3213void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3214{
3215 int rc = 0;
3216
d986bcd1 3217 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3218 return;
3219
3220 /* The following should be done only at AP bring up */
8ccde88a 3221 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3222
3223 /* RXON - unassoc (to set timing command) */
8ccde88a 3224 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3225 iwlcore_commit_rxon(priv);
b481de9c
ZY
3226
3227 /* RXON Timing */
28afaf91 3228 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3229 iwl_setup_rxon_timing(priv);
518099a8
SO
3230 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3231 sizeof(priv->rxon_timing),
3232 &priv->rxon_timing);
b481de9c 3233 if (rc)
39aadf8c 3234 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3235 "Attempting to continue.\n");
3236
3237 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3238 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3239 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3240 priv->staging_rxon.flags |=
b481de9c
ZY
3241 RXON_FLG_SHORT_PREAMBLE_MSK;
3242 else
8ccde88a 3243 priv->staging_rxon.flags &=
b481de9c
ZY
3244 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3245
8ccde88a 3246 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3247 if (priv->assoc_capability &
3248 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3249 priv->staging_rxon.flags |=
b481de9c
ZY
3250 RXON_FLG_SHORT_SLOT_MSK;
3251 else
8ccde88a 3252 priv->staging_rxon.flags &=
b481de9c
ZY
3253 ~RXON_FLG_SHORT_SLOT_MSK;
3254
05c914fe 3255 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3256 priv->staging_rxon.flags &=
b481de9c
ZY
3257 ~RXON_FLG_SHORT_SLOT_MSK;
3258 }
3259 /* restore RXON assoc */
8ccde88a 3260 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3261 iwlcore_commit_rxon(priv);
c587de0b 3262 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3263 }
bb8c093b 3264 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3265
3266 /* FIXME - we need to add code here to detect a totally new
3267 * configuration, reset the AP, unassoc, rxon timing, assoc,
3268 * clear sta table, add BCAST sta... */
3269}
3270
bb8c093b 3271static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3272 struct ieee80211_vif *vif,
3273 struct ieee80211_sta *sta,
3274 struct ieee80211_key_conf *key)
b481de9c 3275{
4a8a4322 3276 struct iwl_priv *priv = hw->priv;
dc822b5d 3277 const u8 *addr;
6e21f15c
AK
3278 int ret = 0;
3279 u8 sta_id = IWL_INVALID_STATION;
3280 u8 static_key;
b481de9c 3281
e1623446 3282 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3283
df878d8f 3284 if (iwl3945_mod_params.sw_crypto) {
e1623446 3285 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3286 return -EOPNOTSUPP;
3287 }
3288
42986796 3289 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3290 static_key = !iwl_is_associated(priv);
3291
3292 if (!static_key) {
c587de0b 3293 sta_id = iwl_find_station(priv, addr);
6e21f15c 3294 if (sta_id == IWL_INVALID_STATION) {
12514396 3295 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3296 addr);
3297 return -EINVAL;
3298 }
b481de9c
ZY
3299 }
3300
3301 mutex_lock(&priv->mutex);
af0053d6 3302 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3303 mutex_unlock(&priv->mutex);
15e869d8 3304
b481de9c 3305 switch (cmd) {
6e21f15c
AK
3306 case SET_KEY:
3307 if (static_key)
3308 ret = iwl3945_set_static_key(priv, key);
3309 else
3310 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3311 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3312 break;
3313 case DISABLE_KEY:
6e21f15c
AK
3314 if (static_key)
3315 ret = iwl3945_remove_static_key(priv);
3316 else
3317 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3318 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3319 break;
3320 default:
42986796 3321 ret = -EINVAL;
b481de9c
ZY
3322 }
3323
e1623446 3324 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3325
42986796 3326 return ret;
b481de9c
ZY
3327}
3328
b481de9c
ZY
3329/*****************************************************************************
3330 *
3331 * sysfs attributes
3332 *
3333 *****************************************************************************/
3334
d08853a3 3335#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3336
3337/*
3338 * The following adds a new attribute to the sysfs representation
3339 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3340 * used for controlling the debug level.
3341 *
3342 * See the level definitions in iwl for details.
a562a9dd 3343 *
3d816c77
RC
3344 * The debug_level being managed using sysfs below is a per device debug
3345 * level that is used instead of the global debug level if it (the per
3346 * device debug level) is set.
b481de9c 3347 */
40b8ec0b
SO
3348static ssize_t show_debug_level(struct device *d,
3349 struct device_attribute *attr, char *buf)
b481de9c 3350{
3d816c77
RC
3351 struct iwl_priv *priv = dev_get_drvdata(d);
3352 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3353}
40b8ec0b
SO
3354static ssize_t store_debug_level(struct device *d,
3355 struct device_attribute *attr,
b481de9c
ZY
3356 const char *buf, size_t count)
3357{
928841b1 3358 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3359 unsigned long val;
3360 int ret;
b481de9c 3361
40b8ec0b
SO
3362 ret = strict_strtoul(buf, 0, &val);
3363 if (ret)
978785a3 3364 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3365 else {
3d816c77 3366 priv->debug_level = val;
20594eb0
WYG
3367 if (iwl_alloc_traffic_mem(priv))
3368 IWL_ERR(priv,
3369 "Not enough memory to generate traffic log\n");
3370 }
b481de9c
ZY
3371 return strnlen(buf, count);
3372}
3373
40b8ec0b
SO
3374static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3375 show_debug_level, store_debug_level);
b481de9c 3376
d08853a3 3377#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3378
b481de9c
ZY
3379static ssize_t show_temperature(struct device *d,
3380 struct device_attribute *attr, char *buf)
3381{
928841b1 3382 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3383
775a6e27 3384 if (!iwl_is_alive(priv))
b481de9c
ZY
3385 return -EAGAIN;
3386
bb8c093b 3387 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3388}
3389
3390static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3391
b481de9c
ZY
3392static ssize_t show_tx_power(struct device *d,
3393 struct device_attribute *attr, char *buf)
3394{
928841b1 3395 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3396 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3397}
3398
3399static ssize_t store_tx_power(struct device *d,
3400 struct device_attribute *attr,
3401 const char *buf, size_t count)
3402{
928841b1 3403 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3404 char *p = (char *)buf;
3405 u32 val;
3406
3407 val = simple_strtoul(p, &p, 10);
3408 if (p == buf)
978785a3 3409 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3410 else
bb8c093b 3411 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3412
3413 return count;
3414}
3415
3416static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3417
3418static ssize_t show_flags(struct device *d,
3419 struct device_attribute *attr, char *buf)
3420{
928841b1 3421 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3422
8ccde88a 3423 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3424}
3425
3426static ssize_t store_flags(struct device *d,
3427 struct device_attribute *attr,
3428 const char *buf, size_t count)
3429{
928841b1 3430 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3431 u32 flags = simple_strtoul(buf, NULL, 0);
3432
3433 mutex_lock(&priv->mutex);
8ccde88a 3434 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3435 /* Cancel any currently running scans... */
af0053d6 3436 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3437 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3438 else {
e1623446 3439 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3440 flags);
8ccde88a 3441 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3442 iwlcore_commit_rxon(priv);
b481de9c
ZY
3443 }
3444 }
3445 mutex_unlock(&priv->mutex);
3446
3447 return count;
3448}
3449
3450static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3451
3452static ssize_t show_filter_flags(struct device *d,
3453 struct device_attribute *attr, char *buf)
3454{
928841b1 3455 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3456
3457 return sprintf(buf, "0x%04X\n",
8ccde88a 3458 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3459}
3460
3461static ssize_t store_filter_flags(struct device *d,
3462 struct device_attribute *attr,
3463 const char *buf, size_t count)
3464{
928841b1 3465 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3466 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3467
3468 mutex_lock(&priv->mutex);
8ccde88a 3469 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3470 /* Cancel any currently running scans... */
af0053d6 3471 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3472 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3473 else {
e1623446 3474 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3475 "0x%04X\n", filter_flags);
8ccde88a 3476 priv->staging_rxon.filter_flags =
b481de9c 3477 cpu_to_le32(filter_flags);
e0158e61 3478 iwlcore_commit_rxon(priv);
b481de9c
ZY
3479 }
3480 }
3481 mutex_unlock(&priv->mutex);
3482
3483 return count;
3484}
3485
3486static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3487 store_filter_flags);
3488
c8b0e6e1 3489#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3490
3491static ssize_t show_measurement(struct device *d,
3492 struct device_attribute *attr, char *buf)
3493{
4a8a4322 3494 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3495 struct iwl_spectrum_notification measure_report;
b481de9c 3496 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3497 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3498 unsigned long flags;
3499
3500 spin_lock_irqsave(&priv->lock, flags);
3501 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3502 spin_unlock_irqrestore(&priv->lock, flags);
3503 return 0;
3504 }
3505 memcpy(&measure_report, &priv->measure_report, size);
3506 priv->measurement_status = 0;
3507 spin_unlock_irqrestore(&priv->lock, flags);
3508
3509 while (size && (PAGE_SIZE - len)) {
3510 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3511 PAGE_SIZE - len, 1);
3512 len = strlen(buf);
3513 if (PAGE_SIZE - len)
3514 buf[len++] = '\n';
3515
3516 ofs += 16;
3517 size -= min(size, 16U);
3518 }
3519
3520 return len;
3521}
3522
3523static ssize_t store_measurement(struct device *d,
3524 struct device_attribute *attr,
3525 const char *buf, size_t count)
3526{
4a8a4322 3527 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3528 struct ieee80211_measurement_params params = {
8ccde88a 3529 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3530 .start_time = cpu_to_le64(priv->last_tsf),
3531 .duration = cpu_to_le16(1),
3532 };
3533 u8 type = IWL_MEASURE_BASIC;
3534 u8 buffer[32];
3535 u8 channel;
3536
3537 if (count) {
3538 char *p = buffer;
3539 strncpy(buffer, buf, min(sizeof(buffer), count));
3540 channel = simple_strtoul(p, NULL, 0);
3541 if (channel)
3542 params.channel = channel;
3543
3544 p = buffer;
3545 while (*p && *p != ' ')
3546 p++;
3547 if (*p)
3548 type = simple_strtoul(p + 1, NULL, 0);
3549 }
3550
e1623446 3551 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3552 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3553 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3554
3555 return count;
3556}
3557
3558static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3559 show_measurement, store_measurement);
c8b0e6e1 3560#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 3561
b481de9c
ZY
3562static ssize_t store_retry_rate(struct device *d,
3563 struct device_attribute *attr,
3564 const char *buf, size_t count)
3565{
4a8a4322 3566 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3567
3568 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3569 if (priv->retry_rate <= 0)
3570 priv->retry_rate = 1;
3571
3572 return count;
3573}
3574
3575static ssize_t show_retry_rate(struct device *d,
3576 struct device_attribute *attr, char *buf)
3577{
4a8a4322 3578 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3579 return sprintf(buf, "%d", priv->retry_rate);
3580}
3581
3582static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3583 store_retry_rate);
3584
d25aabb0 3585
b481de9c
ZY
3586static ssize_t show_channels(struct device *d,
3587 struct device_attribute *attr, char *buf)
3588{
8318d78a
JB
3589 /* all this shit doesn't belong into sysfs anyway */
3590 return 0;
b481de9c
ZY
3591}
3592
3593static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3594
3595static ssize_t show_statistics(struct device *d,
3596 struct device_attribute *attr, char *buf)
3597{
4a8a4322 3598 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3599 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3600 u32 len = 0, ofs = 0;
f2c7e521 3601 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3602 int rc = 0;
3603
775a6e27 3604 if (!iwl_is_alive(priv))
b481de9c
ZY
3605 return -EAGAIN;
3606
3607 mutex_lock(&priv->mutex);
17f841cd 3608 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
3609 mutex_unlock(&priv->mutex);
3610
3611 if (rc) {
3612 len = sprintf(buf,
3613 "Error sending statistics request: 0x%08X\n", rc);
3614 return len;
3615 }
3616
3617 while (size && (PAGE_SIZE - len)) {
3618 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3619 PAGE_SIZE - len, 1);
3620 len = strlen(buf);
3621 if (PAGE_SIZE - len)
3622 buf[len++] = '\n';
3623
3624 ofs += 16;
3625 size -= min(size, 16U);
3626 }
3627
3628 return len;
3629}
3630
3631static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3632
3633static ssize_t show_antenna(struct device *d,
3634 struct device_attribute *attr, char *buf)
3635{
4a8a4322 3636 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3637
775a6e27 3638 if (!iwl_is_alive(priv))
b481de9c
ZY
3639 return -EAGAIN;
3640
7e4bca5e 3641 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3642}
3643
3644static ssize_t store_antenna(struct device *d,
3645 struct device_attribute *attr,
3646 const char *buf, size_t count)
3647{
7530f85f 3648 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3649 int ant;
b481de9c
ZY
3650
3651 if (count == 0)
3652 return 0;
3653
3654 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3655 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3656 return count;
3657 }
3658
3659 if ((ant >= 0) && (ant <= 2)) {
e1623446 3660 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3661 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3662 } else
e1623446 3663 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3664
3665
3666 return count;
3667}
3668
3669static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3670
3671static ssize_t show_status(struct device *d,
3672 struct device_attribute *attr, char *buf)
3673{
928841b1 3674 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3675 if (!iwl_is_alive(priv))
b481de9c
ZY
3676 return -EAGAIN;
3677 return sprintf(buf, "0x%08x\n", (int)priv->status);
3678}
3679
3680static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3681
3682static ssize_t dump_error_log(struct device *d,
3683 struct device_attribute *attr,
3684 const char *buf, size_t count)
3685{
928841b1 3686 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3687 char *p = (char *)buf;
3688
3689 if (p[0] == '1')
928841b1 3690 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3691
3692 return strnlen(buf, count);
3693}
3694
3695static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3696
b481de9c
ZY
3697/*****************************************************************************
3698 *
a96a27f9 3699 * driver setup and tear down
b481de9c
ZY
3700 *
3701 *****************************************************************************/
3702
4a8a4322 3703static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3704{
d21050c7 3705 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3706
3707 init_waitqueue_head(&priv->wait_command_queue);
3708
bb8c093b
CH
3709 INIT_WORK(&priv->up, iwl3945_bg_up);
3710 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3711 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3712 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3713 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3714 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3715 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3716 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3717 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3718 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3719 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3720
3721 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3722
3723 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3724 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3725}
3726
4a8a4322 3727static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3728{
bb8c093b 3729 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3730
e47eb6ad 3731 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3732 cancel_delayed_work(&priv->scan_check);
3733 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3734 cancel_work_sync(&priv->beacon_update);
3735}
3736
bb8c093b 3737static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3738 &dev_attr_antenna.attr,
3739 &dev_attr_channels.attr,
3740 &dev_attr_dump_errors.attr,
b481de9c
ZY
3741 &dev_attr_flags.attr,
3742 &dev_attr_filter_flags.attr,
c8b0e6e1 3743#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3744 &dev_attr_measurement.attr,
3745#endif
b481de9c 3746 &dev_attr_retry_rate.attr,
b481de9c
ZY
3747 &dev_attr_statistics.attr,
3748 &dev_attr_status.attr,
3749 &dev_attr_temperature.attr,
b481de9c 3750 &dev_attr_tx_power.attr,
d08853a3 3751#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3752 &dev_attr_debug_level.attr,
3753#endif
b481de9c
ZY
3754 NULL
3755};
3756
bb8c093b 3757static struct attribute_group iwl3945_attribute_group = {
b481de9c 3758 .name = NULL, /* put in device directory */
bb8c093b 3759 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3760};
3761
bb8c093b
CH
3762static struct ieee80211_ops iwl3945_hw_ops = {
3763 .tx = iwl3945_mac_tx,
3764 .start = iwl3945_mac_start,
3765 .stop = iwl3945_mac_stop,
cbb6ab94 3766 .add_interface = iwl_mac_add_interface,
d8052319 3767 .remove_interface = iwl_mac_remove_interface,
4808368d 3768 .config = iwl_mac_config,
8ccde88a 3769 .configure_filter = iwl_configure_filter,
bb8c093b 3770 .set_key = iwl3945_mac_set_key,
aa89f31e 3771 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 3772 .conf_tx = iwl_mac_conf_tx,
bd564261 3773 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3774 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3775 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3776};
3777
e52119c5 3778static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3779{
3780 int ret;
e6148917 3781 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3782
3783 priv->retry_rate = 1;
3784 priv->ibss_beacon = NULL;
3785
3786 spin_lock_init(&priv->lock);
90a30a02
KA
3787 spin_lock_init(&priv->sta_lock);
3788 spin_lock_init(&priv->hcmd_lock);
3789
3790 INIT_LIST_HEAD(&priv->free_frames);
3791
3792 mutex_init(&priv->mutex);
3793
3794 /* Clear the driver's (not device's) station table */
c587de0b 3795 iwl_clear_stations_table(priv);
90a30a02
KA
3796
3797 priv->data_retry_limit = -1;
3798 priv->ieee_channels = NULL;
3799 priv->ieee_rates = NULL;
3800 priv->band = IEEE80211_BAND_2GHZ;
3801
3802 priv->iw_mode = NL80211_IFTYPE_STATION;
3803
3804 iwl_reset_qos(priv);
3805
3806 priv->qos_data.qos_active = 0;
3807 priv->qos_data.qos_cap.val = 0;
3808
3809 priv->rates_mask = IWL_RATES_MASK;
62ea9c5b 3810 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3811
e6148917
SO
3812 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3813 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3814 eeprom->version);
3815 ret = -EINVAL;
3816 goto err;
3817 }
3818 ret = iwl_init_channel_map(priv);
90a30a02
KA
3819 if (ret) {
3820 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3821 goto err;
3822 }
3823
e6148917
SO
3824 /* Set up txpower settings in driver for all channels */
3825 if (iwl3945_txpower_set_from_eeprom(priv)) {
3826 ret = -EIO;
3827 goto err_free_channel_map;
3828 }
3829
534166de 3830 ret = iwlcore_init_geos(priv);
90a30a02
KA
3831 if (ret) {
3832 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3833 goto err_free_channel_map;
3834 }
534166de
SO
3835 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3836
2a4ddaab
AK
3837 return 0;
3838
3839err_free_channel_map:
3840 iwl_free_channel_map(priv);
3841err:
3842 return ret;
3843}
3844
3845static int iwl3945_setup_mac(struct iwl_priv *priv)
3846{
3847 int ret;
3848 struct ieee80211_hw *hw = priv->hw;
3849
3850 hw->rate_control_algorithm = "iwl-3945-rs";
3851 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3852
3853 /* Tell mac80211 our characteristics */
3854 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b 3855 IEEE80211_HW_NOISE_DBM |
e312c24c
JB
3856 IEEE80211_HW_SPECTRUM_MGMT |
3857 IEEE80211_HW_SUPPORTS_PS |
3858 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3859
3860 hw->wiphy->interface_modes =
3861 BIT(NL80211_IFTYPE_STATION) |
3862 BIT(NL80211_IFTYPE_ADHOC);
3863
3864 hw->wiphy->custom_regulatory = true;
3865
37184244
LR
3866 /* Firmware does not support this */
3867 hw->wiphy->disable_beacon_hints = true;
3868
1ecf9fc1
JB
3869 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3870 /* we create the 802.11 header and a zero-length SSID element */
3871 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3872
2a4ddaab
AK
3873 /* Default value; 4 EDCA QOS priorities */
3874 hw->queues = 4;
3875
534166de
SO
3876 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3877 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3878 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3879
534166de
SO
3880 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3881 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3882 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3883
2a4ddaab
AK
3884 ret = ieee80211_register_hw(priv->hw);
3885 if (ret) {
3886 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3887 return ret;
3888 }
3889 priv->mac80211_registered = 1;
90a30a02 3890
2a4ddaab 3891 return 0;
90a30a02
KA
3892}
3893
bb8c093b 3894static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3895{
3896 int err = 0;
4a8a4322 3897 struct iwl_priv *priv;
b481de9c 3898 struct ieee80211_hw *hw;
c0f20d91 3899 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3900 struct iwl3945_eeprom *eeprom;
0359facc 3901 unsigned long flags;
b481de9c 3902
cee53ddb
KA
3903 /***********************
3904 * 1. Allocating HW data
3905 * ********************/
3906
b481de9c
ZY
3907 /* mac80211 allocates memory for this device instance, including
3908 * space for this driver's private structure */
90a30a02 3909 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3910 if (hw == NULL) {
a3139c59 3911 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3912 err = -ENOMEM;
3913 goto out;
3914 }
b481de9c 3915 priv = hw->priv;
90a30a02 3916 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3917
90a30a02
KA
3918 /*
3919 * Disabling hardware scan means that mac80211 will perform scans
3920 * "the hard way", rather than using device's scan.
3921 */
df878d8f 3922 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3923 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3924 iwl3945_hw_ops.hw_scan = NULL;
3925 }
3926
90a30a02 3927
e1623446 3928 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3929 priv->cfg = cfg;
3930 priv->pci_dev = pdev;
40cefda9 3931 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3932
d08853a3 3933#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3934 atomic_set(&priv->restrict_refcnt, 0);
3935#endif
20594eb0
WYG
3936 if (iwl_alloc_traffic_mem(priv))
3937 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3938
cee53ddb
KA
3939 /***************************
3940 * 2. Initializing PCI bus
3941 * *************************/
b481de9c
ZY
3942 if (pci_enable_device(pdev)) {
3943 err = -ENODEV;
3944 goto out_ieee80211_free_hw;
3945 }
3946
3947 pci_set_master(pdev);
3948
284901a9 3949 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3950 if (!err)
284901a9 3951 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3952 if (err) {
978785a3 3953 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
3954 goto out_pci_disable_device;
3955 }
3956
3957 pci_set_drvdata(pdev, priv);
3958 err = pci_request_regions(pdev, DRV_NAME);
3959 if (err)
3960 goto out_pci_disable_device;
6440adb5 3961
cee53ddb
KA
3962 /***********************
3963 * 3. Read REV Register
3964 * ********************/
b481de9c
ZY
3965 priv->hw_base = pci_iomap(pdev, 0, 0);
3966 if (!priv->hw_base) {
3967 err = -ENODEV;
3968 goto out_pci_release_regions;
3969 }
3970
e1623446 3971 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 3972 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3973 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 3974
cee53ddb
KA
3975 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3976 * PCI Tx retries from interfering with C3 CPU state */
3977 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 3978
a8b50a0a
MA
3979 /* this spin lock will be used in apm_ops.init and EEPROM access
3980 * we should init now
3981 */
3982 spin_lock_init(&priv->reg_lock);
3983
90a30a02
KA
3984 /* amp init */
3985 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 3986 if (err < 0) {
d5df2a16 3987 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
90a30a02 3988 goto out_iounmap;
cee53ddb 3989 }
b481de9c 3990
cee53ddb
KA
3991 /***********************
3992 * 4. Read EEPROM
3993 * ********************/
90a30a02 3994
cee53ddb 3995 /* Read the EEPROM */
e6148917 3996 err = iwl_eeprom_init(priv);
cee53ddb 3997 if (err) {
15b1687c 3998 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 3999 goto out_iounmap;
cee53ddb
KA
4000 }
4001 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4002 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4003 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4004 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4005 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4006
cee53ddb
KA
4007 /***********************
4008 * 5. Setup HW Constants
4009 * ********************/
b481de9c 4010 /* Device-specific setup */
3832ec9d 4011 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4012 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4013 goto out_eeprom_free;
b481de9c
ZY
4014 }
4015
cee53ddb
KA
4016 /***********************
4017 * 6. Setup priv
4018 * ********************/
cee53ddb 4019
90a30a02 4020 err = iwl3945_init_drv(priv);
b481de9c 4021 if (err) {
90a30a02 4022 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4023 goto out_unset_hw_params;
b481de9c
ZY
4024 }
4025
978785a3
TW
4026 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4027 priv->cfg->name);
cee53ddb 4028
cee53ddb 4029 /***********************
09f9bf79 4030 * 7. Setup Services
cee53ddb
KA
4031 * ********************/
4032
4033 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4034 iwl_disable_interrupts(priv);
cee53ddb
KA
4035 spin_unlock_irqrestore(&priv->lock, flags);
4036
2663516d
HS
4037 pci_enable_msi(priv->pci_dev);
4038
ef850d7c
MA
4039 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4040 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4041 if (err) {
4042 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4043 goto out_disable_msi;
4044 }
4045
cee53ddb 4046 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4047 if (err) {
15b1687c 4048 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4049 goto out_release_irq;
849e0dce 4050 }
849e0dce 4051
8ccde88a
SO
4052 iwl_set_rxon_channel(priv,
4053 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4054 iwl3945_setup_deferred_work(priv);
4055 iwl3945_setup_rx_handlers(priv);
4056
cee53ddb 4057 /*********************************
09f9bf79 4058 * 8. Setup and Register mac80211
cee53ddb
KA
4059 * *******************************/
4060
2a4ddaab 4061 iwl_enable_interrupts(priv);
b481de9c 4062
2a4ddaab
AK
4063 err = iwl3945_setup_mac(priv);
4064 if (err)
4065 goto out_remove_sysfs;
cee53ddb 4066
a75fbe8d
AK
4067 err = iwl_dbgfs_register(priv, DRV_NAME);
4068 if (err)
4069 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4070
2663516d
HS
4071 /* Start monitoring the killswitch */
4072 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4073 2 * HZ);
4074
b481de9c
ZY
4075 return 0;
4076
cee53ddb 4077 out_remove_sysfs:
c8f16138
RC
4078 destroy_workqueue(priv->workqueue);
4079 priv->workqueue = NULL;
cee53ddb 4080 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4081 out_release_irq:
2663516d 4082 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4083 out_disable_msi:
4084 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4085 iwlcore_free_geos(priv);
4086 iwl_free_channel_map(priv);
4087 out_unset_hw_params:
4088 iwl3945_unset_hw_params(priv);
4089 out_eeprom_free:
4090 iwl_eeprom_free(priv);
b481de9c
ZY
4091 out_iounmap:
4092 pci_iounmap(pdev, priv->hw_base);
4093 out_pci_release_regions:
4094 pci_release_regions(pdev);
4095 out_pci_disable_device:
b481de9c 4096 pci_set_drvdata(pdev, NULL);
623d563e 4097 pci_disable_device(pdev);
b481de9c
ZY
4098 out_ieee80211_free_hw:
4099 ieee80211_free_hw(priv->hw);
20594eb0 4100 iwl_free_traffic_mem(priv);
b481de9c
ZY
4101 out:
4102 return err;
4103}
4104
c83dbf68 4105static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4106{
4a8a4322 4107 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4108 unsigned long flags;
b481de9c
ZY
4109
4110 if (!priv)
4111 return;
4112
e1623446 4113 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4114
a75fbe8d
AK
4115 iwl_dbgfs_unregister(priv);
4116
b481de9c 4117 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4118
d552bfb6
KA
4119 if (priv->mac80211_registered) {
4120 ieee80211_unregister_hw(priv->hw);
4121 priv->mac80211_registered = 0;
4122 } else {
4123 iwl3945_down(priv);
4124 }
b481de9c 4125
0359facc
MA
4126 /* make sure we flush any pending irq or
4127 * tasklet for the driver
4128 */
4129 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4130 iwl_disable_interrupts(priv);
0359facc
MA
4131 spin_unlock_irqrestore(&priv->lock, flags);
4132
4133 iwl_synchronize_irq(priv);
4134
bb8c093b 4135 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4136
71d449b5 4137 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4138
bb8c093b 4139 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4140
4141 if (priv->rxq.bd)
df833b1d 4142 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4143 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4144
3832ec9d 4145 iwl3945_unset_hw_params(priv);
c587de0b 4146 iwl_clear_stations_table(priv);
b481de9c 4147
6ef89d0a
MA
4148 /*netif_stop_queue(dev); */
4149 flush_workqueue(priv->workqueue);
4150
bb8c093b 4151 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4152 * priv->workqueue... so we can't take down the workqueue
4153 * until now... */
4154 destroy_workqueue(priv->workqueue);
4155 priv->workqueue = NULL;
20594eb0 4156 iwl_free_traffic_mem(priv);
b481de9c 4157
2663516d
HS
4158 free_irq(pdev->irq, priv);
4159 pci_disable_msi(pdev);
4160
b481de9c
ZY
4161 pci_iounmap(pdev, priv->hw_base);
4162 pci_release_regions(pdev);
4163 pci_disable_device(pdev);
4164 pci_set_drvdata(pdev, NULL);
4165
e6148917 4166 iwl_free_channel_map(priv);
534166de 4167 iwlcore_free_geos(priv);
805cee5b 4168 kfree(priv->scan);
b481de9c
ZY
4169 if (priv->ibss_beacon)
4170 dev_kfree_skb(priv->ibss_beacon);
4171
4172 ieee80211_free_hw(priv->hw);
4173}
4174
b481de9c
ZY
4175
4176/*****************************************************************************
4177 *
4178 * driver and module entry point
4179 *
4180 *****************************************************************************/
4181
bb8c093b 4182static struct pci_driver iwl3945_driver = {
b481de9c 4183 .name = DRV_NAME,
bb8c093b
CH
4184 .id_table = iwl3945_hw_card_ids,
4185 .probe = iwl3945_pci_probe,
4186 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4187#ifdef CONFIG_PM
6da3a13e
WYG
4188 .suspend = iwl_pci_suspend,
4189 .resume = iwl_pci_resume,
b481de9c
ZY
4190#endif
4191};
4192
bb8c093b 4193static int __init iwl3945_init(void)
b481de9c
ZY
4194{
4195
4196 int ret;
4197 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4198 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4199
4200 ret = iwl3945_rate_control_register();
4201 if (ret) {
a3139c59
SO
4202 printk(KERN_ERR DRV_NAME
4203 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4204 return ret;
4205 }
4206
bb8c093b 4207 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4208 if (ret) {
a3139c59 4209 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4210 goto error_register;
b481de9c 4211 }
b481de9c
ZY
4212
4213 return ret;
897e1cf2 4214
897e1cf2
RC
4215error_register:
4216 iwl3945_rate_control_unregister();
4217 return ret;
b481de9c
ZY
4218}
4219
bb8c093b 4220static void __exit iwl3945_exit(void)
b481de9c 4221{
bb8c093b 4222 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4223 iwl3945_rate_control_unregister();
b481de9c
ZY
4224}
4225
a0987a8d 4226MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4227
df878d8f 4228module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 4229MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
9c74d9fb
SO
4230module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
4231MODULE_PARM_DESC(swcrypto,
4232 "using software crypto (default 1 [software])\n");
a562a9dd
RC
4233#ifdef CONFIG_IWLWIFI_DEBUG
4234module_param_named(debug, iwl_debug_level, uint, 0644);
b481de9c 4235MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4236#endif
df878d8f 4237module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c 4238MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
af48d048
SO
4239module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444);
4240MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4241
bb8c093b
CH
4242module_exit(iwl3945_exit);
4243module_init(iwl3945_init);