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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/version.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
44 | #include <net/ieee80211_radiotap.h> | |
45 | #include <net/mac80211.h> | |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
b481de9c ZY |
49 | #include "iwl-3945.h" |
50 | #include "iwl-helpers.h" | |
51 | ||
c8b0e6e1 | 52 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 53 | u32 iwl3945_debug_level; |
b481de9c ZY |
54 | #endif |
55 | ||
bb8c093b CH |
56 | static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv, |
57 | struct iwl3945_tx_queue *txq); | |
416e1438 | 58 | |
b481de9c ZY |
59 | /****************************************************************************** |
60 | * | |
61 | * module boiler plate | |
62 | * | |
63 | ******************************************************************************/ | |
64 | ||
65 | /* module parameters */ | |
6440adb5 BC |
66 | static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */ |
67 | static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */ | |
68 | static int iwl3945_param_disable; /* def: 0 = enable radio */ | |
9fbab516 | 69 | static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */ |
6440adb5 BC |
70 | int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */ |
71 | static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */ | |
72 | int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */ | |
b481de9c ZY |
73 | |
74 | /* | |
75 | * module name, copyright, version, etc. | |
76 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | |
77 | */ | |
78 | ||
79 | #define DRV_DESCRIPTION \ | |
80 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
81 | ||
c8b0e6e1 | 82 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
83 | #define VD "d" |
84 | #else | |
85 | #define VD | |
86 | #endif | |
87 | ||
c8b0e6e1 | 88 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
89 | #define VS "s" |
90 | #else | |
91 | #define VS | |
92 | #endif | |
93 | ||
b9e0b449 | 94 | #define IWLWIFI_VERSION "1.2.26k" VD VS |
b481de9c ZY |
95 | #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation" |
96 | #define DRV_VERSION IWLWIFI_VERSION | |
97 | ||
98 | /* Change firmware file name, using "-" and incrementing number, | |
99 | * *only* when uCode interface or architecture changes so that it | |
100 | * is not compatible with earlier drivers. | |
101 | * This number will also appear in << 8 position of 1st dword of uCode file */ | |
102 | #define IWL3945_UCODE_API "-1" | |
103 | ||
104 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
105 | MODULE_VERSION(DRV_VERSION); | |
106 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
107 | MODULE_LICENSE("GPL"); | |
108 | ||
416e1438 | 109 | static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr) |
b481de9c ZY |
110 | { |
111 | u16 fc = le16_to_cpu(hdr->frame_control); | |
112 | int hdr_len = ieee80211_get_hdrlen(fc); | |
113 | ||
114 | if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA)) | |
115 | return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN); | |
116 | return NULL; | |
117 | } | |
118 | ||
8318d78a JB |
119 | static const struct ieee80211_supported_band *iwl3945_get_band( |
120 | struct iwl3945_priv *priv, enum ieee80211_band band) | |
b481de9c | 121 | { |
8318d78a | 122 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
123 | } |
124 | ||
bb8c093b | 125 | static int iwl3945_is_empty_essid(const char *essid, int essid_len) |
b481de9c ZY |
126 | { |
127 | /* Single white space is for Linksys APs */ | |
128 | if (essid_len == 1 && essid[0] == ' ') | |
129 | return 1; | |
130 | ||
131 | /* Otherwise, if the entire essid is 0, we assume it is hidden */ | |
132 | while (essid_len) { | |
133 | essid_len--; | |
134 | if (essid[essid_len] != '\0') | |
135 | return 0; | |
136 | } | |
137 | ||
138 | return 1; | |
139 | } | |
140 | ||
bb8c093b | 141 | static const char *iwl3945_escape_essid(const char *essid, u8 essid_len) |
b481de9c ZY |
142 | { |
143 | static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; | |
144 | const char *s = essid; | |
145 | char *d = escaped; | |
146 | ||
bb8c093b | 147 | if (iwl3945_is_empty_essid(essid, essid_len)) { |
b481de9c ZY |
148 | memcpy(escaped, "<hidden>", sizeof("<hidden>")); |
149 | return escaped; | |
150 | } | |
151 | ||
152 | essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE); | |
153 | while (essid_len--) { | |
154 | if (*s == '\0') { | |
155 | *d++ = '\\'; | |
156 | *d++ = '0'; | |
157 | s++; | |
158 | } else | |
159 | *d++ = *s++; | |
160 | } | |
161 | *d = '\0'; | |
162 | return escaped; | |
163 | } | |
164 | ||
b481de9c ZY |
165 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
166 | * DMA services | |
167 | * | |
168 | * Theory of operation | |
169 | * | |
6440adb5 BC |
170 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
171 | * of buffer descriptors, each of which points to one or more data buffers for | |
172 | * the device to read from or fill. Driver and device exchange status of each | |
173 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
174 | * entries in each circular buffer, to protect against confusing empty and full | |
175 | * queue states. | |
176 | * | |
177 | * The device reads or writes the data in the queues via the device's several | |
178 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
179 | * |
180 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
181 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
182 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
183 | * Tx queue resumed. | |
184 | * | |
6440adb5 BC |
185 | * The 3945 operates with six queues: One receive queue, one transmit queue |
186 | * (#4) for sending commands to the device firmware, and four transmit queues | |
187 | * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused. | |
b481de9c ZY |
188 | ***************************************************/ |
189 | ||
bb8c093b | 190 | static int iwl3945_queue_space(const struct iwl3945_queue *q) |
b481de9c | 191 | { |
fc4b6853 | 192 | int s = q->read_ptr - q->write_ptr; |
b481de9c | 193 | |
fc4b6853 | 194 | if (q->read_ptr > q->write_ptr) |
b481de9c ZY |
195 | s -= q->n_bd; |
196 | ||
197 | if (s <= 0) | |
198 | s += q->n_window; | |
199 | /* keep some reserve to not confuse empty and full situations */ | |
200 | s -= 2; | |
201 | if (s < 0) | |
202 | s = 0; | |
203 | return s; | |
204 | } | |
205 | ||
6440adb5 BC |
206 | /** |
207 | * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning | |
208 | * @index -- current index | |
209 | * @n_bd -- total number of entries in queue (must be power of 2) | |
210 | */ | |
bb8c093b | 211 | static inline int iwl3945_queue_inc_wrap(int index, int n_bd) |
b481de9c ZY |
212 | { |
213 | return ++index & (n_bd - 1); | |
214 | } | |
215 | ||
6440adb5 BC |
216 | /** |
217 | * iwl3945_queue_dec_wrap - increment queue index, wrap back to end | |
218 | * @index -- current index | |
219 | * @n_bd -- total number of entries in queue (must be power of 2) | |
220 | */ | |
bb8c093b | 221 | static inline int iwl3945_queue_dec_wrap(int index, int n_bd) |
b481de9c ZY |
222 | { |
223 | return --index & (n_bd - 1); | |
224 | } | |
225 | ||
bb8c093b | 226 | static inline int x2_queue_used(const struct iwl3945_queue *q, int i) |
b481de9c | 227 | { |
fc4b6853 TW |
228 | return q->write_ptr > q->read_ptr ? |
229 | (i >= q->read_ptr && i < q->write_ptr) : | |
230 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
231 | } |
232 | ||
bb8c093b | 233 | static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge) |
b481de9c | 234 | { |
6440adb5 | 235 | /* This is for scan command, the big buffer at end of command array */ |
b481de9c | 236 | if (is_huge) |
6440adb5 | 237 | return q->n_window; /* must be power of 2 */ |
b481de9c | 238 | |
6440adb5 | 239 | /* Otherwise, use normal size buffers */ |
b481de9c ZY |
240 | return index & (q->n_window - 1); |
241 | } | |
242 | ||
6440adb5 BC |
243 | /** |
244 | * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes | |
245 | */ | |
bb8c093b | 246 | static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q, |
b481de9c ZY |
247 | int count, int slots_num, u32 id) |
248 | { | |
249 | q->n_bd = count; | |
250 | q->n_window = slots_num; | |
251 | q->id = id; | |
252 | ||
bb8c093b CH |
253 | /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap |
254 | * and iwl3945_queue_dec_wrap are broken. */ | |
b481de9c ZY |
255 | BUG_ON(!is_power_of_2(count)); |
256 | ||
257 | /* slots_num must be power-of-two size, otherwise | |
258 | * get_cmd_index is broken. */ | |
259 | BUG_ON(!is_power_of_2(slots_num)); | |
260 | ||
261 | q->low_mark = q->n_window / 4; | |
262 | if (q->low_mark < 4) | |
263 | q->low_mark = 4; | |
264 | ||
265 | q->high_mark = q->n_window / 8; | |
266 | if (q->high_mark < 2) | |
267 | q->high_mark = 2; | |
268 | ||
fc4b6853 | 269 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
6440adb5 BC |
274 | /** |
275 | * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
276 | */ | |
bb8c093b CH |
277 | static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv, |
278 | struct iwl3945_tx_queue *txq, u32 id) | |
b481de9c ZY |
279 | { |
280 | struct pci_dev *dev = priv->pci_dev; | |
281 | ||
6440adb5 BC |
282 | /* Driver private data, only for Tx (not command) queues, |
283 | * not shared with device. */ | |
b481de9c ZY |
284 | if (id != IWL_CMD_QUEUE_NUM) { |
285 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
286 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
287 | if (!txq->txb) { | |
01ebd063 | 288 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
289 | "structures failed\n"); |
290 | goto error; | |
291 | } | |
292 | } else | |
293 | txq->txb = NULL; | |
294 | ||
6440adb5 BC |
295 | /* Circular buffer of transmit frame descriptors (TFDs), |
296 | * shared with device */ | |
b481de9c ZY |
297 | txq->bd = pci_alloc_consistent(dev, |
298 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
299 | &txq->q.dma_addr); | |
300 | ||
301 | if (!txq->bd) { | |
302 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
303 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
304 | goto error; | |
305 | } | |
306 | txq->q.id = id; | |
307 | ||
308 | return 0; | |
309 | ||
310 | error: | |
311 | if (txq->txb) { | |
312 | kfree(txq->txb); | |
313 | txq->txb = NULL; | |
314 | } | |
315 | ||
316 | return -ENOMEM; | |
317 | } | |
318 | ||
6440adb5 BC |
319 | /** |
320 | * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue | |
321 | */ | |
bb8c093b CH |
322 | int iwl3945_tx_queue_init(struct iwl3945_priv *priv, |
323 | struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id) | |
b481de9c ZY |
324 | { |
325 | struct pci_dev *dev = priv->pci_dev; | |
326 | int len; | |
327 | int rc = 0; | |
328 | ||
6440adb5 BC |
329 | /* |
330 | * Alloc buffer array for commands (Tx or other types of commands). | |
331 | * For the command queue (#4), allocate command space + one big | |
332 | * command for scan, since scan command is very huge; the system will | |
333 | * not have two scans at the same time, so only one is needed. | |
334 | * For data Tx queues (all other queues), no super-size command | |
335 | * space is needed. | |
336 | */ | |
bb8c093b | 337 | len = sizeof(struct iwl3945_cmd) * slots_num; |
b481de9c ZY |
338 | if (txq_id == IWL_CMD_QUEUE_NUM) |
339 | len += IWL_MAX_SCAN_SIZE; | |
340 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
341 | if (!txq->cmd) | |
342 | return -ENOMEM; | |
343 | ||
6440adb5 | 344 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 345 | rc = iwl3945_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
346 | if (rc) { |
347 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
348 | ||
349 | return -ENOMEM; | |
350 | } | |
351 | txq->need_update = 0; | |
352 | ||
353 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
bb8c093b | 354 | * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */ |
b481de9c | 355 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
6440adb5 BC |
356 | |
357 | /* Initialize queue high/low-water, head/tail indexes */ | |
bb8c093b | 358 | iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 359 | |
6440adb5 | 360 | /* Tell device where to find queue, enable DMA channel. */ |
bb8c093b | 361 | iwl3945_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
366 | /** | |
bb8c093b | 367 | * iwl3945_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
368 | * @txq: Transmit queue to deallocate. |
369 | * | |
370 | * Empty queue by removing and destroying all BD's. | |
6440adb5 BC |
371 | * Free all buffers. |
372 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 373 | */ |
bb8c093b | 374 | void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) |
b481de9c | 375 | { |
bb8c093b | 376 | struct iwl3945_queue *q = &txq->q; |
b481de9c ZY |
377 | struct pci_dev *dev = priv->pci_dev; |
378 | int len; | |
379 | ||
380 | if (q->n_bd == 0) | |
381 | return; | |
382 | ||
383 | /* first, empty all BD's */ | |
fc4b6853 | 384 | for (; q->write_ptr != q->read_ptr; |
bb8c093b CH |
385 | q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) |
386 | iwl3945_hw_txq_free_tfd(priv, txq); | |
b481de9c | 387 | |
bb8c093b | 388 | len = sizeof(struct iwl3945_cmd) * q->n_window; |
b481de9c ZY |
389 | if (q->id == IWL_CMD_QUEUE_NUM) |
390 | len += IWL_MAX_SCAN_SIZE; | |
391 | ||
6440adb5 | 392 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
393 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
394 | ||
6440adb5 | 395 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 396 | if (txq->q.n_bd) |
bb8c093b | 397 | pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) * |
b481de9c ZY |
398 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
399 | ||
6440adb5 | 400 | /* De-alloc array of per-TFD driver data */ |
b481de9c ZY |
401 | if (txq->txb) { |
402 | kfree(txq->txb); | |
403 | txq->txb = NULL; | |
404 | } | |
405 | ||
6440adb5 | 406 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
407 | memset(txq, 0, sizeof(*txq)); |
408 | } | |
409 | ||
bb8c093b | 410 | const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
b481de9c ZY |
411 | |
412 | /*************** STATION TABLE MANAGEMENT **** | |
9fbab516 | 413 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
414 | * the functionality provided here |
415 | */ | |
416 | ||
417 | /**************************************************************/ | |
01ebd063 | 418 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 BC |
419 | /** |
420 | * iwl3945_remove_station - Remove driver's knowledge of station. | |
421 | * | |
422 | * NOTE: This does not remove station from device's station table. | |
423 | */ | |
bb8c093b | 424 | static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
425 | { |
426 | int index = IWL_INVALID_STATION; | |
427 | int i; | |
428 | unsigned long flags; | |
429 | ||
430 | spin_lock_irqsave(&priv->sta_lock, flags); | |
431 | ||
432 | if (is_ap) | |
433 | index = IWL_AP_ID; | |
434 | else if (is_broadcast_ether_addr(addr)) | |
435 | index = priv->hw_setting.bcast_sta_id; | |
436 | else | |
437 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) | |
438 | if (priv->stations[i].used && | |
439 | !compare_ether_addr(priv->stations[i].sta.sta.addr, | |
440 | addr)) { | |
441 | index = i; | |
442 | break; | |
443 | } | |
444 | ||
445 | if (unlikely(index == IWL_INVALID_STATION)) | |
446 | goto out; | |
447 | ||
448 | if (priv->stations[index].used) { | |
449 | priv->stations[index].used = 0; | |
450 | priv->num_stations--; | |
451 | } | |
452 | ||
453 | BUG_ON(priv->num_stations < 0); | |
454 | ||
455 | out: | |
456 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
457 | return 0; | |
458 | } | |
556f8db7 | 459 | #endif |
6440adb5 BC |
460 | |
461 | /** | |
462 | * iwl3945_clear_stations_table - Clear the driver's station table | |
463 | * | |
464 | * NOTE: This does not clear or otherwise alter the device's station table. | |
465 | */ | |
bb8c093b | 466 | static void iwl3945_clear_stations_table(struct iwl3945_priv *priv) |
b481de9c ZY |
467 | { |
468 | unsigned long flags; | |
469 | ||
470 | spin_lock_irqsave(&priv->sta_lock, flags); | |
471 | ||
472 | priv->num_stations = 0; | |
473 | memset(priv->stations, 0, sizeof(priv->stations)); | |
474 | ||
475 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
476 | } | |
477 | ||
6440adb5 BC |
478 | /** |
479 | * iwl3945_add_station - Add station to station tables in driver and device | |
480 | */ | |
bb8c093b | 481 | u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags) |
b481de9c ZY |
482 | { |
483 | int i; | |
484 | int index = IWL_INVALID_STATION; | |
bb8c093b | 485 | struct iwl3945_station_entry *station; |
b481de9c | 486 | unsigned long flags_spin; |
0795af57 | 487 | DECLARE_MAC_BUF(mac); |
c14c521e | 488 | u8 rate; |
b481de9c ZY |
489 | |
490 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
491 | if (is_ap) | |
492 | index = IWL_AP_ID; | |
493 | else if (is_broadcast_ether_addr(addr)) | |
494 | index = priv->hw_setting.bcast_sta_id; | |
495 | else | |
496 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) { | |
497 | if (!compare_ether_addr(priv->stations[i].sta.sta.addr, | |
498 | addr)) { | |
499 | index = i; | |
500 | break; | |
501 | } | |
502 | ||
503 | if (!priv->stations[i].used && | |
504 | index == IWL_INVALID_STATION) | |
505 | index = i; | |
506 | } | |
507 | ||
01ebd063 | 508 | /* These two conditions has the same outcome but keep them separate |
b481de9c ZY |
509 | since they have different meaning */ |
510 | if (unlikely(index == IWL_INVALID_STATION)) { | |
511 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
512 | return index; | |
513 | } | |
514 | ||
515 | if (priv->stations[index].used && | |
516 | !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) { | |
517 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
518 | return index; | |
519 | } | |
520 | ||
0795af57 | 521 | IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr)); |
b481de9c ZY |
522 | station = &priv->stations[index]; |
523 | station->used = 1; | |
524 | priv->num_stations++; | |
525 | ||
6440adb5 | 526 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 527 | memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd)); |
b481de9c ZY |
528 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
529 | station->sta.mode = 0; | |
530 | station->sta.sta.sta_id = index; | |
531 | station->sta.station_flags = 0; | |
532 | ||
8318d78a | 533 | if (priv->band == IEEE80211_BAND_5GHZ) |
69946333 TW |
534 | rate = IWL_RATE_6M_PLCP; |
535 | else | |
536 | rate = IWL_RATE_1M_PLCP; | |
c14c521e ZY |
537 | |
538 | /* Turn on both antennas for the station... */ | |
539 | station->sta.rate_n_flags = | |
bb8c093b | 540 | iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK); |
c14c521e ZY |
541 | station->current_rate.rate_n_flags = |
542 | le16_to_cpu(station->sta.rate_n_flags); | |
543 | ||
b481de9c | 544 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
6440adb5 BC |
545 | |
546 | /* Add station to device's station table */ | |
bb8c093b | 547 | iwl3945_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
548 | return index; |
549 | ||
550 | } | |
551 | ||
552 | /*************** DRIVER STATUS FUNCTIONS *****/ | |
553 | ||
bb8c093b | 554 | static inline int iwl3945_is_ready(struct iwl3945_priv *priv) |
b481de9c ZY |
555 | { |
556 | /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are | |
557 | * set but EXIT_PENDING is not */ | |
558 | return test_bit(STATUS_READY, &priv->status) && | |
559 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) && | |
560 | !test_bit(STATUS_EXIT_PENDING, &priv->status); | |
561 | } | |
562 | ||
bb8c093b | 563 | static inline int iwl3945_is_alive(struct iwl3945_priv *priv) |
b481de9c ZY |
564 | { |
565 | return test_bit(STATUS_ALIVE, &priv->status); | |
566 | } | |
567 | ||
bb8c093b | 568 | static inline int iwl3945_is_init(struct iwl3945_priv *priv) |
b481de9c ZY |
569 | { |
570 | return test_bit(STATUS_INIT, &priv->status); | |
571 | } | |
572 | ||
bb8c093b | 573 | static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv) |
b481de9c ZY |
574 | { |
575 | return test_bit(STATUS_RF_KILL_HW, &priv->status) || | |
576 | test_bit(STATUS_RF_KILL_SW, &priv->status); | |
577 | } | |
578 | ||
bb8c093b | 579 | static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv) |
b481de9c ZY |
580 | { |
581 | ||
bb8c093b | 582 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
583 | return 0; |
584 | ||
bb8c093b | 585 | return iwl3945_is_ready(priv); |
b481de9c ZY |
586 | } |
587 | ||
588 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
589 | ||
590 | #define IWL_CMD(x) case x : return #x | |
591 | ||
592 | static const char *get_cmd_string(u8 cmd) | |
593 | { | |
594 | switch (cmd) { | |
595 | IWL_CMD(REPLY_ALIVE); | |
596 | IWL_CMD(REPLY_ERROR); | |
597 | IWL_CMD(REPLY_RXON); | |
598 | IWL_CMD(REPLY_RXON_ASSOC); | |
599 | IWL_CMD(REPLY_QOS_PARAM); | |
600 | IWL_CMD(REPLY_RXON_TIMING); | |
601 | IWL_CMD(REPLY_ADD_STA); | |
602 | IWL_CMD(REPLY_REMOVE_STA); | |
603 | IWL_CMD(REPLY_REMOVE_ALL_STA); | |
604 | IWL_CMD(REPLY_3945_RX); | |
605 | IWL_CMD(REPLY_TX); | |
606 | IWL_CMD(REPLY_RATE_SCALE); | |
607 | IWL_CMD(REPLY_LEDS_CMD); | |
608 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | |
609 | IWL_CMD(RADAR_NOTIFICATION); | |
610 | IWL_CMD(REPLY_QUIET_CMD); | |
611 | IWL_CMD(REPLY_CHANNEL_SWITCH); | |
612 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | |
613 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | |
614 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | |
615 | IWL_CMD(POWER_TABLE_CMD); | |
616 | IWL_CMD(PM_SLEEP_NOTIFICATION); | |
617 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | |
618 | IWL_CMD(REPLY_SCAN_CMD); | |
619 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | |
620 | IWL_CMD(SCAN_START_NOTIFICATION); | |
621 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | |
622 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | |
623 | IWL_CMD(BEACON_NOTIFICATION); | |
624 | IWL_CMD(REPLY_TX_BEACON); | |
625 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | |
626 | IWL_CMD(QUIET_NOTIFICATION); | |
627 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | |
628 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | |
629 | IWL_CMD(REPLY_BT_CONFIG); | |
630 | IWL_CMD(REPLY_STATISTICS_CMD); | |
631 | IWL_CMD(STATISTICS_NOTIFICATION); | |
632 | IWL_CMD(REPLY_CARD_STATE_CMD); | |
633 | IWL_CMD(CARD_STATE_NOTIFICATION); | |
634 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | |
635 | default: | |
636 | return "UNKNOWN"; | |
637 | ||
638 | } | |
639 | } | |
640 | ||
641 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) | |
642 | ||
643 | /** | |
bb8c093b | 644 | * iwl3945_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
645 | * @priv: device private data point |
646 | * @cmd: a point to the ucode command structure | |
647 | * | |
648 | * The function returns < 0 values to indicate the operation is | |
649 | * failed. On success, it turns the index (> 0) of command in the | |
650 | * command queue. | |
651 | */ | |
bb8c093b | 652 | static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 653 | { |
bb8c093b CH |
654 | struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
655 | struct iwl3945_queue *q = &txq->q; | |
656 | struct iwl3945_tfd_frame *tfd; | |
b481de9c | 657 | u32 *control_flags; |
bb8c093b | 658 | struct iwl3945_cmd *out_cmd; |
b481de9c ZY |
659 | u32 idx; |
660 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
661 | dma_addr_t phys_addr; | |
662 | int pad; | |
663 | u16 count; | |
664 | int ret; | |
665 | unsigned long flags; | |
666 | ||
667 | /* If any of the command structures end up being larger than | |
668 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
669 | * we will need to increase the size of the TFD entries */ | |
670 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
671 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
672 | ||
c342a1b9 GG |
673 | |
674 | if (iwl3945_is_rfkill(priv)) { | |
675 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
676 | return -EIO; | |
677 | } | |
678 | ||
bb8c093b | 679 | if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
680 | IWL_ERROR("No space for Tx\n"); |
681 | return -ENOSPC; | |
682 | } | |
683 | ||
684 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
685 | ||
fc4b6853 | 686 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
687 | memset(tfd, 0, sizeof(*tfd)); |
688 | ||
689 | control_flags = (u32 *) tfd; | |
690 | ||
fc4b6853 | 691 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
692 | out_cmd = &txq->cmd[idx]; |
693 | ||
694 | out_cmd->hdr.cmd = cmd->id; | |
695 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
696 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
697 | ||
698 | /* At this point, the out_cmd now has all of the incoming cmd | |
699 | * information */ | |
700 | ||
701 | out_cmd->hdr.flags = 0; | |
702 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 703 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c ZY |
704 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
705 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
706 | ||
707 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
bb8c093b CH |
708 | offsetof(struct iwl3945_cmd, hdr); |
709 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | |
b481de9c ZY |
710 | |
711 | pad = U32_PAD(cmd->len); | |
712 | count = TFD_CTL_COUNT_GET(*control_flags); | |
713 | *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad); | |
714 | ||
715 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
716 | "%d bytes at %d[%d]:%d\n", | |
717 | get_cmd_string(out_cmd->hdr.cmd), | |
718 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 719 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
720 | |
721 | txq->need_update = 1; | |
6440adb5 BC |
722 | |
723 | /* Increment and update queue's write index */ | |
bb8c093b CH |
724 | q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd); |
725 | ret = iwl3945_tx_queue_update_write_ptr(priv, txq); | |
b481de9c ZY |
726 | |
727 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
728 | return ret ? ret : idx; | |
729 | } | |
730 | ||
bb8c093b | 731 | static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
732 | { |
733 | int ret; | |
734 | ||
735 | BUG_ON(!(cmd->meta.flags & CMD_ASYNC)); | |
736 | ||
737 | /* An asynchronous command can not expect an SKB to be set. */ | |
738 | BUG_ON(cmd->meta.flags & CMD_WANT_SKB); | |
739 | ||
740 | /* An asynchronous command MUST have a callback. */ | |
741 | BUG_ON(!cmd->meta.u.callback); | |
742 | ||
743 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
744 | return -EBUSY; | |
745 | ||
bb8c093b | 746 | ret = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c | 747 | if (ret < 0) { |
bb8c093b | 748 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
749 | get_cmd_string(cmd->id), ret); |
750 | return ret; | |
751 | } | |
752 | return 0; | |
753 | } | |
754 | ||
bb8c093b | 755 | static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
756 | { |
757 | int cmd_idx; | |
758 | int ret; | |
759 | static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */ | |
760 | ||
761 | BUG_ON(cmd->meta.flags & CMD_ASYNC); | |
762 | ||
763 | /* A synchronous command can not have a callback set. */ | |
764 | BUG_ON(cmd->meta.u.callback != NULL); | |
765 | ||
766 | if (atomic_xchg(&entry, 1)) { | |
767 | IWL_ERROR("Error sending %s: Already sending a host command\n", | |
768 | get_cmd_string(cmd->id)); | |
769 | return -EBUSY; | |
770 | } | |
771 | ||
772 | set_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
773 | ||
774 | if (cmd->meta.flags & CMD_WANT_SKB) | |
775 | cmd->meta.source = &cmd->meta; | |
776 | ||
bb8c093b | 777 | cmd_idx = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c ZY |
778 | if (cmd_idx < 0) { |
779 | ret = cmd_idx; | |
bb8c093b | 780 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
781 | get_cmd_string(cmd->id), ret); |
782 | goto out; | |
783 | } | |
784 | ||
785 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
786 | !test_bit(STATUS_HCMD_ACTIVE, &priv->status), | |
787 | HOST_COMPLETE_TIMEOUT); | |
788 | if (!ret) { | |
789 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) { | |
790 | IWL_ERROR("Error sending %s: time out after %dms.\n", | |
791 | get_cmd_string(cmd->id), | |
792 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
793 | ||
794 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
795 | ret = -ETIMEDOUT; | |
796 | goto cancel; | |
797 | } | |
798 | } | |
799 | ||
800 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
801 | IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n", | |
802 | get_cmd_string(cmd->id)); | |
803 | ret = -ECANCELED; | |
804 | goto fail; | |
805 | } | |
806 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { | |
807 | IWL_DEBUG_INFO("Command %s failed: FW Error\n", | |
808 | get_cmd_string(cmd->id)); | |
809 | ret = -EIO; | |
810 | goto fail; | |
811 | } | |
812 | if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) { | |
813 | IWL_ERROR("Error: Response NULL in '%s'\n", | |
814 | get_cmd_string(cmd->id)); | |
815 | ret = -EIO; | |
816 | goto out; | |
817 | } | |
818 | ||
819 | ret = 0; | |
820 | goto out; | |
821 | ||
822 | cancel: | |
823 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
bb8c093b | 824 | struct iwl3945_cmd *qcmd; |
b481de9c ZY |
825 | |
826 | /* Cancel the CMD_WANT_SKB flag for the cmd in the | |
827 | * TX cmd queue. Otherwise in case the cmd comes | |
828 | * in later, it will possibly set an invalid | |
829 | * address (cmd->meta.source). */ | |
830 | qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; | |
831 | qcmd->meta.flags &= ~CMD_WANT_SKB; | |
832 | } | |
833 | fail: | |
834 | if (cmd->meta.u.skb) { | |
835 | dev_kfree_skb_any(cmd->meta.u.skb); | |
836 | cmd->meta.u.skb = NULL; | |
837 | } | |
838 | out: | |
839 | atomic_set(&entry, 0); | |
840 | return ret; | |
841 | } | |
842 | ||
bb8c093b | 843 | int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 844 | { |
b481de9c | 845 | if (cmd->meta.flags & CMD_ASYNC) |
bb8c093b | 846 | return iwl3945_send_cmd_async(priv, cmd); |
b481de9c | 847 | |
bb8c093b | 848 | return iwl3945_send_cmd_sync(priv, cmd); |
b481de9c ZY |
849 | } |
850 | ||
bb8c093b | 851 | int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data) |
b481de9c | 852 | { |
bb8c093b | 853 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
854 | .id = id, |
855 | .len = len, | |
856 | .data = data, | |
857 | }; | |
858 | ||
bb8c093b | 859 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
860 | } |
861 | ||
bb8c093b | 862 | static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val) |
b481de9c | 863 | { |
bb8c093b | 864 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
865 | .id = id, |
866 | .len = sizeof(val), | |
867 | .data = &val, | |
868 | }; | |
869 | ||
bb8c093b | 870 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
871 | } |
872 | ||
bb8c093b | 873 | int iwl3945_send_statistics_request(struct iwl3945_priv *priv) |
b481de9c | 874 | { |
bb8c093b | 875 | return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0); |
b481de9c ZY |
876 | } |
877 | ||
b481de9c | 878 | /** |
bb8c093b | 879 | * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON |
8318d78a JB |
880 | * @band: 2.4 or 5 GHz band |
881 | * @channel: Any channel valid for the requested band | |
b481de9c | 882 | |
8318d78a | 883 | * In addition to setting the staging RXON, priv->band is also set. |
b481de9c ZY |
884 | * |
885 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
8318d78a | 886 | * in the staging RXON flag structure based on the band |
b481de9c | 887 | */ |
8318d78a JB |
888 | static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, |
889 | enum ieee80211_band band, | |
890 | u16 channel) | |
b481de9c | 891 | { |
8318d78a | 892 | if (!iwl3945_get_channel_info(priv, band, channel)) { |
b481de9c | 893 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
8318d78a | 894 | channel, band); |
b481de9c ZY |
895 | return -EINVAL; |
896 | } | |
897 | ||
898 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
8318d78a | 899 | (priv->band == band)) |
b481de9c ZY |
900 | return 0; |
901 | ||
902 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
8318d78a | 903 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
904 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
905 | else | |
906 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
907 | ||
8318d78a | 908 | priv->band = band; |
b481de9c | 909 | |
8318d78a | 910 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); |
b481de9c ZY |
911 | |
912 | return 0; | |
913 | } | |
914 | ||
915 | /** | |
bb8c093b | 916 | * iwl3945_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
917 | * |
918 | * NOTE: This is really only useful during development and can eventually | |
919 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
920 | * making changes | |
921 | */ | |
bb8c093b | 922 | static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon) |
b481de9c ZY |
923 | { |
924 | int error = 0; | |
925 | int counter = 1; | |
926 | ||
927 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
928 | error |= le32_to_cpu(rxon->flags & | |
929 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
930 | RXON_FLG_RADAR_DETECT_MSK)); | |
931 | if (error) | |
932 | IWL_WARNING("check 24G fields %d | %d\n", | |
933 | counter++, error); | |
934 | } else { | |
935 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
936 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
937 | if (error) | |
938 | IWL_WARNING("check 52 fields %d | %d\n", | |
939 | counter++, error); | |
940 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
941 | if (error) | |
942 | IWL_WARNING("check 52 CCK %d | %d\n", | |
943 | counter++, error); | |
944 | } | |
945 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
946 | if (error) | |
947 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
948 | ||
949 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
950 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
951 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
952 | if (error) | |
953 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
954 | ||
955 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
956 | if (error) | |
957 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
958 | ||
959 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
960 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
961 | if (error) | |
962 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
963 | counter++, error); | |
964 | ||
965 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
966 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
967 | if (error) | |
968 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
969 | counter++, error); | |
970 | ||
971 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
972 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
973 | if (error) | |
974 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
975 | counter++, error); | |
976 | ||
977 | if ((rxon->flags & RXON_FLG_DIS_DIV_MSK)) | |
978 | error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK | | |
979 | RXON_FLG_ANT_A_MSK)) == 0); | |
980 | if (error) | |
981 | IWL_WARNING("check antenna %d %d\n", counter++, error); | |
982 | ||
983 | if (error) | |
984 | IWL_WARNING("Tuning to channel %d\n", | |
985 | le16_to_cpu(rxon->channel)); | |
986 | ||
987 | if (error) { | |
bb8c093b | 988 | IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
989 | return -1; |
990 | } | |
991 | return 0; | |
992 | } | |
993 | ||
994 | /** | |
9fbab516 | 995 | * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 996 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 997 | * |
9fbab516 BC |
998 | * If the RXON structure is changing enough to require a new tune, |
999 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
1000 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 1001 | */ |
bb8c093b | 1002 | static int iwl3945_full_rxon_required(struct iwl3945_priv *priv) |
b481de9c ZY |
1003 | { |
1004 | ||
1005 | /* These items are only settable from the full RXON command */ | |
1006 | if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || | |
1007 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
1008 | priv->active_rxon.bssid_addr) || | |
1009 | compare_ether_addr(priv->staging_rxon.node_addr, | |
1010 | priv->active_rxon.node_addr) || | |
1011 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
1012 | priv->active_rxon.wlap_bssid_addr) || | |
1013 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
1014 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
1015 | (priv->staging_rxon.air_propagation != | |
1016 | priv->active_rxon.air_propagation) || | |
1017 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) | |
1018 | return 1; | |
1019 | ||
1020 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
1021 | * be updated with the RXON_ASSOC command -- however only some | |
1022 | * flag transitions are allowed using RXON_ASSOC */ | |
1023 | ||
1024 | /* Check if we are not switching bands */ | |
1025 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
1026 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
1027 | return 1; | |
1028 | ||
1029 | /* Check if we are switching association toggle */ | |
1030 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
1031 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
1032 | return 1; | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
bb8c093b | 1037 | static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv) |
b481de9c ZY |
1038 | { |
1039 | int rc = 0; | |
bb8c093b CH |
1040 | struct iwl3945_rx_packet *res = NULL; |
1041 | struct iwl3945_rxon_assoc_cmd rxon_assoc; | |
1042 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
1043 | .id = REPLY_RXON_ASSOC, |
1044 | .len = sizeof(rxon_assoc), | |
1045 | .meta.flags = CMD_WANT_SKB, | |
1046 | .data = &rxon_assoc, | |
1047 | }; | |
bb8c093b CH |
1048 | const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon; |
1049 | const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon; | |
b481de9c ZY |
1050 | |
1051 | if ((rxon1->flags == rxon2->flags) && | |
1052 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1053 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1054 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1055 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1060 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1061 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1062 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1063 | rxon_assoc.reserved = 0; | |
1064 | ||
bb8c093b | 1065 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1066 | if (rc) |
1067 | return rc; | |
1068 | ||
bb8c093b | 1069 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1070 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1071 | IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n"); | |
1072 | rc = -EIO; | |
1073 | } | |
1074 | ||
1075 | priv->alloc_rxb_skb--; | |
1076 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1077 | ||
1078 | return rc; | |
1079 | } | |
1080 | ||
1081 | /** | |
bb8c093b | 1082 | * iwl3945_commit_rxon - commit staging_rxon to hardware |
b481de9c | 1083 | * |
01ebd063 | 1084 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
1085 | * the active_rxon structure is updated with the new data. This |
1086 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
1087 | * a HW tune is required based on the RXON structure changes. | |
1088 | */ | |
bb8c093b | 1089 | static int iwl3945_commit_rxon(struct iwl3945_priv *priv) |
b481de9c ZY |
1090 | { |
1091 | /* cast away the const for active_rxon in this function */ | |
bb8c093b | 1092 | struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
b481de9c | 1093 | int rc = 0; |
0795af57 | 1094 | DECLARE_MAC_BUF(mac); |
b481de9c | 1095 | |
bb8c093b | 1096 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
1097 | return -1; |
1098 | ||
1099 | /* always get timestamp with Rx frame */ | |
1100 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
1101 | ||
1102 | /* select antenna */ | |
1103 | priv->staging_rxon.flags &= | |
1104 | ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); | |
1105 | priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv); | |
1106 | ||
bb8c093b | 1107 | rc = iwl3945_check_rxon_cmd(&priv->staging_rxon); |
b481de9c ZY |
1108 | if (rc) { |
1109 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
1110 | return -EINVAL; | |
1111 | } | |
1112 | ||
1113 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 1114 | * iwl3945_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 1115 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
1116 | if (!iwl3945_full_rxon_required(priv)) { |
1117 | rc = iwl3945_send_rxon_assoc(priv); | |
b481de9c ZY |
1118 | if (rc) { |
1119 | IWL_ERROR("Error setting RXON_ASSOC " | |
1120 | "configuration (%d).\n", rc); | |
1121 | return rc; | |
1122 | } | |
1123 | ||
1124 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | /* If we are currently associated and the new config requires | |
1130 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
1131 | * we must clear the associated from the active configuration | |
1132 | * before we apply the new config */ | |
bb8c093b | 1133 | if (iwl3945_is_associated(priv) && |
b481de9c ZY |
1134 | (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
1135 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); | |
1136 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
1137 | ||
bb8c093b CH |
1138 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
1139 | sizeof(struct iwl3945_rxon_cmd), | |
b481de9c ZY |
1140 | &priv->active_rxon); |
1141 | ||
1142 | /* If the mask clearing failed then we set | |
1143 | * active_rxon back to what it was previously */ | |
1144 | if (rc) { | |
1145 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
1146 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
1147 | "configuration (%d).\n", rc); | |
1148 | return rc; | |
1149 | } | |
b481de9c ZY |
1150 | } |
1151 | ||
1152 | IWL_DEBUG_INFO("Sending RXON\n" | |
1153 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
1154 | "* channel = %d\n" | |
0795af57 | 1155 | "* bssid = %s\n", |
b481de9c ZY |
1156 | ((priv->staging_rxon.filter_flags & |
1157 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), | |
1158 | le16_to_cpu(priv->staging_rxon.channel), | |
0795af57 | 1159 | print_mac(mac, priv->staging_rxon.bssid_addr)); |
b481de9c ZY |
1160 | |
1161 | /* Apply the new configuration */ | |
bb8c093b CH |
1162 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
1163 | sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon); | |
b481de9c ZY |
1164 | if (rc) { |
1165 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
1166 | return rc; | |
1167 | } | |
1168 | ||
1169 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
1170 | ||
bb8c093b | 1171 | iwl3945_clear_stations_table(priv); |
556f8db7 | 1172 | |
b481de9c ZY |
1173 | /* If we issue a new RXON command which required a tune then we must |
1174 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 1175 | rc = iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
1176 | if (rc) { |
1177 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
1178 | return rc; | |
1179 | } | |
1180 | ||
1181 | /* Add the broadcast address so we can send broadcast frames */ | |
bb8c093b | 1182 | if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) == |
b481de9c ZY |
1183 | IWL_INVALID_STATION) { |
1184 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
1185 | return -EIO; | |
1186 | } | |
1187 | ||
1188 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
1189 | * add the IWL_AP_ID to the station rate table */ | |
bb8c093b | 1190 | if (iwl3945_is_associated(priv) && |
b481de9c | 1191 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) |
bb8c093b | 1192 | if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0) |
b481de9c ZY |
1193 | == IWL_INVALID_STATION) { |
1194 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
1195 | return -EIO; | |
1196 | } | |
1197 | ||
8318d78a | 1198 | /* Init the hardware's rate fallback order based on the band */ |
b481de9c ZY |
1199 | rc = iwl3945_init_hw_rate_table(priv); |
1200 | if (rc) { | |
1201 | IWL_ERROR("Error setting HW rate table: %02X\n", rc); | |
1202 | return -EIO; | |
1203 | } | |
1204 | ||
1205 | return 0; | |
1206 | } | |
1207 | ||
bb8c093b | 1208 | static int iwl3945_send_bt_config(struct iwl3945_priv *priv) |
b481de9c | 1209 | { |
bb8c093b | 1210 | struct iwl3945_bt_cmd bt_cmd = { |
b481de9c ZY |
1211 | .flags = 3, |
1212 | .lead_time = 0xAA, | |
1213 | .max_kill = 1, | |
1214 | .kill_ack_mask = 0, | |
1215 | .kill_cts_mask = 0, | |
1216 | }; | |
1217 | ||
bb8c093b CH |
1218 | return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
1219 | sizeof(struct iwl3945_bt_cmd), &bt_cmd); | |
b481de9c ZY |
1220 | } |
1221 | ||
bb8c093b | 1222 | static int iwl3945_send_scan_abort(struct iwl3945_priv *priv) |
b481de9c ZY |
1223 | { |
1224 | int rc = 0; | |
bb8c093b CH |
1225 | struct iwl3945_rx_packet *res; |
1226 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
1227 | .id = REPLY_SCAN_ABORT_CMD, |
1228 | .meta.flags = CMD_WANT_SKB, | |
1229 | }; | |
1230 | ||
1231 | /* If there isn't a scan actively going on in the hardware | |
1232 | * then we are in between scan bands and not actually | |
1233 | * actively scanning, so don't send the abort command */ | |
1234 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1235 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1236 | return 0; | |
1237 | } | |
1238 | ||
bb8c093b | 1239 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1240 | if (rc) { |
1241 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1242 | return rc; | |
1243 | } | |
1244 | ||
bb8c093b | 1245 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1246 | if (res->u.status != CAN_ABORT_STATUS) { |
1247 | /* The scan abort will return 1 for success or | |
1248 | * 2 for "failure". A failure condition can be | |
1249 | * due to simply not being in an active scan which | |
1250 | * can occur if we send the scan abort before we | |
1251 | * the microcode has notified us that a scan is | |
1252 | * completed. */ | |
1253 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
1254 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1255 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
1256 | } | |
1257 | ||
1258 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1259 | ||
1260 | return rc; | |
1261 | } | |
1262 | ||
bb8c093b CH |
1263 | static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv, |
1264 | struct iwl3945_cmd *cmd, | |
b481de9c ZY |
1265 | struct sk_buff *skb) |
1266 | { | |
1267 | return 1; | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * CARD_STATE_CMD | |
1272 | * | |
9fbab516 | 1273 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
1274 | * |
1275 | * When in the 'enable' state the card operates as normal. | |
1276 | * When in the 'disable' state, the card enters into a low power mode. | |
1277 | * When in the 'halt' state, the card is shut down and must be fully | |
1278 | * restarted to come back on. | |
1279 | */ | |
bb8c093b | 1280 | static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1281 | { |
bb8c093b | 1282 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
1283 | .id = REPLY_CARD_STATE_CMD, |
1284 | .len = sizeof(u32), | |
1285 | .data = &flags, | |
1286 | .meta.flags = meta_flag, | |
1287 | }; | |
1288 | ||
1289 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1290 | cmd.meta.u.callback = iwl3945_card_state_sync_callback; |
b481de9c | 1291 | |
bb8c093b | 1292 | return iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1293 | } |
1294 | ||
bb8c093b CH |
1295 | static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv, |
1296 | struct iwl3945_cmd *cmd, struct sk_buff *skb) | |
b481de9c | 1297 | { |
bb8c093b | 1298 | struct iwl3945_rx_packet *res = NULL; |
b481de9c ZY |
1299 | |
1300 | if (!skb) { | |
1301 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1302 | return 1; | |
1303 | } | |
1304 | ||
bb8c093b | 1305 | res = (struct iwl3945_rx_packet *)skb->data; |
b481de9c ZY |
1306 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1307 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1308 | res->hdr.flags); | |
1309 | return 1; | |
1310 | } | |
1311 | ||
1312 | switch (res->u.add_sta.status) { | |
1313 | case ADD_STA_SUCCESS_MSK: | |
1314 | break; | |
1315 | default: | |
1316 | break; | |
1317 | } | |
1318 | ||
1319 | /* We didn't cache the SKB; let the caller free it */ | |
1320 | return 1; | |
1321 | } | |
1322 | ||
bb8c093b CH |
1323 | int iwl3945_send_add_station(struct iwl3945_priv *priv, |
1324 | struct iwl3945_addsta_cmd *sta, u8 flags) | |
b481de9c | 1325 | { |
bb8c093b | 1326 | struct iwl3945_rx_packet *res = NULL; |
b481de9c | 1327 | int rc = 0; |
bb8c093b | 1328 | struct iwl3945_host_cmd cmd = { |
b481de9c | 1329 | .id = REPLY_ADD_STA, |
bb8c093b | 1330 | .len = sizeof(struct iwl3945_addsta_cmd), |
b481de9c ZY |
1331 | .meta.flags = flags, |
1332 | .data = sta, | |
1333 | }; | |
1334 | ||
1335 | if (flags & CMD_ASYNC) | |
bb8c093b | 1336 | cmd.meta.u.callback = iwl3945_add_sta_sync_callback; |
b481de9c ZY |
1337 | else |
1338 | cmd.meta.flags |= CMD_WANT_SKB; | |
1339 | ||
bb8c093b | 1340 | rc = iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1341 | |
1342 | if (rc || (flags & CMD_ASYNC)) | |
1343 | return rc; | |
1344 | ||
bb8c093b | 1345 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1346 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1347 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1348 | res->hdr.flags); | |
1349 | rc = -EIO; | |
1350 | } | |
1351 | ||
1352 | if (rc == 0) { | |
1353 | switch (res->u.add_sta.status) { | |
1354 | case ADD_STA_SUCCESS_MSK: | |
1355 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1356 | break; | |
1357 | default: | |
1358 | rc = -EIO; | |
1359 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1360 | break; | |
1361 | } | |
1362 | } | |
1363 | ||
1364 | priv->alloc_rxb_skb--; | |
1365 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1366 | ||
1367 | return rc; | |
1368 | } | |
1369 | ||
bb8c093b | 1370 | static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv, |
b481de9c ZY |
1371 | struct ieee80211_key_conf *keyconf, |
1372 | u8 sta_id) | |
1373 | { | |
1374 | unsigned long flags; | |
1375 | __le16 key_flags = 0; | |
1376 | ||
1377 | switch (keyconf->alg) { | |
1378 | case ALG_CCMP: | |
1379 | key_flags |= STA_KEY_FLG_CCMP; | |
1380 | key_flags |= cpu_to_le16( | |
1381 | keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
1382 | key_flags &= ~STA_KEY_FLG_INVALID; | |
1383 | break; | |
1384 | case ALG_TKIP: | |
1385 | case ALG_WEP: | |
b481de9c ZY |
1386 | default: |
1387 | return -EINVAL; | |
1388 | } | |
1389 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1390 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; | |
1391 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
1392 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
1393 | keyconf->keylen); | |
1394 | ||
1395 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, | |
1396 | keyconf->keylen); | |
1397 | priv->stations[sta_id].sta.key.key_flags = key_flags; | |
1398 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1399 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1400 | ||
1401 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1402 | ||
1403 | IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); | |
bb8c093b | 1404 | iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1405 | return 0; |
1406 | } | |
1407 | ||
bb8c093b | 1408 | static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id) |
b481de9c ZY |
1409 | { |
1410 | unsigned long flags; | |
1411 | ||
1412 | spin_lock_irqsave(&priv->sta_lock, flags); | |
bb8c093b CH |
1413 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key)); |
1414 | memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo)); | |
b481de9c ZY |
1415 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
1416 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1417 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1418 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1419 | ||
1420 | IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); | |
bb8c093b | 1421 | iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1422 | return 0; |
1423 | } | |
1424 | ||
bb8c093b | 1425 | static void iwl3945_clear_free_frames(struct iwl3945_priv *priv) |
b481de9c ZY |
1426 | { |
1427 | struct list_head *element; | |
1428 | ||
1429 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1430 | priv->frames_count); | |
1431 | ||
1432 | while (!list_empty(&priv->free_frames)) { | |
1433 | element = priv->free_frames.next; | |
1434 | list_del(element); | |
bb8c093b | 1435 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
1436 | priv->frames_count--; |
1437 | } | |
1438 | ||
1439 | if (priv->frames_count) { | |
1440 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1441 | priv->frames_count); | |
1442 | priv->frames_count = 0; | |
1443 | } | |
1444 | } | |
1445 | ||
bb8c093b | 1446 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv) |
b481de9c | 1447 | { |
bb8c093b | 1448 | struct iwl3945_frame *frame; |
b481de9c ZY |
1449 | struct list_head *element; |
1450 | if (list_empty(&priv->free_frames)) { | |
1451 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1452 | if (!frame) { | |
1453 | IWL_ERROR("Could not allocate frame!\n"); | |
1454 | return NULL; | |
1455 | } | |
1456 | ||
1457 | priv->frames_count++; | |
1458 | return frame; | |
1459 | } | |
1460 | ||
1461 | element = priv->free_frames.next; | |
1462 | list_del(element); | |
bb8c093b | 1463 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
1464 | } |
1465 | ||
bb8c093b | 1466 | static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
1467 | { |
1468 | memset(frame, 0, sizeof(*frame)); | |
1469 | list_add(&frame->list, &priv->free_frames); | |
1470 | } | |
1471 | ||
bb8c093b | 1472 | unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv, |
b481de9c ZY |
1473 | struct ieee80211_hdr *hdr, |
1474 | const u8 *dest, int left) | |
1475 | { | |
1476 | ||
bb8c093b | 1477 | if (!iwl3945_is_associated(priv) || !priv->ibss_beacon || |
b481de9c ZY |
1478 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && |
1479 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) | |
1480 | return 0; | |
1481 | ||
1482 | if (priv->ibss_beacon->len > left) | |
1483 | return 0; | |
1484 | ||
1485 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1486 | ||
1487 | return priv->ibss_beacon->len; | |
1488 | } | |
1489 | ||
bb8c093b | 1490 | static u8 iwl3945_rate_get_lowest_plcp(int rate_mask) |
b481de9c ZY |
1491 | { |
1492 | u8 i; | |
1493 | ||
1494 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1495 | i = iwl3945_rates[i].next_ieee) { |
b481de9c | 1496 | if (rate_mask & (1 << i)) |
bb8c093b | 1497 | return iwl3945_rates[i].plcp; |
b481de9c ZY |
1498 | } |
1499 | ||
1500 | return IWL_RATE_INVALID; | |
1501 | } | |
1502 | ||
bb8c093b | 1503 | static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv) |
b481de9c | 1504 | { |
bb8c093b | 1505 | struct iwl3945_frame *frame; |
b481de9c ZY |
1506 | unsigned int frame_size; |
1507 | int rc; | |
1508 | u8 rate; | |
1509 | ||
bb8c093b | 1510 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
1511 | |
1512 | if (!frame) { | |
1513 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1514 | "command.\n"); | |
1515 | return -ENOMEM; | |
1516 | } | |
1517 | ||
1518 | if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { | |
bb8c093b | 1519 | rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & |
b481de9c ZY |
1520 | 0xFF0); |
1521 | if (rate == IWL_INVALID_RATE) | |
1522 | rate = IWL_RATE_6M_PLCP; | |
1523 | } else { | |
bb8c093b | 1524 | rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF); |
b481de9c ZY |
1525 | if (rate == IWL_INVALID_RATE) |
1526 | rate = IWL_RATE_1M_PLCP; | |
1527 | } | |
1528 | ||
bb8c093b | 1529 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1530 | |
bb8c093b | 1531 | rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1532 | &frame->u.cmd[0]); |
1533 | ||
bb8c093b | 1534 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
1535 | |
1536 | return rc; | |
1537 | } | |
1538 | ||
1539 | /****************************************************************************** | |
1540 | * | |
1541 | * EEPROM related functions | |
1542 | * | |
1543 | ******************************************************************************/ | |
1544 | ||
bb8c093b | 1545 | static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac) |
b481de9c ZY |
1546 | { |
1547 | memcpy(mac, priv->eeprom.mac_address, 6); | |
1548 | } | |
1549 | ||
74a3a250 RC |
1550 | /* |
1551 | * Clear the OWNER_MSK, to establish driver (instead of uCode running on | |
1552 | * embedded controller) as EEPROM reader; each read is a series of pulses | |
1553 | * to/from the EEPROM chip, not a single event, so even reads could conflict | |
1554 | * if they weren't arbitrated by some ownership mechanism. Here, the driver | |
1555 | * simply claims ownership, which should be safe when this function is called | |
1556 | * (i.e. before loading uCode!). | |
1557 | */ | |
1558 | static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv) | |
1559 | { | |
1560 | _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); | |
1561 | return 0; | |
1562 | } | |
1563 | ||
b481de9c | 1564 | /** |
bb8c093b | 1565 | * iwl3945_eeprom_init - read EEPROM contents |
b481de9c | 1566 | * |
6440adb5 | 1567 | * Load the EEPROM contents from adapter into priv->eeprom |
b481de9c ZY |
1568 | * |
1569 | * NOTE: This routine uses the non-debug IO access functions. | |
1570 | */ | |
bb8c093b | 1571 | int iwl3945_eeprom_init(struct iwl3945_priv *priv) |
b481de9c | 1572 | { |
58ff6d4d | 1573 | u16 *e = (u16 *)&priv->eeprom; |
bb8c093b | 1574 | u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP); |
b481de9c ZY |
1575 | u32 r; |
1576 | int sz = sizeof(priv->eeprom); | |
1577 | int rc; | |
1578 | int i; | |
1579 | u16 addr; | |
1580 | ||
1581 | /* The EEPROM structure has several padding buffers within it | |
1582 | * and when adding new EEPROM maps is subject to programmer errors | |
1583 | * which may be very difficult to identify without explicitly | |
1584 | * checking the resulting size of the eeprom map. */ | |
1585 | BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE); | |
1586 | ||
1587 | if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { | |
1588 | IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); | |
1589 | return -ENOENT; | |
1590 | } | |
1591 | ||
6440adb5 | 1592 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ |
bb8c093b | 1593 | rc = iwl3945_eeprom_acquire_semaphore(priv); |
b481de9c | 1594 | if (rc < 0) { |
91e17473 | 1595 | IWL_ERROR("Failed to acquire EEPROM semaphore.\n"); |
b481de9c ZY |
1596 | return -ENOENT; |
1597 | } | |
1598 | ||
1599 | /* eeprom is an array of 16bit values */ | |
1600 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
bb8c093b CH |
1601 | _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1); |
1602 | _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); | |
b481de9c ZY |
1603 | |
1604 | for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; | |
1605 | i += IWL_EEPROM_ACCESS_DELAY) { | |
bb8c093b | 1606 | r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG); |
b481de9c ZY |
1607 | if (r & CSR_EEPROM_REG_READ_VALID_MSK) |
1608 | break; | |
1609 | udelay(IWL_EEPROM_ACCESS_DELAY); | |
1610 | } | |
1611 | ||
1612 | if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { | |
1613 | IWL_ERROR("Time out reading EEPROM[%d]", addr); | |
1614 | return -ETIMEDOUT; | |
1615 | } | |
58ff6d4d | 1616 | e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); |
b481de9c ZY |
1617 | } |
1618 | ||
1619 | return 0; | |
1620 | } | |
1621 | ||
bb8c093b | 1622 | static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv) |
b481de9c ZY |
1623 | { |
1624 | if (priv->hw_setting.shared_virt) | |
1625 | pci_free_consistent(priv->pci_dev, | |
bb8c093b | 1626 | sizeof(struct iwl3945_shared), |
b481de9c ZY |
1627 | priv->hw_setting.shared_virt, |
1628 | priv->hw_setting.shared_phys); | |
1629 | } | |
1630 | ||
1631 | /** | |
bb8c093b | 1632 | * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1633 | * |
1634 | * return : set the bit for each supported rate insert in ie | |
1635 | */ | |
bb8c093b | 1636 | static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1637 | u16 basic_rate, int *left) |
b481de9c ZY |
1638 | { |
1639 | u16 ret_rates = 0, bit; | |
1640 | int i; | |
c7c46676 TW |
1641 | u8 *cnt = ie; |
1642 | u8 *rates = ie + 1; | |
b481de9c ZY |
1643 | |
1644 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1645 | if (bit & supported_rate) { | |
1646 | ret_rates |= bit; | |
bb8c093b | 1647 | rates[*cnt] = iwl3945_rates[i].ieee | |
c7c46676 TW |
1648 | ((bit & basic_rate) ? 0x80 : 0x00); |
1649 | (*cnt)++; | |
1650 | (*left)--; | |
1651 | if ((*left <= 0) || | |
1652 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1653 | break; |
1654 | } | |
1655 | } | |
1656 | ||
1657 | return ret_rates; | |
1658 | } | |
1659 | ||
1660 | /** | |
bb8c093b | 1661 | * iwl3945_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1662 | */ |
bb8c093b | 1663 | static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv, |
b481de9c ZY |
1664 | struct ieee80211_mgmt *frame, |
1665 | int left, int is_direct) | |
1666 | { | |
1667 | int len = 0; | |
1668 | u8 *pos = NULL; | |
c7c46676 | 1669 | u16 active_rates, ret_rates, cck_rates; |
b481de9c ZY |
1670 | |
1671 | /* Make sure there is enough space for the probe request, | |
1672 | * two mandatory IEs and the data */ | |
1673 | left -= 24; | |
1674 | if (left < 0) | |
1675 | return 0; | |
1676 | len += 24; | |
1677 | ||
1678 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
bb8c093b | 1679 | memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN); |
b481de9c | 1680 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
bb8c093b | 1681 | memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN); |
b481de9c ZY |
1682 | frame->seq_ctrl = 0; |
1683 | ||
1684 | /* fill in our indirect SSID IE */ | |
1685 | /* ...next IE... */ | |
1686 | ||
1687 | left -= 2; | |
1688 | if (left < 0) | |
1689 | return 0; | |
1690 | len += 2; | |
1691 | pos = &(frame->u.probe_req.variable[0]); | |
1692 | *pos++ = WLAN_EID_SSID; | |
1693 | *pos++ = 0; | |
1694 | ||
1695 | /* fill in our direct SSID IE... */ | |
1696 | if (is_direct) { | |
1697 | /* ...next IE... */ | |
1698 | left -= 2 + priv->essid_len; | |
1699 | if (left < 0) | |
1700 | return 0; | |
1701 | /* ... fill it in... */ | |
1702 | *pos++ = WLAN_EID_SSID; | |
1703 | *pos++ = priv->essid_len; | |
1704 | memcpy(pos, priv->essid, priv->essid_len); | |
1705 | pos += priv->essid_len; | |
1706 | len += 2 + priv->essid_len; | |
1707 | } | |
1708 | ||
1709 | /* fill in supported rate */ | |
1710 | /* ...next IE... */ | |
1711 | left -= 2; | |
1712 | if (left < 0) | |
1713 | return 0; | |
c7c46676 | 1714 | |
b481de9c ZY |
1715 | /* ... fill it in... */ |
1716 | *pos++ = WLAN_EID_SUPP_RATES; | |
1717 | *pos = 0; | |
c7c46676 TW |
1718 | |
1719 | priv->active_rate = priv->rates_mask; | |
1720 | active_rates = priv->active_rate; | |
b481de9c ZY |
1721 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; |
1722 | ||
c7c46676 | 1723 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1724 | ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates, |
c7c46676 TW |
1725 | priv->active_rate_basic, &left); |
1726 | active_rates &= ~ret_rates; | |
1727 | ||
bb8c093b | 1728 | ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 TW |
1729 | priv->active_rate_basic, &left); |
1730 | active_rates &= ~ret_rates; | |
1731 | ||
b481de9c ZY |
1732 | len += 2 + *pos; |
1733 | pos += (*pos) + 1; | |
c7c46676 | 1734 | if (active_rates == 0) |
b481de9c ZY |
1735 | goto fill_end; |
1736 | ||
1737 | /* fill in supported extended rate */ | |
1738 | /* ...next IE... */ | |
1739 | left -= 2; | |
1740 | if (left < 0) | |
1741 | return 0; | |
1742 | /* ... fill it in... */ | |
1743 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1744 | *pos = 0; | |
bb8c093b | 1745 | iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 | 1746 | priv->active_rate_basic, &left); |
b481de9c ZY |
1747 | if (*pos > 0) |
1748 | len += 2 + *pos; | |
1749 | ||
1750 | fill_end: | |
1751 | return (u16)len; | |
1752 | } | |
1753 | ||
1754 | /* | |
1755 | * QoS support | |
1756 | */ | |
bb8c093b CH |
1757 | static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv, |
1758 | struct iwl3945_qosparam_cmd *qos) | |
b481de9c ZY |
1759 | { |
1760 | ||
bb8c093b CH |
1761 | return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
1762 | sizeof(struct iwl3945_qosparam_cmd), qos); | |
b481de9c ZY |
1763 | } |
1764 | ||
bb8c093b | 1765 | static void iwl3945_reset_qos(struct iwl3945_priv *priv) |
b481de9c ZY |
1766 | { |
1767 | u16 cw_min = 15; | |
1768 | u16 cw_max = 1023; | |
1769 | u8 aifs = 2; | |
1770 | u8 is_legacy = 0; | |
1771 | unsigned long flags; | |
1772 | int i; | |
1773 | ||
1774 | spin_lock_irqsave(&priv->lock, flags); | |
1775 | priv->qos_data.qos_active = 0; | |
1776 | ||
1777 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) { | |
1778 | if (priv->qos_data.qos_enable) | |
1779 | priv->qos_data.qos_active = 1; | |
1780 | if (!(priv->active_rate & 0xfff0)) { | |
1781 | cw_min = 31; | |
1782 | is_legacy = 1; | |
1783 | } | |
1784 | } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
1785 | if (priv->qos_data.qos_enable) | |
1786 | priv->qos_data.qos_active = 1; | |
1787 | } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
1788 | cw_min = 31; | |
1789 | is_legacy = 1; | |
1790 | } | |
1791 | ||
1792 | if (priv->qos_data.qos_active) | |
1793 | aifs = 3; | |
1794 | ||
1795 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); | |
1796 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
1797 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
1798 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
1799 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
1800 | ||
1801 | if (priv->qos_data.qos_active) { | |
1802 | i = 1; | |
1803 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
1804 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
1805 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
1806 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1807 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1808 | ||
1809 | i = 2; | |
1810 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1811 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
1812 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1813 | cpu_to_le16(cw_max); | |
1814 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1815 | if (is_legacy) | |
1816 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1817 | cpu_to_le16(6016); | |
1818 | else | |
1819 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1820 | cpu_to_le16(3008); | |
1821 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1822 | ||
1823 | i = 3; | |
1824 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1825 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
1826 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1827 | cpu_to_le16((cw_max + 1) / 2 - 1); | |
1828 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1829 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1830 | if (is_legacy) | |
1831 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1832 | cpu_to_le16(3264); | |
1833 | else | |
1834 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1835 | cpu_to_le16(1504); | |
1836 | } else { | |
1837 | for (i = 1; i < 4; i++) { | |
1838 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1839 | cpu_to_le16(cw_min); | |
1840 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1841 | cpu_to_le16(cw_max); | |
1842 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
1843 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1844 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1845 | } | |
1846 | } | |
1847 | IWL_DEBUG_QOS("set QoS to default \n"); | |
1848 | ||
1849 | spin_unlock_irqrestore(&priv->lock, flags); | |
1850 | } | |
1851 | ||
bb8c093b | 1852 | static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force) |
b481de9c ZY |
1853 | { |
1854 | unsigned long flags; | |
1855 | ||
b481de9c ZY |
1856 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1857 | return; | |
1858 | ||
1859 | if (!priv->qos_data.qos_enable) | |
1860 | return; | |
1861 | ||
1862 | spin_lock_irqsave(&priv->lock, flags); | |
1863 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1864 | ||
1865 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1866 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1867 | priv->qos_data.def_qos_parm.qos_flags |= | |
1868 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
1869 | ||
1870 | if (priv->qos_data.qos_active) | |
1871 | priv->qos_data.def_qos_parm.qos_flags |= | |
1872 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1873 | ||
1874 | spin_unlock_irqrestore(&priv->lock, flags); | |
1875 | ||
bb8c093b | 1876 | if (force || iwl3945_is_associated(priv)) { |
b481de9c ZY |
1877 | IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n", |
1878 | priv->qos_data.qos_active); | |
1879 | ||
bb8c093b | 1880 | iwl3945_send_qos_params_command(priv, |
b481de9c ZY |
1881 | &(priv->qos_data.def_qos_parm)); |
1882 | } | |
1883 | } | |
1884 | ||
b481de9c ZY |
1885 | /* |
1886 | * Power management (not Tx power!) functions | |
1887 | */ | |
1888 | #define MSEC_TO_USEC 1024 | |
1889 | ||
1890 | #define NOSLP __constant_cpu_to_le32(0) | |
1891 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK | |
1892 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) | |
1893 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1894 | __constant_cpu_to_le32(X1), \ | |
1895 | __constant_cpu_to_le32(X2), \ | |
1896 | __constant_cpu_to_le32(X3), \ | |
1897 | __constant_cpu_to_le32(X4)} | |
1898 | ||
1899 | ||
1900 | /* default power management (not Tx power) table values */ | |
1901 | /* for tim 0-10 */ | |
bb8c093b | 1902 | static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = { |
b481de9c ZY |
1903 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1904 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1905 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1906 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1907 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1908 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1909 | }; | |
1910 | ||
1911 | /* for tim > 10 */ | |
bb8c093b | 1912 | static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = { |
b481de9c ZY |
1913 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1914 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1915 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1916 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1917 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1918 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1919 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1920 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1921 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1922 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1923 | }; | |
1924 | ||
bb8c093b | 1925 | int iwl3945_power_init_handle(struct iwl3945_priv *priv) |
b481de9c ZY |
1926 | { |
1927 | int rc = 0, i; | |
bb8c093b CH |
1928 | struct iwl3945_power_mgr *pow_data; |
1929 | int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC; | |
b481de9c ZY |
1930 | u16 pci_pm; |
1931 | ||
1932 | IWL_DEBUG_POWER("Initialize power \n"); | |
1933 | ||
1934 | pow_data = &(priv->power_data); | |
1935 | ||
1936 | memset(pow_data, 0, sizeof(*pow_data)); | |
1937 | ||
1938 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1939 | pow_data->dtim_val = 0xffff; | |
1940 | ||
1941 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1942 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1943 | ||
1944 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1945 | if (rc != 0) | |
1946 | return 0; | |
1947 | else { | |
bb8c093b | 1948 | struct iwl3945_powertable_cmd *cmd; |
b481de9c ZY |
1949 | |
1950 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1951 | ||
1952 | for (i = 0; i < IWL_POWER_AC; i++) { | |
1953 | cmd = &pow_data->pwr_range_0[i].cmd; | |
1954 | ||
1955 | if (pci_pm & 0x1) | |
1956 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1957 | else | |
1958 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1959 | } | |
1960 | } | |
1961 | return rc; | |
1962 | } | |
1963 | ||
bb8c093b CH |
1964 | static int iwl3945_update_power_cmd(struct iwl3945_priv *priv, |
1965 | struct iwl3945_powertable_cmd *cmd, u32 mode) | |
b481de9c ZY |
1966 | { |
1967 | int rc = 0, i; | |
1968 | u8 skip; | |
1969 | u32 max_sleep = 0; | |
bb8c093b | 1970 | struct iwl3945_power_vec_entry *range; |
b481de9c | 1971 | u8 period = 0; |
bb8c093b | 1972 | struct iwl3945_power_mgr *pow_data; |
b481de9c ZY |
1973 | |
1974 | if (mode > IWL_POWER_INDEX_5) { | |
1975 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1976 | return -1; | |
1977 | } | |
1978 | pow_data = &(priv->power_data); | |
1979 | ||
1980 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1981 | range = &pow_data->pwr_range_0[0]; | |
1982 | else | |
1983 | range = &pow_data->pwr_range_1[1]; | |
1984 | ||
bb8c093b | 1985 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd)); |
b481de9c ZY |
1986 | |
1987 | #ifdef IWL_MAC80211_DISABLE | |
1988 | if (priv->assoc_network != NULL) { | |
1989 | unsigned long flags; | |
1990 | ||
1991 | period = priv->assoc_network->tim.tim_period; | |
1992 | } | |
1993 | #endif /*IWL_MAC80211_DISABLE */ | |
1994 | skip = range[mode].no_dtim; | |
1995 | ||
1996 | if (period == 0) { | |
1997 | period = 1; | |
1998 | skip = 0; | |
1999 | } | |
2000 | ||
2001 | if (skip == 0) { | |
2002 | max_sleep = period; | |
2003 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
2004 | } else { | |
2005 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
2006 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
2007 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
2008 | } | |
2009 | ||
2010 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
2011 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
2012 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
2013 | } | |
2014 | ||
2015 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
2016 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
2017 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
2018 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
2019 | le32_to_cpu(cmd->sleep_interval[0]), | |
2020 | le32_to_cpu(cmd->sleep_interval[1]), | |
2021 | le32_to_cpu(cmd->sleep_interval[2]), | |
2022 | le32_to_cpu(cmd->sleep_interval[3]), | |
2023 | le32_to_cpu(cmd->sleep_interval[4])); | |
2024 | ||
2025 | return rc; | |
2026 | } | |
2027 | ||
bb8c093b | 2028 | static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode) |
b481de9c | 2029 | { |
9a62f73b | 2030 | u32 uninitialized_var(final_mode); |
b481de9c | 2031 | int rc; |
bb8c093b | 2032 | struct iwl3945_powertable_cmd cmd; |
b481de9c ZY |
2033 | |
2034 | /* If on battery, set to 3, | |
01ebd063 | 2035 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
2036 | * else user level */ |
2037 | switch (mode) { | |
2038 | case IWL_POWER_BATTERY: | |
2039 | final_mode = IWL_POWER_INDEX_3; | |
2040 | break; | |
2041 | case IWL_POWER_AC: | |
2042 | final_mode = IWL_POWER_MODE_CAM; | |
2043 | break; | |
2044 | default: | |
2045 | final_mode = mode; | |
2046 | break; | |
2047 | } | |
2048 | ||
bb8c093b | 2049 | iwl3945_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 2050 | |
bb8c093b | 2051 | rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
2052 | |
2053 | if (final_mode == IWL_POWER_MODE_CAM) | |
2054 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
2055 | else | |
2056 | set_bit(STATUS_POWER_PMI, &priv->status); | |
2057 | ||
2058 | return rc; | |
2059 | } | |
2060 | ||
bb8c093b | 2061 | int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2062 | { |
2063 | /* Filter incoming packets to determine if they are targeted toward | |
2064 | * this network, discarding packets coming from ourselves */ | |
2065 | switch (priv->iw_mode) { | |
2066 | case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */ | |
2067 | /* packets from our adapter are dropped (echo) */ | |
2068 | if (!compare_ether_addr(header->addr2, priv->mac_addr)) | |
2069 | return 0; | |
2070 | /* {broad,multi}cast packets to our IBSS go through */ | |
2071 | if (is_multicast_ether_addr(header->addr1)) | |
2072 | return !compare_ether_addr(header->addr3, priv->bssid); | |
2073 | /* packets to our adapter go through */ | |
2074 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
2075 | case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */ | |
2076 | /* packets from our adapter are dropped (echo) */ | |
2077 | if (!compare_ether_addr(header->addr3, priv->mac_addr)) | |
2078 | return 0; | |
2079 | /* {broad,multi}cast packets to our BSS go through */ | |
2080 | if (is_multicast_ether_addr(header->addr1)) | |
2081 | return !compare_ether_addr(header->addr2, priv->bssid); | |
2082 | /* packets to our adapter go through */ | |
2083 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
2084 | } | |
2085 | ||
2086 | return 1; | |
2087 | } | |
2088 | ||
2089 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
2090 | ||
bb8c093b | 2091 | static const char *iwl3945_get_tx_fail_reason(u32 status) |
b481de9c ZY |
2092 | { |
2093 | switch (status & TX_STATUS_MSK) { | |
2094 | case TX_STATUS_SUCCESS: | |
2095 | return "SUCCESS"; | |
2096 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
2097 | TX_STATUS_ENTRY(LONG_LIMIT); | |
2098 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
2099 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
2100 | TX_STATUS_ENTRY(NEXT_FRAG); | |
2101 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
2102 | TX_STATUS_ENTRY(DEST_PS); | |
2103 | TX_STATUS_ENTRY(ABORTED); | |
2104 | TX_STATUS_ENTRY(BT_RETRY); | |
2105 | TX_STATUS_ENTRY(STA_INVALID); | |
2106 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
2107 | TX_STATUS_ENTRY(TID_DISABLE); | |
2108 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
2109 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
2110 | TX_STATUS_ENTRY(TX_LOCKED); | |
2111 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
2112 | } | |
2113 | ||
2114 | return "UNKNOWN"; | |
2115 | } | |
2116 | ||
2117 | /** | |
bb8c093b | 2118 | * iwl3945_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
2119 | * |
2120 | * NOTE: priv->mutex is not required before calling this function | |
2121 | */ | |
bb8c093b | 2122 | static int iwl3945_scan_cancel(struct iwl3945_priv *priv) |
b481de9c ZY |
2123 | { |
2124 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
2125 | clear_bit(STATUS_SCANNING, &priv->status); | |
2126 | return 0; | |
2127 | } | |
2128 | ||
2129 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2130 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2131 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
2132 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
2133 | queue_work(priv->workqueue, &priv->abort_scan); | |
2134 | ||
2135 | } else | |
2136 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
2137 | ||
2138 | return test_bit(STATUS_SCANNING, &priv->status); | |
2139 | } | |
2140 | ||
2141 | return 0; | |
2142 | } | |
2143 | ||
2144 | /** | |
bb8c093b | 2145 | * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
2146 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
2147 | * | |
2148 | * NOTE: priv->mutex must be held before calling this function | |
2149 | */ | |
bb8c093b | 2150 | static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms) |
b481de9c ZY |
2151 | { |
2152 | unsigned long now = jiffies; | |
2153 | int ret; | |
2154 | ||
bb8c093b | 2155 | ret = iwl3945_scan_cancel(priv); |
b481de9c ZY |
2156 | if (ret && ms) { |
2157 | mutex_unlock(&priv->mutex); | |
2158 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
2159 | test_bit(STATUS_SCANNING, &priv->status)) | |
2160 | msleep(1); | |
2161 | mutex_lock(&priv->mutex); | |
2162 | ||
2163 | return test_bit(STATUS_SCANNING, &priv->status); | |
2164 | } | |
2165 | ||
2166 | return ret; | |
2167 | } | |
2168 | ||
bb8c093b | 2169 | static void iwl3945_sequence_reset(struct iwl3945_priv *priv) |
b481de9c ZY |
2170 | { |
2171 | /* Reset ieee stats */ | |
2172 | ||
2173 | /* We don't reset the net_device_stats (ieee->stats) on | |
2174 | * re-association */ | |
2175 | ||
2176 | priv->last_seq_num = -1; | |
2177 | priv->last_frag_num = -1; | |
2178 | priv->last_packet_time = 0; | |
2179 | ||
bb8c093b | 2180 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
2181 | } |
2182 | ||
2183 | #define MAX_UCODE_BEACON_INTERVAL 1024 | |
2184 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
2185 | ||
bb8c093b | 2186 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
2187 | { |
2188 | u16 new_val = 0; | |
2189 | u16 beacon_factor = 0; | |
2190 | ||
2191 | beacon_factor = | |
2192 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
2193 | / MAX_UCODE_BEACON_INTERVAL; | |
2194 | new_val = beacon_val / beacon_factor; | |
2195 | ||
2196 | return cpu_to_le16(new_val); | |
2197 | } | |
2198 | ||
bb8c093b | 2199 | static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv) |
b481de9c ZY |
2200 | { |
2201 | u64 interval_tm_unit; | |
2202 | u64 tsf, result; | |
2203 | unsigned long flags; | |
2204 | struct ieee80211_conf *conf = NULL; | |
2205 | u16 beacon_int = 0; | |
2206 | ||
2207 | conf = ieee80211_get_hw_conf(priv->hw); | |
2208 | ||
2209 | spin_lock_irqsave(&priv->lock, flags); | |
2210 | priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1); | |
2211 | priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0); | |
2212 | ||
2213 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | |
2214 | ||
2215 | tsf = priv->timestamp1; | |
2216 | tsf = ((tsf << 32) | priv->timestamp0); | |
2217 | ||
2218 | beacon_int = priv->beacon_int; | |
2219 | spin_unlock_irqrestore(&priv->lock, flags); | |
2220 | ||
2221 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) { | |
2222 | if (beacon_int == 0) { | |
2223 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
2224 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
2225 | } else { | |
2226 | priv->rxon_timing.beacon_interval = | |
2227 | cpu_to_le16(beacon_int); | |
2228 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2229 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
2230 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
2231 | } | |
2232 | ||
2233 | priv->rxon_timing.atim_window = 0; | |
2234 | } else { | |
2235 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2236 | iwl3945_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
2237 | /* TODO: we need to get atim_window from upper stack |
2238 | * for now we set to 0 */ | |
2239 | priv->rxon_timing.atim_window = 0; | |
2240 | } | |
2241 | ||
2242 | interval_tm_unit = | |
2243 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
2244 | result = do_div(tsf, interval_tm_unit); | |
2245 | priv->rxon_timing.beacon_init_val = | |
2246 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
2247 | ||
2248 | IWL_DEBUG_ASSOC | |
2249 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
2250 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
2251 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
2252 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
2253 | } | |
2254 | ||
bb8c093b | 2255 | static int iwl3945_scan_initiate(struct iwl3945_priv *priv) |
b481de9c ZY |
2256 | { |
2257 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
2258 | IWL_ERROR("APs don't scan.\n"); | |
2259 | return 0; | |
2260 | } | |
2261 | ||
bb8c093b | 2262 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
2263 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
2264 | return -EIO; | |
2265 | } | |
2266 | ||
2267 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2268 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
2269 | return -EAGAIN; | |
2270 | } | |
2271 | ||
2272 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2273 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
2274 | "Queuing.\n"); | |
2275 | return -EAGAIN; | |
2276 | } | |
2277 | ||
2278 | IWL_DEBUG_INFO("Starting scan...\n"); | |
2279 | priv->scan_bands = 2; | |
2280 | set_bit(STATUS_SCANNING, &priv->status); | |
2281 | priv->scan_start = jiffies; | |
2282 | priv->scan_pass_start = priv->scan_start; | |
2283 | ||
2284 | queue_work(priv->workqueue, &priv->request_scan); | |
2285 | ||
2286 | return 0; | |
2287 | } | |
2288 | ||
bb8c093b | 2289 | static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt) |
b481de9c | 2290 | { |
bb8c093b | 2291 | struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon; |
b481de9c ZY |
2292 | |
2293 | if (hw_decrypt) | |
2294 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
2295 | else | |
2296 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
8318d78a JB |
2301 | static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, |
2302 | enum ieee80211_band band) | |
b481de9c | 2303 | { |
8318d78a | 2304 | if (band == IEEE80211_BAND_5GHZ) { |
b481de9c ZY |
2305 | priv->staging_rxon.flags &= |
2306 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
2307 | | RXON_FLG_CCK_MSK); | |
2308 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2309 | } else { | |
bb8c093b | 2310 | /* Copied from iwl3945_bg_post_associate() */ |
b481de9c ZY |
2311 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
2312 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2313 | else | |
2314 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2315 | ||
2316 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
2317 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2318 | ||
2319 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
2320 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
2321 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
2322 | } | |
2323 | } | |
2324 | ||
2325 | /* | |
01ebd063 | 2326 | * initialize rxon structure with default values from eeprom |
b481de9c | 2327 | */ |
bb8c093b | 2328 | static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv) |
b481de9c | 2329 | { |
bb8c093b | 2330 | const struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
2331 | |
2332 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
2333 | ||
2334 | switch (priv->iw_mode) { | |
2335 | case IEEE80211_IF_TYPE_AP: | |
2336 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
2337 | break; | |
2338 | ||
2339 | case IEEE80211_IF_TYPE_STA: | |
2340 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
2341 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
2342 | break; | |
2343 | ||
2344 | case IEEE80211_IF_TYPE_IBSS: | |
2345 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
2346 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
2347 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
2348 | RXON_FILTER_ACCEPT_GRP_MSK; | |
2349 | break; | |
2350 | ||
2351 | case IEEE80211_IF_TYPE_MNTR: | |
2352 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; | |
2353 | priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
2354 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
2355 | break; | |
2356 | } | |
2357 | ||
2358 | #if 0 | |
2359 | /* TODO: Figure out when short_preamble would be set and cache from | |
2360 | * that */ | |
2361 | if (!hw_to_local(priv->hw)->short_preamble) | |
2362 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2363 | else | |
2364 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2365 | #endif | |
2366 | ||
8318d78a | 2367 | ch_info = iwl3945_get_channel_info(priv, priv->band, |
b481de9c ZY |
2368 | le16_to_cpu(priv->staging_rxon.channel)); |
2369 | ||
2370 | if (!ch_info) | |
2371 | ch_info = &priv->channel_info[0]; | |
2372 | ||
2373 | /* | |
2374 | * in some case A channels are all non IBSS | |
2375 | * in this case force B/G channel | |
2376 | */ | |
2377 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | |
2378 | !(is_channel_ibss(ch_info))) | |
2379 | ch_info = &priv->channel_info[0]; | |
2380 | ||
2381 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
2382 | if (is_channel_a_band(ch_info)) | |
8318d78a | 2383 | priv->band = IEEE80211_BAND_5GHZ; |
b481de9c | 2384 | else |
8318d78a | 2385 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c | 2386 | |
8318d78a | 2387 | iwl3945_set_flags_for_phymode(priv, priv->band); |
b481de9c ZY |
2388 | |
2389 | priv->staging_rxon.ofdm_basic_rates = | |
2390 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2391 | priv->staging_rxon.cck_basic_rates = | |
2392 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2393 | } | |
2394 | ||
bb8c093b | 2395 | static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode) |
b481de9c | 2396 | { |
b481de9c | 2397 | if (mode == IEEE80211_IF_TYPE_IBSS) { |
bb8c093b | 2398 | const struct iwl3945_channel_info *ch_info; |
b481de9c | 2399 | |
bb8c093b | 2400 | ch_info = iwl3945_get_channel_info(priv, |
8318d78a | 2401 | priv->band, |
b481de9c ZY |
2402 | le16_to_cpu(priv->staging_rxon.channel)); |
2403 | ||
2404 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2405 | IWL_ERROR("channel %d not IBSS channel\n", | |
2406 | le16_to_cpu(priv->staging_rxon.channel)); | |
2407 | return -EINVAL; | |
2408 | } | |
2409 | } | |
2410 | ||
b481de9c ZY |
2411 | priv->iw_mode = mode; |
2412 | ||
bb8c093b | 2413 | iwl3945_connection_init_rx_config(priv); |
b481de9c ZY |
2414 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2415 | ||
bb8c093b | 2416 | iwl3945_clear_stations_table(priv); |
b481de9c | 2417 | |
fde3571f MA |
2418 | /* dont commit rxon if rf-kill is on*/ |
2419 | if (!iwl3945_is_ready_rf(priv)) | |
2420 | return -EAGAIN; | |
2421 | ||
2422 | cancel_delayed_work(&priv->scan_check); | |
2423 | if (iwl3945_scan_cancel_timeout(priv, 100)) { | |
2424 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
2425 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
2426 | return -EAGAIN; | |
2427 | } | |
2428 | ||
bb8c093b | 2429 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
2430 | |
2431 | return 0; | |
2432 | } | |
2433 | ||
bb8c093b | 2434 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv, |
b481de9c | 2435 | struct ieee80211_tx_control *ctl, |
bb8c093b | 2436 | struct iwl3945_cmd *cmd, |
b481de9c ZY |
2437 | struct sk_buff *skb_frag, |
2438 | int last_frag) | |
2439 | { | |
bb8c093b | 2440 | struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo; |
b481de9c ZY |
2441 | |
2442 | switch (keyinfo->alg) { | |
2443 | case ALG_CCMP: | |
2444 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
2445 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
2446 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); | |
2447 | break; | |
2448 | ||
2449 | case ALG_TKIP: | |
2450 | #if 0 | |
2451 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; | |
2452 | ||
2453 | if (last_frag) | |
2454 | memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8, | |
2455 | 8); | |
2456 | else | |
2457 | memset(cmd->cmd.tx.tkip_mic.byte, 0, 8); | |
2458 | #endif | |
2459 | break; | |
2460 | ||
2461 | case ALG_WEP: | |
2462 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP | | |
2463 | (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; | |
2464 | ||
2465 | if (keyinfo->keylen == 13) | |
2466 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2467 | ||
2468 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen); | |
2469 | ||
2470 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
2471 | "with key %d\n", ctl->key_idx); | |
2472 | break; | |
2473 | ||
b481de9c ZY |
2474 | default: |
2475 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2476 | break; | |
2477 | } | |
2478 | } | |
2479 | ||
2480 | /* | |
2481 | * handle build REPLY_TX command notification. | |
2482 | */ | |
bb8c093b CH |
2483 | static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv, |
2484 | struct iwl3945_cmd *cmd, | |
b481de9c ZY |
2485 | struct ieee80211_tx_control *ctrl, |
2486 | struct ieee80211_hdr *hdr, | |
2487 | int is_unicast, u8 std_id) | |
2488 | { | |
2489 | __le16 *qc; | |
2490 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2491 | __le32 tx_flags = cmd->cmd.tx.tx_flags; | |
2492 | ||
2493 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
2494 | if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { | |
2495 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
2496 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
2497 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2498 | if (ieee80211_is_probe_response(fc) && | |
2499 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
2500 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2501 | } else { | |
2502 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2503 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2504 | } | |
2505 | ||
2506 | cmd->cmd.tx.sta_id = std_id; | |
2507 | if (ieee80211_get_morefrag(hdr)) | |
2508 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
2509 | ||
2510 | qc = ieee80211_get_qos_ctrl(hdr); | |
2511 | if (qc) { | |
2512 | cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf); | |
2513 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
2514 | } else | |
2515 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2516 | ||
2517 | if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { | |
2518 | tx_flags |= TX_CMD_FLG_RTS_MSK; | |
2519 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
2520 | } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { | |
2521 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
2522 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2523 | } | |
2524 | ||
2525 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2526 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2527 | ||
2528 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
2529 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { | |
2530 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || | |
2531 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) | |
bc434dd2 | 2532 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2533 | else |
bc434dd2 | 2534 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
b481de9c ZY |
2535 | } else |
2536 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; | |
2537 | ||
2538 | cmd->cmd.tx.driver_txop = 0; | |
2539 | cmd->cmd.tx.tx_flags = tx_flags; | |
2540 | cmd->cmd.tx.next_frame_len = 0; | |
2541 | } | |
2542 | ||
6440adb5 BC |
2543 | /** |
2544 | * iwl3945_get_sta_id - Find station's index within station table | |
2545 | */ | |
bb8c093b | 2546 | static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr) |
b481de9c ZY |
2547 | { |
2548 | int sta_id; | |
2549 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2550 | ||
6440adb5 | 2551 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2552 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2553 | is_multicast_ether_addr(hdr->addr1)) | |
2554 | return priv->hw_setting.bcast_sta_id; | |
2555 | ||
2556 | switch (priv->iw_mode) { | |
2557 | ||
6440adb5 BC |
2558 | /* If we are a client station in a BSS network, use the special |
2559 | * AP station entry (that's the only station we communicate with) */ | |
b481de9c ZY |
2560 | case IEEE80211_IF_TYPE_STA: |
2561 | return IWL_AP_ID; | |
2562 | ||
2563 | /* If we are an AP, then find the station, or use BCAST */ | |
2564 | case IEEE80211_IF_TYPE_AP: | |
bb8c093b | 2565 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2566 | if (sta_id != IWL_INVALID_STATION) |
2567 | return sta_id; | |
2568 | return priv->hw_setting.bcast_sta_id; | |
2569 | ||
6440adb5 BC |
2570 | /* If this frame is going out to an IBSS network, find the station, |
2571 | * or create a new station table entry */ | |
0795af57 JP |
2572 | case IEEE80211_IF_TYPE_IBSS: { |
2573 | DECLARE_MAC_BUF(mac); | |
2574 | ||
6440adb5 | 2575 | /* Create new station table entry */ |
bb8c093b | 2576 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2577 | if (sta_id != IWL_INVALID_STATION) |
2578 | return sta_id; | |
2579 | ||
bb8c093b | 2580 | sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC); |
b481de9c ZY |
2581 | |
2582 | if (sta_id != IWL_INVALID_STATION) | |
2583 | return sta_id; | |
2584 | ||
0795af57 | 2585 | IWL_DEBUG_DROP("Station %s not in station map. " |
b481de9c | 2586 | "Defaulting to broadcast...\n", |
0795af57 | 2587 | print_mac(mac, hdr->addr1)); |
bb8c093b | 2588 | iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
b481de9c | 2589 | return priv->hw_setting.bcast_sta_id; |
0795af57 | 2590 | } |
b481de9c | 2591 | default: |
01ebd063 | 2592 | IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); |
b481de9c ZY |
2593 | return priv->hw_setting.bcast_sta_id; |
2594 | } | |
2595 | } | |
2596 | ||
2597 | /* | |
2598 | * start REPLY_TX command process | |
2599 | */ | |
bb8c093b | 2600 | static int iwl3945_tx_skb(struct iwl3945_priv *priv, |
b481de9c ZY |
2601 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) |
2602 | { | |
2603 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
bb8c093b | 2604 | struct iwl3945_tfd_frame *tfd; |
b481de9c ZY |
2605 | u32 *control_flags; |
2606 | int txq_id = ctl->queue; | |
bb8c093b CH |
2607 | struct iwl3945_tx_queue *txq = NULL; |
2608 | struct iwl3945_queue *q = NULL; | |
b481de9c ZY |
2609 | dma_addr_t phys_addr; |
2610 | dma_addr_t txcmd_phys; | |
bb8c093b | 2611 | struct iwl3945_cmd *out_cmd = NULL; |
b481de9c ZY |
2612 | u16 len, idx, len_org; |
2613 | u8 id, hdr_len, unicast; | |
2614 | u8 sta_id; | |
2615 | u16 seq_number = 0; | |
2616 | u16 fc; | |
2617 | __le16 *qc; | |
2618 | u8 wait_write_ptr = 0; | |
2619 | unsigned long flags; | |
2620 | int rc; | |
2621 | ||
2622 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2623 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
2624 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2625 | goto drop_unlock; | |
2626 | } | |
2627 | ||
32bfd35d JB |
2628 | if (!priv->vif) { |
2629 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
b481de9c ZY |
2630 | goto drop_unlock; |
2631 | } | |
2632 | ||
8318d78a | 2633 | if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2634 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2635 | goto drop_unlock; | |
2636 | } | |
2637 | ||
2638 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2639 | id = 0; | |
2640 | ||
2641 | fc = le16_to_cpu(hdr->frame_control); | |
2642 | ||
c8b0e6e1 | 2643 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
2644 | if (ieee80211_is_auth(fc)) |
2645 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
2646 | else if (ieee80211_is_assoc_request(fc)) | |
2647 | IWL_DEBUG_TX("Sending ASSOC frame\n"); | |
2648 | else if (ieee80211_is_reassoc_request(fc)) | |
2649 | IWL_DEBUG_TX("Sending REASSOC frame\n"); | |
2650 | #endif | |
2651 | ||
7878a5a4 | 2652 | /* drop all data frame if we are not associated */ |
a6477249 RC |
2653 | if ((!iwl3945_is_associated(priv) || |
2654 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) && | |
b481de9c | 2655 | ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) { |
bb8c093b | 2656 | IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n"); |
b481de9c ZY |
2657 | goto drop_unlock; |
2658 | } | |
2659 | ||
2660 | spin_unlock_irqrestore(&priv->lock, flags); | |
2661 | ||
2662 | hdr_len = ieee80211_get_hdrlen(fc); | |
6440adb5 BC |
2663 | |
2664 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2665 | sta_id = iwl3945_get_sta_id(priv, hdr); |
b481de9c | 2666 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
2667 | DECLARE_MAC_BUF(mac); |
2668 | ||
2669 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
2670 | print_mac(mac, hdr->addr1)); | |
b481de9c ZY |
2671 | goto drop; |
2672 | } | |
2673 | ||
2674 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2675 | ||
2676 | qc = ieee80211_get_qos_ctrl(hdr); | |
2677 | if (qc) { | |
2678 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2679 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
2680 | IEEE80211_SCTL_SEQ; | |
2681 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2682 | (hdr->seq_ctrl & | |
2683 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2684 | seq_number += 0x10; | |
2685 | } | |
6440adb5 BC |
2686 | |
2687 | /* Descriptor for chosen Tx queue */ | |
b481de9c ZY |
2688 | txq = &priv->txq[txq_id]; |
2689 | q = &txq->q; | |
2690 | ||
2691 | spin_lock_irqsave(&priv->lock, flags); | |
2692 | ||
6440adb5 | 2693 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2694 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2695 | memset(tfd, 0, sizeof(*tfd)); |
2696 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2697 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2698 | |
6440adb5 | 2699 | /* Set up driver data for this TFD */ |
bb8c093b | 2700 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info)); |
fc4b6853 TW |
2701 | txq->txb[q->write_ptr].skb[0] = skb; |
2702 | memcpy(&(txq->txb[q->write_ptr].status.control), | |
b481de9c | 2703 | ctl, sizeof(struct ieee80211_tx_control)); |
6440adb5 BC |
2704 | |
2705 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2706 | out_cmd = &txq->cmd[idx]; |
2707 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2708 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 BC |
2709 | |
2710 | /* | |
2711 | * Set up the Tx-command (not MAC!) header. | |
2712 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2713 | * after Tx, uCode's Tx response will return this value so driver can | |
2714 | * locate the frame within the tx queue and do post-tx processing. | |
2715 | */ | |
b481de9c ZY |
2716 | out_cmd->hdr.cmd = REPLY_TX; |
2717 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2718 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
2719 | |
2720 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2721 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2722 | ||
6440adb5 BC |
2723 | /* |
2724 | * Use the first empty entry in this queue's command buffer array | |
2725 | * to contain the Tx command and MAC header concatenated together | |
2726 | * (payload data will be in another buffer). | |
2727 | * Size of this varies, due to varying MAC header length. | |
2728 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2729 | * of the MAC header (device reads on dword boundaries). | |
2730 | * We'll tell device about this padding later. | |
2731 | */ | |
b481de9c | 2732 | len = priv->hw_setting.tx_cmd_len + |
bb8c093b | 2733 | sizeof(struct iwl3945_cmd_header) + hdr_len; |
b481de9c ZY |
2734 | |
2735 | len_org = len; | |
2736 | len = (len + 3) & ~3; | |
2737 | ||
2738 | if (len_org != len) | |
2739 | len_org = 1; | |
2740 | else | |
2741 | len_org = 0; | |
2742 | ||
6440adb5 BC |
2743 | /* Physical address of this Tx command's header (not MAC header!), |
2744 | * within command buffer array. */ | |
bb8c093b CH |
2745 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx + |
2746 | offsetof(struct iwl3945_cmd, hdr); | |
b481de9c | 2747 | |
6440adb5 BC |
2748 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2749 | * first entry */ | |
bb8c093b | 2750 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c ZY |
2751 | |
2752 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) | |
bb8c093b | 2753 | iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0); |
b481de9c | 2754 | |
6440adb5 BC |
2755 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2756 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2757 | len = skb->len - hdr_len; |
2758 | if (len) { | |
2759 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2760 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2761 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2762 | } |
2763 | ||
b481de9c | 2764 | if (!len) |
6440adb5 | 2765 | /* If there is no payload, then we use only one Tx buffer */ |
b481de9c ZY |
2766 | *control_flags = TFD_CTL_COUNT_SET(1); |
2767 | else | |
6440adb5 BC |
2768 | /* Else use 2 buffers. |
2769 | * Tell 3945 about any padding after MAC header */ | |
b481de9c ZY |
2770 | *control_flags = TFD_CTL_COUNT_SET(2) | |
2771 | TFD_CTL_PAD_SET(U32_PAD(len)); | |
2772 | ||
6440adb5 | 2773 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2774 | len = (u16)skb->len; |
2775 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2776 | ||
2777 | /* TODO need this for burst mode later on */ | |
bb8c093b | 2778 | iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id); |
b481de9c ZY |
2779 | |
2780 | /* set is_hcca to 0; it probably will never be implemented */ | |
bb8c093b | 2781 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0); |
b481de9c ZY |
2782 | |
2783 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; | |
2784 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
2785 | ||
2786 | if (!ieee80211_get_morefrag(hdr)) { | |
2787 | txq->need_update = 1; | |
2788 | if (qc) { | |
2789 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2790 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
2791 | } | |
2792 | } else { | |
2793 | wait_write_ptr = 1; | |
2794 | txq->need_update = 0; | |
2795 | } | |
2796 | ||
bb8c093b | 2797 | iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2798 | sizeof(out_cmd->cmd.tx)); |
2799 | ||
bb8c093b | 2800 | iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
b481de9c ZY |
2801 | ieee80211_get_hdrlen(fc)); |
2802 | ||
6440adb5 | 2803 | /* Tell device the write index *just past* this latest filled TFD */ |
bb8c093b CH |
2804 | q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd); |
2805 | rc = iwl3945_tx_queue_update_write_ptr(priv, txq); | |
b481de9c ZY |
2806 | spin_unlock_irqrestore(&priv->lock, flags); |
2807 | ||
2808 | if (rc) | |
2809 | return rc; | |
2810 | ||
bb8c093b | 2811 | if ((iwl3945_queue_space(q) < q->high_mark) |
b481de9c ZY |
2812 | && priv->mac80211_registered) { |
2813 | if (wait_write_ptr) { | |
2814 | spin_lock_irqsave(&priv->lock, flags); | |
2815 | txq->need_update = 1; | |
bb8c093b | 2816 | iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2817 | spin_unlock_irqrestore(&priv->lock, flags); |
2818 | } | |
2819 | ||
2820 | ieee80211_stop_queue(priv->hw, ctl->queue); | |
2821 | } | |
2822 | ||
2823 | return 0; | |
2824 | ||
2825 | drop_unlock: | |
2826 | spin_unlock_irqrestore(&priv->lock, flags); | |
2827 | drop: | |
2828 | return -1; | |
2829 | } | |
2830 | ||
bb8c093b | 2831 | static void iwl3945_set_rate(struct iwl3945_priv *priv) |
b481de9c | 2832 | { |
8318d78a | 2833 | const struct ieee80211_supported_band *sband = NULL; |
b481de9c ZY |
2834 | struct ieee80211_rate *rate; |
2835 | int i; | |
2836 | ||
8318d78a JB |
2837 | sband = iwl3945_get_band(priv, priv->band); |
2838 | if (!sband) { | |
c4ba9621 SA |
2839 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); |
2840 | return; | |
2841 | } | |
b481de9c ZY |
2842 | |
2843 | priv->active_rate = 0; | |
2844 | priv->active_rate_basic = 0; | |
2845 | ||
8318d78a JB |
2846 | IWL_DEBUG_RATE("Setting rates for %s GHz\n", |
2847 | sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5"); | |
2848 | ||
2849 | for (i = 0; i < sband->n_bitrates; i++) { | |
2850 | rate = &sband->bitrates[i]; | |
2851 | if ((rate->hw_value < IWL_RATE_COUNT) && | |
2852 | !(rate->flags & IEEE80211_CHAN_DISABLED)) { | |
2853 | IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n", | |
2854 | rate->hw_value, iwl3945_rates[rate->hw_value].plcp); | |
2855 | priv->active_rate |= (1 << rate->hw_value); | |
2856 | } | |
b481de9c ZY |
2857 | } |
2858 | ||
2859 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2860 | priv->active_rate, priv->active_rate_basic); | |
2861 | ||
2862 | /* | |
2863 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2864 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2865 | * OFDM | |
2866 | */ | |
2867 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
2868 | priv->staging_rxon.cck_basic_rates = | |
2869 | ((priv->active_rate_basic & | |
2870 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2871 | else | |
2872 | priv->staging_rxon.cck_basic_rates = | |
2873 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2874 | ||
2875 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
2876 | priv->staging_rxon.ofdm_basic_rates = | |
2877 | ((priv->active_rate_basic & | |
2878 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2879 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2880 | else | |
2881 | priv->staging_rxon.ofdm_basic_rates = | |
2882 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2883 | } | |
2884 | ||
bb8c093b | 2885 | static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio) |
b481de9c ZY |
2886 | { |
2887 | unsigned long flags; | |
2888 | ||
2889 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2890 | return; | |
2891 | ||
2892 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2893 | disable_radio ? "OFF" : "ON"); | |
2894 | ||
2895 | if (disable_radio) { | |
bb8c093b | 2896 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
2897 | /* FIXME: This is a workaround for AP */ |
2898 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
2899 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2900 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2901 | CSR_UCODE_SW_BIT_RFKILL); |
2902 | spin_unlock_irqrestore(&priv->lock, flags); | |
bb8c093b | 2903 | iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); |
b481de9c ZY |
2904 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
2905 | } | |
2906 | return; | |
2907 | } | |
2908 | ||
2909 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2910 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2911 | |
2912 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2913 | spin_unlock_irqrestore(&priv->lock, flags); | |
2914 | ||
2915 | /* wake up ucode */ | |
2916 | msleep(10); | |
2917 | ||
2918 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b CH |
2919 | iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
2920 | if (!iwl3945_grab_nic_access(priv)) | |
2921 | iwl3945_release_nic_access(priv); | |
b481de9c ZY |
2922 | spin_unlock_irqrestore(&priv->lock, flags); |
2923 | ||
2924 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2925 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2926 | "disabled by HW switch\n"); | |
2927 | return; | |
2928 | } | |
2929 | ||
2930 | queue_work(priv->workqueue, &priv->restart); | |
2931 | return; | |
2932 | } | |
2933 | ||
bb8c093b | 2934 | void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2935 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2936 | { | |
2937 | u16 fc = | |
2938 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2939 | ||
2940 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
2941 | return; | |
2942 | ||
2943 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2944 | return; | |
2945 | ||
2946 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2947 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2948 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2949 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2950 | RX_RES_STATUS_BAD_ICV_MIC) | |
2951 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2952 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2953 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2954 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2955 | RX_RES_STATUS_DECRYPT_OK) { | |
2956 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2957 | stats->flag |= RX_FLAG_DECRYPTED; | |
2958 | } | |
2959 | break; | |
2960 | ||
2961 | default: | |
2962 | break; | |
2963 | } | |
2964 | } | |
2965 | ||
b481de9c ZY |
2966 | #define IWL_PACKET_RETRY_TIME HZ |
2967 | ||
bb8c093b | 2968 | int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2969 | { |
2970 | u16 sc = le16_to_cpu(header->seq_ctrl); | |
2971 | u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4; | |
2972 | u16 frag = sc & IEEE80211_SCTL_FRAG; | |
2973 | u16 *last_seq, *last_frag; | |
2974 | unsigned long *last_time; | |
2975 | ||
2976 | switch (priv->iw_mode) { | |
2977 | case IEEE80211_IF_TYPE_IBSS:{ | |
2978 | struct list_head *p; | |
bb8c093b | 2979 | struct iwl3945_ibss_seq *entry = NULL; |
b481de9c ZY |
2980 | u8 *mac = header->addr2; |
2981 | int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1); | |
2982 | ||
2983 | __list_for_each(p, &priv->ibss_mac_hash[index]) { | |
bb8c093b | 2984 | entry = list_entry(p, struct iwl3945_ibss_seq, list); |
b481de9c ZY |
2985 | if (!compare_ether_addr(entry->mac, mac)) |
2986 | break; | |
2987 | } | |
2988 | if (p == &priv->ibss_mac_hash[index]) { | |
2989 | entry = kzalloc(sizeof(*entry), GFP_ATOMIC); | |
2990 | if (!entry) { | |
bc434dd2 | 2991 | IWL_ERROR("Cannot malloc new mac entry\n"); |
b481de9c ZY |
2992 | return 0; |
2993 | } | |
2994 | memcpy(entry->mac, mac, ETH_ALEN); | |
2995 | entry->seq_num = seq; | |
2996 | entry->frag_num = frag; | |
2997 | entry->packet_time = jiffies; | |
bc434dd2 | 2998 | list_add(&entry->list, &priv->ibss_mac_hash[index]); |
b481de9c ZY |
2999 | return 0; |
3000 | } | |
3001 | last_seq = &entry->seq_num; | |
3002 | last_frag = &entry->frag_num; | |
3003 | last_time = &entry->packet_time; | |
3004 | break; | |
3005 | } | |
3006 | case IEEE80211_IF_TYPE_STA: | |
3007 | last_seq = &priv->last_seq_num; | |
3008 | last_frag = &priv->last_frag_num; | |
3009 | last_time = &priv->last_packet_time; | |
3010 | break; | |
3011 | default: | |
3012 | return 0; | |
3013 | } | |
3014 | if ((*last_seq == seq) && | |
3015 | time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) { | |
3016 | if (*last_frag == frag) | |
3017 | goto drop; | |
3018 | if (*last_frag + 1 != frag) | |
3019 | /* out-of-order fragment */ | |
3020 | goto drop; | |
3021 | } else | |
3022 | *last_seq = seq; | |
3023 | ||
3024 | *last_frag = frag; | |
3025 | *last_time = jiffies; | |
3026 | return 0; | |
3027 | ||
3028 | drop: | |
3029 | return 1; | |
3030 | } | |
3031 | ||
c8b0e6e1 | 3032 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3033 | |
3034 | #include "iwl-spectrum.h" | |
3035 | ||
3036 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
3037 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
3038 | #define TIME_UNIT 1024 | |
3039 | ||
3040 | /* | |
3041 | * extended beacon time format | |
3042 | * time in usec will be changed into a 32-bit value in 8:24 format | |
3043 | * the high 1 byte is the beacon counts | |
3044 | * the lower 3 bytes is the time in usec within one beacon interval | |
3045 | */ | |
3046 | ||
bb8c093b | 3047 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
3048 | { |
3049 | u32 quot; | |
3050 | u32 rem; | |
3051 | u32 interval = beacon_interval * 1024; | |
3052 | ||
3053 | if (!interval || !usec) | |
3054 | return 0; | |
3055 | ||
3056 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
3057 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
3058 | ||
3059 | return (quot << 24) + rem; | |
3060 | } | |
3061 | ||
3062 | /* base is usually what we get from ucode with each received frame, | |
3063 | * the same as HW timer counter counting down | |
3064 | */ | |
3065 | ||
bb8c093b | 3066 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
3067 | { |
3068 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
3069 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
3070 | u32 interval = beacon_interval * TIME_UNIT; | |
3071 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
3072 | (addon & BEACON_TIME_MASK_HIGH); | |
3073 | ||
3074 | if (base_low > addon_low) | |
3075 | res += base_low - addon_low; | |
3076 | else if (base_low < addon_low) { | |
3077 | res += interval + base_low - addon_low; | |
3078 | res += (1 << 24); | |
3079 | } else | |
3080 | res += (1 << 24); | |
3081 | ||
3082 | return cpu_to_le32(res); | |
3083 | } | |
3084 | ||
bb8c093b | 3085 | static int iwl3945_get_measurement(struct iwl3945_priv *priv, |
b481de9c ZY |
3086 | struct ieee80211_measurement_params *params, |
3087 | u8 type) | |
3088 | { | |
bb8c093b CH |
3089 | struct iwl3945_spectrum_cmd spectrum; |
3090 | struct iwl3945_rx_packet *res; | |
3091 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
3092 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
3093 | .data = (void *)&spectrum, | |
3094 | .meta.flags = CMD_WANT_SKB, | |
3095 | }; | |
3096 | u32 add_time = le64_to_cpu(params->start_time); | |
3097 | int rc; | |
3098 | int spectrum_resp_status; | |
3099 | int duration = le16_to_cpu(params->duration); | |
3100 | ||
bb8c093b | 3101 | if (iwl3945_is_associated(priv)) |
b481de9c | 3102 | add_time = |
bb8c093b | 3103 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
3104 | le64_to_cpu(params->start_time) - priv->last_tsf, |
3105 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
3106 | ||
3107 | memset(&spectrum, 0, sizeof(spectrum)); | |
3108 | ||
3109 | spectrum.channel_count = cpu_to_le16(1); | |
3110 | spectrum.flags = | |
3111 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
3112 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
3113 | cmd.len = sizeof(spectrum); | |
3114 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
3115 | ||
bb8c093b | 3116 | if (iwl3945_is_associated(priv)) |
b481de9c | 3117 | spectrum.start_time = |
bb8c093b | 3118 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
3119 | add_time, |
3120 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
3121 | else | |
3122 | spectrum.start_time = 0; | |
3123 | ||
3124 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
3125 | spectrum.channels[0].channel = params->channel; | |
3126 | spectrum.channels[0].type = type; | |
3127 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
3128 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
3129 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
3130 | ||
bb8c093b | 3131 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
3132 | if (rc) |
3133 | return rc; | |
3134 | ||
bb8c093b | 3135 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
3136 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
3137 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
3138 | rc = -EIO; | |
3139 | } | |
3140 | ||
3141 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
3142 | switch (spectrum_resp_status) { | |
3143 | case 0: /* Command will be handled */ | |
3144 | if (res->u.spectrum.id != 0xff) { | |
bc434dd2 IS |
3145 | IWL_DEBUG_INFO("Replaced existing measurement: %d\n", |
3146 | res->u.spectrum.id); | |
b481de9c ZY |
3147 | priv->measurement_status &= ~MEASUREMENT_READY; |
3148 | } | |
3149 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
3150 | rc = 0; | |
3151 | break; | |
3152 | ||
3153 | case 1: /* Command will not be handled */ | |
3154 | rc = -EAGAIN; | |
3155 | break; | |
3156 | } | |
3157 | ||
3158 | dev_kfree_skb_any(cmd.meta.u.skb); | |
3159 | ||
3160 | return rc; | |
3161 | } | |
3162 | #endif | |
3163 | ||
bb8c093b CH |
3164 | static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv, |
3165 | struct iwl3945_tx_info *tx_sta) | |
b481de9c ZY |
3166 | { |
3167 | ||
3168 | tx_sta->status.ack_signal = 0; | |
3169 | tx_sta->status.excessive_retries = 0; | |
3170 | tx_sta->status.queue_length = 0; | |
3171 | tx_sta->status.queue_number = 0; | |
3172 | ||
3173 | if (in_interrupt()) | |
3174 | ieee80211_tx_status_irqsafe(priv->hw, | |
3175 | tx_sta->skb[0], &(tx_sta->status)); | |
3176 | else | |
3177 | ieee80211_tx_status(priv->hw, | |
3178 | tx_sta->skb[0], &(tx_sta->status)); | |
3179 | ||
3180 | tx_sta->skb[0] = NULL; | |
3181 | } | |
3182 | ||
3183 | /** | |
6440adb5 | 3184 | * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd |
b481de9c | 3185 | * |
6440adb5 BC |
3186 | * When FW advances 'R' index, all entries between old and new 'R' index |
3187 | * need to be reclaimed. As result, some free space forms. If there is | |
3188 | * enough free space (> low mark), wake the stack that feeds us. | |
b481de9c | 3189 | */ |
bb8c093b | 3190 | static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index) |
b481de9c | 3191 | { |
bb8c093b CH |
3192 | struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; |
3193 | struct iwl3945_queue *q = &txq->q; | |
b481de9c ZY |
3194 | int nfreed = 0; |
3195 | ||
3196 | if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) { | |
3197 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
3198 | "is out of range [0-%d] %d %d.\n", txq_id, | |
fc4b6853 | 3199 | index, q->n_bd, q->write_ptr, q->read_ptr); |
b481de9c ZY |
3200 | return 0; |
3201 | } | |
3202 | ||
bb8c093b | 3203 | for (index = iwl3945_queue_inc_wrap(index, q->n_bd); |
fc4b6853 | 3204 | q->read_ptr != index; |
bb8c093b | 3205 | q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
b481de9c | 3206 | if (txq_id != IWL_CMD_QUEUE_NUM) { |
bb8c093b | 3207 | iwl3945_txstatus_to_ieee(priv, |
fc4b6853 | 3208 | &(txq->txb[txq->q.read_ptr])); |
bb8c093b | 3209 | iwl3945_hw_txq_free_tfd(priv, txq); |
b481de9c ZY |
3210 | } else if (nfreed > 1) { |
3211 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
fc4b6853 | 3212 | q->write_ptr, q->read_ptr); |
b481de9c ZY |
3213 | queue_work(priv->workqueue, &priv->restart); |
3214 | } | |
3215 | nfreed++; | |
3216 | } | |
3217 | ||
bb8c093b | 3218 | if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) && |
b481de9c ZY |
3219 | (txq_id != IWL_CMD_QUEUE_NUM) && |
3220 | priv->mac80211_registered) | |
3221 | ieee80211_wake_queue(priv->hw, txq_id); | |
3222 | ||
3223 | ||
3224 | return nfreed; | |
3225 | } | |
3226 | ||
bb8c093b | 3227 | static int iwl3945_is_tx_success(u32 status) |
b481de9c ZY |
3228 | { |
3229 | return (status & 0xFF) == 0x1; | |
3230 | } | |
3231 | ||
3232 | /****************************************************************************** | |
3233 | * | |
3234 | * Generic RX handler implementations | |
3235 | * | |
3236 | ******************************************************************************/ | |
6440adb5 BC |
3237 | /** |
3238 | * iwl3945_rx_reply_tx - Handle Tx response | |
3239 | */ | |
bb8c093b CH |
3240 | static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv, |
3241 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3242 | { |
bb8c093b | 3243 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3244 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3245 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3246 | int index = SEQ_TO_INDEX(sequence); | |
bb8c093b | 3247 | struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; |
b481de9c | 3248 | struct ieee80211_tx_status *tx_status; |
bb8c093b | 3249 | struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
b481de9c ZY |
3250 | u32 status = le32_to_cpu(tx_resp->status); |
3251 | ||
3252 | if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) { | |
3253 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
3254 | "is out of range [0-%d] %d %d\n", txq_id, | |
fc4b6853 TW |
3255 | index, txq->q.n_bd, txq->q.write_ptr, |
3256 | txq->q.read_ptr); | |
b481de9c ZY |
3257 | return; |
3258 | } | |
3259 | ||
fc4b6853 | 3260 | tx_status = &(txq->txb[txq->q.read_ptr].status); |
b481de9c ZY |
3261 | |
3262 | tx_status->retry_count = tx_resp->failure_frame; | |
3263 | tx_status->queue_number = status; | |
3264 | tx_status->queue_length = tx_resp->bt_kill_count; | |
3265 | tx_status->queue_length |= tx_resp->failure_rts; | |
3266 | ||
3267 | tx_status->flags = | |
bb8c093b | 3268 | iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0; |
b481de9c | 3269 | |
b481de9c | 3270 | IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", |
bb8c093b | 3271 | txq_id, iwl3945_get_tx_fail_reason(status), status, |
b481de9c ZY |
3272 | tx_resp->rate, tx_resp->failure_frame); |
3273 | ||
3274 | IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); | |
3275 | if (index != -1) | |
bb8c093b | 3276 | iwl3945_tx_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3277 | |
3278 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) | |
3279 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
3280 | } | |
3281 | ||
3282 | ||
bb8c093b CH |
3283 | static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv, |
3284 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3285 | { |
bb8c093b CH |
3286 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3287 | struct iwl3945_alive_resp *palive; | |
b481de9c ZY |
3288 | struct delayed_work *pwork; |
3289 | ||
3290 | palive = &pkt->u.alive_frame; | |
3291 | ||
3292 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
3293 | "0x%01X 0x%01X\n", | |
3294 | palive->is_valid, palive->ver_type, | |
3295 | palive->ver_subtype); | |
3296 | ||
3297 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
3298 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3299 | memcpy(&priv->card_alive_init, | |
3300 | &pkt->u.alive_frame, | |
bb8c093b | 3301 | sizeof(struct iwl3945_init_alive_resp)); |
b481de9c ZY |
3302 | pwork = &priv->init_alive_start; |
3303 | } else { | |
3304 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
3305 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
bb8c093b | 3306 | sizeof(struct iwl3945_alive_resp)); |
b481de9c | 3307 | pwork = &priv->alive_start; |
bb8c093b | 3308 | iwl3945_disable_events(priv); |
b481de9c ZY |
3309 | } |
3310 | ||
3311 | /* We delay the ALIVE response by 5ms to | |
3312 | * give the HW RF Kill time to activate... */ | |
3313 | if (palive->is_valid == UCODE_VALID_OK) | |
3314 | queue_delayed_work(priv->workqueue, pwork, | |
3315 | msecs_to_jiffies(5)); | |
3316 | else | |
3317 | IWL_WARNING("uCode did not respond OK.\n"); | |
3318 | } | |
3319 | ||
bb8c093b CH |
3320 | static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv, |
3321 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3322 | { |
bb8c093b | 3323 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3324 | |
3325 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
3326 | return; | |
3327 | } | |
3328 | ||
bb8c093b CH |
3329 | static void iwl3945_rx_reply_error(struct iwl3945_priv *priv, |
3330 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3331 | { |
bb8c093b | 3332 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3333 | |
3334 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
3335 | "seq 0x%04X ser 0x%08X\n", | |
3336 | le32_to_cpu(pkt->u.err_resp.error_type), | |
3337 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
3338 | pkt->u.err_resp.cmd_id, | |
3339 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
3340 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
3341 | } | |
3342 | ||
3343 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
3344 | ||
bb8c093b | 3345 | static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb) |
b481de9c | 3346 | { |
bb8c093b CH |
3347 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3348 | struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
3349 | struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif); | |
b481de9c ZY |
3350 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
3351 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
3352 | rxon->channel = csa->channel; | |
3353 | priv->staging_rxon.channel = csa->channel; | |
3354 | } | |
3355 | ||
bb8c093b CH |
3356 | static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv, |
3357 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3358 | { |
c8b0e6e1 | 3359 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
bb8c093b CH |
3360 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3361 | struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
b481de9c ZY |
3362 | |
3363 | if (!report->state) { | |
3364 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
3365 | "Spectrum Measure Notification: Start\n"); | |
3366 | return; | |
3367 | } | |
3368 | ||
3369 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
3370 | priv->measurement_status |= MEASUREMENT_READY; | |
3371 | #endif | |
3372 | } | |
3373 | ||
bb8c093b CH |
3374 | static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv, |
3375 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3376 | { |
c8b0e6e1 | 3377 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3378 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3379 | struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
b481de9c ZY |
3380 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
3381 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
3382 | #endif | |
3383 | } | |
3384 | ||
bb8c093b CH |
3385 | static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv, |
3386 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3387 | { |
bb8c093b | 3388 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3389 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
3390 | "notification for %s:\n", | |
3391 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
bb8c093b | 3392 | iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
3393 | } |
3394 | ||
bb8c093b | 3395 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 3396 | { |
bb8c093b CH |
3397 | struct iwl3945_priv *priv = |
3398 | container_of(work, struct iwl3945_priv, beacon_update); | |
b481de9c ZY |
3399 | struct sk_buff *beacon; |
3400 | ||
3401 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
32bfd35d | 3402 | beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); |
b481de9c ZY |
3403 | |
3404 | if (!beacon) { | |
3405 | IWL_ERROR("update beacon failed\n"); | |
3406 | return; | |
3407 | } | |
3408 | ||
3409 | mutex_lock(&priv->mutex); | |
3410 | /* new beacon skb is allocated every time; dispose previous.*/ | |
3411 | if (priv->ibss_beacon) | |
3412 | dev_kfree_skb(priv->ibss_beacon); | |
3413 | ||
3414 | priv->ibss_beacon = beacon; | |
3415 | mutex_unlock(&priv->mutex); | |
3416 | ||
bb8c093b | 3417 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3418 | } |
3419 | ||
bb8c093b CH |
3420 | static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv, |
3421 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3422 | { |
c8b0e6e1 | 3423 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3424 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3425 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); | |
b481de9c ZY |
3426 | u8 rate = beacon->beacon_notify_hdr.rate; |
3427 | ||
3428 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3429 | "tsf %d %d rate %d\n", | |
3430 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3431 | beacon->beacon_notify_hdr.failure_frame, | |
3432 | le32_to_cpu(beacon->ibss_mgr_status), | |
3433 | le32_to_cpu(beacon->high_tsf), | |
3434 | le32_to_cpu(beacon->low_tsf), rate); | |
3435 | #endif | |
3436 | ||
3437 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && | |
3438 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) | |
3439 | queue_work(priv->workqueue, &priv->beacon_update); | |
3440 | } | |
3441 | ||
3442 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
bb8c093b CH |
3443 | static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv, |
3444 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3445 | { |
c8b0e6e1 | 3446 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3447 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3448 | struct iwl3945_scanreq_notification *notif = | |
3449 | (struct iwl3945_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3450 | |
3451 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3452 | #endif | |
3453 | } | |
3454 | ||
3455 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
bb8c093b CH |
3456 | static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv, |
3457 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3458 | { |
bb8c093b CH |
3459 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3460 | struct iwl3945_scanstart_notification *notif = | |
3461 | (struct iwl3945_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3462 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3463 | IWL_DEBUG_SCAN("Scan start: " | |
3464 | "%d [802.11%s] " | |
3465 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3466 | notif->channel, | |
3467 | notif->band ? "bg" : "a", | |
3468 | notif->tsf_high, | |
3469 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3470 | } | |
3471 | ||
3472 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
bb8c093b CH |
3473 | static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv, |
3474 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3475 | { |
bb8c093b CH |
3476 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3477 | struct iwl3945_scanresults_notification *notif = | |
3478 | (struct iwl3945_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3479 | |
3480 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3481 | "%d [802.11%s] " | |
3482 | "(TSF: 0x%08X:%08X) - %d " | |
3483 | "elapsed=%lu usec (%dms since last)\n", | |
3484 | notif->channel, | |
3485 | notif->band ? "bg" : "a", | |
3486 | le32_to_cpu(notif->tsf_high), | |
3487 | le32_to_cpu(notif->tsf_low), | |
3488 | le32_to_cpu(notif->statistics[0]), | |
3489 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3490 | jiffies_to_msecs(elapsed_jiffies | |
3491 | (priv->last_scan_jiffies, jiffies))); | |
3492 | ||
3493 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3494 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3495 | } |
3496 | ||
3497 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
bb8c093b CH |
3498 | static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv, |
3499 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3500 | { |
bb8c093b CH |
3501 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3502 | struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
b481de9c ZY |
3503 | |
3504 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3505 | scan_notif->scanned_channels, | |
3506 | scan_notif->tsf_low, | |
3507 | scan_notif->tsf_high, scan_notif->status); | |
3508 | ||
3509 | /* The HW is no longer scanning */ | |
3510 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3511 | ||
3512 | /* The scan completion notification came in, so kill that timer... */ | |
3513 | cancel_delayed_work(&priv->scan_check); | |
3514 | ||
3515 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
3516 | (priv->scan_bands == 2) ? "2.4" : "5.2", | |
3517 | jiffies_to_msecs(elapsed_jiffies | |
3518 | (priv->scan_pass_start, jiffies))); | |
3519 | ||
3520 | /* Remove this scanned band from the list | |
3521 | * of pending bands to scan */ | |
3522 | priv->scan_bands--; | |
3523 | ||
3524 | /* If a request to abort was given, or the scan did not succeed | |
3525 | * then we reset the scan state machine and terminate, | |
3526 | * re-queuing another scan if one has been requested */ | |
3527 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3528 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3529 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3530 | } else { | |
3531 | /* If there are more bands on this scan pass reschedule */ | |
3532 | if (priv->scan_bands > 0) | |
3533 | goto reschedule; | |
3534 | } | |
3535 | ||
3536 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3537 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3538 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3539 | ||
3540 | clear_bit(STATUS_SCANNING, &priv->status); | |
3541 | ||
3542 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3543 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3544 | ||
3545 | queue_work(priv->workqueue, &priv->scan_completed); | |
3546 | ||
3547 | return; | |
3548 | ||
3549 | reschedule: | |
3550 | priv->scan_pass_start = jiffies; | |
3551 | queue_work(priv->workqueue, &priv->request_scan); | |
3552 | } | |
3553 | ||
3554 | /* Handle notification from uCode that card's power state is changing | |
3555 | * due to software, hardware, or critical temperature RFKILL */ | |
bb8c093b CH |
3556 | static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv, |
3557 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3558 | { |
bb8c093b | 3559 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3560 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3561 | unsigned long status = priv->status; | |
3562 | ||
3563 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3564 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3565 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3566 | ||
bb8c093b | 3567 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3568 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3569 | ||
3570 | if (flags & HW_CARD_DISABLED) | |
3571 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3572 | else | |
3573 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3574 | ||
3575 | ||
3576 | if (flags & SW_CARD_DISABLED) | |
3577 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3578 | else | |
3579 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3580 | ||
bb8c093b | 3581 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
3582 | |
3583 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3584 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3585 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3586 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3587 | queue_work(priv->workqueue, &priv->rf_kill); | |
3588 | else | |
3589 | wake_up_interruptible(&priv->wait_command_queue); | |
3590 | } | |
3591 | ||
3592 | /** | |
bb8c093b | 3593 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3594 | * |
3595 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3596 | * to the host. | |
3597 | * | |
3598 | * This function chains into the hardware specific files for them to setup | |
3599 | * any hardware specific handlers as well. | |
3600 | */ | |
bb8c093b | 3601 | static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv) |
b481de9c | 3602 | { |
bb8c093b CH |
3603 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
3604 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
3605 | priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error; | |
3606 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa; | |
b481de9c | 3607 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3608 | iwl3945_rx_spectrum_measure_notif; |
3609 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif; | |
b481de9c | 3610 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3611 | iwl3945_rx_pm_debug_statistics_notif; |
3612 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; | |
b481de9c | 3613 | |
9fbab516 BC |
3614 | /* |
3615 | * The same handler is used for both the REPLY to a discrete | |
3616 | * statistics request from the host as well as for the periodic | |
3617 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3618 | */ |
bb8c093b CH |
3619 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
3620 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 3621 | |
bb8c093b CH |
3622 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan; |
3623 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif; | |
b481de9c | 3624 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3625 | iwl3945_rx_scan_results_notif; |
b481de9c | 3626 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3627 | iwl3945_rx_scan_complete_notif; |
3628 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; | |
3629 | priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx; | |
b481de9c | 3630 | |
9fbab516 | 3631 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3632 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
3633 | } |
3634 | ||
3635 | /** | |
bb8c093b | 3636 | * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3637 | * @rxb: Rx buffer to reclaim |
3638 | * | |
3639 | * If an Rx buffer has an async callback associated with it the callback | |
3640 | * will be executed. The attached skb (if present) will only be freed | |
3641 | * if the callback returns 1 | |
3642 | */ | |
bb8c093b CH |
3643 | static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv, |
3644 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3645 | { |
bb8c093b | 3646 | struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3647 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3648 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3649 | int index = SEQ_TO_INDEX(sequence); | |
3650 | int huge = sequence & SEQ_HUGE_FRAME; | |
3651 | int cmd_index; | |
bb8c093b | 3652 | struct iwl3945_cmd *cmd; |
b481de9c ZY |
3653 | |
3654 | /* If a Tx command is being handled and it isn't in the actual | |
3655 | * command queue then there a command routing bug has been introduced | |
3656 | * in the queue management code. */ | |
3657 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
3658 | IWL_ERROR("Error wrong command queue %d command id 0x%X\n", | |
3659 | txq_id, pkt->hdr.cmd); | |
3660 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); | |
3661 | ||
3662 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
3663 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
3664 | ||
3665 | /* Input error checking is done when commands are added to queue. */ | |
3666 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3667 | cmd->meta.source->u.skb = rxb->skb; | |
3668 | rxb->skb = NULL; | |
3669 | } else if (cmd->meta.u.callback && | |
3670 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3671 | rxb->skb = NULL; | |
3672 | ||
bb8c093b | 3673 | iwl3945_tx_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3674 | |
3675 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3676 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3677 | wake_up_interruptible(&priv->wait_command_queue); | |
3678 | } | |
3679 | } | |
3680 | ||
3681 | /************************** RX-FUNCTIONS ****************************/ | |
3682 | /* | |
3683 | * Rx theory of operation | |
3684 | * | |
3685 | * The host allocates 32 DMA target addresses and passes the host address | |
3686 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
3687 | * 0 to 31 | |
3688 | * | |
3689 | * Rx Queue Indexes | |
3690 | * The host/firmware share two index registers for managing the Rx buffers. | |
3691 | * | |
3692 | * The READ index maps to the first position that the firmware may be writing | |
3693 | * to -- the driver can read up to (but not including) this position and get | |
3694 | * good data. | |
3695 | * The READ index is managed by the firmware once the card is enabled. | |
3696 | * | |
3697 | * The WRITE index maps to the last position the driver has read from -- the | |
3698 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3699 | * | |
3700 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3701 | * WRITE = READ. | |
3702 | * | |
9fbab516 | 3703 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3704 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3705 | * | |
9fbab516 | 3706 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3707 | * and fire the RX interrupt. The driver can then query the READ index and |
3708 | * process as many packets as possible, moving the WRITE index forward as it | |
3709 | * resets the Rx queue buffers with new memory. | |
3710 | * | |
3711 | * The management in the driver is as follows: | |
3712 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3713 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3714 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3715 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3716 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3717 | * 'processed' and 'read' driver indexes as well) | |
3718 | * + A received packet is processed and handed to the kernel network stack, | |
3719 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3720 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3721 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3722 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3723 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3724 | * | |
3725 | * | |
3726 | * Driver sequence: | |
3727 | * | |
9fbab516 BC |
3728 | * iwl3945_rx_queue_alloc() Allocates rx_free |
3729 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3730 | * iwl3945_rx_queue_restock |
9fbab516 | 3731 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3732 | * queue, updates firmware pointers, and updates |
3733 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3734 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
3735 | * |
3736 | * -- enable interrupts -- | |
9fbab516 | 3737 | * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the |
b481de9c ZY |
3738 | * READ INDEX, detaching the SKB from the pool. |
3739 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3740 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
3741 | * slots. |
3742 | * ... | |
3743 | * | |
3744 | */ | |
3745 | ||
3746 | /** | |
bb8c093b | 3747 | * iwl3945_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3748 | */ |
bb8c093b | 3749 | static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q) |
b481de9c ZY |
3750 | { |
3751 | int s = q->read - q->write; | |
3752 | if (s <= 0) | |
3753 | s += RX_QUEUE_SIZE; | |
3754 | /* keep some buffer to not confuse full and empty queue */ | |
3755 | s -= 2; | |
3756 | if (s < 0) | |
3757 | s = 0; | |
3758 | return s; | |
3759 | } | |
3760 | ||
3761 | /** | |
bb8c093b | 3762 | * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3763 | */ |
bb8c093b | 3764 | int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q) |
b481de9c ZY |
3765 | { |
3766 | u32 reg = 0; | |
3767 | int rc = 0; | |
3768 | unsigned long flags; | |
3769 | ||
3770 | spin_lock_irqsave(&q->lock, flags); | |
3771 | ||
3772 | if (q->need_update == 0) | |
3773 | goto exit_unlock; | |
3774 | ||
6440adb5 | 3775 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3776 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
bb8c093b | 3777 | reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3778 | |
3779 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
bb8c093b | 3780 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3781 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3782 | goto exit_unlock; | |
3783 | } | |
3784 | ||
bb8c093b | 3785 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
3786 | if (rc) |
3787 | goto exit_unlock; | |
3788 | ||
6440adb5 | 3789 | /* Device expects a multiple of 8 */ |
bb8c093b | 3790 | iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, |
b481de9c | 3791 | q->write & ~0x7); |
bb8c093b | 3792 | iwl3945_release_nic_access(priv); |
6440adb5 BC |
3793 | |
3794 | /* Else device is assumed to be awake */ | |
b481de9c | 3795 | } else |
6440adb5 | 3796 | /* Device expects a multiple of 8 */ |
bb8c093b | 3797 | iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3798 | |
3799 | ||
3800 | q->need_update = 0; | |
3801 | ||
3802 | exit_unlock: | |
3803 | spin_unlock_irqrestore(&q->lock, flags); | |
3804 | return rc; | |
3805 | } | |
3806 | ||
3807 | /** | |
9fbab516 | 3808 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3809 | */ |
bb8c093b | 3810 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv, |
b481de9c ZY |
3811 | dma_addr_t dma_addr) |
3812 | { | |
3813 | return cpu_to_le32((u32)dma_addr); | |
3814 | } | |
3815 | ||
3816 | /** | |
bb8c093b | 3817 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3818 | * |
9fbab516 | 3819 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3820 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3821 | * as we can, pulling from rx_free. |
b481de9c ZY |
3822 | * |
3823 | * This moves the 'write' index forward to catch up with 'processed', and | |
3824 | * also updates the memory address in the firmware to reference the new | |
3825 | * target buffer. | |
3826 | */ | |
bb8c093b | 3827 | static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv) |
b481de9c | 3828 | { |
bb8c093b | 3829 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c | 3830 | struct list_head *element; |
bb8c093b | 3831 | struct iwl3945_rx_mem_buffer *rxb; |
b481de9c ZY |
3832 | unsigned long flags; |
3833 | int write, rc; | |
3834 | ||
3835 | spin_lock_irqsave(&rxq->lock, flags); | |
3836 | write = rxq->write & ~0x7; | |
bb8c093b | 3837 | while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3838 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3839 | element = rxq->rx_free.next; |
bb8c093b | 3840 | rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list); |
b481de9c | 3841 | list_del(element); |
6440adb5 BC |
3842 | |
3843 | /* Point to Rx buffer via next RBD in circular buffer */ | |
bb8c093b | 3844 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr); |
b481de9c ZY |
3845 | rxq->queue[rxq->write] = rxb; |
3846 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3847 | rxq->free_count--; | |
3848 | } | |
3849 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3850 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3851 | * refill it */ | |
3852 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3853 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3854 | ||
3855 | ||
6440adb5 BC |
3856 | /* If we've added more space for the firmware to place data, tell it. |
3857 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3858 | if ((write != (rxq->write & ~0x7)) |
3859 | || (abs(rxq->write - rxq->read) > 7)) { | |
3860 | spin_lock_irqsave(&rxq->lock, flags); | |
3861 | rxq->need_update = 1; | |
3862 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3863 | rc = iwl3945_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3864 | if (rc) |
3865 | return rc; | |
3866 | } | |
3867 | ||
3868 | return 0; | |
3869 | } | |
3870 | ||
3871 | /** | |
bb8c093b | 3872 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3873 | * |
3874 | * When moving to rx_free an SKB is allocated for the slot. | |
3875 | * | |
bb8c093b | 3876 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 3877 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3878 | */ |
5c0eef96 | 3879 | static void iwl3945_rx_allocate(struct iwl3945_priv *priv) |
b481de9c | 3880 | { |
bb8c093b | 3881 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c | 3882 | struct list_head *element; |
bb8c093b | 3883 | struct iwl3945_rx_mem_buffer *rxb; |
b481de9c ZY |
3884 | unsigned long flags; |
3885 | spin_lock_irqsave(&rxq->lock, flags); | |
3886 | while (!list_empty(&rxq->rx_used)) { | |
3887 | element = rxq->rx_used.next; | |
bb8c093b | 3888 | rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list); |
6440adb5 BC |
3889 | |
3890 | /* Alloc a new receive buffer */ | |
b481de9c ZY |
3891 | rxb->skb = |
3892 | alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC); | |
3893 | if (!rxb->skb) { | |
3894 | if (net_ratelimit()) | |
3895 | printk(KERN_CRIT DRV_NAME | |
3896 | ": Can not allocate SKB buffers\n"); | |
3897 | /* We don't reschedule replenish work here -- we will | |
3898 | * call the restock method and if it still needs | |
3899 | * more buffers it will schedule replenish */ | |
3900 | break; | |
3901 | } | |
12342c47 ZY |
3902 | |
3903 | /* If radiotap head is required, reserve some headroom here. | |
3904 | * The physical head count is a variable rx_stats->phy_count. | |
3905 | * We reserve 4 bytes here. Plus these extra bytes, the | |
3906 | * headroom of the physical head should be enough for the | |
3907 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
3908 | */ | |
3909 | skb_reserve(rxb->skb, 4); | |
3910 | ||
b481de9c ZY |
3911 | priv->alloc_rxb_skb++; |
3912 | list_del(element); | |
6440adb5 BC |
3913 | |
3914 | /* Get physical address of RB/SKB */ | |
b481de9c ZY |
3915 | rxb->dma_addr = |
3916 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
3917 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3918 | list_add_tail(&rxb->list, &rxq->rx_free); | |
3919 | rxq->free_count++; | |
3920 | } | |
3921 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3922 | } |
3923 | ||
3924 | /* | |
3925 | * this should be called while priv->lock is locked | |
3926 | */ | |
4fd1f841 | 3927 | static void __iwl3945_rx_replenish(void *data) |
5c0eef96 MA |
3928 | { |
3929 | struct iwl3945_priv *priv = data; | |
3930 | ||
3931 | iwl3945_rx_allocate(priv); | |
3932 | iwl3945_rx_queue_restock(priv); | |
3933 | } | |
3934 | ||
3935 | ||
3936 | void iwl3945_rx_replenish(void *data) | |
3937 | { | |
3938 | struct iwl3945_priv *priv = data; | |
3939 | unsigned long flags; | |
3940 | ||
3941 | iwl3945_rx_allocate(priv); | |
b481de9c ZY |
3942 | |
3943 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3944 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3945 | spin_unlock_irqrestore(&priv->lock, flags); |
3946 | } | |
3947 | ||
3948 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3949 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3950 | * This free routine walks the list of POOL entries and if SKB is set to |
3951 | * non NULL it is unmapped and freed | |
3952 | */ | |
bb8c093b | 3953 | static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
b481de9c ZY |
3954 | { |
3955 | int i; | |
3956 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3957 | if (rxq->pool[i].skb != NULL) { | |
3958 | pci_unmap_single(priv->pci_dev, | |
3959 | rxq->pool[i].dma_addr, | |
3960 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3961 | dev_kfree_skb(rxq->pool[i].skb); | |
3962 | } | |
3963 | } | |
3964 | ||
3965 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3966 | rxq->dma_addr); | |
3967 | rxq->bd = NULL; | |
3968 | } | |
3969 | ||
bb8c093b | 3970 | int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv) |
b481de9c | 3971 | { |
bb8c093b | 3972 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3973 | struct pci_dev *dev = priv->pci_dev; |
3974 | int i; | |
3975 | ||
3976 | spin_lock_init(&rxq->lock); | |
3977 | INIT_LIST_HEAD(&rxq->rx_free); | |
3978 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 BC |
3979 | |
3980 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3981 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3982 | if (!rxq->bd) | |
3983 | return -ENOMEM; | |
6440adb5 | 3984 | |
b481de9c ZY |
3985 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3986 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3987 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3988 | |
b481de9c ZY |
3989 | /* Set us so that we have processed and used all buffers, but have |
3990 | * not restocked the Rx queue with fresh buffers */ | |
3991 | rxq->read = rxq->write = 0; | |
3992 | rxq->free_count = 0; | |
3993 | rxq->need_update = 0; | |
3994 | return 0; | |
3995 | } | |
3996 | ||
bb8c093b | 3997 | void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
b481de9c ZY |
3998 | { |
3999 | unsigned long flags; | |
4000 | int i; | |
4001 | spin_lock_irqsave(&rxq->lock, flags); | |
4002 | INIT_LIST_HEAD(&rxq->rx_free); | |
4003 | INIT_LIST_HEAD(&rxq->rx_used); | |
4004 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
4005 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
4006 | /* In the reset function, these buffers may have been allocated | |
4007 | * to an SKB, so we need to unmap and free potential storage */ | |
4008 | if (rxq->pool[i].skb != NULL) { | |
4009 | pci_unmap_single(priv->pci_dev, | |
4010 | rxq->pool[i].dma_addr, | |
4011 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
4012 | priv->alloc_rxb_skb--; | |
4013 | dev_kfree_skb(rxq->pool[i].skb); | |
4014 | rxq->pool[i].skb = NULL; | |
4015 | } | |
4016 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
4017 | } | |
4018 | ||
4019 | /* Set us so that we have processed and used all buffers, but have | |
4020 | * not restocked the Rx queue with fresh buffers */ | |
4021 | rxq->read = rxq->write = 0; | |
4022 | rxq->free_count = 0; | |
4023 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4024 | } | |
4025 | ||
4026 | /* Convert linear signal-to-noise ratio into dB */ | |
4027 | static u8 ratio2dB[100] = { | |
4028 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
4029 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
4030 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
4031 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
4032 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
4033 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
4034 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
4035 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
4036 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
4037 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
4038 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
4039 | }; | |
4040 | ||
4041 | /* Calculates a relative dB value from a ratio of linear | |
4042 | * (i.e. not dB) signal levels. | |
4043 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 4044 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 4045 | { |
221c80cf AB |
4046 | /* 1000:1 or higher just report as 60 dB */ |
4047 | if (sig_ratio >= 1000) | |
b481de9c ZY |
4048 | return 60; |
4049 | ||
221c80cf | 4050 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 4051 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 4052 | if (sig_ratio >= 100) |
b481de9c ZY |
4053 | return (20 + (int)ratio2dB[sig_ratio/10]); |
4054 | ||
4055 | /* We shouldn't see this */ | |
4056 | if (sig_ratio < 1) | |
4057 | return 0; | |
4058 | ||
4059 | /* Use table for ratios 1:1 - 99:1 */ | |
4060 | return (int)ratio2dB[sig_ratio]; | |
4061 | } | |
4062 | ||
4063 | #define PERFECT_RSSI (-20) /* dBm */ | |
4064 | #define WORST_RSSI (-95) /* dBm */ | |
4065 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
4066 | ||
4067 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
4068 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
4069 | * about formulas used below. */ | |
bb8c093b | 4070 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
4071 | { |
4072 | int sig_qual; | |
4073 | int degradation = PERFECT_RSSI - rssi_dbm; | |
4074 | ||
4075 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
4076 | * as indicator; formula is (signal dbm - noise dbm). | |
4077 | * SNR at or above 40 is a great signal (100%). | |
4078 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
4079 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
4080 | if (noise_dbm) { | |
4081 | if (rssi_dbm - noise_dbm >= 40) | |
4082 | return 100; | |
4083 | else if (rssi_dbm < noise_dbm) | |
4084 | return 0; | |
4085 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
4086 | ||
4087 | /* Else use just the signal level. | |
4088 | * This formula is a least squares fit of data points collected and | |
4089 | * compared with a reference system that had a percentage (%) display | |
4090 | * for signal quality. */ | |
4091 | } else | |
4092 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
4093 | (15 * RSSI_RANGE + 62 * degradation)) / | |
4094 | (RSSI_RANGE * RSSI_RANGE); | |
4095 | ||
4096 | if (sig_qual > 100) | |
4097 | sig_qual = 100; | |
4098 | else if (sig_qual < 1) | |
4099 | sig_qual = 0; | |
4100 | ||
4101 | return sig_qual; | |
4102 | } | |
4103 | ||
4104 | /** | |
9fbab516 | 4105 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
4106 | * |
4107 | * Uses the priv->rx_handlers callback function array to invoke | |
4108 | * the appropriate handlers, including command responses, | |
4109 | * frame-received notifications, and other notifications. | |
4110 | */ | |
bb8c093b | 4111 | static void iwl3945_rx_handle(struct iwl3945_priv *priv) |
b481de9c | 4112 | { |
bb8c093b CH |
4113 | struct iwl3945_rx_mem_buffer *rxb; |
4114 | struct iwl3945_rx_packet *pkt; | |
4115 | struct iwl3945_rx_queue *rxq = &priv->rxq; | |
b481de9c ZY |
4116 | u32 r, i; |
4117 | int reclaim; | |
4118 | unsigned long flags; | |
5c0eef96 | 4119 | u8 fill_rx = 0; |
d68ab680 | 4120 | u32 count = 8; |
b481de9c | 4121 | |
6440adb5 BC |
4122 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
4123 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 4124 | r = iwl3945_hw_get_rx_read(priv); |
b481de9c ZY |
4125 | i = rxq->read; |
4126 | ||
5c0eef96 MA |
4127 | if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
4128 | fill_rx = 1; | |
b481de9c ZY |
4129 | /* Rx interrupt, but nothing sent from uCode */ |
4130 | if (i == r) | |
4131 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
4132 | ||
4133 | while (i != r) { | |
4134 | rxb = rxq->queue[i]; | |
4135 | ||
9fbab516 | 4136 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
4137 | * then a bug has been introduced in the queue refilling |
4138 | * routines -- catch it here */ | |
4139 | BUG_ON(rxb == NULL); | |
4140 | ||
4141 | rxq->queue[i] = NULL; | |
4142 | ||
4143 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, | |
4144 | IWL_RX_BUF_SIZE, | |
4145 | PCI_DMA_FROMDEVICE); | |
bb8c093b | 4146 | pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
b481de9c ZY |
4147 | |
4148 | /* Reclaim a command buffer only if this packet is a response | |
4149 | * to a (driver-originated) command. | |
4150 | * If the packet (e.g. Rx frame) originated from uCode, | |
4151 | * there is no command buffer to reclaim. | |
4152 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
4153 | * but apparently a few don't get set; catch them here. */ | |
4154 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
4155 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
4156 | (pkt->hdr.cmd != REPLY_TX); | |
4157 | ||
4158 | /* Based on type of command response or notification, | |
4159 | * handle those that need handling via function in | |
bb8c093b | 4160 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c ZY |
4161 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
4162 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4163 | "r = %d, i = %d, %s, 0x%02x\n", r, i, | |
4164 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
4165 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
4166 | } else { | |
4167 | /* No handling needed */ | |
4168 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4169 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
4170 | r, i, get_cmd_string(pkt->hdr.cmd), | |
4171 | pkt->hdr.cmd); | |
4172 | } | |
4173 | ||
4174 | if (reclaim) { | |
9fbab516 BC |
4175 | /* Invoke any callbacks, transfer the skb to caller, and |
4176 | * fire off the (possibly) blocking iwl3945_send_cmd() | |
b481de9c ZY |
4177 | * as we reclaim the driver command queue */ |
4178 | if (rxb && rxb->skb) | |
bb8c093b | 4179 | iwl3945_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
4180 | else |
4181 | IWL_WARNING("Claim null rxb?\n"); | |
4182 | } | |
4183 | ||
4184 | /* For now we just don't re-use anything. We can tweak this | |
4185 | * later to try and re-use notification packets and SKBs that | |
4186 | * fail to Rx correctly */ | |
4187 | if (rxb->skb != NULL) { | |
4188 | priv->alloc_rxb_skb--; | |
4189 | dev_kfree_skb_any(rxb->skb); | |
4190 | rxb->skb = NULL; | |
4191 | } | |
4192 | ||
4193 | pci_unmap_single(priv->pci_dev, rxb->dma_addr, | |
4194 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
4195 | spin_lock_irqsave(&rxq->lock, flags); | |
4196 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
4197 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4198 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
4199 | /* If there are a lot of unused frames, |
4200 | * restock the Rx queue so ucode won't assert. */ | |
4201 | if (fill_rx) { | |
4202 | count++; | |
4203 | if (count >= 8) { | |
4204 | priv->rxq.read = i; | |
4205 | __iwl3945_rx_replenish(priv); | |
4206 | count = 0; | |
4207 | } | |
4208 | } | |
b481de9c ZY |
4209 | } |
4210 | ||
4211 | /* Backtrack one entry */ | |
4212 | priv->rxq.read = i; | |
bb8c093b | 4213 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
4214 | } |
4215 | ||
6440adb5 BC |
4216 | /** |
4217 | * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware | |
4218 | */ | |
bb8c093b CH |
4219 | static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv, |
4220 | struct iwl3945_tx_queue *txq) | |
b481de9c ZY |
4221 | { |
4222 | u32 reg = 0; | |
4223 | int rc = 0; | |
4224 | int txq_id = txq->q.id; | |
4225 | ||
4226 | if (txq->need_update == 0) | |
4227 | return rc; | |
4228 | ||
4229 | /* if we're trying to save power */ | |
4230 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
4231 | /* wake up nic if it's powered down ... | |
4232 | * uCode will wake up, and interrupt us again, so next | |
4233 | * time we'll skip this part. */ | |
bb8c093b | 4234 | reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
4235 | |
4236 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
4237 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
bb8c093b | 4238 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
4239 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4240 | return rc; | |
4241 | } | |
4242 | ||
4243 | /* restore this queue's parameters in nic hardware. */ | |
bb8c093b | 4244 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4245 | if (rc) |
4246 | return rc; | |
bb8c093b | 4247 | iwl3945_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4248 | txq->q.write_ptr | (txq_id << 8)); |
bb8c093b | 4249 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4250 | |
4251 | /* else not in power-save mode, uCode will never sleep when we're | |
4252 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
4253 | } else | |
bb8c093b | 4254 | iwl3945_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4255 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
4256 | |
4257 | txq->need_update = 0; | |
4258 | ||
4259 | return rc; | |
4260 | } | |
4261 | ||
c8b0e6e1 | 4262 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4263 | static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon) |
b481de9c | 4264 | { |
0795af57 JP |
4265 | DECLARE_MAC_BUF(mac); |
4266 | ||
b481de9c | 4267 | IWL_DEBUG_RADIO("RX CONFIG:\n"); |
bb8c093b | 4268 | iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
4269 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
4270 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
4271 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
4272 | le32_to_cpu(rxon->filter_flags)); | |
4273 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
4274 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
4275 | rxon->ofdm_basic_rates); | |
4276 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
0795af57 JP |
4277 | IWL_DEBUG_RADIO("u8[6] node_addr: %s\n", |
4278 | print_mac(mac, rxon->node_addr)); | |
4279 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n", | |
4280 | print_mac(mac, rxon->bssid_addr)); | |
b481de9c ZY |
4281 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
4282 | } | |
4283 | #endif | |
4284 | ||
bb8c093b | 4285 | static void iwl3945_enable_interrupts(struct iwl3945_priv *priv) |
b481de9c ZY |
4286 | { |
4287 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
4288 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
bb8c093b | 4289 | iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
4290 | } |
4291 | ||
bb8c093b | 4292 | static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv) |
b481de9c ZY |
4293 | { |
4294 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
4295 | ||
4296 | /* disable interrupts from uCode/NIC to host */ | |
bb8c093b | 4297 | iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
4298 | |
4299 | /* acknowledge/clear/reset any interrupts still pending | |
4300 | * from uCode or flow handler (Rx/Tx DMA) */ | |
bb8c093b CH |
4301 | iwl3945_write32(priv, CSR_INT, 0xffffffff); |
4302 | iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
4303 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
4304 | } | |
4305 | ||
4306 | static const char *desc_lookup(int i) | |
4307 | { | |
4308 | switch (i) { | |
4309 | case 1: | |
4310 | return "FAIL"; | |
4311 | case 2: | |
4312 | return "BAD_PARAM"; | |
4313 | case 3: | |
4314 | return "BAD_CHECKSUM"; | |
4315 | case 4: | |
4316 | return "NMI_INTERRUPT"; | |
4317 | case 5: | |
4318 | return "SYSASSERT"; | |
4319 | case 6: | |
4320 | return "FATAL_ERROR"; | |
4321 | } | |
4322 | ||
4323 | return "UNKNOWN"; | |
4324 | } | |
4325 | ||
4326 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
4327 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
4328 | ||
bb8c093b | 4329 | static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv) |
b481de9c ZY |
4330 | { |
4331 | u32 i; | |
4332 | u32 desc, time, count, base, data1; | |
4333 | u32 blink1, blink2, ilink1, ilink2; | |
4334 | int rc; | |
4335 | ||
4336 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
4337 | ||
bb8c093b | 4338 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4339 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
4340 | return; | |
4341 | } | |
4342 | ||
bb8c093b | 4343 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4344 | if (rc) { |
4345 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4346 | return; | |
4347 | } | |
4348 | ||
bb8c093b | 4349 | count = iwl3945_read_targ_mem(priv, base); |
b481de9c ZY |
4350 | |
4351 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
4352 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 4353 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
4354 | } |
4355 | ||
4356 | IWL_ERROR("Desc Time asrtPC blink2 " | |
4357 | "ilink1 nmiPC Line\n"); | |
4358 | for (i = ERROR_START_OFFSET; | |
4359 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
4360 | i += ERROR_ELEM_SIZE) { | |
bb8c093b | 4361 | desc = iwl3945_read_targ_mem(priv, base + i); |
b481de9c | 4362 | time = |
bb8c093b | 4363 | iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 4364 | blink1 = |
bb8c093b | 4365 | iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 4366 | blink2 = |
bb8c093b | 4367 | iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 4368 | ilink1 = |
bb8c093b | 4369 | iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 4370 | ilink2 = |
bb8c093b | 4371 | iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 4372 | data1 = |
bb8c093b | 4373 | iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c ZY |
4374 | |
4375 | IWL_ERROR | |
4376 | ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
4377 | desc_lookup(desc), desc, time, blink1, blink2, | |
4378 | ilink1, ilink2, data1); | |
4379 | } | |
4380 | ||
bb8c093b | 4381 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4382 | |
4383 | } | |
4384 | ||
f58177b9 | 4385 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
4386 | |
4387 | /** | |
bb8c093b | 4388 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 4389 | * |
bb8c093b | 4390 | * NOTE: Must be called with iwl3945_grab_nic_access() already obtained! |
b481de9c | 4391 | */ |
bb8c093b | 4392 | static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx, |
b481de9c ZY |
4393 | u32 num_events, u32 mode) |
4394 | { | |
4395 | u32 i; | |
4396 | u32 base; /* SRAM byte address of event log header */ | |
4397 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4398 | u32 ptr; /* SRAM byte address of log data */ | |
4399 | u32 ev, time, data; /* event log data */ | |
4400 | ||
4401 | if (num_events == 0) | |
4402 | return; | |
4403 | ||
4404 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4405 | ||
4406 | if (mode == 0) | |
4407 | event_size = 2 * sizeof(u32); | |
4408 | else | |
4409 | event_size = 3 * sizeof(u32); | |
4410 | ||
4411 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4412 | ||
4413 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4414 | * place event id # at far right for easier visual parsing. */ | |
4415 | for (i = 0; i < num_events; i++) { | |
bb8c093b | 4416 | ev = iwl3945_read_targ_mem(priv, ptr); |
b481de9c | 4417 | ptr += sizeof(u32); |
bb8c093b | 4418 | time = iwl3945_read_targ_mem(priv, ptr); |
b481de9c ZY |
4419 | ptr += sizeof(u32); |
4420 | if (mode == 0) | |
4421 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4422 | else { | |
bb8c093b | 4423 | data = iwl3945_read_targ_mem(priv, ptr); |
b481de9c ZY |
4424 | ptr += sizeof(u32); |
4425 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4426 | } | |
4427 | } | |
4428 | } | |
4429 | ||
bb8c093b | 4430 | static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv) |
b481de9c ZY |
4431 | { |
4432 | int rc; | |
4433 | u32 base; /* SRAM byte address of event log header */ | |
4434 | u32 capacity; /* event log capacity in # entries */ | |
4435 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4436 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4437 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4438 | u32 size; /* # entries that we'll print */ | |
4439 | ||
4440 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 4441 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4442 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4443 | return; | |
4444 | } | |
4445 | ||
bb8c093b | 4446 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4447 | if (rc) { |
4448 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4449 | return; | |
4450 | } | |
4451 | ||
4452 | /* event log header */ | |
bb8c093b CH |
4453 | capacity = iwl3945_read_targ_mem(priv, base); |
4454 | mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4455 | num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4456 | next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4457 | |
4458 | size = num_wraps ? capacity : next_entry; | |
4459 | ||
4460 | /* bail out if nothing in log */ | |
4461 | if (size == 0) { | |
583fab37 | 4462 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
bb8c093b | 4463 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4464 | return; |
4465 | } | |
4466 | ||
583fab37 | 4467 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4468 | size, num_wraps); |
4469 | ||
4470 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4471 | * i.e the next one that uCode would fill. */ | |
4472 | if (num_wraps) | |
bb8c093b | 4473 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
4474 | capacity - next_entry, mode); |
4475 | ||
4476 | /* (then/else) start at top of log */ | |
bb8c093b | 4477 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4478 | |
bb8c093b | 4479 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4480 | } |
4481 | ||
4482 | /** | |
bb8c093b | 4483 | * iwl3945_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4484 | */ |
bb8c093b | 4485 | static void iwl3945_irq_handle_error(struct iwl3945_priv *priv) |
b481de9c | 4486 | { |
bb8c093b | 4487 | /* Set the FW error flag -- cleared on iwl3945_down */ |
b481de9c ZY |
4488 | set_bit(STATUS_FW_ERROR, &priv->status); |
4489 | ||
4490 | /* Cancel currently queued command. */ | |
4491 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4492 | ||
c8b0e6e1 | 4493 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
4494 | if (iwl3945_debug_level & IWL_DL_FW_ERRORS) { |
4495 | iwl3945_dump_nic_error_log(priv); | |
4496 | iwl3945_dump_nic_event_log(priv); | |
4497 | iwl3945_print_rx_config_cmd(&priv->staging_rxon); | |
b481de9c ZY |
4498 | } |
4499 | #endif | |
4500 | ||
4501 | wake_up_interruptible(&priv->wait_command_queue); | |
4502 | ||
4503 | /* Keep the restart process from trying to send host | |
4504 | * commands by clearing the INIT status bit */ | |
4505 | clear_bit(STATUS_READY, &priv->status); | |
4506 | ||
4507 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4508 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4509 | "Restarting adapter due to uCode error.\n"); | |
4510 | ||
bb8c093b | 4511 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4512 | memcpy(&priv->recovery_rxon, &priv->active_rxon, |
4513 | sizeof(priv->recovery_rxon)); | |
4514 | priv->error_recovering = 1; | |
4515 | } | |
4516 | queue_work(priv->workqueue, &priv->restart); | |
4517 | } | |
4518 | } | |
4519 | ||
bb8c093b | 4520 | static void iwl3945_error_recovery(struct iwl3945_priv *priv) |
b481de9c ZY |
4521 | { |
4522 | unsigned long flags; | |
4523 | ||
4524 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
4525 | sizeof(priv->staging_rxon)); | |
4526 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4527 | iwl3945_commit_rxon(priv); |
b481de9c | 4528 | |
bb8c093b | 4529 | iwl3945_add_station(priv, priv->bssid, 1, 0); |
b481de9c ZY |
4530 | |
4531 | spin_lock_irqsave(&priv->lock, flags); | |
4532 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
4533 | priv->error_recovering = 0; | |
4534 | spin_unlock_irqrestore(&priv->lock, flags); | |
4535 | } | |
4536 | ||
bb8c093b | 4537 | static void iwl3945_irq_tasklet(struct iwl3945_priv *priv) |
b481de9c ZY |
4538 | { |
4539 | u32 inta, handled = 0; | |
4540 | u32 inta_fh; | |
4541 | unsigned long flags; | |
c8b0e6e1 | 4542 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
4543 | u32 inta_mask; |
4544 | #endif | |
4545 | ||
4546 | spin_lock_irqsave(&priv->lock, flags); | |
4547 | ||
4548 | /* Ack/clear/reset pending uCode interrupts. | |
4549 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4550 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
bb8c093b CH |
4551 | inta = iwl3945_read32(priv, CSR_INT); |
4552 | iwl3945_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4553 | |
4554 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4555 | * Any new interrupts that happen after this, either while we're | |
4556 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
bb8c093b CH |
4557 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); |
4558 | iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4559 | |
c8b0e6e1 | 4560 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4561 | if (iwl3945_debug_level & IWL_DL_ISR) { |
9fbab516 BC |
4562 | /* just for debug */ |
4563 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); | |
b481de9c ZY |
4564 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4565 | inta, inta_mask, inta_fh); | |
4566 | } | |
4567 | #endif | |
4568 | ||
4569 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4570 | * atomic, make sure that inta covers all the interrupts that | |
4571 | * we've discovered, even if FH interrupt came in just after | |
4572 | * reading CSR_INT. */ | |
6f83eaa1 | 4573 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 4574 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4575 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
4576 | inta |= CSR_INT_BIT_FH_TX; |
4577 | ||
4578 | /* Now service all interrupt bits discovered above. */ | |
4579 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4580 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4581 | ||
4582 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4583 | iwl3945_disable_interrupts(priv); |
b481de9c | 4584 | |
bb8c093b | 4585 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4586 | |
4587 | handled |= CSR_INT_BIT_HW_ERR; | |
4588 | ||
4589 | spin_unlock_irqrestore(&priv->lock, flags); | |
4590 | ||
4591 | return; | |
4592 | } | |
4593 | ||
c8b0e6e1 | 4594 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4595 | if (iwl3945_debug_level & (IWL_DL_ISR)) { |
b481de9c | 4596 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4597 | if (inta & CSR_INT_BIT_SCD) |
4598 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4599 | "the frame/frames.\n"); | |
b481de9c ZY |
4600 | |
4601 | /* Alive notification via Rx interrupt will do the real work */ | |
4602 | if (inta & CSR_INT_BIT_ALIVE) | |
4603 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4604 | } | |
4605 | #endif | |
4606 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4607 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c ZY |
4608 | |
4609 | /* HW RF KILL switch toggled (4965 only) */ | |
4610 | if (inta & CSR_INT_BIT_RF_KILL) { | |
4611 | int hw_rf_kill = 0; | |
bb8c093b | 4612 | if (!(iwl3945_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
4613 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
4614 | hw_rf_kill = 1; | |
4615 | ||
4616 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, | |
4617 | "RF_KILL bit toggled to %s.\n", | |
4618 | hw_rf_kill ? "disable radio":"enable radio"); | |
4619 | ||
4620 | /* Queue restart only if RF_KILL switch was set to "kill" | |
4621 | * when we loaded driver, and is now set to "enable". | |
4622 | * After we're Alive, RF_KILL gets handled by | |
3230455d | 4623 | * iwl3945_rx_card_state_notif() */ |
53e49093 ZY |
4624 | if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { |
4625 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
b481de9c | 4626 | queue_work(priv->workqueue, &priv->restart); |
53e49093 | 4627 | } |
b481de9c ZY |
4628 | |
4629 | handled |= CSR_INT_BIT_RF_KILL; | |
4630 | } | |
4631 | ||
4632 | /* Chip got too hot and stopped itself (4965 only) */ | |
4633 | if (inta & CSR_INT_BIT_CT_KILL) { | |
4634 | IWL_ERROR("Microcode CT kill error detected.\n"); | |
4635 | handled |= CSR_INT_BIT_CT_KILL; | |
4636 | } | |
4637 | ||
4638 | /* Error detected by uCode */ | |
4639 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4640 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4641 | inta); | |
bb8c093b | 4642 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4643 | handled |= CSR_INT_BIT_SW_ERR; |
4644 | } | |
4645 | ||
4646 | /* uCode wakes up after power-down sleep */ | |
4647 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4648 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b CH |
4649 | iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq); |
4650 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]); | |
4651 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]); | |
4652 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]); | |
4653 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]); | |
4654 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]); | |
4655 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
4656 | |
4657 | handled |= CSR_INT_BIT_WAKEUP; | |
4658 | } | |
4659 | ||
4660 | /* All uCode command responses, including Tx command responses, | |
4661 | * Rx "responses" (frame-received notification), and other | |
4662 | * notifications from uCode come through here*/ | |
4663 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4664 | iwl3945_rx_handle(priv); |
b481de9c ZY |
4665 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4666 | } | |
4667 | ||
4668 | if (inta & CSR_INT_BIT_FH_TX) { | |
4669 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4670 | ||
bb8c093b CH |
4671 | iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
4672 | if (!iwl3945_grab_nic_access(priv)) { | |
4673 | iwl3945_write_direct32(priv, | |
b481de9c ZY |
4674 | FH_TCSR_CREDIT |
4675 | (ALM_FH_SRVC_CHNL), 0x0); | |
bb8c093b | 4676 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4677 | } |
4678 | handled |= CSR_INT_BIT_FH_TX; | |
4679 | } | |
4680 | ||
4681 | if (inta & ~handled) | |
4682 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4683 | ||
4684 | if (inta & ~CSR_INI_SET_MASK) { | |
4685 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4686 | inta & ~CSR_INI_SET_MASK); | |
4687 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4688 | } | |
4689 | ||
4690 | /* Re-enable all interrupts */ | |
bb8c093b | 4691 | iwl3945_enable_interrupts(priv); |
b481de9c | 4692 | |
c8b0e6e1 | 4693 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
4694 | if (iwl3945_debug_level & (IWL_DL_ISR)) { |
4695 | inta = iwl3945_read32(priv, CSR_INT); | |
4696 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); | |
4697 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4698 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4699 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4700 | } | |
4701 | #endif | |
4702 | spin_unlock_irqrestore(&priv->lock, flags); | |
4703 | } | |
4704 | ||
bb8c093b | 4705 | static irqreturn_t iwl3945_isr(int irq, void *data) |
b481de9c | 4706 | { |
bb8c093b | 4707 | struct iwl3945_priv *priv = data; |
b481de9c ZY |
4708 | u32 inta, inta_mask; |
4709 | u32 inta_fh; | |
4710 | if (!priv) | |
4711 | return IRQ_NONE; | |
4712 | ||
4713 | spin_lock(&priv->lock); | |
4714 | ||
4715 | /* Disable (but don't clear!) interrupts here to avoid | |
4716 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4717 | * If we have something to service, the tasklet will re-enable ints. | |
4718 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
bb8c093b CH |
4719 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */ |
4720 | iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4721 | |
4722 | /* Discover which interrupts are active/pending */ | |
bb8c093b CH |
4723 | inta = iwl3945_read32(priv, CSR_INT); |
4724 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4725 | |
4726 | /* Ignore interrupt if there's nothing in NIC to service. | |
4727 | * This may be due to IRQ shared with another device, | |
4728 | * or due to sporadic interrupts thrown from our NIC. */ | |
4729 | if (!inta && !inta_fh) { | |
4730 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4731 | goto none; | |
4732 | } | |
4733 | ||
4734 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
4735 | /* Hardware disappeared */ | |
4736 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta); | |
cb4da1a3 | 4737 | goto unplugged; |
b481de9c ZY |
4738 | } |
4739 | ||
4740 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4741 | inta, inta_mask, inta_fh); | |
4742 | ||
25c03d8e JP |
4743 | inta &= ~CSR_INT_BIT_SCD; |
4744 | ||
bb8c093b | 4745 | /* iwl3945_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4746 | if (likely(inta || inta_fh)) |
4747 | tasklet_schedule(&priv->irq_tasklet); | |
cb4da1a3 | 4748 | unplugged: |
b481de9c ZY |
4749 | spin_unlock(&priv->lock); |
4750 | ||
4751 | return IRQ_HANDLED; | |
4752 | ||
4753 | none: | |
4754 | /* re-enable interrupts here since we don't have anything to service. */ | |
bb8c093b | 4755 | iwl3945_enable_interrupts(priv); |
b481de9c ZY |
4756 | spin_unlock(&priv->lock); |
4757 | return IRQ_NONE; | |
4758 | } | |
4759 | ||
4760 | /************************** EEPROM BANDS **************************** | |
4761 | * | |
bb8c093b | 4762 | * The iwl3945_eeprom_band definitions below provide the mapping from the |
b481de9c ZY |
4763 | * EEPROM contents to the specific channel number supported for each |
4764 | * band. | |
4765 | * | |
bb8c093b | 4766 | * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3 |
b481de9c ZY |
4767 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. |
4768 | * The specific geography and calibration information for that channel | |
4769 | * is contained in the eeprom map itself. | |
4770 | * | |
4771 | * During init, we copy the eeprom information and channel map | |
4772 | * information into priv->channel_info_24/52 and priv->channel_map_24/52 | |
4773 | * | |
4774 | * channel_map_24/52 provides the index in the channel_info array for a | |
4775 | * given channel. We have to have two separate maps as there is channel | |
4776 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
4777 | * band_2 | |
4778 | * | |
4779 | * A value of 0xff stored in the channel_map indicates that the channel | |
4780 | * is not supported by the hardware at all. | |
4781 | * | |
4782 | * A value of 0xfe in the channel_map indicates that the channel is not | |
4783 | * valid for Tx with the current hardware. This means that | |
4784 | * while the system can tune and receive on a given channel, it may not | |
4785 | * be able to associate or transmit any frames on that | |
4786 | * channel. There is no corresponding channel information for that | |
4787 | * entry. | |
4788 | * | |
4789 | *********************************************************************/ | |
4790 | ||
4791 | /* 2.4 GHz */ | |
bb8c093b | 4792 | static const u8 iwl3945_eeprom_band_1[14] = { |
b481de9c ZY |
4793 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
4794 | }; | |
4795 | ||
4796 | /* 5.2 GHz bands */ | |
9fbab516 | 4797 | static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */ |
b481de9c ZY |
4798 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 |
4799 | }; | |
4800 | ||
9fbab516 | 4801 | static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */ |
b481de9c ZY |
4802 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
4803 | }; | |
4804 | ||
bb8c093b | 4805 | static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */ |
b481de9c ZY |
4806 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
4807 | }; | |
4808 | ||
bb8c093b | 4809 | static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */ |
b481de9c ZY |
4810 | 145, 149, 153, 157, 161, 165 |
4811 | }; | |
4812 | ||
bb8c093b | 4813 | static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band, |
b481de9c | 4814 | int *eeprom_ch_count, |
bb8c093b | 4815 | const struct iwl3945_eeprom_channel |
b481de9c ZY |
4816 | **eeprom_ch_info, |
4817 | const u8 **eeprom_ch_index) | |
4818 | { | |
4819 | switch (band) { | |
4820 | case 1: /* 2.4GHz band */ | |
bb8c093b | 4821 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1); |
b481de9c | 4822 | *eeprom_ch_info = priv->eeprom.band_1_channels; |
bb8c093b | 4823 | *eeprom_ch_index = iwl3945_eeprom_band_1; |
b481de9c | 4824 | break; |
9fbab516 | 4825 | case 2: /* 4.9GHz band */ |
bb8c093b | 4826 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2); |
b481de9c | 4827 | *eeprom_ch_info = priv->eeprom.band_2_channels; |
bb8c093b | 4828 | *eeprom_ch_index = iwl3945_eeprom_band_2; |
b481de9c ZY |
4829 | break; |
4830 | case 3: /* 5.2GHz band */ | |
bb8c093b | 4831 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3); |
b481de9c | 4832 | *eeprom_ch_info = priv->eeprom.band_3_channels; |
bb8c093b | 4833 | *eeprom_ch_index = iwl3945_eeprom_band_3; |
b481de9c | 4834 | break; |
9fbab516 | 4835 | case 4: /* 5.5GHz band */ |
bb8c093b | 4836 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4); |
b481de9c | 4837 | *eeprom_ch_info = priv->eeprom.band_4_channels; |
bb8c093b | 4838 | *eeprom_ch_index = iwl3945_eeprom_band_4; |
b481de9c | 4839 | break; |
9fbab516 | 4840 | case 5: /* 5.7GHz band */ |
bb8c093b | 4841 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5); |
b481de9c | 4842 | *eeprom_ch_info = priv->eeprom.band_5_channels; |
bb8c093b | 4843 | *eeprom_ch_index = iwl3945_eeprom_band_5; |
b481de9c ZY |
4844 | break; |
4845 | default: | |
4846 | BUG(); | |
4847 | return; | |
4848 | } | |
4849 | } | |
4850 | ||
6440adb5 BC |
4851 | /** |
4852 | * iwl3945_get_channel_info - Find driver's private channel info | |
4853 | * | |
4854 | * Based on band and channel number. | |
4855 | */ | |
bb8c093b | 4856 | const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv, |
8318d78a | 4857 | enum ieee80211_band band, u16 channel) |
b481de9c ZY |
4858 | { |
4859 | int i; | |
4860 | ||
8318d78a JB |
4861 | switch (band) { |
4862 | case IEEE80211_BAND_5GHZ: | |
b481de9c ZY |
4863 | for (i = 14; i < priv->channel_count; i++) { |
4864 | if (priv->channel_info[i].channel == channel) | |
4865 | return &priv->channel_info[i]; | |
4866 | } | |
4867 | break; | |
4868 | ||
8318d78a | 4869 | case IEEE80211_BAND_2GHZ: |
b481de9c ZY |
4870 | if (channel >= 1 && channel <= 14) |
4871 | return &priv->channel_info[channel - 1]; | |
4872 | break; | |
8318d78a JB |
4873 | case IEEE80211_NUM_BANDS: |
4874 | WARN_ON(1); | |
b481de9c ZY |
4875 | } |
4876 | ||
4877 | return NULL; | |
4878 | } | |
4879 | ||
4880 | #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
4881 | ? # x " " : "") | |
4882 | ||
6440adb5 BC |
4883 | /** |
4884 | * iwl3945_init_channel_map - Set up driver's info for all possible channels | |
4885 | */ | |
bb8c093b | 4886 | static int iwl3945_init_channel_map(struct iwl3945_priv *priv) |
b481de9c ZY |
4887 | { |
4888 | int eeprom_ch_count = 0; | |
4889 | const u8 *eeprom_ch_index = NULL; | |
bb8c093b | 4890 | const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL; |
b481de9c | 4891 | int band, ch; |
bb8c093b | 4892 | struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
4893 | |
4894 | if (priv->channel_count) { | |
4895 | IWL_DEBUG_INFO("Channel map already initialized.\n"); | |
4896 | return 0; | |
4897 | } | |
4898 | ||
4899 | if (priv->eeprom.version < 0x2f) { | |
4900 | IWL_WARNING("Unsupported EEPROM version: 0x%04X\n", | |
4901 | priv->eeprom.version); | |
4902 | return -EINVAL; | |
4903 | } | |
4904 | ||
4905 | IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n"); | |
4906 | ||
4907 | priv->channel_count = | |
bb8c093b CH |
4908 | ARRAY_SIZE(iwl3945_eeprom_band_1) + |
4909 | ARRAY_SIZE(iwl3945_eeprom_band_2) + | |
4910 | ARRAY_SIZE(iwl3945_eeprom_band_3) + | |
4911 | ARRAY_SIZE(iwl3945_eeprom_band_4) + | |
4912 | ARRAY_SIZE(iwl3945_eeprom_band_5); | |
b481de9c ZY |
4913 | |
4914 | IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count); | |
4915 | ||
bb8c093b | 4916 | priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) * |
b481de9c ZY |
4917 | priv->channel_count, GFP_KERNEL); |
4918 | if (!priv->channel_info) { | |
4919 | IWL_ERROR("Could not allocate channel_info\n"); | |
4920 | priv->channel_count = 0; | |
4921 | return -ENOMEM; | |
4922 | } | |
4923 | ||
4924 | ch_info = priv->channel_info; | |
4925 | ||
4926 | /* Loop through the 5 EEPROM bands adding them in order to the | |
4927 | * channel map we maintain (that contains additional information than | |
4928 | * what just in the EEPROM) */ | |
4929 | for (band = 1; band <= 5; band++) { | |
4930 | ||
bb8c093b | 4931 | iwl3945_init_band_reference(priv, band, &eeprom_ch_count, |
b481de9c ZY |
4932 | &eeprom_ch_info, &eeprom_ch_index); |
4933 | ||
4934 | /* Loop through each band adding each of the channels */ | |
4935 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
4936 | ch_info->channel = eeprom_ch_index[ch]; | |
8318d78a JB |
4937 | ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ : |
4938 | IEEE80211_BAND_5GHZ; | |
b481de9c ZY |
4939 | |
4940 | /* permanently store EEPROM's channel regulatory flags | |
4941 | * and max power in channel info database. */ | |
4942 | ch_info->eeprom = eeprom_ch_info[ch]; | |
4943 | ||
4944 | /* Copy the run-time flags so they are there even on | |
4945 | * invalid channels */ | |
4946 | ch_info->flags = eeprom_ch_info[ch].flags; | |
4947 | ||
4948 | if (!(is_channel_valid(ch_info))) { | |
4949 | IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - " | |
4950 | "No traffic\n", | |
4951 | ch_info->channel, | |
4952 | ch_info->flags, | |
4953 | is_channel_a_band(ch_info) ? | |
4954 | "5.2" : "2.4"); | |
4955 | ch_info++; | |
4956 | continue; | |
4957 | } | |
4958 | ||
4959 | /* Initialize regulatory-based run-time data */ | |
4960 | ch_info->max_power_avg = ch_info->curr_txpow = | |
4961 | eeprom_ch_info[ch].max_power_avg; | |
4962 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
4963 | ch_info->min_power = 0; | |
4964 | ||
8211ef78 | 4965 | IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x" |
b481de9c ZY |
4966 | " %ddBm): Ad-Hoc %ssupported\n", |
4967 | ch_info->channel, | |
4968 | is_channel_a_band(ch_info) ? | |
4969 | "5.2" : "2.4", | |
8211ef78 | 4970 | CHECK_AND_PRINT(VALID), |
b481de9c ZY |
4971 | CHECK_AND_PRINT(IBSS), |
4972 | CHECK_AND_PRINT(ACTIVE), | |
4973 | CHECK_AND_PRINT(RADAR), | |
4974 | CHECK_AND_PRINT(WIDE), | |
4975 | CHECK_AND_PRINT(NARROW), | |
4976 | CHECK_AND_PRINT(DFS), | |
4977 | eeprom_ch_info[ch].flags, | |
4978 | eeprom_ch_info[ch].max_power_avg, | |
4979 | ((eeprom_ch_info[ch]. | |
4980 | flags & EEPROM_CHANNEL_IBSS) | |
4981 | && !(eeprom_ch_info[ch]. | |
4982 | flags & EEPROM_CHANNEL_RADAR)) | |
4983 | ? "" : "not "); | |
4984 | ||
4985 | /* Set the user_txpower_limit to the highest power | |
4986 | * supported by any channel */ | |
4987 | if (eeprom_ch_info[ch].max_power_avg > | |
4988 | priv->user_txpower_limit) | |
4989 | priv->user_txpower_limit = | |
4990 | eeprom_ch_info[ch].max_power_avg; | |
4991 | ||
4992 | ch_info++; | |
4993 | } | |
4994 | } | |
4995 | ||
6440adb5 | 4996 | /* Set up txpower settings in driver for all channels */ |
b481de9c ZY |
4997 | if (iwl3945_txpower_set_from_eeprom(priv)) |
4998 | return -EIO; | |
4999 | ||
5000 | return 0; | |
5001 | } | |
5002 | ||
849e0dce RC |
5003 | /* |
5004 | * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map | |
5005 | */ | |
5006 | static void iwl3945_free_channel_map(struct iwl3945_priv *priv) | |
5007 | { | |
5008 | kfree(priv->channel_info); | |
5009 | priv->channel_count = 0; | |
5010 | } | |
5011 | ||
b481de9c ZY |
5012 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
5013 | * sending probe req. This should be set long enough to hear probe responses | |
5014 | * from more than one AP. */ | |
5015 | #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
5016 | #define IWL_ACTIVE_DWELL_TIME_52 (10) | |
5017 | ||
5018 | /* For faster active scanning, scan will move to the next channel if fewer than | |
5019 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
5020 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
5021 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
5022 | * no other traffic). | |
5023 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
5024 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
5025 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */ | |
5026 | ||
5027 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
5028 | * Must be set longer than active dwell time. | |
5029 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
5030 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
5031 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
5032 | #define IWL_PASSIVE_DWELL_BASE (100) | |
5033 | #define IWL_CHANNEL_TUNE_TIME 5 | |
5034 | ||
8318d78a JB |
5035 | static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, |
5036 | enum ieee80211_band band) | |
b481de9c | 5037 | { |
8318d78a | 5038 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
5039 | return IWL_ACTIVE_DWELL_TIME_52; |
5040 | else | |
5041 | return IWL_ACTIVE_DWELL_TIME_24; | |
5042 | } | |
5043 | ||
8318d78a JB |
5044 | static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, |
5045 | enum ieee80211_band band) | |
b481de9c | 5046 | { |
8318d78a JB |
5047 | u16 active = iwl3945_get_active_dwell_time(priv, band); |
5048 | u16 passive = (band == IEEE80211_BAND_2GHZ) ? | |
b481de9c ZY |
5049 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
5050 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
5051 | ||
bb8c093b | 5052 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
5053 | /* If we're associated, we clamp the maximum passive |
5054 | * dwell time to be 98% of the beacon interval (minus | |
5055 | * 2 * channel tune time) */ | |
5056 | passive = priv->beacon_int; | |
5057 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
5058 | passive = IWL_PASSIVE_DWELL_BASE; | |
5059 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
5060 | } | |
5061 | ||
5062 | if (passive <= active) | |
5063 | passive = active + 1; | |
5064 | ||
5065 | return passive; | |
5066 | } | |
5067 | ||
8318d78a JB |
5068 | static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, |
5069 | enum ieee80211_band band, | |
b481de9c | 5070 | u8 is_active, u8 direct_mask, |
bb8c093b | 5071 | struct iwl3945_scan_channel *scan_ch) |
b481de9c ZY |
5072 | { |
5073 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 5074 | const struct ieee80211_supported_band *sband; |
bb8c093b | 5075 | const struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
5076 | u16 passive_dwell = 0; |
5077 | u16 active_dwell = 0; | |
5078 | int added, i; | |
5079 | ||
8318d78a JB |
5080 | sband = iwl3945_get_band(priv, band); |
5081 | if (!sband) | |
b481de9c ZY |
5082 | return 0; |
5083 | ||
8318d78a | 5084 | channels = sband->channels; |
b481de9c | 5085 | |
8318d78a JB |
5086 | active_dwell = iwl3945_get_active_dwell_time(priv, band); |
5087 | passive_dwell = iwl3945_get_passive_dwell_time(priv, band); | |
b481de9c | 5088 | |
8318d78a JB |
5089 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
5090 | if (channels[i].hw_value == | |
b481de9c | 5091 | le16_to_cpu(priv->active_rxon.channel)) { |
bb8c093b | 5092 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
5093 | IWL_DEBUG_SCAN |
5094 | ("Skipping current channel %d\n", | |
5095 | le16_to_cpu(priv->active_rxon.channel)); | |
5096 | continue; | |
5097 | } | |
5098 | } else if (priv->only_active_channel) | |
5099 | continue; | |
5100 | ||
8318d78a | 5101 | scan_ch->channel = channels[i].hw_value; |
b481de9c | 5102 | |
8318d78a | 5103 | ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel); |
b481de9c ZY |
5104 | if (!is_channel_valid(ch_info)) { |
5105 | IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n", | |
5106 | scan_ch->channel); | |
5107 | continue; | |
5108 | } | |
5109 | ||
5110 | if (!is_active || is_channel_passive(ch_info) || | |
8318d78a | 5111 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) |
b481de9c ZY |
5112 | scan_ch->type = 0; /* passive */ |
5113 | else | |
5114 | scan_ch->type = 1; /* active */ | |
5115 | ||
5116 | if (scan_ch->type & 1) | |
5117 | scan_ch->type |= (direct_mask << 1); | |
5118 | ||
5119 | if (is_channel_narrow(ch_info)) | |
5120 | scan_ch->type |= (1 << 7); | |
5121 | ||
5122 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
5123 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
5124 | ||
9fbab516 | 5125 | /* Set txpower levels to defaults */ |
b481de9c ZY |
5126 | scan_ch->tpc.dsp_atten = 110; |
5127 | /* scan_pwr_info->tpc.dsp_atten; */ | |
5128 | ||
5129 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 5130 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
5131 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
5132 | else { | |
5133 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
5134 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 5135 | * power level: |
8a1b0245 | 5136 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
5137 | */ |
5138 | } | |
5139 | ||
5140 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
5141 | scan_ch->channel, | |
5142 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
5143 | (scan_ch->type & 1) ? | |
5144 | active_dwell : passive_dwell); | |
5145 | ||
5146 | scan_ch++; | |
5147 | added++; | |
5148 | } | |
5149 | ||
5150 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
5151 | return added; | |
5152 | } | |
5153 | ||
bb8c093b | 5154 | static void iwl3945_init_hw_rates(struct iwl3945_priv *priv, |
b481de9c ZY |
5155 | struct ieee80211_rate *rates) |
5156 | { | |
5157 | int i; | |
5158 | ||
5159 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
5160 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
5161 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
5162 | rates[i].hw_value_short = i; | |
5163 | rates[i].flags = 0; | |
5164 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
b481de9c | 5165 | /* |
8318d78a | 5166 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 5167 | */ |
bb8c093b | 5168 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 5169 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 5170 | } |
b481de9c ZY |
5171 | } |
5172 | } | |
5173 | ||
5174 | /** | |
bb8c093b | 5175 | * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 5176 | */ |
bb8c093b | 5177 | static int iwl3945_init_geos(struct iwl3945_priv *priv) |
b481de9c | 5178 | { |
bb8c093b | 5179 | struct iwl3945_channel_info *ch; |
8211ef78 | 5180 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
5181 | struct ieee80211_channel *channels; |
5182 | struct ieee80211_channel *geo_ch; | |
5183 | struct ieee80211_rate *rates; | |
5184 | int i = 0; | |
b481de9c | 5185 | |
8318d78a JB |
5186 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
5187 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
5188 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
5189 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
5190 | return 0; | |
5191 | } | |
5192 | ||
b481de9c ZY |
5193 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
5194 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 5195 | if (!channels) |
b481de9c | 5196 | return -ENOMEM; |
b481de9c | 5197 | |
8211ef78 | 5198 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
5199 | GFP_KERNEL); |
5200 | if (!rates) { | |
b481de9c ZY |
5201 | kfree(channels); |
5202 | return -ENOMEM; | |
5203 | } | |
5204 | ||
b481de9c | 5205 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 TW |
5206 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
5207 | sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)]; | |
5208 | /* just OFDM */ | |
5209 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5210 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
5211 | ||
5212 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
5213 | sband->channels = channels; | |
5214 | /* OFDM & CCK */ | |
5215 | sband->bitrates = rates; | |
5216 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c ZY |
5217 | |
5218 | priv->ieee_channels = channels; | |
5219 | priv->ieee_rates = rates; | |
5220 | ||
bb8c093b | 5221 | iwl3945_init_hw_rates(priv, rates); |
b481de9c | 5222 | |
8211ef78 | 5223 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
5224 | ch = &priv->channel_info[i]; |
5225 | ||
8211ef78 TW |
5226 | /* FIXME: might be removed if scan is OK*/ |
5227 | if (!is_channel_valid(ch)) | |
b481de9c | 5228 | continue; |
b481de9c ZY |
5229 | |
5230 | if (is_channel_a_band(ch)) | |
8211ef78 | 5231 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
8318d78a | 5232 | else |
8211ef78 | 5233 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
b481de9c | 5234 | |
8211ef78 TW |
5235 | geo_ch = &sband->channels[sband->n_channels++]; |
5236 | ||
5237 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
5238 | geo_ch->max_power = ch->max_power_avg; |
5239 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 5240 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
5241 | |
5242 | if (is_channel_valid(ch)) { | |
8318d78a JB |
5243 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
5244 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 5245 | |
8318d78a JB |
5246 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
5247 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
5248 | |
5249 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 5250 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
5251 | |
5252 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
5253 | priv->max_channel_txpower_limit = | |
5254 | ch->max_power_avg; | |
8211ef78 | 5255 | } else { |
8318d78a | 5256 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
5257 | } |
5258 | ||
5259 | /* Save flags for reg domain usage */ | |
5260 | geo_ch->orig_flags = geo_ch->flags; | |
5261 | ||
5262 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
5263 | ch->channel, geo_ch->center_freq, | |
5264 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
5265 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
5266 | "restricted" : "valid", | |
5267 | geo_ch->flags); | |
b481de9c ZY |
5268 | } |
5269 | ||
8318d78a | 5270 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) { |
b481de9c ZY |
5271 | printk(KERN_INFO DRV_NAME |
5272 | ": Incorrectly detected BG card as ABG. Please send " | |
5273 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
5274 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
5275 | priv->is_abg = 0; | |
5276 | } | |
5277 | ||
5278 | printk(KERN_INFO DRV_NAME | |
5279 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
5280 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
5281 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 5282 | |
8318d78a JB |
5283 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ]; |
5284 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 5285 | |
b481de9c ZY |
5286 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
5287 | ||
5288 | return 0; | |
5289 | } | |
5290 | ||
849e0dce RC |
5291 | /* |
5292 | * iwl3945_free_geos - undo allocations in iwl3945_init_geos | |
5293 | */ | |
5294 | static void iwl3945_free_geos(struct iwl3945_priv *priv) | |
5295 | { | |
849e0dce RC |
5296 | kfree(priv->ieee_channels); |
5297 | kfree(priv->ieee_rates); | |
5298 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
5299 | } | |
5300 | ||
b481de9c ZY |
5301 | /****************************************************************************** |
5302 | * | |
5303 | * uCode download functions | |
5304 | * | |
5305 | ******************************************************************************/ | |
5306 | ||
bb8c093b | 5307 | static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv) |
b481de9c | 5308 | { |
98c92211 TW |
5309 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
5310 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
5311 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
5312 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
5313 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
5314 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
5315 | } |
5316 | ||
5317 | /** | |
bb8c093b | 5318 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5319 | * looking at all data. |
5320 | */ | |
bb8c093b | 5321 | static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len) |
b481de9c ZY |
5322 | { |
5323 | u32 val; | |
5324 | u32 save_len = len; | |
5325 | int rc = 0; | |
5326 | u32 errcnt; | |
5327 | ||
5328 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5329 | ||
bb8c093b | 5330 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5331 | if (rc) |
5332 | return rc; | |
5333 | ||
bb8c093b | 5334 | iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
b481de9c ZY |
5335 | |
5336 | errcnt = 0; | |
5337 | for (; len > 0; len -= sizeof(u32), image++) { | |
5338 | /* read data comes through single port, auto-incr addr */ | |
5339 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5340 | * if IWL_DL_IO is set */ | |
bb8c093b | 5341 | val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5342 | if (val != le32_to_cpu(*image)) { |
5343 | IWL_ERROR("uCode INST section is invalid at " | |
5344 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5345 | save_len - len, val, le32_to_cpu(*image)); | |
5346 | rc = -EIO; | |
5347 | errcnt++; | |
5348 | if (errcnt >= 20) | |
5349 | break; | |
5350 | } | |
5351 | } | |
5352 | ||
bb8c093b | 5353 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5354 | |
5355 | if (!errcnt) | |
bc434dd2 | 5356 | IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); |
b481de9c ZY |
5357 | |
5358 | return rc; | |
5359 | } | |
5360 | ||
5361 | ||
5362 | /** | |
bb8c093b | 5363 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5364 | * using sample data 100 bytes apart. If these sample points are good, |
5365 | * it's a pretty good bet that everything between them is good, too. | |
5366 | */ | |
bb8c093b | 5367 | static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
5368 | { |
5369 | u32 val; | |
5370 | int rc = 0; | |
5371 | u32 errcnt = 0; | |
5372 | u32 i; | |
5373 | ||
5374 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5375 | ||
bb8c093b | 5376 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5377 | if (rc) |
5378 | return rc; | |
5379 | ||
5380 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
5381 | /* read data comes through single port, auto-incr addr */ | |
5382 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5383 | * if IWL_DL_IO is set */ | |
bb8c093b | 5384 | iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
b481de9c | 5385 | i + RTC_INST_LOWER_BOUND); |
bb8c093b | 5386 | val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5387 | if (val != le32_to_cpu(*image)) { |
5388 | #if 0 /* Enable this if you want to see details */ | |
5389 | IWL_ERROR("uCode INST section is invalid at " | |
5390 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5391 | i, val, *image); | |
5392 | #endif | |
5393 | rc = -EIO; | |
5394 | errcnt++; | |
5395 | if (errcnt >= 3) | |
5396 | break; | |
5397 | } | |
5398 | } | |
5399 | ||
bb8c093b | 5400 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5401 | |
5402 | return rc; | |
5403 | } | |
5404 | ||
5405 | ||
5406 | /** | |
bb8c093b | 5407 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5408 | * and verify its contents |
5409 | */ | |
bb8c093b | 5410 | static int iwl3945_verify_ucode(struct iwl3945_priv *priv) |
b481de9c ZY |
5411 | { |
5412 | __le32 *image; | |
5413 | u32 len; | |
5414 | int rc = 0; | |
5415 | ||
5416 | /* Try bootstrap */ | |
5417 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5418 | len = priv->ucode_boot.len; | |
bb8c093b | 5419 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5420 | if (rc == 0) { |
5421 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5422 | return 0; | |
5423 | } | |
5424 | ||
5425 | /* Try initialize */ | |
5426 | image = (__le32 *)priv->ucode_init.v_addr; | |
5427 | len = priv->ucode_init.len; | |
bb8c093b | 5428 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5429 | if (rc == 0) { |
5430 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5431 | return 0; | |
5432 | } | |
5433 | ||
5434 | /* Try runtime/protocol */ | |
5435 | image = (__le32 *)priv->ucode_code.v_addr; | |
5436 | len = priv->ucode_code.len; | |
bb8c093b | 5437 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5438 | if (rc == 0) { |
5439 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5440 | return 0; | |
5441 | } | |
5442 | ||
5443 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5444 | ||
9fbab516 BC |
5445 | /* Since nothing seems to match, show first several data entries in |
5446 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5447 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5448 | image = (__le32 *)priv->ucode_boot.v_addr; |
5449 | len = priv->ucode_boot.len; | |
bb8c093b | 5450 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
5451 | |
5452 | return rc; | |
5453 | } | |
5454 | ||
5455 | ||
5456 | /* check contents of special bootstrap uCode SRAM */ | |
bb8c093b | 5457 | static int iwl3945_verify_bsm(struct iwl3945_priv *priv) |
b481de9c ZY |
5458 | { |
5459 | __le32 *image = priv->ucode_boot.v_addr; | |
5460 | u32 len = priv->ucode_boot.len; | |
5461 | u32 reg; | |
5462 | u32 val; | |
5463 | ||
5464 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
5465 | ||
5466 | /* verify BSM SRAM contents */ | |
bb8c093b | 5467 | val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG); |
b481de9c ZY |
5468 | for (reg = BSM_SRAM_LOWER_BOUND; |
5469 | reg < BSM_SRAM_LOWER_BOUND + len; | |
5470 | reg += sizeof(u32), image ++) { | |
bb8c093b | 5471 | val = iwl3945_read_prph(priv, reg); |
b481de9c ZY |
5472 | if (val != le32_to_cpu(*image)) { |
5473 | IWL_ERROR("BSM uCode verification failed at " | |
5474 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
5475 | BSM_SRAM_LOWER_BOUND, | |
5476 | reg - BSM_SRAM_LOWER_BOUND, len, | |
5477 | val, le32_to_cpu(*image)); | |
5478 | return -EIO; | |
5479 | } | |
5480 | } | |
5481 | ||
5482 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
5483 | ||
5484 | return 0; | |
5485 | } | |
5486 | ||
5487 | /** | |
bb8c093b | 5488 | * iwl3945_load_bsm - Load bootstrap instructions |
b481de9c ZY |
5489 | * |
5490 | * BSM operation: | |
5491 | * | |
5492 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
5493 | * in special SRAM that does not power down during RFKILL. When powering back | |
5494 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
5495 | * the bootstrap program into the on-board processor, and starts it. | |
5496 | * | |
5497 | * The bootstrap program loads (via DMA) instructions and data for a new | |
5498 | * program from host DRAM locations indicated by the host driver in the | |
5499 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
5500 | * automatically. | |
5501 | * | |
5502 | * When initializing the NIC, the host driver points the BSM to the | |
5503 | * "initialize" uCode image. This uCode sets up some internal data, then | |
5504 | * notifies host via "initialize alive" that it is complete. | |
5505 | * | |
5506 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
5507 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
5508 | * (filled initially with starting data values for the on-board processor), | |
5509 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
5510 | * which begins normal operation. | |
5511 | * | |
5512 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
5513 | * the backup data cache in DRAM before SRAM is powered down. | |
5514 | * | |
5515 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
5516 | * the runtime uCode instructions and the backup data cache into SRAM, | |
5517 | * and re-launches the runtime uCode from where it left off. | |
5518 | */ | |
bb8c093b | 5519 | static int iwl3945_load_bsm(struct iwl3945_priv *priv) |
b481de9c ZY |
5520 | { |
5521 | __le32 *image = priv->ucode_boot.v_addr; | |
5522 | u32 len = priv->ucode_boot.len; | |
5523 | dma_addr_t pinst; | |
5524 | dma_addr_t pdata; | |
5525 | u32 inst_len; | |
5526 | u32 data_len; | |
5527 | int rc; | |
5528 | int i; | |
5529 | u32 done; | |
5530 | u32 reg_offset; | |
5531 | ||
5532 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
5533 | ||
5534 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
5535 | if (len > IWL_MAX_BSM_SIZE) | |
5536 | return -EINVAL; | |
5537 | ||
5538 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
9fbab516 | 5539 | * in host DRAM ... host DRAM physical address bits 31:0 for 3945. |
bb8c093b | 5540 | * NOTE: iwl3945_initialize_alive_start() will replace these values, |
b481de9c ZY |
5541 | * after the "initialize" uCode has run, to point to |
5542 | * runtime/protocol instructions and backup data cache. */ | |
5543 | pinst = priv->ucode_init.p_addr; | |
5544 | pdata = priv->ucode_init_data.p_addr; | |
5545 | inst_len = priv->ucode_init.len; | |
5546 | data_len = priv->ucode_init_data.len; | |
5547 | ||
bb8c093b | 5548 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5549 | if (rc) |
5550 | return rc; | |
5551 | ||
bb8c093b CH |
5552 | iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5553 | iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5554 | iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
5555 | iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
b481de9c ZY |
5556 | |
5557 | /* Fill BSM memory with bootstrap instructions */ | |
5558 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
5559 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
5560 | reg_offset += sizeof(u32), image++) | |
bb8c093b | 5561 | _iwl3945_write_prph(priv, reg_offset, |
b481de9c ZY |
5562 | le32_to_cpu(*image)); |
5563 | ||
bb8c093b | 5564 | rc = iwl3945_verify_bsm(priv); |
b481de9c | 5565 | if (rc) { |
bb8c093b | 5566 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5567 | return rc; |
5568 | } | |
5569 | ||
5570 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
bb8c093b CH |
5571 | iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); |
5572 | iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG, | |
b481de9c | 5573 | RTC_INST_LOWER_BOUND); |
bb8c093b | 5574 | iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
b481de9c ZY |
5575 | |
5576 | /* Load bootstrap code into instruction SRAM now, | |
5577 | * to prepare to load "initialize" uCode */ | |
bb8c093b | 5578 | iwl3945_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5579 | BSM_WR_CTRL_REG_BIT_START); |
5580 | ||
5581 | /* Wait for load of bootstrap uCode to finish */ | |
5582 | for (i = 0; i < 100; i++) { | |
bb8c093b | 5583 | done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG); |
b481de9c ZY |
5584 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
5585 | break; | |
5586 | udelay(10); | |
5587 | } | |
5588 | if (i < 100) | |
5589 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
5590 | else { | |
5591 | IWL_ERROR("BSM write did not complete!\n"); | |
5592 | return -EIO; | |
5593 | } | |
5594 | ||
5595 | /* Enable future boot loads whenever power management unit triggers it | |
5596 | * (e.g. when powering back up after power-save shutdown) */ | |
bb8c093b | 5597 | iwl3945_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5598 | BSM_WR_CTRL_REG_BIT_START_EN); |
5599 | ||
bb8c093b | 5600 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5601 | |
5602 | return 0; | |
5603 | } | |
5604 | ||
bb8c093b | 5605 | static void iwl3945_nic_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5606 | { |
5607 | /* Remove all resets to allow NIC to operate */ | |
bb8c093b | 5608 | iwl3945_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5609 | } |
5610 | ||
5611 | /** | |
bb8c093b | 5612 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5613 | * |
5614 | * Copy into buffers for card to fetch via bus-mastering | |
5615 | */ | |
bb8c093b | 5616 | static int iwl3945_read_ucode(struct iwl3945_priv *priv) |
b481de9c | 5617 | { |
bb8c093b | 5618 | struct iwl3945_ucode *ucode; |
90e759d1 | 5619 | int ret = 0; |
b481de9c ZY |
5620 | const struct firmware *ucode_raw; |
5621 | /* firmware file name contains uCode/driver compatibility version */ | |
5622 | const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode"; | |
5623 | u8 *src; | |
5624 | size_t len; | |
5625 | u32 ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
5626 | ||
5627 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5628 | * request_firmware() is synchronous, file is in memory on return. */ | |
90e759d1 TW |
5629 | ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev); |
5630 | if (ret < 0) { | |
5631 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5632 | name, ret); | |
b481de9c ZY |
5633 | goto error; |
5634 | } | |
5635 | ||
5636 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5637 | name, ucode_raw->size); | |
5638 | ||
5639 | /* Make sure that we got at least our header! */ | |
5640 | if (ucode_raw->size < sizeof(*ucode)) { | |
5641 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5642 | ret = -EINVAL; |
b481de9c ZY |
5643 | goto err_release; |
5644 | } | |
5645 | ||
5646 | /* Data from ucode file: header followed by uCode images */ | |
5647 | ucode = (void *)ucode_raw->data; | |
5648 | ||
5649 | ver = le32_to_cpu(ucode->ver); | |
5650 | inst_size = le32_to_cpu(ucode->inst_size); | |
5651 | data_size = le32_to_cpu(ucode->data_size); | |
5652 | init_size = le32_to_cpu(ucode->init_size); | |
5653 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5654 | boot_size = le32_to_cpu(ucode->boot_size); | |
5655 | ||
5656 | IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver); | |
bc434dd2 IS |
5657 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size); |
5658 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size); | |
5659 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size); | |
5660 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size); | |
5661 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size); | |
b481de9c ZY |
5662 | |
5663 | /* Verify size of file vs. image size info in file's header */ | |
5664 | if (ucode_raw->size < sizeof(*ucode) + | |
5665 | inst_size + data_size + init_size + | |
5666 | init_data_size + boot_size) { | |
5667 | ||
5668 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5669 | (int)ucode_raw->size); | |
90e759d1 | 5670 | ret = -EINVAL; |
b481de9c ZY |
5671 | goto err_release; |
5672 | } | |
5673 | ||
5674 | /* Verify that uCode images will fit in card's SRAM */ | |
5675 | if (inst_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5676 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5677 | inst_size); | |
5678 | ret = -EINVAL; | |
b481de9c ZY |
5679 | goto err_release; |
5680 | } | |
5681 | ||
5682 | if (data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5683 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5684 | data_size); | |
5685 | ret = -EINVAL; | |
b481de9c ZY |
5686 | goto err_release; |
5687 | } | |
5688 | if (init_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5689 | IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n", |
5690 | init_size); | |
5691 | ret = -EINVAL; | |
b481de9c ZY |
5692 | goto err_release; |
5693 | } | |
5694 | if (init_data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5695 | IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n", |
5696 | init_data_size); | |
5697 | ret = -EINVAL; | |
b481de9c ZY |
5698 | goto err_release; |
5699 | } | |
5700 | if (boot_size > IWL_MAX_BSM_SIZE) { | |
90e759d1 TW |
5701 | IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n", |
5702 | boot_size); | |
5703 | ret = -EINVAL; | |
b481de9c ZY |
5704 | goto err_release; |
5705 | } | |
5706 | ||
5707 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5708 | ||
5709 | /* Runtime instructions and 2 copies of data: | |
5710 | * 1) unmodified from disk | |
5711 | * 2) backup cache for save/restore during power-downs */ | |
5712 | priv->ucode_code.len = inst_size; | |
98c92211 | 5713 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5714 | |
5715 | priv->ucode_data.len = data_size; | |
98c92211 | 5716 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5717 | |
5718 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5719 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 5720 | |
90e759d1 TW |
5721 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
5722 | !priv->ucode_data_backup.v_addr) | |
5723 | goto err_pci_alloc; | |
b481de9c ZY |
5724 | |
5725 | /* Initialization instructions and data */ | |
90e759d1 TW |
5726 | if (init_size && init_data_size) { |
5727 | priv->ucode_init.len = init_size; | |
98c92211 | 5728 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5729 | |
5730 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5731 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5732 | |
5733 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5734 | goto err_pci_alloc; | |
5735 | } | |
b481de9c ZY |
5736 | |
5737 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5738 | if (boot_size) { |
5739 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5740 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5741 | |
90e759d1 TW |
5742 | if (!priv->ucode_boot.v_addr) |
5743 | goto err_pci_alloc; | |
5744 | } | |
b481de9c ZY |
5745 | |
5746 | /* Copy images into buffers for card's bus-master reads ... */ | |
5747 | ||
5748 | /* Runtime instructions (first block of data in file) */ | |
5749 | src = &ucode->data[0]; | |
5750 | len = priv->ucode_code.len; | |
90e759d1 | 5751 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5752 | memcpy(priv->ucode_code.v_addr, src, len); |
5753 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5754 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5755 | ||
5756 | /* Runtime data (2nd block) | |
bb8c093b | 5757 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
5758 | src = &ucode->data[inst_size]; |
5759 | len = priv->ucode_data.len; | |
90e759d1 | 5760 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5761 | memcpy(priv->ucode_data.v_addr, src, len); |
5762 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5763 | ||
5764 | /* Initialization instructions (3rd block) */ | |
5765 | if (init_size) { | |
5766 | src = &ucode->data[inst_size + data_size]; | |
5767 | len = priv->ucode_init.len; | |
90e759d1 TW |
5768 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5769 | len); | |
b481de9c ZY |
5770 | memcpy(priv->ucode_init.v_addr, src, len); |
5771 | } | |
5772 | ||
5773 | /* Initialization data (4th block) */ | |
5774 | if (init_data_size) { | |
5775 | src = &ucode->data[inst_size + data_size + init_size]; | |
5776 | len = priv->ucode_init_data.len; | |
5777 | IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n", | |
5778 | (int)len); | |
5779 | memcpy(priv->ucode_init_data.v_addr, src, len); | |
5780 | } | |
5781 | ||
5782 | /* Bootstrap instructions (5th block) */ | |
5783 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5784 | len = priv->ucode_boot.len; | |
5785 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n", | |
5786 | (int)len); | |
5787 | memcpy(priv->ucode_boot.v_addr, src, len); | |
5788 | ||
5789 | /* We have our copies now, allow OS release its copies */ | |
5790 | release_firmware(ucode_raw); | |
5791 | return 0; | |
5792 | ||
5793 | err_pci_alloc: | |
5794 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5795 | ret = -ENOMEM; |
bb8c093b | 5796 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
5797 | |
5798 | err_release: | |
5799 | release_firmware(ucode_raw); | |
5800 | ||
5801 | error: | |
90e759d1 | 5802 | return ret; |
b481de9c ZY |
5803 | } |
5804 | ||
5805 | ||
5806 | /** | |
bb8c093b | 5807 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5808 | * |
5809 | * Tell initialization uCode where to find runtime uCode. | |
5810 | * | |
5811 | * BSM registers initially contain pointers to initialization uCode. | |
5812 | * We need to replace them to load runtime uCode inst and data, | |
5813 | * and to save runtime data when powering down. | |
5814 | */ | |
bb8c093b | 5815 | static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv) |
b481de9c ZY |
5816 | { |
5817 | dma_addr_t pinst; | |
5818 | dma_addr_t pdata; | |
5819 | int rc = 0; | |
5820 | unsigned long flags; | |
5821 | ||
5822 | /* bits 31:0 for 3945 */ | |
5823 | pinst = priv->ucode_code.p_addr; | |
5824 | pdata = priv->ucode_data_backup.p_addr; | |
5825 | ||
5826 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 5827 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5828 | if (rc) { |
5829 | spin_unlock_irqrestore(&priv->lock, flags); | |
5830 | return rc; | |
5831 | } | |
5832 | ||
5833 | /* Tell bootstrap uCode where to find image to load */ | |
bb8c093b CH |
5834 | iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5835 | iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5836 | iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5837 | priv->ucode_data.len); |
5838 | ||
5839 | /* Inst bytecount must be last to set up, bit 31 signals uCode | |
5840 | * that all new ptr/size info is in place */ | |
bb8c093b | 5841 | iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5842 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5843 | ||
bb8c093b | 5844 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5845 | |
5846 | spin_unlock_irqrestore(&priv->lock, flags); | |
5847 | ||
5848 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5849 | ||
5850 | return rc; | |
5851 | } | |
5852 | ||
5853 | /** | |
bb8c093b | 5854 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5855 | * |
5856 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5857 | * | |
b481de9c | 5858 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 5859 | */ |
bb8c093b | 5860 | static void iwl3945_init_alive_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5861 | { |
5862 | /* Check alive response for "valid" sign from uCode */ | |
5863 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5864 | /* We had an error bringing up the hardware, so take it | |
5865 | * all the way back down so we can try again */ | |
5866 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5867 | goto restart; | |
5868 | } | |
5869 | ||
5870 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5871 | * This is a paranoid check, because we would not have gotten the | |
5872 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5873 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5874 | /* Runtime instruction load was bad; |
5875 | * take it all the way back down so we can try again */ | |
5876 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5877 | goto restart; | |
5878 | } | |
5879 | ||
5880 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5881 | * load and launch runtime uCode, which will send us another "Alive" | |
5882 | * notification. */ | |
5883 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5884 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5885 | /* Runtime instruction load won't happen; |
5886 | * take it all the way back down so we can try again */ | |
5887 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5888 | goto restart; | |
5889 | } | |
5890 | return; | |
5891 | ||
5892 | restart: | |
5893 | queue_work(priv->workqueue, &priv->restart); | |
5894 | } | |
5895 | ||
5896 | ||
5897 | /** | |
bb8c093b | 5898 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5899 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5900 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 5901 | */ |
bb8c093b | 5902 | static void iwl3945_alive_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5903 | { |
5904 | int rc = 0; | |
5905 | int thermal_spin = 0; | |
5906 | u32 rfkill; | |
5907 | ||
5908 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5909 | ||
5910 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5911 | /* We had an error bringing up the hardware, so take it | |
5912 | * all the way back down so we can try again */ | |
5913 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5914 | goto restart; | |
5915 | } | |
5916 | ||
5917 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5918 | * This is a paranoid check, because we would not have gotten the | |
5919 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5920 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5921 | /* Runtime instruction load was bad; |
5922 | * take it all the way back down so we can try again */ | |
5923 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5924 | goto restart; | |
5925 | } | |
5926 | ||
bb8c093b | 5927 | iwl3945_clear_stations_table(priv); |
b481de9c | 5928 | |
bb8c093b | 5929 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5930 | if (rc) { |
5931 | IWL_WARNING("Can not read rfkill status from adapter\n"); | |
5932 | return; | |
5933 | } | |
5934 | ||
bb8c093b | 5935 | rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG); |
b481de9c | 5936 | IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); |
bb8c093b | 5937 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5938 | |
5939 | if (rfkill & 0x1) { | |
5940 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5941 | /* if rfkill is not on, then wait for thermal | |
5942 | * sensor in adapter to kick in */ | |
bb8c093b | 5943 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
5944 | thermal_spin++; |
5945 | udelay(10); | |
5946 | } | |
5947 | ||
5948 | if (thermal_spin) | |
5949 | IWL_DEBUG_INFO("Thermal calibration took %dus\n", | |
5950 | thermal_spin * 10); | |
5951 | } else | |
5952 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5953 | ||
9fbab516 | 5954 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
5955 | set_bit(STATUS_ALIVE, &priv->status); |
5956 | ||
5957 | /* Clear out the uCode error bit if it is set */ | |
5958 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5959 | ||
bb8c093b | 5960 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
5961 | return; |
5962 | ||
5a66926a | 5963 | ieee80211_start_queues(priv->hw); |
b481de9c ZY |
5964 | |
5965 | priv->active_rate = priv->rates_mask; | |
5966 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5967 | ||
bb8c093b | 5968 | iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5969 | |
bb8c093b CH |
5970 | if (iwl3945_is_associated(priv)) { |
5971 | struct iwl3945_rxon_cmd *active_rxon = | |
5972 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); | |
b481de9c ZY |
5973 | |
5974 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
5975 | sizeof(priv->staging_rxon)); | |
5976 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5977 | } else { | |
5978 | /* Initialize our rx_config data */ | |
bb8c093b | 5979 | iwl3945_connection_init_rx_config(priv); |
b481de9c ZY |
5980 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
5981 | } | |
5982 | ||
9fbab516 | 5983 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5984 | iwl3945_send_bt_config(priv); |
b481de9c ZY |
5985 | |
5986 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5987 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
5988 | |
5989 | /* At this point, the NIC is initialized and operational */ | |
5990 | priv->notif_missed_beacons = 0; | |
5991 | set_bit(STATUS_READY, &priv->status); | |
5992 | ||
5993 | iwl3945_reg_txpower_periodic(priv); | |
5994 | ||
5995 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); | |
5a66926a | 5996 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5997 | |
5998 | if (priv->error_recovering) | |
bb8c093b | 5999 | iwl3945_error_recovery(priv); |
b481de9c ZY |
6000 | |
6001 | return; | |
6002 | ||
6003 | restart: | |
6004 | queue_work(priv->workqueue, &priv->restart); | |
6005 | } | |
6006 | ||
bb8c093b | 6007 | static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv); |
b481de9c | 6008 | |
bb8c093b | 6009 | static void __iwl3945_down(struct iwl3945_priv *priv) |
b481de9c ZY |
6010 | { |
6011 | unsigned long flags; | |
6012 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
6013 | struct ieee80211_conf *conf = NULL; | |
6014 | ||
6015 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
6016 | ||
6017 | conf = ieee80211_get_hw_conf(priv->hw); | |
6018 | ||
6019 | if (!exit_pending) | |
6020 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
6021 | ||
bb8c093b | 6022 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
6023 | |
6024 | /* Unblock any waiting calls */ | |
6025 | wake_up_interruptible_all(&priv->wait_command_queue); | |
6026 | ||
b481de9c ZY |
6027 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
6028 | * exiting the module */ | |
6029 | if (!exit_pending) | |
6030 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
6031 | ||
6032 | /* stop and reset the on-board processor */ | |
bb8c093b | 6033 | iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
6034 | |
6035 | /* tell the device to stop sending interrupts */ | |
bb8c093b | 6036 | iwl3945_disable_interrupts(priv); |
b481de9c ZY |
6037 | |
6038 | if (priv->mac80211_registered) | |
6039 | ieee80211_stop_queues(priv->hw); | |
6040 | ||
bb8c093b | 6041 | /* If we have not previously called iwl3945_init() then |
b481de9c | 6042 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
bb8c093b | 6043 | if (!iwl3945_is_init(priv)) { |
b481de9c ZY |
6044 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
6045 | STATUS_RF_KILL_HW | | |
6046 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
6047 | STATUS_RF_KILL_SW | | |
9788864e RC |
6048 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
6049 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
6050 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
6051 | STATUS_IN_SUSPEND; | |
6052 | goto exit; | |
6053 | } | |
6054 | ||
6055 | /* ...otherwise clear out all the status bits but the RF Kill and | |
6056 | * SUSPEND bits and continue taking the NIC down. */ | |
6057 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
6058 | STATUS_RF_KILL_HW | | |
6059 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
6060 | STATUS_RF_KILL_SW | | |
9788864e RC |
6061 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
6062 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
6063 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
6064 | STATUS_IN_SUSPEND | | |
6065 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
6066 | STATUS_FW_ERROR; | |
6067 | ||
6068 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 6069 | iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
6070 | spin_unlock_irqrestore(&priv->lock, flags); |
6071 | ||
bb8c093b CH |
6072 | iwl3945_hw_txq_ctx_stop(priv); |
6073 | iwl3945_hw_rxq_stop(priv); | |
b481de9c ZY |
6074 | |
6075 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b CH |
6076 | if (!iwl3945_grab_nic_access(priv)) { |
6077 | iwl3945_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 6078 | APMG_CLK_VAL_DMA_CLK_RQT); |
bb8c093b | 6079 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
6080 | } |
6081 | spin_unlock_irqrestore(&priv->lock, flags); | |
6082 | ||
6083 | udelay(5); | |
6084 | ||
bb8c093b CH |
6085 | iwl3945_hw_nic_stop_master(priv); |
6086 | iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
6087 | iwl3945_hw_nic_reset(priv); | |
b481de9c ZY |
6088 | |
6089 | exit: | |
bb8c093b | 6090 | memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp)); |
b481de9c ZY |
6091 | |
6092 | if (priv->ibss_beacon) | |
6093 | dev_kfree_skb(priv->ibss_beacon); | |
6094 | priv->ibss_beacon = NULL; | |
6095 | ||
6096 | /* clear out any free frames */ | |
bb8c093b | 6097 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
6098 | } |
6099 | ||
bb8c093b | 6100 | static void iwl3945_down(struct iwl3945_priv *priv) |
b481de9c ZY |
6101 | { |
6102 | mutex_lock(&priv->mutex); | |
bb8c093b | 6103 | __iwl3945_down(priv); |
b481de9c | 6104 | mutex_unlock(&priv->mutex); |
b24d22b1 | 6105 | |
bb8c093b | 6106 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
6107 | } |
6108 | ||
6109 | #define MAX_HW_RESTARTS 5 | |
6110 | ||
bb8c093b | 6111 | static int __iwl3945_up(struct iwl3945_priv *priv) |
b481de9c ZY |
6112 | { |
6113 | int rc, i; | |
6114 | ||
6115 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6116 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
6117 | return -EIO; | |
6118 | } | |
6119 | ||
6120 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
6121 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
6122 | "parameter)\n"); | |
e655b9f0 ZY |
6123 | return -ENODEV; |
6124 | } | |
6125 | ||
e903fbd4 RC |
6126 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
6127 | IWL_ERROR("ucode not available for device bringup\n"); | |
6128 | return -EIO; | |
6129 | } | |
6130 | ||
e655b9f0 ZY |
6131 | /* If platform's RF_KILL switch is NOT set to KILL */ |
6132 | if (iwl3945_read32(priv, CSR_GP_CNTRL) & | |
6133 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
6134 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
6135 | else { | |
6136 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6137 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
6138 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); | |
6139 | return -ENODEV; | |
6140 | } | |
b481de9c ZY |
6141 | } |
6142 | ||
bb8c093b | 6143 | iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 6144 | |
bb8c093b | 6145 | rc = iwl3945_hw_nic_init(priv); |
b481de9c ZY |
6146 | if (rc) { |
6147 | IWL_ERROR("Unable to int nic\n"); | |
6148 | return rc; | |
6149 | } | |
6150 | ||
6151 | /* make sure rfkill handshake bits are cleared */ | |
bb8c093b CH |
6152 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
6153 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
6154 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
6155 | ||
6156 | /* clear (again), then enable host interrupts */ | |
bb8c093b CH |
6157 | iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); |
6158 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
6159 | |
6160 | /* really make sure rfkill handshake bits are cleared */ | |
bb8c093b CH |
6161 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
6162 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
6163 | |
6164 | /* Copy original ucode data image from disk into backup cache. | |
6165 | * This will be used to initialize the on-board processor's | |
6166 | * data SRAM for a clean start when the runtime program first loads. */ | |
6167 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 6168 | priv->ucode_data.len); |
b481de9c | 6169 | |
e655b9f0 ZY |
6170 | /* We return success when we resume from suspend and rf_kill is on. */ |
6171 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
6172 | return 0; | |
6173 | ||
b481de9c ZY |
6174 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
6175 | ||
bb8c093b | 6176 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
6177 | |
6178 | /* load bootstrap state machine, | |
6179 | * load bootstrap program into processor's memory, | |
6180 | * prepare to load the "initialize" uCode */ | |
bb8c093b | 6181 | rc = iwl3945_load_bsm(priv); |
b481de9c ZY |
6182 | |
6183 | if (rc) { | |
6184 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc); | |
6185 | continue; | |
6186 | } | |
6187 | ||
6188 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 6189 | iwl3945_nic_start(priv); |
b481de9c | 6190 | |
b481de9c ZY |
6191 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
6192 | ||
6193 | return 0; | |
6194 | } | |
6195 | ||
6196 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 6197 | __iwl3945_down(priv); |
b481de9c ZY |
6198 | |
6199 | /* tried to restart and config the device for as long as our | |
6200 | * patience could withstand */ | |
6201 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
6202 | return -EIO; | |
6203 | } | |
6204 | ||
6205 | ||
6206 | /***************************************************************************** | |
6207 | * | |
6208 | * Workqueue callbacks | |
6209 | * | |
6210 | *****************************************************************************/ | |
6211 | ||
bb8c093b | 6212 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 6213 | { |
bb8c093b CH |
6214 | struct iwl3945_priv *priv = |
6215 | container_of(data, struct iwl3945_priv, init_alive_start.work); | |
b481de9c ZY |
6216 | |
6217 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6218 | return; | |
6219 | ||
6220 | mutex_lock(&priv->mutex); | |
bb8c093b | 6221 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
6222 | mutex_unlock(&priv->mutex); |
6223 | } | |
6224 | ||
bb8c093b | 6225 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 6226 | { |
bb8c093b CH |
6227 | struct iwl3945_priv *priv = |
6228 | container_of(data, struct iwl3945_priv, alive_start.work); | |
b481de9c ZY |
6229 | |
6230 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6231 | return; | |
6232 | ||
6233 | mutex_lock(&priv->mutex); | |
bb8c093b | 6234 | iwl3945_alive_start(priv); |
b481de9c ZY |
6235 | mutex_unlock(&priv->mutex); |
6236 | } | |
6237 | ||
bb8c093b | 6238 | static void iwl3945_bg_rf_kill(struct work_struct *work) |
b481de9c | 6239 | { |
bb8c093b | 6240 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill); |
b481de9c ZY |
6241 | |
6242 | wake_up_interruptible(&priv->wait_command_queue); | |
6243 | ||
6244 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6245 | return; | |
6246 | ||
6247 | mutex_lock(&priv->mutex); | |
6248 | ||
bb8c093b | 6249 | if (!iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6250 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
6251 | "HW and/or SW RF Kill no longer active, restarting " | |
6252 | "device\n"); | |
6253 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6254 | queue_work(priv->workqueue, &priv->restart); | |
6255 | } else { | |
6256 | ||
6257 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
6258 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
6259 | "disabled by SW switch\n"); | |
6260 | else | |
6261 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
6262 | "Kill switch must be turned off for " | |
6263 | "wireless networking to work.\n"); | |
6264 | } | |
6265 | mutex_unlock(&priv->mutex); | |
6266 | } | |
6267 | ||
6268 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) | |
6269 | ||
bb8c093b | 6270 | static void iwl3945_bg_scan_check(struct work_struct *data) |
b481de9c | 6271 | { |
bb8c093b CH |
6272 | struct iwl3945_priv *priv = |
6273 | container_of(data, struct iwl3945_priv, scan_check.work); | |
b481de9c ZY |
6274 | |
6275 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6276 | return; | |
6277 | ||
6278 | mutex_lock(&priv->mutex); | |
6279 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
6280 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6281 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
6282 | "Scan completion watchdog resetting adapter (%dms)\n", | |
6283 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
15e869d8 | 6284 | |
b481de9c | 6285 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 6286 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6287 | } |
6288 | mutex_unlock(&priv->mutex); | |
6289 | } | |
6290 | ||
bb8c093b | 6291 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 6292 | { |
bb8c093b CH |
6293 | struct iwl3945_priv *priv = |
6294 | container_of(data, struct iwl3945_priv, request_scan); | |
6295 | struct iwl3945_host_cmd cmd = { | |
b481de9c | 6296 | .id = REPLY_SCAN_CMD, |
bb8c093b | 6297 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
6298 | .meta.flags = CMD_SIZE_HUGE, |
6299 | }; | |
6300 | int rc = 0; | |
bb8c093b | 6301 | struct iwl3945_scan_cmd *scan; |
b481de9c ZY |
6302 | struct ieee80211_conf *conf = NULL; |
6303 | u8 direct_mask; | |
8318d78a | 6304 | enum ieee80211_band band; |
b481de9c ZY |
6305 | |
6306 | conf = ieee80211_get_hw_conf(priv->hw); | |
6307 | ||
6308 | mutex_lock(&priv->mutex); | |
6309 | ||
bb8c093b | 6310 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
6311 | IWL_WARNING("request scan called when driver not ready.\n"); |
6312 | goto done; | |
6313 | } | |
6314 | ||
6315 | /* Make sure the scan wasn't cancelled before this queued work | |
6316 | * was given the chance to run... */ | |
6317 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
6318 | goto done; | |
6319 | ||
6320 | /* This should never be called or scheduled if there is currently | |
6321 | * a scan active in the hardware. */ | |
6322 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
6323 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
6324 | "Ignoring second request.\n"); | |
6325 | rc = -EIO; | |
6326 | goto done; | |
6327 | } | |
6328 | ||
6329 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6330 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
6331 | goto done; | |
6332 | } | |
6333 | ||
6334 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6335 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
6336 | goto done; | |
6337 | } | |
6338 | ||
bb8c093b | 6339 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6340 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
6341 | goto done; | |
6342 | } | |
6343 | ||
6344 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6345 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
6346 | goto done; | |
6347 | } | |
6348 | ||
6349 | if (!priv->scan_bands) { | |
6350 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
6351 | goto done; | |
6352 | } | |
6353 | ||
6354 | if (!priv->scan) { | |
bb8c093b | 6355 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + |
b481de9c ZY |
6356 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
6357 | if (!priv->scan) { | |
6358 | rc = -ENOMEM; | |
6359 | goto done; | |
6360 | } | |
6361 | } | |
6362 | scan = priv->scan; | |
bb8c093b | 6363 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
6364 | |
6365 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
6366 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
6367 | ||
bb8c093b | 6368 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
6369 | u16 interval = 0; |
6370 | u32 extra; | |
6371 | u32 suspend_time = 100; | |
6372 | u32 scan_suspend_time = 100; | |
6373 | unsigned long flags; | |
6374 | ||
6375 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
6376 | ||
6377 | spin_lock_irqsave(&priv->lock, flags); | |
6378 | interval = priv->beacon_int; | |
6379 | spin_unlock_irqrestore(&priv->lock, flags); | |
6380 | ||
6381 | scan->suspend_time = 0; | |
15e869d8 | 6382 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
6383 | if (!interval) |
6384 | interval = suspend_time; | |
6385 | /* | |
6386 | * suspend time format: | |
6387 | * 0-19: beacon interval in usec (time before exec.) | |
6388 | * 20-23: 0 | |
6389 | * 24-31: number of beacons (suspend between channels) | |
6390 | */ | |
6391 | ||
6392 | extra = (suspend_time / interval) << 24; | |
6393 | scan_suspend_time = 0xFF0FFFFF & | |
6394 | (extra | ((suspend_time % interval) * 1024)); | |
6395 | ||
6396 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
6397 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
6398 | scan_suspend_time, interval); | |
6399 | } | |
6400 | ||
6401 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
6402 | if (priv->one_direct_scan) { | |
6403 | IWL_DEBUG_SCAN | |
6404 | ("Kicking off one direct scan for '%s'\n", | |
bb8c093b | 6405 | iwl3945_escape_essid(priv->direct_ssid, |
b481de9c ZY |
6406 | priv->direct_ssid_len)); |
6407 | scan->direct_scan[0].id = WLAN_EID_SSID; | |
6408 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
6409 | memcpy(scan->direct_scan[0].ssid, | |
6410 | priv->direct_ssid, priv->direct_ssid_len); | |
6411 | direct_mask = 1; | |
bb8c093b | 6412 | } else if (!iwl3945_is_associated(priv) && priv->essid_len) { |
b481de9c ZY |
6413 | scan->direct_scan[0].id = WLAN_EID_SSID; |
6414 | scan->direct_scan[0].len = priv->essid_len; | |
6415 | memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len); | |
6416 | direct_mask = 1; | |
6417 | } else | |
6418 | direct_mask = 0; | |
6419 | ||
6420 | /* We don't build a direct scan probe request; the uCode will do | |
6421 | * that based on the direct_mask added to each channel entry */ | |
6422 | scan->tx_cmd.len = cpu_to_le16( | |
bb8c093b | 6423 | iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data, |
18904f58 | 6424 | IWL_MAX_SCAN_SIZE - sizeof(*scan), 0)); |
b481de9c ZY |
6425 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
6426 | scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id; | |
6427 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
6428 | ||
6429 | /* flags + rate selection */ | |
6430 | ||
6431 | switch (priv->scan_bands) { | |
6432 | case 2: | |
6433 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
6434 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
6435 | scan->good_CRC_th = 0; | |
8318d78a | 6436 | band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
6437 | break; |
6438 | ||
6439 | case 1: | |
6440 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; | |
6441 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 6442 | band = IEEE80211_BAND_5GHZ; |
b481de9c ZY |
6443 | break; |
6444 | ||
6445 | default: | |
6446 | IWL_WARNING("Invalid scan band count\n"); | |
6447 | goto done; | |
6448 | } | |
6449 | ||
6450 | /* select Rx antennas */ | |
6451 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
6452 | ||
6453 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) | |
6454 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; | |
6455 | ||
6456 | if (direct_mask) | |
6457 | IWL_DEBUG_SCAN | |
6458 | ("Initiating direct scan for %s.\n", | |
bb8c093b | 6459 | iwl3945_escape_essid(priv->essid, priv->essid_len)); |
b481de9c ZY |
6460 | else |
6461 | IWL_DEBUG_SCAN("Initiating indirect scan.\n"); | |
6462 | ||
6463 | scan->channel_count = | |
bb8c093b | 6464 | iwl3945_get_channels_for_scan( |
8318d78a | 6465 | priv, band, 1, /* active */ |
b481de9c ZY |
6466 | direct_mask, |
6467 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
6468 | ||
6469 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + | |
bb8c093b | 6470 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
6471 | cmd.data = scan; |
6472 | scan->len = cpu_to_le16(cmd.len); | |
6473 | ||
6474 | set_bit(STATUS_SCAN_HW, &priv->status); | |
bb8c093b | 6475 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
6476 | if (rc) |
6477 | goto done; | |
6478 | ||
6479 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
6480 | IWL_SCAN_CHECK_WATCHDOG); | |
6481 | ||
6482 | mutex_unlock(&priv->mutex); | |
6483 | return; | |
6484 | ||
6485 | done: | |
01ebd063 | 6486 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
6487 | queue_work(priv->workqueue, &priv->scan_completed); |
6488 | mutex_unlock(&priv->mutex); | |
6489 | } | |
6490 | ||
bb8c093b | 6491 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 6492 | { |
bb8c093b | 6493 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up); |
b481de9c ZY |
6494 | |
6495 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6496 | return; | |
6497 | ||
6498 | mutex_lock(&priv->mutex); | |
bb8c093b | 6499 | __iwl3945_up(priv); |
b481de9c ZY |
6500 | mutex_unlock(&priv->mutex); |
6501 | } | |
6502 | ||
bb8c093b | 6503 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 6504 | { |
bb8c093b | 6505 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart); |
b481de9c ZY |
6506 | |
6507 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6508 | return; | |
6509 | ||
bb8c093b | 6510 | iwl3945_down(priv); |
b481de9c ZY |
6511 | queue_work(priv->workqueue, &priv->up); |
6512 | } | |
6513 | ||
bb8c093b | 6514 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 6515 | { |
bb8c093b CH |
6516 | struct iwl3945_priv *priv = |
6517 | container_of(data, struct iwl3945_priv, rx_replenish); | |
b481de9c ZY |
6518 | |
6519 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6520 | return; | |
6521 | ||
6522 | mutex_lock(&priv->mutex); | |
bb8c093b | 6523 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
6524 | mutex_unlock(&priv->mutex); |
6525 | } | |
6526 | ||
7878a5a4 MA |
6527 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
6528 | ||
bb8c093b | 6529 | static void iwl3945_bg_post_associate(struct work_struct *data) |
b481de9c | 6530 | { |
bb8c093b | 6531 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, |
b481de9c ZY |
6532 | post_associate.work); |
6533 | ||
6534 | int rc = 0; | |
6535 | struct ieee80211_conf *conf = NULL; | |
0795af57 | 6536 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6537 | |
6538 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6539 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | |
6540 | return; | |
6541 | } | |
6542 | ||
6543 | ||
0795af57 JP |
6544 | IWL_DEBUG_ASSOC("Associated as %d to: %s\n", |
6545 | priv->assoc_id, | |
6546 | print_mac(mac, priv->active_rxon.bssid_addr)); | |
b481de9c ZY |
6547 | |
6548 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6549 | return; | |
6550 | ||
6551 | mutex_lock(&priv->mutex); | |
6552 | ||
32bfd35d | 6553 | if (!priv->vif || !priv->is_open) { |
6ef89d0a MA |
6554 | mutex_unlock(&priv->mutex); |
6555 | return; | |
6556 | } | |
bb8c093b | 6557 | iwl3945_scan_cancel_timeout(priv, 200); |
15e869d8 | 6558 | |
b481de9c ZY |
6559 | conf = ieee80211_get_hw_conf(priv->hw); |
6560 | ||
6561 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6562 | iwl3945_commit_rxon(priv); |
b481de9c | 6563 | |
bb8c093b CH |
6564 | memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd)); |
6565 | iwl3945_setup_rxon_timing(priv); | |
6566 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6567 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6568 | if (rc) | |
6569 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6570 | "Attempting to continue.\n"); | |
6571 | ||
6572 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
6573 | ||
6574 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6575 | ||
6576 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6577 | priv->assoc_id, priv->beacon_int); | |
6578 | ||
6579 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6580 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6581 | else | |
6582 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6583 | ||
6584 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6585 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6586 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
6587 | else | |
6588 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6589 | ||
6590 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6591 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6592 | ||
6593 | } | |
6594 | ||
bb8c093b | 6595 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6596 | |
6597 | switch (priv->iw_mode) { | |
6598 | case IEEE80211_IF_TYPE_STA: | |
bb8c093b | 6599 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6600 | break; |
6601 | ||
6602 | case IEEE80211_IF_TYPE_IBSS: | |
6603 | ||
6604 | /* clear out the station table */ | |
bb8c093b | 6605 | iwl3945_clear_stations_table(priv); |
b481de9c | 6606 | |
bb8c093b CH |
6607 | iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0); |
6608 | iwl3945_add_station(priv, priv->bssid, 0, 0); | |
b481de9c | 6609 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 6610 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
6611 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
6612 | CMD_ASYNC); | |
bb8c093b CH |
6613 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
6614 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
6615 | |
6616 | break; | |
6617 | ||
6618 | default: | |
6619 | IWL_ERROR("%s Should not be called in %d mode\n", | |
bc434dd2 | 6620 | __FUNCTION__, priv->iw_mode); |
b481de9c ZY |
6621 | break; |
6622 | } | |
6623 | ||
bb8c093b | 6624 | iwl3945_sequence_reset(priv); |
b481de9c | 6625 | |
bb8c093b | 6626 | iwl3945_activate_qos(priv, 0); |
292ae174 | 6627 | |
7878a5a4 MA |
6628 | /* we have just associated, don't start scan too early */ |
6629 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
b481de9c ZY |
6630 | mutex_unlock(&priv->mutex); |
6631 | } | |
6632 | ||
bb8c093b | 6633 | static void iwl3945_bg_abort_scan(struct work_struct *work) |
b481de9c | 6634 | { |
bb8c093b | 6635 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan); |
b481de9c | 6636 | |
bb8c093b | 6637 | if (!iwl3945_is_ready(priv)) |
b481de9c ZY |
6638 | return; |
6639 | ||
6640 | mutex_lock(&priv->mutex); | |
6641 | ||
6642 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6643 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6644 | |
6645 | mutex_unlock(&priv->mutex); | |
6646 | } | |
6647 | ||
76bb77e0 ZY |
6648 | static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); |
6649 | ||
bb8c093b | 6650 | static void iwl3945_bg_scan_completed(struct work_struct *work) |
b481de9c | 6651 | { |
bb8c093b CH |
6652 | struct iwl3945_priv *priv = |
6653 | container_of(work, struct iwl3945_priv, scan_completed); | |
b481de9c ZY |
6654 | |
6655 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6656 | ||
6657 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6658 | return; | |
6659 | ||
a0646470 ZY |
6660 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
6661 | iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw)); | |
76bb77e0 | 6662 | |
b481de9c ZY |
6663 | ieee80211_scan_completed(priv->hw); |
6664 | ||
6665 | /* Since setting the TXPOWER may have been deferred while | |
6666 | * performing the scan, fire one off */ | |
6667 | mutex_lock(&priv->mutex); | |
bb8c093b | 6668 | iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
6669 | mutex_unlock(&priv->mutex); |
6670 | } | |
6671 | ||
6672 | /***************************************************************************** | |
6673 | * | |
6674 | * mac80211 entry point functions | |
6675 | * | |
6676 | *****************************************************************************/ | |
6677 | ||
5a66926a ZY |
6678 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6679 | ||
bb8c093b | 6680 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6681 | { |
bb8c093b | 6682 | struct iwl3945_priv *priv = hw->priv; |
5a66926a | 6683 | int ret; |
b481de9c ZY |
6684 | |
6685 | IWL_DEBUG_MAC80211("enter\n"); | |
6686 | ||
5a66926a ZY |
6687 | if (pci_enable_device(priv->pci_dev)) { |
6688 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6689 | return -ENODEV; | |
6690 | } | |
6691 | pci_restore_state(priv->pci_dev); | |
6692 | pci_enable_msi(priv->pci_dev); | |
6693 | ||
6694 | ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED, | |
6695 | DRV_NAME, priv); | |
6696 | if (ret) { | |
6697 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6698 | goto out_disable_msi; | |
6699 | } | |
6700 | ||
b481de9c ZY |
6701 | /* we should be verifying the device is ready to be opened */ |
6702 | mutex_lock(&priv->mutex); | |
6703 | ||
5a66926a ZY |
6704 | memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd)); |
6705 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
6706 | * ucode filename and max sizes are card-specific. */ | |
6707 | ||
6708 | if (!priv->ucode_code.len) { | |
6709 | ret = iwl3945_read_ucode(priv); | |
6710 | if (ret) { | |
6711 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6712 | mutex_unlock(&priv->mutex); | |
6713 | goto out_release_irq; | |
6714 | } | |
6715 | } | |
b481de9c | 6716 | |
e655b9f0 | 6717 | ret = __iwl3945_up(priv); |
b481de9c ZY |
6718 | |
6719 | mutex_unlock(&priv->mutex); | |
5a66926a | 6720 | |
e655b9f0 ZY |
6721 | if (ret) |
6722 | goto out_release_irq; | |
6723 | ||
6724 | IWL_DEBUG_INFO("Start UP work.\n"); | |
6725 | ||
6726 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6727 | return 0; | |
6728 | ||
5a66926a ZY |
6729 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6730 | * mac80211 will not be run successfully. */ | |
6731 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6732 | test_bit(STATUS_READY, &priv->status), | |
6733 | UCODE_READY_TIMEOUT); | |
6734 | if (!ret) { | |
6735 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6736 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6737 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6738 | ret = -ETIMEDOUT; | |
6739 | goto out_release_irq; | |
6740 | } | |
6741 | } | |
6742 | ||
e655b9f0 | 6743 | priv->is_open = 1; |
b481de9c ZY |
6744 | IWL_DEBUG_MAC80211("leave\n"); |
6745 | return 0; | |
5a66926a ZY |
6746 | |
6747 | out_release_irq: | |
6748 | free_irq(priv->pci_dev->irq, priv); | |
6749 | out_disable_msi: | |
6750 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6751 | pci_disable_device(priv->pci_dev); |
6752 | priv->is_open = 0; | |
6753 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6754 | return ret; |
b481de9c ZY |
6755 | } |
6756 | ||
bb8c093b | 6757 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6758 | { |
bb8c093b | 6759 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6760 | |
6761 | IWL_DEBUG_MAC80211("enter\n"); | |
6ef89d0a | 6762 | |
e655b9f0 ZY |
6763 | if (!priv->is_open) { |
6764 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6765 | return; | |
6766 | } | |
6767 | ||
b481de9c | 6768 | priv->is_open = 0; |
5a66926a ZY |
6769 | |
6770 | if (iwl3945_is_ready_rf(priv)) { | |
e655b9f0 ZY |
6771 | /* stop mac, cancel any scan request and clear |
6772 | * RXON_FILTER_ASSOC_MSK BIT | |
6773 | */ | |
5a66926a ZY |
6774 | mutex_lock(&priv->mutex); |
6775 | iwl3945_scan_cancel_timeout(priv, 100); | |
6776 | cancel_delayed_work(&priv->post_associate); | |
fde3571f | 6777 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6778 | } |
6779 | ||
5a66926a ZY |
6780 | iwl3945_down(priv); |
6781 | ||
6782 | flush_workqueue(priv->workqueue); | |
6783 | free_irq(priv->pci_dev->irq, priv); | |
6784 | pci_disable_msi(priv->pci_dev); | |
6785 | pci_save_state(priv->pci_dev); | |
6786 | pci_disable_device(priv->pci_dev); | |
6ef89d0a | 6787 | |
b481de9c | 6788 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6789 | } |
6790 | ||
bb8c093b | 6791 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
6792 | struct ieee80211_tx_control *ctl) |
6793 | { | |
bb8c093b | 6794 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6795 | |
6796 | IWL_DEBUG_MAC80211("enter\n"); | |
6797 | ||
6798 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | |
6799 | IWL_DEBUG_MAC80211("leave - monitor\n"); | |
6800 | return -1; | |
6801 | } | |
6802 | ||
6803 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | |
8318d78a | 6804 | ctl->tx_rate->bitrate); |
b481de9c | 6805 | |
bb8c093b | 6806 | if (iwl3945_tx_skb(priv, skb, ctl)) |
b481de9c ZY |
6807 | dev_kfree_skb_any(skb); |
6808 | ||
6809 | IWL_DEBUG_MAC80211("leave\n"); | |
6810 | return 0; | |
6811 | } | |
6812 | ||
bb8c093b | 6813 | static int iwl3945_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6814 | struct ieee80211_if_init_conf *conf) |
6815 | { | |
bb8c093b | 6816 | struct iwl3945_priv *priv = hw->priv; |
b481de9c | 6817 | unsigned long flags; |
0795af57 | 6818 | DECLARE_MAC_BUF(mac); |
b481de9c | 6819 | |
32bfd35d | 6820 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6821 | |
32bfd35d JB |
6822 | if (priv->vif) { |
6823 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
864792e3 | 6824 | return -EOPNOTSUPP; |
b481de9c ZY |
6825 | } |
6826 | ||
6827 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6828 | priv->vif = conf->vif; |
b481de9c ZY |
6829 | |
6830 | spin_unlock_irqrestore(&priv->lock, flags); | |
6831 | ||
6832 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6833 | |
6834 | if (conf->mac_addr) { | |
6835 | IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr)); | |
6836 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
6837 | } | |
6838 | ||
5a66926a ZY |
6839 | if (iwl3945_is_ready(priv)) |
6840 | iwl3945_set_mode(priv, conf->type); | |
b481de9c | 6841 | |
b481de9c ZY |
6842 | mutex_unlock(&priv->mutex); |
6843 | ||
5a66926a | 6844 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6845 | return 0; |
6846 | } | |
6847 | ||
6848 | /** | |
bb8c093b | 6849 | * iwl3945_mac_config - mac80211 config callback |
b481de9c ZY |
6850 | * |
6851 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6852 | * be set inappropriately and the driver currently sets the hardware up to | |
6853 | * use it whenever needed. | |
6854 | */ | |
bb8c093b | 6855 | static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
b481de9c | 6856 | { |
bb8c093b CH |
6857 | struct iwl3945_priv *priv = hw->priv; |
6858 | const struct iwl3945_channel_info *ch_info; | |
b481de9c | 6859 | unsigned long flags; |
76bb77e0 | 6860 | int ret = 0; |
b481de9c ZY |
6861 | |
6862 | mutex_lock(&priv->mutex); | |
8318d78a | 6863 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6864 | |
12342c47 ZY |
6865 | priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP); |
6866 | ||
bb8c093b | 6867 | if (!iwl3945_is_ready(priv)) { |
b481de9c | 6868 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6869 | ret = -EIO; |
6870 | goto out; | |
b481de9c ZY |
6871 | } |
6872 | ||
bb8c093b | 6873 | if (unlikely(!iwl3945_param_disable_hw_scan && |
b481de9c | 6874 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6875 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6876 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6877 | mutex_unlock(&priv->mutex); |
a0646470 | 6878 | return 0; |
b481de9c ZY |
6879 | } |
6880 | ||
6881 | spin_lock_irqsave(&priv->lock, flags); | |
6882 | ||
8318d78a JB |
6883 | ch_info = iwl3945_get_channel_info(priv, conf->channel->band, |
6884 | conf->channel->hw_value); | |
b481de9c ZY |
6885 | if (!is_channel_valid(ch_info)) { |
6886 | IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n", | |
8318d78a | 6887 | conf->channel->hw_value, conf->channel->band); |
b481de9c ZY |
6888 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6889 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6890 | ret = -EINVAL; |
6891 | goto out; | |
b481de9c ZY |
6892 | } |
6893 | ||
8318d78a | 6894 | iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value); |
b481de9c | 6895 | |
8318d78a | 6896 | iwl3945_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6897 | |
6898 | /* The list of supported rates and rate mask can be different | |
6899 | * for each phymode; since the phymode may have changed, reset | |
6900 | * the rate mask to what mac80211 lists */ | |
bb8c093b | 6901 | iwl3945_set_rate(priv); |
b481de9c ZY |
6902 | |
6903 | spin_unlock_irqrestore(&priv->lock, flags); | |
6904 | ||
6905 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6906 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6907 | iwl3945_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6908 | goto out; |
b481de9c ZY |
6909 | } |
6910 | #endif | |
6911 | ||
bb8c093b | 6912 | iwl3945_radio_kill_sw(priv, !conf->radio_enabled); |
b481de9c ZY |
6913 | |
6914 | if (!conf->radio_enabled) { | |
6915 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6916 | goto out; |
b481de9c ZY |
6917 | } |
6918 | ||
bb8c093b | 6919 | if (iwl3945_is_rfkill(priv)) { |
b481de9c | 6920 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6921 | ret = -EIO; |
6922 | goto out; | |
b481de9c ZY |
6923 | } |
6924 | ||
bb8c093b | 6925 | iwl3945_set_rate(priv); |
b481de9c ZY |
6926 | |
6927 | if (memcmp(&priv->active_rxon, | |
6928 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
bb8c093b | 6929 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6930 | else |
6931 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6932 | ||
6933 | IWL_DEBUG_MAC80211("leave\n"); | |
6934 | ||
76bb77e0 | 6935 | out: |
a0646470 | 6936 | clear_bit(STATUS_CONF_PENDING, &priv->status); |
b481de9c | 6937 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6938 | return ret; |
b481de9c ZY |
6939 | } |
6940 | ||
bb8c093b | 6941 | static void iwl3945_config_ap(struct iwl3945_priv *priv) |
b481de9c ZY |
6942 | { |
6943 | int rc = 0; | |
6944 | ||
d986bcd1 | 6945 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6946 | return; |
6947 | ||
6948 | /* The following should be done only at AP bring up */ | |
6949 | if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { | |
6950 | ||
6951 | /* RXON - unassoc (to set timing command) */ | |
6952 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6953 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6954 | |
6955 | /* RXON Timing */ | |
bb8c093b CH |
6956 | memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd)); |
6957 | iwl3945_setup_rxon_timing(priv); | |
6958 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6959 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6960 | if (rc) | |
6961 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6962 | "Attempting to continue.\n"); | |
6963 | ||
6964 | /* FIXME: what should be the assoc_id for AP? */ | |
6965 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6966 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6967 | priv->staging_rxon.flags |= | |
6968 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
6969 | else | |
6970 | priv->staging_rxon.flags &= | |
6971 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6972 | ||
6973 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6974 | if (priv->assoc_capability & | |
6975 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6976 | priv->staging_rxon.flags |= | |
6977 | RXON_FLG_SHORT_SLOT_MSK; | |
6978 | else | |
6979 | priv->staging_rxon.flags &= | |
6980 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6981 | ||
6982 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6983 | priv->staging_rxon.flags &= | |
6984 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6985 | } | |
6986 | /* restore RXON assoc */ | |
6987 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
bb8c093b CH |
6988 | iwl3945_commit_rxon(priv); |
6989 | iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0); | |
556f8db7 | 6990 | } |
bb8c093b | 6991 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
6992 | |
6993 | /* FIXME - we need to add code here to detect a totally new | |
6994 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6995 | * clear sta table, add BCAST sta... */ | |
6996 | } | |
6997 | ||
32bfd35d JB |
6998 | static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, |
6999 | struct ieee80211_vif *vif, | |
b481de9c ZY |
7000 | struct ieee80211_if_conf *conf) |
7001 | { | |
bb8c093b | 7002 | struct iwl3945_priv *priv = hw->priv; |
0795af57 | 7003 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
7004 | unsigned long flags; |
7005 | int rc; | |
7006 | ||
7007 | if (conf == NULL) | |
7008 | return -EIO; | |
7009 | ||
4150c572 JB |
7010 | /* XXX: this MUST use conf->mac_addr */ |
7011 | ||
b481de9c ZY |
7012 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && |
7013 | (!conf->beacon || !conf->ssid_len)) { | |
7014 | IWL_DEBUG_MAC80211 | |
7015 | ("Leaving in AP mode because HostAPD is not ready.\n"); | |
7016 | return 0; | |
7017 | } | |
7018 | ||
5a66926a ZY |
7019 | if (!iwl3945_is_alive(priv)) |
7020 | return -EAGAIN; | |
7021 | ||
b481de9c ZY |
7022 | mutex_lock(&priv->mutex); |
7023 | ||
b481de9c | 7024 | if (conf->bssid) |
0795af57 JP |
7025 | IWL_DEBUG_MAC80211("bssid: %s\n", |
7026 | print_mac(mac, conf->bssid)); | |
b481de9c | 7027 | |
4150c572 JB |
7028 | /* |
7029 | * very dubious code was here; the probe filtering flag is never set: | |
7030 | * | |
b481de9c ZY |
7031 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
7032 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 JB |
7033 | */ |
7034 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) { | |
b481de9c ZY |
7035 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
7036 | mutex_unlock(&priv->mutex); | |
7037 | return 0; | |
7038 | } | |
7039 | ||
32bfd35d JB |
7040 | if (priv->vif != vif) { |
7041 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
b481de9c ZY |
7042 | mutex_unlock(&priv->mutex); |
7043 | return 0; | |
7044 | } | |
7045 | ||
7046 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
7047 | if (!conf->bssid) { | |
7048 | conf->bssid = priv->mac_addr; | |
7049 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
0795af57 JP |
7050 | IWL_DEBUG_MAC80211("bssid was set to: %s\n", |
7051 | print_mac(mac, conf->bssid)); | |
b481de9c ZY |
7052 | } |
7053 | if (priv->ibss_beacon) | |
7054 | dev_kfree_skb(priv->ibss_beacon); | |
7055 | ||
7056 | priv->ibss_beacon = conf->beacon; | |
7057 | } | |
7058 | ||
fde3571f MA |
7059 | if (iwl3945_is_rfkill(priv)) |
7060 | goto done; | |
7061 | ||
b481de9c ZY |
7062 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
7063 | !is_multicast_ether_addr(conf->bssid)) { | |
7064 | /* If there is currently a HW scan going on in the background | |
7065 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 7066 | if (iwl3945_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
7067 | IWL_WARNING("Aborted scan still in progress " |
7068 | "after 100ms\n"); | |
7069 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
7070 | mutex_unlock(&priv->mutex); | |
7071 | return -EAGAIN; | |
7072 | } | |
7073 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
7074 | ||
7075 | /* TODO: Audit driver for usage of these members and see | |
7076 | * if mac80211 deprecates them (priv->bssid looks like it | |
7077 | * shouldn't be there, but I haven't scanned the IBSS code | |
7078 | * to verify) - jpk */ | |
7079 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
7080 | ||
7081 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 7082 | iwl3945_config_ap(priv); |
b481de9c | 7083 | else { |
bb8c093b | 7084 | rc = iwl3945_commit_rxon(priv); |
b481de9c | 7085 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc) |
bb8c093b | 7086 | iwl3945_add_station(priv, |
556f8db7 | 7087 | priv->active_rxon.bssid_addr, 1, 0); |
b481de9c ZY |
7088 | } |
7089 | ||
7090 | } else { | |
bb8c093b | 7091 | iwl3945_scan_cancel_timeout(priv, 100); |
b481de9c | 7092 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7093 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7094 | } |
7095 | ||
fde3571f | 7096 | done: |
b481de9c ZY |
7097 | spin_lock_irqsave(&priv->lock, flags); |
7098 | if (!conf->ssid_len) | |
7099 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
7100 | else | |
7101 | memcpy(priv->essid, conf->ssid, conf->ssid_len); | |
7102 | ||
7103 | priv->essid_len = conf->ssid_len; | |
7104 | spin_unlock_irqrestore(&priv->lock, flags); | |
7105 | ||
7106 | IWL_DEBUG_MAC80211("leave\n"); | |
7107 | mutex_unlock(&priv->mutex); | |
7108 | ||
7109 | return 0; | |
7110 | } | |
7111 | ||
bb8c093b | 7112 | static void iwl3945_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
7113 | unsigned int changed_flags, |
7114 | unsigned int *total_flags, | |
7115 | int mc_count, struct dev_addr_list *mc_list) | |
7116 | { | |
7117 | /* | |
7118 | * XXX: dummy | |
bb8c093b | 7119 | * see also iwl3945_connection_init_rx_config |
4150c572 JB |
7120 | */ |
7121 | *total_flags = 0; | |
7122 | } | |
7123 | ||
bb8c093b | 7124 | static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
7125 | struct ieee80211_if_init_conf *conf) |
7126 | { | |
bb8c093b | 7127 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7128 | |
7129 | IWL_DEBUG_MAC80211("enter\n"); | |
7130 | ||
7131 | mutex_lock(&priv->mutex); | |
6ef89d0a | 7132 | |
fde3571f MA |
7133 | if (iwl3945_is_ready_rf(priv)) { |
7134 | iwl3945_scan_cancel_timeout(priv, 100); | |
7135 | cancel_delayed_work(&priv->post_associate); | |
7136 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
7137 | iwl3945_commit_rxon(priv); | |
7138 | } | |
32bfd35d JB |
7139 | if (priv->vif == conf->vif) { |
7140 | priv->vif = NULL; | |
b481de9c ZY |
7141 | memset(priv->bssid, 0, ETH_ALEN); |
7142 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
7143 | priv->essid_len = 0; | |
7144 | } | |
7145 | mutex_unlock(&priv->mutex); | |
7146 | ||
7147 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
7148 | } |
7149 | ||
bb8c093b | 7150 | static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
7151 | { |
7152 | int rc = 0; | |
7153 | unsigned long flags; | |
bb8c093b | 7154 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7155 | |
7156 | IWL_DEBUG_MAC80211("enter\n"); | |
7157 | ||
15e869d8 | 7158 | mutex_lock(&priv->mutex); |
b481de9c ZY |
7159 | spin_lock_irqsave(&priv->lock, flags); |
7160 | ||
bb8c093b | 7161 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7162 | rc = -EIO; |
7163 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
7164 | goto out_unlock; | |
7165 | } | |
7166 | ||
7167 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */ | |
7168 | rc = -EIO; | |
7169 | IWL_ERROR("ERROR: APs don't scan\n"); | |
7170 | goto out_unlock; | |
7171 | } | |
7172 | ||
7878a5a4 MA |
7173 | /* we don't schedule scan within next_scan_jiffies period */ |
7174 | if (priv->next_scan_jiffies && | |
7175 | time_after(priv->next_scan_jiffies, jiffies)) { | |
7176 | rc = -EAGAIN; | |
7177 | goto out_unlock; | |
7178 | } | |
b481de9c | 7179 | /* if we just finished scan ask for delay */ |
7878a5a4 MA |
7180 | if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies + |
7181 | IWL_DELAY_NEXT_SCAN, jiffies)) { | |
b481de9c ZY |
7182 | rc = -EAGAIN; |
7183 | goto out_unlock; | |
7184 | } | |
7185 | if (len) { | |
7878a5a4 | 7186 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
bb8c093b | 7187 | iwl3945_escape_essid(ssid, len), (int)len); |
b481de9c ZY |
7188 | |
7189 | priv->one_direct_scan = 1; | |
7190 | priv->direct_ssid_len = (u8) | |
7191 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
7192 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
6ef89d0a MA |
7193 | } else |
7194 | priv->one_direct_scan = 0; | |
b481de9c | 7195 | |
bb8c093b | 7196 | rc = iwl3945_scan_initiate(priv); |
b481de9c ZY |
7197 | |
7198 | IWL_DEBUG_MAC80211("leave\n"); | |
7199 | ||
7200 | out_unlock: | |
7201 | spin_unlock_irqrestore(&priv->lock, flags); | |
15e869d8 | 7202 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
7203 | |
7204 | return rc; | |
7205 | } | |
7206 | ||
bb8c093b | 7207 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
7208 | const u8 *local_addr, const u8 *addr, |
7209 | struct ieee80211_key_conf *key) | |
7210 | { | |
bb8c093b | 7211 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7212 | int rc = 0; |
7213 | u8 sta_id; | |
7214 | ||
7215 | IWL_DEBUG_MAC80211("enter\n"); | |
7216 | ||
bb8c093b | 7217 | if (!iwl3945_param_hwcrypto) { |
b481de9c ZY |
7218 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
7219 | return -EOPNOTSUPP; | |
7220 | } | |
7221 | ||
7222 | if (is_zero_ether_addr(addr)) | |
7223 | /* only support pairwise keys */ | |
7224 | return -EOPNOTSUPP; | |
7225 | ||
bb8c093b | 7226 | sta_id = iwl3945_hw_find_station(priv, addr); |
b481de9c | 7227 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
7228 | DECLARE_MAC_BUF(mac); |
7229 | ||
7230 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
7231 | print_mac(mac, addr)); | |
b481de9c ZY |
7232 | return -EINVAL; |
7233 | } | |
7234 | ||
7235 | mutex_lock(&priv->mutex); | |
7236 | ||
bb8c093b | 7237 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 7238 | |
b481de9c ZY |
7239 | switch (cmd) { |
7240 | case SET_KEY: | |
bb8c093b | 7241 | rc = iwl3945_update_sta_key_info(priv, key, sta_id); |
b481de9c | 7242 | if (!rc) { |
bb8c093b CH |
7243 | iwl3945_set_rxon_hwcrypto(priv, 1); |
7244 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
7245 | key->hw_key_idx = sta_id; |
7246 | IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n"); | |
7247 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
7248 | } | |
7249 | break; | |
7250 | case DISABLE_KEY: | |
bb8c093b | 7251 | rc = iwl3945_clear_sta_key_info(priv, sta_id); |
b481de9c | 7252 | if (!rc) { |
bb8c093b CH |
7253 | iwl3945_set_rxon_hwcrypto(priv, 0); |
7254 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
7255 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); |
7256 | } | |
7257 | break; | |
7258 | default: | |
7259 | rc = -EINVAL; | |
7260 | } | |
7261 | ||
7262 | IWL_DEBUG_MAC80211("leave\n"); | |
7263 | mutex_unlock(&priv->mutex); | |
7264 | ||
7265 | return rc; | |
7266 | } | |
7267 | ||
bb8c093b | 7268 | static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue, |
b481de9c ZY |
7269 | const struct ieee80211_tx_queue_params *params) |
7270 | { | |
bb8c093b | 7271 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7272 | unsigned long flags; |
7273 | int q; | |
b481de9c ZY |
7274 | |
7275 | IWL_DEBUG_MAC80211("enter\n"); | |
7276 | ||
bb8c093b | 7277 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7278 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7279 | return -EIO; | |
7280 | } | |
7281 | ||
7282 | if (queue >= AC_NUM) { | |
7283 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
7284 | return 0; | |
7285 | } | |
7286 | ||
b481de9c ZY |
7287 | if (!priv->qos_data.qos_enable) { |
7288 | priv->qos_data.qos_active = 0; | |
7289 | IWL_DEBUG_MAC80211("leave - qos not enabled\n"); | |
7290 | return 0; | |
7291 | } | |
7292 | q = AC_NUM - 1 - queue; | |
7293 | ||
7294 | spin_lock_irqsave(&priv->lock, flags); | |
7295 | ||
7296 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
7297 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
7298 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
7299 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 7300 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
7301 | |
7302 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
7303 | priv->qos_data.qos_active = 1; | |
7304 | ||
7305 | spin_unlock_irqrestore(&priv->lock, flags); | |
7306 | ||
7307 | mutex_lock(&priv->mutex); | |
7308 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b CH |
7309 | iwl3945_activate_qos(priv, 1); |
7310 | else if (priv->assoc_id && iwl3945_is_associated(priv)) | |
7311 | iwl3945_activate_qos(priv, 0); | |
b481de9c ZY |
7312 | |
7313 | mutex_unlock(&priv->mutex); | |
7314 | ||
b481de9c ZY |
7315 | IWL_DEBUG_MAC80211("leave\n"); |
7316 | return 0; | |
7317 | } | |
7318 | ||
bb8c093b | 7319 | static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7320 | struct ieee80211_tx_queue_stats *stats) |
7321 | { | |
bb8c093b | 7322 | struct iwl3945_priv *priv = hw->priv; |
b481de9c | 7323 | int i, avail; |
bb8c093b CH |
7324 | struct iwl3945_tx_queue *txq; |
7325 | struct iwl3945_queue *q; | |
b481de9c ZY |
7326 | unsigned long flags; |
7327 | ||
7328 | IWL_DEBUG_MAC80211("enter\n"); | |
7329 | ||
bb8c093b | 7330 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7331 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7332 | return -EIO; | |
7333 | } | |
7334 | ||
7335 | spin_lock_irqsave(&priv->lock, flags); | |
7336 | ||
7337 | for (i = 0; i < AC_NUM; i++) { | |
7338 | txq = &priv->txq[i]; | |
7339 | q = &txq->q; | |
bb8c093b | 7340 | avail = iwl3945_queue_space(q); |
b481de9c ZY |
7341 | |
7342 | stats->data[i].len = q->n_window - avail; | |
7343 | stats->data[i].limit = q->n_window - q->high_mark; | |
7344 | stats->data[i].count = q->n_window; | |
7345 | ||
7346 | } | |
7347 | spin_unlock_irqrestore(&priv->lock, flags); | |
7348 | ||
7349 | IWL_DEBUG_MAC80211("leave\n"); | |
7350 | ||
7351 | return 0; | |
7352 | } | |
7353 | ||
bb8c093b | 7354 | static int iwl3945_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7355 | struct ieee80211_low_level_stats *stats) |
7356 | { | |
7357 | IWL_DEBUG_MAC80211("enter\n"); | |
7358 | IWL_DEBUG_MAC80211("leave\n"); | |
7359 | ||
7360 | return 0; | |
7361 | } | |
7362 | ||
bb8c093b | 7363 | static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw) |
b481de9c ZY |
7364 | { |
7365 | IWL_DEBUG_MAC80211("enter\n"); | |
7366 | IWL_DEBUG_MAC80211("leave\n"); | |
7367 | ||
7368 | return 0; | |
7369 | } | |
7370 | ||
bb8c093b | 7371 | static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7372 | { |
bb8c093b | 7373 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7374 | unsigned long flags; |
7375 | ||
7376 | mutex_lock(&priv->mutex); | |
7377 | IWL_DEBUG_MAC80211("enter\n"); | |
7378 | ||
bb8c093b | 7379 | iwl3945_reset_qos(priv); |
292ae174 | 7380 | |
b481de9c ZY |
7381 | cancel_delayed_work(&priv->post_associate); |
7382 | ||
7383 | spin_lock_irqsave(&priv->lock, flags); | |
7384 | priv->assoc_id = 0; | |
7385 | priv->assoc_capability = 0; | |
7386 | priv->call_post_assoc_from_beacon = 0; | |
7387 | ||
7388 | /* new association get rid of ibss beacon skb */ | |
7389 | if (priv->ibss_beacon) | |
7390 | dev_kfree_skb(priv->ibss_beacon); | |
7391 | ||
7392 | priv->ibss_beacon = NULL; | |
7393 | ||
7394 | priv->beacon_int = priv->hw->conf.beacon_int; | |
7395 | priv->timestamp1 = 0; | |
7396 | priv->timestamp0 = 0; | |
7397 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA)) | |
7398 | priv->beacon_int = 0; | |
7399 | ||
7400 | spin_unlock_irqrestore(&priv->lock, flags); | |
7401 | ||
fde3571f MA |
7402 | if (!iwl3945_is_ready_rf(priv)) { |
7403 | IWL_DEBUG_MAC80211("leave - not ready\n"); | |
7404 | mutex_unlock(&priv->mutex); | |
7405 | return; | |
7406 | } | |
7407 | ||
15e869d8 MA |
7408 | /* we are restarting association process |
7409 | * clear RXON_FILTER_ASSOC_MSK bit | |
7410 | */ | |
7411 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
bb8c093b | 7412 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 7413 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7414 | iwl3945_commit_rxon(priv); |
15e869d8 MA |
7415 | } |
7416 | ||
b481de9c ZY |
7417 | /* Per mac80211.h: This is only used in IBSS mode... */ |
7418 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
15e869d8 | 7419 | |
b481de9c ZY |
7420 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7421 | mutex_unlock(&priv->mutex); | |
7422 | return; | |
b481de9c ZY |
7423 | } |
7424 | ||
7425 | priv->only_active_channel = 0; | |
7426 | ||
bb8c093b | 7427 | iwl3945_set_rate(priv); |
b481de9c ZY |
7428 | |
7429 | mutex_unlock(&priv->mutex); | |
7430 | ||
7431 | IWL_DEBUG_MAC80211("leave\n"); | |
7432 | ||
7433 | } | |
7434 | ||
bb8c093b | 7435 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
7436 | struct ieee80211_tx_control *control) |
7437 | { | |
bb8c093b | 7438 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7439 | unsigned long flags; |
7440 | ||
7441 | mutex_lock(&priv->mutex); | |
7442 | IWL_DEBUG_MAC80211("enter\n"); | |
7443 | ||
bb8c093b | 7444 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7445 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7446 | mutex_unlock(&priv->mutex); | |
7447 | return -EIO; | |
7448 | } | |
7449 | ||
7450 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
7451 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); | |
7452 | mutex_unlock(&priv->mutex); | |
7453 | return -EIO; | |
7454 | } | |
7455 | ||
7456 | spin_lock_irqsave(&priv->lock, flags); | |
7457 | ||
7458 | if (priv->ibss_beacon) | |
7459 | dev_kfree_skb(priv->ibss_beacon); | |
7460 | ||
7461 | priv->ibss_beacon = skb; | |
7462 | ||
7463 | priv->assoc_id = 0; | |
7464 | ||
7465 | IWL_DEBUG_MAC80211("leave\n"); | |
7466 | spin_unlock_irqrestore(&priv->lock, flags); | |
7467 | ||
bb8c093b | 7468 | iwl3945_reset_qos(priv); |
b481de9c ZY |
7469 | |
7470 | queue_work(priv->workqueue, &priv->post_associate.work); | |
7471 | ||
7472 | mutex_unlock(&priv->mutex); | |
7473 | ||
7474 | return 0; | |
7475 | } | |
7476 | ||
7477 | /***************************************************************************** | |
7478 | * | |
7479 | * sysfs attributes | |
7480 | * | |
7481 | *****************************************************************************/ | |
7482 | ||
c8b0e6e1 | 7483 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
7484 | |
7485 | /* | |
7486 | * The following adds a new attribute to the sysfs representation | |
7487 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7488 | * used for controlling the debug level. | |
7489 | * | |
7490 | * See the level definitions in iwl for details. | |
7491 | */ | |
7492 | ||
7493 | static ssize_t show_debug_level(struct device_driver *d, char *buf) | |
7494 | { | |
bb8c093b | 7495 | return sprintf(buf, "0x%08X\n", iwl3945_debug_level); |
b481de9c ZY |
7496 | } |
7497 | static ssize_t store_debug_level(struct device_driver *d, | |
7498 | const char *buf, size_t count) | |
7499 | { | |
7500 | char *p = (char *)buf; | |
7501 | u32 val; | |
7502 | ||
7503 | val = simple_strtoul(p, &p, 0); | |
7504 | if (p == buf) | |
7505 | printk(KERN_INFO DRV_NAME | |
7506 | ": %s is not in hex or decimal form.\n", buf); | |
7507 | else | |
bb8c093b | 7508 | iwl3945_debug_level = val; |
b481de9c ZY |
7509 | |
7510 | return strnlen(buf, count); | |
7511 | } | |
7512 | ||
7513 | static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
7514 | show_debug_level, store_debug_level); | |
7515 | ||
c8b0e6e1 | 7516 | #endif /* CONFIG_IWL3945_DEBUG */ |
b481de9c ZY |
7517 | |
7518 | static ssize_t show_rf_kill(struct device *d, | |
7519 | struct device_attribute *attr, char *buf) | |
7520 | { | |
7521 | /* | |
7522 | * 0 - RF kill not enabled | |
7523 | * 1 - SW based RF kill active (sysfs) | |
7524 | * 2 - HW based RF kill active | |
7525 | * 3 - Both HW and SW based RF kill active | |
7526 | */ | |
bb8c093b | 7527 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7528 | int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) | |
7529 | (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0); | |
7530 | ||
7531 | return sprintf(buf, "%i\n", val); | |
7532 | } | |
7533 | ||
7534 | static ssize_t store_rf_kill(struct device *d, | |
7535 | struct device_attribute *attr, | |
7536 | const char *buf, size_t count) | |
7537 | { | |
bb8c093b | 7538 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7539 | |
7540 | mutex_lock(&priv->mutex); | |
bb8c093b | 7541 | iwl3945_radio_kill_sw(priv, buf[0] == '1'); |
b481de9c ZY |
7542 | mutex_unlock(&priv->mutex); |
7543 | ||
7544 | return count; | |
7545 | } | |
7546 | ||
7547 | static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill); | |
7548 | ||
7549 | static ssize_t show_temperature(struct device *d, | |
7550 | struct device_attribute *attr, char *buf) | |
7551 | { | |
bb8c093b | 7552 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c | 7553 | |
bb8c093b | 7554 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7555 | return -EAGAIN; |
7556 | ||
bb8c093b | 7557 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
7558 | } |
7559 | ||
7560 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7561 | ||
7562 | static ssize_t show_rs_window(struct device *d, | |
7563 | struct device_attribute *attr, | |
7564 | char *buf) | |
7565 | { | |
bb8c093b CH |
7566 | struct iwl3945_priv *priv = d->driver_data; |
7567 | return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID); | |
b481de9c ZY |
7568 | } |
7569 | static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL); | |
7570 | ||
7571 | static ssize_t show_tx_power(struct device *d, | |
7572 | struct device_attribute *attr, char *buf) | |
7573 | { | |
bb8c093b | 7574 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7575 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7576 | } | |
7577 | ||
7578 | static ssize_t store_tx_power(struct device *d, | |
7579 | struct device_attribute *attr, | |
7580 | const char *buf, size_t count) | |
7581 | { | |
bb8c093b | 7582 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7583 | char *p = (char *)buf; |
7584 | u32 val; | |
7585 | ||
7586 | val = simple_strtoul(p, &p, 10); | |
7587 | if (p == buf) | |
7588 | printk(KERN_INFO DRV_NAME | |
7589 | ": %s is not in decimal form.\n", buf); | |
7590 | else | |
bb8c093b | 7591 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7592 | |
7593 | return count; | |
7594 | } | |
7595 | ||
7596 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7597 | ||
7598 | static ssize_t show_flags(struct device *d, | |
7599 | struct device_attribute *attr, char *buf) | |
7600 | { | |
bb8c093b | 7601 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7602 | |
7603 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
7604 | } | |
7605 | ||
7606 | static ssize_t store_flags(struct device *d, | |
7607 | struct device_attribute *attr, | |
7608 | const char *buf, size_t count) | |
7609 | { | |
bb8c093b | 7610 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7611 | u32 flags = simple_strtoul(buf, NULL, 0); |
7612 | ||
7613 | mutex_lock(&priv->mutex); | |
7614 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
7615 | /* Cancel any currently running scans... */ | |
bb8c093b | 7616 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7617 | IWL_WARNING("Could not cancel scan.\n"); |
7618 | else { | |
7619 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7620 | flags); | |
7621 | priv->staging_rxon.flags = cpu_to_le32(flags); | |
bb8c093b | 7622 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7623 | } |
7624 | } | |
7625 | mutex_unlock(&priv->mutex); | |
7626 | ||
7627 | return count; | |
7628 | } | |
7629 | ||
7630 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7631 | ||
7632 | static ssize_t show_filter_flags(struct device *d, | |
7633 | struct device_attribute *attr, char *buf) | |
7634 | { | |
bb8c093b | 7635 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7636 | |
7637 | return sprintf(buf, "0x%04X\n", | |
7638 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
7639 | } | |
7640 | ||
7641 | static ssize_t store_filter_flags(struct device *d, | |
7642 | struct device_attribute *attr, | |
7643 | const char *buf, size_t count) | |
7644 | { | |
bb8c093b | 7645 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7646 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7647 | ||
7648 | mutex_lock(&priv->mutex); | |
7649 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
7650 | /* Cancel any currently running scans... */ | |
bb8c093b | 7651 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7652 | IWL_WARNING("Could not cancel scan.\n"); |
7653 | else { | |
7654 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7655 | "0x%04X\n", filter_flags); | |
7656 | priv->staging_rxon.filter_flags = | |
7657 | cpu_to_le32(filter_flags); | |
bb8c093b | 7658 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7659 | } |
7660 | } | |
7661 | mutex_unlock(&priv->mutex); | |
7662 | ||
7663 | return count; | |
7664 | } | |
7665 | ||
7666 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7667 | store_filter_flags); | |
7668 | ||
c8b0e6e1 | 7669 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7670 | |
7671 | static ssize_t show_measurement(struct device *d, | |
7672 | struct device_attribute *attr, char *buf) | |
7673 | { | |
bb8c093b CH |
7674 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7675 | struct iwl3945_spectrum_notification measure_report; | |
b481de9c ZY |
7676 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
7677 | u8 *data = (u8 *) & measure_report; | |
7678 | unsigned long flags; | |
7679 | ||
7680 | spin_lock_irqsave(&priv->lock, flags); | |
7681 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7682 | spin_unlock_irqrestore(&priv->lock, flags); | |
7683 | return 0; | |
7684 | } | |
7685 | memcpy(&measure_report, &priv->measure_report, size); | |
7686 | priv->measurement_status = 0; | |
7687 | spin_unlock_irqrestore(&priv->lock, flags); | |
7688 | ||
7689 | while (size && (PAGE_SIZE - len)) { | |
7690 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7691 | PAGE_SIZE - len, 1); | |
7692 | len = strlen(buf); | |
7693 | if (PAGE_SIZE - len) | |
7694 | buf[len++] = '\n'; | |
7695 | ||
7696 | ofs += 16; | |
7697 | size -= min(size, 16U); | |
7698 | } | |
7699 | ||
7700 | return len; | |
7701 | } | |
7702 | ||
7703 | static ssize_t store_measurement(struct device *d, | |
7704 | struct device_attribute *attr, | |
7705 | const char *buf, size_t count) | |
7706 | { | |
bb8c093b | 7707 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7708 | struct ieee80211_measurement_params params = { |
7709 | .channel = le16_to_cpu(priv->active_rxon.channel), | |
7710 | .start_time = cpu_to_le64(priv->last_tsf), | |
7711 | .duration = cpu_to_le16(1), | |
7712 | }; | |
7713 | u8 type = IWL_MEASURE_BASIC; | |
7714 | u8 buffer[32]; | |
7715 | u8 channel; | |
7716 | ||
7717 | if (count) { | |
7718 | char *p = buffer; | |
7719 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7720 | channel = simple_strtoul(p, NULL, 0); | |
7721 | if (channel) | |
7722 | params.channel = channel; | |
7723 | ||
7724 | p = buffer; | |
7725 | while (*p && *p != ' ') | |
7726 | p++; | |
7727 | if (*p) | |
7728 | type = simple_strtoul(p + 1, NULL, 0); | |
7729 | } | |
7730 | ||
7731 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7732 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7733 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7734 | |
7735 | return count; | |
7736 | } | |
7737 | ||
7738 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7739 | show_measurement, store_measurement); | |
c8b0e6e1 | 7740 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 7741 | |
b481de9c ZY |
7742 | static ssize_t store_retry_rate(struct device *d, |
7743 | struct device_attribute *attr, | |
7744 | const char *buf, size_t count) | |
7745 | { | |
bb8c093b | 7746 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7747 | |
7748 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7749 | if (priv->retry_rate <= 0) | |
7750 | priv->retry_rate = 1; | |
7751 | ||
7752 | return count; | |
7753 | } | |
7754 | ||
7755 | static ssize_t show_retry_rate(struct device *d, | |
7756 | struct device_attribute *attr, char *buf) | |
7757 | { | |
bb8c093b | 7758 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7759 | return sprintf(buf, "%d", priv->retry_rate); |
7760 | } | |
7761 | ||
7762 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7763 | store_retry_rate); | |
7764 | ||
7765 | static ssize_t store_power_level(struct device *d, | |
7766 | struct device_attribute *attr, | |
7767 | const char *buf, size_t count) | |
7768 | { | |
bb8c093b | 7769 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7770 | int rc; |
7771 | int mode; | |
7772 | ||
7773 | mode = simple_strtoul(buf, NULL, 0); | |
7774 | mutex_lock(&priv->mutex); | |
7775 | ||
bb8c093b | 7776 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
7777 | rc = -EAGAIN; |
7778 | goto out; | |
7779 | } | |
7780 | ||
7781 | if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) | |
7782 | mode = IWL_POWER_AC; | |
7783 | else | |
7784 | mode |= IWL_POWER_ENABLED; | |
7785 | ||
7786 | if (mode != priv->power_mode) { | |
bb8c093b | 7787 | rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7788 | if (rc) { |
7789 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7790 | goto out; | |
7791 | } | |
7792 | priv->power_mode = mode; | |
7793 | } | |
7794 | ||
7795 | rc = count; | |
7796 | ||
7797 | out: | |
7798 | mutex_unlock(&priv->mutex); | |
7799 | return rc; | |
7800 | } | |
7801 | ||
7802 | #define MAX_WX_STRING 80 | |
7803 | ||
7804 | /* Values are in microsecond */ | |
7805 | static const s32 timeout_duration[] = { | |
7806 | 350000, | |
7807 | 250000, | |
7808 | 75000, | |
7809 | 37000, | |
7810 | 25000, | |
7811 | }; | |
7812 | static const s32 period_duration[] = { | |
7813 | 400000, | |
7814 | 700000, | |
7815 | 1000000, | |
7816 | 1000000, | |
7817 | 1000000 | |
7818 | }; | |
7819 | ||
7820 | static ssize_t show_power_level(struct device *d, | |
7821 | struct device_attribute *attr, char *buf) | |
7822 | { | |
bb8c093b | 7823 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7824 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7825 | char *p = buf; | |
7826 | ||
7827 | p += sprintf(p, "%d ", level); | |
7828 | switch (level) { | |
7829 | case IWL_POWER_MODE_CAM: | |
7830 | case IWL_POWER_AC: | |
7831 | p += sprintf(p, "(AC)"); | |
7832 | break; | |
7833 | case IWL_POWER_BATTERY: | |
7834 | p += sprintf(p, "(BATTERY)"); | |
7835 | break; | |
7836 | default: | |
7837 | p += sprintf(p, | |
7838 | "(Timeout %dms, Period %dms)", | |
7839 | timeout_duration[level - 1] / 1000, | |
7840 | period_duration[level - 1] / 1000); | |
7841 | } | |
7842 | ||
7843 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7844 | p += sprintf(p, " OFF\n"); | |
7845 | else | |
7846 | p += sprintf(p, " \n"); | |
7847 | ||
7848 | return (p - buf + 1); | |
7849 | ||
7850 | } | |
7851 | ||
7852 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7853 | store_power_level); | |
7854 | ||
7855 | static ssize_t show_channels(struct device *d, | |
7856 | struct device_attribute *attr, char *buf) | |
7857 | { | |
8318d78a JB |
7858 | /* all this shit doesn't belong into sysfs anyway */ |
7859 | return 0; | |
b481de9c ZY |
7860 | } |
7861 | ||
7862 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7863 | ||
7864 | static ssize_t show_statistics(struct device *d, | |
7865 | struct device_attribute *attr, char *buf) | |
7866 | { | |
bb8c093b CH |
7867 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7868 | u32 size = sizeof(struct iwl3945_notif_statistics); | |
b481de9c ZY |
7869 | u32 len = 0, ofs = 0; |
7870 | u8 *data = (u8 *) & priv->statistics; | |
7871 | int rc = 0; | |
7872 | ||
bb8c093b | 7873 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7874 | return -EAGAIN; |
7875 | ||
7876 | mutex_lock(&priv->mutex); | |
bb8c093b | 7877 | rc = iwl3945_send_statistics_request(priv); |
b481de9c ZY |
7878 | mutex_unlock(&priv->mutex); |
7879 | ||
7880 | if (rc) { | |
7881 | len = sprintf(buf, | |
7882 | "Error sending statistics request: 0x%08X\n", rc); | |
7883 | return len; | |
7884 | } | |
7885 | ||
7886 | while (size && (PAGE_SIZE - len)) { | |
7887 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7888 | PAGE_SIZE - len, 1); | |
7889 | len = strlen(buf); | |
7890 | if (PAGE_SIZE - len) | |
7891 | buf[len++] = '\n'; | |
7892 | ||
7893 | ofs += 16; | |
7894 | size -= min(size, 16U); | |
7895 | } | |
7896 | ||
7897 | return len; | |
7898 | } | |
7899 | ||
7900 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7901 | ||
7902 | static ssize_t show_antenna(struct device *d, | |
7903 | struct device_attribute *attr, char *buf) | |
7904 | { | |
bb8c093b | 7905 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c | 7906 | |
bb8c093b | 7907 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7908 | return -EAGAIN; |
7909 | ||
7910 | return sprintf(buf, "%d\n", priv->antenna); | |
7911 | } | |
7912 | ||
7913 | static ssize_t store_antenna(struct device *d, | |
7914 | struct device_attribute *attr, | |
7915 | const char *buf, size_t count) | |
7916 | { | |
7917 | int ant; | |
bb8c093b | 7918 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7919 | |
7920 | if (count == 0) | |
7921 | return 0; | |
7922 | ||
7923 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7924 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7925 | return count; | |
7926 | } | |
7927 | ||
7928 | if ((ant >= 0) && (ant <= 2)) { | |
7929 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7930 | priv->antenna = (enum iwl3945_antenna)ant; |
b481de9c ZY |
7931 | } else |
7932 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7933 | ||
7934 | ||
7935 | return count; | |
7936 | } | |
7937 | ||
7938 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7939 | ||
7940 | static ssize_t show_status(struct device *d, | |
7941 | struct device_attribute *attr, char *buf) | |
7942 | { | |
bb8c093b CH |
7943 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
7944 | if (!iwl3945_is_alive(priv)) | |
b481de9c ZY |
7945 | return -EAGAIN; |
7946 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7947 | } | |
7948 | ||
7949 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7950 | ||
7951 | static ssize_t dump_error_log(struct device *d, | |
7952 | struct device_attribute *attr, | |
7953 | const char *buf, size_t count) | |
7954 | { | |
7955 | char *p = (char *)buf; | |
7956 | ||
7957 | if (p[0] == '1') | |
bb8c093b | 7958 | iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data); |
b481de9c ZY |
7959 | |
7960 | return strnlen(buf, count); | |
7961 | } | |
7962 | ||
7963 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7964 | ||
7965 | static ssize_t dump_event_log(struct device *d, | |
7966 | struct device_attribute *attr, | |
7967 | const char *buf, size_t count) | |
7968 | { | |
7969 | char *p = (char *)buf; | |
7970 | ||
7971 | if (p[0] == '1') | |
bb8c093b | 7972 | iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data); |
b481de9c ZY |
7973 | |
7974 | return strnlen(buf, count); | |
7975 | } | |
7976 | ||
7977 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7978 | ||
7979 | /***************************************************************************** | |
7980 | * | |
7981 | * driver setup and teardown | |
7982 | * | |
7983 | *****************************************************************************/ | |
7984 | ||
bb8c093b | 7985 | static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv) |
b481de9c ZY |
7986 | { |
7987 | priv->workqueue = create_workqueue(DRV_NAME); | |
7988 | ||
7989 | init_waitqueue_head(&priv->wait_command_queue); | |
7990 | ||
bb8c093b CH |
7991 | INIT_WORK(&priv->up, iwl3945_bg_up); |
7992 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
7993 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
7994 | INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed); | |
7995 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
7996 | INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan); | |
7997 | INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill); | |
7998 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); | |
7999 | INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate); | |
8000 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); | |
8001 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
8002 | INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check); | |
8003 | ||
8004 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
8005 | |
8006 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 8007 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
8008 | } |
8009 | ||
bb8c093b | 8010 | static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv) |
b481de9c | 8011 | { |
bb8c093b | 8012 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 8013 | |
e47eb6ad | 8014 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
8015 | cancel_delayed_work(&priv->scan_check); |
8016 | cancel_delayed_work(&priv->alive_start); | |
8017 | cancel_delayed_work(&priv->post_associate); | |
8018 | cancel_work_sync(&priv->beacon_update); | |
8019 | } | |
8020 | ||
bb8c093b | 8021 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
8022 | &dev_attr_antenna.attr, |
8023 | &dev_attr_channels.attr, | |
8024 | &dev_attr_dump_errors.attr, | |
8025 | &dev_attr_dump_events.attr, | |
8026 | &dev_attr_flags.attr, | |
8027 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 8028 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
8029 | &dev_attr_measurement.attr, |
8030 | #endif | |
8031 | &dev_attr_power_level.attr, | |
b481de9c ZY |
8032 | &dev_attr_retry_rate.attr, |
8033 | &dev_attr_rf_kill.attr, | |
8034 | &dev_attr_rs_window.attr, | |
8035 | &dev_attr_statistics.attr, | |
8036 | &dev_attr_status.attr, | |
8037 | &dev_attr_temperature.attr, | |
b481de9c ZY |
8038 | &dev_attr_tx_power.attr, |
8039 | ||
8040 | NULL | |
8041 | }; | |
8042 | ||
bb8c093b | 8043 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 8044 | .name = NULL, /* put in device directory */ |
bb8c093b | 8045 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
8046 | }; |
8047 | ||
bb8c093b CH |
8048 | static struct ieee80211_ops iwl3945_hw_ops = { |
8049 | .tx = iwl3945_mac_tx, | |
8050 | .start = iwl3945_mac_start, | |
8051 | .stop = iwl3945_mac_stop, | |
8052 | .add_interface = iwl3945_mac_add_interface, | |
8053 | .remove_interface = iwl3945_mac_remove_interface, | |
8054 | .config = iwl3945_mac_config, | |
8055 | .config_interface = iwl3945_mac_config_interface, | |
8056 | .configure_filter = iwl3945_configure_filter, | |
8057 | .set_key = iwl3945_mac_set_key, | |
8058 | .get_stats = iwl3945_mac_get_stats, | |
8059 | .get_tx_stats = iwl3945_mac_get_tx_stats, | |
8060 | .conf_tx = iwl3945_mac_conf_tx, | |
8061 | .get_tsf = iwl3945_mac_get_tsf, | |
8062 | .reset_tsf = iwl3945_mac_reset_tsf, | |
8063 | .beacon_update = iwl3945_mac_beacon_update, | |
8064 | .hw_scan = iwl3945_mac_hw_scan | |
b481de9c ZY |
8065 | }; |
8066 | ||
bb8c093b | 8067 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
8068 | { |
8069 | int err = 0; | |
8070 | u32 pci_id; | |
bb8c093b | 8071 | struct iwl3945_priv *priv; |
b481de9c ZY |
8072 | struct ieee80211_hw *hw; |
8073 | int i; | |
5a66926a | 8074 | DECLARE_MAC_BUF(mac); |
b481de9c | 8075 | |
6440adb5 BC |
8076 | /* Disabling hardware scan means that mac80211 will perform scans |
8077 | * "the hard way", rather than using device's scan. */ | |
bb8c093b | 8078 | if (iwl3945_param_disable_hw_scan) { |
b481de9c | 8079 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
bb8c093b | 8080 | iwl3945_hw_ops.hw_scan = NULL; |
b481de9c ZY |
8081 | } |
8082 | ||
bb8c093b CH |
8083 | if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) || |
8084 | (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) { | |
b481de9c ZY |
8085 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", |
8086 | IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES); | |
8087 | err = -EINVAL; | |
8088 | goto out; | |
8089 | } | |
8090 | ||
8091 | /* mac80211 allocates memory for this device instance, including | |
8092 | * space for this driver's private structure */ | |
bb8c093b | 8093 | hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops); |
b481de9c ZY |
8094 | if (hw == NULL) { |
8095 | IWL_ERROR("Can not allocate network device\n"); | |
8096 | err = -ENOMEM; | |
8097 | goto out; | |
8098 | } | |
8099 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
8100 | ||
f51359a8 JB |
8101 | hw->rate_control_algorithm = "iwl-3945-rs"; |
8102 | ||
b481de9c ZY |
8103 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); |
8104 | priv = hw->priv; | |
8105 | priv->hw = hw; | |
8106 | ||
8107 | priv->pci_dev = pdev; | |
6440adb5 BC |
8108 | |
8109 | /* Select antenna (may be helpful if only one antenna is connected) */ | |
bb8c093b | 8110 | priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna; |
c8b0e6e1 | 8111 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8112 | iwl3945_debug_level = iwl3945_param_debug; |
b481de9c ZY |
8113 | atomic_set(&priv->restrict_refcnt, 0); |
8114 | #endif | |
8115 | priv->retry_rate = 1; | |
8116 | ||
8117 | priv->ibss_beacon = NULL; | |
8118 | ||
8119 | /* Tell mac80211 and its clients (e.g. Wireless Extensions) | |
8120 | * the range of signal quality values that we'll provide. | |
8121 | * Negative values for level/noise indicate that we'll provide dBm. | |
8122 | * For WE, at least, non-0 values here *enable* display of values | |
8123 | * in app (iwconfig). */ | |
8124 | hw->max_rssi = -20; /* signal level, negative indicates dBm */ | |
8125 | hw->max_noise = -20; /* noise level, negative indicates dBm */ | |
8126 | hw->max_signal = 100; /* link quality indication (%) */ | |
8127 | ||
8128 | /* Tell mac80211 our Tx characteristics */ | |
8129 | hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE; | |
8130 | ||
6440adb5 | 8131 | /* 4 EDCA QOS priorities */ |
b481de9c ZY |
8132 | hw->queues = 4; |
8133 | ||
8134 | spin_lock_init(&priv->lock); | |
8135 | spin_lock_init(&priv->power_data.lock); | |
8136 | spin_lock_init(&priv->sta_lock); | |
8137 | spin_lock_init(&priv->hcmd_lock); | |
8138 | ||
8139 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) | |
8140 | INIT_LIST_HEAD(&priv->ibss_mac_hash[i]); | |
8141 | ||
8142 | INIT_LIST_HEAD(&priv->free_frames); | |
8143 | ||
8144 | mutex_init(&priv->mutex); | |
8145 | if (pci_enable_device(pdev)) { | |
8146 | err = -ENODEV; | |
8147 | goto out_ieee80211_free_hw; | |
8148 | } | |
8149 | ||
8150 | pci_set_master(pdev); | |
8151 | ||
6440adb5 | 8152 | /* Clear the driver's (not device's) station table */ |
bb8c093b | 8153 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
8154 | |
8155 | priv->data_retry_limit = -1; | |
8156 | priv->ieee_channels = NULL; | |
8157 | priv->ieee_rates = NULL; | |
8318d78a | 8158 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
8159 | |
8160 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
8161 | if (!err) | |
8162 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
8163 | if (err) { | |
8164 | printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n"); | |
8165 | goto out_pci_disable_device; | |
8166 | } | |
8167 | ||
8168 | pci_set_drvdata(pdev, priv); | |
8169 | err = pci_request_regions(pdev, DRV_NAME); | |
8170 | if (err) | |
8171 | goto out_pci_disable_device; | |
6440adb5 | 8172 | |
b481de9c ZY |
8173 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
8174 | * PCI Tx retries from interfering with C3 CPU state */ | |
8175 | pci_write_config_byte(pdev, 0x41, 0x00); | |
6440adb5 | 8176 | |
b481de9c ZY |
8177 | priv->hw_base = pci_iomap(pdev, 0, 0); |
8178 | if (!priv->hw_base) { | |
8179 | err = -ENODEV; | |
8180 | goto out_pci_release_regions; | |
8181 | } | |
8182 | ||
8183 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
8184 | (unsigned long long) pci_resource_len(pdev, 0)); | |
8185 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
8186 | ||
8187 | /* Initialize module parameter values here */ | |
8188 | ||
6440adb5 | 8189 | /* Disable radio (SW RF KILL) via parameter when loading driver */ |
bb8c093b | 8190 | if (iwl3945_param_disable) { |
b481de9c ZY |
8191 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
8192 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
8193 | } | |
8194 | ||
8195 | priv->iw_mode = IEEE80211_IF_TYPE_STA; | |
8196 | ||
8197 | pci_id = | |
8198 | (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device; | |
8199 | ||
8200 | switch (pci_id) { | |
8201 | case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */ | |
8202 | case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */ | |
8203 | case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */ | |
8204 | case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */ | |
8205 | priv->is_abg = 0; | |
8206 | break; | |
8207 | ||
8208 | /* | |
8209 | * Rest are assumed ABG SKU -- if this is not the | |
8210 | * case then the card will get the wrong 'Detected' | |
8211 | * line in the kernel log however the code that | |
8212 | * initializes the GEO table will detect no A-band | |
8213 | * channels and remove the is_abg mask. | |
8214 | */ | |
8215 | default: | |
8216 | priv->is_abg = 1; | |
8217 | break; | |
8218 | } | |
8219 | ||
8220 | printk(KERN_INFO DRV_NAME | |
8221 | ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n", | |
8222 | priv->is_abg ? "A" : ""); | |
8223 | ||
8224 | /* Device-specific setup */ | |
bb8c093b | 8225 | if (iwl3945_hw_set_hw_setting(priv)) { |
b481de9c | 8226 | IWL_ERROR("failed to set hw settings\n"); |
b481de9c ZY |
8227 | goto out_iounmap; |
8228 | } | |
8229 | ||
bb8c093b | 8230 | if (iwl3945_param_qos_enable) |
b481de9c ZY |
8231 | priv->qos_data.qos_enable = 1; |
8232 | ||
bb8c093b | 8233 | iwl3945_reset_qos(priv); |
b481de9c ZY |
8234 | |
8235 | priv->qos_data.qos_active = 0; | |
8236 | priv->qos_data.qos_cap.val = 0; | |
b481de9c | 8237 | |
8318d78a | 8238 | iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); |
bb8c093b CH |
8239 | iwl3945_setup_deferred_work(priv); |
8240 | iwl3945_setup_rx_handlers(priv); | |
b481de9c ZY |
8241 | |
8242 | priv->rates_mask = IWL_RATES_MASK; | |
8243 | /* If power management is turned on, default to AC mode */ | |
8244 | priv->power_mode = IWL_POWER_AC; | |
8245 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; | |
8246 | ||
bb8c093b | 8247 | iwl3945_disable_interrupts(priv); |
49df2b33 | 8248 | |
bb8c093b | 8249 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c ZY |
8250 | if (err) { |
8251 | IWL_ERROR("failed to create sysfs device attributes\n"); | |
b481de9c ZY |
8252 | goto out_release_irq; |
8253 | } | |
8254 | ||
5a66926a ZY |
8255 | /* nic init */ |
8256 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
8257 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
8258 | ||
8259 | iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
8260 | err = iwl3945_poll_bit(priv, CSR_GP_CNTRL, | |
8261 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
8262 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
8263 | if (err < 0) { | |
8264 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
8265 | goto out_remove_sysfs; | |
8266 | } | |
8267 | /* Read the EEPROM */ | |
8268 | err = iwl3945_eeprom_init(priv); | |
b481de9c | 8269 | if (err) { |
5a66926a ZY |
8270 | IWL_ERROR("Unable to init EEPROM\n"); |
8271 | goto out_remove_sysfs; | |
b481de9c | 8272 | } |
5a66926a ZY |
8273 | /* MAC Address location in EEPROM same for 3945/4965 */ |
8274 | get_eeprom_mac(priv, priv->mac_addr); | |
8275 | IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); | |
8276 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
b481de9c | 8277 | |
849e0dce RC |
8278 | err = iwl3945_init_channel_map(priv); |
8279 | if (err) { | |
8280 | IWL_ERROR("initializing regulatory failed: %d\n", err); | |
8281 | goto out_remove_sysfs; | |
8282 | } | |
8283 | ||
8284 | err = iwl3945_init_geos(priv); | |
8285 | if (err) { | |
8286 | IWL_ERROR("initializing geos failed: %d\n", err); | |
8287 | goto out_free_channel_map; | |
8288 | } | |
849e0dce | 8289 | |
5a66926a ZY |
8290 | iwl3945_rate_control_register(priv->hw); |
8291 | err = ieee80211_register_hw(priv->hw); | |
8292 | if (err) { | |
8293 | IWL_ERROR("Failed to register network device (error %d)\n", err); | |
849e0dce | 8294 | goto out_free_geos; |
5a66926a | 8295 | } |
b481de9c | 8296 | |
5a66926a ZY |
8297 | priv->hw->conf.beacon_int = 100; |
8298 | priv->mac80211_registered = 1; | |
8299 | pci_save_state(pdev); | |
8300 | pci_disable_device(pdev); | |
b481de9c ZY |
8301 | |
8302 | return 0; | |
8303 | ||
849e0dce RC |
8304 | out_free_geos: |
8305 | iwl3945_free_geos(priv); | |
8306 | out_free_channel_map: | |
8307 | iwl3945_free_channel_map(priv); | |
5a66926a | 8308 | out_remove_sysfs: |
bb8c093b | 8309 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c ZY |
8310 | |
8311 | out_release_irq: | |
b481de9c ZY |
8312 | destroy_workqueue(priv->workqueue); |
8313 | priv->workqueue = NULL; | |
bb8c093b | 8314 | iwl3945_unset_hw_setting(priv); |
b481de9c ZY |
8315 | |
8316 | out_iounmap: | |
8317 | pci_iounmap(pdev, priv->hw_base); | |
8318 | out_pci_release_regions: | |
8319 | pci_release_regions(pdev); | |
8320 | out_pci_disable_device: | |
8321 | pci_disable_device(pdev); | |
8322 | pci_set_drvdata(pdev, NULL); | |
8323 | out_ieee80211_free_hw: | |
8324 | ieee80211_free_hw(priv->hw); | |
8325 | out: | |
8326 | return err; | |
8327 | } | |
8328 | ||
bb8c093b | 8329 | static void iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 8330 | { |
bb8c093b | 8331 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c ZY |
8332 | struct list_head *p, *q; |
8333 | int i; | |
8334 | ||
8335 | if (!priv) | |
8336 | return; | |
8337 | ||
8338 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
8339 | ||
b481de9c | 8340 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 8341 | |
bb8c093b | 8342 | iwl3945_down(priv); |
b481de9c ZY |
8343 | |
8344 | /* Free MAC hash list for ADHOC */ | |
8345 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) { | |
8346 | list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) { | |
8347 | list_del(p); | |
bb8c093b | 8348 | kfree(list_entry(p, struct iwl3945_ibss_seq, list)); |
b481de9c ZY |
8349 | } |
8350 | } | |
8351 | ||
bb8c093b | 8352 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 8353 | |
bb8c093b | 8354 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
8355 | |
8356 | if (priv->rxq.bd) | |
bb8c093b CH |
8357 | iwl3945_rx_queue_free(priv, &priv->rxq); |
8358 | iwl3945_hw_txq_ctx_free(priv); | |
b481de9c | 8359 | |
bb8c093b CH |
8360 | iwl3945_unset_hw_setting(priv); |
8361 | iwl3945_clear_stations_table(priv); | |
b481de9c ZY |
8362 | |
8363 | if (priv->mac80211_registered) { | |
8364 | ieee80211_unregister_hw(priv->hw); | |
bb8c093b | 8365 | iwl3945_rate_control_unregister(priv->hw); |
b481de9c ZY |
8366 | } |
8367 | ||
6ef89d0a MA |
8368 | /*netif_stop_queue(dev); */ |
8369 | flush_workqueue(priv->workqueue); | |
8370 | ||
bb8c093b | 8371 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
8372 | * priv->workqueue... so we can't take down the workqueue |
8373 | * until now... */ | |
8374 | destroy_workqueue(priv->workqueue); | |
8375 | priv->workqueue = NULL; | |
8376 | ||
b481de9c ZY |
8377 | pci_iounmap(pdev, priv->hw_base); |
8378 | pci_release_regions(pdev); | |
8379 | pci_disable_device(pdev); | |
8380 | pci_set_drvdata(pdev, NULL); | |
8381 | ||
849e0dce RC |
8382 | iwl3945_free_channel_map(priv); |
8383 | iwl3945_free_geos(priv); | |
b481de9c ZY |
8384 | |
8385 | if (priv->ibss_beacon) | |
8386 | dev_kfree_skb(priv->ibss_beacon); | |
8387 | ||
8388 | ieee80211_free_hw(priv->hw); | |
8389 | } | |
8390 | ||
8391 | #ifdef CONFIG_PM | |
8392 | ||
bb8c093b | 8393 | static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 8394 | { |
bb8c093b | 8395 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8396 | |
e655b9f0 ZY |
8397 | if (priv->is_open) { |
8398 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
8399 | iwl3945_mac_stop(priv->hw); | |
8400 | priv->is_open = 1; | |
8401 | } | |
b481de9c | 8402 | |
b481de9c ZY |
8403 | pci_set_power_state(pdev, PCI_D3hot); |
8404 | ||
b481de9c ZY |
8405 | return 0; |
8406 | } | |
8407 | ||
bb8c093b | 8408 | static int iwl3945_pci_resume(struct pci_dev *pdev) |
b481de9c | 8409 | { |
bb8c093b | 8410 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8411 | |
b481de9c | 8412 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8413 | |
e655b9f0 ZY |
8414 | if (priv->is_open) |
8415 | iwl3945_mac_start(priv->hw); | |
b481de9c | 8416 | |
e655b9f0 | 8417 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8418 | return 0; |
8419 | } | |
8420 | ||
8421 | #endif /* CONFIG_PM */ | |
8422 | ||
8423 | /***************************************************************************** | |
8424 | * | |
8425 | * driver and module entry point | |
8426 | * | |
8427 | *****************************************************************************/ | |
8428 | ||
bb8c093b | 8429 | static struct pci_driver iwl3945_driver = { |
b481de9c | 8430 | .name = DRV_NAME, |
bb8c093b CH |
8431 | .id_table = iwl3945_hw_card_ids, |
8432 | .probe = iwl3945_pci_probe, | |
8433 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 8434 | #ifdef CONFIG_PM |
bb8c093b CH |
8435 | .suspend = iwl3945_pci_suspend, |
8436 | .resume = iwl3945_pci_resume, | |
b481de9c ZY |
8437 | #endif |
8438 | }; | |
8439 | ||
bb8c093b | 8440 | static int __init iwl3945_init(void) |
b481de9c ZY |
8441 | { |
8442 | ||
8443 | int ret; | |
8444 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8445 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
bb8c093b | 8446 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c ZY |
8447 | if (ret) { |
8448 | IWL_ERROR("Unable to initialize PCI module\n"); | |
8449 | return ret; | |
8450 | } | |
c8b0e6e1 | 8451 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8452 | ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level); |
b481de9c ZY |
8453 | if (ret) { |
8454 | IWL_ERROR("Unable to create driver sysfs file\n"); | |
bb8c093b | 8455 | pci_unregister_driver(&iwl3945_driver); |
b481de9c ZY |
8456 | return ret; |
8457 | } | |
8458 | #endif | |
8459 | ||
8460 | return ret; | |
8461 | } | |
8462 | ||
bb8c093b | 8463 | static void __exit iwl3945_exit(void) |
b481de9c | 8464 | { |
c8b0e6e1 | 8465 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8466 | driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level); |
b481de9c | 8467 | #endif |
bb8c093b | 8468 | pci_unregister_driver(&iwl3945_driver); |
b481de9c ZY |
8469 | } |
8470 | ||
bb8c093b | 8471 | module_param_named(antenna, iwl3945_param_antenna, int, 0444); |
b481de9c | 8472 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
bb8c093b | 8473 | module_param_named(disable, iwl3945_param_disable, int, 0444); |
b481de9c | 8474 | MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])"); |
bb8c093b | 8475 | module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444); |
b481de9c ZY |
8476 | MODULE_PARM_DESC(hwcrypto, |
8477 | "using hardware crypto engine (default 0 [software])\n"); | |
bb8c093b | 8478 | module_param_named(debug, iwl3945_param_debug, int, 0444); |
b481de9c | 8479 | MODULE_PARM_DESC(debug, "debug output mask"); |
bb8c093b | 8480 | module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444); |
b481de9c ZY |
8481 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
8482 | ||
bb8c093b | 8483 | module_param_named(queues_num, iwl3945_param_queues_num, int, 0444); |
b481de9c ZY |
8484 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
8485 | ||
8486 | /* QoS */ | |
bb8c093b | 8487 | module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444); |
b481de9c ZY |
8488 | MODULE_PARM_DESC(qos_enable, "enable all QoS functionality"); |
8489 | ||
bb8c093b CH |
8490 | module_exit(iwl3945_exit); |
8491 | module_init(iwl3945_init); |