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iwlwifi: enhance WPA authenication stability
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
b481de9c
ZY		 49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
c8b0e6e1 52#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 53u32 iwl3945_debug_level;
b481de9c
ZY		 54#endif
55
bb8c093b
CH		 56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
416e1438 58
b481de9c
ZY		 59/******************************************************************************
60 *
61 * module boiler plate
62 *
63 ******************************************************************************/
64
65/* module parameters */
6440adb5
BC		 66static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
67static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
68static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 69static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
BC		 70int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
71static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
72int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 89#define VS "s"
90#else
91#define VS
92#endif
93
80f3e024 94#define IWLWIFI_VERSION "1.1.19k" VD VS
b481de9c
ZY		 95#define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
96#define DRV_VERSION IWLWIFI_VERSION
97
98/* Change firmware file name, using "-" and incrementing number,
99 * *only* when uCode interface or architecture changes so that it
100 * is not compatible with earlier drivers.
101 * This number will also appear in << 8 position of 1st dword of uCode file */
102#define IWL3945_UCODE_API "-1"
103
104MODULE_DESCRIPTION(DRV_DESCRIPTION);
105MODULE_VERSION(DRV_VERSION);
106MODULE_AUTHOR(DRV_COPYRIGHT);
107MODULE_LICENSE("GPL");
108
416e1438 109static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
b481de9c
ZY		 110{
111 u16 fc = le16_to_cpu(hdr->frame_control);
112 int hdr_len = ieee80211_get_hdrlen(fc);
113
114 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
115 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
116 return NULL;
117}
118
bb8c093b
CH		 119static const struct ieee80211_hw_mode *iwl3945_get_hw_mode(
120 struct iwl3945_priv *priv, int mode)
b481de9c
ZY		 121{
122 int i;
123
124 for (i = 0; i < 3; i++)
125 if (priv->modes[i].mode == mode)
126 return &priv->modes[i];
127
128 return NULL;
129}
130
bb8c093b 131static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 132{
133 /* Single white space is for Linksys APs */
134 if (essid_len == 1 && essid[0] == ' ')
135 return 1;
136
137 /* Otherwise, if the entire essid is 0, we assume it is hidden */
138 while (essid_len) {
139 essid_len--;
140 if (essid[essid_len] != '\0')
141 return 0;
142 }
143
144 return 1;
145}
146
bb8c093b 147static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 148{
149 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
150 const char *s = essid;
151 char *d = escaped;
152
bb8c093b 153 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 154 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
155 return escaped;
156 }
157
158 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
159 while (essid_len--) {
160 if (*s == '\0') {
161 *d++ = '\\';
162 *d++ = '0';
163 s++;
164 } else
165 *d++ = *s++;
166 }
167 *d = '\0';
168 return escaped;
169}
170
bb8c093b 171static void iwl3945_print_hex_dump(int level, void *p, u32 len)
b481de9c 172{
c8b0e6e1 173#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 174 if (!(iwl3945_debug_level & level))
b481de9c
ZY		 175 return;
176
177 print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
178 p, len, 1);
179#endif
180}
181
182/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
183 * DMA services
184 *
185 * Theory of operation
186 *
6440adb5
BC		 187 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
188 * of buffer descriptors, each of which points to one or more data buffers for
189 * the device to read from or fill. Driver and device exchange status of each
190 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
191 * entries in each circular buffer, to protect against confusing empty and full
192 * queue states.
193 *
194 * The device reads or writes the data in the queues via the device's several
195 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 196 *
197 * For Tx queue, there are low mark and high mark limits. If, after queuing
198 * the packet for Tx, free space become < low mark, Tx queue stopped. When
199 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
200 * Tx queue resumed.
201 *
6440adb5
BC		 202 * The 3945 operates with six queues: One receive queue, one transmit queue
203 * (#4) for sending commands to the device firmware, and four transmit queues
204 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 205 ***************************************************/
206
bb8c093b 207static int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 208{
fc4b6853 209 int s = q->read_ptr - q->write_ptr;
b481de9c 210
fc4b6853 211 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 212 s -= q->n_bd;
213
214 if (s <= 0)
215 s += q->n_window;
216 /* keep some reserve to not confuse empty and full situations */
217 s -= 2;
218 if (s < 0)
219 s = 0;
220 return s;
221}
222
6440adb5
BC		 223/**
224 * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
225 * @index -- current index
226 * @n_bd -- total number of entries in queue (must be power of 2)
227 */
bb8c093b 228static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
b481de9c
ZY		 229{
230 return ++index & (n_bd - 1);
231}
232
6440adb5
BC		 233/**
234 * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
235 * @index -- current index
236 * @n_bd -- total number of entries in queue (must be power of 2)
237 */
bb8c093b 238static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 239{
240 return --index & (n_bd - 1);
241}
242
bb8c093b 243static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 244{
fc4b6853
TW		 245 return q->write_ptr > q->read_ptr ?
246 (i >= q->read_ptr && i < q->write_ptr) :
247 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 248}
249
bb8c093b 250static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 251{
6440adb5 252 /* This is for scan command, the big buffer at end of command array */
b481de9c 253 if (is_huge)
6440adb5 254 return q->n_window; /* must be power of 2 */
b481de9c 255
6440adb5 256 /* Otherwise, use normal size buffers */
b481de9c
ZY		 257 return index & (q->n_window - 1);
258}
259
6440adb5
BC		 260/**
261 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
262 */
bb8c093b 263static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 264 int count, int slots_num, u32 id)
265{
266 q->n_bd = count;
267 q->n_window = slots_num;
268 q->id = id;
269
bb8c093b
CH		 270 /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
271 * and iwl3945_queue_dec_wrap are broken. */
b481de9c
ZY		 272 BUG_ON(!is_power_of_2(count));
273
274 /* slots_num must be power-of-two size, otherwise
275 * get_cmd_index is broken. */
276 BUG_ON(!is_power_of_2(slots_num));
277
278 q->low_mark = q->n_window / 4;
279 if (q->low_mark < 4)
280 q->low_mark = 4;
281
282 q->high_mark = q->n_window / 8;
283 if (q->high_mark < 2)
284 q->high_mark = 2;
285
fc4b6853 286 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 287
288 return 0;
289}
290
6440adb5
BC		 291/**
292 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
293 */
bb8c093b
CH		 294static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
295 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 296{
297 struct pci_dev *dev = priv->pci_dev;
298
6440adb5
BC		 299 /* Driver private data, only for Tx (not command) queues,
300 * not shared with device. */
b481de9c
ZY		 301 if (id != IWL_CMD_QUEUE_NUM) {
302 txq->txb = kmalloc(sizeof(txq->txb[0]) *
303 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
304 if (!txq->txb) {
01ebd063 305 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 306 "structures failed\n");
307 goto error;
308 }
309 } else
310 txq->txb = NULL;
311
6440adb5
BC		 312 /* Circular buffer of transmit frame descriptors (TFDs),
313 * shared with device */
b481de9c
ZY		 314 txq->bd = pci_alloc_consistent(dev,
315 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
316 &txq->q.dma_addr);
317
318 if (!txq->bd) {
319 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
320 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
321 goto error;
322 }
323 txq->q.id = id;
324
325 return 0;
326
327 error:
328 if (txq->txb) {
329 kfree(txq->txb);
330 txq->txb = NULL;
331 }
332
333 return -ENOMEM;
334}
335
6440adb5
BC		 336/**
337 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
338 */
bb8c093b
CH		 339int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
340 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 341{
342 struct pci_dev *dev = priv->pci_dev;
343 int len;
344 int rc = 0;
345
6440adb5
BC		 346 /*
347 * Alloc buffer array for commands (Tx or other types of commands).
348 * For the command queue (#4), allocate command space + one big
349 * command for scan, since scan command is very huge; the system will
350 * not have two scans at the same time, so only one is needed.
351 * For data Tx queues (all other queues), no super-size command
352 * space is needed.
353 */
bb8c093b 354 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 355 if (txq_id == IWL_CMD_QUEUE_NUM)
356 len += IWL_MAX_SCAN_SIZE;
357 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
358 if (!txq->cmd)
359 return -ENOMEM;
360
6440adb5 361 /* Alloc driver data array and TFD circular buffer */
bb8c093b 362 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 363 if (rc) {
364 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
365
366 return -ENOMEM;
367 }
368 txq->need_update = 0;
369
370 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
bb8c093b 371 * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
b481de9c 372 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
BC		 373
374 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 375 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 376
6440adb5 377 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 378 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 379
380 return 0;
381}
382
383/**
bb8c093b 384 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 385 * @txq: Transmit queue to deallocate.
386 *
387 * Empty queue by removing and destroying all BD's.
6440adb5
BC		 388 * Free all buffers.
389 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 390 */
bb8c093b 391void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 392{
bb8c093b 393 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 394 struct pci_dev *dev = priv->pci_dev;
395 int len;
396
397 if (q->n_bd == 0)
398 return;
399
400 /* first, empty all BD's */
fc4b6853 401 for (; q->write_ptr != q->read_ptr;
bb8c093b
CH		 402 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
403 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 404
bb8c093b 405 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 406 if (q->id == IWL_CMD_QUEUE_NUM)
407 len += IWL_MAX_SCAN_SIZE;
408
6440adb5 409 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 410 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
411
6440adb5 412 /* De-alloc circular buffer of TFDs */
b481de9c 413 if (txq->q.n_bd)
bb8c093b 414 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 415 txq->q.n_bd, txq->bd, txq->q.dma_addr);
416
6440adb5 417 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 418 if (txq->txb) {
419 kfree(txq->txb);
420 txq->txb = NULL;
421 }
422
6440adb5 423 /* 0-fill queue descriptor structure */
b481de9c
ZY		 424 memset(txq, 0, sizeof(*txq));
425}
426
bb8c093b 427const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 428
429/*************** STATION TABLE MANAGEMENT ****
9fbab516 430 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 431 * the functionality provided here
432 */
433
434/**************************************************************/
01ebd063 435#if 0 /* temporary disable till we add real remove station */
6440adb5
BC		 436/**
437 * iwl3945_remove_station - Remove driver's knowledge of station.
438 *
439 * NOTE: This does not remove station from device's station table.
440 */
bb8c093b 441static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 442{
443 int index = IWL_INVALID_STATION;
444 int i;
445 unsigned long flags;
446
447 spin_lock_irqsave(&priv->sta_lock, flags);
448
449 if (is_ap)
450 index = IWL_AP_ID;
451 else if (is_broadcast_ether_addr(addr))
452 index = priv->hw_setting.bcast_sta_id;
453 else
454 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
455 if (priv->stations[i].used &&
456 !compare_ether_addr(priv->stations[i].sta.sta.addr,
457 addr)) {
458 index = i;
459 break;
460 }
461
462 if (unlikely(index == IWL_INVALID_STATION))
463 goto out;
464
465 if (priv->stations[index].used) {
466 priv->stations[index].used = 0;
467 priv->num_stations--;
468 }
469
470 BUG_ON(priv->num_stations < 0);
471
472out:
473 spin_unlock_irqrestore(&priv->sta_lock, flags);
474 return 0;
475}
556f8db7 476#endif
6440adb5
BC		 477
478/**
479 * iwl3945_clear_stations_table - Clear the driver's station table
480 *
481 * NOTE: This does not clear or otherwise alter the device's station table.
482 */
bb8c093b 483static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 484{
485 unsigned long flags;
486
487 spin_lock_irqsave(&priv->sta_lock, flags);
488
489 priv->num_stations = 0;
490 memset(priv->stations, 0, sizeof(priv->stations));
491
492 spin_unlock_irqrestore(&priv->sta_lock, flags);
493}
494
6440adb5
BC		 495/**
496 * iwl3945_add_station - Add station to station tables in driver and device
497 */
bb8c093b 498u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 499{
500 int i;
501 int index = IWL_INVALID_STATION;
bb8c093b 502 struct iwl3945_station_entry *station;
b481de9c 503 unsigned long flags_spin;
0795af57 504 DECLARE_MAC_BUF(mac);
c14c521e 505 u8 rate;
b481de9c
ZY		 506
507 spin_lock_irqsave(&priv->sta_lock, flags_spin);
508 if (is_ap)
509 index = IWL_AP_ID;
510 else if (is_broadcast_ether_addr(addr))
511 index = priv->hw_setting.bcast_sta_id;
512 else
513 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
514 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
515 addr)) {
516 index = i;
517 break;
518 }
519
520 if (!priv->stations[i].used &&
521 index == IWL_INVALID_STATION)
522 index = i;
523 }
524
01ebd063 525 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 526 since they have different meaning */
527 if (unlikely(index == IWL_INVALID_STATION)) {
528 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
529 return index;
530 }
531
532 if (priv->stations[index].used &&
533 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
534 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
535 return index;
536 }
537
0795af57 538 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 539 station = &priv->stations[index];
540 station->used = 1;
541 priv->num_stations++;
542
6440adb5 543 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 544 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 545 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
546 station->sta.mode = 0;
547 station->sta.sta.sta_id = index;
548 station->sta.station_flags = 0;
549
69946333
TW		 550 if (priv->phymode == MODE_IEEE80211A)
551 rate = IWL_RATE_6M_PLCP;
552 else
553 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 554
555 /* Turn on both antennas for the station... */
556 station->sta.rate_n_flags =
bb8c093b 557 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 558 station->current_rate.rate_n_flags =
559 le16_to_cpu(station->sta.rate_n_flags);
560
b481de9c 561 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
BC		 562
563 /* Add station to device's station table */
bb8c093b 564 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 565 return index;
566
567}
568
569/*************** DRIVER STATUS FUNCTIONS *****/
570
bb8c093b 571static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 572{
573 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
574 * set but EXIT_PENDING is not */
575 return test_bit(STATUS_READY, &priv->status) &&
576 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
577 !test_bit(STATUS_EXIT_PENDING, &priv->status);
578}
579
bb8c093b 580static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 581{
582 return test_bit(STATUS_ALIVE, &priv->status);
583}
584
bb8c093b 585static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 586{
587 return test_bit(STATUS_INIT, &priv->status);
588}
589
bb8c093b 590static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c
ZY		 591{
592 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
593 test_bit(STATUS_RF_KILL_SW, &priv->status);
594}
595
bb8c093b 596static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 597{
598
bb8c093b 599 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 600 return 0;
601
bb8c093b 602 return iwl3945_is_ready(priv);
b481de9c
ZY		 603}
604
605/*************** HOST COMMAND QUEUE FUNCTIONS *****/
606
607#define IWL_CMD(x) case x : return #x
608
609static const char *get_cmd_string(u8 cmd)
610{
611 switch (cmd) {
612 IWL_CMD(REPLY_ALIVE);
613 IWL_CMD(REPLY_ERROR);
614 IWL_CMD(REPLY_RXON);
615 IWL_CMD(REPLY_RXON_ASSOC);
616 IWL_CMD(REPLY_QOS_PARAM);
617 IWL_CMD(REPLY_RXON_TIMING);
618 IWL_CMD(REPLY_ADD_STA);
619 IWL_CMD(REPLY_REMOVE_STA);
620 IWL_CMD(REPLY_REMOVE_ALL_STA);
621 IWL_CMD(REPLY_3945_RX);
622 IWL_CMD(REPLY_TX);
623 IWL_CMD(REPLY_RATE_SCALE);
624 IWL_CMD(REPLY_LEDS_CMD);
625 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
626 IWL_CMD(RADAR_NOTIFICATION);
627 IWL_CMD(REPLY_QUIET_CMD);
628 IWL_CMD(REPLY_CHANNEL_SWITCH);
629 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
630 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
631 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
632 IWL_CMD(POWER_TABLE_CMD);
633 IWL_CMD(PM_SLEEP_NOTIFICATION);
634 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
635 IWL_CMD(REPLY_SCAN_CMD);
636 IWL_CMD(REPLY_SCAN_ABORT_CMD);
637 IWL_CMD(SCAN_START_NOTIFICATION);
638 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
639 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
640 IWL_CMD(BEACON_NOTIFICATION);
641 IWL_CMD(REPLY_TX_BEACON);
642 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
643 IWL_CMD(QUIET_NOTIFICATION);
644 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
645 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
646 IWL_CMD(REPLY_BT_CONFIG);
647 IWL_CMD(REPLY_STATISTICS_CMD);
648 IWL_CMD(STATISTICS_NOTIFICATION);
649 IWL_CMD(REPLY_CARD_STATE_CMD);
650 IWL_CMD(CARD_STATE_NOTIFICATION);
651 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
652 default:
653 return "UNKNOWN";
654
655 }
656}
657
658#define HOST_COMPLETE_TIMEOUT (HZ / 2)
659
660/**
bb8c093b 661 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 662 * @priv: device private data point
663 * @cmd: a point to the ucode command structure
664 *
665 * The function returns < 0 values to indicate the operation is
666 * failed. On success, it turns the index (> 0) of command in the
667 * command queue.
668 */
bb8c093b 669static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 670{
bb8c093b
CH		 671 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
672 struct iwl3945_queue *q = &txq->q;
673 struct iwl3945_tfd_frame *tfd;
b481de9c 674 u32 *control_flags;
bb8c093b 675 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 676 u32 idx;
677 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
678 dma_addr_t phys_addr;
679 int pad;
680 u16 count;
681 int ret;
682 unsigned long flags;
683
684 /* If any of the command structures end up being larger than
685 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
686 * we will need to increase the size of the TFD entries */
687 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
688 !(cmd->meta.flags & CMD_SIZE_HUGE));
689
bb8c093b 690 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 691 IWL_ERROR("No space for Tx\n");
692 return -ENOSPC;
693 }
694
695 spin_lock_irqsave(&priv->hcmd_lock, flags);
696
fc4b6853 697 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 698 memset(tfd, 0, sizeof(*tfd));
699
700 control_flags = (u32 *) tfd;
701
fc4b6853 702 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 703 out_cmd = &txq->cmd[idx];
704
705 out_cmd->hdr.cmd = cmd->id;
706 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
707 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
708
709 /* At this point, the out_cmd now has all of the incoming cmd
710 * information */
711
712 out_cmd->hdr.flags = 0;
713 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 714 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 715 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
716 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
717
718 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 719 offsetof(struct iwl3945_cmd, hdr);
720 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 721
722 pad = U32_PAD(cmd->len);
723 count = TFD_CTL_COUNT_GET(*control_flags);
724 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
725
726 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
727 "%d bytes at %d[%d]:%d\n",
728 get_cmd_string(out_cmd->hdr.cmd),
729 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 730 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 731
732 txq->need_update = 1;
6440adb5
BC		 733
734 /* Increment and update queue's write index */
bb8c093b
CH		 735 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
736 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 737
738 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
739 return ret ? ret : idx;
740}
741
bb8c093b 742static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 743{
744 int ret;
745
746 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
747
748 /* An asynchronous command can not expect an SKB to be set. */
749 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
750
751 /* An asynchronous command MUST have a callback. */
752 BUG_ON(!cmd->meta.u.callback);
753
754 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
755 return -EBUSY;
756
bb8c093b 757 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 758 if (ret < 0) {
bb8c093b 759 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 760 get_cmd_string(cmd->id), ret);
761 return ret;
762 }
763 return 0;
764}
765
bb8c093b 766static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 767{
768 int cmd_idx;
769 int ret;
770 static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
771
772 BUG_ON(cmd->meta.flags & CMD_ASYNC);
773
774 /* A synchronous command can not have a callback set. */
775 BUG_ON(cmd->meta.u.callback != NULL);
776
777 if (atomic_xchg(&entry, 1)) {
778 IWL_ERROR("Error sending %s: Already sending a host command\n",
779 get_cmd_string(cmd->id));
780 return -EBUSY;
781 }
782
783 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
784
785 if (cmd->meta.flags & CMD_WANT_SKB)
786 cmd->meta.source = &cmd->meta;
787
bb8c093b 788 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 789 if (cmd_idx < 0) {
790 ret = cmd_idx;
bb8c093b 791 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 792 get_cmd_string(cmd->id), ret);
793 goto out;
794 }
795
796 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
797 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
798 HOST_COMPLETE_TIMEOUT);
799 if (!ret) {
800 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
801 IWL_ERROR("Error sending %s: time out after %dms.\n",
802 get_cmd_string(cmd->id),
803 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
804
805 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
806 ret = -ETIMEDOUT;
807 goto cancel;
808 }
809 }
810
811 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
812 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
813 get_cmd_string(cmd->id));
814 ret = -ECANCELED;
815 goto fail;
816 }
817 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
818 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
819 get_cmd_string(cmd->id));
820 ret = -EIO;
821 goto fail;
822 }
823 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
824 IWL_ERROR("Error: Response NULL in '%s'\n",
825 get_cmd_string(cmd->id));
826 ret = -EIO;
827 goto out;
828 }
829
830 ret = 0;
831 goto out;
832
833cancel:
834 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 835 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 836
837 /* Cancel the CMD_WANT_SKB flag for the cmd in the
838 * TX cmd queue. Otherwise in case the cmd comes
839 * in later, it will possibly set an invalid
840 * address (cmd->meta.source). */
841 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
842 qcmd->meta.flags &= ~CMD_WANT_SKB;
843 }
844fail:
845 if (cmd->meta.u.skb) {
846 dev_kfree_skb_any(cmd->meta.u.skb);
847 cmd->meta.u.skb = NULL;
848 }
849out:
850 atomic_set(&entry, 0);
851 return ret;
852}
853
bb8c093b 854int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 855{
b481de9c 856 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 857 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 858
bb8c093b 859 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 860}
861
bb8c093b 862int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 863{
bb8c093b 864 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 865 .id = id,
866 .len = len,
867 .data = data,
868 };
869
bb8c093b 870 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 871}
872
bb8c093b 873static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 874{
bb8c093b 875 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 876 .id = id,
877 .len = sizeof(val),
878 .data = &val,
879 };
880
bb8c093b 881 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 882}
883
bb8c093b 884int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 885{
bb8c093b 886 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 887}
888
b481de9c 889/**
bb8c093b 890 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
b481de9c
ZY		 891 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
892 * @channel: Any channel valid for the requested phymode
893
894 * In addition to setting the staging RXON, priv->phymode is also set.
895 *
896 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
897 * in the staging RXON flag structure based on the phymode
898 */
bb8c093b 899static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, u8 phymode, u16 channel)
b481de9c 900{
bb8c093b 901 if (!iwl3945_get_channel_info(priv, phymode, channel)) {
b481de9c
ZY		 902 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
903 channel, phymode);
904 return -EINVAL;
905 }
906
907 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
908 (priv->phymode == phymode))
909 return 0;
910
911 priv->staging_rxon.channel = cpu_to_le16(channel);
912 if (phymode == MODE_IEEE80211A)
913 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
914 else
915 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
916
917 priv->phymode = phymode;
918
919 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
920
921 return 0;
922}
923
924/**
bb8c093b 925 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 926 *
927 * NOTE: This is really only useful during development and can eventually
928 * be #ifdef'd out once the driver is stable and folks aren't actively
929 * making changes
930 */
bb8c093b 931static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 932{
933 int error = 0;
934 int counter = 1;
935
936 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
937 error |= le32_to_cpu(rxon->flags &
938 (RXON_FLG_TGJ_NARROW_BAND_MSK |
939 RXON_FLG_RADAR_DETECT_MSK));
940 if (error)
941 IWL_WARNING("check 24G fields %d | %d\n",
942 counter++, error);
943 } else {
944 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
945 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
946 if (error)
947 IWL_WARNING("check 52 fields %d | %d\n",
948 counter++, error);
949 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
950 if (error)
951 IWL_WARNING("check 52 CCK %d | %d\n",
952 counter++, error);
953 }
954 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
955 if (error)
956 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
957
958 /* make sure basic rates 6Mbps and 1Mbps are supported */
959 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
960 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
961 if (error)
962 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
963
964 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
965 if (error)
966 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
967
968 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
969 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
970 if (error)
971 IWL_WARNING("check CCK and short slot %d | %d\n",
972 counter++, error);
973
974 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
975 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
976 if (error)
977 IWL_WARNING("check CCK & auto detect %d | %d\n",
978 counter++, error);
979
980 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
981 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
982 if (error)
983 IWL_WARNING("check TGG and auto detect %d | %d\n",
984 counter++, error);
985
986 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
987 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
988 RXON_FLG_ANT_A_MSK)) == 0);
989 if (error)
990 IWL_WARNING("check antenna %d %d\n", counter++, error);
991
992 if (error)
993 IWL_WARNING("Tuning to channel %d\n",
994 le16_to_cpu(rxon->channel));
995
996 if (error) {
bb8c093b 997 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 998 return -1;
999 }
1000 return 0;
1001}
1002
1003/**
9fbab516 1004 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 1005 * @priv: staging_rxon is compared to active_rxon
b481de9c 1006 *
9fbab516
BC		 1007 * If the RXON structure is changing enough to require a new tune,
1008 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
1009 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 1010 */
bb8c093b 1011static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 1012{
1013
1014 /* These items are only settable from the full RXON command */
1015 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
1016 compare_ether_addr(priv->staging_rxon.bssid_addr,
1017 priv->active_rxon.bssid_addr) ||
1018 compare_ether_addr(priv->staging_rxon.node_addr,
1019 priv->active_rxon.node_addr) ||
1020 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
1021 priv->active_rxon.wlap_bssid_addr) ||
1022 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
1023 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
1024 (priv->staging_rxon.air_propagation !=
1025 priv->active_rxon.air_propagation) ||
1026 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
1027 return 1;
1028
1029 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
1030 * be updated with the RXON_ASSOC command -- however only some
1031 * flag transitions are allowed using RXON_ASSOC */
1032
1033 /* Check if we are not switching bands */
1034 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1035 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1036 return 1;
1037
1038 /* Check if we are switching association toggle */
1039 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1040 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1041 return 1;
1042
1043 return 0;
1044}
1045
bb8c093b 1046static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1047{
1048 int rc = 0;
bb8c093b
CH		 1049 struct iwl3945_rx_packet *res = NULL;
1050 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1051 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1052 .id = REPLY_RXON_ASSOC,
1053 .len = sizeof(rxon_assoc),
1054 .meta.flags = CMD_WANT_SKB,
1055 .data = &rxon_assoc,
1056 };
bb8c093b
CH		 1057 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1058 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1059
1060 if ((rxon1->flags == rxon2->flags) &&
1061 (rxon1->filter_flags == rxon2->filter_flags) &&
1062 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1063 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1064 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1065 return 0;
1066 }
1067
1068 rxon_assoc.flags = priv->staging_rxon.flags;
1069 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1070 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1071 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1072 rxon_assoc.reserved = 0;
1073
bb8c093b 1074 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1075 if (rc)
1076 return rc;
1077
bb8c093b 1078 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1079 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1080 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1081 rc = -EIO;
1082 }
1083
1084 priv->alloc_rxb_skb--;
1085 dev_kfree_skb_any(cmd.meta.u.skb);
1086
1087 return rc;
1088}
1089
1090/**
bb8c093b 1091 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1092 *
01ebd063 1093 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1094 * the active_rxon structure is updated with the new data. This
1095 * function correctly transitions out of the RXON_ASSOC_MSK state if
1096 * a HW tune is required based on the RXON structure changes.
1097 */
bb8c093b 1098static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1099{
1100 /* cast away the const for active_rxon in this function */
bb8c093b 1101 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1102 int rc = 0;
0795af57 1103 DECLARE_MAC_BUF(mac);
b481de9c 1104
bb8c093b 1105 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1106 return -1;
1107
1108 /* always get timestamp with Rx frame */
1109 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1110
1111 /* select antenna */
1112 priv->staging_rxon.flags &=
1113 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1114 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1115
bb8c093b 1116 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1117 if (rc) {
1118 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1119 return -EINVAL;
1120 }
1121
1122 /* If we don't need to send a full RXON, we can use
bb8c093b 1123 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1124 * and other flags for the current radio configuration. */
bb8c093b
CH		 1125 if (!iwl3945_full_rxon_required(priv)) {
1126 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1127 if (rc) {
1128 IWL_ERROR("Error setting RXON_ASSOC "
1129 "configuration (%d).\n", rc);
1130 return rc;
1131 }
1132
1133 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1134
1135 return 0;
1136 }
1137
1138 /* If we are currently associated and the new config requires
1139 * an RXON_ASSOC and the new config wants the associated mask enabled,
1140 * we must clear the associated from the active configuration
1141 * before we apply the new config */
bb8c093b 1142 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1143 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1144 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1145 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1146
bb8c093b
CH		 1147 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1148 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1149 &priv->active_rxon);
1150
1151 /* If the mask clearing failed then we set
1152 * active_rxon back to what it was previously */
1153 if (rc) {
1154 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1155 IWL_ERROR("Error clearing ASSOC_MSK on current "
1156 "configuration (%d).\n", rc);
1157 return rc;
1158 }
b481de9c
ZY		 1159 }
1160
1161 IWL_DEBUG_INFO("Sending RXON\n"
1162 "* with%s RXON_FILTER_ASSOC_MSK\n"
1163 "* channel = %d\n"
0795af57 1164 "* bssid = %s\n",
b481de9c
ZY		 1165 ((priv->staging_rxon.filter_flags &
1166 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1167 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1168 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1169
1170 /* Apply the new configuration */
bb8c093b
CH		 1171 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1172 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1173 if (rc) {
1174 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1175 return rc;
1176 }
1177
1178 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1179
bb8c093b 1180 iwl3945_clear_stations_table(priv);
556f8db7 1181
b481de9c
ZY		 1182 /* If we issue a new RXON command which required a tune then we must
1183 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1184 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1185 if (rc) {
1186 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1187 return rc;
1188 }
1189
1190 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1191 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1192 IWL_INVALID_STATION) {
1193 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1194 return -EIO;
1195 }
1196
1197 /* If we have set the ASSOC_MSK and we are in BSS mode then
1198 * add the IWL_AP_ID to the station rate table */
bb8c093b 1199 if (iwl3945_is_associated(priv) &&
b481de9c 1200 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1201 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1202 == IWL_INVALID_STATION) {
1203 IWL_ERROR("Error adding AP address for transmit.\n");
1204 return -EIO;
1205 }
1206
1207 /* Init the hardware's rate fallback order based on the
1208 * phymode */
1209 rc = iwl3945_init_hw_rate_table(priv);
1210 if (rc) {
1211 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1212 return -EIO;
1213 }
1214
1215 return 0;
1216}
1217
bb8c093b 1218static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1219{
bb8c093b 1220 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1221 .flags = 3,
1222 .lead_time = 0xAA,
1223 .max_kill = 1,
1224 .kill_ack_mask = 0,
1225 .kill_cts_mask = 0,
1226 };
1227
bb8c093b
CH		 1228 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1229 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1230}
1231
bb8c093b 1232static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1233{
1234 int rc = 0;
bb8c093b
CH		 1235 struct iwl3945_rx_packet *res;
1236 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1237 .id = REPLY_SCAN_ABORT_CMD,
1238 .meta.flags = CMD_WANT_SKB,
1239 };
1240
1241 /* If there isn't a scan actively going on in the hardware
1242 * then we are in between scan bands and not actually
1243 * actively scanning, so don't send the abort command */
1244 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1245 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1246 return 0;
1247 }
1248
bb8c093b 1249 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1250 if (rc) {
1251 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1252 return rc;
1253 }
1254
bb8c093b 1255 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1256 if (res->u.status != CAN_ABORT_STATUS) {
1257 /* The scan abort will return 1 for success or
1258 * 2 for "failure". A failure condition can be
1259 * due to simply not being in an active scan which
1260 * can occur if we send the scan abort before we
1261 * the microcode has notified us that a scan is
1262 * completed. */
1263 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1264 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1265 clear_bit(STATUS_SCAN_HW, &priv->status);
1266 }
1267
1268 dev_kfree_skb_any(cmd.meta.u.skb);
1269
1270 return rc;
1271}
1272
bb8c093b
CH		 1273static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1274 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1275 struct sk_buff *skb)
1276{
1277 return 1;
1278}
1279
1280/*
1281 * CARD_STATE_CMD
1282 *
9fbab516 1283 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1284 *
1285 * When in the 'enable' state the card operates as normal.
1286 * When in the 'disable' state, the card enters into a low power mode.
1287 * When in the 'halt' state, the card is shut down and must be fully
1288 * restarted to come back on.
1289 */
bb8c093b 1290static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1291{
bb8c093b 1292 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1293 .id = REPLY_CARD_STATE_CMD,
1294 .len = sizeof(u32),
1295 .data = &flags,
1296 .meta.flags = meta_flag,
1297 };
1298
1299 if (meta_flag & CMD_ASYNC)
bb8c093b 1300 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1301
bb8c093b 1302 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1303}
1304
bb8c093b
CH		 1305static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1306 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1307{
bb8c093b 1308 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1309
1310 if (!skb) {
1311 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1312 return 1;
1313 }
1314
bb8c093b 1315 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1316 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1317 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1318 res->hdr.flags);
1319 return 1;
1320 }
1321
1322 switch (res->u.add_sta.status) {
1323 case ADD_STA_SUCCESS_MSK:
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 /* We didn't cache the SKB; let the caller free it */
1330 return 1;
1331}
1332
bb8c093b
CH		 1333int iwl3945_send_add_station(struct iwl3945_priv *priv,
1334 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1335{
bb8c093b 1336 struct iwl3945_rx_packet *res = NULL;
b481de9c 1337 int rc = 0;
bb8c093b 1338 struct iwl3945_host_cmd cmd = {
b481de9c 1339 .id = REPLY_ADD_STA,
bb8c093b 1340 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1341 .meta.flags = flags,
1342 .data = sta,
1343 };
1344
1345 if (flags & CMD_ASYNC)
bb8c093b 1346 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1347 else
1348 cmd.meta.flags |= CMD_WANT_SKB;
1349
bb8c093b 1350 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1351
1352 if (rc || (flags & CMD_ASYNC))
1353 return rc;
1354
bb8c093b 1355 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1356 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1357 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1358 res->hdr.flags);
1359 rc = -EIO;
1360 }
1361
1362 if (rc == 0) {
1363 switch (res->u.add_sta.status) {
1364 case ADD_STA_SUCCESS_MSK:
1365 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1366 break;
1367 default:
1368 rc = -EIO;
1369 IWL_WARNING("REPLY_ADD_STA failed\n");
1370 break;
1371 }
1372 }
1373
1374 priv->alloc_rxb_skb--;
1375 dev_kfree_skb_any(cmd.meta.u.skb);
1376
1377 return rc;
1378}
1379
bb8c093b 1380static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1381 struct ieee80211_key_conf *keyconf,
1382 u8 sta_id)
1383{
1384 unsigned long flags;
1385 __le16 key_flags = 0;
1386
1387 switch (keyconf->alg) {
1388 case ALG_CCMP:
1389 key_flags |= STA_KEY_FLG_CCMP;
1390 key_flags |= cpu_to_le16(
1391 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1392 key_flags &= ~STA_KEY_FLG_INVALID;
1393 break;
1394 case ALG_TKIP:
1395 case ALG_WEP:
b481de9c
ZY		 1396 default:
1397 return -EINVAL;
1398 }
1399 spin_lock_irqsave(&priv->sta_lock, flags);
1400 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1401 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1402 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1403 keyconf->keylen);
1404
1405 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1406 keyconf->keylen);
1407 priv->stations[sta_id].sta.key.key_flags = key_flags;
1408 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1409 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1410
1411 spin_unlock_irqrestore(&priv->sta_lock, flags);
1412
1413 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1414 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1415 return 0;
1416}
1417
bb8c093b 1418static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1419{
1420 unsigned long flags;
1421
1422 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1423 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1424 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1425 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1426 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1427 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1428 spin_unlock_irqrestore(&priv->sta_lock, flags);
1429
1430 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1431 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1432 return 0;
1433}
1434
bb8c093b 1435static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1436{
1437 struct list_head *element;
1438
1439 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1440 priv->frames_count);
1441
1442 while (!list_empty(&priv->free_frames)) {
1443 element = priv->free_frames.next;
1444 list_del(element);
bb8c093b 1445 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1446 priv->frames_count--;
1447 }
1448
1449 if (priv->frames_count) {
1450 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1451 priv->frames_count);
1452 priv->frames_count = 0;
1453 }
1454}
1455
bb8c093b 1456static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1457{
bb8c093b 1458 struct iwl3945_frame *frame;
b481de9c
ZY		 1459 struct list_head *element;
1460 if (list_empty(&priv->free_frames)) {
1461 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1462 if (!frame) {
1463 IWL_ERROR("Could not allocate frame!\n");
1464 return NULL;
1465 }
1466
1467 priv->frames_count++;
1468 return frame;
1469 }
1470
1471 element = priv->free_frames.next;
1472 list_del(element);
bb8c093b 1473 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1474}
1475
bb8c093b 1476static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1477{
1478 memset(frame, 0, sizeof(*frame));
1479 list_add(&frame->list, &priv->free_frames);
1480}
1481
bb8c093b 1482unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1483 struct ieee80211_hdr *hdr,
1484 const u8 *dest, int left)
1485{
1486
bb8c093b 1487 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1488 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1489 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1490 return 0;
1491
1492 if (priv->ibss_beacon->len > left)
1493 return 0;
1494
1495 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1496
1497 return priv->ibss_beacon->len;
1498}
1499
bb8c093b 1500static int iwl3945_rate_index_from_plcp(int plcp)
b481de9c
ZY		 1501{
1502 int i = 0;
1503
1504 for (i = 0; i < IWL_RATE_COUNT; i++)
bb8c093b 1505 if (iwl3945_rates[i].plcp == plcp)
b481de9c
ZY		 1506 return i;
1507 return -1;
1508}
1509
bb8c093b 1510static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1511{
1512 u8 i;
1513
1514 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1515 i = iwl3945_rates[i].next_ieee) {
b481de9c 1516 if (rate_mask & (1 << i))
bb8c093b 1517 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1518 }
1519
1520 return IWL_RATE_INVALID;
1521}
1522
bb8c093b 1523static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1524{
bb8c093b 1525 struct iwl3945_frame *frame;
b481de9c
ZY		 1526 unsigned int frame_size;
1527 int rc;
1528 u8 rate;
1529
bb8c093b 1530 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1531
1532 if (!frame) {
1533 IWL_ERROR("Could not obtain free frame buffer for beacon "
1534 "command.\n");
1535 return -ENOMEM;
1536 }
1537
1538 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1539 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1540 0xFF0);
1541 if (rate == IWL_INVALID_RATE)
1542 rate = IWL_RATE_6M_PLCP;
1543 } else {
bb8c093b 1544 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1545 if (rate == IWL_INVALID_RATE)
1546 rate = IWL_RATE_1M_PLCP;
1547 }
1548
bb8c093b 1549 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1550
bb8c093b 1551 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1552 &frame->u.cmd[0]);
1553
bb8c093b 1554 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1555
1556 return rc;
1557}
1558
1559/******************************************************************************
1560 *
1561 * EEPROM related functions
1562 *
1563 ******************************************************************************/
1564
bb8c093b 1565static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1566{
1567 memcpy(mac, priv->eeprom.mac_address, 6);
1568}
1569
1570/**
bb8c093b 1571 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1572 *
6440adb5 1573 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1574 *
1575 * NOTE: This routine uses the non-debug IO access functions.
1576 */
bb8c093b 1577int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c
ZY		 1578{
1579 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1580 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1581 u32 r;
1582 int sz = sizeof(priv->eeprom);
1583 int rc;
1584 int i;
1585 u16 addr;
1586
1587 /* The EEPROM structure has several padding buffers within it
1588 * and when adding new EEPROM maps is subject to programmer errors
1589 * which may be very difficult to identify without explicitly
1590 * checking the resulting size of the eeprom map. */
1591 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1592
1593 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1594 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1595 return -ENOENT;
1596 }
1597
6440adb5 1598 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1599 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1600 if (rc < 0) {
91e17473 1601 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1602 return -ENOENT;
1603 }
1604
1605 /* eeprom is an array of 16bit values */
1606 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1607 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1608 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1609
1610 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1611 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1612 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1613 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1614 break;
1615 udelay(IWL_EEPROM_ACCESS_DELAY);
1616 }
1617
1618 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1619 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1620 return -ETIMEDOUT;
1621 }
1622 e[addr / 2] = le16_to_cpu(r >> 16);
1623 }
1624
1625 return 0;
1626}
1627
1628/******************************************************************************
1629 *
1630 * Misc. internal state and helper functions
1631 *
1632 ******************************************************************************/
c8b0e6e1 1633#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 1634
1635/**
bb8c093b 1636 * iwl3945_report_frame - dump frame to syslog during debug sessions
b481de9c 1637 *
9fbab516 1638 * You may hack this function to show different aspects of received frames,
b481de9c
ZY		 1639 * including selective frame dumps.
1640 * group100 parameter selects whether to show 1 out of 100 good frames.
b481de9c 1641 */
bb8c093b
CH		 1642void iwl3945_report_frame(struct iwl3945_priv *priv,
1643 struct iwl3945_rx_packet *pkt,
b481de9c
ZY		 1644 struct ieee80211_hdr *header, int group100)
1645{
1646 u32 to_us;
1647 u32 print_summary = 0;
1648 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
1649 u32 hundred = 0;
1650 u32 dataframe = 0;
1651 u16 fc;
1652 u16 seq_ctl;
1653 u16 channel;
1654 u16 phy_flags;
1655 int rate_sym;
1656 u16 length;
1657 u16 status;
1658 u16 bcn_tmr;
1659 u32 tsf_low;
1660 u64 tsf;
1661 u8 rssi;
1662 u8 agc;
1663 u16 sig_avg;
1664 u16 noise_diff;
bb8c093b
CH		 1665 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
1666 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
1667 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 1668 u8 *data = IWL_RX_DATA(pkt);
1669
1670 /* MAC header */
1671 fc = le16_to_cpu(header->frame_control);
1672 seq_ctl = le16_to_cpu(header->seq_ctrl);
1673
1674 /* metadata */
1675 channel = le16_to_cpu(rx_hdr->channel);
1676 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
1677 rate_sym = rx_hdr->rate;
1678 length = le16_to_cpu(rx_hdr->len);
1679
1680 /* end-of-frame status and timestamp */
1681 status = le32_to_cpu(rx_end->status);
1682 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
1683 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
1684 tsf = le64_to_cpu(rx_end->timestamp);
1685
1686 /* signal statistics */
1687 rssi = rx_stats->rssi;
1688 agc = rx_stats->agc;
1689 sig_avg = le16_to_cpu(rx_stats->sig_avg);
1690 noise_diff = le16_to_cpu(rx_stats->noise_diff);
1691
1692 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
1693
1694 /* if data frame is to us and all is good,
1695 * (optionally) print summary for only 1 out of every 100 */
1696 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
1697 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
1698 dataframe = 1;
1699 if (!group100)
1700 print_summary = 1; /* print each frame */
1701 else if (priv->framecnt_to_us < 100) {
1702 priv->framecnt_to_us++;
1703 print_summary = 0;
1704 } else {
1705 priv->framecnt_to_us = 0;
1706 print_summary = 1;
1707 hundred = 1;
1708 }
1709 } else {
1710 /* print summary for all other frames */
1711 print_summary = 1;
1712 }
1713
1714 if (print_summary) {
1715 char *title;
1716 u32 rate;
1717
1718 if (hundred)
1719 title = "100Frames";
1720 else if (fc & IEEE80211_FCTL_RETRY)
1721 title = "Retry";
1722 else if (ieee80211_is_assoc_response(fc))
1723 title = "AscRsp";
1724 else if (ieee80211_is_reassoc_response(fc))
1725 title = "RasRsp";
1726 else if (ieee80211_is_probe_response(fc)) {
1727 title = "PrbRsp";
1728 print_dump = 1; /* dump frame contents */
1729 } else if (ieee80211_is_beacon(fc)) {
1730 title = "Beacon";
1731 print_dump = 1; /* dump frame contents */
1732 } else if (ieee80211_is_atim(fc))
1733 title = "ATIM";
1734 else if (ieee80211_is_auth(fc))
1735 title = "Auth";
1736 else if (ieee80211_is_deauth(fc))
1737 title = "DeAuth";
1738 else if (ieee80211_is_disassoc(fc))
1739 title = "DisAssoc";
1740 else
1741 title = "Frame";
1742
bb8c093b 1743 rate = iwl3945_rate_index_from_plcp(rate_sym);
b481de9c
ZY		 1744 if (rate == -1)
1745 rate = 0;
1746 else
bb8c093b 1747 rate = iwl3945_rates[rate].ieee / 2;
b481de9c
ZY		 1748
1749 /* print frame summary.
1750 * MAC addresses show just the last byte (for brevity),
1751 * but you can hack it to show more, if you'd like to. */
1752 if (dataframe)
1753 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
1754 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
1755 title, fc, header->addr1[5],
1756 length, rssi, channel, rate);
1757 else {
1758 /* src/dst addresses assume managed mode */
1759 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
1760 "src=0x%02x, rssi=%u, tim=%lu usec, "
1761 "phy=0x%02x, chnl=%d\n",
1762 title, fc, header->addr1[5],
1763 header->addr3[5], rssi,
1764 tsf_low - priv->scan_start_tsf,
1765 phy_flags, channel);
1766 }
1767 }
1768 if (print_dump)
bb8c093b 1769 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
b481de9c
ZY		 1770}
1771#endif
1772
bb8c093b 1773static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1774{
1775 if (priv->hw_setting.shared_virt)
1776 pci_free_consistent(priv->pci_dev,
bb8c093b 1777 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1778 priv->hw_setting.shared_virt,
1779 priv->hw_setting.shared_phys);
1780}
1781
1782/**
bb8c093b 1783 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1784 *
1785 * return : set the bit for each supported rate insert in ie
1786 */
bb8c093b 1787static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1788 u16 basic_rate, int *left)
b481de9c
ZY		 1789{
1790 u16 ret_rates = 0, bit;
1791 int i;
c7c46676
TW		 1792 u8 *cnt = ie;
1793 u8 *rates = ie + 1;
b481de9c
ZY		 1794
1795 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1796 if (bit & supported_rate) {
1797 ret_rates |= bit;
bb8c093b 1798 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1799 ((bit & basic_rate) ? 0x80 : 0x00);
1800 (*cnt)++;
1801 (*left)--;
1802 if ((*left <= 0) ||
1803 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1804 break;
1805 }
1806 }
1807
1808 return ret_rates;
1809}
1810
1811/**
bb8c093b 1812 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1813 */
bb8c093b 1814static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1815 struct ieee80211_mgmt *frame,
1816 int left, int is_direct)
1817{
1818 int len = 0;
1819 u8 *pos = NULL;
c7c46676 1820 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1821
1822 /* Make sure there is enough space for the probe request,
1823 * two mandatory IEs and the data */
1824 left -= 24;
1825 if (left < 0)
1826 return 0;
1827 len += 24;
1828
1829 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1830 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1831 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1832 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1833 frame->seq_ctrl = 0;
1834
1835 /* fill in our indirect SSID IE */
1836 /* ...next IE... */
1837
1838 left -= 2;
1839 if (left < 0)
1840 return 0;
1841 len += 2;
1842 pos = &(frame->u.probe_req.variable[0]);
1843 *pos++ = WLAN_EID_SSID;
1844 *pos++ = 0;
1845
1846 /* fill in our direct SSID IE... */
1847 if (is_direct) {
1848 /* ...next IE... */
1849 left -= 2 + priv->essid_len;
1850 if (left < 0)
1851 return 0;
1852 /* ... fill it in... */
1853 *pos++ = WLAN_EID_SSID;
1854 *pos++ = priv->essid_len;
1855 memcpy(pos, priv->essid, priv->essid_len);
1856 pos += priv->essid_len;
1857 len += 2 + priv->essid_len;
1858 }
1859
1860 /* fill in supported rate */
1861 /* ...next IE... */
1862 left -= 2;
1863 if (left < 0)
1864 return 0;
c7c46676 1865
b481de9c
ZY		 1866 /* ... fill it in... */
1867 *pos++ = WLAN_EID_SUPP_RATES;
1868 *pos = 0;
c7c46676
TW		 1869
1870 priv->active_rate = priv->rates_mask;
1871 active_rates = priv->active_rate;
b481de9c
ZY		 1872 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1873
c7c46676 1874 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1875 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1876 priv->active_rate_basic, &left);
1877 active_rates &= ~ret_rates;
1878
bb8c093b 1879 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1880 priv->active_rate_basic, &left);
1881 active_rates &= ~ret_rates;
1882
b481de9c
ZY		 1883 len += 2 + *pos;
1884 pos += (*pos) + 1;
c7c46676 1885 if (active_rates == 0)
b481de9c
ZY		 1886 goto fill_end;
1887
1888 /* fill in supported extended rate */
1889 /* ...next IE... */
1890 left -= 2;
1891 if (left < 0)
1892 return 0;
1893 /* ... fill it in... */
1894 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1895 *pos = 0;
bb8c093b 1896 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1897 priv->active_rate_basic, &left);
b481de9c
ZY		 1898 if (*pos > 0)
1899 len += 2 + *pos;
1900
1901 fill_end:
1902 return (u16)len;
1903}
1904
1905/*
1906 * QoS support
1907*/
c8b0e6e1 1908#ifdef CONFIG_IWL3945_QOS
bb8c093b
CH		 1909static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1910 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1911{
1912
bb8c093b
CH		 1913 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1914 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1915}
1916
bb8c093b 1917static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1918{
1919 u16 cw_min = 15;
1920 u16 cw_max = 1023;
1921 u8 aifs = 2;
1922 u8 is_legacy = 0;
1923 unsigned long flags;
1924 int i;
1925
1926 spin_lock_irqsave(&priv->lock, flags);
1927 priv->qos_data.qos_active = 0;
1928
1929 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1930 if (priv->qos_data.qos_enable)
1931 priv->qos_data.qos_active = 1;
1932 if (!(priv->active_rate & 0xfff0)) {
1933 cw_min = 31;
1934 is_legacy = 1;
1935 }
1936 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1937 if (priv->qos_data.qos_enable)
1938 priv->qos_data.qos_active = 1;
1939 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1940 cw_min = 31;
1941 is_legacy = 1;
1942 }
1943
1944 if (priv->qos_data.qos_active)
1945 aifs = 3;
1946
1947 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1948 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1949 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1950 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1951 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1952
1953 if (priv->qos_data.qos_active) {
1954 i = 1;
1955 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1956 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1957 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1958 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1959 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1960
1961 i = 2;
1962 priv->qos_data.def_qos_parm.ac[i].cw_min =
1963 cpu_to_le16((cw_min + 1) / 2 - 1);
1964 priv->qos_data.def_qos_parm.ac[i].cw_max =
1965 cpu_to_le16(cw_max);
1966 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1967 if (is_legacy)
1968 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1969 cpu_to_le16(6016);
1970 else
1971 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1972 cpu_to_le16(3008);
1973 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1974
1975 i = 3;
1976 priv->qos_data.def_qos_parm.ac[i].cw_min =
1977 cpu_to_le16((cw_min + 1) / 4 - 1);
1978 priv->qos_data.def_qos_parm.ac[i].cw_max =
1979 cpu_to_le16((cw_max + 1) / 2 - 1);
1980 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1981 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1982 if (is_legacy)
1983 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1984 cpu_to_le16(3264);
1985 else
1986 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1987 cpu_to_le16(1504);
1988 } else {
1989 for (i = 1; i < 4; i++) {
1990 priv->qos_data.def_qos_parm.ac[i].cw_min =
1991 cpu_to_le16(cw_min);
1992 priv->qos_data.def_qos_parm.ac[i].cw_max =
1993 cpu_to_le16(cw_max);
1994 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1995 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1996 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1997 }
1998 }
1999 IWL_DEBUG_QOS("set QoS to default \n");
2000
2001 spin_unlock_irqrestore(&priv->lock, flags);
2002}
2003
bb8c093b 2004static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 2005{
2006 unsigned long flags;
2007
b481de9c
ZY		 2008 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2009 return;
2010
2011 if (!priv->qos_data.qos_enable)
2012 return;
2013
2014 spin_lock_irqsave(&priv->lock, flags);
2015 priv->qos_data.def_qos_parm.qos_flags = 0;
2016
2017 if (priv->qos_data.qos_cap.q_AP.queue_request &&
2018 !priv->qos_data.qos_cap.q_AP.txop_request)
2019 priv->qos_data.def_qos_parm.qos_flags |=
2020 QOS_PARAM_FLG_TXOP_TYPE_MSK;
2021
2022 if (priv->qos_data.qos_active)
2023 priv->qos_data.def_qos_parm.qos_flags |=
2024 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
2025
2026 spin_unlock_irqrestore(&priv->lock, flags);
2027
bb8c093b 2028 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 2029 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
2030 priv->qos_data.qos_active);
2031
bb8c093b 2032 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 2033 &(priv->qos_data.def_qos_parm));
2034 }
2035}
2036
c8b0e6e1 2037#endif /* CONFIG_IWL3945_QOS */
b481de9c
ZY		 2038/*
2039 * Power management (not Tx power!) functions
2040 */
2041#define MSEC_TO_USEC 1024
2042
2043#define NOSLP __constant_cpu_to_le32(0)
2044#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
2045#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
2046#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
2047 __constant_cpu_to_le32(X1), \
2048 __constant_cpu_to_le32(X2), \
2049 __constant_cpu_to_le32(X3), \
2050 __constant_cpu_to_le32(X4)}
2051
2052
2053/* default power management (not Tx power) table values */
2054/* for tim 0-10 */
bb8c093b 2055static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 2056 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2057 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
2058 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
2059 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
2060 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
2061 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
2062};
2063
2064/* for tim > 10 */
bb8c093b 2065static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 2066 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
2067 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
2068 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
2069 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
2070 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
2071 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
2072 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
2073 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
2074 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
2075 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
2076};
2077
bb8c093b 2078int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 2079{
2080 int rc = 0, i;
bb8c093b
CH		 2081 struct iwl3945_power_mgr *pow_data;
2082 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 2083 u16 pci_pm;
2084
2085 IWL_DEBUG_POWER("Initialize power \n");
2086
2087 pow_data = &(priv->power_data);
2088
2089 memset(pow_data, 0, sizeof(*pow_data));
2090
2091 pow_data->active_index = IWL_POWER_RANGE_0;
2092 pow_data->dtim_val = 0xffff;
2093
2094 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
2095 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
2096
2097 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
2098 if (rc != 0)
2099 return 0;
2100 else {
bb8c093b 2101 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 2102
2103 IWL_DEBUG_POWER("adjust power command flags\n");
2104
2105 for (i = 0; i < IWL_POWER_AC; i++) {
2106 cmd = &pow_data->pwr_range_0[i].cmd;
2107
2108 if (pci_pm & 0x1)
2109 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
2110 else
2111 cmd->flags |= IWL_POWER_PCI_PM_MSK;
2112 }
2113 }
2114 return rc;
2115}
2116
bb8c093b
CH		 2117static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
2118 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 2119{
2120 int rc = 0, i;
2121 u8 skip;
2122 u32 max_sleep = 0;
bb8c093b 2123 struct iwl3945_power_vec_entry *range;
b481de9c 2124 u8 period = 0;
bb8c093b 2125 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 2126
2127 if (mode > IWL_POWER_INDEX_5) {
2128 IWL_DEBUG_POWER("Error invalid power mode \n");
2129 return -1;
2130 }
2131 pow_data = &(priv->power_data);
2132
2133 if (pow_data->active_index == IWL_POWER_RANGE_0)
2134 range = &pow_data->pwr_range_0[0];
2135 else
2136 range = &pow_data->pwr_range_1[1];
2137
bb8c093b 2138 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 2139
2140#ifdef IWL_MAC80211_DISABLE
2141 if (priv->assoc_network != NULL) {
2142 unsigned long flags;
2143
2144 period = priv->assoc_network->tim.tim_period;
2145 }
2146#endif /*IWL_MAC80211_DISABLE */
2147 skip = range[mode].no_dtim;
2148
2149 if (period == 0) {
2150 period = 1;
2151 skip = 0;
2152 }
2153
2154 if (skip == 0) {
2155 max_sleep = period;
2156 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
2157 } else {
2158 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
2159 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
2160 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
2161 }
2162
2163 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
2164 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
2165 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
2166 }
2167
2168 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
2169 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
2170 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
2171 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
2172 le32_to_cpu(cmd->sleep_interval[0]),
2173 le32_to_cpu(cmd->sleep_interval[1]),
2174 le32_to_cpu(cmd->sleep_interval[2]),
2175 le32_to_cpu(cmd->sleep_interval[3]),
2176 le32_to_cpu(cmd->sleep_interval[4]));
2177
2178 return rc;
2179}
2180
bb8c093b 2181static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 2182{
9a62f73b 2183 u32 uninitialized_var(final_mode);
b481de9c 2184 int rc;
bb8c093b 2185 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2186
2187 /* If on battery, set to 3,
01ebd063 2188 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2189 * else user level */
2190 switch (mode) {
2191 case IWL_POWER_BATTERY:
2192 final_mode = IWL_POWER_INDEX_3;
2193 break;
2194 case IWL_POWER_AC:
2195 final_mode = IWL_POWER_MODE_CAM;
2196 break;
2197 default:
2198 final_mode = mode;
2199 break;
2200 }
2201
bb8c093b 2202 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2203
bb8c093b 2204 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2205
2206 if (final_mode == IWL_POWER_MODE_CAM)
2207 clear_bit(STATUS_POWER_PMI, &priv->status);
2208 else
2209 set_bit(STATUS_POWER_PMI, &priv->status);
2210
2211 return rc;
2212}
2213
bb8c093b 2214int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2215{
2216 /* Filter incoming packets to determine if they are targeted toward
2217 * this network, discarding packets coming from ourselves */
2218 switch (priv->iw_mode) {
2219 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2220 /* packets from our adapter are dropped (echo) */
2221 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2222 return 0;
2223 /* {broad,multi}cast packets to our IBSS go through */
2224 if (is_multicast_ether_addr(header->addr1))
2225 return !compare_ether_addr(header->addr3, priv->bssid);
2226 /* packets to our adapter go through */
2227 return !compare_ether_addr(header->addr1, priv->mac_addr);
2228 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2229 /* packets from our adapter are dropped (echo) */
2230 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2231 return 0;
2232 /* {broad,multi}cast packets to our BSS go through */
2233 if (is_multicast_ether_addr(header->addr1))
2234 return !compare_ether_addr(header->addr2, priv->bssid);
2235 /* packets to our adapter go through */
2236 return !compare_ether_addr(header->addr1, priv->mac_addr);
2237 }
2238
2239 return 1;
2240}
2241
2242#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2243
bb8c093b 2244static const char *iwl3945_get_tx_fail_reason(u32 status)
b481de9c
ZY		 2245{
2246 switch (status & TX_STATUS_MSK) {
2247 case TX_STATUS_SUCCESS:
2248 return "SUCCESS";
2249 TX_STATUS_ENTRY(SHORT_LIMIT);
2250 TX_STATUS_ENTRY(LONG_LIMIT);
2251 TX_STATUS_ENTRY(FIFO_UNDERRUN);
2252 TX_STATUS_ENTRY(MGMNT_ABORT);
2253 TX_STATUS_ENTRY(NEXT_FRAG);
2254 TX_STATUS_ENTRY(LIFE_EXPIRE);
2255 TX_STATUS_ENTRY(DEST_PS);
2256 TX_STATUS_ENTRY(ABORTED);
2257 TX_STATUS_ENTRY(BT_RETRY);
2258 TX_STATUS_ENTRY(STA_INVALID);
2259 TX_STATUS_ENTRY(FRAG_DROPPED);
2260 TX_STATUS_ENTRY(TID_DISABLE);
2261 TX_STATUS_ENTRY(FRAME_FLUSHED);
2262 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
2263 TX_STATUS_ENTRY(TX_LOCKED);
2264 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
2265 }
2266
2267 return "UNKNOWN";
2268}
2269
2270/**
bb8c093b 2271 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2272 *
2273 * NOTE: priv->mutex is not required before calling this function
2274 */
bb8c093b 2275static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2276{
2277 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2278 clear_bit(STATUS_SCANNING, &priv->status);
2279 return 0;
2280 }
2281
2282 if (test_bit(STATUS_SCANNING, &priv->status)) {
2283 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2284 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2285 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2286 queue_work(priv->workqueue, &priv->abort_scan);
2287
2288 } else
2289 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2290
2291 return test_bit(STATUS_SCANNING, &priv->status);
2292 }
2293
2294 return 0;
2295}
2296
2297/**
bb8c093b 2298 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2299 * @ms: amount of time to wait (in milliseconds) for scan to abort
2300 *
2301 * NOTE: priv->mutex must be held before calling this function
2302 */
bb8c093b 2303static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2304{
2305 unsigned long now = jiffies;
2306 int ret;
2307
bb8c093b 2308 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2309 if (ret && ms) {
2310 mutex_unlock(&priv->mutex);
2311 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2312 test_bit(STATUS_SCANNING, &priv->status))
2313 msleep(1);
2314 mutex_lock(&priv->mutex);
2315
2316 return test_bit(STATUS_SCANNING, &priv->status);
2317 }
2318
2319 return ret;
2320}
2321
bb8c093b 2322static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2323{
2324 /* Reset ieee stats */
2325
2326 /* We don't reset the net_device_stats (ieee->stats) on
2327 * re-association */
2328
2329 priv->last_seq_num = -1;
2330 priv->last_frag_num = -1;
2331 priv->last_packet_time = 0;
2332
bb8c093b 2333 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2334}
2335
2336#define MAX_UCODE_BEACON_INTERVAL 1024
2337#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2338
bb8c093b 2339static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2340{
2341 u16 new_val = 0;
2342 u16 beacon_factor = 0;
2343
2344 beacon_factor =
2345 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2346 / MAX_UCODE_BEACON_INTERVAL;
2347 new_val = beacon_val / beacon_factor;
2348
2349 return cpu_to_le16(new_val);
2350}
2351
bb8c093b 2352static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2353{
2354 u64 interval_tm_unit;
2355 u64 tsf, result;
2356 unsigned long flags;
2357 struct ieee80211_conf *conf = NULL;
2358 u16 beacon_int = 0;
2359
2360 conf = ieee80211_get_hw_conf(priv->hw);
2361
2362 spin_lock_irqsave(&priv->lock, flags);
2363 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2364 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2365
2366 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2367
2368 tsf = priv->timestamp1;
2369 tsf = ((tsf << 32) | priv->timestamp0);
2370
2371 beacon_int = priv->beacon_int;
2372 spin_unlock_irqrestore(&priv->lock, flags);
2373
2374 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2375 if (beacon_int == 0) {
2376 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2377 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2378 } else {
2379 priv->rxon_timing.beacon_interval =
2380 cpu_to_le16(beacon_int);
2381 priv->rxon_timing.beacon_interval =
bb8c093b 2382 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2383 le16_to_cpu(priv->rxon_timing.beacon_interval));
2384 }
2385
2386 priv->rxon_timing.atim_window = 0;
2387 } else {
2388 priv->rxon_timing.beacon_interval =
bb8c093b 2389 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2390 /* TODO: we need to get atim_window from upper stack
2391 * for now we set to 0 */
2392 priv->rxon_timing.atim_window = 0;
2393 }
2394
2395 interval_tm_unit =
2396 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2397 result = do_div(tsf, interval_tm_unit);
2398 priv->rxon_timing.beacon_init_val =
2399 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2400
2401 IWL_DEBUG_ASSOC
2402 ("beacon interval %d beacon timer %d beacon tim %d\n",
2403 le16_to_cpu(priv->rxon_timing.beacon_interval),
2404 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2405 le16_to_cpu(priv->rxon_timing.atim_window));
2406}
2407
bb8c093b 2408static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2409{
2410 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2411 IWL_ERROR("APs don't scan.\n");
2412 return 0;
2413 }
2414
bb8c093b 2415 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2416 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2417 return -EIO;
2418 }
2419
2420 if (test_bit(STATUS_SCANNING, &priv->status)) {
2421 IWL_DEBUG_SCAN("Scan already in progress.\n");
2422 return -EAGAIN;
2423 }
2424
2425 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2426 IWL_DEBUG_SCAN("Scan request while abort pending. "
2427 "Queuing.\n");
2428 return -EAGAIN;
2429 }
2430
2431 IWL_DEBUG_INFO("Starting scan...\n");
2432 priv->scan_bands = 2;
2433 set_bit(STATUS_SCANNING, &priv->status);
2434 priv->scan_start = jiffies;
2435 priv->scan_pass_start = priv->scan_start;
2436
2437 queue_work(priv->workqueue, &priv->request_scan);
2438
2439 return 0;
2440}
2441
bb8c093b 2442static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2443{
bb8c093b 2444 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2445
2446 if (hw_decrypt)
2447 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2448 else
2449 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2450
2451 return 0;
2452}
2453
bb8c093b 2454static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode)
b481de9c
ZY		 2455{
2456 if (phymode == MODE_IEEE80211A) {
2457 priv->staging_rxon.flags &=
2458 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2459 | RXON_FLG_CCK_MSK);
2460 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2461 } else {
bb8c093b 2462 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2463 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2464 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2465 else
2466 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2467
2468 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2469 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2470
2471 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2472 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2473 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2474 }
2475}
2476
2477/*
01ebd063 2478 * initialize rxon structure with default values from eeprom
b481de9c 2479 */
bb8c093b 2480static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2481{
bb8c093b 2482 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2483
2484 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2485
2486 switch (priv->iw_mode) {
2487 case IEEE80211_IF_TYPE_AP:
2488 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2489 break;
2490
2491 case IEEE80211_IF_TYPE_STA:
2492 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2493 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2494 break;
2495
2496 case IEEE80211_IF_TYPE_IBSS:
2497 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2498 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2499 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2500 RXON_FILTER_ACCEPT_GRP_MSK;
2501 break;
2502
2503 case IEEE80211_IF_TYPE_MNTR:
2504 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2505 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2506 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2507 break;
2508 }
2509
2510#if 0
2511 /* TODO: Figure out when short_preamble would be set and cache from
2512 * that */
2513 if (!hw_to_local(priv->hw)->short_preamble)
2514 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2515 else
2516 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2517#endif
2518
bb8c093b 2519 ch_info = iwl3945_get_channel_info(priv, priv->phymode,
b481de9c
ZY		 2520 le16_to_cpu(priv->staging_rxon.channel));
2521
2522 if (!ch_info)
2523 ch_info = &priv->channel_info[0];
2524
2525 /*
2526 * in some case A channels are all non IBSS
2527 * in this case force B/G channel
2528 */
2529 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2530 !(is_channel_ibss(ch_info)))
2531 ch_info = &priv->channel_info[0];
2532
2533 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2534 if (is_channel_a_band(ch_info))
2535 priv->phymode = MODE_IEEE80211A;
2536 else
2537 priv->phymode = MODE_IEEE80211G;
2538
bb8c093b 2539 iwl3945_set_flags_for_phymode(priv, priv->phymode);
b481de9c
ZY		 2540
2541 priv->staging_rxon.ofdm_basic_rates =
2542 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2543 priv->staging_rxon.cck_basic_rates =
2544 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2545}
2546
bb8c093b 2547static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2548{
bb8c093b 2549 if (!iwl3945_is_ready_rf(priv))
b481de9c
ZY		 2550 return -EAGAIN;
2551
2552 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2553 const struct iwl3945_channel_info *ch_info;
b481de9c 2554
bb8c093b 2555 ch_info = iwl3945_get_channel_info(priv,
b481de9c
ZY		 2556 priv->phymode,
2557 le16_to_cpu(priv->staging_rxon.channel));
2558
2559 if (!ch_info || !is_channel_ibss(ch_info)) {
2560 IWL_ERROR("channel %d not IBSS channel\n",
2561 le16_to_cpu(priv->staging_rxon.channel));
2562 return -EINVAL;
2563 }
2564 }
2565
2566 cancel_delayed_work(&priv->scan_check);
bb8c093b 2567 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 2568 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2569 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2570 return -EAGAIN;
2571 }
2572
2573 priv->iw_mode = mode;
2574
bb8c093b 2575 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2576 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2577
bb8c093b 2578 iwl3945_clear_stations_table(priv);
b481de9c 2579
bb8c093b 2580 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2581
2582 return 0;
2583}
2584
bb8c093b 2585static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
b481de9c 2586 struct ieee80211_tx_control *ctl,
bb8c093b 2587 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2588 struct sk_buff *skb_frag,
2589 int last_frag)
2590{
bb8c093b 2591 struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
b481de9c
ZY		 2592
2593 switch (keyinfo->alg) {
2594 case ALG_CCMP:
2595 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2596 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2597 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2598 break;
2599
2600 case ALG_TKIP:
2601#if 0
2602 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2603
2604 if (last_frag)
2605 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2606 8);
2607 else
2608 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2609#endif
2610 break;
2611
2612 case ALG_WEP:
2613 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2614 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2615
2616 if (keyinfo->keylen == 13)
2617 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2618
2619 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2620
2621 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2622 "with key %d\n", ctl->key_idx);
2623 break;
2624
b481de9c
ZY		 2625 default:
2626 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2627 break;
2628 }
2629}
2630
2631/*
2632 * handle build REPLY_TX command notification.
2633 */
bb8c093b
CH		 2634static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2635 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2636 struct ieee80211_tx_control *ctrl,
2637 struct ieee80211_hdr *hdr,
2638 int is_unicast, u8 std_id)
2639{
2640 __le16 *qc;
2641 u16 fc = le16_to_cpu(hdr->frame_control);
2642 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2643
2644 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2645 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2646 tx_flags |= TX_CMD_FLG_ACK_MSK;
2647 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2648 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2649 if (ieee80211_is_probe_response(fc) &&
2650 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2651 tx_flags |= TX_CMD_FLG_TSF_MSK;
2652 } else {
2653 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2654 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2655 }
2656
2657 cmd->cmd.tx.sta_id = std_id;
2658 if (ieee80211_get_morefrag(hdr))
2659 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2660
2661 qc = ieee80211_get_qos_ctrl(hdr);
2662 if (qc) {
2663 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2664 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2665 } else
2666 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2667
2668 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2669 tx_flags |= TX_CMD_FLG_RTS_MSK;
2670 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2671 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2672 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2673 tx_flags |= TX_CMD_FLG_CTS_MSK;
2674 }
2675
2676 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2677 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2678
2679 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2680 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2681 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2682 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2683 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2684 else
bc434dd2 2685 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
b481de9c
ZY		 2686 } else
2687 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2688
2689 cmd->cmd.tx.driver_txop = 0;
2690 cmd->cmd.tx.tx_flags = tx_flags;
2691 cmd->cmd.tx.next_frame_len = 0;
2692}
2693
6440adb5
BC		 2694/**
2695 * iwl3945_get_sta_id - Find station's index within station table
2696 */
bb8c093b 2697static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2698{
2699 int sta_id;
2700 u16 fc = le16_to_cpu(hdr->frame_control);
2701
6440adb5 2702 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2703 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2704 is_multicast_ether_addr(hdr->addr1))
2705 return priv->hw_setting.bcast_sta_id;
2706
2707 switch (priv->iw_mode) {
2708
6440adb5
BC		 2709 /* If we are a client station in a BSS network, use the special
2710 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2711 case IEEE80211_IF_TYPE_STA:
2712 return IWL_AP_ID;
2713
2714 /* If we are an AP, then find the station, or use BCAST */
2715 case IEEE80211_IF_TYPE_AP:
bb8c093b 2716 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2717 if (sta_id != IWL_INVALID_STATION)
2718 return sta_id;
2719 return priv->hw_setting.bcast_sta_id;
2720
6440adb5
BC		 2721 /* If this frame is going out to an IBSS network, find the station,
2722 * or create a new station table entry */
0795af57
JP		 2723 case IEEE80211_IF_TYPE_IBSS: {
2724 DECLARE_MAC_BUF(mac);
2725
6440adb5 2726 /* Create new station table entry */
bb8c093b 2727 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2728 if (sta_id != IWL_INVALID_STATION)
2729 return sta_id;
2730
bb8c093b 2731 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2732
2733 if (sta_id != IWL_INVALID_STATION)
2734 return sta_id;
2735
0795af57 2736 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2737 "Defaulting to broadcast...\n",
0795af57 2738 print_mac(mac, hdr->addr1));
bb8c093b 2739 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2740 return priv->hw_setting.bcast_sta_id;
0795af57 2741 }
b481de9c 2742 default:
01ebd063 2743 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2744 return priv->hw_setting.bcast_sta_id;
2745 }
2746}
2747
2748/*
2749 * start REPLY_TX command process
2750 */
bb8c093b 2751static int iwl3945_tx_skb(struct iwl3945_priv *priv,
b481de9c
ZY		 2752 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2753{
2754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2755 struct iwl3945_tfd_frame *tfd;
b481de9c
ZY		 2756 u32 *control_flags;
2757 int txq_id = ctl->queue;
bb8c093b
CH		 2758 struct iwl3945_tx_queue *txq = NULL;
2759 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2760 dma_addr_t phys_addr;
2761 dma_addr_t txcmd_phys;
bb8c093b 2762 struct iwl3945_cmd *out_cmd = NULL;
b481de9c
ZY		 2763 u16 len, idx, len_org;
2764 u8 id, hdr_len, unicast;
2765 u8 sta_id;
2766 u16 seq_number = 0;
2767 u16 fc;
2768 __le16 *qc;
2769 u8 wait_write_ptr = 0;
2770 unsigned long flags;
2771 int rc;
2772
2773 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2774 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2775 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2776 goto drop_unlock;
2777 }
2778
2779 if (!priv->interface_id) {
2780 IWL_DEBUG_DROP("Dropping - !priv->interface_id\n");
2781 goto drop_unlock;
2782 }
2783
2784 if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
2785 IWL_ERROR("ERROR: No TX rate available.\n");
2786 goto drop_unlock;
2787 }
2788
2789 unicast = !is_multicast_ether_addr(hdr->addr1);
2790 id = 0;
2791
2792 fc = le16_to_cpu(hdr->frame_control);
2793
c8b0e6e1 2794#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2795 if (ieee80211_is_auth(fc))
2796 IWL_DEBUG_TX("Sending AUTH frame\n");
2797 else if (ieee80211_is_assoc_request(fc))
2798 IWL_DEBUG_TX("Sending ASSOC frame\n");
2799 else if (ieee80211_is_reassoc_request(fc))
2800 IWL_DEBUG_TX("Sending REASSOC frame\n");
2801#endif
2802
7878a5a4
MA		 2803 /* drop all data frame if we are not associated */
2804 if (!iwl3945_is_associated(priv) && !priv->assoc_id &&
b481de9c 2805 ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
bb8c093b 2806 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2807 goto drop_unlock;
2808 }
2809
2810 spin_unlock_irqrestore(&priv->lock, flags);
2811
2812 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
BC		 2813
2814 /* Find (or create) index into station table for destination station */
bb8c093b 2815 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2816 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2817 DECLARE_MAC_BUF(mac);
2818
2819 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2820 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2821 goto drop;
2822 }
2823
2824 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2825
2826 qc = ieee80211_get_qos_ctrl(hdr);
2827 if (qc) {
2828 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2829 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2830 IEEE80211_SCTL_SEQ;
2831 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2832 (hdr->seq_ctrl &
2833 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2834 seq_number += 0x10;
2835 }
6440adb5
BC		 2836
2837 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2838 txq = &priv->txq[txq_id];
2839 q = &txq->q;
2840
2841 spin_lock_irqsave(&priv->lock, flags);
2842
6440adb5 2843 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2844 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2845 memset(tfd, 0, sizeof(*tfd));
2846 control_flags = (u32 *) tfd;
fc4b6853 2847 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2848
6440adb5 2849 /* Set up driver data for this TFD */
bb8c093b 2850 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853
TW		 2851 txq->txb[q->write_ptr].skb[0] = skb;
2852 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2853 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
BC		 2854
2855 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2856 out_cmd = &txq->cmd[idx];
2857 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2858 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
BC		 2859
2860 /*
2861 * Set up the Tx-command (not MAC!) header.
2862 * Store the chosen Tx queue and TFD index within the sequence field;
2863 * after Tx, uCode's Tx response will return this value so driver can
2864 * locate the frame within the tx queue and do post-tx processing.
2865 */
b481de9c
ZY		 2866 out_cmd->hdr.cmd = REPLY_TX;
2867 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2868 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC		 2869
2870 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2871 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2872
6440adb5
BC		 2873 /*
2874 * Use the first empty entry in this queue's command buffer array
2875 * to contain the Tx command and MAC header concatenated together
2876 * (payload data will be in another buffer).
2877 * Size of this varies, due to varying MAC header length.
2878 * If end is not dword aligned, we'll have 2 extra bytes at the end
2879 * of the MAC header (device reads on dword boundaries).
2880 * We'll tell device about this padding later.
2881 */
b481de9c 2882 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2883 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2884
2885 len_org = len;
2886 len = (len + 3) & ~3;
2887
2888 if (len_org != len)
2889 len_org = 1;
2890 else
2891 len_org = 0;
2892
6440adb5
BC		 2893 /* Physical address of this Tx command's header (not MAC header!),
2894 * within command buffer array. */
bb8c093b
CH		 2895 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2896 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2897
6440adb5
BC		 2898 /* Add buffer containing Tx command and MAC(!) header to TFD's
2899 * first entry */
bb8c093b 2900 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY		 2901
2902 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
bb8c093b 2903 iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
b481de9c 2904
6440adb5
BC		 2905 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2906 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2907 len = skb->len - hdr_len;
2908 if (len) {
2909 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2910 len, PCI_DMA_TODEVICE);
bb8c093b 2911 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2912 }
2913
b481de9c 2914 if (!len)
6440adb5 2915 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2916 *control_flags = TFD_CTL_COUNT_SET(1);
2917 else
6440adb5
BC		 2918 /* Else use 2 buffers.
2919 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2920 *control_flags = TFD_CTL_COUNT_SET(2) |
2921 TFD_CTL_PAD_SET(U32_PAD(len));
2922
6440adb5 2923 /* Total # bytes to be transmitted */
b481de9c
ZY		 2924 len = (u16)skb->len;
2925 out_cmd->cmd.tx.len = cpu_to_le16(len);
2926
2927 /* TODO need this for burst mode later on */
bb8c093b 2928 iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY		 2929
2930 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2931 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c
ZY		 2932
2933 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2934 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2935
2936 if (!ieee80211_get_morefrag(hdr)) {
2937 txq->need_update = 1;
2938 if (qc) {
2939 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2940 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2941 }
2942 } else {
2943 wait_write_ptr = 1;
2944 txq->need_update = 0;
2945 }
2946
bb8c093b 2947 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2948 sizeof(out_cmd->cmd.tx));
2949
bb8c093b 2950 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 2951 ieee80211_get_hdrlen(fc));
2952
6440adb5 2953 /* Tell device the write index *just past* this latest filled TFD */
bb8c093b
CH		 2954 q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
2955 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2956 spin_unlock_irqrestore(&priv->lock, flags);
2957
2958 if (rc)
2959 return rc;
2960
bb8c093b 2961 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2962 && priv->mac80211_registered) {
2963 if (wait_write_ptr) {
2964 spin_lock_irqsave(&priv->lock, flags);
2965 txq->need_update = 1;
bb8c093b 2966 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2967 spin_unlock_irqrestore(&priv->lock, flags);
2968 }
2969
2970 ieee80211_stop_queue(priv->hw, ctl->queue);
2971 }
2972
2973 return 0;
2974
2975drop_unlock:
2976 spin_unlock_irqrestore(&priv->lock, flags);
2977drop:
2978 return -1;
2979}
2980
bb8c093b 2981static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c
ZY		 2982{
2983 const struct ieee80211_hw_mode *hw = NULL;
2984 struct ieee80211_rate *rate;
2985 int i;
2986
bb8c093b 2987 hw = iwl3945_get_hw_mode(priv, priv->phymode);
c4ba9621
SA		 2988 if (!hw) {
2989 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2990 return;
2991 }
b481de9c
ZY		 2992
2993 priv->active_rate = 0;
2994 priv->active_rate_basic = 0;
2995
2996 IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
2997 hw->mode == MODE_IEEE80211A ?
2998 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
2999
3000 for (i = 0; i < hw->num_rates; i++) {
3001 rate = &(hw->rates[i]);
3002 if ((rate->val < IWL_RATE_COUNT) &&
3003 (rate->flags & IEEE80211_RATE_SUPPORTED)) {
3004 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
bb8c093b 3005 rate->val, iwl3945_rates[rate->val].plcp,
b481de9c
ZY		 3006 (rate->flags & IEEE80211_RATE_BASIC) ?
3007 "*" : "");
3008 priv->active_rate |= (1 << rate->val);
3009 if (rate->flags & IEEE80211_RATE_BASIC)
3010 priv->active_rate_basic |= (1 << rate->val);
3011 } else
3012 IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
bb8c093b 3013 rate->val, iwl3945_rates[rate->val].plcp);
b481de9c
ZY		 3014 }
3015
3016 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
3017 priv->active_rate, priv->active_rate_basic);
3018
3019 /*
3020 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
3021 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
3022 * OFDM
3023 */
3024 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
3025 priv->staging_rxon.cck_basic_rates =
3026 ((priv->active_rate_basic &
3027 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
3028 else
3029 priv->staging_rxon.cck_basic_rates =
3030 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
3031
3032 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
3033 priv->staging_rxon.ofdm_basic_rates =
3034 ((priv->active_rate_basic &
3035 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
3036 IWL_FIRST_OFDM_RATE) & 0xFF;
3037 else
3038 priv->staging_rxon.ofdm_basic_rates =
3039 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
3040}
3041
bb8c093b 3042static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 3043{
3044 unsigned long flags;
3045
3046 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
3047 return;
3048
3049 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
3050 disable_radio ? "OFF" : "ON");
3051
3052 if (disable_radio) {
bb8c093b 3053 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3054 /* FIXME: This is a workaround for AP */
3055 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
3056 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3057 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3058 CSR_UCODE_SW_BIT_RFKILL);
3059 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 3060 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 3061 set_bit(STATUS_RF_KILL_SW, &priv->status);
3062 }
3063 return;
3064 }
3065
3066 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3067 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3068
3069 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3070 spin_unlock_irqrestore(&priv->lock, flags);
3071
3072 /* wake up ucode */
3073 msleep(10);
3074
3075 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 3076 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3077 if (!iwl3945_grab_nic_access(priv))
3078 iwl3945_release_nic_access(priv);
b481de9c
ZY		 3079 spin_unlock_irqrestore(&priv->lock, flags);
3080
3081 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
3082 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
3083 "disabled by HW switch\n");
3084 return;
3085 }
3086
3087 queue_work(priv->workqueue, &priv->restart);
3088 return;
3089}
3090
bb8c093b 3091void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 3092 u32 decrypt_res, struct ieee80211_rx_status *stats)
3093{
3094 u16 fc =
3095 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
3096
3097 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
3098 return;
3099
3100 if (!(fc & IEEE80211_FCTL_PROTECTED))
3101 return;
3102
3103 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
3104 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
3105 case RX_RES_STATUS_SEC_TYPE_TKIP:
3106 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3107 RX_RES_STATUS_BAD_ICV_MIC)
3108 stats->flag |= RX_FLAG_MMIC_ERROR;
3109 case RX_RES_STATUS_SEC_TYPE_WEP:
3110 case RX_RES_STATUS_SEC_TYPE_CCMP:
3111 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
3112 RX_RES_STATUS_DECRYPT_OK) {
3113 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
3114 stats->flag |= RX_FLAG_DECRYPTED;
3115 }
3116 break;
3117
3118 default:
3119 break;
3120 }
3121}
3122
bb8c093b
CH		 3123void iwl3945_handle_data_packet_monitor(struct iwl3945_priv *priv,
3124 struct iwl3945_rx_mem_buffer *rxb,
b481de9c
ZY		 3125 void *data, short len,
3126 struct ieee80211_rx_status *stats,
3127 u16 phy_flags)
3128{
bb8c093b 3129 struct iwl3945_rt_rx_hdr *iwl3945_rt;
b481de9c
ZY		 3130
3131 /* First cache any information we need before we overwrite
3132 * the information provided in the skb from the hardware */
3133 s8 signal = stats->ssi;
3134 s8 noise = 0;
3135 int rate = stats->rate;
3136 u64 tsf = stats->mactime;
3137 __le16 phy_flags_hw = cpu_to_le16(phy_flags);
3138
3139 /* We received data from the HW, so stop the watchdog */
bb8c093b 3140 if (len > IWL_RX_BUF_SIZE - sizeof(*iwl3945_rt)) {
b481de9c
ZY		 3141 IWL_DEBUG_DROP("Dropping too large packet in monitor\n");
3142 return;
3143 }
3144
3145 /* copy the frame data to write after where the radiotap header goes */
bb8c093b
CH		 3146 iwl3945_rt = (void *)rxb->skb->data;
3147 memmove(iwl3945_rt->payload, data, len);
b481de9c 3148
bb8c093b
CH		 3149 iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3150 iwl3945_rt->rt_hdr.it_pad = 0; /* always good to zero */
b481de9c
ZY		 3151
3152 /* total header + data */
bb8c093b 3153 iwl3945_rt->rt_hdr.it_len = cpu_to_le16(sizeof(*iwl3945_rt));
b481de9c
ZY		 3154
3155 /* Set the size of the skb to the size of the frame */
bb8c093b 3156 skb_put(rxb->skb, sizeof(*iwl3945_rt) + len);
b481de9c
ZY		 3157
3158 /* Big bitfield of all the fields we provide in radiotap */
bb8c093b 3159 iwl3945_rt->rt_hdr.it_present =
b481de9c
ZY		 3160 cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3161 (1 << IEEE80211_RADIOTAP_FLAGS) |
3162 (1 << IEEE80211_RADIOTAP_RATE) |
3163 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3164 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3165 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3166 (1 << IEEE80211_RADIOTAP_ANTENNA));
3167
3168 /* Zero the flags, we'll add to them as we go */
bb8c093b 3169 iwl3945_rt->rt_flags = 0;
b481de9c 3170
bb8c093b 3171 iwl3945_rt->rt_tsf = cpu_to_le64(tsf);
b481de9c
ZY		 3172
3173 /* Convert to dBm */
bb8c093b
CH		 3174 iwl3945_rt->rt_dbmsignal = signal;
3175 iwl3945_rt->rt_dbmnoise = noise;
b481de9c
ZY		 3176
3177 /* Convert the channel frequency and set the flags */
bb8c093b 3178 iwl3945_rt->rt_channelMHz = cpu_to_le16(stats->freq);
b481de9c 3179 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
bb8c093b 3180 iwl3945_rt->rt_chbitmask =
b481de9c
ZY		 3181 cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ));
3182 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
bb8c093b 3183 iwl3945_rt->rt_chbitmask =
b481de9c
ZY		 3184 cpu_to_le16((IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ));
3185 else /* 802.11g */
bb8c093b 3186 iwl3945_rt->rt_chbitmask =
b481de9c
ZY		 3187 cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ));
3188
bb8c093b 3189 rate = iwl3945_rate_index_from_plcp(rate);
b481de9c 3190 if (rate == -1)
bb8c093b 3191 iwl3945_rt->rt_rate = 0;
b481de9c 3192 else
bb8c093b 3193 iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
b481de9c
ZY		 3194
3195 /* antenna number */
bb8c093b 3196 iwl3945_rt->rt_antenna =
b481de9c
ZY		 3197 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
3198
3199 /* set the preamble flag if we have it */
3200 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
bb8c093b 3201 iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
b481de9c
ZY		 3202
3203 IWL_DEBUG_RX("Rx packet of %d bytes.\n", rxb->skb->len);
3204
3205 stats->flag |= RX_FLAG_RADIOTAP;
3206 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3207 rxb->skb = NULL;
3208}
3209
3210
3211#define IWL_PACKET_RETRY_TIME HZ
3212
bb8c093b 3213int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 3214{
3215 u16 sc = le16_to_cpu(header->seq_ctrl);
3216 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
3217 u16 frag = sc & IEEE80211_SCTL_FRAG;
3218 u16 *last_seq, *last_frag;
3219 unsigned long *last_time;
3220
3221 switch (priv->iw_mode) {
3222 case IEEE80211_IF_TYPE_IBSS:{
3223 struct list_head *p;
bb8c093b 3224 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 3225 u8 *mac = header->addr2;
3226 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
3227
3228 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 3229 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 3230 if (!compare_ether_addr(entry->mac, mac))
3231 break;
3232 }
3233 if (p == &priv->ibss_mac_hash[index]) {
3234 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
3235 if (!entry) {
bc434dd2 3236 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 3237 return 0;
3238 }
3239 memcpy(entry->mac, mac, ETH_ALEN);
3240 entry->seq_num = seq;
3241 entry->frag_num = frag;
3242 entry->packet_time = jiffies;
bc434dd2 3243 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 3244 return 0;
3245 }
3246 last_seq = &entry->seq_num;
3247 last_frag = &entry->frag_num;
3248 last_time = &entry->packet_time;
3249 break;
3250 }
3251 case IEEE80211_IF_TYPE_STA:
3252 last_seq = &priv->last_seq_num;
3253 last_frag = &priv->last_frag_num;
3254 last_time = &priv->last_packet_time;
3255 break;
3256 default:
3257 return 0;
3258 }
3259 if ((*last_seq == seq) &&
3260 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
3261 if (*last_frag == frag)
3262 goto drop;
3263 if (*last_frag + 1 != frag)
3264 /* out-of-order fragment */
3265 goto drop;
3266 } else
3267 *last_seq = seq;
3268
3269 *last_frag = frag;
3270 *last_time = jiffies;
3271 return 0;
3272
3273 drop:
3274 return 1;
3275}
3276
c8b0e6e1 3277#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 3278
3279#include "iwl-spectrum.h"
3280
3281#define BEACON_TIME_MASK_LOW 0x00FFFFFF
3282#define BEACON_TIME_MASK_HIGH 0xFF000000
3283#define TIME_UNIT 1024
3284
3285/*
3286 * extended beacon time format
3287 * time in usec will be changed into a 32-bit value in 8:24 format
3288 * the high 1 byte is the beacon counts
3289 * the lower 3 bytes is the time in usec within one beacon interval
3290 */
3291
bb8c093b 3292static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 3293{
3294 u32 quot;
3295 u32 rem;
3296 u32 interval = beacon_interval * 1024;
3297
3298 if (!interval || !usec)
3299 return 0;
3300
3301 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3302 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3303
3304 return (quot << 24) + rem;
3305}
3306
3307/* base is usually what we get from ucode with each received frame,
3308 * the same as HW timer counter counting down
3309 */
3310
bb8c093b 3311static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3312{
3313 u32 base_low = base & BEACON_TIME_MASK_LOW;
3314 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3315 u32 interval = beacon_interval * TIME_UNIT;
3316 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3317 (addon & BEACON_TIME_MASK_HIGH);
3318
3319 if (base_low > addon_low)
3320 res += base_low - addon_low;
3321 else if (base_low < addon_low) {
3322 res += interval + base_low - addon_low;
3323 res += (1 << 24);
3324 } else
3325 res += (1 << 24);
3326
3327 return cpu_to_le32(res);
3328}
3329
bb8c093b 3330static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3331 struct ieee80211_measurement_params *params,
3332 u8 type)
3333{
bb8c093b
CH		 3334 struct iwl3945_spectrum_cmd spectrum;
3335 struct iwl3945_rx_packet *res;
3336 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3337 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3338 .data = (void *)&spectrum,
3339 .meta.flags = CMD_WANT_SKB,
3340 };
3341 u32 add_time = le64_to_cpu(params->start_time);
3342 int rc;
3343 int spectrum_resp_status;
3344 int duration = le16_to_cpu(params->duration);
3345
bb8c093b 3346 if (iwl3945_is_associated(priv))
b481de9c 3347 add_time =
bb8c093b 3348 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3349 le64_to_cpu(params->start_time) - priv->last_tsf,
3350 le16_to_cpu(priv->rxon_timing.beacon_interval));
3351
3352 memset(&spectrum, 0, sizeof(spectrum));
3353
3354 spectrum.channel_count = cpu_to_le16(1);
3355 spectrum.flags =
3356 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3357 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3358 cmd.len = sizeof(spectrum);
3359 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3360
bb8c093b 3361 if (iwl3945_is_associated(priv))
b481de9c 3362 spectrum.start_time =
bb8c093b 3363 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3364 add_time,
3365 le16_to_cpu(priv->rxon_timing.beacon_interval));
3366 else
3367 spectrum.start_time = 0;
3368
3369 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3370 spectrum.channels[0].channel = params->channel;
3371 spectrum.channels[0].type = type;
3372 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3373 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3374 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3375
bb8c093b 3376 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3377 if (rc)
3378 return rc;
3379
bb8c093b 3380 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3381 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3382 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3383 rc = -EIO;
3384 }
3385
3386 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3387 switch (spectrum_resp_status) {
3388 case 0: /* Command will be handled */
3389 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3390 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3391 res->u.spectrum.id);
b481de9c
ZY		 3392 priv->measurement_status &= ~MEASUREMENT_READY;
3393 }
3394 priv->measurement_status |= MEASUREMENT_ACTIVE;
3395 rc = 0;
3396 break;
3397
3398 case 1: /* Command will not be handled */
3399 rc = -EAGAIN;
3400 break;
3401 }
3402
3403 dev_kfree_skb_any(cmd.meta.u.skb);
3404
3405 return rc;
3406}
3407#endif
3408
bb8c093b
CH		 3409static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
3410 struct iwl3945_tx_info *tx_sta)
b481de9c
ZY		 3411{
3412
3413 tx_sta->status.ack_signal = 0;
3414 tx_sta->status.excessive_retries = 0;
3415 tx_sta->status.queue_length = 0;
3416 tx_sta->status.queue_number = 0;
3417
3418 if (in_interrupt())
3419 ieee80211_tx_status_irqsafe(priv->hw,
3420 tx_sta->skb[0], &(tx_sta->status));
3421 else
3422 ieee80211_tx_status(priv->hw,
3423 tx_sta->skb[0], &(tx_sta->status));
3424
3425 tx_sta->skb[0] = NULL;
3426}
3427
3428/**
6440adb5 3429 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 3430 *
6440adb5
BC		 3431 * When FW advances 'R' index, all entries between old and new 'R' index
3432 * need to be reclaimed. As result, some free space forms. If there is
3433 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 3434 */
bb8c093b 3435static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
b481de9c 3436{
bb8c093b
CH		 3437 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3438 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 3439 int nfreed = 0;
3440
3441 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
3442 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3443 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 3444 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY		 3445 return 0;
3446 }
3447
bb8c093b 3448 for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
fc4b6853 3449 q->read_ptr != index;
bb8c093b 3450 q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 3451 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 3452 iwl3945_txstatus_to_ieee(priv,
fc4b6853 3453 &(txq->txb[txq->q.read_ptr]));
bb8c093b 3454 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c
ZY		 3455 } else if (nfreed > 1) {
3456 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 3457 q->write_ptr, q->read_ptr);
b481de9c
ZY		 3458 queue_work(priv->workqueue, &priv->restart);
3459 }
3460 nfreed++;
3461 }
3462
bb8c093b 3463 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY		 3464 (txq_id != IWL_CMD_QUEUE_NUM) &&
3465 priv->mac80211_registered)
3466 ieee80211_wake_queue(priv->hw, txq_id);
3467
3468
3469 return nfreed;
3470}
3471
bb8c093b 3472static int iwl3945_is_tx_success(u32 status)
b481de9c
ZY		 3473{
3474 return (status & 0xFF) == 0x1;
3475}
3476
3477/******************************************************************************
3478 *
3479 * Generic RX handler implementations
3480 *
3481 ******************************************************************************/
6440adb5
BC		 3482/**
3483 * iwl3945_rx_reply_tx - Handle Tx response
3484 */
bb8c093b
CH		 3485static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
3486 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3487{
bb8c093b 3488 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3489 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3490 int txq_id = SEQ_TO_QUEUE(sequence);
3491 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3492 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3493 struct ieee80211_tx_status *tx_status;
bb8c093b 3494 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c
ZY		 3495 u32 status = le32_to_cpu(tx_resp->status);
3496
3497 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3498 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3499 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW		 3500 index, txq->q.n_bd, txq->q.write_ptr,
3501 txq->q.read_ptr);
b481de9c
ZY		 3502 return;
3503 }
3504
fc4b6853 3505 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY		 3506
3507 tx_status->retry_count = tx_resp->failure_frame;
3508 tx_status->queue_number = status;
3509 tx_status->queue_length = tx_resp->bt_kill_count;
3510 tx_status->queue_length |= tx_resp->failure_rts;
3511
3512 tx_status->flags =
bb8c093b 3513 iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
b481de9c 3514
bb8c093b 3515 tx_status->control.tx_rate = iwl3945_rate_index_from_plcp(tx_resp->rate);
b481de9c
ZY		 3516
3517 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
bb8c093b 3518 txq_id, iwl3945_get_tx_fail_reason(status), status,
b481de9c
ZY		 3519 tx_resp->rate, tx_resp->failure_frame);
3520
3521 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3522 if (index != -1)
bb8c093b 3523 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3524
3525 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3526 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3527}
3528
3529
bb8c093b
CH		 3530static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3531 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3532{
bb8c093b
CH		 3533 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3534 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3535 struct delayed_work *pwork;
3536
3537 palive = &pkt->u.alive_frame;
3538
3539 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3540 "0x%01X 0x%01X\n",
3541 palive->is_valid, palive->ver_type,
3542 palive->ver_subtype);
3543
3544 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3545 IWL_DEBUG_INFO("Initialization Alive received.\n");
3546 memcpy(&priv->card_alive_init,
3547 &pkt->u.alive_frame,
bb8c093b 3548 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3549 pwork = &priv->init_alive_start;
3550 } else {
3551 IWL_DEBUG_INFO("Runtime Alive received.\n");
3552 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3553 sizeof(struct iwl3945_alive_resp));
b481de9c 3554 pwork = &priv->alive_start;
bb8c093b 3555 iwl3945_disable_events(priv);
b481de9c
ZY		 3556 }
3557
3558 /* We delay the ALIVE response by 5ms to
3559 * give the HW RF Kill time to activate... */
3560 if (palive->is_valid == UCODE_VALID_OK)
3561 queue_delayed_work(priv->workqueue, pwork,
3562 msecs_to_jiffies(5));
3563 else
3564 IWL_WARNING("uCode did not respond OK.\n");
3565}
3566
bb8c093b
CH		 3567static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3568 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3569{
bb8c093b 3570 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3571
3572 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3573 return;
3574}
3575
bb8c093b
CH		 3576static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3577 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3578{
bb8c093b 3579 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3580
3581 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3582 "seq 0x%04X ser 0x%08X\n",
3583 le32_to_cpu(pkt->u.err_resp.error_type),
3584 get_cmd_string(pkt->u.err_resp.cmd_id),
3585 pkt->u.err_resp.cmd_id,
3586 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3587 le32_to_cpu(pkt->u.err_resp.error_info));
3588}
3589
3590#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3591
bb8c093b 3592static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3593{
bb8c093b
CH		 3594 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3595 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3596 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3597 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3598 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3599 rxon->channel = csa->channel;
3600 priv->staging_rxon.channel = csa->channel;
3601}
3602
bb8c093b
CH		 3603static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3604 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3605{
c8b0e6e1 3606#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3607 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3608 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3609
3610 if (!report->state) {
3611 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3612 "Spectrum Measure Notification: Start\n");
3613 return;
3614 }
3615
3616 memcpy(&priv->measure_report, report, sizeof(*report));
3617 priv->measurement_status |= MEASUREMENT_READY;
3618#endif
3619}
3620
bb8c093b
CH		 3621static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3622 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3623{
c8b0e6e1 3624#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3625 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3626 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3627 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3628 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3629#endif
3630}
3631
bb8c093b
CH		 3632static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3633 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3634{
bb8c093b 3635 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3636 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3637 "notification for %s:\n",
3638 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3639 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3640}
3641
bb8c093b 3642static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3643{
bb8c093b
CH		 3644 struct iwl3945_priv *priv =
3645 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3646 struct sk_buff *beacon;
3647
3648 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
3649 beacon = ieee80211_beacon_get(priv->hw, priv->interface_id, NULL);
3650
3651 if (!beacon) {
3652 IWL_ERROR("update beacon failed\n");
3653 return;
3654 }
3655
3656 mutex_lock(&priv->mutex);
3657 /* new beacon skb is allocated every time; dispose previous.*/
3658 if (priv->ibss_beacon)
3659 dev_kfree_skb(priv->ibss_beacon);
3660
3661 priv->ibss_beacon = beacon;
3662 mutex_unlock(&priv->mutex);
3663
bb8c093b 3664 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3665}
3666
bb8c093b
CH		 3667static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3668 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3669{
c8b0e6e1 3670#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3671 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3672 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3673 u8 rate = beacon->beacon_notify_hdr.rate;
3674
3675 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3676 "tsf %d %d rate %d\n",
3677 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3678 beacon->beacon_notify_hdr.failure_frame,
3679 le32_to_cpu(beacon->ibss_mgr_status),
3680 le32_to_cpu(beacon->high_tsf),
3681 le32_to_cpu(beacon->low_tsf), rate);
3682#endif
3683
3684 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3685 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3686 queue_work(priv->workqueue, &priv->beacon_update);
3687}
3688
3689/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3690static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3691 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3692{
c8b0e6e1 3693#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3694 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3695 struct iwl3945_scanreq_notification *notif =
3696 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3697
3698 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3699#endif
3700}
3701
3702/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3703static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3704 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3705{
bb8c093b
CH		 3706 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3707 struct iwl3945_scanstart_notification *notif =
3708 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3709 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3710 IWL_DEBUG_SCAN("Scan start: "
3711 "%d [802.11%s] "
3712 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3713 notif->channel,
3714 notif->band ? "bg" : "a",
3715 notif->tsf_high,
3716 notif->tsf_low, notif->status, notif->beacon_timer);
3717}
3718
3719/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3720static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3721 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3722{
bb8c093b
CH		 3723 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3724 struct iwl3945_scanresults_notification *notif =
3725 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3726
3727 IWL_DEBUG_SCAN("Scan ch.res: "
3728 "%d [802.11%s] "
3729 "(TSF: 0x%08X:%08X) - %d "
3730 "elapsed=%lu usec (%dms since last)\n",
3731 notif->channel,
3732 notif->band ? "bg" : "a",
3733 le32_to_cpu(notif->tsf_high),
3734 le32_to_cpu(notif->tsf_low),
3735 le32_to_cpu(notif->statistics[0]),
3736 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3737 jiffies_to_msecs(elapsed_jiffies
3738 (priv->last_scan_jiffies, jiffies)));
3739
3740 priv->last_scan_jiffies = jiffies;
7878a5a4 3741 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3742}
3743
3744/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3745static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3746 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3747{
bb8c093b
CH		 3748 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3749 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3750
3751 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3752 scan_notif->scanned_channels,
3753 scan_notif->tsf_low,
3754 scan_notif->tsf_high, scan_notif->status);
3755
3756 /* The HW is no longer scanning */
3757 clear_bit(STATUS_SCAN_HW, &priv->status);
3758
3759 /* The scan completion notification came in, so kill that timer... */
3760 cancel_delayed_work(&priv->scan_check);
3761
3762 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3763 (priv->scan_bands == 2) ? "2.4" : "5.2",
3764 jiffies_to_msecs(elapsed_jiffies
3765 (priv->scan_pass_start, jiffies)));
3766
3767 /* Remove this scanned band from the list
3768 * of pending bands to scan */
3769 priv->scan_bands--;
3770
3771 /* If a request to abort was given, or the scan did not succeed
3772 * then we reset the scan state machine and terminate,
3773 * re-queuing another scan if one has been requested */
3774 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3775 IWL_DEBUG_INFO("Aborted scan completed.\n");
3776 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3777 } else {
3778 /* If there are more bands on this scan pass reschedule */
3779 if (priv->scan_bands > 0)
3780 goto reschedule;
3781 }
3782
3783 priv->last_scan_jiffies = jiffies;
7878a5a4 3784 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3785 IWL_DEBUG_INFO("Setting scan to off\n");
3786
3787 clear_bit(STATUS_SCANNING, &priv->status);
3788
3789 IWL_DEBUG_INFO("Scan took %dms\n",
3790 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3791
3792 queue_work(priv->workqueue, &priv->scan_completed);
3793
3794 return;
3795
3796reschedule:
3797 priv->scan_pass_start = jiffies;
3798 queue_work(priv->workqueue, &priv->request_scan);
3799}
3800
3801/* Handle notification from uCode that card's power state is changing
3802 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3803static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3804 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3805{
bb8c093b 3806 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3807 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3808 unsigned long status = priv->status;
3809
3810 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3811 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3812 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3813
bb8c093b 3814 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3815 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3816
3817 if (flags & HW_CARD_DISABLED)
3818 set_bit(STATUS_RF_KILL_HW, &priv->status);
3819 else
3820 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3821
3822
3823 if (flags & SW_CARD_DISABLED)
3824 set_bit(STATUS_RF_KILL_SW, &priv->status);
3825 else
3826 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3827
bb8c093b 3828 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3829
3830 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3831 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3832 (test_bit(STATUS_RF_KILL_SW, &status) !=
3833 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3834 queue_work(priv->workqueue, &priv->rf_kill);
3835 else
3836 wake_up_interruptible(&priv->wait_command_queue);
3837}
3838
3839/**
bb8c093b 3840 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3841 *
3842 * Setup the RX handlers for each of the reply types sent from the uCode
3843 * to the host.
3844 *
3845 * This function chains into the hardware specific files for them to setup
3846 * any hardware specific handlers as well.
3847 */
bb8c093b 3848static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3849{
bb8c093b
CH		 3850 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3851 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3852 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3853 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3854 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3855 iwl3945_rx_spectrum_measure_notif;
3856 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3857 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3858 iwl3945_rx_pm_debug_statistics_notif;
3859 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3860
9fbab516
BC		 3861 /*
3862 * The same handler is used for both the REPLY to a discrete
3863 * statistics request from the host as well as for the periodic
3864 * statistics notifications (after received beacons) from the uCode.
b481de9c 3865 */
bb8c093b
CH		 3866 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3867 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3868
bb8c093b
CH		 3869 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3870 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3871 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3872 iwl3945_rx_scan_results_notif;
b481de9c 3873 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3874 iwl3945_rx_scan_complete_notif;
3875 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
3876 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c 3877
9fbab516 3878 /* Set up hardware specific Rx handlers */
bb8c093b 3879 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3880}
3881
3882/**
bb8c093b 3883 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3884 * @rxb: Rx buffer to reclaim
3885 *
3886 * If an Rx buffer has an async callback associated with it the callback
3887 * will be executed. The attached skb (if present) will only be freed
3888 * if the callback returns 1
3889 */
bb8c093b
CH		 3890static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3891 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3892{
bb8c093b 3893 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3894 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3895 int txq_id = SEQ_TO_QUEUE(sequence);
3896 int index = SEQ_TO_INDEX(sequence);
3897 int huge = sequence & SEQ_HUGE_FRAME;
3898 int cmd_index;
bb8c093b 3899 struct iwl3945_cmd *cmd;
b481de9c
ZY		 3900
3901 /* If a Tx command is being handled and it isn't in the actual
3902 * command queue then there a command routing bug has been introduced
3903 * in the queue management code. */
3904 if (txq_id != IWL_CMD_QUEUE_NUM)
3905 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
3906 txq_id, pkt->hdr.cmd);
3907 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3908
3909 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3910 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3911
3912 /* Input error checking is done when commands are added to queue. */
3913 if (cmd->meta.flags & CMD_WANT_SKB) {
3914 cmd->meta.source->u.skb = rxb->skb;
3915 rxb->skb = NULL;
3916 } else if (cmd->meta.u.callback &&
3917 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3918 rxb->skb = NULL;
3919
bb8c093b 3920 iwl3945_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3921
3922 if (!(cmd->meta.flags & CMD_ASYNC)) {
3923 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3924 wake_up_interruptible(&priv->wait_command_queue);
3925 }
3926}
3927
3928/************************** RX-FUNCTIONS ****************************/
3929/*
3930 * Rx theory of operation
3931 *
3932 * The host allocates 32 DMA target addresses and passes the host address
3933 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3934 * 0 to 31
3935 *
3936 * Rx Queue Indexes
3937 * The host/firmware share two index registers for managing the Rx buffers.
3938 *
3939 * The READ index maps to the first position that the firmware may be writing
3940 * to -- the driver can read up to (but not including) this position and get
3941 * good data.
3942 * The READ index is managed by the firmware once the card is enabled.
3943 *
3944 * The WRITE index maps to the last position the driver has read from -- the
3945 * position preceding WRITE is the last slot the firmware can place a packet.
3946 *
3947 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3948 * WRITE = READ.
3949 *
9fbab516 3950 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3951 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3952 *
9fbab516 3953 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3954 * and fire the RX interrupt. The driver can then query the READ index and
3955 * process as many packets as possible, moving the WRITE index forward as it
3956 * resets the Rx queue buffers with new memory.
3957 *
3958 * The management in the driver is as follows:
3959 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3960 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3961 * to replenish the iwl->rxq->rx_free.
bb8c093b 3962 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3963 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3964 * 'processed' and 'read' driver indexes as well)
3965 * + A received packet is processed and handed to the kernel network stack,
3966 * detached from the iwl->rxq. The driver 'processed' index is updated.
3967 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3968 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3969 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3970 * were enough free buffers and RX_STALLED is set it is cleared.
3971 *
3972 *
3973 * Driver sequence:
3974 *
9fbab516
BC		 3975 * iwl3945_rx_queue_alloc() Allocates rx_free
3976 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3977 * iwl3945_rx_queue_restock
9fbab516 3978 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3979 * queue, updates firmware pointers, and updates
3980 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3981 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3982 *
3983 * -- enable interrupts --
9fbab516 3984 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3985 * READ INDEX, detaching the SKB from the pool.
3986 * Moves the packet buffer from queue to rx_used.
bb8c093b 3987 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3988 * slots.
3989 * ...
3990 *
3991 */
3992
3993/**
bb8c093b 3994 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3995 */
bb8c093b 3996static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3997{
3998 int s = q->read - q->write;
3999 if (s <= 0)
4000 s += RX_QUEUE_SIZE;
4001 /* keep some buffer to not confuse full and empty queue */
4002 s -= 2;
4003 if (s < 0)
4004 s = 0;
4005 return s;
4006}
4007
4008/**
bb8c093b 4009 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 4010 */
bb8c093b 4011int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 4012{
4013 u32 reg = 0;
4014 int rc = 0;
4015 unsigned long flags;
4016
4017 spin_lock_irqsave(&q->lock, flags);
4018
4019 if (q->need_update == 0)
4020 goto exit_unlock;
4021
6440adb5 4022 /* If power-saving is in use, make sure device is awake */
b481de9c 4023 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 4024 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4025
4026 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 4027 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4028 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4029 goto exit_unlock;
4030 }
4031
bb8c093b 4032 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4033 if (rc)
4034 goto exit_unlock;
4035
6440adb5 4036 /* Device expects a multiple of 8 */
bb8c093b 4037 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 4038 q->write & ~0x7);
bb8c093b 4039 iwl3945_release_nic_access(priv);
6440adb5
BC		 4040
4041 /* Else device is assumed to be awake */
b481de9c 4042 } else
6440adb5 4043 /* Device expects a multiple of 8 */
bb8c093b 4044 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 4045
4046
4047 q->need_update = 0;
4048
4049 exit_unlock:
4050 spin_unlock_irqrestore(&q->lock, flags);
4051 return rc;
4052}
4053
4054/**
9fbab516 4055 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 4056 */
bb8c093b 4057static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 4058 dma_addr_t dma_addr)
4059{
4060 return cpu_to_le32((u32)dma_addr);
4061}
4062
4063/**
bb8c093b 4064 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 4065 *
9fbab516 4066 * If there are slots in the RX queue that need to be restocked,
b481de9c 4067 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 4068 * as we can, pulling from rx_free.
b481de9c
ZY		 4069 *
4070 * This moves the 'write' index forward to catch up with 'processed', and
4071 * also updates the memory address in the firmware to reference the new
4072 * target buffer.
4073 */
bb8c093b 4074static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 4075{
bb8c093b 4076 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 4077 struct list_head *element;
bb8c093b 4078 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 4079 unsigned long flags;
4080 int write, rc;
4081
4082 spin_lock_irqsave(&rxq->lock, flags);
4083 write = rxq->write & ~0x7;
bb8c093b 4084 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 4085 /* Get next free Rx buffer, remove from free list */
b481de9c 4086 element = rxq->rx_free.next;
bb8c093b 4087 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 4088 list_del(element);
6440adb5
BC		 4089
4090 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 4091 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 4092 rxq->queue[rxq->write] = rxb;
4093 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
4094 rxq->free_count--;
4095 }
4096 spin_unlock_irqrestore(&rxq->lock, flags);
4097 /* If the pre-allocated buffer pool is dropping low, schedule to
4098 * refill it */
4099 if (rxq->free_count <= RX_LOW_WATERMARK)
4100 queue_work(priv->workqueue, &priv->rx_replenish);
4101
4102
6440adb5
BC		 4103 /* If we've added more space for the firmware to place data, tell it.
4104 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 4105 if ((write != (rxq->write & ~0x7))
4106 || (abs(rxq->write - rxq->read) > 7)) {
4107 spin_lock_irqsave(&rxq->lock, flags);
4108 rxq->need_update = 1;
4109 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 4110 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 4111 if (rc)
4112 return rc;
4113 }
4114
4115 return 0;
4116}
4117
4118/**
bb8c093b 4119 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 4120 *
4121 * When moving to rx_free an SKB is allocated for the slot.
4122 *
bb8c093b 4123 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 4124 * This is called as a scheduled work item (except for during initialization)
b481de9c 4125 */
bb8c093b 4126void iwl3945_rx_replenish(void *data)
b481de9c 4127{
bb8c093b
CH		 4128 struct iwl3945_priv *priv = data;
4129 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 4130 struct list_head *element;
bb8c093b 4131 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 4132 unsigned long flags;
4133 spin_lock_irqsave(&rxq->lock, flags);
4134 while (!list_empty(&rxq->rx_used)) {
4135 element = rxq->rx_used.next;
bb8c093b 4136 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
BC		 4137
4138 /* Alloc a new receive buffer */
b481de9c
ZY		 4139 rxb->skb =
4140 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
4141 if (!rxb->skb) {
4142 if (net_ratelimit())
4143 printk(KERN_CRIT DRV_NAME
4144 ": Can not allocate SKB buffers\n");
4145 /* We don't reschedule replenish work here -- we will
4146 * call the restock method and if it still needs
4147 * more buffers it will schedule replenish */
4148 break;
4149 }
4150 priv->alloc_rxb_skb++;
4151 list_del(element);
6440adb5
BC		 4152
4153 /* Get physical address of RB/SKB */
b481de9c
ZY		 4154 rxb->dma_addr =
4155 pci_map_single(priv->pci_dev, rxb->skb->data,
4156 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4157 list_add_tail(&rxb->list, &rxq->rx_free);
4158 rxq->free_count++;
4159 }
4160 spin_unlock_irqrestore(&rxq->lock, flags);
4161
4162 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4163 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4164 spin_unlock_irqrestore(&priv->lock, flags);
4165}
4166
4167/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 4168 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 4169 * This free routine walks the list of POOL entries and if SKB is set to
4170 * non NULL it is unmapped and freed
4171 */
bb8c093b 4172static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 4173{
4174 int i;
4175 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
4176 if (rxq->pool[i].skb != NULL) {
4177 pci_unmap_single(priv->pci_dev,
4178 rxq->pool[i].dma_addr,
4179 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4180 dev_kfree_skb(rxq->pool[i].skb);
4181 }
4182 }
4183
4184 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4185 rxq->dma_addr);
4186 rxq->bd = NULL;
4187}
4188
bb8c093b 4189int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 4190{
bb8c093b 4191 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4192 struct pci_dev *dev = priv->pci_dev;
4193 int i;
4194
4195 spin_lock_init(&rxq->lock);
4196 INIT_LIST_HEAD(&rxq->rx_free);
4197 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
BC		 4198
4199 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 4200 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
4201 if (!rxq->bd)
4202 return -ENOMEM;
6440adb5 4203
b481de9c
ZY		 4204 /* Fill the rx_used queue with _all_ of the Rx buffers */
4205 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
4206 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 4207
b481de9c
ZY		 4208 /* Set us so that we have processed and used all buffers, but have
4209 * not restocked the Rx queue with fresh buffers */
4210 rxq->read = rxq->write = 0;
4211 rxq->free_count = 0;
4212 rxq->need_update = 0;
4213 return 0;
4214}
4215
bb8c093b 4216void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 4217{
4218 unsigned long flags;
4219 int i;
4220 spin_lock_irqsave(&rxq->lock, flags);
4221 INIT_LIST_HEAD(&rxq->rx_free);
4222 INIT_LIST_HEAD(&rxq->rx_used);
4223 /* Fill the rx_used queue with _all_ of the Rx buffers */
4224 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
4225 /* In the reset function, these buffers may have been allocated
4226 * to an SKB, so we need to unmap and free potential storage */
4227 if (rxq->pool[i].skb != NULL) {
4228 pci_unmap_single(priv->pci_dev,
4229 rxq->pool[i].dma_addr,
4230 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4231 priv->alloc_rxb_skb--;
4232 dev_kfree_skb(rxq->pool[i].skb);
4233 rxq->pool[i].skb = NULL;
4234 }
4235 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4236 }
4237
4238 /* Set us so that we have processed and used all buffers, but have
4239 * not restocked the Rx queue with fresh buffers */
4240 rxq->read = rxq->write = 0;
4241 rxq->free_count = 0;
4242 spin_unlock_irqrestore(&rxq->lock, flags);
4243}
4244
4245/* Convert linear signal-to-noise ratio into dB */
4246static u8 ratio2dB[100] = {
4247/* 0 1 2 3 4 5 6 7 8 9 */
4248 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4249 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4250 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4251 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4252 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4253 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4254 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4255 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4256 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4257 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4258};
4259
4260/* Calculates a relative dB value from a ratio of linear
4261 * (i.e. not dB) signal levels.
4262 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4263int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c
ZY		 4264{
4265 /* Anything above 1000:1 just report as 60 dB */
4266 if (sig_ratio > 1000)
4267 return 60;
4268
4269 /* Above 100:1, divide by 10 and use table,
4270 * add 20 dB to make up for divide by 10 */
4271 if (sig_ratio > 100)
4272 return (20 + (int)ratio2dB[sig_ratio/10]);
4273
4274 /* We shouldn't see this */
4275 if (sig_ratio < 1)
4276 return 0;
4277
4278 /* Use table for ratios 1:1 - 99:1 */
4279 return (int)ratio2dB[sig_ratio];
4280}
4281
4282#define PERFECT_RSSI (-20) /* dBm */
4283#define WORST_RSSI (-95) /* dBm */
4284#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4285
4286/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4287 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4288 * about formulas used below. */
bb8c093b 4289int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 4290{
4291 int sig_qual;
4292 int degradation = PERFECT_RSSI - rssi_dbm;
4293
4294 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4295 * as indicator; formula is (signal dbm - noise dbm).
4296 * SNR at or above 40 is a great signal (100%).
4297 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4298 * Weakest usable signal is usually 10 - 15 dB SNR. */
4299 if (noise_dbm) {
4300 if (rssi_dbm - noise_dbm >= 40)
4301 return 100;
4302 else if (rssi_dbm < noise_dbm)
4303 return 0;
4304 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4305
4306 /* Else use just the signal level.
4307 * This formula is a least squares fit of data points collected and
4308 * compared with a reference system that had a percentage (%) display
4309 * for signal quality. */
4310 } else
4311 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4312 (15 * RSSI_RANGE + 62 * degradation)) /
4313 (RSSI_RANGE * RSSI_RANGE);
4314
4315 if (sig_qual > 100)
4316 sig_qual = 100;
4317 else if (sig_qual < 1)
4318 sig_qual = 0;
4319
4320 return sig_qual;
4321}
4322
4323/**
9fbab516 4324 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 4325 *
4326 * Uses the priv->rx_handlers callback function array to invoke
4327 * the appropriate handlers, including command responses,
4328 * frame-received notifications, and other notifications.
4329 */
bb8c093b 4330static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 4331{
bb8c093b
CH		 4332 struct iwl3945_rx_mem_buffer *rxb;
4333 struct iwl3945_rx_packet *pkt;
4334 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4335 u32 r, i;
4336 int reclaim;
4337 unsigned long flags;
4338
6440adb5
BC		 4339 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4340 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4341 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 4342 i = rxq->read;
4343
4344 /* Rx interrupt, but nothing sent from uCode */
4345 if (i == r)
4346 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4347
4348 while (i != r) {
4349 rxb = rxq->queue[i];
4350
9fbab516 4351 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4352 * then a bug has been introduced in the queue refilling
4353 * routines -- catch it here */
4354 BUG_ON(rxb == NULL);
4355
4356 rxq->queue[i] = NULL;
4357
4358 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4359 IWL_RX_BUF_SIZE,
4360 PCI_DMA_FROMDEVICE);
bb8c093b 4361 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4362
4363 /* Reclaim a command buffer only if this packet is a response
4364 * to a (driver-originated) command.
4365 * If the packet (e.g. Rx frame) originated from uCode,
4366 * there is no command buffer to reclaim.
4367 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4368 * but apparently a few don't get set; catch them here. */
4369 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4370 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4371 (pkt->hdr.cmd != REPLY_TX);
4372
4373 /* Based on type of command response or notification,
4374 * handle those that need handling via function in
bb8c093b 4375 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4376 if (priv->rx_handlers[pkt->hdr.cmd]) {
4377 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4378 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4379 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4380 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4381 } else {
4382 /* No handling needed */
4383 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4384 "r %d i %d No handler needed for %s, 0x%02x\n",
4385 r, i, get_cmd_string(pkt->hdr.cmd),
4386 pkt->hdr.cmd);
4387 }
4388
4389 if (reclaim) {
9fbab516
BC		 4390 /* Invoke any callbacks, transfer the skb to caller, and
4391 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4392 * as we reclaim the driver command queue */
4393 if (rxb && rxb->skb)
bb8c093b 4394 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4395 else
4396 IWL_WARNING("Claim null rxb?\n");
4397 }
4398
4399 /* For now we just don't re-use anything. We can tweak this
4400 * later to try and re-use notification packets and SKBs that
4401 * fail to Rx correctly */
4402 if (rxb->skb != NULL) {
4403 priv->alloc_rxb_skb--;
4404 dev_kfree_skb_any(rxb->skb);
4405 rxb->skb = NULL;
4406 }
4407
4408 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4409 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4410 spin_lock_irqsave(&rxq->lock, flags);
4411 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4412 spin_unlock_irqrestore(&rxq->lock, flags);
4413 i = (i + 1) & RX_QUEUE_MASK;
4414 }
4415
4416 /* Backtrack one entry */
4417 priv->rxq.read = i;
bb8c093b 4418 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4419}
4420
6440adb5
BC		 4421/**
4422 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4423 */
bb8c093b
CH		 4424static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4425 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4426{
4427 u32 reg = 0;
4428 int rc = 0;
4429 int txq_id = txq->q.id;
4430
4431 if (txq->need_update == 0)
4432 return rc;
4433
4434 /* if we're trying to save power */
4435 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4436 /* wake up nic if it's powered down ...
4437 * uCode will wake up, and interrupt us again, so next
4438 * time we'll skip this part. */
bb8c093b 4439 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4440
4441 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4442 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4443 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4444 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4445 return rc;
4446 }
4447
4448 /* restore this queue's parameters in nic hardware. */
bb8c093b 4449 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4450 if (rc)
4451 return rc;
bb8c093b 4452 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4453 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4454 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4455
4456 /* else not in power-save mode, uCode will never sleep when we're
4457 * trying to tx (during RFKILL, we're not trying to tx). */
4458 } else
bb8c093b 4459 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4460 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4461
4462 txq->need_update = 0;
4463
4464 return rc;
4465}
4466
c8b0e6e1 4467#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4468static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4469{
0795af57
JP		 4470 DECLARE_MAC_BUF(mac);
4471
b481de9c 4472 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4473 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4474 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4475 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4476 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4477 le32_to_cpu(rxon->filter_flags));
4478 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4479 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4480 rxon->ofdm_basic_rates);
4481 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4482 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4483 print_mac(mac, rxon->node_addr));
4484 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4485 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4486 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4487}
4488#endif
4489
bb8c093b 4490static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4491{
4492 IWL_DEBUG_ISR("Enabling interrupts\n");
4493 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4494 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4495}
4496
bb8c093b 4497static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4498{
4499 clear_bit(STATUS_INT_ENABLED, &priv->status);
4500
4501 /* disable interrupts from uCode/NIC to host */
bb8c093b 4502 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4503
4504 /* acknowledge/clear/reset any interrupts still pending
4505 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4506 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4507 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4508 IWL_DEBUG_ISR("Disabled interrupts\n");
4509}
4510
4511static const char *desc_lookup(int i)
4512{
4513 switch (i) {
4514 case 1:
4515 return "FAIL";
4516 case 2:
4517 return "BAD_PARAM";
4518 case 3:
4519 return "BAD_CHECKSUM";
4520 case 4:
4521 return "NMI_INTERRUPT";
4522 case 5:
4523 return "SYSASSERT";
4524 case 6:
4525 return "FATAL_ERROR";
4526 }
4527
4528 return "UNKNOWN";
4529}
4530
4531#define ERROR_START_OFFSET (1 * sizeof(u32))
4532#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4533
bb8c093b 4534static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4535{
4536 u32 i;
4537 u32 desc, time, count, base, data1;
4538 u32 blink1, blink2, ilink1, ilink2;
4539 int rc;
4540
4541 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4542
bb8c093b 4543 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4544 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4545 return;
4546 }
4547
bb8c093b 4548 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4549 if (rc) {
4550 IWL_WARNING("Can not read from adapter at this time.\n");
4551 return;
4552 }
4553
bb8c093b 4554 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4555
4556 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4557 IWL_ERROR("Start IWL Error Log Dump:\n");
4558 IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
4559 priv->status, priv->config, count);
4560 }
4561
4562 IWL_ERROR("Desc Time asrtPC blink2 "
4563 "ilink1 nmiPC Line\n");
4564 for (i = ERROR_START_OFFSET;
4565 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4566 i += ERROR_ELEM_SIZE) {
bb8c093b 4567 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4568 time =
bb8c093b 4569 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4570 blink1 =
bb8c093b 4571 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4572 blink2 =
bb8c093b 4573 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4574 ilink1 =
bb8c093b 4575 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4576 ilink2 =
bb8c093b 4577 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4578 data1 =
bb8c093b 4579 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4580
4581 IWL_ERROR
4582 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4583 desc_lookup(desc), desc, time, blink1, blink2,
4584 ilink1, ilink2, data1);
4585 }
4586
bb8c093b 4587 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4588
4589}
4590
f58177b9 4591#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4592
4593/**
bb8c093b 4594 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4595 *
bb8c093b 4596 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4597 */
bb8c093b 4598static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4599 u32 num_events, u32 mode)
4600{
4601 u32 i;
4602 u32 base; /* SRAM byte address of event log header */
4603 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4604 u32 ptr; /* SRAM byte address of log data */
4605 u32 ev, time, data; /* event log data */
4606
4607 if (num_events == 0)
4608 return;
4609
4610 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4611
4612 if (mode == 0)
4613 event_size = 2 * sizeof(u32);
4614 else
4615 event_size = 3 * sizeof(u32);
4616
4617 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4618
4619 /* "time" is actually "data" for mode 0 (no timestamp).
4620 * place event id # at far right for easier visual parsing. */
4621 for (i = 0; i < num_events; i++) {
bb8c093b 4622 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4623 ptr += sizeof(u32);
bb8c093b 4624 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4625 ptr += sizeof(u32);
4626 if (mode == 0)
4627 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4628 else {
bb8c093b 4629 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4630 ptr += sizeof(u32);
4631 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4632 }
4633 }
4634}
4635
bb8c093b 4636static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4637{
4638 int rc;
4639 u32 base; /* SRAM byte address of event log header */
4640 u32 capacity; /* event log capacity in # entries */
4641 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4642 u32 num_wraps; /* # times uCode wrapped to top of log */
4643 u32 next_entry; /* index of next entry to be written by uCode */
4644 u32 size; /* # entries that we'll print */
4645
4646 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4647 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4648 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4649 return;
4650 }
4651
bb8c093b 4652 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4653 if (rc) {
4654 IWL_WARNING("Can not read from adapter at this time.\n");
4655 return;
4656 }
4657
4658 /* event log header */
bb8c093b
CH		 4659 capacity = iwl3945_read_targ_mem(priv, base);
4660 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4661 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4662 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4663
4664 size = num_wraps ? capacity : next_entry;
4665
4666 /* bail out if nothing in log */
4667 if (size == 0) {
583fab37 4668 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4669 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4670 return;
4671 }
4672
583fab37 4673 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4674 size, num_wraps);
4675
4676 /* if uCode has wrapped back to top of log, start at the oldest entry,
4677 * i.e the next one that uCode would fill. */
4678 if (num_wraps)
bb8c093b 4679 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4680 capacity - next_entry, mode);
4681
4682 /* (then/else) start at top of log */
bb8c093b 4683 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4684
bb8c093b 4685 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4686}
4687
4688/**
bb8c093b 4689 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4690 */
bb8c093b 4691static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4692{
bb8c093b 4693 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4694 set_bit(STATUS_FW_ERROR, &priv->status);
4695
4696 /* Cancel currently queued command. */
4697 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4698
c8b0e6e1 4699#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4700 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4701 iwl3945_dump_nic_error_log(priv);
4702 iwl3945_dump_nic_event_log(priv);
4703 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4704 }
4705#endif
4706
4707 wake_up_interruptible(&priv->wait_command_queue);
4708
4709 /* Keep the restart process from trying to send host
4710 * commands by clearing the INIT status bit */
4711 clear_bit(STATUS_READY, &priv->status);
4712
4713 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4714 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4715 "Restarting adapter due to uCode error.\n");
4716
bb8c093b 4717 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4718 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4719 sizeof(priv->recovery_rxon));
4720 priv->error_recovering = 1;
4721 }
4722 queue_work(priv->workqueue, &priv->restart);
4723 }
4724}
4725
bb8c093b 4726static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4727{
4728 unsigned long flags;
4729
4730 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4731 sizeof(priv->staging_rxon));
4732 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4733 iwl3945_commit_rxon(priv);
b481de9c 4734
bb8c093b 4735 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4736
4737 spin_lock_irqsave(&priv->lock, flags);
4738 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4739 priv->error_recovering = 0;
4740 spin_unlock_irqrestore(&priv->lock, flags);
4741}
4742
bb8c093b 4743static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4744{
4745 u32 inta, handled = 0;
4746 u32 inta_fh;
4747 unsigned long flags;
c8b0e6e1 4748#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4749 u32 inta_mask;
4750#endif
4751
4752 spin_lock_irqsave(&priv->lock, flags);
4753
4754 /* Ack/clear/reset pending uCode interrupts.
4755 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4756 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4757 inta = iwl3945_read32(priv, CSR_INT);
4758 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4759
4760 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4761 * Any new interrupts that happen after this, either while we're
4762 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4763 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4764 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4765
c8b0e6e1 4766#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4767 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4768 /* just for debug */
4769 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4770 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4771 inta, inta_mask, inta_fh);
4772 }
4773#endif
4774
4775 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4776 * atomic, make sure that inta covers all the interrupts that
4777 * we've discovered, even if FH interrupt came in just after
4778 * reading CSR_INT. */
4779 if (inta_fh & CSR_FH_INT_RX_MASK)
4780 inta |= CSR_INT_BIT_FH_RX;
4781 if (inta_fh & CSR_FH_INT_TX_MASK)
4782 inta |= CSR_INT_BIT_FH_TX;
4783
4784 /* Now service all interrupt bits discovered above. */
4785 if (inta & CSR_INT_BIT_HW_ERR) {
4786 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4787
4788 /* Tell the device to stop sending interrupts */
bb8c093b 4789 iwl3945_disable_interrupts(priv);
b481de9c 4790
bb8c093b 4791 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4792
4793 handled |= CSR_INT_BIT_HW_ERR;
4794
4795 spin_unlock_irqrestore(&priv->lock, flags);
4796
4797 return;
4798 }
4799
c8b0e6e1 4800#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4801 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c
ZY		 4802 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4803 if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
4804 IWL_DEBUG_ISR("Microcode started or stopped.\n");
4805
4806 /* Alive notification via Rx interrupt will do the real work */
4807 if (inta & CSR_INT_BIT_ALIVE)
4808 IWL_DEBUG_ISR("Alive interrupt\n");
4809 }
4810#endif
4811 /* Safely ignore these bits for debug checks below */
4812 inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
4813
4814 /* HW RF KILL switch toggled (4965 only) */
4815 if (inta & CSR_INT_BIT_RF_KILL) {
4816 int hw_rf_kill = 0;
bb8c093b 4817 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4818 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4819 hw_rf_kill = 1;
4820
4821 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4822 "RF_KILL bit toggled to %s.\n",
4823 hw_rf_kill ? "disable radio":"enable radio");
4824
4825 /* Queue restart only if RF_KILL switch was set to "kill"
4826 * when we loaded driver, and is now set to "enable".
4827 * After we're Alive, RF_KILL gets handled by
4828 * iwl_rx_card_state_notif() */
53e49093
ZY		 4829 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4830 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4831 queue_work(priv->workqueue, &priv->restart);
53e49093 4832 }
b481de9c
ZY		 4833
4834 handled |= CSR_INT_BIT_RF_KILL;
4835 }
4836
4837 /* Chip got too hot and stopped itself (4965 only) */
4838 if (inta & CSR_INT_BIT_CT_KILL) {
4839 IWL_ERROR("Microcode CT kill error detected.\n");
4840 handled |= CSR_INT_BIT_CT_KILL;
4841 }
4842
4843 /* Error detected by uCode */
4844 if (inta & CSR_INT_BIT_SW_ERR) {
4845 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4846 inta);
bb8c093b 4847 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4848 handled |= CSR_INT_BIT_SW_ERR;
4849 }
4850
4851 /* uCode wakes up after power-down sleep */
4852 if (inta & CSR_INT_BIT_WAKEUP) {
4853 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4854 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4855 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4856 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4857 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4858 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4859 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4860 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4861
4862 handled |= CSR_INT_BIT_WAKEUP;
4863 }
4864
4865 /* All uCode command responses, including Tx command responses,
4866 * Rx "responses" (frame-received notification), and other
4867 * notifications from uCode come through here*/
4868 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4869 iwl3945_rx_handle(priv);
b481de9c
ZY		 4870 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4871 }
4872
4873 if (inta & CSR_INT_BIT_FH_TX) {
4874 IWL_DEBUG_ISR("Tx interrupt\n");
4875
bb8c093b
CH		 4876 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4877 if (!iwl3945_grab_nic_access(priv)) {
4878 iwl3945_write_direct32(priv,
b481de9c
ZY		 4879 FH_TCSR_CREDIT
4880 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4881 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4882 }
4883 handled |= CSR_INT_BIT_FH_TX;
4884 }
4885
4886 if (inta & ~handled)
4887 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4888
4889 if (inta & ~CSR_INI_SET_MASK) {
4890 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4891 inta & ~CSR_INI_SET_MASK);
4892 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4893 }
4894
4895 /* Re-enable all interrupts */
bb8c093b 4896 iwl3945_enable_interrupts(priv);
b481de9c 4897
c8b0e6e1 4898#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4899 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4900 inta = iwl3945_read32(priv, CSR_INT);
4901 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4902 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4903 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4904 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4905 }
4906#endif
4907 spin_unlock_irqrestore(&priv->lock, flags);
4908}
4909
bb8c093b 4910static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4911{
bb8c093b 4912 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4913 u32 inta, inta_mask;
4914 u32 inta_fh;
4915 if (!priv)
4916 return IRQ_NONE;
4917
4918 spin_lock(&priv->lock);
4919
4920 /* Disable (but don't clear!) interrupts here to avoid
4921 * back-to-back ISRs and sporadic interrupts from our NIC.
4922 * If we have something to service, the tasklet will re-enable ints.
4923 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4924 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4925 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4926
4927 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4928 inta = iwl3945_read32(priv, CSR_INT);
4929 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4930
4931 /* Ignore interrupt if there's nothing in NIC to service.
4932 * This may be due to IRQ shared with another device,
4933 * or due to sporadic interrupts thrown from our NIC. */
4934 if (!inta && !inta_fh) {
4935 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4936 goto none;
4937 }
4938
4939 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4940 /* Hardware disappeared */
4941 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4942 goto unplugged;
b481de9c
ZY		 4943 }
4944
4945 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4946 inta, inta_mask, inta_fh);
4947
bb8c093b 4948 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
b481de9c 4949 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4950unplugged:
b481de9c
ZY		 4951 spin_unlock(&priv->lock);
4952
4953 return IRQ_HANDLED;
4954
4955 none:
4956 /* re-enable interrupts here since we don't have anything to service. */
bb8c093b 4957 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4958 spin_unlock(&priv->lock);
4959 return IRQ_NONE;
4960}
4961
4962/************************** EEPROM BANDS ****************************
4963 *
bb8c093b 4964 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4965 * EEPROM contents to the specific channel number supported for each
4966 * band.
4967 *
bb8c093b 4968 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4969 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4970 * The specific geography and calibration information for that channel
4971 * is contained in the eeprom map itself.
4972 *
4973 * During init, we copy the eeprom information and channel map
4974 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4975 *
4976 * channel_map_24/52 provides the index in the channel_info array for a
4977 * given channel. We have to have two separate maps as there is channel
4978 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4979 * band_2
4980 *
4981 * A value of 0xff stored in the channel_map indicates that the channel
4982 * is not supported by the hardware at all.
4983 *
4984 * A value of 0xfe in the channel_map indicates that the channel is not
4985 * valid for Tx with the current hardware. This means that
4986 * while the system can tune and receive on a given channel, it may not
4987 * be able to associate or transmit any frames on that
4988 * channel. There is no corresponding channel information for that
4989 * entry.
4990 *
4991 *********************************************************************/
4992
4993/* 2.4 GHz */
bb8c093b 4994static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4995 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4996};
4997
4998/* 5.2 GHz bands */
9fbab516 4999static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 5000 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
5001};
5002
9fbab516 5003static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 5004 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
5005};
5006
bb8c093b 5007static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 5008 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
5009};
5010
bb8c093b 5011static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 5012 145, 149, 153, 157, 161, 165
5013};
5014
bb8c093b 5015static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 5016 int *eeprom_ch_count,
bb8c093b 5017 const struct iwl3945_eeprom_channel
b481de9c
ZY		 5018 **eeprom_ch_info,
5019 const u8 **eeprom_ch_index)
5020{
5021 switch (band) {
5022 case 1: /* 2.4GHz band */
bb8c093b 5023 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 5024 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 5025 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 5026 break;
9fbab516 5027 case 2: /* 4.9GHz band */
bb8c093b 5028 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 5029 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 5030 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 5031 break;
5032 case 3: /* 5.2GHz band */
bb8c093b 5033 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 5034 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 5035 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 5036 break;
9fbab516 5037 case 4: /* 5.5GHz band */
bb8c093b 5038 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 5039 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 5040 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 5041 break;
9fbab516 5042 case 5: /* 5.7GHz band */
bb8c093b 5043 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 5044 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 5045 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 5046 break;
5047 default:
5048 BUG();
5049 return;
5050 }
5051}
5052
6440adb5
BC		 5053/**
5054 * iwl3945_get_channel_info - Find driver's private channel info
5055 *
5056 * Based on band and channel number.
5057 */
bb8c093b 5058const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
b481de9c
ZY		 5059 int phymode, u16 channel)
5060{
5061 int i;
5062
5063 switch (phymode) {
5064 case MODE_IEEE80211A:
5065 for (i = 14; i < priv->channel_count; i++) {
5066 if (priv->channel_info[i].channel == channel)
5067 return &priv->channel_info[i];
5068 }
5069 break;
5070
5071 case MODE_IEEE80211B:
5072 case MODE_IEEE80211G:
5073 if (channel >= 1 && channel <= 14)
5074 return &priv->channel_info[channel - 1];
5075 break;
5076
5077 }
5078
5079 return NULL;
5080}
5081
5082#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
5083 ? # x " " : "")
5084
6440adb5
BC		 5085/**
5086 * iwl3945_init_channel_map - Set up driver's info for all possible channels
5087 */
bb8c093b 5088static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 5089{
5090 int eeprom_ch_count = 0;
5091 const u8 *eeprom_ch_index = NULL;
bb8c093b 5092 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 5093 int band, ch;
bb8c093b 5094 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 5095
5096 if (priv->channel_count) {
5097 IWL_DEBUG_INFO("Channel map already initialized.\n");
5098 return 0;
5099 }
5100
5101 if (priv->eeprom.version < 0x2f) {
5102 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
5103 priv->eeprom.version);
5104 return -EINVAL;
5105 }
5106
5107 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
5108
5109 priv->channel_count =
bb8c093b
CH		 5110 ARRAY_SIZE(iwl3945_eeprom_band_1) +
5111 ARRAY_SIZE(iwl3945_eeprom_band_2) +
5112 ARRAY_SIZE(iwl3945_eeprom_band_3) +
5113 ARRAY_SIZE(iwl3945_eeprom_band_4) +
5114 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 5115
5116 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
5117
bb8c093b 5118 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 5119 priv->channel_count, GFP_KERNEL);
5120 if (!priv->channel_info) {
5121 IWL_ERROR("Could not allocate channel_info\n");
5122 priv->channel_count = 0;
5123 return -ENOMEM;
5124 }
5125
5126 ch_info = priv->channel_info;
5127
5128 /* Loop through the 5 EEPROM bands adding them in order to the
5129 * channel map we maintain (that contains additional information than
5130 * what just in the EEPROM) */
5131 for (band = 1; band <= 5; band++) {
5132
bb8c093b 5133 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 5134 &eeprom_ch_info, &eeprom_ch_index);
5135
5136 /* Loop through each band adding each of the channels */
5137 for (ch = 0; ch < eeprom_ch_count; ch++) {
5138 ch_info->channel = eeprom_ch_index[ch];
5139 ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
5140 MODE_IEEE80211A;
5141
5142 /* permanently store EEPROM's channel regulatory flags
5143 * and max power in channel info database. */
5144 ch_info->eeprom = eeprom_ch_info[ch];
5145
5146 /* Copy the run-time flags so they are there even on
5147 * invalid channels */
5148 ch_info->flags = eeprom_ch_info[ch].flags;
5149
5150 if (!(is_channel_valid(ch_info))) {
5151 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
5152 "No traffic\n",
5153 ch_info->channel,
5154 ch_info->flags,
5155 is_channel_a_band(ch_info) ?
5156 "5.2" : "2.4");
5157 ch_info++;
5158 continue;
5159 }
5160
5161 /* Initialize regulatory-based run-time data */
5162 ch_info->max_power_avg = ch_info->curr_txpow =
5163 eeprom_ch_info[ch].max_power_avg;
5164 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
5165 ch_info->min_power = 0;
5166
5167 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
5168 " %ddBm): Ad-Hoc %ssupported\n",
5169 ch_info->channel,
5170 is_channel_a_band(ch_info) ?
5171 "5.2" : "2.4",
5172 CHECK_AND_PRINT(IBSS),
5173 CHECK_AND_PRINT(ACTIVE),
5174 CHECK_AND_PRINT(RADAR),
5175 CHECK_AND_PRINT(WIDE),
5176 CHECK_AND_PRINT(NARROW),
5177 CHECK_AND_PRINT(DFS),
5178 eeprom_ch_info[ch].flags,
5179 eeprom_ch_info[ch].max_power_avg,
5180 ((eeprom_ch_info[ch].
5181 flags & EEPROM_CHANNEL_IBSS)
5182 && !(eeprom_ch_info[ch].
5183 flags & EEPROM_CHANNEL_RADAR))
5184 ? "" : "not ");
5185
5186 /* Set the user_txpower_limit to the highest power
5187 * supported by any channel */
5188 if (eeprom_ch_info[ch].max_power_avg >
5189 priv->user_txpower_limit)
5190 priv->user_txpower_limit =
5191 eeprom_ch_info[ch].max_power_avg;
5192
5193 ch_info++;
5194 }
5195 }
5196
6440adb5 5197 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 5198 if (iwl3945_txpower_set_from_eeprom(priv))
5199 return -EIO;
5200
5201 return 0;
5202}
5203
5204/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
5205 * sending probe req. This should be set long enough to hear probe responses
5206 * from more than one AP. */
5207#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
5208#define IWL_ACTIVE_DWELL_TIME_52 (10)
5209
5210/* For faster active scanning, scan will move to the next channel if fewer than
5211 * PLCP_QUIET_THRESH packets are heard on this channel within
5212 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
5213 * time if it's a quiet channel (nothing responded to our probe, and there's
5214 * no other traffic).
5215 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
5216#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
5217#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
5218
5219/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
5220 * Must be set longer than active dwell time.
5221 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
5222#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
5223#define IWL_PASSIVE_DWELL_TIME_52 (10)
5224#define IWL_PASSIVE_DWELL_BASE (100)
5225#define IWL_CHANNEL_TUNE_TIME 5
5226
bb8c093b 5227static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, int phymode)
b481de9c
ZY		 5228{
5229 if (phymode == MODE_IEEE80211A)
5230 return IWL_ACTIVE_DWELL_TIME_52;
5231 else
5232 return IWL_ACTIVE_DWELL_TIME_24;
5233}
5234
bb8c093b 5235static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, int phymode)
b481de9c 5236{
bb8c093b 5237 u16 active = iwl3945_get_active_dwell_time(priv, phymode);
b481de9c
ZY		 5238 u16 passive = (phymode != MODE_IEEE80211A) ?
5239 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
5240 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
5241
bb8c093b 5242 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 5243 /* If we're associated, we clamp the maximum passive
5244 * dwell time to be 98% of the beacon interval (minus
5245 * 2 * channel tune time) */
5246 passive = priv->beacon_int;
5247 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
5248 passive = IWL_PASSIVE_DWELL_BASE;
5249 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
5250 }
5251
5252 if (passive <= active)
5253 passive = active + 1;
5254
5255 return passive;
5256}
5257
bb8c093b 5258static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, int phymode,
b481de9c 5259 u8 is_active, u8 direct_mask,
bb8c093b 5260 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 5261{
5262 const struct ieee80211_channel *channels = NULL;
5263 const struct ieee80211_hw_mode *hw_mode;
bb8c093b 5264 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 5265 u16 passive_dwell = 0;
5266 u16 active_dwell = 0;
5267 int added, i;
5268
bb8c093b 5269 hw_mode = iwl3945_get_hw_mode(priv, phymode);
b481de9c
ZY		 5270 if (!hw_mode)
5271 return 0;
5272
5273 channels = hw_mode->channels;
5274
bb8c093b
CH		 5275 active_dwell = iwl3945_get_active_dwell_time(priv, phymode);
5276 passive_dwell = iwl3945_get_passive_dwell_time(priv, phymode);
b481de9c
ZY		 5277
5278 for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
5279 if (channels[i].chan ==
5280 le16_to_cpu(priv->active_rxon.channel)) {
bb8c093b 5281 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 5282 IWL_DEBUG_SCAN
5283 ("Skipping current channel %d\n",
5284 le16_to_cpu(priv->active_rxon.channel));
5285 continue;
5286 }
5287 } else if (priv->only_active_channel)
5288 continue;
5289
5290 scan_ch->channel = channels[i].chan;
5291
bb8c093b 5292 ch_info = iwl3945_get_channel_info(priv, phymode, scan_ch->channel);
b481de9c
ZY		 5293 if (!is_channel_valid(ch_info)) {
5294 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
5295 scan_ch->channel);
5296 continue;
5297 }
5298
5299 if (!is_active || is_channel_passive(ch_info) ||
5300 !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
5301 scan_ch->type = 0; /* passive */
5302 else
5303 scan_ch->type = 1; /* active */
5304
5305 if (scan_ch->type & 1)
5306 scan_ch->type |= (direct_mask << 1);
5307
5308 if (is_channel_narrow(ch_info))
5309 scan_ch->type |= (1 << 7);
5310
5311 scan_ch->active_dwell = cpu_to_le16(active_dwell);
5312 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
5313
9fbab516 5314 /* Set txpower levels to defaults */
b481de9c
ZY		 5315 scan_ch->tpc.dsp_atten = 110;
5316 /* scan_pwr_info->tpc.dsp_atten; */
5317
5318 /*scan_pwr_info->tpc.tx_gain; */
5319 if (phymode == MODE_IEEE80211A)
5320 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5321 else {
5322 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5323 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516
BC		 5324 * power level:
5325 * scan_ch->tpc.tx_gain = ((1<<5) | (2 << 3)) | 3;
b481de9c
ZY		 5326 */
5327 }
5328
5329 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5330 scan_ch->channel,
5331 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5332 (scan_ch->type & 1) ?
5333 active_dwell : passive_dwell);
5334
5335 scan_ch++;
5336 added++;
5337 }
5338
5339 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5340 return added;
5341}
5342
bb8c093b 5343static void iwl3945_reset_channel_flag(struct iwl3945_priv *priv)
b481de9c
ZY		 5344{
5345 int i, j;
5346 for (i = 0; i < 3; i++) {
5347 struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
5348 for (j = 0; j < hw_mode->num_channels; j++)
5349 hw_mode->channels[j].flag = hw_mode->channels[j].val;
5350 }
5351}
5352
bb8c093b 5353static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5354 struct ieee80211_rate *rates)
5355{
5356 int i;
5357
5358 for (i = 0; i < IWL_RATE_COUNT; i++) {
bb8c093b 5359 rates[i].rate = iwl3945_rates[i].ieee * 5;
b481de9c
ZY		 5360 rates[i].val = i; /* Rate scaling will work on indexes */
5361 rates[i].val2 = i;
5362 rates[i].flags = IEEE80211_RATE_SUPPORTED;
5363 /* Only OFDM have the bits-per-symbol set */
5364 if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
5365 rates[i].flags |= IEEE80211_RATE_OFDM;
5366 else {
5367 /*
5368 * If CCK 1M then set rate flag to CCK else CCK_2
5369 * which is CCK | PREAMBLE2
5370 */
bb8c093b 5371 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
b481de9c
ZY		 5372 IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
5373 }
5374
5375 /* Set up which ones are basic rates... */
5376 if (IWL_BASIC_RATES_MASK & (1 << i))
5377 rates[i].flags |= IEEE80211_RATE_BASIC;
5378 }
5379}
5380
5381/**
bb8c093b 5382 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5383 */
bb8c093b 5384static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5385{
bb8c093b 5386 struct iwl3945_channel_info *ch;
b481de9c
ZY		 5387 struct ieee80211_hw_mode *modes;
5388 struct ieee80211_channel *channels;
5389 struct ieee80211_channel *geo_ch;
5390 struct ieee80211_rate *rates;
5391 int i = 0;
5392 enum {
5393 A = 0,
5394 B = 1,
5395 G = 2,
5396 };
5397 int mode_count = 3;
5398
5399 if (priv->modes) {
5400 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5401 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5402 return 0;
5403 }
5404
5405 modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
5406 GFP_KERNEL);
5407 if (!modes)
5408 return -ENOMEM;
5409
5410 channels = kzalloc(sizeof(struct ieee80211_channel) *
5411 priv->channel_count, GFP_KERNEL);
5412 if (!channels) {
5413 kfree(modes);
5414 return -ENOMEM;
5415 }
5416
5417 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
5418 GFP_KERNEL);
5419 if (!rates) {
5420 kfree(modes);
5421 kfree(channels);
5422 return -ENOMEM;
5423 }
5424
5425 /* 0 = 802.11a
5426 * 1 = 802.11b
5427 * 2 = 802.11g
5428 */
5429
5430 /* 5.2GHz channels start after the 2.4GHz channels */
5431 modes[A].mode = MODE_IEEE80211A;
bb8c093b 5432 modes[A].channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
14577f23 5433 modes[A].rates = &rates[4];
b481de9c
ZY		 5434 modes[A].num_rates = 8; /* just OFDM */
5435 modes[A].num_channels = 0;
5436
5437 modes[B].mode = MODE_IEEE80211B;
5438 modes[B].channels = channels;
14577f23 5439 modes[B].rates = rates;
b481de9c
ZY		 5440 modes[B].num_rates = 4; /* just CCK */
5441 modes[B].num_channels = 0;
5442
5443 modes[G].mode = MODE_IEEE80211G;
5444 modes[G].channels = channels;
5445 modes[G].rates = rates;
5446 modes[G].num_rates = 12; /* OFDM & CCK */
5447 modes[G].num_channels = 0;
5448
5449 priv->ieee_channels = channels;
5450 priv->ieee_rates = rates;
5451
bb8c093b 5452 iwl3945_init_hw_rates(priv, rates);
b481de9c
ZY		 5453
5454 for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
5455 ch = &priv->channel_info[i];
5456
5457 if (!is_channel_valid(ch)) {
5458 IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
5459 "skipping.\n",
5460 ch->channel, is_channel_a_band(ch) ?
5461 "5.2" : "2.4");
5462 continue;
5463 }
5464
5465 if (is_channel_a_band(ch))
5466 geo_ch = &modes[A].channels[modes[A].num_channels++];
5467 else {
5468 geo_ch = &modes[B].channels[modes[B].num_channels++];
5469 modes[G].num_channels++;
5470 }
5471
5472 geo_ch->freq = ieee80211chan2mhz(ch->channel);
5473 geo_ch->chan = ch->channel;
5474 geo_ch->power_level = ch->max_power_avg;
5475 geo_ch->antenna_max = 0xff;
5476
5477 if (is_channel_valid(ch)) {
5478 geo_ch->flag = IEEE80211_CHAN_W_SCAN;
5479 if (ch->flags & EEPROM_CHANNEL_IBSS)
5480 geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
5481
5482 if (ch->flags & EEPROM_CHANNEL_ACTIVE)
5483 geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
5484
5485 if (ch->flags & EEPROM_CHANNEL_RADAR)
5486 geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
5487
5488 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5489 priv->max_channel_txpower_limit =
5490 ch->max_power_avg;
5491 }
5492
5493 geo_ch->val = geo_ch->flag;
5494 }
5495
5496 if ((modes[A].num_channels == 0) && priv->is_abg) {
5497 printk(KERN_INFO DRV_NAME
5498 ": Incorrectly detected BG card as ABG. Please send "
5499 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5500 priv->pci_dev->device, priv->pci_dev->subsystem_device);
5501 priv->is_abg = 0;
5502 }
5503
5504 printk(KERN_INFO DRV_NAME
5505 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
5506 modes[G].num_channels, modes[A].num_channels);
5507
5508 /*
5509 * NOTE: We register these in preference of order -- the
5510 * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
5511 * a phymode based on rates or AP capabilities but seems to
5512 * configure it purely on if the channel being configured
5513 * is supported by a mode -- and the first match is taken
5514 */
5515
5516 if (modes[G].num_channels)
5517 ieee80211_register_hwmode(priv->hw, &modes[G]);
5518 if (modes[B].num_channels)
5519 ieee80211_register_hwmode(priv->hw, &modes[B]);
5520 if (modes[A].num_channels)
5521 ieee80211_register_hwmode(priv->hw, &modes[A]);
5522
5523 priv->modes = modes;
5524 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5525
5526 return 0;
5527}
5528
5529/******************************************************************************
5530 *
5531 * uCode download functions
5532 *
5533 ******************************************************************************/
5534
bb8c093b 5535static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c
ZY		 5536{
5537 if (priv->ucode_code.v_addr != NULL) {
5538 pci_free_consistent(priv->pci_dev,
5539 priv->ucode_code.len,
5540 priv->ucode_code.v_addr,
5541 priv->ucode_code.p_addr);
5542 priv->ucode_code.v_addr = NULL;
5543 }
5544 if (priv->ucode_data.v_addr != NULL) {
5545 pci_free_consistent(priv->pci_dev,
5546 priv->ucode_data.len,
5547 priv->ucode_data.v_addr,
5548 priv->ucode_data.p_addr);
5549 priv->ucode_data.v_addr = NULL;
5550 }
5551 if (priv->ucode_data_backup.v_addr != NULL) {
5552 pci_free_consistent(priv->pci_dev,
5553 priv->ucode_data_backup.len,
5554 priv->ucode_data_backup.v_addr,
5555 priv->ucode_data_backup.p_addr);
5556 priv->ucode_data_backup.v_addr = NULL;
5557 }
5558 if (priv->ucode_init.v_addr != NULL) {
5559 pci_free_consistent(priv->pci_dev,
5560 priv->ucode_init.len,
5561 priv->ucode_init.v_addr,
5562 priv->ucode_init.p_addr);
5563 priv->ucode_init.v_addr = NULL;
5564 }
5565 if (priv->ucode_init_data.v_addr != NULL) {
5566 pci_free_consistent(priv->pci_dev,
5567 priv->ucode_init_data.len,
5568 priv->ucode_init_data.v_addr,
5569 priv->ucode_init_data.p_addr);
5570 priv->ucode_init_data.v_addr = NULL;
5571 }
5572 if (priv->ucode_boot.v_addr != NULL) {
5573 pci_free_consistent(priv->pci_dev,
5574 priv->ucode_boot.len,
5575 priv->ucode_boot.v_addr,
5576 priv->ucode_boot.p_addr);
5577 priv->ucode_boot.v_addr = NULL;
5578 }
5579}
5580
5581/**
bb8c093b 5582 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5583 * looking at all data.
5584 */
bb8c093b 5585static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5586{
5587 u32 val;
5588 u32 save_len = len;
5589 int rc = 0;
5590 u32 errcnt;
5591
5592 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5593
bb8c093b 5594 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5595 if (rc)
5596 return rc;
5597
bb8c093b 5598 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5599
5600 errcnt = 0;
5601 for (; len > 0; len -= sizeof(u32), image++) {
5602 /* read data comes through single port, auto-incr addr */
5603 /* NOTE: Use the debugless read so we don't flood kernel log
5604 * if IWL_DL_IO is set */
bb8c093b 5605 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5606 if (val != le32_to_cpu(*image)) {
5607 IWL_ERROR("uCode INST section is invalid at "
5608 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5609 save_len - len, val, le32_to_cpu(*image));
5610 rc = -EIO;
5611 errcnt++;
5612 if (errcnt >= 20)
5613 break;
5614 }
5615 }
5616
bb8c093b 5617 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5618
5619 if (!errcnt)
bc434dd2 5620 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5621
5622 return rc;
5623}
5624
5625
5626/**
bb8c093b 5627 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5628 * using sample data 100 bytes apart. If these sample points are good,
5629 * it's a pretty good bet that everything between them is good, too.
5630 */
bb8c093b 5631static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5632{
5633 u32 val;
5634 int rc = 0;
5635 u32 errcnt = 0;
5636 u32 i;
5637
5638 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5639
bb8c093b 5640 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5641 if (rc)
5642 return rc;
5643
5644 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5645 /* read data comes through single port, auto-incr addr */
5646 /* NOTE: Use the debugless read so we don't flood kernel log
5647 * if IWL_DL_IO is set */
bb8c093b 5648 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5649 i + RTC_INST_LOWER_BOUND);
bb8c093b 5650 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5651 if (val != le32_to_cpu(*image)) {
5652#if 0 /* Enable this if you want to see details */
5653 IWL_ERROR("uCode INST section is invalid at "
5654 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5655 i, val, *image);
5656#endif
5657 rc = -EIO;
5658 errcnt++;
5659 if (errcnt >= 3)
5660 break;
5661 }
5662 }
5663
bb8c093b 5664 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5665
5666 return rc;
5667}
5668
5669
5670/**
bb8c093b 5671 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5672 * and verify its contents
5673 */
bb8c093b 5674static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5675{
5676 __le32 *image;
5677 u32 len;
5678 int rc = 0;
5679
5680 /* Try bootstrap */
5681 image = (__le32 *)priv->ucode_boot.v_addr;
5682 len = priv->ucode_boot.len;
bb8c093b 5683 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5684 if (rc == 0) {
5685 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5686 return 0;
5687 }
5688
5689 /* Try initialize */
5690 image = (__le32 *)priv->ucode_init.v_addr;
5691 len = priv->ucode_init.len;
bb8c093b 5692 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5693 if (rc == 0) {
5694 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5695 return 0;
5696 }
5697
5698 /* Try runtime/protocol */
5699 image = (__le32 *)priv->ucode_code.v_addr;
5700 len = priv->ucode_code.len;
bb8c093b 5701 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5702 if (rc == 0) {
5703 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5704 return 0;
5705 }
5706
5707 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5708
9fbab516
BC		 5709 /* Since nothing seems to match, show first several data entries in
5710 * instruction SRAM, so maybe visual inspection will give a clue.
5711 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5712 image = (__le32 *)priv->ucode_boot.v_addr;
5713 len = priv->ucode_boot.len;
bb8c093b 5714 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5715
5716 return rc;
5717}
5718
5719
5720/* check contents of special bootstrap uCode SRAM */
bb8c093b 5721static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5722{
5723 __le32 *image = priv->ucode_boot.v_addr;
5724 u32 len = priv->ucode_boot.len;
5725 u32 reg;
5726 u32 val;
5727
5728 IWL_DEBUG_INFO("Begin verify bsm\n");
5729
5730 /* verify BSM SRAM contents */
bb8c093b 5731 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5732 for (reg = BSM_SRAM_LOWER_BOUND;
5733 reg < BSM_SRAM_LOWER_BOUND + len;
5734 reg += sizeof(u32), image ++) {
bb8c093b 5735 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5736 if (val != le32_to_cpu(*image)) {
5737 IWL_ERROR("BSM uCode verification failed at "
5738 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5739 BSM_SRAM_LOWER_BOUND,
5740 reg - BSM_SRAM_LOWER_BOUND, len,
5741 val, le32_to_cpu(*image));
5742 return -EIO;
5743 }
5744 }
5745
5746 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5747
5748 return 0;
5749}
5750
5751/**
bb8c093b 5752 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5753 *
5754 * BSM operation:
5755 *
5756 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5757 * in special SRAM that does not power down during RFKILL. When powering back
5758 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5759 * the bootstrap program into the on-board processor, and starts it.
5760 *
5761 * The bootstrap program loads (via DMA) instructions and data for a new
5762 * program from host DRAM locations indicated by the host driver in the
5763 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5764 * automatically.
5765 *
5766 * When initializing the NIC, the host driver points the BSM to the
5767 * "initialize" uCode image. This uCode sets up some internal data, then
5768 * notifies host via "initialize alive" that it is complete.
5769 *
5770 * The host then replaces the BSM_DRAM_* pointer values to point to the
5771 * normal runtime uCode instructions and a backup uCode data cache buffer
5772 * (filled initially with starting data values for the on-board processor),
5773 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5774 * which begins normal operation.
5775 *
5776 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5777 * the backup data cache in DRAM before SRAM is powered down.
5778 *
5779 * When powering back up, the BSM loads the bootstrap program. This reloads
5780 * the runtime uCode instructions and the backup data cache into SRAM,
5781 * and re-launches the runtime uCode from where it left off.
5782 */
bb8c093b 5783static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5784{
5785 __le32 *image = priv->ucode_boot.v_addr;
5786 u32 len = priv->ucode_boot.len;
5787 dma_addr_t pinst;
5788 dma_addr_t pdata;
5789 u32 inst_len;
5790 u32 data_len;
5791 int rc;
5792 int i;
5793 u32 done;
5794 u32 reg_offset;
5795
5796 IWL_DEBUG_INFO("Begin load bsm\n");
5797
5798 /* make sure bootstrap program is no larger than BSM's SRAM size */
5799 if (len > IWL_MAX_BSM_SIZE)
5800 return -EINVAL;
5801
5802 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5803 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5804 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5805 * after the "initialize" uCode has run, to point to
5806 * runtime/protocol instructions and backup data cache. */
5807 pinst = priv->ucode_init.p_addr;
5808 pdata = priv->ucode_init_data.p_addr;
5809 inst_len = priv->ucode_init.len;
5810 data_len = priv->ucode_init_data.len;
5811
bb8c093b 5812 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5813 if (rc)
5814 return rc;
5815
bb8c093b
CH		 5816 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5817 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5818 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5819 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5820
5821 /* Fill BSM memory with bootstrap instructions */
5822 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5823 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5824 reg_offset += sizeof(u32), image++)
bb8c093b 5825 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5826 le32_to_cpu(*image));
5827
bb8c093b 5828 rc = iwl3945_verify_bsm(priv);
b481de9c 5829 if (rc) {
bb8c093b 5830 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5831 return rc;
5832 }
5833
5834 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5835 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5836 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5837 RTC_INST_LOWER_BOUND);
bb8c093b 5838 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5839
5840 /* Load bootstrap code into instruction SRAM now,
5841 * to prepare to load "initialize" uCode */
bb8c093b 5842 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5843 BSM_WR_CTRL_REG_BIT_START);
5844
5845 /* Wait for load of bootstrap uCode to finish */
5846 for (i = 0; i < 100; i++) {
bb8c093b 5847 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5848 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5849 break;
5850 udelay(10);
5851 }
5852 if (i < 100)
5853 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5854 else {
5855 IWL_ERROR("BSM write did not complete!\n");
5856 return -EIO;
5857 }
5858
5859 /* Enable future boot loads whenever power management unit triggers it
5860 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5861 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5862 BSM_WR_CTRL_REG_BIT_START_EN);
5863
bb8c093b 5864 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5865
5866 return 0;
5867}
5868
bb8c093b 5869static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5870{
5871 /* Remove all resets to allow NIC to operate */
bb8c093b 5872 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5873}
5874
90e759d1
TW		 5875static int iwl3945_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
5876{
5877 desc->v_addr = pci_alloc_consistent(pci_dev, desc->len, &desc->p_addr);
5878 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
5879}
5880
b481de9c 5881/**
bb8c093b 5882 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5883 *
5884 * Copy into buffers for card to fetch via bus-mastering
5885 */
bb8c093b 5886static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5887{
bb8c093b 5888 struct iwl3945_ucode *ucode;
90e759d1 5889 int ret = 0;
b481de9c
ZY		 5890 const struct firmware *ucode_raw;
5891 /* firmware file name contains uCode/driver compatibility version */
5892 const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
5893 u8 *src;
5894 size_t len;
5895 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5896
5897 /* Ask kernel firmware_class module to get the boot firmware off disk.
5898 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5899 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5900 if (ret < 0) {
5901 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5902 name, ret);
b481de9c
ZY		 5903 goto error;
5904 }
5905
5906 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5907 name, ucode_raw->size);
5908
5909 /* Make sure that we got at least our header! */
5910 if (ucode_raw->size < sizeof(*ucode)) {
5911 IWL_ERROR("File size way too small!\n");
90e759d1 5912 ret = -EINVAL;
b481de9c
ZY		 5913 goto err_release;
5914 }
5915
5916 /* Data from ucode file: header followed by uCode images */
5917 ucode = (void *)ucode_raw->data;
5918
5919 ver = le32_to_cpu(ucode->ver);
5920 inst_size = le32_to_cpu(ucode->inst_size);
5921 data_size = le32_to_cpu(ucode->data_size);
5922 init_size = le32_to_cpu(ucode->init_size);
5923 init_data_size = le32_to_cpu(ucode->init_data_size);
5924 boot_size = le32_to_cpu(ucode->boot_size);
5925
5926 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5927 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5928 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5929 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5930 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5931 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5932
5933 /* Verify size of file vs. image size info in file's header */
5934 if (ucode_raw->size < sizeof(*ucode) +
5935 inst_size + data_size + init_size +
5936 init_data_size + boot_size) {
5937
5938 IWL_DEBUG_INFO("uCode file size %d too small\n",
5939 (int)ucode_raw->size);
90e759d1 5940 ret = -EINVAL;
b481de9c
ZY		 5941 goto err_release;
5942 }
5943
5944 /* Verify that uCode images will fit in card's SRAM */
5945 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5946 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5947 inst_size);
5948 ret = -EINVAL;
b481de9c
ZY		 5949 goto err_release;
5950 }
5951
5952 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5953 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5954 data_size);
5955 ret = -EINVAL;
b481de9c
ZY		 5956 goto err_release;
5957 }
5958 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5959 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5960 init_size);
5961 ret = -EINVAL;
b481de9c
ZY		 5962 goto err_release;
5963 }
5964 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5965 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5966 init_data_size);
5967 ret = -EINVAL;
b481de9c
ZY		 5968 goto err_release;
5969 }
5970 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5971 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5972 boot_size);
5973 ret = -EINVAL;
b481de9c
ZY		 5974 goto err_release;
5975 }
5976
5977 /* Allocate ucode buffers for card's bus-master loading ... */
5978
5979 /* Runtime instructions and 2 copies of data:
5980 * 1) unmodified from disk
5981 * 2) backup cache for save/restore during power-downs */
5982 priv->ucode_code.len = inst_size;
90e759d1 5983 iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5984
5985 priv->ucode_data.len = data_size;
90e759d1 5986 iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5987
5988 priv->ucode_data_backup.len = data_size;
90e759d1 5989 iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5990
90e759d1
TW		 5991 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5992 !priv->ucode_data_backup.v_addr)
5993 goto err_pci_alloc;
b481de9c
ZY		 5994
5995 /* Initialization instructions and data */
90e759d1
TW		 5996 if (init_size && init_data_size) {
5997 priv->ucode_init.len = init_size;
5998 iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
5999
6000 priv->ucode_init_data.len = init_data_size;
6001 iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
6002
6003 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
6004 goto err_pci_alloc;
6005 }
b481de9c
ZY		 6006
6007 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 6008 if (boot_size) {
6009 priv->ucode_boot.len = boot_size;
6010 iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 6011
90e759d1
TW		 6012 if (!priv->ucode_boot.v_addr)
6013 goto err_pci_alloc;
6014 }
b481de9c
ZY		 6015
6016 /* Copy images into buffers for card's bus-master reads ... */
6017
6018 /* Runtime instructions (first block of data in file) */
6019 src = &ucode->data[0];
6020 len = priv->ucode_code.len;
90e759d1 6021 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 6022 memcpy(priv->ucode_code.v_addr, src, len);
6023 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
6024 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
6025
6026 /* Runtime data (2nd block)
bb8c093b 6027 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 6028 src = &ucode->data[inst_size];
6029 len = priv->ucode_data.len;
90e759d1 6030 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 6031 memcpy(priv->ucode_data.v_addr, src, len);
6032 memcpy(priv->ucode_data_backup.v_addr, src, len);
6033
6034 /* Initialization instructions (3rd block) */
6035 if (init_size) {
6036 src = &ucode->data[inst_size + data_size];
6037 len = priv->ucode_init.len;
90e759d1
TW		 6038 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
6039 len);
b481de9c
ZY		 6040 memcpy(priv->ucode_init.v_addr, src, len);
6041 }
6042
6043 /* Initialization data (4th block) */
6044 if (init_data_size) {
6045 src = &ucode->data[inst_size + data_size + init_size];
6046 len = priv->ucode_init_data.len;
6047 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
6048 (int)len);
6049 memcpy(priv->ucode_init_data.v_addr, src, len);
6050 }
6051
6052 /* Bootstrap instructions (5th block) */
6053 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
6054 len = priv->ucode_boot.len;
6055 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
6056 (int)len);
6057 memcpy(priv->ucode_boot.v_addr, src, len);
6058
6059 /* We have our copies now, allow OS release its copies */
6060 release_firmware(ucode_raw);
6061 return 0;
6062
6063 err_pci_alloc:
6064 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 6065 ret = -ENOMEM;
bb8c093b 6066 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 6067
6068 err_release:
6069 release_firmware(ucode_raw);
6070
6071 error:
90e759d1 6072 return ret;
b481de9c
ZY		 6073}
6074
6075
6076/**
bb8c093b 6077 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 6078 *
6079 * Tell initialization uCode where to find runtime uCode.
6080 *
6081 * BSM registers initially contain pointers to initialization uCode.
6082 * We need to replace them to load runtime uCode inst and data,
6083 * and to save runtime data when powering down.
6084 */
bb8c093b 6085static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 6086{
6087 dma_addr_t pinst;
6088 dma_addr_t pdata;
6089 int rc = 0;
6090 unsigned long flags;
6091
6092 /* bits 31:0 for 3945 */
6093 pinst = priv->ucode_code.p_addr;
6094 pdata = priv->ucode_data_backup.p_addr;
6095
6096 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6097 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 6098 if (rc) {
6099 spin_unlock_irqrestore(&priv->lock, flags);
6100 return rc;
6101 }
6102
6103 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 6104 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6105 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6106 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 6107 priv->ucode_data.len);
6108
6109 /* Inst bytecount must be last to set up, bit 31 signals uCode
6110 * that all new ptr/size info is in place */
bb8c093b 6111 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 6112 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6113
bb8c093b 6114 iwl3945_release_nic_access(priv);
b481de9c
ZY		 6115
6116 spin_unlock_irqrestore(&priv->lock, flags);
6117
6118 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
6119
6120 return rc;
6121}
6122
6123/**
bb8c093b 6124 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 6125 *
6126 * Called after REPLY_ALIVE notification received from "initialize" uCode.
6127 *
b481de9c 6128 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 6129 */
bb8c093b 6130static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 6131{
6132 /* Check alive response for "valid" sign from uCode */
6133 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
6134 /* We had an error bringing up the hardware, so take it
6135 * all the way back down so we can try again */
6136 IWL_DEBUG_INFO("Initialize Alive failed.\n");
6137 goto restart;
6138 }
6139
6140 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
6141 * This is a paranoid check, because we would not have gotten the
6142 * "initialize" alive if code weren't properly loaded. */
bb8c093b 6143 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 6144 /* Runtime instruction load was bad;
6145 * take it all the way back down so we can try again */
6146 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
6147 goto restart;
6148 }
6149
6150 /* Send pointers to protocol/runtime uCode image ... init code will
6151 * load and launch runtime uCode, which will send us another "Alive"
6152 * notification. */
6153 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 6154 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 6155 /* Runtime instruction load won't happen;
6156 * take it all the way back down so we can try again */
6157 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
6158 goto restart;
6159 }
6160 return;
6161
6162 restart:
6163 queue_work(priv->workqueue, &priv->restart);
6164}
6165
6166
6167/**
bb8c093b 6168 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 6169 * from protocol/runtime uCode (initialization uCode's
bb8c093b 6170 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 6171 */
bb8c093b 6172static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 6173{
6174 int rc = 0;
6175 int thermal_spin = 0;
6176 u32 rfkill;
6177
6178 IWL_DEBUG_INFO("Runtime Alive received.\n");
6179
6180 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
6181 /* We had an error bringing up the hardware, so take it
6182 * all the way back down so we can try again */
6183 IWL_DEBUG_INFO("Alive failed.\n");
6184 goto restart;
6185 }
6186
6187 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
6188 * This is a paranoid check, because we would not have gotten the
6189 * "runtime" alive if code weren't properly loaded. */
bb8c093b 6190 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 6191 /* Runtime instruction load was bad;
6192 * take it all the way back down so we can try again */
6193 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
6194 goto restart;
6195 }
6196
bb8c093b 6197 iwl3945_clear_stations_table(priv);
b481de9c 6198
bb8c093b 6199 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 6200 if (rc) {
6201 IWL_WARNING("Can not read rfkill status from adapter\n");
6202 return;
6203 }
6204
bb8c093b 6205 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 6206 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 6207 iwl3945_release_nic_access(priv);
b481de9c
ZY		 6208
6209 if (rfkill & 0x1) {
6210 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6211 /* if rfkill is not on, then wait for thermal
6212 * sensor in adapter to kick in */
bb8c093b 6213 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 6214 thermal_spin++;
6215 udelay(10);
6216 }
6217
6218 if (thermal_spin)
6219 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
6220 thermal_spin * 10);
6221 } else
6222 set_bit(STATUS_RF_KILL_HW, &priv->status);
6223
9fbab516 6224 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 6225 set_bit(STATUS_ALIVE, &priv->status);
6226
6227 /* Clear out the uCode error bit if it is set */
6228 clear_bit(STATUS_FW_ERROR, &priv->status);
6229
bb8c093b 6230 rc = iwl3945_init_channel_map(priv);
b481de9c
ZY		 6231 if (rc) {
6232 IWL_ERROR("initializing regulatory failed: %d\n", rc);
6233 return;
6234 }
6235
bb8c093b 6236 iwl3945_init_geos(priv);
b481de9c 6237
bb8c093b 6238 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 6239 return;
6240
6241 if (!priv->mac80211_registered) {
6242 /* Unlock so any user space entry points can call back into
6243 * the driver without a deadlock... */
6244 mutex_unlock(&priv->mutex);
bb8c093b 6245 iwl3945_rate_control_register(priv->hw);
b481de9c
ZY		 6246 rc = ieee80211_register_hw(priv->hw);
6247 priv->hw->conf.beacon_int = 100;
6248 mutex_lock(&priv->mutex);
6249
6250 if (rc) {
bb8c093b 6251 iwl3945_rate_control_unregister(priv->hw);
b481de9c
ZY		 6252 IWL_ERROR("Failed to register network "
6253 "device (error %d)\n", rc);
6254 return;
6255 }
6256
6257 priv->mac80211_registered = 1;
6258
bb8c093b 6259 iwl3945_reset_channel_flag(priv);
b481de9c
ZY		 6260 } else
6261 ieee80211_start_queues(priv->hw);
6262
6263 priv->active_rate = priv->rates_mask;
6264 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
6265
bb8c093b 6266 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 6267
bb8c093b
CH		 6268 if (iwl3945_is_associated(priv)) {
6269 struct iwl3945_rxon_cmd *active_rxon =
6270 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 6271
6272 memcpy(&priv->staging_rxon, &priv->active_rxon,
6273 sizeof(priv->staging_rxon));
6274 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6275 } else {
6276 /* Initialize our rx_config data */
bb8c093b 6277 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 6278 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
6279 }
6280
9fbab516 6281 /* Configure Bluetooth device coexistence support */
bb8c093b 6282 iwl3945_send_bt_config(priv);
b481de9c
ZY		 6283
6284 /* Configure the adapter for unassociated operation */
bb8c093b 6285 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6286
6287 /* At this point, the NIC is initialized and operational */
6288 priv->notif_missed_beacons = 0;
6289 set_bit(STATUS_READY, &priv->status);
6290
6291 iwl3945_reg_txpower_periodic(priv);
6292
6293 IWL_DEBUG_INFO("ALIVE processing complete.\n");
6294
6295 if (priv->error_recovering)
bb8c093b 6296 iwl3945_error_recovery(priv);
b481de9c
ZY		 6297
6298 return;
6299
6300 restart:
6301 queue_work(priv->workqueue, &priv->restart);
6302}
6303
bb8c093b 6304static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 6305
bb8c093b 6306static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 6307{
6308 unsigned long flags;
6309 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
6310 struct ieee80211_conf *conf = NULL;
6311
6312 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
6313
6314 conf = ieee80211_get_hw_conf(priv->hw);
6315
6316 if (!exit_pending)
6317 set_bit(STATUS_EXIT_PENDING, &priv->status);
6318
bb8c093b 6319 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6320
6321 /* Unblock any waiting calls */
6322 wake_up_interruptible_all(&priv->wait_command_queue);
6323
b481de9c
ZY		 6324 /* Wipe out the EXIT_PENDING status bit if we are not actually
6325 * exiting the module */
6326 if (!exit_pending)
6327 clear_bit(STATUS_EXIT_PENDING, &priv->status);
6328
6329 /* stop and reset the on-board processor */
bb8c093b 6330 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 6331
6332 /* tell the device to stop sending interrupts */
bb8c093b 6333 iwl3945_disable_interrupts(priv);
b481de9c
ZY		 6334
6335 if (priv->mac80211_registered)
6336 ieee80211_stop_queues(priv->hw);
6337
bb8c093b 6338 /* If we have not previously called iwl3945_init() then
b481de9c 6339 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 6340 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 6341 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6342 STATUS_RF_KILL_HW |
6343 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6344 STATUS_RF_KILL_SW |
6345 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6346 STATUS_IN_SUSPEND;
6347 goto exit;
6348 }
6349
6350 /* ...otherwise clear out all the status bits but the RF Kill and
6351 * SUSPEND bits and continue taking the NIC down. */
6352 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
6353 STATUS_RF_KILL_HW |
6354 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
6355 STATUS_RF_KILL_SW |
6356 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
6357 STATUS_IN_SUSPEND |
6358 test_bit(STATUS_FW_ERROR, &priv->status) <<
6359 STATUS_FW_ERROR;
6360
6361 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 6362 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 6363 spin_unlock_irqrestore(&priv->lock, flags);
6364
bb8c093b
CH		 6365 iwl3945_hw_txq_ctx_stop(priv);
6366 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 6367
6368 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 6369 if (!iwl3945_grab_nic_access(priv)) {
6370 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 6371 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 6372 iwl3945_release_nic_access(priv);
b481de9c
ZY		 6373 }
6374 spin_unlock_irqrestore(&priv->lock, flags);
6375
6376 udelay(5);
6377
bb8c093b
CH		 6378 iwl3945_hw_nic_stop_master(priv);
6379 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
6380 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 6381
6382 exit:
bb8c093b 6383 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 6384
6385 if (priv->ibss_beacon)
6386 dev_kfree_skb(priv->ibss_beacon);
6387 priv->ibss_beacon = NULL;
6388
6389 /* clear out any free frames */
bb8c093b 6390 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 6391}
6392
bb8c093b 6393static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 6394{
6395 mutex_lock(&priv->mutex);
bb8c093b 6396 __iwl3945_down(priv);
b481de9c 6397 mutex_unlock(&priv->mutex);
b24d22b1 6398
bb8c093b 6399 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 6400}
6401
6402#define MAX_HW_RESTARTS 5
6403
bb8c093b 6404static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c 6405{
0795af57 6406 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6407 int rc, i;
6408
6409 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6410 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6411 return -EIO;
6412 }
6413
6414 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6415 IWL_WARNING("Radio disabled by SW RF kill (module "
6416 "parameter)\n");
6417 return 0;
6418 }
6419
a781cf94
RC		 6420 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6421 IWL_ERROR("ucode not available for device bringup\n");
6422 return -EIO;
6423 }
6424
bb8c093b 6425 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6426
bb8c093b 6427 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6428 if (rc) {
6429 IWL_ERROR("Unable to int nic\n");
6430 return rc;
6431 }
6432
6433 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6434 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6435 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6436 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6437
6438 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6439 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6440 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6441
6442 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6443 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6444 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6445
6446 /* Copy original ucode data image from disk into backup cache.
6447 * This will be used to initialize the on-board processor's
6448 * data SRAM for a clean start when the runtime program first loads. */
6449 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
6450 priv->ucode_data.len);
6451
6452 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6453
bb8c093b 6454 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6455
6456 /* load bootstrap state machine,
6457 * load bootstrap program into processor's memory,
6458 * prepare to load the "initialize" uCode */
bb8c093b 6459 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6460
6461 if (rc) {
6462 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6463 continue;
6464 }
6465
6466 /* start card; "initialize" will load runtime ucode */
bb8c093b 6467 iwl3945_nic_start(priv);
b481de9c 6468
9fbab516 6469 /* MAC Address location in EEPROM is same for 3945/4965 */
b481de9c 6470 get_eeprom_mac(priv, priv->mac_addr);
0795af57
JP		 6471 IWL_DEBUG_INFO("MAC address: %s\n",
6472 print_mac(mac, priv->mac_addr));
b481de9c
ZY		 6473
6474 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
6475
6476 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6477
6478 return 0;
6479 }
6480
6481 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6482 __iwl3945_down(priv);
b481de9c
ZY		 6483
6484 /* tried to restart and config the device for as long as our
6485 * patience could withstand */
6486 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6487 return -EIO;
6488}
6489
6490
6491/*****************************************************************************
6492 *
6493 * Workqueue callbacks
6494 *
6495 *****************************************************************************/
6496
bb8c093b 6497static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6498{
bb8c093b
CH		 6499 struct iwl3945_priv *priv =
6500 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6501
6502 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6503 return;
6504
6505 mutex_lock(&priv->mutex);
bb8c093b 6506 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6507 mutex_unlock(&priv->mutex);
6508}
6509
bb8c093b 6510static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6511{
bb8c093b
CH		 6512 struct iwl3945_priv *priv =
6513 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6514
6515 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6516 return;
6517
6518 mutex_lock(&priv->mutex);
bb8c093b 6519 iwl3945_alive_start(priv);
b481de9c
ZY		 6520 mutex_unlock(&priv->mutex);
6521}
6522
bb8c093b 6523static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6524{
bb8c093b 6525 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6526
6527 wake_up_interruptible(&priv->wait_command_queue);
6528
6529 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6530 return;
6531
6532 mutex_lock(&priv->mutex);
6533
bb8c093b 6534 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6535 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6536 "HW and/or SW RF Kill no longer active, restarting "
6537 "device\n");
6538 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6539 queue_work(priv->workqueue, &priv->restart);
6540 } else {
6541
6542 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6543 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6544 "disabled by SW switch\n");
6545 else
6546 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6547 "Kill switch must be turned off for "
6548 "wireless networking to work.\n");
6549 }
6550 mutex_unlock(&priv->mutex);
6551}
6552
6553#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6554
bb8c093b 6555static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6556{
bb8c093b
CH		 6557 struct iwl3945_priv *priv =
6558 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6559
6560 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6561 return;
6562
6563 mutex_lock(&priv->mutex);
6564 if (test_bit(STATUS_SCANNING, &priv->status) ||
6565 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6566 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6567 "Scan completion watchdog resetting adapter (%dms)\n",
6568 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6569
b481de9c 6570 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6571 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6572 }
6573 mutex_unlock(&priv->mutex);
6574}
6575
bb8c093b 6576static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6577{
bb8c093b
CH		 6578 struct iwl3945_priv *priv =
6579 container_of(data, struct iwl3945_priv, request_scan);
6580 struct iwl3945_host_cmd cmd = {
b481de9c 6581 .id = REPLY_SCAN_CMD,
bb8c093b 6582 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6583 .meta.flags = CMD_SIZE_HUGE,
6584 };
6585 int rc = 0;
bb8c093b 6586 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6587 struct ieee80211_conf *conf = NULL;
6588 u8 direct_mask;
6589 int phymode;
6590
6591 conf = ieee80211_get_hw_conf(priv->hw);
6592
6593 mutex_lock(&priv->mutex);
6594
bb8c093b 6595 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6596 IWL_WARNING("request scan called when driver not ready.\n");
6597 goto done;
6598 }
6599
6600 /* Make sure the scan wasn't cancelled before this queued work
6601 * was given the chance to run... */
6602 if (!test_bit(STATUS_SCANNING, &priv->status))
6603 goto done;
6604
6605 /* This should never be called or scheduled if there is currently
6606 * a scan active in the hardware. */
6607 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6608 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6609 "Ignoring second request.\n");
6610 rc = -EIO;
6611 goto done;
6612 }
6613
6614 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6615 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6616 goto done;
6617 }
6618
6619 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6620 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6621 goto done;
6622 }
6623
bb8c093b 6624 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6625 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6626 goto done;
6627 }
6628
6629 if (!test_bit(STATUS_READY, &priv->status)) {
6630 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6631 goto done;
6632 }
6633
6634 if (!priv->scan_bands) {
6635 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6636 goto done;
6637 }
6638
6639 if (!priv->scan) {
bb8c093b 6640 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6641 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6642 if (!priv->scan) {
6643 rc = -ENOMEM;
6644 goto done;
6645 }
6646 }
6647 scan = priv->scan;
bb8c093b 6648 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6649
6650 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6651 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6652
bb8c093b 6653 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6654 u16 interval = 0;
6655 u32 extra;
6656 u32 suspend_time = 100;
6657 u32 scan_suspend_time = 100;
6658 unsigned long flags;
6659
6660 IWL_DEBUG_INFO("Scanning while associated...\n");
6661
6662 spin_lock_irqsave(&priv->lock, flags);
6663 interval = priv->beacon_int;
6664 spin_unlock_irqrestore(&priv->lock, flags);
6665
6666 scan->suspend_time = 0;
15e869d8 6667 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6668 if (!interval)
6669 interval = suspend_time;
6670 /*
6671 * suspend time format:
6672 * 0-19: beacon interval in usec (time before exec.)
6673 * 20-23: 0
6674 * 24-31: number of beacons (suspend between channels)
6675 */
6676
6677 extra = (suspend_time / interval) << 24;
6678 scan_suspend_time = 0xFF0FFFFF &
6679 (extra | ((suspend_time % interval) * 1024));
6680
6681 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6682 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6683 scan_suspend_time, interval);
6684 }
6685
6686 /* We should add the ability for user to lock to PASSIVE ONLY */
6687 if (priv->one_direct_scan) {
6688 IWL_DEBUG_SCAN
6689 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6690 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6691 priv->direct_ssid_len));
6692 scan->direct_scan[0].id = WLAN_EID_SSID;
6693 scan->direct_scan[0].len = priv->direct_ssid_len;
6694 memcpy(scan->direct_scan[0].ssid,
6695 priv->direct_ssid, priv->direct_ssid_len);
6696 direct_mask = 1;
bb8c093b 6697 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
b481de9c
ZY		 6698 scan->direct_scan[0].id = WLAN_EID_SSID;
6699 scan->direct_scan[0].len = priv->essid_len;
6700 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6701 direct_mask = 1;
6702 } else
6703 direct_mask = 0;
6704
6705 /* We don't build a direct scan probe request; the uCode will do
6706 * that based on the direct_mask added to each channel entry */
6707 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6708 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
b481de9c
ZY		 6709 IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
6710 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6711 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6712 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6713
6714 /* flags + rate selection */
6715
6716 switch (priv->scan_bands) {
6717 case 2:
6718 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6719 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6720 scan->good_CRC_th = 0;
6721 phymode = MODE_IEEE80211G;
6722 break;
6723
6724 case 1:
6725 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6726 scan->good_CRC_th = IWL_GOOD_CRC_TH;
6727 phymode = MODE_IEEE80211A;
6728 break;
6729
6730 default:
6731 IWL_WARNING("Invalid scan band count\n");
6732 goto done;
6733 }
6734
6735 /* select Rx antennas */
6736 scan->flags |= iwl3945_get_antenna_flags(priv);
6737
6738 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6739 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6740
6741 if (direct_mask)
6742 IWL_DEBUG_SCAN
6743 ("Initiating direct scan for %s.\n",
bb8c093b 6744 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6745 else
6746 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
6747
6748 scan->channel_count =
bb8c093b 6749 iwl3945_get_channels_for_scan(
b481de9c
ZY		 6750 priv, phymode, 1, /* active */
6751 direct_mask,
6752 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6753
6754 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6755 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6756 cmd.data = scan;
6757 scan->len = cpu_to_le16(cmd.len);
6758
6759 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6760 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6761 if (rc)
6762 goto done;
6763
6764 queue_delayed_work(priv->workqueue, &priv->scan_check,
6765 IWL_SCAN_CHECK_WATCHDOG);
6766
6767 mutex_unlock(&priv->mutex);
6768 return;
6769
6770 done:
01ebd063 6771 /* inform mac80211 scan aborted */
b481de9c
ZY		 6772 queue_work(priv->workqueue, &priv->scan_completed);
6773 mutex_unlock(&priv->mutex);
6774}
6775
bb8c093b 6776static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6777{
bb8c093b 6778 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6779
6780 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6781 return;
6782
6783 mutex_lock(&priv->mutex);
bb8c093b 6784 __iwl3945_up(priv);
b481de9c
ZY		 6785 mutex_unlock(&priv->mutex);
6786}
6787
bb8c093b 6788static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6789{
bb8c093b 6790 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6791
6792 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6793 return;
6794
bb8c093b 6795 iwl3945_down(priv);
b481de9c
ZY		 6796 queue_work(priv->workqueue, &priv->up);
6797}
6798
bb8c093b 6799static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6800{
bb8c093b
CH		 6801 struct iwl3945_priv *priv =
6802 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6803
6804 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6805 return;
6806
6807 mutex_lock(&priv->mutex);
bb8c093b 6808 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6809 mutex_unlock(&priv->mutex);
6810}
6811
7878a5a4
MA		 6812#define IWL_DELAY_NEXT_SCAN (HZ*2)
6813
bb8c093b 6814static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6815{
bb8c093b 6816 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6817 post_associate.work);
6818
6819 int rc = 0;
6820 struct ieee80211_conf *conf = NULL;
0795af57 6821 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6822
6823 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6824 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6825 return;
6826 }
6827
6828
0795af57
JP		 6829 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6830 priv->assoc_id,
6831 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6832
6833 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6834 return;
6835
6836 mutex_lock(&priv->mutex);
6837
6ef89d0a
MA		 6838 if (!priv->interface_id || !priv->is_open) {
6839 mutex_unlock(&priv->mutex);
6840 return;
6841 }
bb8c093b 6842 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6843
b481de9c
ZY		 6844 conf = ieee80211_get_hw_conf(priv->hw);
6845
6846 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6847 iwl3945_commit_rxon(priv);
b481de9c 6848
bb8c093b
CH		 6849 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6850 iwl3945_setup_rxon_timing(priv);
6851 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6852 sizeof(priv->rxon_timing), &priv->rxon_timing);
6853 if (rc)
6854 IWL_WARNING("REPLY_RXON_TIMING failed - "
6855 "Attempting to continue.\n");
6856
6857 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6858
6859 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6860
6861 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6862 priv->assoc_id, priv->beacon_int);
6863
6864 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6865 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6866 else
6867 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6868
6869 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6870 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6871 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6872 else
6873 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6874
6875 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6876 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6877
6878 }
6879
bb8c093b 6880 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6881
6882 switch (priv->iw_mode) {
6883 case IEEE80211_IF_TYPE_STA:
bb8c093b 6884 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6885 break;
6886
6887 case IEEE80211_IF_TYPE_IBSS:
6888
6889 /* clear out the station table */
bb8c093b 6890 iwl3945_clear_stations_table(priv);
b481de9c 6891
bb8c093b
CH		 6892 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6893 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c
ZY		 6894 iwl3945_sync_sta(priv, IWL_STA_ID,
6895 (priv->phymode == MODE_IEEE80211A)?
6896 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6897 CMD_ASYNC);
bb8c093b
CH		 6898 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6899 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6900
6901 break;
6902
6903 default:
6904 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6905 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6906 break;
6907 }
6908
bb8c093b 6909 iwl3945_sequence_reset(priv);
b481de9c 6910
c8b0e6e1 6911#ifdef CONFIG_IWL3945_QOS
bb8c093b 6912 iwl3945_activate_qos(priv, 0);
c8b0e6e1 6913#endif /* CONFIG_IWL3945_QOS */
7878a5a4
MA		 6914 /* we have just associated, don't start scan too early */
6915 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6916 mutex_unlock(&priv->mutex);
6917}
6918
bb8c093b 6919static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6920{
bb8c093b 6921 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6922
bb8c093b 6923 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6924 return;
6925
6926 mutex_lock(&priv->mutex);
6927
6928 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6929 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6930
6931 mutex_unlock(&priv->mutex);
6932}
6933
bb8c093b 6934static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6935{
bb8c093b
CH		 6936 struct iwl3945_priv *priv =
6937 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6938
6939 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6940
6941 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6942 return;
6943
6944 ieee80211_scan_completed(priv->hw);
6945
6946 /* Since setting the TXPOWER may have been deferred while
6947 * performing the scan, fire one off */
6948 mutex_lock(&priv->mutex);
bb8c093b 6949 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6950 mutex_unlock(&priv->mutex);
6951}
6952
6953/*****************************************************************************
6954 *
6955 * mac80211 entry point functions
6956 *
6957 *****************************************************************************/
6958
bb8c093b 6959static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6960{
bb8c093b 6961 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6962
6963 IWL_DEBUG_MAC80211("enter\n");
6964
6965 /* we should be verifying the device is ready to be opened */
6966 mutex_lock(&priv->mutex);
6967
6968 priv->is_open = 1;
6969
bb8c093b 6970 if (!iwl3945_is_rfkill(priv))
b481de9c
ZY		 6971 ieee80211_start_queues(priv->hw);
6972
6973 mutex_unlock(&priv->mutex);
6974 IWL_DEBUG_MAC80211("leave\n");
6975 return 0;
6976}
6977
bb8c093b 6978static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6979{
bb8c093b 6980 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6981
6982 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a
MA		 6983
6984
6985 mutex_lock(&priv->mutex);
6986 /* stop mac, cancel any scan request and clear
6987 * RXON_FILTER_ASSOC_MSK BIT
6988 */
b481de9c 6989 priv->is_open = 0;
bb8c093b 6990 iwl3945_scan_cancel_timeout(priv, 100);
6ef89d0a
MA		 6991 cancel_delayed_work(&priv->post_associate);
6992 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6993 iwl3945_commit_rxon(priv);
6ef89d0a
MA		 6994 mutex_unlock(&priv->mutex);
6995
b481de9c 6996 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6997}
6998
bb8c093b 6999static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7000 struct ieee80211_tx_control *ctl)
7001{
bb8c093b 7002 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7003
7004 IWL_DEBUG_MAC80211("enter\n");
7005
7006 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
7007 IWL_DEBUG_MAC80211("leave - monitor\n");
7008 return -1;
7009 }
7010
7011 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
7012 ctl->tx_rate);
7013
bb8c093b 7014 if (iwl3945_tx_skb(priv, skb, ctl))
b481de9c
ZY		 7015 dev_kfree_skb_any(skb);
7016
7017 IWL_DEBUG_MAC80211("leave\n");
7018 return 0;
7019}
7020
bb8c093b 7021static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7022 struct ieee80211_if_init_conf *conf)
7023{
bb8c093b 7024 struct iwl3945_priv *priv = hw->priv;
b481de9c 7025 unsigned long flags;
0795af57 7026 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 7027
7028 IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
b481de9c
ZY		 7029
7030 if (priv->interface_id) {
7031 IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
864792e3 7032 return -EOPNOTSUPP;
b481de9c
ZY		 7033 }
7034
7035 spin_lock_irqsave(&priv->lock, flags);
7036 priv->interface_id = conf->if_id;
7037
7038 spin_unlock_irqrestore(&priv->lock, flags);
7039
7040 mutex_lock(&priv->mutex);
864792e3
TW		 7041
7042 if (conf->mac_addr) {
7043 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
7044 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
7045 }
7046
bb8c093b 7047 iwl3945_set_mode(priv, conf->type);
b481de9c
ZY		 7048
7049 IWL_DEBUG_MAC80211("leave\n");
7050 mutex_unlock(&priv->mutex);
7051
7052 return 0;
7053}
7054
7055/**
bb8c093b 7056 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 7057 *
7058 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
7059 * be set inappropriately and the driver currently sets the hardware up to
7060 * use it whenever needed.
7061 */
bb8c093b 7062static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 7063{
bb8c093b
CH		 7064 struct iwl3945_priv *priv = hw->priv;
7065 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 7066 unsigned long flags;
7067
7068 mutex_lock(&priv->mutex);
7069 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
7070
bb8c093b 7071 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7072 IWL_DEBUG_MAC80211("leave - not ready\n");
7073 mutex_unlock(&priv->mutex);
7074 return -EIO;
7075 }
7076
7077 /* TODO: Figure out how to get ieee80211_local->sta_scanning w/ only
01ebd063 7078 * what is exposed through include/ declarations */
bb8c093b 7079 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c
ZY		 7080 test_bit(STATUS_SCANNING, &priv->status))) {
7081 IWL_DEBUG_MAC80211("leave - scanning\n");
7082 mutex_unlock(&priv->mutex);
7083 return 0;
7084 }
7085
7086 spin_lock_irqsave(&priv->lock, flags);
7087
bb8c093b 7088 ch_info = iwl3945_get_channel_info(priv, conf->phymode, conf->channel);
b481de9c
ZY		 7089 if (!is_channel_valid(ch_info)) {
7090 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
7091 conf->channel, conf->phymode);
7092 IWL_DEBUG_MAC80211("leave - invalid channel\n");
7093 spin_unlock_irqrestore(&priv->lock, flags);
7094 mutex_unlock(&priv->mutex);
7095 return -EINVAL;
7096 }
7097
bb8c093b 7098 iwl3945_set_rxon_channel(priv, conf->phymode, conf->channel);
b481de9c 7099
bb8c093b 7100 iwl3945_set_flags_for_phymode(priv, conf->phymode);
b481de9c
ZY		 7101
7102 /* The list of supported rates and rate mask can be different
7103 * for each phymode; since the phymode may have changed, reset
7104 * the rate mask to what mac80211 lists */
bb8c093b 7105 iwl3945_set_rate(priv);
b481de9c
ZY		 7106
7107 spin_unlock_irqrestore(&priv->lock, flags);
7108
7109#ifdef IEEE80211_CONF_CHANNEL_SWITCH
7110 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 7111 iwl3945_hw_channel_switch(priv, conf->channel);
b481de9c
ZY		 7112 mutex_unlock(&priv->mutex);
7113 return 0;
7114 }
7115#endif
7116
bb8c093b 7117 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 7118
7119 if (!conf->radio_enabled) {
7120 IWL_DEBUG_MAC80211("leave - radio disabled\n");
7121 mutex_unlock(&priv->mutex);
7122 return 0;
7123 }
7124
bb8c093b 7125 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 7126 IWL_DEBUG_MAC80211("leave - RF kill\n");
7127 mutex_unlock(&priv->mutex);
7128 return -EIO;
7129 }
7130
bb8c093b 7131 iwl3945_set_rate(priv);
b481de9c
ZY		 7132
7133 if (memcmp(&priv->active_rxon,
7134 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 7135 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7136 else
7137 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
7138
7139 IWL_DEBUG_MAC80211("leave\n");
7140
7141 mutex_unlock(&priv->mutex);
7142
7143 return 0;
7144}
7145
bb8c093b 7146static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 7147{
7148 int rc = 0;
7149
7150 if (priv->status & STATUS_EXIT_PENDING)
7151 return;
7152
7153 /* The following should be done only at AP bring up */
7154 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
7155
7156 /* RXON - unassoc (to set timing command) */
7157 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7158 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7159
7160 /* RXON Timing */
bb8c093b
CH		 7161 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
7162 iwl3945_setup_rxon_timing(priv);
7163 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 7164 sizeof(priv->rxon_timing), &priv->rxon_timing);
7165 if (rc)
7166 IWL_WARNING("REPLY_RXON_TIMING failed - "
7167 "Attempting to continue.\n");
7168
7169 /* FIXME: what should be the assoc_id for AP? */
7170 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
7171 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
7172 priv->staging_rxon.flags |=
7173 RXON_FLG_SHORT_PREAMBLE_MSK;
7174 else
7175 priv->staging_rxon.flags &=
7176 ~RXON_FLG_SHORT_PREAMBLE_MSK;
7177
7178 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
7179 if (priv->assoc_capability &
7180 WLAN_CAPABILITY_SHORT_SLOT_TIME)
7181 priv->staging_rxon.flags |=
7182 RXON_FLG_SHORT_SLOT_MSK;
7183 else
7184 priv->staging_rxon.flags &=
7185 ~RXON_FLG_SHORT_SLOT_MSK;
7186
7187 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
7188 priv->staging_rxon.flags &=
7189 ~RXON_FLG_SHORT_SLOT_MSK;
7190 }
7191 /* restore RXON assoc */
7192 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 7193 iwl3945_commit_rxon(priv);
7194 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 7195 }
bb8c093b 7196 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 7197
7198 /* FIXME - we need to add code here to detect a totally new
7199 * configuration, reset the AP, unassoc, rxon timing, assoc,
7200 * clear sta table, add BCAST sta... */
7201}
7202
bb8c093b 7203static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, int if_id,
b481de9c
ZY		 7204 struct ieee80211_if_conf *conf)
7205{
bb8c093b 7206 struct iwl3945_priv *priv = hw->priv;
0795af57 7207 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 7208 unsigned long flags;
7209 int rc;
7210
7211 if (conf == NULL)
7212 return -EIO;
7213
4150c572
JB		 7214 /* XXX: this MUST use conf->mac_addr */
7215
b481de9c
ZY		 7216 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
7217 (!conf->beacon || !conf->ssid_len)) {
7218 IWL_DEBUG_MAC80211
7219 ("Leaving in AP mode because HostAPD is not ready.\n");
7220 return 0;
7221 }
7222
7223 mutex_lock(&priv->mutex);
7224
7225 IWL_DEBUG_MAC80211("enter: interface id %d\n", if_id);
7226 if (conf->bssid)
0795af57
JP		 7227 IWL_DEBUG_MAC80211("bssid: %s\n",
7228 print_mac(mac, conf->bssid));
b481de9c 7229
4150c572
JB		 7230/*
7231 * very dubious code was here; the probe filtering flag is never set:
7232 *
b481de9c
ZY		 7233 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
7234 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572
JB		 7235 */
7236 if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
b481de9c
ZY		 7237 IWL_DEBUG_MAC80211("leave - scanning\n");
7238 mutex_unlock(&priv->mutex);
7239 return 0;
7240 }
7241
7242 if (priv->interface_id != if_id) {
7243 IWL_DEBUG_MAC80211("leave - interface_id != if_id\n");
7244 mutex_unlock(&priv->mutex);
7245 return 0;
7246 }
7247
7248 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
7249 if (!conf->bssid) {
7250 conf->bssid = priv->mac_addr;
7251 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 7252 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
7253 print_mac(mac, conf->bssid));
b481de9c
ZY		 7254 }
7255 if (priv->ibss_beacon)
7256 dev_kfree_skb(priv->ibss_beacon);
7257
7258 priv->ibss_beacon = conf->beacon;
7259 }
7260
7261 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
7262 !is_multicast_ether_addr(conf->bssid)) {
7263 /* If there is currently a HW scan going on in the background
7264 * then we need to cancel it else the RXON below will fail. */
bb8c093b 7265 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 7266 IWL_WARNING("Aborted scan still in progress "
7267 "after 100ms\n");
7268 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
7269 mutex_unlock(&priv->mutex);
7270 return -EAGAIN;
7271 }
7272 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
7273
7274 /* TODO: Audit driver for usage of these members and see
7275 * if mac80211 deprecates them (priv->bssid looks like it
7276 * shouldn't be there, but I haven't scanned the IBSS code
7277 * to verify) - jpk */
7278 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
7279
7280 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7281 iwl3945_config_ap(priv);
b481de9c 7282 else {
bb8c093b 7283 rc = iwl3945_commit_rxon(priv);
b481de9c 7284 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 7285 iwl3945_add_station(priv,
556f8db7 7286 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 7287 }
7288
7289 } else {
bb8c093b 7290 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 7291 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7292 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7293 }
7294
7295 spin_lock_irqsave(&priv->lock, flags);
7296 if (!conf->ssid_len)
7297 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7298 else
7299 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7300
7301 priv->essid_len = conf->ssid_len;
7302 spin_unlock_irqrestore(&priv->lock, flags);
7303
7304 IWL_DEBUG_MAC80211("leave\n");
7305 mutex_unlock(&priv->mutex);
7306
7307 return 0;
7308}
7309
bb8c093b 7310static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7311 unsigned int changed_flags,
7312 unsigned int *total_flags,
7313 int mc_count, struct dev_addr_list *mc_list)
7314{
7315 /*
7316 * XXX: dummy
bb8c093b 7317 * see also iwl3945_connection_init_rx_config
4150c572
JB		 7318 */
7319 *total_flags = 0;
7320}
7321
bb8c093b 7322static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7323 struct ieee80211_if_init_conf *conf)
7324{
bb8c093b 7325 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7326
7327 IWL_DEBUG_MAC80211("enter\n");
7328
7329 mutex_lock(&priv->mutex);
6ef89d0a 7330
bb8c093b 7331 iwl3945_scan_cancel_timeout(priv, 100);
6ef89d0a
MA		 7332 cancel_delayed_work(&priv->post_associate);
7333 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7334 iwl3945_commit_rxon(priv);
6ef89d0a 7335
b481de9c
ZY		 7336 if (priv->interface_id == conf->if_id) {
7337 priv->interface_id = 0;
7338 memset(priv->bssid, 0, ETH_ALEN);
7339 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7340 priv->essid_len = 0;
7341 }
7342 mutex_unlock(&priv->mutex);
7343
7344 IWL_DEBUG_MAC80211("leave\n");
7345
7346}
7347
bb8c093b 7348static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7349{
7350 int rc = 0;
7351 unsigned long flags;
bb8c093b 7352 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7353
7354 IWL_DEBUG_MAC80211("enter\n");
7355
15e869d8 7356 mutex_lock(&priv->mutex);
b481de9c
ZY		 7357 spin_lock_irqsave(&priv->lock, flags);
7358
bb8c093b 7359 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7360 rc = -EIO;
7361 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7362 goto out_unlock;
7363 }
7364
7365 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7366 rc = -EIO;
7367 IWL_ERROR("ERROR: APs don't scan\n");
7368 goto out_unlock;
7369 }
7370
7878a5a4
MA		 7371 /* we don't schedule scan within next_scan_jiffies period */
7372 if (priv->next_scan_jiffies &&
7373 time_after(priv->next_scan_jiffies, jiffies)) {
7374 rc = -EAGAIN;
7375 goto out_unlock;
7376 }
b481de9c 7377 /* if we just finished scan ask for delay */
7878a5a4
MA		 7378 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7379 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY		 7380 rc = -EAGAIN;
7381 goto out_unlock;
7382 }
7383 if (len) {
7878a5a4 7384 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7385 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7386
7387 priv->one_direct_scan = 1;
7388 priv->direct_ssid_len = (u8)
7389 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7390 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7391 } else
7392 priv->one_direct_scan = 0;
b481de9c 7393
bb8c093b 7394 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7395
7396 IWL_DEBUG_MAC80211("leave\n");
7397
7398out_unlock:
7399 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7400 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7401
7402 return rc;
7403}
7404
bb8c093b 7405static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7406 const u8 *local_addr, const u8 *addr,
7407 struct ieee80211_key_conf *key)
7408{
bb8c093b 7409 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7410 int rc = 0;
7411 u8 sta_id;
7412
7413 IWL_DEBUG_MAC80211("enter\n");
7414
bb8c093b 7415 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7416 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7417 return -EOPNOTSUPP;
7418 }
7419
7420 if (is_zero_ether_addr(addr))
7421 /* only support pairwise keys */
7422 return -EOPNOTSUPP;
7423
bb8c093b 7424 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7425 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7426 DECLARE_MAC_BUF(mac);
7427
7428 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7429 print_mac(mac, addr));
b481de9c
ZY		 7430 return -EINVAL;
7431 }
7432
7433 mutex_lock(&priv->mutex);
7434
bb8c093b 7435 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7436
b481de9c
ZY		 7437 switch (cmd) {
7438 case SET_KEY:
bb8c093b 7439 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7440 if (!rc) {
bb8c093b
CH		 7441 iwl3945_set_rxon_hwcrypto(priv, 1);
7442 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7443 key->hw_key_idx = sta_id;
7444 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7445 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7446 }
7447 break;
7448 case DISABLE_KEY:
bb8c093b 7449 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7450 if (!rc) {
bb8c093b
CH		 7451 iwl3945_set_rxon_hwcrypto(priv, 0);
7452 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7453 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7454 }
7455 break;
7456 default:
7457 rc = -EINVAL;
7458 }
7459
7460 IWL_DEBUG_MAC80211("leave\n");
7461 mutex_unlock(&priv->mutex);
7462
7463 return rc;
7464}
7465
bb8c093b 7466static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY		 7467 const struct ieee80211_tx_queue_params *params)
7468{
bb8c093b 7469 struct iwl3945_priv *priv = hw->priv;
c8b0e6e1 7470#ifdef CONFIG_IWL3945_QOS
b481de9c
ZY		 7471 unsigned long flags;
7472 int q;
0054b34d 7473#endif /* CONFIG_IWL3945_QOS */
b481de9c
ZY		 7474
7475 IWL_DEBUG_MAC80211("enter\n");
7476
bb8c093b 7477 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7478 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7479 return -EIO;
7480 }
7481
7482 if (queue >= AC_NUM) {
7483 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7484 return 0;
7485 }
7486
c8b0e6e1 7487#ifdef CONFIG_IWL3945_QOS
b481de9c
ZY		 7488 if (!priv->qos_data.qos_enable) {
7489 priv->qos_data.qos_active = 0;
7490 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7491 return 0;
7492 }
7493 q = AC_NUM - 1 - queue;
7494
7495 spin_lock_irqsave(&priv->lock, flags);
7496
7497 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7498 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7499 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7500 priv->qos_data.def_qos_parm.ac[q].edca_txop =
7501 cpu_to_le16((params->burst_time * 100));
7502
7503 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7504 priv->qos_data.qos_active = 1;
7505
7506 spin_unlock_irqrestore(&priv->lock, flags);
7507
7508 mutex_lock(&priv->mutex);
7509 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7510 iwl3945_activate_qos(priv, 1);
7511 else if (priv->assoc_id && iwl3945_is_associated(priv))
7512 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7513
7514 mutex_unlock(&priv->mutex);
7515
c8b0e6e1 7516#endif /*CONFIG_IWL3945_QOS */
b481de9c
ZY		 7517
7518 IWL_DEBUG_MAC80211("leave\n");
7519 return 0;
7520}
7521
bb8c093b 7522static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7523 struct ieee80211_tx_queue_stats *stats)
7524{
bb8c093b 7525 struct iwl3945_priv *priv = hw->priv;
b481de9c 7526 int i, avail;
bb8c093b
CH		 7527 struct iwl3945_tx_queue *txq;
7528 struct iwl3945_queue *q;
b481de9c
ZY		 7529 unsigned long flags;
7530
7531 IWL_DEBUG_MAC80211("enter\n");
7532
bb8c093b 7533 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7534 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7535 return -EIO;
7536 }
7537
7538 spin_lock_irqsave(&priv->lock, flags);
7539
7540 for (i = 0; i < AC_NUM; i++) {
7541 txq = &priv->txq[i];
7542 q = &txq->q;
bb8c093b 7543 avail = iwl3945_queue_space(q);
b481de9c
ZY		 7544
7545 stats->data[i].len = q->n_window - avail;
7546 stats->data[i].limit = q->n_window - q->high_mark;
7547 stats->data[i].count = q->n_window;
7548
7549 }
7550 spin_unlock_irqrestore(&priv->lock, flags);
7551
7552 IWL_DEBUG_MAC80211("leave\n");
7553
7554 return 0;
7555}
7556
bb8c093b 7557static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7558 struct ieee80211_low_level_stats *stats)
7559{
7560 IWL_DEBUG_MAC80211("enter\n");
7561 IWL_DEBUG_MAC80211("leave\n");
7562
7563 return 0;
7564}
7565
bb8c093b 7566static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7567{
7568 IWL_DEBUG_MAC80211("enter\n");
7569 IWL_DEBUG_MAC80211("leave\n");
7570
7571 return 0;
7572}
7573
bb8c093b 7574static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7575{
bb8c093b 7576 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7577 unsigned long flags;
7578
7579 mutex_lock(&priv->mutex);
7580 IWL_DEBUG_MAC80211("enter\n");
7581
c8b0e6e1 7582#ifdef CONFIG_IWL3945_QOS
bb8c093b 7583 iwl3945_reset_qos(priv);
b481de9c
ZY		 7584#endif
7585 cancel_delayed_work(&priv->post_associate);
7586
7587 spin_lock_irqsave(&priv->lock, flags);
7588 priv->assoc_id = 0;
7589 priv->assoc_capability = 0;
7590 priv->call_post_assoc_from_beacon = 0;
7591
7592 /* new association get rid of ibss beacon skb */
7593 if (priv->ibss_beacon)
7594 dev_kfree_skb(priv->ibss_beacon);
7595
7596 priv->ibss_beacon = NULL;
7597
7598 priv->beacon_int = priv->hw->conf.beacon_int;
7599 priv->timestamp1 = 0;
7600 priv->timestamp0 = 0;
7601 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7602 priv->beacon_int = 0;
7603
7604 spin_unlock_irqrestore(&priv->lock, flags);
7605
15e869d8
MA		 7606 /* we are restarting association process
7607 * clear RXON_FILTER_ASSOC_MSK bit
7608 */
7609 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7610 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7611 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7612 iwl3945_commit_rxon(priv);
15e869d8
MA		 7613 }
7614
b481de9c
ZY		 7615 /* Per mac80211.h: This is only used in IBSS mode... */
7616 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7617
b481de9c
ZY		 7618 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7619 mutex_unlock(&priv->mutex);
7620 return;
7621 }
7622
bb8c093b 7623 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7624 IWL_DEBUG_MAC80211("leave - not ready\n");
7625 mutex_unlock(&priv->mutex);
7626 return;
7627 }
7628
7629 priv->only_active_channel = 0;
7630
bb8c093b 7631 iwl3945_set_rate(priv);
b481de9c
ZY		 7632
7633 mutex_unlock(&priv->mutex);
7634
7635 IWL_DEBUG_MAC80211("leave\n");
7636
7637}
7638
bb8c093b 7639static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7640 struct ieee80211_tx_control *control)
7641{
bb8c093b 7642 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7643 unsigned long flags;
7644
7645 mutex_lock(&priv->mutex);
7646 IWL_DEBUG_MAC80211("enter\n");
7647
bb8c093b 7648 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7649 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7650 mutex_unlock(&priv->mutex);
7651 return -EIO;
7652 }
7653
7654 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7655 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7656 mutex_unlock(&priv->mutex);
7657 return -EIO;
7658 }
7659
7660 spin_lock_irqsave(&priv->lock, flags);
7661
7662 if (priv->ibss_beacon)
7663 dev_kfree_skb(priv->ibss_beacon);
7664
7665 priv->ibss_beacon = skb;
7666
7667 priv->assoc_id = 0;
7668
7669 IWL_DEBUG_MAC80211("leave\n");
7670 spin_unlock_irqrestore(&priv->lock, flags);
7671
c8b0e6e1 7672#ifdef CONFIG_IWL3945_QOS
bb8c093b 7673 iwl3945_reset_qos(priv);
b481de9c
ZY		 7674#endif
7675
7676 queue_work(priv->workqueue, &priv->post_associate.work);
7677
7678 mutex_unlock(&priv->mutex);
7679
7680 return 0;
7681}
7682
7683/*****************************************************************************
7684 *
7685 * sysfs attributes
7686 *
7687 *****************************************************************************/
7688
c8b0e6e1 7689#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7690
7691/*
7692 * The following adds a new attribute to the sysfs representation
7693 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7694 * used for controlling the debug level.
7695 *
7696 * See the level definitions in iwl for details.
7697 */
7698
7699static ssize_t show_debug_level(struct device_driver *d, char *buf)
7700{
bb8c093b 7701 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7702}
7703static ssize_t store_debug_level(struct device_driver *d,
7704 const char *buf, size_t count)
7705{
7706 char *p = (char *)buf;
7707 u32 val;
7708
7709 val = simple_strtoul(p, &p, 0);
7710 if (p == buf)
7711 printk(KERN_INFO DRV_NAME
7712 ": %s is not in hex or decimal form.\n", buf);
7713 else
bb8c093b 7714 iwl3945_debug_level = val;
b481de9c
ZY		 7715
7716 return strnlen(buf, count);
7717}
7718
7719static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7720 show_debug_level, store_debug_level);
7721
c8b0e6e1 7722#endif /* CONFIG_IWL3945_DEBUG */
b481de9c
ZY		 7723
7724static ssize_t show_rf_kill(struct device *d,
7725 struct device_attribute *attr, char *buf)
7726{
7727 /*
7728 * 0 - RF kill not enabled
7729 * 1 - SW based RF kill active (sysfs)
7730 * 2 - HW based RF kill active
7731 * 3 - Both HW and SW based RF kill active
7732 */
bb8c093b 7733 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7734 int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
7735 (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
7736
7737 return sprintf(buf, "%i\n", val);
7738}
7739
7740static ssize_t store_rf_kill(struct device *d,
7741 struct device_attribute *attr,
7742 const char *buf, size_t count)
7743{
bb8c093b 7744 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7745
7746 mutex_lock(&priv->mutex);
bb8c093b 7747 iwl3945_radio_kill_sw(priv, buf[0] == '1');
b481de9c
ZY		 7748 mutex_unlock(&priv->mutex);
7749
7750 return count;
7751}
7752
7753static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
7754
7755static ssize_t show_temperature(struct device *d,
7756 struct device_attribute *attr, char *buf)
7757{
bb8c093b 7758 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7759
bb8c093b 7760 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7761 return -EAGAIN;
7762
bb8c093b 7763 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7764}
7765
7766static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7767
7768static ssize_t show_rs_window(struct device *d,
7769 struct device_attribute *attr,
7770 char *buf)
7771{
bb8c093b
CH		 7772 struct iwl3945_priv *priv = d->driver_data;
7773 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7774}
7775static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7776
7777static ssize_t show_tx_power(struct device *d,
7778 struct device_attribute *attr, char *buf)
7779{
bb8c093b 7780 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7781 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7782}
7783
7784static ssize_t store_tx_power(struct device *d,
7785 struct device_attribute *attr,
7786 const char *buf, size_t count)
7787{
bb8c093b 7788 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7789 char *p = (char *)buf;
7790 u32 val;
7791
7792 val = simple_strtoul(p, &p, 10);
7793 if (p == buf)
7794 printk(KERN_INFO DRV_NAME
7795 ": %s is not in decimal form.\n", buf);
7796 else
bb8c093b 7797 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7798
7799 return count;
7800}
7801
7802static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7803
7804static ssize_t show_flags(struct device *d,
7805 struct device_attribute *attr, char *buf)
7806{
bb8c093b 7807 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7808
7809 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7810}
7811
7812static ssize_t store_flags(struct device *d,
7813 struct device_attribute *attr,
7814 const char *buf, size_t count)
7815{
bb8c093b 7816 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7817 u32 flags = simple_strtoul(buf, NULL, 0);
7818
7819 mutex_lock(&priv->mutex);
7820 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7821 /* Cancel any currently running scans... */
bb8c093b 7822 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7823 IWL_WARNING("Could not cancel scan.\n");
7824 else {
7825 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7826 flags);
7827 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7828 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7829 }
7830 }
7831 mutex_unlock(&priv->mutex);
7832
7833 return count;
7834}
7835
7836static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7837
7838static ssize_t show_filter_flags(struct device *d,
7839 struct device_attribute *attr, char *buf)
7840{
bb8c093b 7841 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7842
7843 return sprintf(buf, "0x%04X\n",
7844 le32_to_cpu(priv->active_rxon.filter_flags));
7845}
7846
7847static ssize_t store_filter_flags(struct device *d,
7848 struct device_attribute *attr,
7849 const char *buf, size_t count)
7850{
bb8c093b 7851 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7852 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7853
7854 mutex_lock(&priv->mutex);
7855 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7856 /* Cancel any currently running scans... */
bb8c093b 7857 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7858 IWL_WARNING("Could not cancel scan.\n");
7859 else {
7860 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7861 "0x%04X\n", filter_flags);
7862 priv->staging_rxon.filter_flags =
7863 cpu_to_le32(filter_flags);
bb8c093b 7864 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7865 }
7866 }
7867 mutex_unlock(&priv->mutex);
7868
7869 return count;
7870}
7871
7872static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7873 store_filter_flags);
7874
7875static ssize_t show_tune(struct device *d,
7876 struct device_attribute *attr, char *buf)
7877{
bb8c093b 7878 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7879
7880 return sprintf(buf, "0x%04X\n",
7881 (priv->phymode << 8) |
7882 le16_to_cpu(priv->active_rxon.channel));
7883}
7884
bb8c093b 7885static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode);
b481de9c
ZY		 7886
7887static ssize_t store_tune(struct device *d,
7888 struct device_attribute *attr,
7889 const char *buf, size_t count)
7890{
bb8c093b 7891 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7892 char *p = (char *)buf;
7893 u16 tune = simple_strtoul(p, &p, 0);
7894 u8 phymode = (tune >> 8) & 0xff;
7895 u16 channel = tune & 0xff;
7896
7897 IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
7898
7899 mutex_lock(&priv->mutex);
7900 if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
7901 (priv->phymode != phymode)) {
bb8c093b 7902 const struct iwl3945_channel_info *ch_info;
b481de9c 7903
bb8c093b 7904 ch_info = iwl3945_get_channel_info(priv, phymode, channel);
b481de9c
ZY		 7905 if (!ch_info) {
7906 IWL_WARNING("Requested invalid phymode/channel "
7907 "combination: %d %d\n", phymode, channel);
7908 mutex_unlock(&priv->mutex);
7909 return -EINVAL;
7910 }
7911
7912 /* Cancel any currently running scans... */
bb8c093b 7913 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7914 IWL_WARNING("Could not cancel scan.\n");
7915 else {
7916 IWL_DEBUG_INFO("Committing phymode and "
7917 "rxon.channel = %d %d\n",
7918 phymode, channel);
7919
bb8c093b
CH		 7920 iwl3945_set_rxon_channel(priv, phymode, channel);
7921 iwl3945_set_flags_for_phymode(priv, phymode);
b481de9c 7922
bb8c093b
CH		 7923 iwl3945_set_rate(priv);
7924 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7925 }
7926 }
7927 mutex_unlock(&priv->mutex);
7928
7929 return count;
7930}
7931
7932static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
7933
c8b0e6e1 7934#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7935
7936static ssize_t show_measurement(struct device *d,
7937 struct device_attribute *attr, char *buf)
7938{
bb8c093b
CH		 7939 struct iwl3945_priv *priv = dev_get_drvdata(d);
7940 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7941 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7942 u8 *data = (u8 *) & measure_report;
7943 unsigned long flags;
7944
7945 spin_lock_irqsave(&priv->lock, flags);
7946 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7947 spin_unlock_irqrestore(&priv->lock, flags);
7948 return 0;
7949 }
7950 memcpy(&measure_report, &priv->measure_report, size);
7951 priv->measurement_status = 0;
7952 spin_unlock_irqrestore(&priv->lock, flags);
7953
7954 while (size && (PAGE_SIZE - len)) {
7955 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7956 PAGE_SIZE - len, 1);
7957 len = strlen(buf);
7958 if (PAGE_SIZE - len)
7959 buf[len++] = '\n';
7960
7961 ofs += 16;
7962 size -= min(size, 16U);
7963 }
7964
7965 return len;
7966}
7967
7968static ssize_t store_measurement(struct device *d,
7969 struct device_attribute *attr,
7970 const char *buf, size_t count)
7971{
bb8c093b 7972 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7973 struct ieee80211_measurement_params params = {
7974 .channel = le16_to_cpu(priv->active_rxon.channel),
7975 .start_time = cpu_to_le64(priv->last_tsf),
7976 .duration = cpu_to_le16(1),
7977 };
7978 u8 type = IWL_MEASURE_BASIC;
7979 u8 buffer[32];
7980 u8 channel;
7981
7982 if (count) {
7983 char *p = buffer;
7984 strncpy(buffer, buf, min(sizeof(buffer), count));
7985 channel = simple_strtoul(p, NULL, 0);
7986 if (channel)
7987 params.channel = channel;
7988
7989 p = buffer;
7990 while (*p && *p != ' ')
7991 p++;
7992 if (*p)
7993 type = simple_strtoul(p + 1, NULL, 0);
7994 }
7995
7996 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7997 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7998 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7999
8000 return count;
8001}
8002
8003static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
8004 show_measurement, store_measurement);
c8b0e6e1 8005#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c
ZY		 8006
8007static ssize_t show_rate(struct device *d,
8008 struct device_attribute *attr, char *buf)
8009{
bb8c093b 8010 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8011 unsigned long flags;
8012 int i;
8013
8014 spin_lock_irqsave(&priv->sta_lock, flags);
8015 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
8016 i = priv->stations[IWL_AP_ID].current_rate.s.rate;
8017 else
8018 i = priv->stations[IWL_STA_ID].current_rate.s.rate;
8019 spin_unlock_irqrestore(&priv->sta_lock, flags);
8020
bb8c093b 8021 i = iwl3945_rate_index_from_plcp(i);
b481de9c
ZY		 8022 if (i == -1)
8023 return sprintf(buf, "0\n");
8024
8025 return sprintf(buf, "%d%s\n",
bb8c093b
CH		 8026 (iwl3945_rates[i].ieee >> 1),
8027 (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
b481de9c
ZY		 8028}
8029
8030static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
8031
8032static ssize_t store_retry_rate(struct device *d,
8033 struct device_attribute *attr,
8034 const char *buf, size_t count)
8035{
bb8c093b 8036 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8037
8038 priv->retry_rate = simple_strtoul(buf, NULL, 0);
8039 if (priv->retry_rate <= 0)
8040 priv->retry_rate = 1;
8041
8042 return count;
8043}
8044
8045static ssize_t show_retry_rate(struct device *d,
8046 struct device_attribute *attr, char *buf)
8047{
bb8c093b 8048 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8049 return sprintf(buf, "%d", priv->retry_rate);
8050}
8051
8052static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
8053 store_retry_rate);
8054
8055static ssize_t store_power_level(struct device *d,
8056 struct device_attribute *attr,
8057 const char *buf, size_t count)
8058{
bb8c093b 8059 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8060 int rc;
8061 int mode;
8062
8063 mode = simple_strtoul(buf, NULL, 0);
8064 mutex_lock(&priv->mutex);
8065
bb8c093b 8066 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 8067 rc = -EAGAIN;
8068 goto out;
8069 }
8070
8071 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
8072 mode = IWL_POWER_AC;
8073 else
8074 mode |= IWL_POWER_ENABLED;
8075
8076 if (mode != priv->power_mode) {
bb8c093b 8077 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 8078 if (rc) {
8079 IWL_DEBUG_MAC80211("failed setting power mode.\n");
8080 goto out;
8081 }
8082 priv->power_mode = mode;
8083 }
8084
8085 rc = count;
8086
8087 out:
8088 mutex_unlock(&priv->mutex);
8089 return rc;
8090}
8091
8092#define MAX_WX_STRING 80
8093
8094/* Values are in microsecond */
8095static const s32 timeout_duration[] = {
8096 350000,
8097 250000,
8098 75000,
8099 37000,
8100 25000,
8101};
8102static const s32 period_duration[] = {
8103 400000,
8104 700000,
8105 1000000,
8106 1000000,
8107 1000000
8108};
8109
8110static ssize_t show_power_level(struct device *d,
8111 struct device_attribute *attr, char *buf)
8112{
bb8c093b 8113 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8114 int level = IWL_POWER_LEVEL(priv->power_mode);
8115 char *p = buf;
8116
8117 p += sprintf(p, "%d ", level);
8118 switch (level) {
8119 case IWL_POWER_MODE_CAM:
8120 case IWL_POWER_AC:
8121 p += sprintf(p, "(AC)");
8122 break;
8123 case IWL_POWER_BATTERY:
8124 p += sprintf(p, "(BATTERY)");
8125 break;
8126 default:
8127 p += sprintf(p,
8128 "(Timeout %dms, Period %dms)",
8129 timeout_duration[level - 1] / 1000,
8130 period_duration[level - 1] / 1000);
8131 }
8132
8133 if (!(priv->power_mode & IWL_POWER_ENABLED))
8134 p += sprintf(p, " OFF\n");
8135 else
8136 p += sprintf(p, " \n");
8137
8138 return (p - buf + 1);
8139
8140}
8141
8142static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
8143 store_power_level);
8144
8145static ssize_t show_channels(struct device *d,
8146 struct device_attribute *attr, char *buf)
8147{
bb8c093b 8148 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8149 int len = 0, i;
8150 struct ieee80211_channel *channels = NULL;
8151 const struct ieee80211_hw_mode *hw_mode = NULL;
8152 int count = 0;
8153
bb8c093b 8154 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 8155 return -EAGAIN;
8156
bb8c093b 8157 hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211G);
b481de9c 8158 if (!hw_mode)
bb8c093b 8159 hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211B);
b481de9c
ZY		 8160 if (hw_mode) {
8161 channels = hw_mode->channels;
8162 count = hw_mode->num_channels;
8163 }
8164
8165 len +=
8166 sprintf(&buf[len],
8167 "Displaying %d channels in 2.4GHz band "
8168 "(802.11bg):\n", count);
8169
8170 for (i = 0; i < count; i++)
8171 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
8172 channels[i].chan,
8173 channels[i].power_level,
8174 channels[i].
8175 flag & IEEE80211_CHAN_W_RADAR_DETECT ?
8176 " (IEEE 802.11h required)" : "",
8177 (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
8178 || (channels[i].
8179 flag &
8180 IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
8181 ", IBSS",
8182 channels[i].
8183 flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
8184 "active/passive" : "passive only");
8185
bb8c093b 8186 hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211A);
b481de9c
ZY		 8187 if (hw_mode) {
8188 channels = hw_mode->channels;
8189 count = hw_mode->num_channels;
8190 } else {
8191 channels = NULL;
8192 count = 0;
8193 }
8194
8195 len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
8196 "(802.11a):\n", count);
8197
8198 for (i = 0; i < count; i++)
8199 len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
8200 channels[i].chan,
8201 channels[i].power_level,
8202 channels[i].
8203 flag & IEEE80211_CHAN_W_RADAR_DETECT ?
8204 " (IEEE 802.11h required)" : "",
8205 (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
8206 || (channels[i].
8207 flag &
8208 IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
8209 ", IBSS",
8210 channels[i].
8211 flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
8212 "active/passive" : "passive only");
8213
8214 return len;
8215}
8216
8217static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
8218
8219static ssize_t show_statistics(struct device *d,
8220 struct device_attribute *attr, char *buf)
8221{
bb8c093b
CH		 8222 struct iwl3945_priv *priv = dev_get_drvdata(d);
8223 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 8224 u32 len = 0, ofs = 0;
8225 u8 *data = (u8 *) & priv->statistics;
8226 int rc = 0;
8227
bb8c093b 8228 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 8229 return -EAGAIN;
8230
8231 mutex_lock(&priv->mutex);
bb8c093b 8232 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 8233 mutex_unlock(&priv->mutex);
8234
8235 if (rc) {
8236 len = sprintf(buf,
8237 "Error sending statistics request: 0x%08X\n", rc);
8238 return len;
8239 }
8240
8241 while (size && (PAGE_SIZE - len)) {
8242 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
8243 PAGE_SIZE - len, 1);
8244 len = strlen(buf);
8245 if (PAGE_SIZE - len)
8246 buf[len++] = '\n';
8247
8248 ofs += 16;
8249 size -= min(size, 16U);
8250 }
8251
8252 return len;
8253}
8254
8255static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
8256
8257static ssize_t show_antenna(struct device *d,
8258 struct device_attribute *attr, char *buf)
8259{
bb8c093b 8260 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 8261
bb8c093b 8262 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 8263 return -EAGAIN;
8264
8265 return sprintf(buf, "%d\n", priv->antenna);
8266}
8267
8268static ssize_t store_antenna(struct device *d,
8269 struct device_attribute *attr,
8270 const char *buf, size_t count)
8271{
8272 int ant;
bb8c093b 8273 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 8274
8275 if (count == 0)
8276 return 0;
8277
8278 if (sscanf(buf, "%1i", &ant) != 1) {
8279 IWL_DEBUG_INFO("not in hex or decimal form.\n");
8280 return count;
8281 }
8282
8283 if ((ant >= 0) && (ant <= 2)) {
8284 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 8285 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 8286 } else
8287 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
8288
8289
8290 return count;
8291}
8292
8293static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
8294
8295static ssize_t show_status(struct device *d,
8296 struct device_attribute *attr, char *buf)
8297{
bb8c093b
CH		 8298 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
8299 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 8300 return -EAGAIN;
8301 return sprintf(buf, "0x%08x\n", (int)priv->status);
8302}
8303
8304static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
8305
8306static ssize_t dump_error_log(struct device *d,
8307 struct device_attribute *attr,
8308 const char *buf, size_t count)
8309{
8310 char *p = (char *)buf;
8311
8312 if (p[0] == '1')
bb8c093b 8313 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 8314
8315 return strnlen(buf, count);
8316}
8317
8318static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
8319
8320static ssize_t dump_event_log(struct device *d,
8321 struct device_attribute *attr,
8322 const char *buf, size_t count)
8323{
8324 char *p = (char *)buf;
8325
8326 if (p[0] == '1')
bb8c093b 8327 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 8328
8329 return strnlen(buf, count);
8330}
8331
8332static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
8333
8334/*****************************************************************************
8335 *
8336 * driver setup and teardown
8337 *
8338 *****************************************************************************/
8339
bb8c093b 8340static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 8341{
8342 priv->workqueue = create_workqueue(DRV_NAME);
8343
8344 init_waitqueue_head(&priv->wait_command_queue);
8345
bb8c093b
CH		 8346 INIT_WORK(&priv->up, iwl3945_bg_up);
8347 INIT_WORK(&priv->restart, iwl3945_bg_restart);
8348 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
8349 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
8350 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
8351 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
8352 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
8353 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
8354 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
8355 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
8356 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
8357 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
8358
8359 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 8360
8361 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 8362 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 8363}
8364
bb8c093b 8365static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 8366{
bb8c093b 8367 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 8368
e47eb6ad 8369 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 8370 cancel_delayed_work(&priv->scan_check);
8371 cancel_delayed_work(&priv->alive_start);
8372 cancel_delayed_work(&priv->post_associate);
8373 cancel_work_sync(&priv->beacon_update);
8374}
8375
bb8c093b 8376static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 8377 &dev_attr_antenna.attr,
8378 &dev_attr_channels.attr,
8379 &dev_attr_dump_errors.attr,
8380 &dev_attr_dump_events.attr,
8381 &dev_attr_flags.attr,
8382 &dev_attr_filter_flags.attr,
c8b0e6e1 8383#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 8384 &dev_attr_measurement.attr,
8385#endif
8386 &dev_attr_power_level.attr,
8387 &dev_attr_rate.attr,
8388 &dev_attr_retry_rate.attr,
8389 &dev_attr_rf_kill.attr,
8390 &dev_attr_rs_window.attr,
8391 &dev_attr_statistics.attr,
8392 &dev_attr_status.attr,
8393 &dev_attr_temperature.attr,
8394 &dev_attr_tune.attr,
8395 &dev_attr_tx_power.attr,
8396
8397 NULL
8398};
8399
bb8c093b 8400static struct attribute_group iwl3945_attribute_group = {
b481de9c 8401 .name = NULL, /* put in device directory */
bb8c093b 8402 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 8403};
8404
bb8c093b
CH		 8405static struct ieee80211_ops iwl3945_hw_ops = {
8406 .tx = iwl3945_mac_tx,
8407 .start = iwl3945_mac_start,
8408 .stop = iwl3945_mac_stop,
8409 .add_interface = iwl3945_mac_add_interface,
8410 .remove_interface = iwl3945_mac_remove_interface,
8411 .config = iwl3945_mac_config,
8412 .config_interface = iwl3945_mac_config_interface,
8413 .configure_filter = iwl3945_configure_filter,
8414 .set_key = iwl3945_mac_set_key,
8415 .get_stats = iwl3945_mac_get_stats,
8416 .get_tx_stats = iwl3945_mac_get_tx_stats,
8417 .conf_tx = iwl3945_mac_conf_tx,
8418 .get_tsf = iwl3945_mac_get_tsf,
8419 .reset_tsf = iwl3945_mac_reset_tsf,
8420 .beacon_update = iwl3945_mac_beacon_update,
8421 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 8422};
8423
bb8c093b 8424static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 8425{
8426 int err = 0;
8427 u32 pci_id;
bb8c093b 8428 struct iwl3945_priv *priv;
b481de9c
ZY		 8429 struct ieee80211_hw *hw;
8430 int i;
8431
6440adb5
BC		 8432 /* Disabling hardware scan means that mac80211 will perform scans
8433 * "the hard way", rather than using device's scan. */
bb8c093b 8434 if (iwl3945_param_disable_hw_scan) {
b481de9c 8435 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 8436 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 8437 }
8438
bb8c093b
CH		 8439 if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
8440 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c
ZY		 8441 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
8442 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
8443 err = -EINVAL;
8444 goto out;
8445 }
8446
8447 /* mac80211 allocates memory for this device instance, including
8448 * space for this driver's private structure */
bb8c093b 8449 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 8450 if (hw == NULL) {
8451 IWL_ERROR("Can not allocate network device\n");
8452 err = -ENOMEM;
8453 goto out;
8454 }
8455 SET_IEEE80211_DEV(hw, &pdev->dev);
8456
f51359a8
JB		 8457 hw->rate_control_algorithm = "iwl-3945-rs";
8458
b481de9c
ZY		 8459 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
8460 priv = hw->priv;
8461 priv->hw = hw;
8462
8463 priv->pci_dev = pdev;
6440adb5
BC		 8464
8465 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 8466 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 8467#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8468 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 8469 atomic_set(&priv->restrict_refcnt, 0);
8470#endif
8471 priv->retry_rate = 1;
8472
8473 priv->ibss_beacon = NULL;
8474
8475 /* Tell mac80211 and its clients (e.g. Wireless Extensions)
8476 * the range of signal quality values that we'll provide.
8477 * Negative values for level/noise indicate that we'll provide dBm.
8478 * For WE, at least, non-0 values here *enable* display of values
8479 * in app (iwconfig). */
8480 hw->max_rssi = -20; /* signal level, negative indicates dBm */
8481 hw->max_noise = -20; /* noise level, negative indicates dBm */
8482 hw->max_signal = 100; /* link quality indication (%) */
8483
8484 /* Tell mac80211 our Tx characteristics */
8485 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
8486
6440adb5 8487 /* 4 EDCA QOS priorities */
b481de9c
ZY		 8488 hw->queues = 4;
8489
8490 spin_lock_init(&priv->lock);
8491 spin_lock_init(&priv->power_data.lock);
8492 spin_lock_init(&priv->sta_lock);
8493 spin_lock_init(&priv->hcmd_lock);
8494
8495 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8496 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8497
8498 INIT_LIST_HEAD(&priv->free_frames);
8499
8500 mutex_init(&priv->mutex);
8501 if (pci_enable_device(pdev)) {
8502 err = -ENODEV;
8503 goto out_ieee80211_free_hw;
8504 }
8505
8506 pci_set_master(pdev);
8507
6440adb5 8508 /* Clear the driver's (not device's) station table */
bb8c093b 8509 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8510
8511 priv->data_retry_limit = -1;
8512 priv->ieee_channels = NULL;
8513 priv->ieee_rates = NULL;
8514 priv->phymode = -1;
8515
8516 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8517 if (!err)
8518 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8519 if (err) {
8520 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8521 goto out_pci_disable_device;
8522 }
8523
8524 pci_set_drvdata(pdev, priv);
8525 err = pci_request_regions(pdev, DRV_NAME);
8526 if (err)
8527 goto out_pci_disable_device;
6440adb5 8528
b481de9c
ZY		 8529 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8530 * PCI Tx retries from interfering with C3 CPU state */
8531 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8532
b481de9c
ZY		 8533 priv->hw_base = pci_iomap(pdev, 0, 0);
8534 if (!priv->hw_base) {
8535 err = -ENODEV;
8536 goto out_pci_release_regions;
8537 }
8538
8539 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8540 (unsigned long long) pci_resource_len(pdev, 0));
8541 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8542
8543 /* Initialize module parameter values here */
8544
6440adb5 8545 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8546 if (iwl3945_param_disable) {
b481de9c
ZY		 8547 set_bit(STATUS_RF_KILL_SW, &priv->status);
8548 IWL_DEBUG_INFO("Radio disabled.\n");
8549 }
8550
8551 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8552
8553 pci_id =
8554 (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
8555
8556 switch (pci_id) {
8557 case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
8558 case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
8559 case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
8560 case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
8561 priv->is_abg = 0;
8562 break;
8563
8564 /*
8565 * Rest are assumed ABG SKU -- if this is not the
8566 * case then the card will get the wrong 'Detected'
8567 * line in the kernel log however the code that
8568 * initializes the GEO table will detect no A-band
8569 * channels and remove the is_abg mask.
8570 */
8571 default:
8572 priv->is_abg = 1;
8573 break;
8574 }
8575
8576 printk(KERN_INFO DRV_NAME
8577 ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
8578 priv->is_abg ? "A" : "");
8579
8580 /* Device-specific setup */
bb8c093b 8581 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c
ZY		 8582 IWL_ERROR("failed to set hw settings\n");
8583 mutex_unlock(&priv->mutex);
8584 goto out_iounmap;
8585 }
8586
c8b0e6e1 8587#ifdef CONFIG_IWL3945_QOS
bb8c093b 8588 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8589 priv->qos_data.qos_enable = 1;
8590
bb8c093b 8591 iwl3945_reset_qos(priv);
b481de9c
ZY		 8592
8593 priv->qos_data.qos_active = 0;
8594 priv->qos_data.qos_cap.val = 0;
c8b0e6e1 8595#endif /* CONFIG_IWL3945_QOS */
b481de9c 8596
bb8c093b
CH		 8597 iwl3945_set_rxon_channel(priv, MODE_IEEE80211G, 6);
8598 iwl3945_setup_deferred_work(priv);
8599 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8600
8601 priv->rates_mask = IWL_RATES_MASK;
8602 /* If power management is turned on, default to AC mode */
8603 priv->power_mode = IWL_POWER_AC;
8604 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8605
bb8c093b 8606 iwl3945_disable_interrupts(priv);
49df2b33 8607
b481de9c
ZY		 8608 pci_enable_msi(pdev);
8609
bb8c093b 8610 err = request_irq(pdev->irq, iwl3945_isr, IRQF_SHARED, DRV_NAME, priv);
b481de9c
ZY		 8611 if (err) {
8612 IWL_ERROR("Error allocating IRQ %d\n", pdev->irq);
8613 goto out_disable_msi;
8614 }
8615
8616 mutex_lock(&priv->mutex);
8617
bb8c093b 8618 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8619 if (err) {
8620 IWL_ERROR("failed to create sysfs device attributes\n");
8621 mutex_unlock(&priv->mutex);
8622 goto out_release_irq;
8623 }
8624
8625 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
8626 * ucode filename and max sizes are card-specific. */
bb8c093b 8627 err = iwl3945_read_ucode(priv);
b481de9c
ZY		 8628 if (err) {
8629 IWL_ERROR("Could not read microcode: %d\n", err);
8630 mutex_unlock(&priv->mutex);
8631 goto out_pci_alloc;
8632 }
8633
8634 mutex_unlock(&priv->mutex);
8635
01ebd063 8636 IWL_DEBUG_INFO("Queueing UP work.\n");
b481de9c
ZY		 8637
8638 queue_work(priv->workqueue, &priv->up);
8639
8640 return 0;
8641
8642 out_pci_alloc:
bb8c093b 8643 iwl3945_dealloc_ucode_pci(priv);
b481de9c 8644
bb8c093b 8645 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8646
8647 out_release_irq:
8648 free_irq(pdev->irq, priv);
8649
8650 out_disable_msi:
8651 pci_disable_msi(pdev);
8652 destroy_workqueue(priv->workqueue);
8653 priv->workqueue = NULL;
bb8c093b 8654 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8655
8656 out_iounmap:
8657 pci_iounmap(pdev, priv->hw_base);
8658 out_pci_release_regions:
8659 pci_release_regions(pdev);
8660 out_pci_disable_device:
8661 pci_disable_device(pdev);
8662 pci_set_drvdata(pdev, NULL);
8663 out_ieee80211_free_hw:
8664 ieee80211_free_hw(priv->hw);
8665 out:
8666 return err;
8667}
8668
bb8c093b 8669static void iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8670{
bb8c093b 8671 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8672 struct list_head *p, *q;
8673 int i;
8674
8675 if (!priv)
8676 return;
8677
8678 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8679
b481de9c 8680 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8681
bb8c093b 8682 iwl3945_down(priv);
b481de9c
ZY		 8683
8684 /* Free MAC hash list for ADHOC */
8685 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8686 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8687 list_del(p);
bb8c093b 8688 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8689 }
8690 }
8691
bb8c093b 8692 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8693
bb8c093b 8694 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8695
8696 if (priv->rxq.bd)
bb8c093b
CH		 8697 iwl3945_rx_queue_free(priv, &priv->rxq);
8698 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8699
bb8c093b
CH		 8700 iwl3945_unset_hw_setting(priv);
8701 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8702
8703 if (priv->mac80211_registered) {
8704 ieee80211_unregister_hw(priv->hw);
bb8c093b 8705 iwl3945_rate_control_unregister(priv->hw);
b481de9c
ZY		 8706 }
8707
6ef89d0a
MA		 8708 /*netif_stop_queue(dev); */
8709 flush_workqueue(priv->workqueue);
8710
bb8c093b 8711 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8712 * priv->workqueue... so we can't take down the workqueue
8713 * until now... */
8714 destroy_workqueue(priv->workqueue);
8715 priv->workqueue = NULL;
8716
8717 free_irq(pdev->irq, priv);
8718 pci_disable_msi(pdev);
8719 pci_iounmap(pdev, priv->hw_base);
8720 pci_release_regions(pdev);
8721 pci_disable_device(pdev);
8722 pci_set_drvdata(pdev, NULL);
8723
8724 kfree(priv->channel_info);
8725
8726 kfree(priv->ieee_channels);
8727 kfree(priv->ieee_rates);
8728
8729 if (priv->ibss_beacon)
8730 dev_kfree_skb(priv->ibss_beacon);
8731
8732 ieee80211_free_hw(priv->hw);
8733}
8734
8735#ifdef CONFIG_PM
8736
bb8c093b 8737static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8738{
bb8c093b 8739 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8740
b481de9c
ZY		 8741 set_bit(STATUS_IN_SUSPEND, &priv->status);
8742
8743 /* Take down the device; powers it off, etc. */
bb8c093b 8744 iwl3945_down(priv);
b481de9c
ZY		 8745
8746 if (priv->mac80211_registered)
8747 ieee80211_stop_queues(priv->hw);
8748
8749 pci_save_state(pdev);
8750 pci_disable_device(pdev);
8751 pci_set_power_state(pdev, PCI_D3hot);
8752
b481de9c
ZY		 8753 return 0;
8754}
8755
bb8c093b 8756static void iwl3945_resume(struct iwl3945_priv *priv)
b481de9c
ZY		 8757{
8758 unsigned long flags;
8759
8760 /* The following it a temporary work around due to the
8761 * suspend / resume not fully initializing the NIC correctly.
8762 * Without all of the following, resume will not attempt to take
8763 * down the NIC (it shouldn't really need to) and will just try
8764 * and bring the NIC back up. However that fails during the
bb8c093b
CH		 8765 * ucode verification process. This then causes iwl3945_down to be
8766 * called *after* iwl3945_hw_nic_init() has succeeded -- which
b481de9c
ZY		 8767 * then lets the next init sequence succeed. So, we've
8768 * replicated all of that NIC init code here... */
8769
bb8c093b 8770 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 8771
bb8c093b 8772 iwl3945_hw_nic_init(priv);
b481de9c 8773
bb8c093b
CH		 8774 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
8775 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 8776 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
bb8c093b
CH		 8777 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
8778 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
8779 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 8780
8781 /* tell the device to stop sending interrupts */
bb8c093b 8782 iwl3945_disable_interrupts(priv);
b481de9c
ZY		 8783
8784 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8785 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c 8786
bb8c093b
CH		 8787 if (!iwl3945_grab_nic_access(priv)) {
8788 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 8789 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 8790 iwl3945_release_nic_access(priv);
b481de9c
ZY		 8791 }
8792 spin_unlock_irqrestore(&priv->lock, flags);
8793
8794 udelay(5);
8795
bb8c093b 8796 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 8797
8798 /* Bring the device back up */
8799 clear_bit(STATUS_IN_SUSPEND, &priv->status);
8800 queue_work(priv->workqueue, &priv->up);
8801}
8802
bb8c093b 8803static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8804{
bb8c093b 8805 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8806 int err;
8807
8808 printk(KERN_INFO "Coming out of suspend...\n");
8809
b481de9c
ZY		 8810 pci_set_power_state(pdev, PCI_D0);
8811 err = pci_enable_device(pdev);
8812 pci_restore_state(pdev);
8813
8814 /*
8815 * Suspend/Resume resets the PCI configuration space, so we have to
8816 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
8817 * from interfering with C3 CPU state. pci_restore_state won't help
8818 * here since it only restores the first 64 bytes pci config header.
8819 */
8820 pci_write_config_byte(pdev, 0x41, 0x00);
8821
bb8c093b 8822 iwl3945_resume(priv);
b481de9c
ZY		 8823
8824 return 0;
8825}
8826
8827#endif /* CONFIG_PM */
8828
8829/*****************************************************************************
8830 *
8831 * driver and module entry point
8832 *
8833 *****************************************************************************/
8834
bb8c093b 8835static struct pci_driver iwl3945_driver = {
b481de9c 8836 .name = DRV_NAME,
bb8c093b
CH		 8837 .id_table = iwl3945_hw_card_ids,
8838 .probe = iwl3945_pci_probe,
8839 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8840#ifdef CONFIG_PM
bb8c093b
CH		 8841 .suspend = iwl3945_pci_suspend,
8842 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8843#endif
8844};
8845
bb8c093b 8846static int __init iwl3945_init(void)
b481de9c
ZY		 8847{
8848
8849 int ret;
8850 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8851 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
bb8c093b 8852 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8853 if (ret) {
8854 IWL_ERROR("Unable to initialize PCI module\n");
8855 return ret;
8856 }
c8b0e6e1 8857#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8858 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8859 if (ret) {
8860 IWL_ERROR("Unable to create driver sysfs file\n");
bb8c093b 8861 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY		 8862 return ret;
8863 }
8864#endif
8865
8866 return ret;
8867}
8868
bb8c093b 8869static void __exit iwl3945_exit(void)
b481de9c 8870{
c8b0e6e1 8871#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8872 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8873#endif
bb8c093b 8874 pci_unregister_driver(&iwl3945_driver);
b481de9c
ZY		 8875}
8876
bb8c093b 8877module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8878MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8879module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8880MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8881module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8882MODULE_PARM_DESC(hwcrypto,
8883 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8884module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8885MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8886module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8887MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8888
bb8c093b 8889module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8890MODULE_PARM_DESC(queues_num, "number of hw queues.");
8891
8892/* QoS */
bb8c093b 8893module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8894MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8895
bb8c093b
CH		 8896module_exit(iwl3945_exit);
8897module_init(iwl3945_init);
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