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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
b481de9c
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
WT
51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
b481de9c 55#include "iwl-3945.h"
5747d47f 56#include "iwl-core.h"
4a6547c7 57#include "iwl-helpers.h"
d20b3c65 58#include "iwl-dev.h"
81963d68 59#include "iwl-spectrum.h"
b481de9c 60
b481de9c
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61/*
62 * module name, copyright, version, etc.
b481de9c
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63 */
64
65#define DRV_DESCRIPTION \
66"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
67
d08853a3 68#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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69#define VD "d"
70#else
71#define VD
72#endif
73
81963d68
RC
74/*
75 * add "s" to indicate spectrum measurement included.
76 * we add it here to be consistent with previous releases in which
77 * this was configurable.
78 */
79#define DRV_VERSION IWLWIFI_VERSION VD "s"
1f447808 80#define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
b481de9c
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82
83MODULE_DESCRIPTION(DRV_DESCRIPTION);
84MODULE_VERSION(DRV_VERSION);
a7b75207 85MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
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86MODULE_LICENSE("GPL");
87
df878d8f
KA
88 /* module parameters */
89struct iwl_mod_params iwl3945_mod_params = {
9c74d9fb 90 .sw_crypto = 1,
af48d048 91 .restart_fw = 1,
df878d8f
KA
92 /* the rest are 0 by default */
93};
94
7e4bca5e
SO
95/**
96 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
97 * @priv: eeprom and antenna fields are used to determine antenna flags
98 *
99 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
100 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
101 *
102 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
103 * IWL_ANTENNA_MAIN - Force MAIN antenna
104 * IWL_ANTENNA_AUX - Force AUX antenna
105 */
106__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
107{
108 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
109
110 switch (iwl3945_mod_params.antenna) {
111 case IWL_ANTENNA_DIVERSITY:
112 return 0;
113
114 case IWL_ANTENNA_MAIN:
115 if (eeprom->antenna_switch_type)
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
118
119 case IWL_ANTENNA_AUX:
120 if (eeprom->antenna_switch_type)
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
123 }
124
125 /* bad antenna selector value */
126 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
127 iwl3945_mod_params.antenna);
128
129 return 0; /* "diversity" is default if error */
130}
131
6e21f15c 132static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
ZY
133 struct ieee80211_key_conf *keyconf,
134 u8 sta_id)
135{
136 unsigned long flags;
137 __le16 key_flags = 0;
6e21f15c
AK
138 int ret;
139
140 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
141 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
142
143 if (sta_id == priv->hw_params.bcast_sta_id)
144 key_flags |= STA_KEY_MULTICAST_MSK;
145
146 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
147 keyconf->hw_key_idx = keyconf->keyidx;
148 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 149
b481de9c 150 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
151 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
152 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
153 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
ZY
154 keyconf->keylen);
155
c587de0b 156 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 157 keyconf->keylen);
6e21f15c 158
c587de0b 159 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 160 == STA_KEY_FLG_NO_ENC)
c587de0b 161 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
162 iwl_get_free_ucode_key_index(priv);
163 /* else, we are overriding an existing key => no need to allocated room
164 * in uCode. */
165
c587de0b 166 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
167 "no space for a new key");
168
c587de0b
TW
169 priv->stations[sta_id].sta.key.key_flags = key_flags;
170 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
171 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 172
6e21f15c
AK
173 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
174
c587de0b 175 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 176
b481de9c
ZY
177 spin_unlock_irqrestore(&priv->sta_lock, flags);
178
6e21f15c
AK
179 return ret;
180}
181
182static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
183 struct ieee80211_key_conf *keyconf,
184 u8 sta_id)
185{
186 return -EOPNOTSUPP;
187}
188
189static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
190 struct ieee80211_key_conf *keyconf,
191 u8 sta_id)
192{
193 return -EOPNOTSUPP;
b481de9c
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194}
195
4a8a4322 196static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
201 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
202 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 203 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
204 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
205 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
206 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
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207 spin_unlock_irqrestore(&priv->sta_lock, flags);
208
e1623446 209 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 210 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
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211 return 0;
212}
213
fa11d525 214static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
215 struct ieee80211_key_conf *keyconf, u8 sta_id)
216{
217 int ret = 0;
218
219 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
220
221 switch (keyconf->alg) {
222 case ALG_CCMP:
223 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
224 break;
225 case ALG_TKIP:
226 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
227 break;
228 case ALG_WEP:
229 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
230 break;
231 default:
1e680233 232 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
233 ret = -EINVAL;
234 }
235
236 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
237 keyconf->alg, keyconf->keylen, keyconf->keyidx,
238 sta_id, ret);
239
240 return ret;
241}
242
243static int iwl3945_remove_static_key(struct iwl_priv *priv)
244{
245 int ret = -EOPNOTSUPP;
246
247 return ret;
248}
249
250static int iwl3945_set_static_key(struct iwl_priv *priv,
251 struct ieee80211_key_conf *key)
252{
253 if (key->alg == ALG_WEP)
254 return -EOPNOTSUPP;
255
256 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
257 return -EINVAL;
258}
259
4a8a4322 260static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
261{
262 struct list_head *element;
263
e1623446 264 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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265 priv->frames_count);
266
267 while (!list_empty(&priv->free_frames)) {
268 element = priv->free_frames.next;
269 list_del(element);
bb8c093b 270 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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271 priv->frames_count--;
272 }
273
274 if (priv->frames_count) {
39aadf8c 275 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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276 priv->frames_count);
277 priv->frames_count = 0;
278 }
279}
280
4a8a4322 281static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 282{
bb8c093b 283 struct iwl3945_frame *frame;
b481de9c
ZY
284 struct list_head *element;
285 if (list_empty(&priv->free_frames)) {
286 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
287 if (!frame) {
15b1687c 288 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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289 return NULL;
290 }
291
292 priv->frames_count++;
293 return frame;
294 }
295
296 element = priv->free_frames.next;
297 list_del(element);
bb8c093b 298 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
299}
300
4a8a4322 301static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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302{
303 memset(frame, 0, sizeof(*frame));
304 list_add(&frame->list, &priv->free_frames);
305}
306
4a8a4322 307unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 308 struct ieee80211_hdr *hdr,
73ec1cc2 309 int left)
b481de9c
ZY
310{
311
8ccde88a 312 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
313 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
314 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
315 return 0;
316
317 if (priv->ibss_beacon->len > left)
318 return 0;
319
320 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
321
322 return priv->ibss_beacon->len;
323}
324
4a8a4322 325static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 326{
bb8c093b 327 struct iwl3945_frame *frame;
b481de9c
ZY
328 unsigned int frame_size;
329 int rc;
330 u8 rate;
331
bb8c093b 332 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
333
334 if (!frame) {
15b1687c 335 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
336 "command.\n");
337 return -ENOMEM;
338 }
339
8ccde88a 340 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 341
bb8c093b 342 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 343
518099a8 344 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
345 &frame->u.cmd[0]);
346
bb8c093b 347 iwl3945_free_frame(priv, frame);
b481de9c
ZY
348
349 return rc;
350}
351
4a8a4322 352static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 353{
3832ec9d 354 if (priv->shared_virt)
f36d04ab
SG
355 dma_free_coherent(&priv->pci_dev->dev,
356 sizeof(struct iwl3945_shared),
357 priv->shared_virt,
358 priv->shared_phys);
b481de9c
ZY
359}
360
4a8a4322 361static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 362 struct ieee80211_tx_info *info,
c2acea8e 363 struct iwl_device_cmd *cmd,
b481de9c 364 struct sk_buff *skb_frag,
6e21f15c 365 int sta_id)
b481de9c 366{
9744c91f 367 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 368 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
369
370 switch (keyinfo->alg) {
371 case ALG_CCMP:
9744c91f
AK
372 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
373 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
e1623446 374 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
375 break;
376
377 case ALG_TKIP:
b481de9c
ZY
378 break;
379
380 case ALG_WEP:
9744c91f 381 tx_cmd->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 382 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
383
384 if (keyinfo->keylen == 13)
9744c91f 385 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 386
9744c91f 387 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 388
e1623446 389 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 390 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
391 break;
392
b481de9c 393 default:
978785a3 394 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
395 break;
396 }
397}
398
399/*
400 * handle build REPLY_TX command notification.
401 */
4a8a4322 402static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 403 struct iwl_device_cmd *cmd,
e039fa4a 404 struct ieee80211_tx_info *info,
e52119c5 405 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 406{
9744c91f
AK
407 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
408 __le32 tx_flags = tx_cmd->tx_flags;
fd7c8a40 409 __le16 fc = hdr->frame_control;
b481de9c 410
9744c91f 411 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 412 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 413 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 414 if (ieee80211_is_mgmt(fc))
b481de9c 415 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 416 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
417 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
418 tx_flags |= TX_CMD_FLG_TSF_MSK;
419 } else {
420 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422 }
423
9744c91f 424 tx_cmd->sta_id = std_id;
8b7b1e05 425 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
426 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
427
fd7c8a40
HH
428 if (ieee80211_is_data_qos(fc)) {
429 u8 *qc = ieee80211_get_qos_ctl(hdr);
9744c91f 430 tx_cmd->tid_tspec = qc[0] & 0xf;
b481de9c 431 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 432 } else {
b481de9c 433 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 434 }
b481de9c 435
37dc70fe 436 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
b481de9c
ZY
437
438 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
439 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
440
441 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
442 if (ieee80211_is_mgmt(fc)) {
443 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
9744c91f 444 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 445 else
9744c91f 446 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 447 } else {
9744c91f 448 tx_cmd->timeout.pm_frame_timeout = 0;
ab53d8af 449 }
b481de9c 450
9744c91f
AK
451 tx_cmd->driver_txop = 0;
452 tx_cmd->tx_flags = tx_flags;
453 tx_cmd->next_frame_len = 0;
b481de9c
ZY
454}
455
b481de9c
ZY
456/*
457 * start REPLY_TX command process
458 */
4a8a4322 459static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
460{
461 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 462 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9744c91f 463 struct iwl3945_tx_cmd *tx_cmd;
188cf6c7 464 struct iwl_tx_queue *txq = NULL;
d20b3c65 465 struct iwl_queue *q = NULL;
c2acea8e
JB
466 struct iwl_device_cmd *out_cmd;
467 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
468 dma_addr_t phys_addr;
469 dma_addr_t txcmd_phys;
e52119c5 470 int txq_id = skb_get_queue_mapping(skb);
df833b1d 471 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
472 u8 id;
473 u8 unicast;
b481de9c 474 u8 sta_id;
54dbb525 475 u8 tid = 0;
b481de9c 476 u16 seq_number = 0;
fd7c8a40 477 __le16 fc;
b481de9c 478 u8 wait_write_ptr = 0;
54dbb525 479 u8 *qc = NULL;
b481de9c 480 unsigned long flags;
b481de9c
ZY
481
482 spin_lock_irqsave(&priv->lock, flags);
775a6e27 483 if (iwl_is_rfkill(priv)) {
e1623446 484 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
485 goto drop_unlock;
486 }
487
e039fa4a 488 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 489 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
490 goto drop_unlock;
491 }
492
493 unicast = !is_multicast_ether_addr(hdr->addr1);
494 id = 0;
495
fd7c8a40 496 fc = hdr->frame_control;
b481de9c 497
d08853a3 498#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 499 if (ieee80211_is_auth(fc))
e1623446 500 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 501 else if (ieee80211_is_assoc_req(fc))
e1623446 502 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 503 else if (ieee80211_is_reassoc_req(fc))
e1623446 504 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
505#endif
506
aa065263 507 /* drop all non-injected data frame if we are not associated */
914233d6 508 if (ieee80211_is_data(fc) &&
aa065263 509 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
8ccde88a 510 (!iwl_is_associated(priv) ||
05c914fe 511 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 512 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
513 goto drop_unlock;
514 }
515
516 spin_unlock_irqrestore(&priv->lock, flags);
517
7294ec95 518 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
519
520 /* Find (or create) index into station table for destination station */
aa065263
GS
521 if (info->flags & IEEE80211_TX_CTL_INJECTED)
522 sta_id = priv->hw_params.bcast_sta_id;
523 else
524 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 525 if (sta_id == IWL_INVALID_STATION) {
e1623446 526 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 527 hdr->addr1);
b481de9c
ZY
528 goto drop;
529 }
530
e1623446 531 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 532
fd7c8a40
HH
533 if (ieee80211_is_data_qos(fc)) {
534 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 535 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
536 if (unlikely(tid >= MAX_TID_COUNT))
537 goto drop;
c587de0b 538 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
539 IEEE80211_SCTL_SEQ;
540 hdr->seq_ctrl = cpu_to_le16(seq_number) |
541 (hdr->seq_ctrl &
c1b4aa3f 542 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
543 seq_number += 0x10;
544 }
6440adb5
BC
545
546 /* Descriptor for chosen Tx queue */
188cf6c7 547 txq = &priv->txq[txq_id];
b481de9c
ZY
548 q = &txq->q;
549
dc57a303
ZY
550 if ((iwl_queue_space(q) < q->high_mark))
551 goto drop;
552
b481de9c
ZY
553 spin_lock_irqsave(&priv->lock, flags);
554
fc4b6853 555 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 556
6440adb5 557 /* Set up driver data for this TFD */
dbb6654c 558 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 559 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
560
561 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 562 out_cmd = txq->cmd[idx];
c2acea8e 563 out_meta = &txq->meta[idx];
9744c91f 564 tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 565 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
9744c91f 566 memset(tx_cmd, 0, sizeof(*tx_cmd));
6440adb5
BC
567
568 /*
569 * Set up the Tx-command (not MAC!) header.
570 * Store the chosen Tx queue and TFD index within the sequence field;
571 * after Tx, uCode's Tx response will return this value so driver can
572 * locate the frame within the tx queue and do post-tx processing.
573 */
b481de9c
ZY
574 out_cmd->hdr.cmd = REPLY_TX;
575 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 576 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
577
578 /* Copy MAC header from skb into command buffer */
9744c91f 579 memcpy(tx_cmd->hdr, hdr, hdr_len);
b481de9c 580
df833b1d
RC
581
582 if (info->control.hw_key)
583 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
584
585 /* TODO need this for burst mode later on */
586 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
587
588 /* set is_hcca to 0; it probably will never be implemented */
589 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
590
591 /* Total # bytes to be transmitted */
592 len = (u16)skb->len;
9744c91f 593 tx_cmd->len = cpu_to_le16(len);
df833b1d 594
20594eb0 595 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 596 iwl_update_stats(priv, true, fc, len);
9744c91f
AK
597 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
598 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
df833b1d
RC
599
600 if (!ieee80211_has_morefrags(hdr->frame_control)) {
601 txq->need_update = 1;
602 if (qc)
c587de0b 603 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
604 } else {
605 wait_write_ptr = 1;
606 txq->need_update = 0;
607 }
608
609 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
610 le16_to_cpu(out_cmd->hdr.sequence));
9744c91f
AK
611 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
612 iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
613 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
df833b1d
RC
614 ieee80211_hdrlen(fc));
615
6440adb5
BC
616 /*
617 * Use the first empty entry in this queue's command buffer array
618 * to contain the Tx command and MAC header concatenated together
619 * (payload data will be in another buffer).
620 * Size of this varies, due to varying MAC header length.
621 * If end is not dword aligned, we'll have 2 extra bytes at the end
622 * of the MAC header (device reads on dword boundaries).
623 * We'll tell device about this padding later.
624 */
3832ec9d 625 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 626 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
627
628 len_org = len;
629 len = (len + 3) & ~3;
630
631 if (len_org != len)
632 len_org = 1;
633 else
634 len_org = 0;
635
6440adb5
BC
636 /* Physical address of this Tx command's header (not MAC header!),
637 * within command buffer array. */
df833b1d
RC
638 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
639 len, PCI_DMA_TODEVICE);
640 /* we do not map meta data ... so we can safely access address to
641 * provide to unmap command*/
c2acea8e
JB
642 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
643 pci_unmap_len_set(out_meta, len, len);
b481de9c 644
6440adb5
BC
645 /* Add buffer containing Tx command and MAC(!) header to TFD's
646 * first entry */
7aaa1d79
SO
647 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
648 txcmd_phys, len, 1, 0);
b481de9c 649
b481de9c 650
6440adb5
BC
651 /* Set up TFD's 2nd entry to point directly to remainder of skb,
652 * if any (802.11 null frames have no payload). */
b481de9c
ZY
653 len = skb->len - hdr_len;
654 if (len) {
655 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
656 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
657 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
658 phys_addr, len,
659 0, U32_PAD(len));
b481de9c
ZY
660 }
661
b481de9c 662
6440adb5 663 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 664 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 665 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
666 spin_unlock_irqrestore(&priv->lock, flags);
667
d20b3c65 668 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
669 && priv->mac80211_registered) {
670 if (wait_write_ptr) {
671 spin_lock_irqsave(&priv->lock, flags);
672 txq->need_update = 1;
4f3602c8 673 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
674 spin_unlock_irqrestore(&priv->lock, flags);
675 }
676
e4e72fb4 677 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
678 }
679
680 return 0;
681
682drop_unlock:
683 spin_unlock_irqrestore(&priv->lock, flags);
684drop:
685 return -1;
686}
687
b481de9c
ZY
688#define BEACON_TIME_MASK_LOW 0x00FFFFFF
689#define BEACON_TIME_MASK_HIGH 0xFF000000
690#define TIME_UNIT 1024
691
692/*
693 * extended beacon time format
694 * time in usec will be changed into a 32-bit value in 8:24 format
695 * the high 1 byte is the beacon counts
696 * the lower 3 bytes is the time in usec within one beacon interval
697 */
698
bb8c093b 699static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
700{
701 u32 quot;
702 u32 rem;
703 u32 interval = beacon_interval * 1024;
704
705 if (!interval || !usec)
706 return 0;
707
708 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
709 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
710
711 return (quot << 24) + rem;
712}
713
714/* base is usually what we get from ucode with each received frame,
715 * the same as HW timer counter counting down
716 */
717
bb8c093b 718static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
719{
720 u32 base_low = base & BEACON_TIME_MASK_LOW;
721 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
722 u32 interval = beacon_interval * TIME_UNIT;
723 u32 res = (base & BEACON_TIME_MASK_HIGH) +
724 (addon & BEACON_TIME_MASK_HIGH);
725
726 if (base_low > addon_low)
727 res += base_low - addon_low;
728 else if (base_low < addon_low) {
729 res += interval + base_low - addon_low;
730 res += (1 << 24);
731 } else
732 res += (1 << 24);
733
734 return cpu_to_le32(res);
735}
736
4a8a4322 737static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
738 struct ieee80211_measurement_params *params,
739 u8 type)
740{
600c0e11 741 struct iwl_spectrum_cmd spectrum;
2f301227 742 struct iwl_rx_packet *pkt;
c2d79b48 743 struct iwl_host_cmd cmd = {
b481de9c
ZY
744 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
745 .data = (void *)&spectrum,
c2acea8e 746 .flags = CMD_WANT_SKB,
b481de9c
ZY
747 };
748 u32 add_time = le64_to_cpu(params->start_time);
749 int rc;
750 int spectrum_resp_status;
751 int duration = le16_to_cpu(params->duration);
752
8ccde88a 753 if (iwl_is_associated(priv))
b481de9c 754 add_time =
bb8c093b 755 iwl3945_usecs_to_beacons(
b481de9c
ZY
756 le64_to_cpu(params->start_time) - priv->last_tsf,
757 le16_to_cpu(priv->rxon_timing.beacon_interval));
758
759 memset(&spectrum, 0, sizeof(spectrum));
760
761 spectrum.channel_count = cpu_to_le16(1);
762 spectrum.flags =
763 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
764 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
765 cmd.len = sizeof(spectrum);
766 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
767
8ccde88a 768 if (iwl_is_associated(priv))
b481de9c 769 spectrum.start_time =
bb8c093b 770 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
771 add_time,
772 le16_to_cpu(priv->rxon_timing.beacon_interval));
773 else
774 spectrum.start_time = 0;
775
776 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
777 spectrum.channels[0].channel = params->channel;
778 spectrum.channels[0].type = type;
8ccde88a 779 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
780 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
781 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
782
518099a8 783 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
784 if (rc)
785 return rc;
786
2f301227
ZY
787 pkt = (struct iwl_rx_packet *)cmd.reply_page;
788 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 789 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
790 rc = -EIO;
791 }
792
2f301227 793 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
b481de9c
ZY
794 switch (spectrum_resp_status) {
795 case 0: /* Command will be handled */
2f301227 796 if (pkt->u.spectrum.id != 0xff) {
e1623446 797 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
2f301227 798 pkt->u.spectrum.id);
b481de9c
ZY
799 priv->measurement_status &= ~MEASUREMENT_READY;
800 }
801 priv->measurement_status |= MEASUREMENT_ACTIVE;
802 rc = 0;
803 break;
804
805 case 1: /* Command will not be handled */
806 rc = -EAGAIN;
807 break;
808 }
809
64a76b50 810 iwl_free_pages(priv, cmd.reply_page);
b481de9c
ZY
811
812 return rc;
813}
b481de9c 814
4a8a4322 815static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 816 struct iwl_rx_mem_buffer *rxb)
b481de9c 817{
2f301227 818 struct iwl_rx_packet *pkt = rxb_addr(rxb);
3d24a9f7 819 struct iwl_alive_resp *palive;
b481de9c
ZY
820 struct delayed_work *pwork;
821
822 palive = &pkt->u.alive_frame;
823
e1623446 824 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
825 "0x%01X 0x%01X\n",
826 palive->is_valid, palive->ver_type,
827 palive->ver_subtype);
828
829 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 830 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
831 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
832 sizeof(struct iwl_alive_resp));
b481de9c
ZY
833 pwork = &priv->init_alive_start;
834 } else {
e1623446 835 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 836 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 837 sizeof(struct iwl_alive_resp));
b481de9c 838 pwork = &priv->alive_start;
bb8c093b 839 iwl3945_disable_events(priv);
b481de9c
ZY
840 }
841
842 /* We delay the ALIVE response by 5ms to
843 * give the HW RF Kill time to activate... */
844 if (palive->is_valid == UCODE_VALID_OK)
845 queue_delayed_work(priv->workqueue, pwork,
846 msecs_to_jiffies(5));
847 else
39aadf8c 848 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
849}
850
4a8a4322 851static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 852 struct iwl_rx_mem_buffer *rxb)
b481de9c 853{
c7e035a9 854#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 855 struct iwl_rx_packet *pkt = rxb_addr(rxb);
c7e035a9 856#endif
b481de9c 857
e1623446 858 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
859 return;
860}
861
bb8c093b 862static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 863{
4a8a4322
AK
864 struct iwl_priv *priv =
865 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
866 struct sk_buff *beacon;
867
868 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 869 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
870
871 if (!beacon) {
15b1687c 872 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
873 return;
874 }
875
876 mutex_lock(&priv->mutex);
877 /* new beacon skb is allocated every time; dispose previous.*/
878 if (priv->ibss_beacon)
879 dev_kfree_skb(priv->ibss_beacon);
880
881 priv->ibss_beacon = beacon;
882 mutex_unlock(&priv->mutex);
883
bb8c093b 884 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
885}
886
4a8a4322 887static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 888 struct iwl_rx_mem_buffer *rxb)
b481de9c 889{
d08853a3 890#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 891 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b 892 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
893 u8 rate = beacon->beacon_notify_hdr.rate;
894
e1623446 895 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
896 "tsf %d %d rate %d\n",
897 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
898 beacon->beacon_notify_hdr.failure_frame,
899 le32_to_cpu(beacon->ibss_mgr_status),
900 le32_to_cpu(beacon->high_tsf),
901 le32_to_cpu(beacon->low_tsf), rate);
902#endif
903
05c914fe 904 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
905 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
906 queue_work(priv->workqueue, &priv->beacon_update);
907}
908
b481de9c
ZY
909/* Handle notification from uCode that card's power state is changing
910 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 911static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 912 struct iwl_rx_mem_buffer *rxb)
b481de9c 913{
2f301227 914 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
915 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
916 unsigned long status = priv->status;
917
4c423a2b 918 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
919 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
920 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
921
5d49f498 922 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
923 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
924
925 if (flags & HW_CARD_DISABLED)
926 set_bit(STATUS_RF_KILL_HW, &priv->status);
927 else
928 clear_bit(STATUS_RF_KILL_HW, &priv->status);
929
930
af0053d6 931 iwl_scan_cancel(priv);
b481de9c
ZY
932
933 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
934 test_bit(STATUS_RF_KILL_HW, &priv->status)))
935 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
936 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
937 else
938 wake_up_interruptible(&priv->wait_command_queue);
939}
940
941/**
bb8c093b 942 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
943 *
944 * Setup the RX handlers for each of the reply types sent from the uCode
945 * to the host.
946 *
947 * This function chains into the hardware specific files for them to setup
948 * any hardware specific handlers as well.
949 */
4a8a4322 950static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 951{
bb8c093b
CH
952 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
953 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 954 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 955 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
956 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
957 iwl_rx_spectrum_measure_notif;
030f05ed 958 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 959 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 960 iwl_rx_pm_debug_statistics_notif;
bb8c093b 961 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 962
9fbab516
BC
963 /*
964 * The same handler is used for both the REPLY to a discrete
965 * statistics request from the host as well as for the periodic
966 * statistics notifications (after received beacons) from the uCode.
b481de9c 967 */
bb8c093b
CH
968 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
969 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 970
cade0eb2 971 iwl_setup_rx_scan_handlers(priv);
bb8c093b 972 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 973
9fbab516 974 /* Set up hardware specific Rx handlers */
bb8c093b 975 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
976}
977
b481de9c
ZY
978/************************** RX-FUNCTIONS ****************************/
979/*
980 * Rx theory of operation
981 *
982 * The host allocates 32 DMA target addresses and passes the host address
983 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
984 * 0 to 31
985 *
986 * Rx Queue Indexes
987 * The host/firmware share two index registers for managing the Rx buffers.
988 *
989 * The READ index maps to the first position that the firmware may be writing
990 * to -- the driver can read up to (but not including) this position and get
991 * good data.
992 * The READ index is managed by the firmware once the card is enabled.
993 *
994 * The WRITE index maps to the last position the driver has read from -- the
995 * position preceding WRITE is the last slot the firmware can place a packet.
996 *
997 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
998 * WRITE = READ.
999 *
9fbab516 1000 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1001 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1002 *
9fbab516 1003 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1004 * and fire the RX interrupt. The driver can then query the READ index and
1005 * process as many packets as possible, moving the WRITE index forward as it
1006 * resets the Rx queue buffers with new memory.
1007 *
1008 * The management in the driver is as follows:
1009 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1010 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1011 * to replenish the iwl->rxq->rx_free.
bb8c093b 1012 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1013 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1014 * 'processed' and 'read' driver indexes as well)
1015 * + A received packet is processed and handed to the kernel network stack,
1016 * detached from the iwl->rxq. The driver 'processed' index is updated.
1017 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1018 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1019 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1020 * were enough free buffers and RX_STALLED is set it is cleared.
1021 *
1022 *
1023 * Driver sequence:
1024 *
9fbab516 1025 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1026 * iwl3945_rx_queue_restock
9fbab516 1027 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1028 * queue, updates firmware pointers, and updates
1029 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1030 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1031 *
1032 * -- enable interrupts --
6100b588 1033 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1034 * READ INDEX, detaching the SKB from the pool.
1035 * Moves the packet buffer from queue to rx_used.
bb8c093b 1036 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1037 * slots.
1038 * ...
1039 *
1040 */
1041
b481de9c 1042/**
9fbab516 1043 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1044 */
4a8a4322 1045static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1046 dma_addr_t dma_addr)
1047{
1048 return cpu_to_le32((u32)dma_addr);
1049}
1050
1051/**
bb8c093b 1052 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1053 *
9fbab516 1054 * If there are slots in the RX queue that need to be restocked,
b481de9c 1055 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1056 * as we can, pulling from rx_free.
b481de9c
ZY
1057 *
1058 * This moves the 'write' index forward to catch up with 'processed', and
1059 * also updates the memory address in the firmware to reference the new
1060 * target buffer.
1061 */
7bfedc59 1062static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1063{
cc2f362c 1064 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1065 struct list_head *element;
6100b588 1066 struct iwl_rx_mem_buffer *rxb;
b481de9c 1067 unsigned long flags;
7bfedc59 1068 int write;
b481de9c
ZY
1069
1070 spin_lock_irqsave(&rxq->lock, flags);
1071 write = rxq->write & ~0x7;
37d68317 1072 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1073 /* Get next free Rx buffer, remove from free list */
b481de9c 1074 element = rxq->rx_free.next;
6100b588 1075 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1076 list_del(element);
6440adb5
BC
1077
1078 /* Point to Rx buffer via next RBD in circular buffer */
2f301227 1079 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
b481de9c
ZY
1080 rxq->queue[rxq->write] = rxb;
1081 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1082 rxq->free_count--;
1083 }
1084 spin_unlock_irqrestore(&rxq->lock, flags);
1085 /* If the pre-allocated buffer pool is dropping low, schedule to
1086 * refill it */
1087 if (rxq->free_count <= RX_LOW_WATERMARK)
1088 queue_work(priv->workqueue, &priv->rx_replenish);
1089
1090
6440adb5
BC
1091 /* If we've added more space for the firmware to place data, tell it.
1092 * Increment device's write pointer in multiples of 8. */
d14d4440 1093 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1094 || (abs(rxq->write - rxq->read) > 7)) {
1095 spin_lock_irqsave(&rxq->lock, flags);
1096 rxq->need_update = 1;
1097 spin_unlock_irqrestore(&rxq->lock, flags);
7bfedc59 1098 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c 1099 }
b481de9c
ZY
1100}
1101
1102/**
bb8c093b 1103 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1104 *
1105 * When moving to rx_free an SKB is allocated for the slot.
1106 *
bb8c093b 1107 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1108 * This is called as a scheduled work item (except for during initialization)
b481de9c 1109 */
d14d4440 1110static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1111{
cc2f362c 1112 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1113 struct list_head *element;
6100b588 1114 struct iwl_rx_mem_buffer *rxb;
2f301227 1115 struct page *page;
b481de9c 1116 unsigned long flags;
29b1b268 1117 gfp_t gfp_mask = priority;
72240498
AK
1118
1119 while (1) {
1120 spin_lock_irqsave(&rxq->lock, flags);
1121
1122 if (list_empty(&rxq->rx_used)) {
1123 spin_unlock_irqrestore(&rxq->lock, flags);
1124 return;
1125 }
72240498 1126 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1127
f82a924c 1128 if (rxq->free_count > RX_LOW_WATERMARK)
29b1b268 1129 gfp_mask |= __GFP_NOWARN;
2f301227
ZY
1130
1131 if (priv->hw_params.rx_page_order > 0)
29b1b268 1132 gfp_mask |= __GFP_COMP;
2f301227 1133
6440adb5 1134 /* Alloc a new receive buffer */
29b1b268 1135 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
2f301227 1136 if (!page) {
b481de9c 1137 if (net_ratelimit())
f82a924c
RC
1138 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1139 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1140 net_ratelimit())
1141 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1142 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1143 rxq->free_count);
b481de9c
ZY
1144 /* We don't reschedule replenish work here -- we will
1145 * call the restock method and if it still needs
1146 * more buffers it will schedule replenish */
1147 break;
1148 }
12342c47 1149
de0bd508
RC
1150 spin_lock_irqsave(&rxq->lock, flags);
1151 if (list_empty(&rxq->rx_used)) {
1152 spin_unlock_irqrestore(&rxq->lock, flags);
2f301227 1153 __free_pages(page, priv->hw_params.rx_page_order);
de0bd508
RC
1154 return;
1155 }
1156 element = rxq->rx_used.next;
1157 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1158 list_del(element);
1159 spin_unlock_irqrestore(&rxq->lock, flags);
1160
2f301227 1161 rxb->page = page;
6440adb5 1162 /* Get physical address of RB/SKB */
2f301227
ZY
1163 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
1164 PAGE_SIZE << priv->hw_params.rx_page_order,
1165 PCI_DMA_FROMDEVICE);
72240498
AK
1166
1167 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1168
b481de9c
ZY
1169 list_add_tail(&rxb->list, &rxq->rx_free);
1170 rxq->free_count++;
2f301227
ZY
1171 priv->alloc_rxb_page++;
1172
72240498 1173 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1174 }
5c0eef96
MA
1175}
1176
df833b1d
RC
1177void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1178{
1179 unsigned long flags;
1180 int i;
1181 spin_lock_irqsave(&rxq->lock, flags);
1182 INIT_LIST_HEAD(&rxq->rx_free);
1183 INIT_LIST_HEAD(&rxq->rx_used);
1184 /* Fill the rx_used queue with _all_ of the Rx buffers */
1185 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1186 /* In the reset function, these buffers may have been allocated
1187 * to an SKB, so we need to unmap and free potential storage */
2f301227
ZY
1188 if (rxq->pool[i].page != NULL) {
1189 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1190 PAGE_SIZE << priv->hw_params.rx_page_order,
1191 PCI_DMA_FROMDEVICE);
64a76b50 1192 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1193 rxq->pool[i].page = NULL;
df833b1d
RC
1194 }
1195 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1196 }
1197
1198 /* Set us so that we have processed and used all buffers, but have
1199 * not restocked the Rx queue with fresh buffers */
1200 rxq->read = rxq->write = 0;
d14d4440 1201 rxq->write_actual = 0;
2f301227 1202 rxq->free_count = 0;
df833b1d
RC
1203 spin_unlock_irqrestore(&rxq->lock, flags);
1204}
df833b1d 1205
5c0eef96
MA
1206void iwl3945_rx_replenish(void *data)
1207{
4a8a4322 1208 struct iwl_priv *priv = data;
5c0eef96
MA
1209 unsigned long flags;
1210
d14d4440 1211 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1212
1213 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1214 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1215 spin_unlock_irqrestore(&priv->lock, flags);
1216}
1217
d14d4440
AK
1218static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1219{
1220 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1221
1222 iwl3945_rx_queue_restock(priv);
1223}
1224
1225
df833b1d
RC
1226/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1227 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1228 * This free routine walks the list of POOL entries and if SKB is set to
1229 * non NULL it is unmapped and freed
1230 */
1231static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1232{
1233 int i;
1234 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
2f301227
ZY
1235 if (rxq->pool[i].page != NULL) {
1236 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1237 PAGE_SIZE << priv->hw_params.rx_page_order,
1238 PCI_DMA_FROMDEVICE);
64a76b50 1239 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1240 rxq->pool[i].page = NULL;
df833b1d
RC
1241 }
1242 }
1243
f36d04ab
SG
1244 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1245 rxq->dma_addr);
1246 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
1247 rxq->rb_stts, rxq->rb_stts_dma);
df833b1d
RC
1248 rxq->bd = NULL;
1249 rxq->rb_stts = NULL;
1250}
df833b1d
RC
1251
1252
b481de9c
ZY
1253/* Convert linear signal-to-noise ratio into dB */
1254static u8 ratio2dB[100] = {
1255/* 0 1 2 3 4 5 6 7 8 9 */
1256 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1257 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1258 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1259 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1260 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1261 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1262 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1263 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1264 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1265 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1266};
1267
1268/* Calculates a relative dB value from a ratio of linear
1269 * (i.e. not dB) signal levels.
1270 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1271int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1272{
221c80cf
AB
1273 /* 1000:1 or higher just report as 60 dB */
1274 if (sig_ratio >= 1000)
b481de9c
ZY
1275 return 60;
1276
221c80cf 1277 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1278 * add 20 dB to make up for divide by 10 */
221c80cf 1279 if (sig_ratio >= 100)
3ac7f146 1280 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1281
1282 /* We shouldn't see this */
1283 if (sig_ratio < 1)
1284 return 0;
1285
1286 /* Use table for ratios 1:1 - 99:1 */
1287 return (int)ratio2dB[sig_ratio];
1288}
1289
b481de9c 1290/**
9fbab516 1291 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1292 *
1293 * Uses the priv->rx_handlers callback function array to invoke
1294 * the appropriate handlers, including command responses,
1295 * frame-received notifications, and other notifications.
1296 */
4a8a4322 1297static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1298{
6100b588 1299 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1300 struct iwl_rx_packet *pkt;
cc2f362c 1301 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1302 u32 r, i;
1303 int reclaim;
1304 unsigned long flags;
5c0eef96 1305 u8 fill_rx = 0;
d68ab680 1306 u32 count = 8;
d14d4440 1307 int total_empty = 0;
b481de9c 1308
6440adb5
BC
1309 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1310 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1311 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1312 i = rxq->read;
1313
d14d4440 1314 /* calculate total frames need to be restock after handling RX */
7300515d 1315 total_empty = r - rxq->write_actual;
d14d4440
AK
1316 if (total_empty < 0)
1317 total_empty += RX_QUEUE_SIZE;
1318
1319 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1320 fill_rx = 1;
b481de9c
ZY
1321 /* Rx interrupt, but nothing sent from uCode */
1322 if (i == r)
af472a95 1323 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1324
1325 while (i != r) {
1326 rxb = rxq->queue[i];
1327
9fbab516 1328 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1329 * then a bug has been introduced in the queue refilling
1330 * routines -- catch it here */
1331 BUG_ON(rxb == NULL);
1332
1333 rxq->queue[i] = NULL;
1334
2f301227
ZY
1335 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1336 PAGE_SIZE << priv->hw_params.rx_page_order,
1337 PCI_DMA_FROMDEVICE);
1338 pkt = rxb_addr(rxb);
b481de9c 1339
be1a71a1
JB
1340 trace_iwlwifi_dev_rx(priv, pkt,
1341 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
1342
b481de9c
ZY
1343 /* Reclaim a command buffer only if this packet is a response
1344 * to a (driver-originated) command.
1345 * If the packet (e.g. Rx frame) originated from uCode,
1346 * there is no command buffer to reclaim.
1347 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1348 * but apparently a few don't get set; catch them here. */
1349 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1350 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1351 (pkt->hdr.cmd != REPLY_TX);
1352
1353 /* Based on type of command response or notification,
1354 * handle those that need handling via function in
bb8c093b 1355 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1356 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1357 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c 1358 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
86ddbf62 1359 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1360 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
1361 } else {
1362 /* No handling needed */
2f301227
ZY
1363 IWL_DEBUG_RX(priv,
1364 "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1365 r, i, get_cmd_string(pkt->hdr.cmd),
1366 pkt->hdr.cmd);
1367 }
1368
29b1b268
ZY
1369 /*
1370 * XXX: After here, we should always check rxb->page
1371 * against NULL before touching it or its virtual
1372 * memory (pkt). Because some rx_handler might have
1373 * already taken or freed the pages.
1374 */
1375
b481de9c 1376 if (reclaim) {
2f301227
ZY
1377 /* Invoke any callbacks, transfer the buffer to caller,
1378 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1379 * as we reclaim the driver command queue */
29b1b268 1380 if (rxb->page)
732587ab 1381 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1382 else
39aadf8c 1383 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1384 }
1385
7300515d
ZY
1386 /* Reuse the page if possible. For notification packets and
1387 * SKBs that fail to Rx correctly, add them back into the
1388 * rx_free list for reuse later. */
1389 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1390 if (rxb->page != NULL) {
7300515d
ZY
1391 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1392 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1393 PCI_DMA_FROMDEVICE);
1394 list_add_tail(&rxb->list, &rxq->rx_free);
1395 rxq->free_count++;
1396 } else
1397 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1398
b481de9c 1399 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1400
b481de9c 1401 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1402 /* If there are a lot of unused frames,
1403 * restock the Rx queue so ucode won't assert. */
1404 if (fill_rx) {
1405 count++;
1406 if (count >= 8) {
7300515d 1407 rxq->read = i;
d14d4440 1408 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1409 count = 0;
1410 }
1411 }
b481de9c
ZY
1412 }
1413
1414 /* Backtrack one entry */
7300515d 1415 rxq->read = i;
d14d4440
AK
1416 if (fill_rx)
1417 iwl3945_rx_replenish_now(priv);
1418 else
1419 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1420}
1421
0359facc 1422/* call this function to flush any scheduled tasklet */
4a8a4322 1423static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1424{
a96a27f9 1425 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1426 synchronize_irq(priv->pci_dev->irq);
1427 tasklet_kill(&priv->irq_tasklet);
1428}
1429
b481de9c
ZY
1430static const char *desc_lookup(int i)
1431{
1432 switch (i) {
1433 case 1:
1434 return "FAIL";
1435 case 2:
1436 return "BAD_PARAM";
1437 case 3:
1438 return "BAD_CHECKSUM";
1439 case 4:
1440 return "NMI_INTERRUPT";
1441 case 5:
1442 return "SYSASSERT";
1443 case 6:
1444 return "FATAL_ERROR";
1445 }
1446
1447 return "UNKNOWN";
1448}
1449
1450#define ERROR_START_OFFSET (1 * sizeof(u32))
1451#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1452
b7a79404 1453void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1454{
1455 u32 i;
1456 u32 desc, time, count, base, data1;
1457 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1458
1459 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1460
bb8c093b 1461 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1462 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1463 return;
1464 }
1465
b481de9c 1466
5d49f498 1467 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1468
1469 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1470 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1471 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1472 priv->status, count);
b481de9c
ZY
1473 }
1474
15b1687c 1475 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1476 "ilink1 nmiPC Line\n");
1477 for (i = ERROR_START_OFFSET;
1478 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1479 i += ERROR_ELEM_SIZE) {
5d49f498 1480 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1481 time =
5d49f498 1482 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1483 blink1 =
5d49f498 1484 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1485 blink2 =
5d49f498 1486 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1487 ilink1 =
5d49f498 1488 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1489 ilink2 =
5d49f498 1490 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1491 data1 =
5d49f498 1492 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1493
15b1687c
WT
1494 IWL_ERR(priv,
1495 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1496 desc_lookup(desc), desc, time, blink1, blink2,
1497 ilink1, ilink2, data1);
be1a71a1
JB
1498 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
1499 0, blink1, blink2, ilink1, ilink2);
b481de9c 1500 }
b481de9c
ZY
1501}
1502
f58177b9 1503#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1504
1505/**
bb8c093b 1506 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1507 *
b481de9c 1508 */
b03d7d0f
WYG
1509static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1510 u32 num_events, u32 mode,
1511 int pos, char **buf, size_t bufsz)
b481de9c
ZY
1512{
1513 u32 i;
1514 u32 base; /* SRAM byte address of event log header */
1515 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1516 u32 ptr; /* SRAM byte address of log data */
1517 u32 ev, time, data; /* event log data */
e5854471 1518 unsigned long reg_flags;
b481de9c
ZY
1519
1520 if (num_events == 0)
b03d7d0f 1521 return pos;
b481de9c
ZY
1522
1523 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1524
1525 if (mode == 0)
1526 event_size = 2 * sizeof(u32);
1527 else
1528 event_size = 3 * sizeof(u32);
1529
1530 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1531
e5854471
BC
1532 /* Make sure device is powered up for SRAM reads */
1533 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1534 iwl_grab_nic_access(priv);
1535
1536 /* Set starting address; reads will auto-increment */
1537 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1538 rmb();
1539
b481de9c
ZY
1540 /* "time" is actually "data" for mode 0 (no timestamp).
1541 * place event id # at far right for easier visual parsing. */
1542 for (i = 0; i < num_events; i++) {
e5854471
BC
1543 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1544 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
15b1687c
WT
1545 if (mode == 0) {
1546 /* data, ev */
b03d7d0f
WYG
1547 if (bufsz) {
1548 pos += scnprintf(*buf + pos, bufsz - pos,
1549 "0x%08x:%04u\n",
1550 time, ev);
1551 } else {
1552 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1553 trace_iwlwifi_dev_ucode_event(priv, 0,
1554 time, ev);
1555 }
15b1687c 1556 } else {
e5854471 1557 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1558 if (bufsz) {
1559 pos += scnprintf(*buf + pos, bufsz - pos,
1560 "%010u:0x%08x:%04u\n",
1561 time, data, ev);
1562 } else {
1563 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
1564 time, data, ev);
1565 trace_iwlwifi_dev_ucode_event(priv, time,
1566 data, ev);
1567 }
b481de9c
ZY
1568 }
1569 }
e5854471
BC
1570
1571 /* Allow device to power down */
1572 iwl_release_nic_access(priv);
1573 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1574 return pos;
b481de9c
ZY
1575}
1576
c341ddb2
WYG
1577/**
1578 * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
1579 */
b03d7d0f 1580static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
c341ddb2 1581 u32 num_wraps, u32 next_entry,
b03d7d0f
WYG
1582 u32 size, u32 mode,
1583 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1584{
1585 /*
1586 * display the newest DEFAULT_LOG_ENTRIES entries
1587 * i.e the entries just before the next ont that uCode would fill.
1588 */
1589 if (num_wraps) {
1590 if (next_entry < size) {
b03d7d0f
WYG
1591 pos = iwl3945_print_event_log(priv,
1592 capacity - (size - next_entry),
1593 size - next_entry, mode,
1594 pos, buf, bufsz);
1595 pos = iwl3945_print_event_log(priv, 0,
1596 next_entry, mode,
1597 pos, buf, bufsz);
c341ddb2 1598 } else
b03d7d0f
WYG
1599 pos = iwl3945_print_event_log(priv, next_entry - size,
1600 size, mode,
1601 pos, buf, bufsz);
c341ddb2
WYG
1602 } else {
1603 if (next_entry < size)
b03d7d0f
WYG
1604 pos = iwl3945_print_event_log(priv, 0,
1605 next_entry, mode,
1606 pos, buf, bufsz);
c341ddb2 1607 else
b03d7d0f
WYG
1608 pos = iwl3945_print_event_log(priv, next_entry - size,
1609 size, mode,
1610 pos, buf, bufsz);
c341ddb2 1611 }
b03d7d0f 1612 return pos;
c341ddb2
WYG
1613}
1614
84c40692
BC
1615/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1616#define IWL3945_MAX_EVENT_LOG_SIZE (512)
1617
c341ddb2
WYG
1618#define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
1619
b03d7d0f
WYG
1620int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1621 char **buf, bool display)
b481de9c 1622{
b481de9c
ZY
1623 u32 base; /* SRAM byte address of event log header */
1624 u32 capacity; /* event log capacity in # entries */
1625 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1626 u32 num_wraps; /* # times uCode wrapped to top of log */
1627 u32 next_entry; /* index of next entry to be written by uCode */
1628 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1629 int pos = 0;
1630 size_t bufsz = 0;
b481de9c
ZY
1631
1632 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1633 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1634 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
937c397e 1635 return -EINVAL;
b481de9c
ZY
1636 }
1637
b481de9c 1638 /* event log header */
5d49f498
AK
1639 capacity = iwl_read_targ_mem(priv, base);
1640 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1641 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1642 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c 1643
84c40692
BC
1644 if (capacity > IWL3945_MAX_EVENT_LOG_SIZE) {
1645 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1646 capacity, IWL3945_MAX_EVENT_LOG_SIZE);
1647 capacity = IWL3945_MAX_EVENT_LOG_SIZE;
1648 }
1649
1650 if (next_entry > IWL3945_MAX_EVENT_LOG_SIZE) {
1651 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1652 next_entry, IWL3945_MAX_EVENT_LOG_SIZE);
1653 next_entry = IWL3945_MAX_EVENT_LOG_SIZE;
1654 }
1655
b481de9c
ZY
1656 size = num_wraps ? capacity : next_entry;
1657
1658 /* bail out if nothing in log */
1659 if (size == 0) {
15b1687c 1660 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1661 return pos;
b481de9c
ZY
1662 }
1663
c341ddb2 1664#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1665 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1666 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1667 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1668#else
1669 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1670 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1671#endif
1672
1673 IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
1674 size);
b481de9c 1675
c341ddb2 1676#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
1677 if (display) {
1678 if (full_log)
1679 bufsz = capacity * 48;
1680 else
1681 bufsz = size * 48;
1682 *buf = kmalloc(bufsz, GFP_KERNEL);
1683 if (!*buf)
937c397e 1684 return -ENOMEM;
b03d7d0f 1685 }
c341ddb2
WYG
1686 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1687 /* if uCode has wrapped back to top of log,
1688 * start at the oldest entry,
1689 * i.e the next one that uCode would fill.
1690 */
1691 if (num_wraps)
b03d7d0f
WYG
1692 pos = iwl3945_print_event_log(priv, next_entry,
1693 capacity - next_entry, mode,
1694 pos, buf, bufsz);
c341ddb2
WYG
1695
1696 /* (then/else) start at top of log */
b03d7d0f
WYG
1697 pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
1698 pos, buf, bufsz);
c341ddb2 1699 } else
b03d7d0f
WYG
1700 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1701 next_entry, size, mode,
1702 pos, buf, bufsz);
b7a79404 1703#else
b03d7d0f
WYG
1704 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1705 next_entry, size, mode,
1706 pos, buf, bufsz);
c341ddb2 1707#endif
b03d7d0f 1708 return pos;
b7a79404
RC
1709}
1710
4a8a4322 1711static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1712{
1713 u32 inta, handled = 0;
1714 u32 inta_fh;
1715 unsigned long flags;
d08853a3 1716#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1717 u32 inta_mask;
1718#endif
1719
1720 spin_lock_irqsave(&priv->lock, flags);
1721
1722 /* Ack/clear/reset pending uCode interrupts.
1723 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1724 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1725 inta = iwl_read32(priv, CSR_INT);
1726 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1727
1728 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1729 * Any new interrupts that happen after this, either while we're
1730 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1731 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1732 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1733
d08853a3 1734#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1735 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1736 /* just for debug */
5d49f498 1737 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1738 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1739 inta, inta_mask, inta_fh);
1740 }
1741#endif
1742
2f301227
ZY
1743 spin_unlock_irqrestore(&priv->lock, flags);
1744
b481de9c
ZY
1745 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1746 * atomic, make sure that inta covers all the interrupts that
1747 * we've discovered, even if FH interrupt came in just after
1748 * reading CSR_INT. */
6f83eaa1 1749 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1750 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1751 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1752 inta |= CSR_INT_BIT_FH_TX;
1753
1754 /* Now service all interrupt bits discovered above. */
1755 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1756 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1757
1758 /* Tell the device to stop sending interrupts */
ed3b932e 1759 iwl_disable_interrupts(priv);
b481de9c 1760
86ddbf62 1761 priv->isr_stats.hw++;
8ccde88a 1762 iwl_irq_handle_error(priv);
b481de9c
ZY
1763
1764 handled |= CSR_INT_BIT_HW_ERR;
1765
b481de9c
ZY
1766 return;
1767 }
1768
d08853a3 1769#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1770 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1771 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1772 if (inta & CSR_INT_BIT_SCD) {
e1623446 1773 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1774 "the frame/frames.\n");
86ddbf62
AK
1775 priv->isr_stats.sch++;
1776 }
b481de9c
ZY
1777
1778 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1779 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1780 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1781 priv->isr_stats.alive++;
1782 }
b481de9c
ZY
1783 }
1784#endif
1785 /* Safely ignore these bits for debug checks below */
25c03d8e 1786 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1787
b481de9c
ZY
1788 /* Error detected by uCode */
1789 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1790 IWL_ERR(priv, "Microcode SW error detected. "
1791 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1792 priv->isr_stats.sw++;
1793 priv->isr_stats.sw_err = inta;
8ccde88a 1794 iwl_irq_handle_error(priv);
b481de9c
ZY
1795 handled |= CSR_INT_BIT_SW_ERR;
1796 }
1797
1798 /* uCode wakes up after power-down sleep */
1799 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1800 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1801 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1802 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1803 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1804 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1805 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1806 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1807 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1808
86ddbf62 1809 priv->isr_stats.wakeup++;
b481de9c
ZY
1810 handled |= CSR_INT_BIT_WAKEUP;
1811 }
1812
1813 /* All uCode command responses, including Tx command responses,
1814 * Rx "responses" (frame-received notification), and other
1815 * notifications from uCode come through here*/
1816 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1817 iwl3945_rx_handle(priv);
86ddbf62 1818 priv->isr_stats.rx++;
b481de9c
ZY
1819 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1820 }
1821
1822 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1823 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1824 priv->isr_stats.tx++;
b481de9c 1825
5d49f498 1826 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1827 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1828 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1829 handled |= CSR_INT_BIT_FH_TX;
1830 }
1831
86ddbf62 1832 if (inta & ~handled) {
15b1687c 1833 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1834 priv->isr_stats.unhandled++;
1835 }
b481de9c 1836
40cefda9 1837 if (inta & ~priv->inta_mask) {
39aadf8c 1838 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1839 inta & ~priv->inta_mask);
39aadf8c 1840 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1841 }
1842
1843 /* Re-enable all interrupts */
0359facc
MA
1844 /* only Re-enable if disabled by irq */
1845 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1846 iwl_enable_interrupts(priv);
b481de9c 1847
d08853a3 1848#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1849 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1850 inta = iwl_read32(priv, CSR_INT);
1851 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1852 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1853 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1854 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1855 }
1856#endif
b481de9c
ZY
1857}
1858
4a8a4322 1859static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1860 enum ieee80211_band band,
f9340520 1861 u8 is_active, u8 n_probes,
bb8c093b 1862 struct iwl3945_scan_channel *scan_ch)
b481de9c 1863{
4e05c234 1864 struct ieee80211_channel *chan;
8318d78a 1865 const struct ieee80211_supported_band *sband;
d20b3c65 1866 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1867 u16 passive_dwell = 0;
1868 u16 active_dwell = 0;
1869 int added, i;
1870
cbba18c6 1871 sband = iwl_get_hw_mode(priv, band);
8318d78a 1872 if (!sband)
b481de9c
ZY
1873 return 0;
1874
77fecfb8
SO
1875 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1876 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1877
8f4807a1
AK
1878 if (passive_dwell <= active_dwell)
1879 passive_dwell = active_dwell + 1;
1880
4e05c234
JB
1881 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1882 chan = priv->scan_request->channels[i];
1883
1884 if (chan->band != band)
182e2e66
JB
1885 continue;
1886
4e05c234 1887 scan_ch->channel = chan->hw_value;
b481de9c 1888
e6148917 1889 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1890 if (!is_channel_valid(ch_info)) {
e1623446 1891 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1892 scan_ch->channel);
1893 continue;
1894 }
1895
011a0330
AK
1896 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1897 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1898 /* If passive , set up for auto-switch
1899 * and use long active_dwell time.
1900 */
b481de9c 1901 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1902 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1903 scan_ch->type = 0; /* passive */
011a0330
AK
1904 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1905 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1906 } else {
b481de9c 1907 scan_ch->type = 1; /* active */
011a0330 1908 }
b481de9c 1909
011a0330
AK
1910 /* Set direct probe bits. These may be used both for active
1911 * scan channels (probes gets sent right away),
1912 * or for passive channels (probes get se sent only after
1913 * hearing clear Rx packet).*/
1914 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1915 if (n_probes)
0d21044e 1916 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1917 } else {
1918 /* uCode v1 does not allow setting direct probe bits on
1919 * passive channel. */
1920 if ((scan_ch->type & 1) && n_probes)
0d21044e 1921 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1922 }
b481de9c 1923
9fbab516 1924 /* Set txpower levels to defaults */
b481de9c
ZY
1925 scan_ch->tpc.dsp_atten = 110;
1926 /* scan_pwr_info->tpc.dsp_atten; */
1927
1928 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1929 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1930 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1931 else {
1932 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1933 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1934 * power level:
8a1b0245 1935 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1936 */
1937 }
1938
e1623446 1939 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1940 scan_ch->channel,
1941 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1942 (scan_ch->type & 1) ?
1943 active_dwell : passive_dwell);
1944
1945 scan_ch++;
1946 added++;
1947 }
1948
e1623446 1949 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1950 return added;
1951}
1952
4a8a4322 1953static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1954 struct ieee80211_rate *rates)
1955{
1956 int i;
1957
1958 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1959 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1960 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1961 rates[i].hw_value_short = i;
1962 rates[i].flags = 0;
d9829a67 1963 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1964 /*
8318d78a 1965 * If CCK != 1M then set short preamble rate flag.
b481de9c 1966 */
bb8c093b 1967 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1968 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1969 }
b481de9c
ZY
1970 }
1971}
1972
b481de9c
ZY
1973/******************************************************************************
1974 *
1975 * uCode download functions
1976 *
1977 ******************************************************************************/
1978
4a8a4322 1979static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1980{
98c92211
TW
1981 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1982 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1983 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1984 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1985 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1986 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1987}
1988
1989/**
bb8c093b 1990 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1991 * looking at all data.
1992 */
4a8a4322 1993static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1994{
1995 u32 val;
1996 u32 save_len = len;
1997 int rc = 0;
1998 u32 errcnt;
1999
e1623446 2000 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2001
5d49f498 2002 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2003 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
2004
2005 errcnt = 0;
2006 for (; len > 0; len -= sizeof(u32), image++) {
2007 /* read data comes through single port, auto-incr addr */
2008 /* NOTE: Use the debugless read so we don't flood kernel log
2009 * if IWL_DL_IO is set */
5d49f498 2010 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 2011 if (val != le32_to_cpu(*image)) {
15b1687c 2012 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2013 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2014 save_len - len, val, le32_to_cpu(*image));
2015 rc = -EIO;
2016 errcnt++;
2017 if (errcnt >= 20)
2018 break;
2019 }
2020 }
2021
b481de9c
ZY
2022
2023 if (!errcnt)
e1623446
TW
2024 IWL_DEBUG_INFO(priv,
2025 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2026
2027 return rc;
2028}
2029
2030
2031/**
bb8c093b 2032 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2033 * using sample data 100 bytes apart. If these sample points are good,
2034 * it's a pretty good bet that everything between them is good, too.
2035 */
4a8a4322 2036static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2037{
2038 u32 val;
2039 int rc = 0;
2040 u32 errcnt = 0;
2041 u32 i;
2042
e1623446 2043 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2044
b481de9c
ZY
2045 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2046 /* read data comes through single port, auto-incr addr */
2047 /* NOTE: Use the debugless read so we don't flood kernel log
2048 * if IWL_DL_IO is set */
5d49f498 2049 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2050 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2051 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2052 if (val != le32_to_cpu(*image)) {
2053#if 0 /* Enable this if you want to see details */
15b1687c 2054 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2055 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2056 i, val, *image);
2057#endif
2058 rc = -EIO;
2059 errcnt++;
2060 if (errcnt >= 3)
2061 break;
2062 }
2063 }
2064
b481de9c
ZY
2065 return rc;
2066}
2067
2068
2069/**
bb8c093b 2070 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2071 * and verify its contents
2072 */
4a8a4322 2073static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2074{
2075 __le32 *image;
2076 u32 len;
2077 int rc = 0;
2078
2079 /* Try bootstrap */
2080 image = (__le32 *)priv->ucode_boot.v_addr;
2081 len = priv->ucode_boot.len;
bb8c093b 2082 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2083 if (rc == 0) {
e1623446 2084 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2085 return 0;
2086 }
2087
2088 /* Try initialize */
2089 image = (__le32 *)priv->ucode_init.v_addr;
2090 len = priv->ucode_init.len;
bb8c093b 2091 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2092 if (rc == 0) {
e1623446 2093 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2094 return 0;
2095 }
2096
2097 /* Try runtime/protocol */
2098 image = (__le32 *)priv->ucode_code.v_addr;
2099 len = priv->ucode_code.len;
bb8c093b 2100 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2101 if (rc == 0) {
e1623446 2102 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2103 return 0;
2104 }
2105
15b1687c 2106 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2107
9fbab516
BC
2108 /* Since nothing seems to match, show first several data entries in
2109 * instruction SRAM, so maybe visual inspection will give a clue.
2110 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2111 image = (__le32 *)priv->ucode_boot.v_addr;
2112 len = priv->ucode_boot.len;
bb8c093b 2113 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2114
2115 return rc;
2116}
2117
4a8a4322 2118static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2119{
2120 /* Remove all resets to allow NIC to operate */
5d49f498 2121 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2122}
2123
2124/**
bb8c093b 2125 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2126 *
2127 * Copy into buffers for card to fetch via bus-mastering
2128 */
4a8a4322 2129static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2130{
cc0f555d 2131 const struct iwl_ucode_header *ucode;
a0987a8d 2132 int ret = -EINVAL, index;
b481de9c
ZY
2133 const struct firmware *ucode_raw;
2134 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2135 const char *name_pre = priv->cfg->fw_name_pre;
2136 const unsigned int api_max = priv->cfg->ucode_api_max;
2137 const unsigned int api_min = priv->cfg->ucode_api_min;
2138 char buf[25];
b481de9c
ZY
2139 u8 *src;
2140 size_t len;
a0987a8d 2141 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2142
2143 /* Ask kernel firmware_class module to get the boot firmware off disk.
2144 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2145 for (index = api_max; index >= api_min; index--) {
2146 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2147 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2148 if (ret < 0) {
15b1687c 2149 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2150 buf, ret);
2151 if (ret == -ENOENT)
2152 continue;
2153 else
2154 goto error;
2155 } else {
2156 if (index < api_max)
15b1687c
WT
2157 IWL_ERR(priv, "Loaded firmware %s, "
2158 "which is deprecated. "
2159 " Please use API v%u instead.\n",
a0987a8d 2160 buf, api_max);
e1623446
TW
2161 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2162 "(%zd bytes) from disk\n",
a0987a8d
RC
2163 buf, ucode_raw->size);
2164 break;
2165 }
b481de9c
ZY
2166 }
2167
a0987a8d
RC
2168 if (ret < 0)
2169 goto error;
b481de9c
ZY
2170
2171 /* Make sure that we got at least our header! */
cc0f555d 2172 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2173 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2174 ret = -EINVAL;
b481de9c
ZY
2175 goto err_release;
2176 }
2177
2178 /* Data from ucode file: header followed by uCode images */
cc0f555d 2179 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2180
c02b3acd 2181 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2182 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2183 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2184 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2185 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2186 init_data_size =
2187 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2188 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2189 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2190
a0987a8d
RC
2191 /* api_ver should match the api version forming part of the
2192 * firmware filename ... but we don't check for that and only rely
877d0310 2193 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2194
2195 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2196 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2197 "Driver supports v%u, firmware is v%u.\n",
2198 api_max, api_ver);
2199 priv->ucode_ver = 0;
2200 ret = -EINVAL;
2201 goto err_release;
2202 }
2203 if (api_ver != api_max)
15b1687c 2204 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2205 "got %u. New firmware can be obtained "
2206 "from http://www.intellinuxwireless.org.\n",
2207 api_max, api_ver);
2208
978785a3
TW
2209 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2210 IWL_UCODE_MAJOR(priv->ucode_ver),
2211 IWL_UCODE_MINOR(priv->ucode_ver),
2212 IWL_UCODE_API(priv->ucode_ver),
2213 IWL_UCODE_SERIAL(priv->ucode_ver));
2214
5ebeb5a6
RC
2215 snprintf(priv->hw->wiphy->fw_version,
2216 sizeof(priv->hw->wiphy->fw_version),
2217 "%u.%u.%u.%u",
2218 IWL_UCODE_MAJOR(priv->ucode_ver),
2219 IWL_UCODE_MINOR(priv->ucode_ver),
2220 IWL_UCODE_API(priv->ucode_ver),
2221 IWL_UCODE_SERIAL(priv->ucode_ver));
2222
e1623446 2223 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2224 priv->ucode_ver);
e1623446
TW
2225 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2226 inst_size);
2227 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2228 data_size);
2229 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2230 init_size);
2231 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2232 init_data_size);
2233 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2234 boot_size);
b481de9c 2235
a0987a8d 2236
b481de9c 2237 /* Verify size of file vs. image size info in file's header */
cc0f555d 2238 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2239 inst_size + data_size + init_size +
2240 init_data_size + boot_size) {
2241
cc0f555d
JS
2242 IWL_DEBUG_INFO(priv,
2243 "uCode file size %zd does not match expected size\n",
2244 ucode_raw->size);
90e759d1 2245 ret = -EINVAL;
b481de9c
ZY
2246 goto err_release;
2247 }
2248
2249 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2250 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2251 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2252 inst_size);
2253 ret = -EINVAL;
b481de9c
ZY
2254 goto err_release;
2255 }
2256
250bdd21 2257 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2258 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2259 data_size);
2260 ret = -EINVAL;
b481de9c
ZY
2261 goto err_release;
2262 }
250bdd21 2263 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2264 IWL_DEBUG_INFO(priv,
2265 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2266 init_size);
2267 ret = -EINVAL;
b481de9c
ZY
2268 goto err_release;
2269 }
250bdd21 2270 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2271 IWL_DEBUG_INFO(priv,
2272 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2273 init_data_size);
2274 ret = -EINVAL;
b481de9c
ZY
2275 goto err_release;
2276 }
250bdd21 2277 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2278 IWL_DEBUG_INFO(priv,
2279 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2280 boot_size);
2281 ret = -EINVAL;
b481de9c
ZY
2282 goto err_release;
2283 }
2284
2285 /* Allocate ucode buffers for card's bus-master loading ... */
2286
2287 /* Runtime instructions and 2 copies of data:
2288 * 1) unmodified from disk
2289 * 2) backup cache for save/restore during power-downs */
2290 priv->ucode_code.len = inst_size;
98c92211 2291 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2292
2293 priv->ucode_data.len = data_size;
98c92211 2294 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2295
2296 priv->ucode_data_backup.len = data_size;
98c92211 2297 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2298
90e759d1
TW
2299 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2300 !priv->ucode_data_backup.v_addr)
2301 goto err_pci_alloc;
b481de9c
ZY
2302
2303 /* Initialization instructions and data */
90e759d1
TW
2304 if (init_size && init_data_size) {
2305 priv->ucode_init.len = init_size;
98c92211 2306 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2307
2308 priv->ucode_init_data.len = init_data_size;
98c92211 2309 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2310
2311 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2312 goto err_pci_alloc;
2313 }
b481de9c
ZY
2314
2315 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2316 if (boot_size) {
2317 priv->ucode_boot.len = boot_size;
98c92211 2318 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2319
90e759d1
TW
2320 if (!priv->ucode_boot.v_addr)
2321 goto err_pci_alloc;
2322 }
b481de9c
ZY
2323
2324 /* Copy images into buffers for card's bus-master reads ... */
2325
2326 /* Runtime instructions (first block of data in file) */
cc0f555d 2327 len = inst_size;
e1623446
TW
2328 IWL_DEBUG_INFO(priv,
2329 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2330 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2331 src += len;
2332
e1623446 2333 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2334 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2335
2336 /* Runtime data (2nd block)
bb8c093b 2337 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2338 len = data_size;
e1623446
TW
2339 IWL_DEBUG_INFO(priv,
2340 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2341 memcpy(priv->ucode_data.v_addr, src, len);
2342 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2343 src += len;
b481de9c
ZY
2344
2345 /* Initialization instructions (3rd block) */
2346 if (init_size) {
cc0f555d 2347 len = init_size;
e1623446
TW
2348 IWL_DEBUG_INFO(priv,
2349 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2350 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2351 src += len;
b481de9c
ZY
2352 }
2353
2354 /* Initialization data (4th block) */
2355 if (init_data_size) {
cc0f555d 2356 len = init_data_size;
e1623446
TW
2357 IWL_DEBUG_INFO(priv,
2358 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2359 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2360 src += len;
b481de9c
ZY
2361 }
2362
2363 /* Bootstrap instructions (5th block) */
cc0f555d 2364 len = boot_size;
e1623446
TW
2365 IWL_DEBUG_INFO(priv,
2366 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2367 memcpy(priv->ucode_boot.v_addr, src, len);
2368
2369 /* We have our copies now, allow OS release its copies */
2370 release_firmware(ucode_raw);
2371 return 0;
2372
2373 err_pci_alloc:
15b1687c 2374 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2375 ret = -ENOMEM;
bb8c093b 2376 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2377
2378 err_release:
2379 release_firmware(ucode_raw);
2380
2381 error:
90e759d1 2382 return ret;
b481de9c
ZY
2383}
2384
2385
2386/**
bb8c093b 2387 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2388 *
2389 * Tell initialization uCode where to find runtime uCode.
2390 *
2391 * BSM registers initially contain pointers to initialization uCode.
2392 * We need to replace them to load runtime uCode inst and data,
2393 * and to save runtime data when powering down.
2394 */
4a8a4322 2395static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2396{
2397 dma_addr_t pinst;
2398 dma_addr_t pdata;
b481de9c
ZY
2399
2400 /* bits 31:0 for 3945 */
2401 pinst = priv->ucode_code.p_addr;
2402 pdata = priv->ucode_data_backup.p_addr;
2403
b481de9c 2404 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2405 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2406 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2407 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2408 priv->ucode_data.len);
2409
a96a27f9 2410 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2411 * that all new ptr/size info is in place */
5d49f498 2412 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2413 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2414
e1623446 2415 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2416
a8b50a0a 2417 return 0;
b481de9c
ZY
2418}
2419
2420/**
bb8c093b 2421 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2422 *
2423 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2424 *
b481de9c 2425 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2426 */
4a8a4322 2427static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2428{
2429 /* Check alive response for "valid" sign from uCode */
2430 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2431 /* We had an error bringing up the hardware, so take it
2432 * all the way back down so we can try again */
e1623446 2433 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2434 goto restart;
2435 }
2436
2437 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2438 * This is a paranoid check, because we would not have gotten the
2439 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2440 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2441 /* Runtime instruction load was bad;
2442 * take it all the way back down so we can try again */
e1623446 2443 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2444 goto restart;
2445 }
2446
2447 /* Send pointers to protocol/runtime uCode image ... init code will
2448 * load and launch runtime uCode, which will send us another "Alive"
2449 * notification. */
e1623446 2450 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2451 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2452 /* Runtime instruction load won't happen;
2453 * take it all the way back down so we can try again */
e1623446 2454 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2455 goto restart;
2456 }
2457 return;
2458
2459 restart:
2460 queue_work(priv->workqueue, &priv->restart);
2461}
2462
b481de9c 2463/**
bb8c093b 2464 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2465 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2466 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2467 */
4a8a4322 2468static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2469{
b481de9c
ZY
2470 int thermal_spin = 0;
2471 u32 rfkill;
2472
e1623446 2473 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2474
2475 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2476 /* We had an error bringing up the hardware, so take it
2477 * all the way back down so we can try again */
e1623446 2478 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2479 goto restart;
2480 }
2481
2482 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2483 * This is a paranoid check, because we would not have gotten the
2484 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2485 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2486 /* Runtime instruction load was bad;
2487 * take it all the way back down so we can try again */
e1623446 2488 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2489 goto restart;
2490 }
2491
c587de0b 2492 iwl_clear_stations_table(priv);
b481de9c 2493
5d49f498 2494 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2495 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2496
2497 if (rfkill & 0x1) {
2498 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2499 /* if RFKILL is not on, then wait for thermal
b481de9c 2500 * sensor in adapter to kick in */
bb8c093b 2501 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2502 thermal_spin++;
2503 udelay(10);
2504 }
2505
2506 if (thermal_spin)
e1623446 2507 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2508 thermal_spin * 10);
2509 } else
2510 set_bit(STATUS_RF_KILL_HW, &priv->status);
2511
9fbab516 2512 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2513 set_bit(STATUS_ALIVE, &priv->status);
2514
775a6e27 2515 if (iwl_is_rfkill(priv))
b481de9c
ZY
2516 return;
2517
36d6825b 2518 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2519
2520 priv->active_rate = priv->rates_mask;
2521 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2522
4d6ccbf5 2523 iwl_power_update_mode(priv, true);
b481de9c 2524
8ccde88a 2525 if (iwl_is_associated(priv)) {
bb8c093b 2526 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2527 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2528
8a9b9926 2529 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2530 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2531 } else {
2532 /* Initialize our rx_config data */
8ccde88a 2533 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2534 }
2535
9fbab516 2536 /* Configure Bluetooth device coexistence support */
17f841cd 2537 iwl_send_bt_config(priv);
b481de9c
ZY
2538
2539 /* Configure the adapter for unassociated operation */
e0158e61 2540 iwlcore_commit_rxon(priv);
b481de9c 2541
b481de9c
ZY
2542 iwl3945_reg_txpower_periodic(priv);
2543
e932a609 2544 iwl_leds_init(priv);
fe00b5a5 2545
e1623446 2546 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2547 set_bit(STATUS_READY, &priv->status);
5a66926a 2548 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2549
9bdf5eca
MA
2550 /* reassociate for ADHOC mode */
2551 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2552 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2553 priv->vif);
2554 if (beacon)
9944b938 2555 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2556 }
2557
f45c2714 2558 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2559 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2560
b481de9c
ZY
2561 return;
2562
2563 restart:
2564 queue_work(priv->workqueue, &priv->restart);
2565}
2566
4a8a4322 2567static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2568
4a8a4322 2569static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2570{
2571 unsigned long flags;
2572 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2573 struct ieee80211_conf *conf = NULL;
2574
e1623446 2575 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2576
2577 conf = ieee80211_get_hw_conf(priv->hw);
2578
2579 if (!exit_pending)
2580 set_bit(STATUS_EXIT_PENDING, &priv->status);
2581
c587de0b 2582 iwl_clear_stations_table(priv);
b481de9c
ZY
2583
2584 /* Unblock any waiting calls */
2585 wake_up_interruptible_all(&priv->wait_command_queue);
2586
b481de9c
ZY
2587 /* Wipe out the EXIT_PENDING status bit if we are not actually
2588 * exiting the module */
2589 if (!exit_pending)
2590 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2591
2592 /* stop and reset the on-board processor */
5d49f498 2593 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2594
2595 /* tell the device to stop sending interrupts */
0359facc 2596 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2597 iwl_disable_interrupts(priv);
0359facc
MA
2598 spin_unlock_irqrestore(&priv->lock, flags);
2599 iwl_synchronize_irq(priv);
b481de9c
ZY
2600
2601 if (priv->mac80211_registered)
2602 ieee80211_stop_queues(priv->hw);
2603
bb8c093b 2604 /* If we have not previously called iwl3945_init() then
6da3a13e 2605 * clear all bits but the RF Kill bits and return */
775a6e27 2606 if (!iwl_is_init(priv)) {
b481de9c
ZY
2607 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2608 STATUS_RF_KILL_HW |
9788864e
RC
2609 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2610 STATUS_GEO_CONFIGURED |
ebef2008
AK
2611 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2612 STATUS_EXIT_PENDING;
b481de9c
ZY
2613 goto exit;
2614 }
2615
6da3a13e 2616 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2617 * bit and continue taking the NIC down. */
b481de9c
ZY
2618 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2619 STATUS_RF_KILL_HW |
9788864e
RC
2620 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2621 STATUS_GEO_CONFIGURED |
b481de9c 2622 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2623 STATUS_FW_ERROR |
2624 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2625 STATUS_EXIT_PENDING;
b481de9c 2626
bb8c093b
CH
2627 iwl3945_hw_txq_ctx_stop(priv);
2628 iwl3945_hw_rxq_stop(priv);
b481de9c 2629
309e731a
BC
2630 /* Power-down device's busmaster DMA clocks */
2631 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2632 udelay(5);
2633
4d2ccdb9
BC
2634 /* Stop the device, and put it in low power state */
2635 priv->cfg->ops->lib->apm_ops.stop(priv);
e9414b6b 2636
b481de9c 2637 exit:
3d24a9f7 2638 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2639
2640 if (priv->ibss_beacon)
2641 dev_kfree_skb(priv->ibss_beacon);
2642 priv->ibss_beacon = NULL;
2643
2644 /* clear out any free frames */
bb8c093b 2645 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2646}
2647
4a8a4322 2648static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2649{
2650 mutex_lock(&priv->mutex);
bb8c093b 2651 __iwl3945_down(priv);
b481de9c 2652 mutex_unlock(&priv->mutex);
b24d22b1 2653
bb8c093b 2654 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2655}
2656
2657#define MAX_HW_RESTARTS 5
2658
4a8a4322 2659static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2660{
2661 int rc, i;
2662
2663 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2664 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2665 return -EIO;
2666 }
2667
e903fbd4 2668 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2669 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2670 return -EIO;
2671 }
2672
e655b9f0 2673 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2674 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2675 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2676 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2677 else {
2678 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2679 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2680 return -ENODEV;
b481de9c 2681 }
80fcc9e2 2682
5d49f498 2683 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2684
bb8c093b 2685 rc = iwl3945_hw_nic_init(priv);
b481de9c 2686 if (rc) {
15b1687c 2687 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2688 return rc;
2689 }
2690
2691 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2692 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2693 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2694 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2695
2696 /* clear (again), then enable host interrupts */
5d49f498 2697 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2698 iwl_enable_interrupts(priv);
b481de9c
ZY
2699
2700 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2701 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2702 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2703
2704 /* Copy original ucode data image from disk into backup cache.
2705 * This will be used to initialize the on-board processor's
2706 * data SRAM for a clean start when the runtime program first loads. */
2707 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2708 priv->ucode_data.len);
b481de9c 2709
e655b9f0
ZY
2710 /* We return success when we resume from suspend and rf_kill is on. */
2711 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2712 return 0;
2713
b481de9c
ZY
2714 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2715
c587de0b 2716 iwl_clear_stations_table(priv);
b481de9c
ZY
2717
2718 /* load bootstrap state machine,
2719 * load bootstrap program into processor's memory,
2720 * prepare to load the "initialize" uCode */
0164b9b4 2721 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2722
2723 if (rc) {
15b1687c
WT
2724 IWL_ERR(priv,
2725 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2726 continue;
2727 }
2728
2729 /* start card; "initialize" will load runtime ucode */
bb8c093b 2730 iwl3945_nic_start(priv);
b481de9c 2731
e1623446 2732 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2733
2734 return 0;
2735 }
2736
2737 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2738 __iwl3945_down(priv);
ebef2008 2739 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2740
2741 /* tried to restart and config the device for as long as our
2742 * patience could withstand */
15b1687c 2743 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2744 return -EIO;
2745}
2746
2747
2748/*****************************************************************************
2749 *
2750 * Workqueue callbacks
2751 *
2752 *****************************************************************************/
2753
bb8c093b 2754static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2755{
4a8a4322
AK
2756 struct iwl_priv *priv =
2757 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2758
2759 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2760 return;
2761
2762 mutex_lock(&priv->mutex);
bb8c093b 2763 iwl3945_init_alive_start(priv);
b481de9c
ZY
2764 mutex_unlock(&priv->mutex);
2765}
2766
bb8c093b 2767static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2768{
4a8a4322
AK
2769 struct iwl_priv *priv =
2770 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2771
2772 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2773 return;
2774
2775 mutex_lock(&priv->mutex);
bb8c093b 2776 iwl3945_alive_start(priv);
b481de9c
ZY
2777 mutex_unlock(&priv->mutex);
2778}
2779
743cdf1b
BC
2780/*
2781 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2782 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2783 * *is* readable even when device has been SW_RESET into low power mode
2784 * (e.g. during RF KILL).
2785 */
2663516d
HS
2786static void iwl3945_rfkill_poll(struct work_struct *data)
2787{
2788 struct iwl_priv *priv =
2789 container_of(data, struct iwl_priv, rfkill_poll.work);
743cdf1b
BC
2790 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
2791 bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
2792 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2663516d 2793
743cdf1b
BC
2794 if (new_rfkill != old_rfkill) {
2795 if (new_rfkill)
2796 set_bit(STATUS_RF_KILL_HW, &priv->status);
2797 else
2798 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2663516d 2799
743cdf1b
BC
2800 wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
2801
2802 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
2803 new_rfkill ? "disable radio" : "enable radio");
2804 }
2663516d 2805
743cdf1b
BC
2806 /* Keep this running, even if radio now enabled. This will be
2807 * cancelled in mac_start() if system decides to start again */
2663516d
HS
2808 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2809 round_jiffies_relative(2 * HZ));
2810
2811}
2812
b481de9c 2813#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2814static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2815{
4a8a4322
AK
2816 struct iwl_priv *priv =
2817 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2818 struct iwl_host_cmd cmd = {
b481de9c 2819 .id = REPLY_SCAN_CMD,
bb8c093b 2820 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2821 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2822 };
2823 int rc = 0;
bb8c093b 2824 struct iwl3945_scan_cmd *scan;
b481de9c 2825 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2826 u8 n_probes = 0;
8318d78a 2827 enum ieee80211_band band;
1ecf9fc1 2828 bool is_active = false;
b481de9c
ZY
2829
2830 conf = ieee80211_get_hw_conf(priv->hw);
2831
2832 mutex_lock(&priv->mutex);
2833
fbc9f97b
RC
2834 cancel_delayed_work(&priv->scan_check);
2835
775a6e27 2836 if (!iwl_is_ready(priv)) {
39aadf8c 2837 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2838 goto done;
2839 }
2840
a96a27f9 2841 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2842 * was given the chance to run... */
2843 if (!test_bit(STATUS_SCANNING, &priv->status))
2844 goto done;
2845
2846 /* This should never be called or scheduled if there is currently
2847 * a scan active in the hardware. */
2848 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2849 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2850 "Ignoring second request.\n");
b481de9c
ZY
2851 rc = -EIO;
2852 goto done;
2853 }
2854
2855 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2856 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2857 goto done;
2858 }
2859
2860 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2861 IWL_DEBUG_HC(priv,
2862 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2863 goto done;
2864 }
2865
775a6e27 2866 if (iwl_is_rfkill(priv)) {
e1623446 2867 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2868 goto done;
2869 }
2870
2871 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2872 IWL_DEBUG_HC(priv,
2873 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2874 goto done;
2875 }
2876
2877 if (!priv->scan_bands) {
e1623446 2878 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2879 goto done;
2880 }
2881
805cee5b
WT
2882 if (!priv->scan) {
2883 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2884 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2885 if (!priv->scan) {
b481de9c
ZY
2886 rc = -ENOMEM;
2887 goto done;
2888 }
2889 }
805cee5b 2890 scan = priv->scan;
bb8c093b 2891 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2892
2893 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2894 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2895
8ccde88a 2896 if (iwl_is_associated(priv)) {
b481de9c
ZY
2897 u16 interval = 0;
2898 u32 extra;
2899 u32 suspend_time = 100;
2900 u32 scan_suspend_time = 100;
2901 unsigned long flags;
2902
e1623446 2903 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2904
2905 spin_lock_irqsave(&priv->lock, flags);
2906 interval = priv->beacon_int;
2907 spin_unlock_irqrestore(&priv->lock, flags);
2908
2909 scan->suspend_time = 0;
15e869d8 2910 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2911 if (!interval)
2912 interval = suspend_time;
2913 /*
2914 * suspend time format:
2915 * 0-19: beacon interval in usec (time before exec.)
2916 * 20-23: 0
2917 * 24-31: number of beacons (suspend between channels)
2918 */
2919
2920 extra = (suspend_time / interval) << 24;
2921 scan_suspend_time = 0xFF0FFFFF &
2922 (extra | ((suspend_time % interval) * 1024));
2923
2924 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2925 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2926 scan_suspend_time, interval);
2927 }
2928
1ecf9fc1
JB
2929 if (priv->scan_request->n_ssids) {
2930 int i, p = 0;
2931 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2932 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2933 /* always does wildcard anyway */
2934 if (!priv->scan_request->ssids[i].ssid_len)
2935 continue;
2936 scan->direct_scan[p].id = WLAN_EID_SSID;
2937 scan->direct_scan[p].len =
2938 priv->scan_request->ssids[i].ssid_len;
2939 memcpy(scan->direct_scan[p].ssid,
2940 priv->scan_request->ssids[i].ssid,
2941 priv->scan_request->ssids[i].ssid_len);
2942 n_probes++;
2943 p++;
2944 }
2945 is_active = true;
f9340520 2946 } else
1ecf9fc1 2947 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2948
2949 /* We don't build a direct scan probe request; the uCode will do
2950 * that based on the direct_mask added to each channel entry */
b481de9c 2951 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2952 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2953 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2954
2955 /* flags + rate selection */
2956
66b5004d 2957 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2958 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2959 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2960 scan->good_CRC_th = 0;
8318d78a 2961 band = IEEE80211_BAND_2GHZ;
66b5004d 2962 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2963 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2964 /*
2965 * If active scaning is requested but a certain channel
2966 * is marked passive, we can do active scanning if we
2967 * detect transmissions.
2968 */
2969 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2970 band = IEEE80211_BAND_5GHZ;
66b5004d 2971 } else {
39aadf8c 2972 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2973 goto done;
2974 }
2975
77fecfb8 2976 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2977 iwl_fill_probe_req(priv,
2978 (struct ieee80211_mgmt *)scan->data,
2979 priv->scan_request->ie,
2980 priv->scan_request->ie_len,
2981 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2982
b481de9c
ZY
2983 /* select Rx antennas */
2984 scan->flags |= iwl3945_get_antenna_flags(priv);
2985
279b05d4 2986 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2987 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2988
f9340520 2989 scan->channel_count =
1ecf9fc1 2990 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2991 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2992
14b54336 2993 if (scan->channel_count == 0) {
e1623446 2994 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2995 goto done;
2996 }
2997
b481de9c 2998 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2999 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
3000 cmd.data = scan;
3001 scan->len = cpu_to_le16(cmd.len);
3002
3003 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 3004 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3005 if (rc)
3006 goto done;
3007
3008 queue_delayed_work(priv->workqueue, &priv->scan_check,
3009 IWL_SCAN_CHECK_WATCHDOG);
3010
3011 mutex_unlock(&priv->mutex);
3012 return;
3013
3014 done:
2420ebc1
MA
3015 /* can not perform scan make sure we clear scanning
3016 * bits from status so next scan request can be performed.
3017 * if we dont clear scanning status bit here all next scan
3018 * will fail
3019 */
3020 clear_bit(STATUS_SCAN_HW, &priv->status);
3021 clear_bit(STATUS_SCANNING, &priv->status);
3022
01ebd063 3023 /* inform mac80211 scan aborted */
b481de9c
ZY
3024 queue_work(priv->workqueue, &priv->scan_completed);
3025 mutex_unlock(&priv->mutex);
3026}
3027
bb8c093b 3028static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3029{
4a8a4322 3030 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3031
3032 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3033 return;
3034
19cc1087
JB
3035 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3036 mutex_lock(&priv->mutex);
3037 priv->vif = NULL;
3038 priv->is_open = 0;
3039 mutex_unlock(&priv->mutex);
3040 iwl3945_down(priv);
3041 ieee80211_restart_hw(priv->hw);
3042 } else {
3043 iwl3945_down(priv);
80676518
JB
3044
3045 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3046 return;
3047
3048 mutex_lock(&priv->mutex);
3049 __iwl3945_up(priv);
3050 mutex_unlock(&priv->mutex);
19cc1087 3051 }
b481de9c
ZY
3052}
3053
bb8c093b 3054static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3055{
4a8a4322
AK
3056 struct iwl_priv *priv =
3057 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3058
3059 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3060 return;
3061
3062 mutex_lock(&priv->mutex);
bb8c093b 3063 iwl3945_rx_replenish(priv);
b481de9c
ZY
3064 mutex_unlock(&priv->mutex);
3065}
3066
7878a5a4
MA
3067#define IWL_DELAY_NEXT_SCAN (HZ*2)
3068
5bbe233b 3069void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3070{
b481de9c
ZY
3071 int rc = 0;
3072 struct ieee80211_conf *conf = NULL;
3073
05c914fe 3074 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3075 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3076 return;
3077 }
3078
3079
e1623446 3080 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3081 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3082
3083 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3084 return;
3085
322a9811 3086 if (!priv->vif || !priv->is_open)
6ef89d0a 3087 return;
322a9811 3088
af0053d6 3089 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3090
b481de9c
ZY
3091 conf = ieee80211_get_hw_conf(priv->hw);
3092
8ccde88a 3093 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3094 iwlcore_commit_rxon(priv);
b481de9c 3095
28afaf91 3096 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3097 iwl_setup_rxon_timing(priv);
518099a8 3098 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3099 sizeof(priv->rxon_timing), &priv->rxon_timing);
3100 if (rc)
39aadf8c 3101 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3102 "Attempting to continue.\n");
3103
8ccde88a 3104 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3105
8ccde88a 3106 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3107
e1623446 3108 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3109 priv->assoc_id, priv->beacon_int);
3110
3111 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3112 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3113 else
8ccde88a 3114 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3115
8ccde88a 3116 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3117 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3118 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3119 else
8ccde88a 3120 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3121
05c914fe 3122 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3123 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3124
3125 }
3126
e0158e61 3127 iwlcore_commit_rxon(priv);
b481de9c
ZY
3128
3129 switch (priv->iw_mode) {
05c914fe 3130 case NL80211_IFTYPE_STATION:
bb8c093b 3131 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3132 break;
3133
05c914fe 3134 case NL80211_IFTYPE_ADHOC:
b481de9c 3135
ce546fd2 3136 priv->assoc_id = 1;
c587de0b 3137 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3138 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3139 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3140 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3141 CMD_ASYNC);
bb8c093b
CH
3142 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3143 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3144
3145 break;
3146
3147 default:
15b1687c 3148 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3149 __func__, priv->iw_mode);
b481de9c
ZY
3150 break;
3151 }
3152
14d2aac5 3153 iwl_activate_qos(priv, 0);
292ae174 3154
7878a5a4
MA
3155 /* we have just associated, don't start scan too early */
3156 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3157}
3158
b481de9c
ZY
3159/*****************************************************************************
3160 *
3161 * mac80211 entry point functions
3162 *
3163 *****************************************************************************/
3164
5a66926a
ZY
3165#define UCODE_READY_TIMEOUT (2 * HZ)
3166
bb8c093b 3167static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3168{
4a8a4322 3169 struct iwl_priv *priv = hw->priv;
5a66926a 3170 int ret;
b481de9c 3171
e1623446 3172 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3173
3174 /* we should be verifying the device is ready to be opened */
3175 mutex_lock(&priv->mutex);
3176
5a66926a
ZY
3177 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3178 * ucode filename and max sizes are card-specific. */
3179
3180 if (!priv->ucode_code.len) {
3181 ret = iwl3945_read_ucode(priv);
3182 if (ret) {
15b1687c 3183 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3184 mutex_unlock(&priv->mutex);
3185 goto out_release_irq;
3186 }
3187 }
b481de9c 3188
e655b9f0 3189 ret = __iwl3945_up(priv);
b481de9c
ZY
3190
3191 mutex_unlock(&priv->mutex);
5a66926a 3192
e655b9f0
ZY
3193 if (ret)
3194 goto out_release_irq;
3195
e1623446 3196 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3197
5a66926a
ZY
3198 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3199 * mac80211 will not be run successfully. */
3200 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3201 test_bit(STATUS_READY, &priv->status),
3202 UCODE_READY_TIMEOUT);
3203 if (!ret) {
3204 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3205 IWL_ERR(priv,
3206 "Wait for START_ALIVE timeout after %dms.\n",
3207 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3208 ret = -ETIMEDOUT;
3209 goto out_release_irq;
3210 }
3211 }
3212
2663516d
HS
3213 /* ucode is running and will send rfkill notifications,
3214 * no need to poll the killswitch state anymore */
3215 cancel_delayed_work(&priv->rfkill_poll);
3216
e932a609
JB
3217 iwl_led_start(priv);
3218
e655b9f0 3219 priv->is_open = 1;
e1623446 3220 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3221 return 0;
5a66926a
ZY
3222
3223out_release_irq:
e655b9f0 3224 priv->is_open = 0;
e1623446 3225 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3226 return ret;
b481de9c
ZY
3227}
3228
bb8c093b 3229static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3230{
4a8a4322 3231 struct iwl_priv *priv = hw->priv;
b481de9c 3232
e1623446 3233 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3234
e655b9f0 3235 if (!priv->is_open) {
e1623446 3236 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3237 return;
3238 }
3239
b481de9c 3240 priv->is_open = 0;
5a66926a 3241
775a6e27 3242 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3243 /* stop mac, cancel any scan request and clear
3244 * RXON_FILTER_ASSOC_MSK BIT
3245 */
5a66926a 3246 mutex_lock(&priv->mutex);
af0053d6 3247 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3248 mutex_unlock(&priv->mutex);
fde3571f
MA
3249 }
3250
5a66926a
ZY
3251 iwl3945_down(priv);
3252
3253 flush_workqueue(priv->workqueue);
2663516d
HS
3254
3255 /* start polling the killswitch state again */
3256 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3257 round_jiffies_relative(2 * HZ));
6ef89d0a 3258
e1623446 3259 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3260}
3261
e039fa4a 3262static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3263{
4a8a4322 3264 struct iwl_priv *priv = hw->priv;
b481de9c 3265
e1623446 3266 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3267
e1623446 3268 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3269 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3270
e039fa4a 3271 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3272 dev_kfree_skb_any(skb);
3273
e1623446 3274 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3275 return NETDEV_TX_OK;
b481de9c
ZY
3276}
3277
60690a6a 3278void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3279{
3280 int rc = 0;
3281
d986bcd1 3282 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3283 return;
3284
3285 /* The following should be done only at AP bring up */
8ccde88a 3286 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3287
3288 /* RXON - unassoc (to set timing command) */
8ccde88a 3289 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3290 iwlcore_commit_rxon(priv);
b481de9c
ZY
3291
3292 /* RXON Timing */
28afaf91 3293 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3294 iwl_setup_rxon_timing(priv);
518099a8
SO
3295 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3296 sizeof(priv->rxon_timing),
3297 &priv->rxon_timing);
b481de9c 3298 if (rc)
39aadf8c 3299 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3300 "Attempting to continue.\n");
3301
3302 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3303 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3304 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3305 priv->staging_rxon.flags |=
b481de9c
ZY
3306 RXON_FLG_SHORT_PREAMBLE_MSK;
3307 else
8ccde88a 3308 priv->staging_rxon.flags &=
b481de9c
ZY
3309 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3310
8ccde88a 3311 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3312 if (priv->assoc_capability &
3313 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3314 priv->staging_rxon.flags |=
b481de9c
ZY
3315 RXON_FLG_SHORT_SLOT_MSK;
3316 else
8ccde88a 3317 priv->staging_rxon.flags &=
b481de9c
ZY
3318 ~RXON_FLG_SHORT_SLOT_MSK;
3319
05c914fe 3320 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3321 priv->staging_rxon.flags &=
b481de9c
ZY
3322 ~RXON_FLG_SHORT_SLOT_MSK;
3323 }
3324 /* restore RXON assoc */
8ccde88a 3325 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3326 iwlcore_commit_rxon(priv);
c587de0b 3327 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3328 }
bb8c093b 3329 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3330
3331 /* FIXME - we need to add code here to detect a totally new
3332 * configuration, reset the AP, unassoc, rxon timing, assoc,
3333 * clear sta table, add BCAST sta... */
3334}
3335
bb8c093b 3336static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3337 struct ieee80211_vif *vif,
3338 struct ieee80211_sta *sta,
3339 struct ieee80211_key_conf *key)
b481de9c 3340{
4a8a4322 3341 struct iwl_priv *priv = hw->priv;
dc822b5d 3342 const u8 *addr;
6e21f15c
AK
3343 int ret = 0;
3344 u8 sta_id = IWL_INVALID_STATION;
3345 u8 static_key;
b481de9c 3346
e1623446 3347 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3348
df878d8f 3349 if (iwl3945_mod_params.sw_crypto) {
e1623446 3350 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3351 return -EOPNOTSUPP;
3352 }
3353
42986796 3354 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3355 static_key = !iwl_is_associated(priv);
3356
3357 if (!static_key) {
c587de0b 3358 sta_id = iwl_find_station(priv, addr);
6e21f15c 3359 if (sta_id == IWL_INVALID_STATION) {
12514396 3360 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3361 addr);
3362 return -EINVAL;
3363 }
b481de9c
ZY
3364 }
3365
3366 mutex_lock(&priv->mutex);
af0053d6 3367 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3368 mutex_unlock(&priv->mutex);
15e869d8 3369
b481de9c 3370 switch (cmd) {
6e21f15c
AK
3371 case SET_KEY:
3372 if (static_key)
3373 ret = iwl3945_set_static_key(priv, key);
3374 else
3375 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3376 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3377 break;
3378 case DISABLE_KEY:
6e21f15c
AK
3379 if (static_key)
3380 ret = iwl3945_remove_static_key(priv);
3381 else
3382 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3383 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3384 break;
3385 default:
42986796 3386 ret = -EINVAL;
b481de9c
ZY
3387 }
3388
e1623446 3389 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3390
42986796 3391 return ret;
b481de9c
ZY
3392}
3393
b481de9c
ZY
3394/*****************************************************************************
3395 *
3396 * sysfs attributes
3397 *
3398 *****************************************************************************/
3399
d08853a3 3400#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3401
3402/*
3403 * The following adds a new attribute to the sysfs representation
3404 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3405 * used for controlling the debug level.
3406 *
3407 * See the level definitions in iwl for details.
a562a9dd 3408 *
3d816c77
RC
3409 * The debug_level being managed using sysfs below is a per device debug
3410 * level that is used instead of the global debug level if it (the per
3411 * device debug level) is set.
b481de9c 3412 */
40b8ec0b
SO
3413static ssize_t show_debug_level(struct device *d,
3414 struct device_attribute *attr, char *buf)
b481de9c 3415{
3d816c77
RC
3416 struct iwl_priv *priv = dev_get_drvdata(d);
3417 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3418}
40b8ec0b
SO
3419static ssize_t store_debug_level(struct device *d,
3420 struct device_attribute *attr,
b481de9c
ZY
3421 const char *buf, size_t count)
3422{
928841b1 3423 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3424 unsigned long val;
3425 int ret;
b481de9c 3426
40b8ec0b
SO
3427 ret = strict_strtoul(buf, 0, &val);
3428 if (ret)
978785a3 3429 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3430 else {
3d816c77 3431 priv->debug_level = val;
20594eb0
WYG
3432 if (iwl_alloc_traffic_mem(priv))
3433 IWL_ERR(priv,
3434 "Not enough memory to generate traffic log\n");
3435 }
b481de9c
ZY
3436 return strnlen(buf, count);
3437}
3438
40b8ec0b
SO
3439static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3440 show_debug_level, store_debug_level);
b481de9c 3441
d08853a3 3442#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3443
b481de9c
ZY
3444static ssize_t show_temperature(struct device *d,
3445 struct device_attribute *attr, char *buf)
3446{
928841b1 3447 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3448
775a6e27 3449 if (!iwl_is_alive(priv))
b481de9c
ZY
3450 return -EAGAIN;
3451
bb8c093b 3452 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3453}
3454
3455static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3456
b481de9c
ZY
3457static ssize_t show_tx_power(struct device *d,
3458 struct device_attribute *attr, char *buf)
3459{
928841b1 3460 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3461 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3462}
3463
3464static ssize_t store_tx_power(struct device *d,
3465 struct device_attribute *attr,
3466 const char *buf, size_t count)
3467{
928841b1 3468 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3469 char *p = (char *)buf;
3470 u32 val;
3471
3472 val = simple_strtoul(p, &p, 10);
3473 if (p == buf)
978785a3 3474 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3475 else
bb8c093b 3476 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3477
3478 return count;
3479}
3480
3481static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3482
3483static ssize_t show_flags(struct device *d,
3484 struct device_attribute *attr, char *buf)
3485{
928841b1 3486 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3487
8ccde88a 3488 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3489}
3490
3491static ssize_t store_flags(struct device *d,
3492 struct device_attribute *attr,
3493 const char *buf, size_t count)
3494{
928841b1 3495 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3496 u32 flags = simple_strtoul(buf, NULL, 0);
3497
3498 mutex_lock(&priv->mutex);
8ccde88a 3499 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3500 /* Cancel any currently running scans... */
af0053d6 3501 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3502 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3503 else {
e1623446 3504 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3505 flags);
8ccde88a 3506 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3507 iwlcore_commit_rxon(priv);
b481de9c
ZY
3508 }
3509 }
3510 mutex_unlock(&priv->mutex);
3511
3512 return count;
3513}
3514
3515static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3516
3517static ssize_t show_filter_flags(struct device *d,
3518 struct device_attribute *attr, char *buf)
3519{
928841b1 3520 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3521
3522 return sprintf(buf, "0x%04X\n",
8ccde88a 3523 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3524}
3525
3526static ssize_t store_filter_flags(struct device *d,
3527 struct device_attribute *attr,
3528 const char *buf, size_t count)
3529{
928841b1 3530 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3531 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3532
3533 mutex_lock(&priv->mutex);
8ccde88a 3534 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3535 /* Cancel any currently running scans... */
af0053d6 3536 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3537 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3538 else {
e1623446 3539 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3540 "0x%04X\n", filter_flags);
8ccde88a 3541 priv->staging_rxon.filter_flags =
b481de9c 3542 cpu_to_le32(filter_flags);
e0158e61 3543 iwlcore_commit_rxon(priv);
b481de9c
ZY
3544 }
3545 }
3546 mutex_unlock(&priv->mutex);
3547
3548 return count;
3549}
3550
3551static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3552 store_filter_flags);
3553
b481de9c
ZY
3554static ssize_t show_measurement(struct device *d,
3555 struct device_attribute *attr, char *buf)
3556{
4a8a4322 3557 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3558 struct iwl_spectrum_notification measure_report;
b481de9c 3559 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3560 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3561 unsigned long flags;
3562
3563 spin_lock_irqsave(&priv->lock, flags);
3564 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3565 spin_unlock_irqrestore(&priv->lock, flags);
3566 return 0;
3567 }
3568 memcpy(&measure_report, &priv->measure_report, size);
3569 priv->measurement_status = 0;
3570 spin_unlock_irqrestore(&priv->lock, flags);
3571
3572 while (size && (PAGE_SIZE - len)) {
3573 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3574 PAGE_SIZE - len, 1);
3575 len = strlen(buf);
3576 if (PAGE_SIZE - len)
3577 buf[len++] = '\n';
3578
3579 ofs += 16;
3580 size -= min(size, 16U);
3581 }
3582
3583 return len;
3584}
3585
3586static ssize_t store_measurement(struct device *d,
3587 struct device_attribute *attr,
3588 const char *buf, size_t count)
3589{
4a8a4322 3590 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3591 struct ieee80211_measurement_params params = {
8ccde88a 3592 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3593 .start_time = cpu_to_le64(priv->last_tsf),
3594 .duration = cpu_to_le16(1),
3595 };
3596 u8 type = IWL_MEASURE_BASIC;
3597 u8 buffer[32];
3598 u8 channel;
3599
3600 if (count) {
3601 char *p = buffer;
3602 strncpy(buffer, buf, min(sizeof(buffer), count));
3603 channel = simple_strtoul(p, NULL, 0);
3604 if (channel)
3605 params.channel = channel;
3606
3607 p = buffer;
3608 while (*p && *p != ' ')
3609 p++;
3610 if (*p)
3611 type = simple_strtoul(p + 1, NULL, 0);
3612 }
3613
e1623446 3614 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3615 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3616 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3617
3618 return count;
3619}
3620
3621static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3622 show_measurement, store_measurement);
b481de9c 3623
b481de9c
ZY
3624static ssize_t store_retry_rate(struct device *d,
3625 struct device_attribute *attr,
3626 const char *buf, size_t count)
3627{
4a8a4322 3628 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3629
3630 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3631 if (priv->retry_rate <= 0)
3632 priv->retry_rate = 1;
3633
3634 return count;
3635}
3636
3637static ssize_t show_retry_rate(struct device *d,
3638 struct device_attribute *attr, char *buf)
3639{
4a8a4322 3640 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3641 return sprintf(buf, "%d", priv->retry_rate);
3642}
3643
3644static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3645 store_retry_rate);
3646
d25aabb0 3647
b481de9c
ZY
3648static ssize_t show_channels(struct device *d,
3649 struct device_attribute *attr, char *buf)
3650{
8318d78a
JB
3651 /* all this shit doesn't belong into sysfs anyway */
3652 return 0;
b481de9c
ZY
3653}
3654
3655static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3656
3657static ssize_t show_statistics(struct device *d,
3658 struct device_attribute *attr, char *buf)
3659{
4a8a4322 3660 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3661 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3662 u32 len = 0, ofs = 0;
f2c7e521 3663 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3664 int rc = 0;
3665
775a6e27 3666 if (!iwl_is_alive(priv))
b481de9c
ZY
3667 return -EAGAIN;
3668
3669 mutex_lock(&priv->mutex);
ef8d5529 3670 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3671 mutex_unlock(&priv->mutex);
3672
3673 if (rc) {
3674 len = sprintf(buf,
3675 "Error sending statistics request: 0x%08X\n", rc);
3676 return len;
3677 }
3678
3679 while (size && (PAGE_SIZE - len)) {
3680 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3681 PAGE_SIZE - len, 1);
3682 len = strlen(buf);
3683 if (PAGE_SIZE - len)
3684 buf[len++] = '\n';
3685
3686 ofs += 16;
3687 size -= min(size, 16U);
3688 }
3689
3690 return len;
3691}
3692
3693static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3694
3695static ssize_t show_antenna(struct device *d,
3696 struct device_attribute *attr, char *buf)
3697{
4a8a4322 3698 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3699
775a6e27 3700 if (!iwl_is_alive(priv))
b481de9c
ZY
3701 return -EAGAIN;
3702
7e4bca5e 3703 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3704}
3705
3706static ssize_t store_antenna(struct device *d,
3707 struct device_attribute *attr,
3708 const char *buf, size_t count)
3709{
7530f85f 3710 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3711 int ant;
b481de9c
ZY
3712
3713 if (count == 0)
3714 return 0;
3715
3716 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3717 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3718 return count;
3719 }
3720
3721 if ((ant >= 0) && (ant <= 2)) {
e1623446 3722 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3723 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3724 } else
e1623446 3725 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3726
3727
3728 return count;
3729}
3730
3731static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3732
3733static ssize_t show_status(struct device *d,
3734 struct device_attribute *attr, char *buf)
3735{
928841b1 3736 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3737 if (!iwl_is_alive(priv))
b481de9c
ZY
3738 return -EAGAIN;
3739 return sprintf(buf, "0x%08x\n", (int)priv->status);
3740}
3741
3742static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3743
3744static ssize_t dump_error_log(struct device *d,
3745 struct device_attribute *attr,
3746 const char *buf, size_t count)
3747{
928841b1 3748 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3749 char *p = (char *)buf;
3750
3751 if (p[0] == '1')
928841b1 3752 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3753
3754 return strnlen(buf, count);
3755}
3756
3757static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3758
b481de9c
ZY
3759/*****************************************************************************
3760 *
a96a27f9 3761 * driver setup and tear down
b481de9c
ZY
3762 *
3763 *****************************************************************************/
3764
4a8a4322 3765static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3766{
d21050c7 3767 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3768
3769 init_waitqueue_head(&priv->wait_command_queue);
3770
bb8c093b
CH
3771 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3772 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3773 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3774 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3775 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3776 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3777 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3778 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3779 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3780 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3781
3782 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3783
3784 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3785 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3786}
3787
4a8a4322 3788static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3789{
bb8c093b 3790 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3791
e47eb6ad 3792 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3793 cancel_delayed_work(&priv->scan_check);
3794 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3795 cancel_work_sync(&priv->beacon_update);
3796}
3797
bb8c093b 3798static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3799 &dev_attr_antenna.attr,
3800 &dev_attr_channels.attr,
3801 &dev_attr_dump_errors.attr,
b481de9c
ZY
3802 &dev_attr_flags.attr,
3803 &dev_attr_filter_flags.attr,
b481de9c 3804 &dev_attr_measurement.attr,
b481de9c 3805 &dev_attr_retry_rate.attr,
b481de9c
ZY
3806 &dev_attr_statistics.attr,
3807 &dev_attr_status.attr,
3808 &dev_attr_temperature.attr,
b481de9c 3809 &dev_attr_tx_power.attr,
d08853a3 3810#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3811 &dev_attr_debug_level.attr,
3812#endif
b481de9c
ZY
3813 NULL
3814};
3815
bb8c093b 3816static struct attribute_group iwl3945_attribute_group = {
b481de9c 3817 .name = NULL, /* put in device directory */
bb8c093b 3818 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3819};
3820
bb8c093b
CH
3821static struct ieee80211_ops iwl3945_hw_ops = {
3822 .tx = iwl3945_mac_tx,
3823 .start = iwl3945_mac_start,
3824 .stop = iwl3945_mac_stop,
cbb6ab94 3825 .add_interface = iwl_mac_add_interface,
d8052319 3826 .remove_interface = iwl_mac_remove_interface,
4808368d 3827 .config = iwl_mac_config,
8ccde88a 3828 .configure_filter = iwl_configure_filter,
bb8c093b 3829 .set_key = iwl3945_mac_set_key,
488829f1 3830 .conf_tx = iwl_mac_conf_tx,
bd564261 3831 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3832 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3833 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3834};
3835
e52119c5 3836static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3837{
3838 int ret;
e6148917 3839 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3840
3841 priv->retry_rate = 1;
3842 priv->ibss_beacon = NULL;
3843
90a30a02
KA
3844 spin_lock_init(&priv->sta_lock);
3845 spin_lock_init(&priv->hcmd_lock);
3846
3847 INIT_LIST_HEAD(&priv->free_frames);
3848
3849 mutex_init(&priv->mutex);
d2dfe6df 3850 mutex_init(&priv->sync_cmd_mutex);
90a30a02
KA
3851
3852 /* Clear the driver's (not device's) station table */
c587de0b 3853 iwl_clear_stations_table(priv);
90a30a02 3854
90a30a02
KA
3855 priv->ieee_channels = NULL;
3856 priv->ieee_rates = NULL;
3857 priv->band = IEEE80211_BAND_2GHZ;
3858
3859 priv->iw_mode = NL80211_IFTYPE_STATION;
a13d276f 3860 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
90a30a02
KA
3861
3862 iwl_reset_qos(priv);
3863
3864 priv->qos_data.qos_active = 0;
3865 priv->qos_data.qos_cap.val = 0;
3866
3867 priv->rates_mask = IWL_RATES_MASK;
62ea9c5b 3868 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3869
e6148917
SO
3870 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3871 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3872 eeprom->version);
3873 ret = -EINVAL;
3874 goto err;
3875 }
3876 ret = iwl_init_channel_map(priv);
90a30a02
KA
3877 if (ret) {
3878 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3879 goto err;
3880 }
3881
e6148917
SO
3882 /* Set up txpower settings in driver for all channels */
3883 if (iwl3945_txpower_set_from_eeprom(priv)) {
3884 ret = -EIO;
3885 goto err_free_channel_map;
3886 }
3887
534166de 3888 ret = iwlcore_init_geos(priv);
90a30a02
KA
3889 if (ret) {
3890 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3891 goto err_free_channel_map;
3892 }
534166de
SO
3893 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3894
2a4ddaab
AK
3895 return 0;
3896
3897err_free_channel_map:
3898 iwl_free_channel_map(priv);
3899err:
3900 return ret;
3901}
3902
3903static int iwl3945_setup_mac(struct iwl_priv *priv)
3904{
3905 int ret;
3906 struct ieee80211_hw *hw = priv->hw;
3907
3908 hw->rate_control_algorithm = "iwl-3945-rs";
3909 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3910
3911 /* Tell mac80211 our characteristics */
3912 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b 3913 IEEE80211_HW_NOISE_DBM |
bc45a670
RC
3914 IEEE80211_HW_SPECTRUM_MGMT;
3915
3916 if (!priv->cfg->broken_powersave)
3917 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3918 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3919
3920 hw->wiphy->interface_modes =
3921 BIT(NL80211_IFTYPE_STATION) |
3922 BIT(NL80211_IFTYPE_ADHOC);
3923
5be83de5
JB
3924 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
3925 WIPHY_FLAG_DISABLE_BEACON_HINTS;
37184244 3926
1ecf9fc1
JB
3927 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3928 /* we create the 802.11 header and a zero-length SSID element */
3929 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3930
2a4ddaab
AK
3931 /* Default value; 4 EDCA QOS priorities */
3932 hw->queues = 4;
3933
534166de
SO
3934 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3935 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3936 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3937
534166de
SO
3938 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3939 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3940 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3941
2a4ddaab
AK
3942 ret = ieee80211_register_hw(priv->hw);
3943 if (ret) {
3944 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3945 return ret;
3946 }
3947 priv->mac80211_registered = 1;
90a30a02 3948
2a4ddaab 3949 return 0;
90a30a02
KA
3950}
3951
bb8c093b 3952static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3953{
3954 int err = 0;
4a8a4322 3955 struct iwl_priv *priv;
b481de9c 3956 struct ieee80211_hw *hw;
c0f20d91 3957 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3958 struct iwl3945_eeprom *eeprom;
0359facc 3959 unsigned long flags;
b481de9c 3960
cee53ddb
KA
3961 /***********************
3962 * 1. Allocating HW data
3963 * ********************/
3964
b481de9c
ZY
3965 /* mac80211 allocates memory for this device instance, including
3966 * space for this driver's private structure */
90a30a02 3967 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3968 if (hw == NULL) {
a3139c59 3969 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3970 err = -ENOMEM;
3971 goto out;
3972 }
b481de9c 3973 priv = hw->priv;
90a30a02 3974 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3975
90a30a02
KA
3976 /*
3977 * Disabling hardware scan means that mac80211 will perform scans
3978 * "the hard way", rather than using device's scan.
3979 */
df878d8f 3980 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3981 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3982 iwl3945_hw_ops.hw_scan = NULL;
3983 }
3984
90a30a02 3985
e1623446 3986 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3987 priv->cfg = cfg;
3988 priv->pci_dev = pdev;
40cefda9 3989 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3990
d08853a3 3991#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3992 atomic_set(&priv->restrict_refcnt, 0);
3993#endif
20594eb0
WYG
3994 if (iwl_alloc_traffic_mem(priv))
3995 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3996
cee53ddb
KA
3997 /***************************
3998 * 2. Initializing PCI bus
3999 * *************************/
b481de9c
ZY
4000 if (pci_enable_device(pdev)) {
4001 err = -ENODEV;
4002 goto out_ieee80211_free_hw;
4003 }
4004
4005 pci_set_master(pdev);
4006
284901a9 4007 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4008 if (!err)
284901a9 4009 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4010 if (err) {
978785a3 4011 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
4012 goto out_pci_disable_device;
4013 }
4014
4015 pci_set_drvdata(pdev, priv);
4016 err = pci_request_regions(pdev, DRV_NAME);
4017 if (err)
4018 goto out_pci_disable_device;
6440adb5 4019
cee53ddb
KA
4020 /***********************
4021 * 3. Read REV Register
4022 * ********************/
b481de9c
ZY
4023 priv->hw_base = pci_iomap(pdev, 0, 0);
4024 if (!priv->hw_base) {
4025 err = -ENODEV;
4026 goto out_pci_release_regions;
4027 }
4028
e1623446 4029 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4030 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4031 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4032
cee53ddb
KA
4033 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4034 * PCI Tx retries from interfering with C3 CPU state */
4035 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4036
731a29b7 4037 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
4038 * we should init now
4039 */
4040 spin_lock_init(&priv->reg_lock);
731a29b7 4041 spin_lock_init(&priv->lock);
a8b50a0a 4042
4843b5a7
RC
4043 /*
4044 * stop and reset the on-board processor just in case it is in a
4045 * strange state ... like being left stranded by a primary kernel
4046 * and this is now the kdump kernel trying to start up
4047 */
4048 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4049
cee53ddb
KA
4050 /***********************
4051 * 4. Read EEPROM
4052 * ********************/
90a30a02 4053
cee53ddb 4054 /* Read the EEPROM */
e6148917 4055 err = iwl_eeprom_init(priv);
cee53ddb 4056 if (err) {
15b1687c 4057 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4058 goto out_iounmap;
cee53ddb
KA
4059 }
4060 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4061 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4062 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4063 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4064 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4065
cee53ddb
KA
4066 /***********************
4067 * 5. Setup HW Constants
4068 * ********************/
b481de9c 4069 /* Device-specific setup */
3832ec9d 4070 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4071 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4072 goto out_eeprom_free;
b481de9c
ZY
4073 }
4074
cee53ddb
KA
4075 /***********************
4076 * 6. Setup priv
4077 * ********************/
cee53ddb 4078
90a30a02 4079 err = iwl3945_init_drv(priv);
b481de9c 4080 if (err) {
90a30a02 4081 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4082 goto out_unset_hw_params;
b481de9c
ZY
4083 }
4084
978785a3
TW
4085 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4086 priv->cfg->name);
cee53ddb 4087
cee53ddb 4088 /***********************
09f9bf79 4089 * 7. Setup Services
cee53ddb
KA
4090 * ********************/
4091
4092 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4093 iwl_disable_interrupts(priv);
cee53ddb
KA
4094 spin_unlock_irqrestore(&priv->lock, flags);
4095
2663516d
HS
4096 pci_enable_msi(priv->pci_dev);
4097
ef850d7c
MA
4098 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4099 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4100 if (err) {
4101 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4102 goto out_disable_msi;
4103 }
4104
cee53ddb 4105 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4106 if (err) {
15b1687c 4107 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4108 goto out_release_irq;
849e0dce 4109 }
849e0dce 4110
8ccde88a
SO
4111 iwl_set_rxon_channel(priv,
4112 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4113 iwl3945_setup_deferred_work(priv);
4114 iwl3945_setup_rx_handlers(priv);
008a9e3e 4115 iwl_power_initialize(priv);
cee53ddb 4116
cee53ddb 4117 /*********************************
09f9bf79 4118 * 8. Setup and Register mac80211
cee53ddb
KA
4119 * *******************************/
4120
2a4ddaab 4121 iwl_enable_interrupts(priv);
b481de9c 4122
2a4ddaab
AK
4123 err = iwl3945_setup_mac(priv);
4124 if (err)
4125 goto out_remove_sysfs;
cee53ddb 4126
a75fbe8d
AK
4127 err = iwl_dbgfs_register(priv, DRV_NAME);
4128 if (err)
4129 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4130
2663516d
HS
4131 /* Start monitoring the killswitch */
4132 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4133 2 * HZ);
4134
b481de9c
ZY
4135 return 0;
4136
cee53ddb 4137 out_remove_sysfs:
c8f16138
RC
4138 destroy_workqueue(priv->workqueue);
4139 priv->workqueue = NULL;
cee53ddb 4140 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4141 out_release_irq:
2663516d 4142 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4143 out_disable_msi:
4144 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4145 iwlcore_free_geos(priv);
4146 iwl_free_channel_map(priv);
4147 out_unset_hw_params:
4148 iwl3945_unset_hw_params(priv);
4149 out_eeprom_free:
4150 iwl_eeprom_free(priv);
b481de9c
ZY
4151 out_iounmap:
4152 pci_iounmap(pdev, priv->hw_base);
4153 out_pci_release_regions:
4154 pci_release_regions(pdev);
4155 out_pci_disable_device:
b481de9c 4156 pci_set_drvdata(pdev, NULL);
623d563e 4157 pci_disable_device(pdev);
b481de9c 4158 out_ieee80211_free_hw:
20594eb0 4159 iwl_free_traffic_mem(priv);
d7c76f4c 4160 ieee80211_free_hw(priv->hw);
b481de9c
ZY
4161 out:
4162 return err;
4163}
4164
c83dbf68 4165static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4166{
4a8a4322 4167 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4168 unsigned long flags;
b481de9c
ZY
4169
4170 if (!priv)
4171 return;
4172
e1623446 4173 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4174
a75fbe8d
AK
4175 iwl_dbgfs_unregister(priv);
4176
b481de9c 4177 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4178
d552bfb6
KA
4179 if (priv->mac80211_registered) {
4180 ieee80211_unregister_hw(priv->hw);
4181 priv->mac80211_registered = 0;
4182 } else {
4183 iwl3945_down(priv);
4184 }
b481de9c 4185
c166b25a
BC
4186 /*
4187 * Make sure device is reset to low power before unloading driver.
4188 * This may be redundant with iwl_down(), but there are paths to
4189 * run iwl_down() without calling apm_ops.stop(), and there are
4190 * paths to avoid running iwl_down() at all before leaving driver.
4191 * This (inexpensive) call *makes sure* device is reset.
4192 */
4193 priv->cfg->ops->lib->apm_ops.stop(priv);
4194
0359facc
MA
4195 /* make sure we flush any pending irq or
4196 * tasklet for the driver
4197 */
4198 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4199 iwl_disable_interrupts(priv);
0359facc
MA
4200 spin_unlock_irqrestore(&priv->lock, flags);
4201
4202 iwl_synchronize_irq(priv);
4203
bb8c093b 4204 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4205
71d449b5 4206 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4207
bb8c093b 4208 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4209
4210 if (priv->rxq.bd)
df833b1d 4211 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4212 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4213
3832ec9d 4214 iwl3945_unset_hw_params(priv);
c587de0b 4215 iwl_clear_stations_table(priv);
b481de9c 4216
6ef89d0a
MA
4217 /*netif_stop_queue(dev); */
4218 flush_workqueue(priv->workqueue);
4219
bb8c093b 4220 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4221 * priv->workqueue... so we can't take down the workqueue
4222 * until now... */
4223 destroy_workqueue(priv->workqueue);
4224 priv->workqueue = NULL;
20594eb0 4225 iwl_free_traffic_mem(priv);
b481de9c 4226
2663516d
HS
4227 free_irq(pdev->irq, priv);
4228 pci_disable_msi(pdev);
4229
b481de9c
ZY
4230 pci_iounmap(pdev, priv->hw_base);
4231 pci_release_regions(pdev);
4232 pci_disable_device(pdev);
4233 pci_set_drvdata(pdev, NULL);
4234
e6148917 4235 iwl_free_channel_map(priv);
534166de 4236 iwlcore_free_geos(priv);
805cee5b 4237 kfree(priv->scan);
b481de9c
ZY
4238 if (priv->ibss_beacon)
4239 dev_kfree_skb(priv->ibss_beacon);
4240
4241 ieee80211_free_hw(priv->hw);
4242}
4243
b481de9c
ZY
4244
4245/*****************************************************************************
4246 *
4247 * driver and module entry point
4248 *
4249 *****************************************************************************/
4250
bb8c093b 4251static struct pci_driver iwl3945_driver = {
b481de9c 4252 .name = DRV_NAME,
bb8c093b
CH
4253 .id_table = iwl3945_hw_card_ids,
4254 .probe = iwl3945_pci_probe,
4255 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4256#ifdef CONFIG_PM
6da3a13e
WYG
4257 .suspend = iwl_pci_suspend,
4258 .resume = iwl_pci_resume,
b481de9c
ZY
4259#endif
4260};
4261
bb8c093b 4262static int __init iwl3945_init(void)
b481de9c
ZY
4263{
4264
4265 int ret;
4266 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4267 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4268
4269 ret = iwl3945_rate_control_register();
4270 if (ret) {
a3139c59
SO
4271 printk(KERN_ERR DRV_NAME
4272 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4273 return ret;
4274 }
4275
bb8c093b 4276 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4277 if (ret) {
a3139c59 4278 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4279 goto error_register;
b481de9c 4280 }
b481de9c
ZY
4281
4282 return ret;
897e1cf2 4283
897e1cf2
RC
4284error_register:
4285 iwl3945_rate_control_unregister();
4286 return ret;
b481de9c
ZY
4287}
4288
bb8c093b 4289static void __exit iwl3945_exit(void)
b481de9c 4290{
bb8c093b 4291 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4292 iwl3945_rate_control_unregister();
b481de9c
ZY
4293}
4294
a0987a8d 4295MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4296
4e30cb69 4297module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
b481de9c 4298MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4e30cb69 4299module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
9c74d9fb
SO
4300MODULE_PARM_DESC(swcrypto,
4301 "using software crypto (default 1 [software])\n");
a562a9dd 4302#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4303module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
b481de9c 4304MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4305#endif
4e30cb69
WYG
4306module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
4307 int, S_IRUGO);
b481de9c 4308MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4e30cb69 4309module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
af48d048
SO
4310MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4311
bb8c093b
CH
4312module_exit(iwl3945_exit);
4313module_init(iwl3945_init);