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iwlagn: simplify ucode loading
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CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
d43c36dc 36#include <linux/sched.h>
b481de9c
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37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
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41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
WT
51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
17f841cd 54#include "iwl-sta.h"
b481de9c
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55#include "iwl-3945.h"
56#include "iwl-helpers.h"
5747d47f 57#include "iwl-core.h"
d20b3c65 58#include "iwl-dev.h"
81963d68 59#include "iwl-spectrum.h"
b481de9c 60
b481de9c
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61/*
62 * module name, copyright, version, etc.
b481de9c
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63 */
64
65#define DRV_DESCRIPTION \
66"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
67
d08853a3 68#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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69#define VD "d"
70#else
71#define VD
72#endif
73
81963d68
RC
74/*
75 * add "s" to indicate spectrum measurement included.
76 * we add it here to be consistent with previous releases in which
77 * this was configurable.
78 */
79#define DRV_VERSION IWLWIFI_VERSION VD "s"
1f447808 80#define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
a7b75207 81#define DRV_AUTHOR "<ilw@linux.intel.com>"
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82
83MODULE_DESCRIPTION(DRV_DESCRIPTION);
84MODULE_VERSION(DRV_VERSION);
a7b75207 85MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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86MODULE_LICENSE("GPL");
87
df878d8f
KA
88 /* module parameters */
89struct iwl_mod_params iwl3945_mod_params = {
9c74d9fb 90 .sw_crypto = 1,
af48d048 91 .restart_fw = 1,
df878d8f
KA
92 /* the rest are 0 by default */
93};
94
7e4bca5e
SO
95/**
96 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
97 * @priv: eeprom and antenna fields are used to determine antenna flags
98 *
99 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
100 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
101 *
102 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
103 * IWL_ANTENNA_MAIN - Force MAIN antenna
104 * IWL_ANTENNA_AUX - Force AUX antenna
105 */
106__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
107{
108 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
109
110 switch (iwl3945_mod_params.antenna) {
111 case IWL_ANTENNA_DIVERSITY:
112 return 0;
113
114 case IWL_ANTENNA_MAIN:
115 if (eeprom->antenna_switch_type)
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
118
119 case IWL_ANTENNA_AUX:
120 if (eeprom->antenna_switch_type)
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
123 }
124
125 /* bad antenna selector value */
126 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
127 iwl3945_mod_params.antenna);
128
129 return 0; /* "diversity" is default if error */
130}
131
6e21f15c 132static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
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133 struct ieee80211_key_conf *keyconf,
134 u8 sta_id)
135{
136 unsigned long flags;
137 __le16 key_flags = 0;
6e21f15c
AK
138 int ret;
139
140 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
141 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
142
143 if (sta_id == priv->hw_params.bcast_sta_id)
144 key_flags |= STA_KEY_MULTICAST_MSK;
145
146 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
147 keyconf->hw_key_idx = keyconf->keyidx;
148 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 149
b481de9c 150 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
151 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
152 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
153 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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154 keyconf->keylen);
155
c587de0b 156 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 157 keyconf->keylen);
6e21f15c 158
c587de0b 159 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 160 == STA_KEY_FLG_NO_ENC)
c587de0b 161 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
162 iwl_get_free_ucode_key_index(priv);
163 /* else, we are overriding an existing key => no need to allocated room
164 * in uCode. */
165
c587de0b 166 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
167 "no space for a new key");
168
c587de0b
TW
169 priv->stations[sta_id].sta.key.key_flags = key_flags;
170 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
171 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 172
6e21f15c
AK
173 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
174
c587de0b 175 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 176
b481de9c
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177 spin_unlock_irqrestore(&priv->sta_lock, flags);
178
6e21f15c
AK
179 return ret;
180}
181
182static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
183 struct ieee80211_key_conf *keyconf,
184 u8 sta_id)
185{
186 return -EOPNOTSUPP;
187}
188
189static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
190 struct ieee80211_key_conf *keyconf,
191 u8 sta_id)
192{
193 return -EOPNOTSUPP;
b481de9c
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194}
195
4a8a4322 196static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
201 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
202 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 203 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
204 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
205 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
206 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
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207 spin_unlock_irqrestore(&priv->sta_lock, flags);
208
e1623446 209 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 210 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
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211 return 0;
212}
213
fa11d525 214static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
215 struct ieee80211_key_conf *keyconf, u8 sta_id)
216{
217 int ret = 0;
218
219 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
220
221 switch (keyconf->alg) {
222 case ALG_CCMP:
223 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
224 break;
225 case ALG_TKIP:
226 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
227 break;
228 case ALG_WEP:
229 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
230 break;
231 default:
1e680233 232 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
233 ret = -EINVAL;
234 }
235
236 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
237 keyconf->alg, keyconf->keylen, keyconf->keyidx,
238 sta_id, ret);
239
240 return ret;
241}
242
243static int iwl3945_remove_static_key(struct iwl_priv *priv)
244{
245 int ret = -EOPNOTSUPP;
246
247 return ret;
248}
249
250static int iwl3945_set_static_key(struct iwl_priv *priv,
251 struct ieee80211_key_conf *key)
252{
253 if (key->alg == ALG_WEP)
254 return -EOPNOTSUPP;
255
256 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
257 return -EINVAL;
258}
259
4a8a4322 260static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
261{
262 struct list_head *element;
263
e1623446 264 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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265 priv->frames_count);
266
267 while (!list_empty(&priv->free_frames)) {
268 element = priv->free_frames.next;
269 list_del(element);
bb8c093b 270 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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271 priv->frames_count--;
272 }
273
274 if (priv->frames_count) {
39aadf8c 275 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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276 priv->frames_count);
277 priv->frames_count = 0;
278 }
279}
280
4a8a4322 281static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 282{
bb8c093b 283 struct iwl3945_frame *frame;
b481de9c
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284 struct list_head *element;
285 if (list_empty(&priv->free_frames)) {
286 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
287 if (!frame) {
15b1687c 288 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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289 return NULL;
290 }
291
292 priv->frames_count++;
293 return frame;
294 }
295
296 element = priv->free_frames.next;
297 list_del(element);
bb8c093b 298 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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299}
300
4a8a4322 301static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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302{
303 memset(frame, 0, sizeof(*frame));
304 list_add(&frame->list, &priv->free_frames);
305}
306
4a8a4322 307unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 308 struct ieee80211_hdr *hdr,
73ec1cc2 309 int left)
b481de9c
ZY
310{
311
8ccde88a 312 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
313 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
314 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
315 return 0;
316
317 if (priv->ibss_beacon->len > left)
318 return 0;
319
320 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
321
322 return priv->ibss_beacon->len;
323}
324
4a8a4322 325static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 326{
bb8c093b 327 struct iwl3945_frame *frame;
b481de9c
ZY
328 unsigned int frame_size;
329 int rc;
330 u8 rate;
331
bb8c093b 332 frame = iwl3945_get_free_frame(priv);
b481de9c
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333
334 if (!frame) {
15b1687c 335 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
336 "command.\n");
337 return -ENOMEM;
338 }
339
8ccde88a 340 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 341
bb8c093b 342 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 343
518099a8 344 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
345 &frame->u.cmd[0]);
346
bb8c093b 347 iwl3945_free_frame(priv, frame);
b481de9c
ZY
348
349 return rc;
350}
351
4a8a4322 352static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 353{
3832ec9d 354 if (priv->shared_virt)
b481de9c 355 pci_free_consistent(priv->pci_dev,
bb8c093b 356 sizeof(struct iwl3945_shared),
3832ec9d
AK
357 priv->shared_virt,
358 priv->shared_phys);
b481de9c
ZY
359}
360
4a8a4322 361static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 362 struct ieee80211_tx_info *info,
c2acea8e 363 struct iwl_device_cmd *cmd,
b481de9c 364 struct sk_buff *skb_frag,
6e21f15c 365 int sta_id)
b481de9c 366{
9744c91f 367 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 368 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
369
370 switch (keyinfo->alg) {
371 case ALG_CCMP:
9744c91f
AK
372 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
373 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
e1623446 374 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
375 break;
376
377 case ALG_TKIP:
b481de9c
ZY
378 break;
379
380 case ALG_WEP:
9744c91f 381 tx_cmd->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 382 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
383
384 if (keyinfo->keylen == 13)
9744c91f 385 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 386
9744c91f 387 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 388
e1623446 389 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 390 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
391 break;
392
b481de9c 393 default:
978785a3 394 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
395 break;
396 }
397}
398
399/*
400 * handle build REPLY_TX command notification.
401 */
4a8a4322 402static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 403 struct iwl_device_cmd *cmd,
e039fa4a 404 struct ieee80211_tx_info *info,
e52119c5 405 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 406{
9744c91f
AK
407 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
408 __le32 tx_flags = tx_cmd->tx_flags;
fd7c8a40 409 __le16 fc = hdr->frame_control;
b481de9c 410
9744c91f 411 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 412 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 413 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 414 if (ieee80211_is_mgmt(fc))
b481de9c 415 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 416 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
417 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
418 tx_flags |= TX_CMD_FLG_TSF_MSK;
419 } else {
420 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422 }
423
9744c91f 424 tx_cmd->sta_id = std_id;
8b7b1e05 425 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
426 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
427
fd7c8a40
HH
428 if (ieee80211_is_data_qos(fc)) {
429 u8 *qc = ieee80211_get_qos_ctl(hdr);
9744c91f 430 tx_cmd->tid_tspec = qc[0] & 0xf;
b481de9c 431 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 432 } else {
b481de9c 433 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 434 }
b481de9c 435
37dc70fe 436 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
b481de9c
ZY
437
438 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
439 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
440
441 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
442 if (ieee80211_is_mgmt(fc)) {
443 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
9744c91f 444 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 445 else
9744c91f 446 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 447 } else {
9744c91f 448 tx_cmd->timeout.pm_frame_timeout = 0;
ab53d8af 449 }
b481de9c 450
9744c91f
AK
451 tx_cmd->driver_txop = 0;
452 tx_cmd->tx_flags = tx_flags;
453 tx_cmd->next_frame_len = 0;
b481de9c
ZY
454}
455
b481de9c
ZY
456/*
457 * start REPLY_TX command process
458 */
4a8a4322 459static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
460{
461 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 462 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9744c91f 463 struct iwl3945_tx_cmd *tx_cmd;
188cf6c7 464 struct iwl_tx_queue *txq = NULL;
d20b3c65 465 struct iwl_queue *q = NULL;
c2acea8e
JB
466 struct iwl_device_cmd *out_cmd;
467 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
468 dma_addr_t phys_addr;
469 dma_addr_t txcmd_phys;
e52119c5 470 int txq_id = skb_get_queue_mapping(skb);
df833b1d 471 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
472 u8 id;
473 u8 unicast;
b481de9c 474 u8 sta_id;
54dbb525 475 u8 tid = 0;
b481de9c 476 u16 seq_number = 0;
fd7c8a40 477 __le16 fc;
b481de9c 478 u8 wait_write_ptr = 0;
54dbb525 479 u8 *qc = NULL;
b481de9c
ZY
480 unsigned long flags;
481 int rc;
482
483 spin_lock_irqsave(&priv->lock, flags);
775a6e27 484 if (iwl_is_rfkill(priv)) {
e1623446 485 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
486 goto drop_unlock;
487 }
488
e039fa4a 489 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 490 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
491 goto drop_unlock;
492 }
493
494 unicast = !is_multicast_ether_addr(hdr->addr1);
495 id = 0;
496
fd7c8a40 497 fc = hdr->frame_control;
b481de9c 498
d08853a3 499#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 500 if (ieee80211_is_auth(fc))
e1623446 501 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 502 else if (ieee80211_is_assoc_req(fc))
e1623446 503 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 504 else if (ieee80211_is_reassoc_req(fc))
e1623446 505 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
506#endif
507
aa065263 508 /* drop all non-injected data frame if we are not associated */
914233d6 509 if (ieee80211_is_data(fc) &&
aa065263 510 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
8ccde88a 511 (!iwl_is_associated(priv) ||
05c914fe 512 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 513 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
514 goto drop_unlock;
515 }
516
517 spin_unlock_irqrestore(&priv->lock, flags);
518
7294ec95 519 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
520
521 /* Find (or create) index into station table for destination station */
aa065263
GS
522 if (info->flags & IEEE80211_TX_CTL_INJECTED)
523 sta_id = priv->hw_params.bcast_sta_id;
524 else
525 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 526 if (sta_id == IWL_INVALID_STATION) {
e1623446 527 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 528 hdr->addr1);
b481de9c
ZY
529 goto drop;
530 }
531
e1623446 532 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 533
fd7c8a40
HH
534 if (ieee80211_is_data_qos(fc)) {
535 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 536 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
537 if (unlikely(tid >= MAX_TID_COUNT))
538 goto drop;
c587de0b 539 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
540 IEEE80211_SCTL_SEQ;
541 hdr->seq_ctrl = cpu_to_le16(seq_number) |
542 (hdr->seq_ctrl &
c1b4aa3f 543 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
544 seq_number += 0x10;
545 }
6440adb5
BC
546
547 /* Descriptor for chosen Tx queue */
188cf6c7 548 txq = &priv->txq[txq_id];
b481de9c
ZY
549 q = &txq->q;
550
dc57a303
ZY
551 if ((iwl_queue_space(q) < q->high_mark))
552 goto drop;
553
b481de9c
ZY
554 spin_lock_irqsave(&priv->lock, flags);
555
fc4b6853 556 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 557
6440adb5 558 /* Set up driver data for this TFD */
dbb6654c 559 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 560 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
561
562 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 563 out_cmd = txq->cmd[idx];
c2acea8e 564 out_meta = &txq->meta[idx];
9744c91f 565 tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 566 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
9744c91f 567 memset(tx_cmd, 0, sizeof(*tx_cmd));
6440adb5
BC
568
569 /*
570 * Set up the Tx-command (not MAC!) header.
571 * Store the chosen Tx queue and TFD index within the sequence field;
572 * after Tx, uCode's Tx response will return this value so driver can
573 * locate the frame within the tx queue and do post-tx processing.
574 */
b481de9c
ZY
575 out_cmd->hdr.cmd = REPLY_TX;
576 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 577 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
578
579 /* Copy MAC header from skb into command buffer */
9744c91f 580 memcpy(tx_cmd->hdr, hdr, hdr_len);
b481de9c 581
df833b1d
RC
582
583 if (info->control.hw_key)
584 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
585
586 /* TODO need this for burst mode later on */
587 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
588
589 /* set is_hcca to 0; it probably will never be implemented */
590 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
591
592 /* Total # bytes to be transmitted */
593 len = (u16)skb->len;
9744c91f 594 tx_cmd->len = cpu_to_le16(len);
df833b1d 595
20594eb0 596 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 597 iwl_update_stats(priv, true, fc, len);
9744c91f
AK
598 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
599 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
df833b1d
RC
600
601 if (!ieee80211_has_morefrags(hdr->frame_control)) {
602 txq->need_update = 1;
603 if (qc)
c587de0b 604 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
605 } else {
606 wait_write_ptr = 1;
607 txq->need_update = 0;
608 }
609
610 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
611 le16_to_cpu(out_cmd->hdr.sequence));
9744c91f
AK
612 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
613 iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
614 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
df833b1d
RC
615 ieee80211_hdrlen(fc));
616
6440adb5
BC
617 /*
618 * Use the first empty entry in this queue's command buffer array
619 * to contain the Tx command and MAC header concatenated together
620 * (payload data will be in another buffer).
621 * Size of this varies, due to varying MAC header length.
622 * If end is not dword aligned, we'll have 2 extra bytes at the end
623 * of the MAC header (device reads on dword boundaries).
624 * We'll tell device about this padding later.
625 */
3832ec9d 626 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 627 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
628
629 len_org = len;
630 len = (len + 3) & ~3;
631
632 if (len_org != len)
633 len_org = 1;
634 else
635 len_org = 0;
636
6440adb5
BC
637 /* Physical address of this Tx command's header (not MAC header!),
638 * within command buffer array. */
df833b1d
RC
639 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
640 len, PCI_DMA_TODEVICE);
641 /* we do not map meta data ... so we can safely access address to
642 * provide to unmap command*/
c2acea8e
JB
643 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
644 pci_unmap_len_set(out_meta, len, len);
b481de9c 645
6440adb5
BC
646 /* Add buffer containing Tx command and MAC(!) header to TFD's
647 * first entry */
7aaa1d79
SO
648 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
649 txcmd_phys, len, 1, 0);
b481de9c 650
b481de9c 651
6440adb5
BC
652 /* Set up TFD's 2nd entry to point directly to remainder of skb,
653 * if any (802.11 null frames have no payload). */
b481de9c
ZY
654 len = skb->len - hdr_len;
655 if (len) {
656 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
657 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
658 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
659 phys_addr, len,
660 0, U32_PAD(len));
b481de9c
ZY
661 }
662
b481de9c 663
6440adb5 664 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 665 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 666 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
667 spin_unlock_irqrestore(&priv->lock, flags);
668
669 if (rc)
670 return rc;
671
d20b3c65 672 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
673 && priv->mac80211_registered) {
674 if (wait_write_ptr) {
675 spin_lock_irqsave(&priv->lock, flags);
676 txq->need_update = 1;
4f3602c8 677 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
678 spin_unlock_irqrestore(&priv->lock, flags);
679 }
680
e4e72fb4 681 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
682 }
683
684 return 0;
685
686drop_unlock:
687 spin_unlock_irqrestore(&priv->lock, flags);
688drop:
689 return -1;
690}
691
b481de9c
ZY
692#define BEACON_TIME_MASK_LOW 0x00FFFFFF
693#define BEACON_TIME_MASK_HIGH 0xFF000000
694#define TIME_UNIT 1024
695
696/*
697 * extended beacon time format
698 * time in usec will be changed into a 32-bit value in 8:24 format
699 * the high 1 byte is the beacon counts
700 * the lower 3 bytes is the time in usec within one beacon interval
701 */
702
bb8c093b 703static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
704{
705 u32 quot;
706 u32 rem;
707 u32 interval = beacon_interval * 1024;
708
709 if (!interval || !usec)
710 return 0;
711
712 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
713 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
714
715 return (quot << 24) + rem;
716}
717
718/* base is usually what we get from ucode with each received frame,
719 * the same as HW timer counter counting down
720 */
721
bb8c093b 722static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
723{
724 u32 base_low = base & BEACON_TIME_MASK_LOW;
725 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
726 u32 interval = beacon_interval * TIME_UNIT;
727 u32 res = (base & BEACON_TIME_MASK_HIGH) +
728 (addon & BEACON_TIME_MASK_HIGH);
729
730 if (base_low > addon_low)
731 res += base_low - addon_low;
732 else if (base_low < addon_low) {
733 res += interval + base_low - addon_low;
734 res += (1 << 24);
735 } else
736 res += (1 << 24);
737
738 return cpu_to_le32(res);
739}
740
4a8a4322 741static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
742 struct ieee80211_measurement_params *params,
743 u8 type)
744{
600c0e11 745 struct iwl_spectrum_cmd spectrum;
2f301227 746 struct iwl_rx_packet *pkt;
c2d79b48 747 struct iwl_host_cmd cmd = {
b481de9c
ZY
748 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
749 .data = (void *)&spectrum,
c2acea8e 750 .flags = CMD_WANT_SKB,
b481de9c
ZY
751 };
752 u32 add_time = le64_to_cpu(params->start_time);
753 int rc;
754 int spectrum_resp_status;
755 int duration = le16_to_cpu(params->duration);
756
8ccde88a 757 if (iwl_is_associated(priv))
b481de9c 758 add_time =
bb8c093b 759 iwl3945_usecs_to_beacons(
b481de9c
ZY
760 le64_to_cpu(params->start_time) - priv->last_tsf,
761 le16_to_cpu(priv->rxon_timing.beacon_interval));
762
763 memset(&spectrum, 0, sizeof(spectrum));
764
765 spectrum.channel_count = cpu_to_le16(1);
766 spectrum.flags =
767 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
768 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
769 cmd.len = sizeof(spectrum);
770 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
771
8ccde88a 772 if (iwl_is_associated(priv))
b481de9c 773 spectrum.start_time =
bb8c093b 774 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
775 add_time,
776 le16_to_cpu(priv->rxon_timing.beacon_interval));
777 else
778 spectrum.start_time = 0;
779
780 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
781 spectrum.channels[0].channel = params->channel;
782 spectrum.channels[0].type = type;
8ccde88a 783 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
784 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
785 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
786
518099a8 787 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
788 if (rc)
789 return rc;
790
2f301227
ZY
791 pkt = (struct iwl_rx_packet *)cmd.reply_page;
792 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 793 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
794 rc = -EIO;
795 }
796
2f301227 797 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
b481de9c
ZY
798 switch (spectrum_resp_status) {
799 case 0: /* Command will be handled */
2f301227 800 if (pkt->u.spectrum.id != 0xff) {
e1623446 801 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
2f301227 802 pkt->u.spectrum.id);
b481de9c
ZY
803 priv->measurement_status &= ~MEASUREMENT_READY;
804 }
805 priv->measurement_status |= MEASUREMENT_ACTIVE;
806 rc = 0;
807 break;
808
809 case 1: /* Command will not be handled */
810 rc = -EAGAIN;
811 break;
812 }
813
64a76b50 814 iwl_free_pages(priv, cmd.reply_page);
b481de9c
ZY
815
816 return rc;
817}
b481de9c 818
4a8a4322 819static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 820 struct iwl_rx_mem_buffer *rxb)
b481de9c 821{
2f301227 822 struct iwl_rx_packet *pkt = rxb_addr(rxb);
3d24a9f7 823 struct iwl_alive_resp *palive;
b481de9c
ZY
824 struct delayed_work *pwork;
825
826 palive = &pkt->u.alive_frame;
827
e1623446 828 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
829 "0x%01X 0x%01X\n",
830 palive->is_valid, palive->ver_type,
831 palive->ver_subtype);
832
833 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 834 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
835 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
836 sizeof(struct iwl_alive_resp));
b481de9c
ZY
837 pwork = &priv->init_alive_start;
838 } else {
e1623446 839 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 840 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 841 sizeof(struct iwl_alive_resp));
b481de9c 842 pwork = &priv->alive_start;
bb8c093b 843 iwl3945_disable_events(priv);
b481de9c
ZY
844 }
845
846 /* We delay the ALIVE response by 5ms to
847 * give the HW RF Kill time to activate... */
848 if (palive->is_valid == UCODE_VALID_OK)
849 queue_delayed_work(priv->workqueue, pwork,
850 msecs_to_jiffies(5));
851 else
39aadf8c 852 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
853}
854
4a8a4322 855static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 856 struct iwl_rx_mem_buffer *rxb)
b481de9c 857{
c7e035a9 858#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 859 struct iwl_rx_packet *pkt = rxb_addr(rxb);
c7e035a9 860#endif
b481de9c 861
e1623446 862 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
863 return;
864}
865
bb8c093b 866static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 867{
4a8a4322
AK
868 struct iwl_priv *priv =
869 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
870 struct sk_buff *beacon;
871
872 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 873 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
874
875 if (!beacon) {
15b1687c 876 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
877 return;
878 }
879
880 mutex_lock(&priv->mutex);
881 /* new beacon skb is allocated every time; dispose previous.*/
882 if (priv->ibss_beacon)
883 dev_kfree_skb(priv->ibss_beacon);
884
885 priv->ibss_beacon = beacon;
886 mutex_unlock(&priv->mutex);
887
bb8c093b 888 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
889}
890
4a8a4322 891static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 892 struct iwl_rx_mem_buffer *rxb)
b481de9c 893{
d08853a3 894#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 895 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b 896 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
897 u8 rate = beacon->beacon_notify_hdr.rate;
898
e1623446 899 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
900 "tsf %d %d rate %d\n",
901 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
902 beacon->beacon_notify_hdr.failure_frame,
903 le32_to_cpu(beacon->ibss_mgr_status),
904 le32_to_cpu(beacon->high_tsf),
905 le32_to_cpu(beacon->low_tsf), rate);
906#endif
907
05c914fe 908 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
909 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
910 queue_work(priv->workqueue, &priv->beacon_update);
911}
912
b481de9c
ZY
913/* Handle notification from uCode that card's power state is changing
914 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 915static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 916 struct iwl_rx_mem_buffer *rxb)
b481de9c 917{
2f301227 918 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
919 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
920 unsigned long status = priv->status;
921
4c423a2b 922 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
923 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
924 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
925
5d49f498 926 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
927 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
928
929 if (flags & HW_CARD_DISABLED)
930 set_bit(STATUS_RF_KILL_HW, &priv->status);
931 else
932 clear_bit(STATUS_RF_KILL_HW, &priv->status);
933
934
af0053d6 935 iwl_scan_cancel(priv);
b481de9c
ZY
936
937 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
938 test_bit(STATUS_RF_KILL_HW, &priv->status)))
939 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
940 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
941 else
942 wake_up_interruptible(&priv->wait_command_queue);
943}
944
945/**
bb8c093b 946 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
947 *
948 * Setup the RX handlers for each of the reply types sent from the uCode
949 * to the host.
950 *
951 * This function chains into the hardware specific files for them to setup
952 * any hardware specific handlers as well.
953 */
4a8a4322 954static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 955{
bb8c093b
CH
956 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
957 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 958 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 959 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
960 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
961 iwl_rx_spectrum_measure_notif;
030f05ed 962 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 963 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 964 iwl_rx_pm_debug_statistics_notif;
bb8c093b 965 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 966
9fbab516
BC
967 /*
968 * The same handler is used for both the REPLY to a discrete
969 * statistics request from the host as well as for the periodic
970 * statistics notifications (after received beacons) from the uCode.
b481de9c 971 */
bb8c093b
CH
972 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
973 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 974
cade0eb2 975 iwl_setup_rx_scan_handlers(priv);
bb8c093b 976 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 977
9fbab516 978 /* Set up hardware specific Rx handlers */
bb8c093b 979 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
980}
981
b481de9c
ZY
982/************************** RX-FUNCTIONS ****************************/
983/*
984 * Rx theory of operation
985 *
986 * The host allocates 32 DMA target addresses and passes the host address
987 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
988 * 0 to 31
989 *
990 * Rx Queue Indexes
991 * The host/firmware share two index registers for managing the Rx buffers.
992 *
993 * The READ index maps to the first position that the firmware may be writing
994 * to -- the driver can read up to (but not including) this position and get
995 * good data.
996 * The READ index is managed by the firmware once the card is enabled.
997 *
998 * The WRITE index maps to the last position the driver has read from -- the
999 * position preceding WRITE is the last slot the firmware can place a packet.
1000 *
1001 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1002 * WRITE = READ.
1003 *
9fbab516 1004 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1005 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1006 *
9fbab516 1007 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1008 * and fire the RX interrupt. The driver can then query the READ index and
1009 * process as many packets as possible, moving the WRITE index forward as it
1010 * resets the Rx queue buffers with new memory.
1011 *
1012 * The management in the driver is as follows:
1013 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1014 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1015 * to replenish the iwl->rxq->rx_free.
bb8c093b 1016 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1017 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1018 * 'processed' and 'read' driver indexes as well)
1019 * + A received packet is processed and handed to the kernel network stack,
1020 * detached from the iwl->rxq. The driver 'processed' index is updated.
1021 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1022 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1023 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1024 * were enough free buffers and RX_STALLED is set it is cleared.
1025 *
1026 *
1027 * Driver sequence:
1028 *
9fbab516 1029 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1030 * iwl3945_rx_queue_restock
9fbab516 1031 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1032 * queue, updates firmware pointers, and updates
1033 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1034 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1035 *
1036 * -- enable interrupts --
6100b588 1037 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1038 * READ INDEX, detaching the SKB from the pool.
1039 * Moves the packet buffer from queue to rx_used.
bb8c093b 1040 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1041 * slots.
1042 * ...
1043 *
1044 */
1045
b481de9c 1046/**
9fbab516 1047 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1048 */
4a8a4322 1049static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1050 dma_addr_t dma_addr)
1051{
1052 return cpu_to_le32((u32)dma_addr);
1053}
1054
1055/**
bb8c093b 1056 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1057 *
9fbab516 1058 * If there are slots in the RX queue that need to be restocked,
b481de9c 1059 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1060 * as we can, pulling from rx_free.
b481de9c
ZY
1061 *
1062 * This moves the 'write' index forward to catch up with 'processed', and
1063 * also updates the memory address in the firmware to reference the new
1064 * target buffer.
1065 */
4a8a4322 1066static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1067{
cc2f362c 1068 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1069 struct list_head *element;
6100b588 1070 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1071 unsigned long flags;
1072 int write, rc;
1073
1074 spin_lock_irqsave(&rxq->lock, flags);
1075 write = rxq->write & ~0x7;
37d68317 1076 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1077 /* Get next free Rx buffer, remove from free list */
b481de9c 1078 element = rxq->rx_free.next;
6100b588 1079 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1080 list_del(element);
6440adb5
BC
1081
1082 /* Point to Rx buffer via next RBD in circular buffer */
2f301227 1083 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
b481de9c
ZY
1084 rxq->queue[rxq->write] = rxb;
1085 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1086 rxq->free_count--;
1087 }
1088 spin_unlock_irqrestore(&rxq->lock, flags);
1089 /* If the pre-allocated buffer pool is dropping low, schedule to
1090 * refill it */
1091 if (rxq->free_count <= RX_LOW_WATERMARK)
1092 queue_work(priv->workqueue, &priv->rx_replenish);
1093
1094
6440adb5
BC
1095 /* If we've added more space for the firmware to place data, tell it.
1096 * Increment device's write pointer in multiples of 8. */
d14d4440 1097 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1098 || (abs(rxq->write - rxq->read) > 7)) {
1099 spin_lock_irqsave(&rxq->lock, flags);
1100 rxq->need_update = 1;
1101 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1102 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1103 if (rc)
1104 return rc;
1105 }
1106
1107 return 0;
1108}
1109
1110/**
bb8c093b 1111 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1112 *
1113 * When moving to rx_free an SKB is allocated for the slot.
1114 *
bb8c093b 1115 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1116 * This is called as a scheduled work item (except for during initialization)
b481de9c 1117 */
d14d4440 1118static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1119{
cc2f362c 1120 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1121 struct list_head *element;
6100b588 1122 struct iwl_rx_mem_buffer *rxb;
2f301227 1123 struct page *page;
b481de9c 1124 unsigned long flags;
29b1b268 1125 gfp_t gfp_mask = priority;
72240498
AK
1126
1127 while (1) {
1128 spin_lock_irqsave(&rxq->lock, flags);
1129
1130 if (list_empty(&rxq->rx_used)) {
1131 spin_unlock_irqrestore(&rxq->lock, flags);
1132 return;
1133 }
72240498 1134 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1135
f82a924c 1136 if (rxq->free_count > RX_LOW_WATERMARK)
29b1b268 1137 gfp_mask |= __GFP_NOWARN;
2f301227
ZY
1138
1139 if (priv->hw_params.rx_page_order > 0)
29b1b268 1140 gfp_mask |= __GFP_COMP;
2f301227 1141
6440adb5 1142 /* Alloc a new receive buffer */
29b1b268 1143 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
2f301227 1144 if (!page) {
b481de9c 1145 if (net_ratelimit())
f82a924c
RC
1146 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1147 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1148 net_ratelimit())
1149 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1150 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1151 rxq->free_count);
b481de9c
ZY
1152 /* We don't reschedule replenish work here -- we will
1153 * call the restock method and if it still needs
1154 * more buffers it will schedule replenish */
1155 break;
1156 }
12342c47 1157
de0bd508
RC
1158 spin_lock_irqsave(&rxq->lock, flags);
1159 if (list_empty(&rxq->rx_used)) {
1160 spin_unlock_irqrestore(&rxq->lock, flags);
2f301227 1161 __free_pages(page, priv->hw_params.rx_page_order);
de0bd508
RC
1162 return;
1163 }
1164 element = rxq->rx_used.next;
1165 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1166 list_del(element);
1167 spin_unlock_irqrestore(&rxq->lock, flags);
1168
2f301227 1169 rxb->page = page;
6440adb5 1170 /* Get physical address of RB/SKB */
2f301227
ZY
1171 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
1172 PAGE_SIZE << priv->hw_params.rx_page_order,
1173 PCI_DMA_FROMDEVICE);
72240498
AK
1174
1175 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1176
b481de9c
ZY
1177 list_add_tail(&rxb->list, &rxq->rx_free);
1178 rxq->free_count++;
2f301227
ZY
1179 priv->alloc_rxb_page++;
1180
72240498 1181 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1182 }
5c0eef96
MA
1183}
1184
df833b1d
RC
1185void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1186{
1187 unsigned long flags;
1188 int i;
1189 spin_lock_irqsave(&rxq->lock, flags);
1190 INIT_LIST_HEAD(&rxq->rx_free);
1191 INIT_LIST_HEAD(&rxq->rx_used);
1192 /* Fill the rx_used queue with _all_ of the Rx buffers */
1193 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1194 /* In the reset function, these buffers may have been allocated
1195 * to an SKB, so we need to unmap and free potential storage */
2f301227
ZY
1196 if (rxq->pool[i].page != NULL) {
1197 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1198 PAGE_SIZE << priv->hw_params.rx_page_order,
1199 PCI_DMA_FROMDEVICE);
64a76b50 1200 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1201 rxq->pool[i].page = NULL;
df833b1d
RC
1202 }
1203 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1204 }
1205
1206 /* Set us so that we have processed and used all buffers, but have
1207 * not restocked the Rx queue with fresh buffers */
1208 rxq->read = rxq->write = 0;
d14d4440 1209 rxq->write_actual = 0;
2f301227 1210 rxq->free_count = 0;
df833b1d
RC
1211 spin_unlock_irqrestore(&rxq->lock, flags);
1212}
df833b1d 1213
5c0eef96
MA
1214void iwl3945_rx_replenish(void *data)
1215{
4a8a4322 1216 struct iwl_priv *priv = data;
5c0eef96
MA
1217 unsigned long flags;
1218
d14d4440 1219 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1220
1221 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1222 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1223 spin_unlock_irqrestore(&priv->lock, flags);
1224}
1225
d14d4440
AK
1226static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1227{
1228 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1229
1230 iwl3945_rx_queue_restock(priv);
1231}
1232
1233
df833b1d
RC
1234/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1235 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1236 * This free routine walks the list of POOL entries and if SKB is set to
1237 * non NULL it is unmapped and freed
1238 */
1239static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1240{
1241 int i;
1242 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
2f301227
ZY
1243 if (rxq->pool[i].page != NULL) {
1244 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1245 PAGE_SIZE << priv->hw_params.rx_page_order,
1246 PCI_DMA_FROMDEVICE);
64a76b50 1247 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1248 rxq->pool[i].page = NULL;
df833b1d
RC
1249 }
1250 }
1251
1252 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1253 rxq->dma_addr);
1254 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1255 rxq->rb_stts, rxq->rb_stts_dma);
1256 rxq->bd = NULL;
1257 rxq->rb_stts = NULL;
1258}
df833b1d
RC
1259
1260
b481de9c
ZY
1261/* Convert linear signal-to-noise ratio into dB */
1262static u8 ratio2dB[100] = {
1263/* 0 1 2 3 4 5 6 7 8 9 */
1264 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1265 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1266 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1267 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1268 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1269 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1270 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1271 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1272 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1273 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1274};
1275
1276/* Calculates a relative dB value from a ratio of linear
1277 * (i.e. not dB) signal levels.
1278 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1279int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1280{
221c80cf
AB
1281 /* 1000:1 or higher just report as 60 dB */
1282 if (sig_ratio >= 1000)
b481de9c
ZY
1283 return 60;
1284
221c80cf 1285 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1286 * add 20 dB to make up for divide by 10 */
221c80cf 1287 if (sig_ratio >= 100)
3ac7f146 1288 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1289
1290 /* We shouldn't see this */
1291 if (sig_ratio < 1)
1292 return 0;
1293
1294 /* Use table for ratios 1:1 - 99:1 */
1295 return (int)ratio2dB[sig_ratio];
1296}
1297
b481de9c 1298/**
9fbab516 1299 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1300 *
1301 * Uses the priv->rx_handlers callback function array to invoke
1302 * the appropriate handlers, including command responses,
1303 * frame-received notifications, and other notifications.
1304 */
4a8a4322 1305static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1306{
6100b588 1307 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1308 struct iwl_rx_packet *pkt;
cc2f362c 1309 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1310 u32 r, i;
1311 int reclaim;
1312 unsigned long flags;
5c0eef96 1313 u8 fill_rx = 0;
d68ab680 1314 u32 count = 8;
d14d4440 1315 int total_empty = 0;
b481de9c 1316
6440adb5
BC
1317 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1318 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1319 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1320 i = rxq->read;
1321
d14d4440 1322 /* calculate total frames need to be restock after handling RX */
7300515d 1323 total_empty = r - rxq->write_actual;
d14d4440
AK
1324 if (total_empty < 0)
1325 total_empty += RX_QUEUE_SIZE;
1326
1327 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1328 fill_rx = 1;
b481de9c
ZY
1329 /* Rx interrupt, but nothing sent from uCode */
1330 if (i == r)
af472a95 1331 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1332
1333 while (i != r) {
1334 rxb = rxq->queue[i];
1335
9fbab516 1336 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1337 * then a bug has been introduced in the queue refilling
1338 * routines -- catch it here */
1339 BUG_ON(rxb == NULL);
1340
1341 rxq->queue[i] = NULL;
1342
2f301227
ZY
1343 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1344 PAGE_SIZE << priv->hw_params.rx_page_order,
1345 PCI_DMA_FROMDEVICE);
1346 pkt = rxb_addr(rxb);
b481de9c 1347
be1a71a1
JB
1348 trace_iwlwifi_dev_rx(priv, pkt,
1349 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
1350
b481de9c
ZY
1351 /* Reclaim a command buffer only if this packet is a response
1352 * to a (driver-originated) command.
1353 * If the packet (e.g. Rx frame) originated from uCode,
1354 * there is no command buffer to reclaim.
1355 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1356 * but apparently a few don't get set; catch them here. */
1357 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1358 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1359 (pkt->hdr.cmd != REPLY_TX);
1360
1361 /* Based on type of command response or notification,
1362 * handle those that need handling via function in
bb8c093b 1363 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1364 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1365 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c 1366 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
86ddbf62 1367 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1368 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
1369 } else {
1370 /* No handling needed */
2f301227
ZY
1371 IWL_DEBUG_RX(priv,
1372 "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1373 r, i, get_cmd_string(pkt->hdr.cmd),
1374 pkt->hdr.cmd);
1375 }
1376
29b1b268
ZY
1377 /*
1378 * XXX: After here, we should always check rxb->page
1379 * against NULL before touching it or its virtual
1380 * memory (pkt). Because some rx_handler might have
1381 * already taken or freed the pages.
1382 */
1383
b481de9c 1384 if (reclaim) {
2f301227
ZY
1385 /* Invoke any callbacks, transfer the buffer to caller,
1386 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1387 * as we reclaim the driver command queue */
29b1b268 1388 if (rxb->page)
732587ab 1389 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1390 else
39aadf8c 1391 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1392 }
1393
7300515d
ZY
1394 /* Reuse the page if possible. For notification packets and
1395 * SKBs that fail to Rx correctly, add them back into the
1396 * rx_free list for reuse later. */
1397 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1398 if (rxb->page != NULL) {
7300515d
ZY
1399 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1400 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1401 PCI_DMA_FROMDEVICE);
1402 list_add_tail(&rxb->list, &rxq->rx_free);
1403 rxq->free_count++;
1404 } else
1405 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1406
b481de9c 1407 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1408
b481de9c 1409 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1410 /* If there are a lot of unused frames,
1411 * restock the Rx queue so ucode won't assert. */
1412 if (fill_rx) {
1413 count++;
1414 if (count >= 8) {
7300515d 1415 rxq->read = i;
d14d4440 1416 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1417 count = 0;
1418 }
1419 }
b481de9c
ZY
1420 }
1421
1422 /* Backtrack one entry */
7300515d 1423 rxq->read = i;
d14d4440
AK
1424 if (fill_rx)
1425 iwl3945_rx_replenish_now(priv);
1426 else
1427 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1428}
1429
0359facc 1430/* call this function to flush any scheduled tasklet */
4a8a4322 1431static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1432{
a96a27f9 1433 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1434 synchronize_irq(priv->pci_dev->irq);
1435 tasklet_kill(&priv->irq_tasklet);
1436}
1437
b481de9c
ZY
1438static const char *desc_lookup(int i)
1439{
1440 switch (i) {
1441 case 1:
1442 return "FAIL";
1443 case 2:
1444 return "BAD_PARAM";
1445 case 3:
1446 return "BAD_CHECKSUM";
1447 case 4:
1448 return "NMI_INTERRUPT";
1449 case 5:
1450 return "SYSASSERT";
1451 case 6:
1452 return "FATAL_ERROR";
1453 }
1454
1455 return "UNKNOWN";
1456}
1457
1458#define ERROR_START_OFFSET (1 * sizeof(u32))
1459#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1460
b7a79404 1461void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1462{
1463 u32 i;
1464 u32 desc, time, count, base, data1;
1465 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1466
1467 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1468
bb8c093b 1469 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1470 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1471 return;
1472 }
1473
b481de9c 1474
5d49f498 1475 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1476
1477 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1478 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1479 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1480 priv->status, count);
b481de9c
ZY
1481 }
1482
15b1687c 1483 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1484 "ilink1 nmiPC Line\n");
1485 for (i = ERROR_START_OFFSET;
1486 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1487 i += ERROR_ELEM_SIZE) {
5d49f498 1488 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1489 time =
5d49f498 1490 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1491 blink1 =
5d49f498 1492 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1493 blink2 =
5d49f498 1494 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1495 ilink1 =
5d49f498 1496 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1497 ilink2 =
5d49f498 1498 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1499 data1 =
5d49f498 1500 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1501
15b1687c
WT
1502 IWL_ERR(priv,
1503 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1504 desc_lookup(desc), desc, time, blink1, blink2,
1505 ilink1, ilink2, data1);
be1a71a1
JB
1506 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
1507 0, blink1, blink2, ilink1, ilink2);
b481de9c 1508 }
b481de9c
ZY
1509}
1510
f58177b9 1511#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1512
1513/**
bb8c093b 1514 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1515 *
b481de9c 1516 */
b03d7d0f
WYG
1517static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1518 u32 num_events, u32 mode,
1519 int pos, char **buf, size_t bufsz)
b481de9c
ZY
1520{
1521 u32 i;
1522 u32 base; /* SRAM byte address of event log header */
1523 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1524 u32 ptr; /* SRAM byte address of log data */
1525 u32 ev, time, data; /* event log data */
e5854471 1526 unsigned long reg_flags;
b481de9c
ZY
1527
1528 if (num_events == 0)
b03d7d0f 1529 return pos;
b481de9c
ZY
1530
1531 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1532
1533 if (mode == 0)
1534 event_size = 2 * sizeof(u32);
1535 else
1536 event_size = 3 * sizeof(u32);
1537
1538 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1539
e5854471
BC
1540 /* Make sure device is powered up for SRAM reads */
1541 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1542 iwl_grab_nic_access(priv);
1543
1544 /* Set starting address; reads will auto-increment */
1545 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1546 rmb();
1547
b481de9c
ZY
1548 /* "time" is actually "data" for mode 0 (no timestamp).
1549 * place event id # at far right for easier visual parsing. */
1550 for (i = 0; i < num_events; i++) {
e5854471
BC
1551 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1552 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
15b1687c
WT
1553 if (mode == 0) {
1554 /* data, ev */
b03d7d0f
WYG
1555 if (bufsz) {
1556 pos += scnprintf(*buf + pos, bufsz - pos,
1557 "0x%08x:%04u\n",
1558 time, ev);
1559 } else {
1560 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1561 trace_iwlwifi_dev_ucode_event(priv, 0,
1562 time, ev);
1563 }
15b1687c 1564 } else {
e5854471 1565 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1566 if (bufsz) {
1567 pos += scnprintf(*buf + pos, bufsz - pos,
1568 "%010u:0x%08x:%04u\n",
1569 time, data, ev);
1570 } else {
1571 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
1572 time, data, ev);
1573 trace_iwlwifi_dev_ucode_event(priv, time,
1574 data, ev);
1575 }
b481de9c
ZY
1576 }
1577 }
e5854471
BC
1578
1579 /* Allow device to power down */
1580 iwl_release_nic_access(priv);
1581 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1582 return pos;
b481de9c
ZY
1583}
1584
c341ddb2
WYG
1585/**
1586 * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
1587 */
b03d7d0f 1588static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
c341ddb2 1589 u32 num_wraps, u32 next_entry,
b03d7d0f
WYG
1590 u32 size, u32 mode,
1591 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1592{
1593 /*
1594 * display the newest DEFAULT_LOG_ENTRIES entries
1595 * i.e the entries just before the next ont that uCode would fill.
1596 */
1597 if (num_wraps) {
1598 if (next_entry < size) {
b03d7d0f
WYG
1599 pos = iwl3945_print_event_log(priv,
1600 capacity - (size - next_entry),
1601 size - next_entry, mode,
1602 pos, buf, bufsz);
1603 pos = iwl3945_print_event_log(priv, 0,
1604 next_entry, mode,
1605 pos, buf, bufsz);
c341ddb2 1606 } else
b03d7d0f
WYG
1607 pos = iwl3945_print_event_log(priv, next_entry - size,
1608 size, mode,
1609 pos, buf, bufsz);
c341ddb2
WYG
1610 } else {
1611 if (next_entry < size)
b03d7d0f
WYG
1612 pos = iwl3945_print_event_log(priv, 0,
1613 next_entry, mode,
1614 pos, buf, bufsz);
c341ddb2 1615 else
b03d7d0f
WYG
1616 pos = iwl3945_print_event_log(priv, next_entry - size,
1617 size, mode,
1618 pos, buf, bufsz);
c341ddb2 1619 }
b03d7d0f 1620 return pos;
c341ddb2
WYG
1621}
1622
84c40692
BC
1623/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1624#define IWL3945_MAX_EVENT_LOG_SIZE (512)
1625
c341ddb2
WYG
1626#define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
1627
b03d7d0f
WYG
1628int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1629 char **buf, bool display)
b481de9c 1630{
b481de9c
ZY
1631 u32 base; /* SRAM byte address of event log header */
1632 u32 capacity; /* event log capacity in # entries */
1633 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1634 u32 num_wraps; /* # times uCode wrapped to top of log */
1635 u32 next_entry; /* index of next entry to be written by uCode */
1636 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1637 int pos = 0;
1638 size_t bufsz = 0;
b481de9c
ZY
1639
1640 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1641 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1642 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
937c397e 1643 return -EINVAL;
b481de9c
ZY
1644 }
1645
b481de9c 1646 /* event log header */
5d49f498
AK
1647 capacity = iwl_read_targ_mem(priv, base);
1648 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1649 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1650 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c 1651
84c40692
BC
1652 if (capacity > IWL3945_MAX_EVENT_LOG_SIZE) {
1653 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1654 capacity, IWL3945_MAX_EVENT_LOG_SIZE);
1655 capacity = IWL3945_MAX_EVENT_LOG_SIZE;
1656 }
1657
1658 if (next_entry > IWL3945_MAX_EVENT_LOG_SIZE) {
1659 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1660 next_entry, IWL3945_MAX_EVENT_LOG_SIZE);
1661 next_entry = IWL3945_MAX_EVENT_LOG_SIZE;
1662 }
1663
b481de9c
ZY
1664 size = num_wraps ? capacity : next_entry;
1665
1666 /* bail out if nothing in log */
1667 if (size == 0) {
15b1687c 1668 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1669 return pos;
b481de9c
ZY
1670 }
1671
c341ddb2 1672#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1673 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1674 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1675 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1676#else
1677 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1678 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1679#endif
1680
1681 IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
1682 size);
b481de9c 1683
c341ddb2 1684#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
1685 if (display) {
1686 if (full_log)
1687 bufsz = capacity * 48;
1688 else
1689 bufsz = size * 48;
1690 *buf = kmalloc(bufsz, GFP_KERNEL);
1691 if (!*buf)
937c397e 1692 return -ENOMEM;
b03d7d0f 1693 }
c341ddb2
WYG
1694 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1695 /* if uCode has wrapped back to top of log,
1696 * start at the oldest entry,
1697 * i.e the next one that uCode would fill.
1698 */
1699 if (num_wraps)
b03d7d0f
WYG
1700 pos = iwl3945_print_event_log(priv, next_entry,
1701 capacity - next_entry, mode,
1702 pos, buf, bufsz);
c341ddb2
WYG
1703
1704 /* (then/else) start at top of log */
b03d7d0f
WYG
1705 pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
1706 pos, buf, bufsz);
c341ddb2 1707 } else
b03d7d0f
WYG
1708 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1709 next_entry, size, mode,
1710 pos, buf, bufsz);
b7a79404 1711#else
b03d7d0f
WYG
1712 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1713 next_entry, size, mode,
1714 pos, buf, bufsz);
c341ddb2 1715#endif
b03d7d0f 1716 return pos;
b7a79404
RC
1717}
1718
4a8a4322 1719static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1720{
1721 u32 inta, handled = 0;
1722 u32 inta_fh;
1723 unsigned long flags;
d08853a3 1724#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1725 u32 inta_mask;
1726#endif
1727
1728 spin_lock_irqsave(&priv->lock, flags);
1729
1730 /* Ack/clear/reset pending uCode interrupts.
1731 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1732 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1733 inta = iwl_read32(priv, CSR_INT);
1734 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1735
1736 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1737 * Any new interrupts that happen after this, either while we're
1738 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1739 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1740 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1741
d08853a3 1742#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1743 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1744 /* just for debug */
5d49f498 1745 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1746 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1747 inta, inta_mask, inta_fh);
1748 }
1749#endif
1750
2f301227
ZY
1751 spin_unlock_irqrestore(&priv->lock, flags);
1752
b481de9c
ZY
1753 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1754 * atomic, make sure that inta covers all the interrupts that
1755 * we've discovered, even if FH interrupt came in just after
1756 * reading CSR_INT. */
6f83eaa1 1757 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1758 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1759 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1760 inta |= CSR_INT_BIT_FH_TX;
1761
1762 /* Now service all interrupt bits discovered above. */
1763 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1764 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1765
1766 /* Tell the device to stop sending interrupts */
ed3b932e 1767 iwl_disable_interrupts(priv);
b481de9c 1768
86ddbf62 1769 priv->isr_stats.hw++;
8ccde88a 1770 iwl_irq_handle_error(priv);
b481de9c
ZY
1771
1772 handled |= CSR_INT_BIT_HW_ERR;
1773
b481de9c
ZY
1774 return;
1775 }
1776
d08853a3 1777#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1778 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1779 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1780 if (inta & CSR_INT_BIT_SCD) {
e1623446 1781 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1782 "the frame/frames.\n");
86ddbf62
AK
1783 priv->isr_stats.sch++;
1784 }
b481de9c
ZY
1785
1786 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1787 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1788 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1789 priv->isr_stats.alive++;
1790 }
b481de9c
ZY
1791 }
1792#endif
1793 /* Safely ignore these bits for debug checks below */
25c03d8e 1794 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1795
b481de9c
ZY
1796 /* Error detected by uCode */
1797 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1798 IWL_ERR(priv, "Microcode SW error detected. "
1799 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1800 priv->isr_stats.sw++;
1801 priv->isr_stats.sw_err = inta;
8ccde88a 1802 iwl_irq_handle_error(priv);
b481de9c
ZY
1803 handled |= CSR_INT_BIT_SW_ERR;
1804 }
1805
1806 /* uCode wakes up after power-down sleep */
1807 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1808 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1809 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1810 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1811 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1812 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1813 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1814 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1815 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1816
86ddbf62 1817 priv->isr_stats.wakeup++;
b481de9c
ZY
1818 handled |= CSR_INT_BIT_WAKEUP;
1819 }
1820
1821 /* All uCode command responses, including Tx command responses,
1822 * Rx "responses" (frame-received notification), and other
1823 * notifications from uCode come through here*/
1824 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1825 iwl3945_rx_handle(priv);
86ddbf62 1826 priv->isr_stats.rx++;
b481de9c
ZY
1827 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1828 }
1829
1830 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1831 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1832 priv->isr_stats.tx++;
b481de9c 1833
5d49f498 1834 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1835 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1836 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1837 handled |= CSR_INT_BIT_FH_TX;
1838 }
1839
86ddbf62 1840 if (inta & ~handled) {
15b1687c 1841 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1842 priv->isr_stats.unhandled++;
1843 }
b481de9c 1844
40cefda9 1845 if (inta & ~priv->inta_mask) {
39aadf8c 1846 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1847 inta & ~priv->inta_mask);
39aadf8c 1848 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1849 }
1850
1851 /* Re-enable all interrupts */
0359facc
MA
1852 /* only Re-enable if disabled by irq */
1853 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1854 iwl_enable_interrupts(priv);
b481de9c 1855
d08853a3 1856#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1857 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1858 inta = iwl_read32(priv, CSR_INT);
1859 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1860 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1861 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1862 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1863 }
1864#endif
b481de9c
ZY
1865}
1866
4a8a4322 1867static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1868 enum ieee80211_band band,
f9340520 1869 u8 is_active, u8 n_probes,
bb8c093b 1870 struct iwl3945_scan_channel *scan_ch)
b481de9c 1871{
4e05c234 1872 struct ieee80211_channel *chan;
8318d78a 1873 const struct ieee80211_supported_band *sband;
d20b3c65 1874 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1875 u16 passive_dwell = 0;
1876 u16 active_dwell = 0;
1877 int added, i;
1878
cbba18c6 1879 sband = iwl_get_hw_mode(priv, band);
8318d78a 1880 if (!sband)
b481de9c
ZY
1881 return 0;
1882
77fecfb8
SO
1883 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1884 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1885
8f4807a1
AK
1886 if (passive_dwell <= active_dwell)
1887 passive_dwell = active_dwell + 1;
1888
4e05c234
JB
1889 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1890 chan = priv->scan_request->channels[i];
1891
1892 if (chan->band != band)
182e2e66
JB
1893 continue;
1894
4e05c234 1895 scan_ch->channel = chan->hw_value;
b481de9c 1896
e6148917 1897 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1898 if (!is_channel_valid(ch_info)) {
e1623446 1899 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1900 scan_ch->channel);
1901 continue;
1902 }
1903
011a0330
AK
1904 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1905 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1906 /* If passive , set up for auto-switch
1907 * and use long active_dwell time.
1908 */
b481de9c 1909 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1910 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1911 scan_ch->type = 0; /* passive */
011a0330
AK
1912 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1913 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1914 } else {
b481de9c 1915 scan_ch->type = 1; /* active */
011a0330 1916 }
b481de9c 1917
011a0330
AK
1918 /* Set direct probe bits. These may be used both for active
1919 * scan channels (probes gets sent right away),
1920 * or for passive channels (probes get se sent only after
1921 * hearing clear Rx packet).*/
1922 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1923 if (n_probes)
0d21044e 1924 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1925 } else {
1926 /* uCode v1 does not allow setting direct probe bits on
1927 * passive channel. */
1928 if ((scan_ch->type & 1) && n_probes)
0d21044e 1929 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1930 }
b481de9c 1931
9fbab516 1932 /* Set txpower levels to defaults */
b481de9c
ZY
1933 scan_ch->tpc.dsp_atten = 110;
1934 /* scan_pwr_info->tpc.dsp_atten; */
1935
1936 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1937 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1938 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1939 else {
1940 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1941 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1942 * power level:
8a1b0245 1943 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1944 */
1945 }
1946
e1623446 1947 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1948 scan_ch->channel,
1949 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1950 (scan_ch->type & 1) ?
1951 active_dwell : passive_dwell);
1952
1953 scan_ch++;
1954 added++;
1955 }
1956
e1623446 1957 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1958 return added;
1959}
1960
4a8a4322 1961static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1962 struct ieee80211_rate *rates)
1963{
1964 int i;
1965
1966 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1967 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1968 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1969 rates[i].hw_value_short = i;
1970 rates[i].flags = 0;
d9829a67 1971 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1972 /*
8318d78a 1973 * If CCK != 1M then set short preamble rate flag.
b481de9c 1974 */
bb8c093b 1975 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1976 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1977 }
b481de9c
ZY
1978 }
1979}
1980
b481de9c
ZY
1981/******************************************************************************
1982 *
1983 * uCode download functions
1984 *
1985 ******************************************************************************/
1986
4a8a4322 1987static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1988{
98c92211
TW
1989 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1990 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1991 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1992 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1993 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1994 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1995}
1996
1997/**
bb8c093b 1998 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1999 * looking at all data.
2000 */
4a8a4322 2001static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2002{
2003 u32 val;
2004 u32 save_len = len;
2005 int rc = 0;
2006 u32 errcnt;
2007
e1623446 2008 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2009
5d49f498 2010 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2011 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
2012
2013 errcnt = 0;
2014 for (; len > 0; len -= sizeof(u32), image++) {
2015 /* read data comes through single port, auto-incr addr */
2016 /* NOTE: Use the debugless read so we don't flood kernel log
2017 * if IWL_DL_IO is set */
5d49f498 2018 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 2019 if (val != le32_to_cpu(*image)) {
15b1687c 2020 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2021 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2022 save_len - len, val, le32_to_cpu(*image));
2023 rc = -EIO;
2024 errcnt++;
2025 if (errcnt >= 20)
2026 break;
2027 }
2028 }
2029
b481de9c
ZY
2030
2031 if (!errcnt)
e1623446
TW
2032 IWL_DEBUG_INFO(priv,
2033 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2034
2035 return rc;
2036}
2037
2038
2039/**
bb8c093b 2040 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2041 * using sample data 100 bytes apart. If these sample points are good,
2042 * it's a pretty good bet that everything between them is good, too.
2043 */
4a8a4322 2044static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2045{
2046 u32 val;
2047 int rc = 0;
2048 u32 errcnt = 0;
2049 u32 i;
2050
e1623446 2051 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2052
b481de9c
ZY
2053 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2054 /* read data comes through single port, auto-incr addr */
2055 /* NOTE: Use the debugless read so we don't flood kernel log
2056 * if IWL_DL_IO is set */
5d49f498 2057 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2058 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2059 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2060 if (val != le32_to_cpu(*image)) {
2061#if 0 /* Enable this if you want to see details */
15b1687c 2062 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2063 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2064 i, val, *image);
2065#endif
2066 rc = -EIO;
2067 errcnt++;
2068 if (errcnt >= 3)
2069 break;
2070 }
2071 }
2072
b481de9c
ZY
2073 return rc;
2074}
2075
2076
2077/**
bb8c093b 2078 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2079 * and verify its contents
2080 */
4a8a4322 2081static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2082{
2083 __le32 *image;
2084 u32 len;
2085 int rc = 0;
2086
2087 /* Try bootstrap */
2088 image = (__le32 *)priv->ucode_boot.v_addr;
2089 len = priv->ucode_boot.len;
bb8c093b 2090 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2091 if (rc == 0) {
e1623446 2092 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2093 return 0;
2094 }
2095
2096 /* Try initialize */
2097 image = (__le32 *)priv->ucode_init.v_addr;
2098 len = priv->ucode_init.len;
bb8c093b 2099 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2100 if (rc == 0) {
e1623446 2101 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2102 return 0;
2103 }
2104
2105 /* Try runtime/protocol */
2106 image = (__le32 *)priv->ucode_code.v_addr;
2107 len = priv->ucode_code.len;
bb8c093b 2108 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2109 if (rc == 0) {
e1623446 2110 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2111 return 0;
2112 }
2113
15b1687c 2114 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2115
9fbab516
BC
2116 /* Since nothing seems to match, show first several data entries in
2117 * instruction SRAM, so maybe visual inspection will give a clue.
2118 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2119 image = (__le32 *)priv->ucode_boot.v_addr;
2120 len = priv->ucode_boot.len;
bb8c093b 2121 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2122
2123 return rc;
2124}
2125
4a8a4322 2126static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2127{
2128 /* Remove all resets to allow NIC to operate */
5d49f498 2129 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2130}
2131
2132/**
bb8c093b 2133 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2134 *
2135 * Copy into buffers for card to fetch via bus-mastering
2136 */
4a8a4322 2137static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2138{
cc0f555d 2139 const struct iwl_ucode_header *ucode;
a0987a8d 2140 int ret = -EINVAL, index;
b481de9c
ZY
2141 const struct firmware *ucode_raw;
2142 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2143 const char *name_pre = priv->cfg->fw_name_pre;
2144 const unsigned int api_max = priv->cfg->ucode_api_max;
2145 const unsigned int api_min = priv->cfg->ucode_api_min;
2146 char buf[25];
b481de9c
ZY
2147 u8 *src;
2148 size_t len;
a0987a8d 2149 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2150
2151 /* Ask kernel firmware_class module to get the boot firmware off disk.
2152 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2153 for (index = api_max; index >= api_min; index--) {
2154 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2155 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2156 if (ret < 0) {
15b1687c 2157 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2158 buf, ret);
2159 if (ret == -ENOENT)
2160 continue;
2161 else
2162 goto error;
2163 } else {
2164 if (index < api_max)
15b1687c
WT
2165 IWL_ERR(priv, "Loaded firmware %s, "
2166 "which is deprecated. "
2167 " Please use API v%u instead.\n",
a0987a8d 2168 buf, api_max);
e1623446
TW
2169 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2170 "(%zd bytes) from disk\n",
a0987a8d
RC
2171 buf, ucode_raw->size);
2172 break;
2173 }
b481de9c
ZY
2174 }
2175
a0987a8d
RC
2176 if (ret < 0)
2177 goto error;
b481de9c
ZY
2178
2179 /* Make sure that we got at least our header! */
cc0f555d 2180 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2181 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2182 ret = -EINVAL;
b481de9c
ZY
2183 goto err_release;
2184 }
2185
2186 /* Data from ucode file: header followed by uCode images */
cc0f555d 2187 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2188
c02b3acd 2189 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2190 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2191 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2192 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2193 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2194 init_data_size =
2195 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2196 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2197 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2198
a0987a8d
RC
2199 /* api_ver should match the api version forming part of the
2200 * firmware filename ... but we don't check for that and only rely
877d0310 2201 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2202
2203 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2204 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2205 "Driver supports v%u, firmware is v%u.\n",
2206 api_max, api_ver);
2207 priv->ucode_ver = 0;
2208 ret = -EINVAL;
2209 goto err_release;
2210 }
2211 if (api_ver != api_max)
15b1687c 2212 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2213 "got %u. New firmware can be obtained "
2214 "from http://www.intellinuxwireless.org.\n",
2215 api_max, api_ver);
2216
978785a3
TW
2217 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2218 IWL_UCODE_MAJOR(priv->ucode_ver),
2219 IWL_UCODE_MINOR(priv->ucode_ver),
2220 IWL_UCODE_API(priv->ucode_ver),
2221 IWL_UCODE_SERIAL(priv->ucode_ver));
2222
5ebeb5a6
RC
2223 snprintf(priv->hw->wiphy->fw_version,
2224 sizeof(priv->hw->wiphy->fw_version),
2225 "%u.%u.%u.%u",
2226 IWL_UCODE_MAJOR(priv->ucode_ver),
2227 IWL_UCODE_MINOR(priv->ucode_ver),
2228 IWL_UCODE_API(priv->ucode_ver),
2229 IWL_UCODE_SERIAL(priv->ucode_ver));
2230
e1623446 2231 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2232 priv->ucode_ver);
e1623446
TW
2233 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2234 inst_size);
2235 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2236 data_size);
2237 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2238 init_size);
2239 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2240 init_data_size);
2241 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2242 boot_size);
b481de9c 2243
a0987a8d 2244
b481de9c 2245 /* Verify size of file vs. image size info in file's header */
cc0f555d 2246 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2247 inst_size + data_size + init_size +
2248 init_data_size + boot_size) {
2249
cc0f555d
JS
2250 IWL_DEBUG_INFO(priv,
2251 "uCode file size %zd does not match expected size\n",
2252 ucode_raw->size);
90e759d1 2253 ret = -EINVAL;
b481de9c
ZY
2254 goto err_release;
2255 }
2256
2257 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2258 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2259 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2260 inst_size);
2261 ret = -EINVAL;
b481de9c
ZY
2262 goto err_release;
2263 }
2264
250bdd21 2265 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2266 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2267 data_size);
2268 ret = -EINVAL;
b481de9c
ZY
2269 goto err_release;
2270 }
250bdd21 2271 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2272 IWL_DEBUG_INFO(priv,
2273 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2274 init_size);
2275 ret = -EINVAL;
b481de9c
ZY
2276 goto err_release;
2277 }
250bdd21 2278 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2279 IWL_DEBUG_INFO(priv,
2280 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2281 init_data_size);
2282 ret = -EINVAL;
b481de9c
ZY
2283 goto err_release;
2284 }
250bdd21 2285 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2286 IWL_DEBUG_INFO(priv,
2287 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2288 boot_size);
2289 ret = -EINVAL;
b481de9c
ZY
2290 goto err_release;
2291 }
2292
2293 /* Allocate ucode buffers for card's bus-master loading ... */
2294
2295 /* Runtime instructions and 2 copies of data:
2296 * 1) unmodified from disk
2297 * 2) backup cache for save/restore during power-downs */
2298 priv->ucode_code.len = inst_size;
98c92211 2299 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2300
2301 priv->ucode_data.len = data_size;
98c92211 2302 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2303
2304 priv->ucode_data_backup.len = data_size;
98c92211 2305 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2306
90e759d1
TW
2307 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2308 !priv->ucode_data_backup.v_addr)
2309 goto err_pci_alloc;
b481de9c
ZY
2310
2311 /* Initialization instructions and data */
90e759d1
TW
2312 if (init_size && init_data_size) {
2313 priv->ucode_init.len = init_size;
98c92211 2314 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2315
2316 priv->ucode_init_data.len = init_data_size;
98c92211 2317 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2318
2319 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2320 goto err_pci_alloc;
2321 }
b481de9c
ZY
2322
2323 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2324 if (boot_size) {
2325 priv->ucode_boot.len = boot_size;
98c92211 2326 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2327
90e759d1
TW
2328 if (!priv->ucode_boot.v_addr)
2329 goto err_pci_alloc;
2330 }
b481de9c
ZY
2331
2332 /* Copy images into buffers for card's bus-master reads ... */
2333
2334 /* Runtime instructions (first block of data in file) */
cc0f555d 2335 len = inst_size;
e1623446
TW
2336 IWL_DEBUG_INFO(priv,
2337 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2338 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2339 src += len;
2340
e1623446 2341 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2342 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2343
2344 /* Runtime data (2nd block)
bb8c093b 2345 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2346 len = data_size;
e1623446
TW
2347 IWL_DEBUG_INFO(priv,
2348 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2349 memcpy(priv->ucode_data.v_addr, src, len);
2350 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2351 src += len;
b481de9c
ZY
2352
2353 /* Initialization instructions (3rd block) */
2354 if (init_size) {
cc0f555d 2355 len = init_size;
e1623446
TW
2356 IWL_DEBUG_INFO(priv,
2357 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2358 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2359 src += len;
b481de9c
ZY
2360 }
2361
2362 /* Initialization data (4th block) */
2363 if (init_data_size) {
cc0f555d 2364 len = init_data_size;
e1623446
TW
2365 IWL_DEBUG_INFO(priv,
2366 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2367 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2368 src += len;
b481de9c
ZY
2369 }
2370
2371 /* Bootstrap instructions (5th block) */
cc0f555d 2372 len = boot_size;
e1623446
TW
2373 IWL_DEBUG_INFO(priv,
2374 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2375 memcpy(priv->ucode_boot.v_addr, src, len);
2376
2377 /* We have our copies now, allow OS release its copies */
2378 release_firmware(ucode_raw);
2379 return 0;
2380
2381 err_pci_alloc:
15b1687c 2382 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2383 ret = -ENOMEM;
bb8c093b 2384 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2385
2386 err_release:
2387 release_firmware(ucode_raw);
2388
2389 error:
90e759d1 2390 return ret;
b481de9c
ZY
2391}
2392
2393
2394/**
bb8c093b 2395 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2396 *
2397 * Tell initialization uCode where to find runtime uCode.
2398 *
2399 * BSM registers initially contain pointers to initialization uCode.
2400 * We need to replace them to load runtime uCode inst and data,
2401 * and to save runtime data when powering down.
2402 */
4a8a4322 2403static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2404{
2405 dma_addr_t pinst;
2406 dma_addr_t pdata;
b481de9c
ZY
2407
2408 /* bits 31:0 for 3945 */
2409 pinst = priv->ucode_code.p_addr;
2410 pdata = priv->ucode_data_backup.p_addr;
2411
b481de9c 2412 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2413 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2414 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2415 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2416 priv->ucode_data.len);
2417
a96a27f9 2418 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2419 * that all new ptr/size info is in place */
5d49f498 2420 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2421 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2422
e1623446 2423 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2424
a8b50a0a 2425 return 0;
b481de9c
ZY
2426}
2427
2428/**
bb8c093b 2429 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2430 *
2431 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2432 *
b481de9c 2433 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2434 */
4a8a4322 2435static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2436{
2437 /* Check alive response for "valid" sign from uCode */
2438 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2439 /* We had an error bringing up the hardware, so take it
2440 * all the way back down so we can try again */
e1623446 2441 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2442 goto restart;
2443 }
2444
2445 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2446 * This is a paranoid check, because we would not have gotten the
2447 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2448 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2449 /* Runtime instruction load was bad;
2450 * take it all the way back down so we can try again */
e1623446 2451 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2452 goto restart;
2453 }
2454
2455 /* Send pointers to protocol/runtime uCode image ... init code will
2456 * load and launch runtime uCode, which will send us another "Alive"
2457 * notification. */
e1623446 2458 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2459 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2460 /* Runtime instruction load won't happen;
2461 * take it all the way back down so we can try again */
e1623446 2462 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2463 goto restart;
2464 }
2465 return;
2466
2467 restart:
2468 queue_work(priv->workqueue, &priv->restart);
2469}
2470
b481de9c 2471/**
bb8c093b 2472 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2473 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2474 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2475 */
4a8a4322 2476static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2477{
b481de9c
ZY
2478 int thermal_spin = 0;
2479 u32 rfkill;
2480
e1623446 2481 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2482
2483 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2484 /* We had an error bringing up the hardware, so take it
2485 * all the way back down so we can try again */
e1623446 2486 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2487 goto restart;
2488 }
2489
2490 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2491 * This is a paranoid check, because we would not have gotten the
2492 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2493 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2494 /* Runtime instruction load was bad;
2495 * take it all the way back down so we can try again */
e1623446 2496 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2497 goto restart;
2498 }
2499
c587de0b 2500 iwl_clear_stations_table(priv);
b481de9c 2501
5d49f498 2502 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2503 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2504
2505 if (rfkill & 0x1) {
2506 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2507 /* if RFKILL is not on, then wait for thermal
b481de9c 2508 * sensor in adapter to kick in */
bb8c093b 2509 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2510 thermal_spin++;
2511 udelay(10);
2512 }
2513
2514 if (thermal_spin)
e1623446 2515 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2516 thermal_spin * 10);
2517 } else
2518 set_bit(STATUS_RF_KILL_HW, &priv->status);
2519
9fbab516 2520 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2521 set_bit(STATUS_ALIVE, &priv->status);
2522
775a6e27 2523 if (iwl_is_rfkill(priv))
b481de9c
ZY
2524 return;
2525
36d6825b 2526 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2527
2528 priv->active_rate = priv->rates_mask;
2529 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2530
4d6ccbf5 2531 iwl_power_update_mode(priv, true);
b481de9c 2532
8ccde88a 2533 if (iwl_is_associated(priv)) {
bb8c093b 2534 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2535 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2536
8a9b9926 2537 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2538 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2539 } else {
2540 /* Initialize our rx_config data */
8ccde88a 2541 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2542 }
2543
9fbab516 2544 /* Configure Bluetooth device coexistence support */
17f841cd 2545 iwl_send_bt_config(priv);
b481de9c
ZY
2546
2547 /* Configure the adapter for unassociated operation */
e0158e61 2548 iwlcore_commit_rxon(priv);
b481de9c 2549
b481de9c
ZY
2550 iwl3945_reg_txpower_periodic(priv);
2551
e932a609 2552 iwl_leds_init(priv);
fe00b5a5 2553
e1623446 2554 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2555 set_bit(STATUS_READY, &priv->status);
5a66926a 2556 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2557
9bdf5eca
MA
2558 /* reassociate for ADHOC mode */
2559 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2560 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2561 priv->vif);
2562 if (beacon)
9944b938 2563 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2564 }
2565
f45c2714 2566 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2567 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2568
b481de9c
ZY
2569 return;
2570
2571 restart:
2572 queue_work(priv->workqueue, &priv->restart);
2573}
2574
4a8a4322 2575static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2576
4a8a4322 2577static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2578{
2579 unsigned long flags;
2580 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2581 struct ieee80211_conf *conf = NULL;
2582
e1623446 2583 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2584
2585 conf = ieee80211_get_hw_conf(priv->hw);
2586
2587 if (!exit_pending)
2588 set_bit(STATUS_EXIT_PENDING, &priv->status);
2589
c587de0b 2590 iwl_clear_stations_table(priv);
b481de9c
ZY
2591
2592 /* Unblock any waiting calls */
2593 wake_up_interruptible_all(&priv->wait_command_queue);
2594
b481de9c
ZY
2595 /* Wipe out the EXIT_PENDING status bit if we are not actually
2596 * exiting the module */
2597 if (!exit_pending)
2598 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2599
2600 /* stop and reset the on-board processor */
5d49f498 2601 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2602
2603 /* tell the device to stop sending interrupts */
0359facc 2604 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2605 iwl_disable_interrupts(priv);
0359facc
MA
2606 spin_unlock_irqrestore(&priv->lock, flags);
2607 iwl_synchronize_irq(priv);
b481de9c
ZY
2608
2609 if (priv->mac80211_registered)
2610 ieee80211_stop_queues(priv->hw);
2611
bb8c093b 2612 /* If we have not previously called iwl3945_init() then
6da3a13e 2613 * clear all bits but the RF Kill bits and return */
775a6e27 2614 if (!iwl_is_init(priv)) {
b481de9c
ZY
2615 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2616 STATUS_RF_KILL_HW |
9788864e
RC
2617 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2618 STATUS_GEO_CONFIGURED |
ebef2008
AK
2619 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2620 STATUS_EXIT_PENDING;
b481de9c
ZY
2621 goto exit;
2622 }
2623
6da3a13e 2624 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2625 * bit and continue taking the NIC down. */
b481de9c
ZY
2626 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2627 STATUS_RF_KILL_HW |
9788864e
RC
2628 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2629 STATUS_GEO_CONFIGURED |
b481de9c 2630 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2631 STATUS_FW_ERROR |
2632 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2633 STATUS_EXIT_PENDING;
b481de9c 2634
bb8c093b
CH
2635 iwl3945_hw_txq_ctx_stop(priv);
2636 iwl3945_hw_rxq_stop(priv);
b481de9c 2637
309e731a
BC
2638 /* Power-down device's busmaster DMA clocks */
2639 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2640 udelay(5);
2641
4d2ccdb9
BC
2642 /* Stop the device, and put it in low power state */
2643 priv->cfg->ops->lib->apm_ops.stop(priv);
e9414b6b 2644
b481de9c 2645 exit:
3d24a9f7 2646 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2647
2648 if (priv->ibss_beacon)
2649 dev_kfree_skb(priv->ibss_beacon);
2650 priv->ibss_beacon = NULL;
2651
2652 /* clear out any free frames */
bb8c093b 2653 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2654}
2655
4a8a4322 2656static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2657{
2658 mutex_lock(&priv->mutex);
bb8c093b 2659 __iwl3945_down(priv);
b481de9c 2660 mutex_unlock(&priv->mutex);
b24d22b1 2661
bb8c093b 2662 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2663}
2664
2665#define MAX_HW_RESTARTS 5
2666
4a8a4322 2667static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2668{
2669 int rc, i;
2670
2671 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2672 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2673 return -EIO;
2674 }
2675
e903fbd4 2676 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2677 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2678 return -EIO;
2679 }
2680
e655b9f0 2681 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2682 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2683 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2684 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2685 else {
2686 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2687 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2688 return -ENODEV;
b481de9c 2689 }
80fcc9e2 2690
5d49f498 2691 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2692
bb8c093b 2693 rc = iwl3945_hw_nic_init(priv);
b481de9c 2694 if (rc) {
15b1687c 2695 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2696 return rc;
2697 }
2698
2699 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2700 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2701 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2702 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2703
2704 /* clear (again), then enable host interrupts */
5d49f498 2705 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2706 iwl_enable_interrupts(priv);
b481de9c
ZY
2707
2708 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2709 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2710 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2711
2712 /* Copy original ucode data image from disk into backup cache.
2713 * This will be used to initialize the on-board processor's
2714 * data SRAM for a clean start when the runtime program first loads. */
2715 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2716 priv->ucode_data.len);
b481de9c 2717
e655b9f0
ZY
2718 /* We return success when we resume from suspend and rf_kill is on. */
2719 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2720 return 0;
2721
b481de9c
ZY
2722 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2723
c587de0b 2724 iwl_clear_stations_table(priv);
b481de9c
ZY
2725
2726 /* load bootstrap state machine,
2727 * load bootstrap program into processor's memory,
2728 * prepare to load the "initialize" uCode */
0164b9b4 2729 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2730
2731 if (rc) {
15b1687c
WT
2732 IWL_ERR(priv,
2733 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2734 continue;
2735 }
2736
2737 /* start card; "initialize" will load runtime ucode */
bb8c093b 2738 iwl3945_nic_start(priv);
b481de9c 2739
e1623446 2740 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2741
2742 return 0;
2743 }
2744
2745 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2746 __iwl3945_down(priv);
ebef2008 2747 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2748
2749 /* tried to restart and config the device for as long as our
2750 * patience could withstand */
15b1687c 2751 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2752 return -EIO;
2753}
2754
2755
2756/*****************************************************************************
2757 *
2758 * Workqueue callbacks
2759 *
2760 *****************************************************************************/
2761
bb8c093b 2762static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2763{
4a8a4322
AK
2764 struct iwl_priv *priv =
2765 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2766
2767 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2768 return;
2769
2770 mutex_lock(&priv->mutex);
bb8c093b 2771 iwl3945_init_alive_start(priv);
b481de9c
ZY
2772 mutex_unlock(&priv->mutex);
2773}
2774
bb8c093b 2775static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2776{
4a8a4322
AK
2777 struct iwl_priv *priv =
2778 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2779
2780 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2781 return;
2782
2783 mutex_lock(&priv->mutex);
bb8c093b 2784 iwl3945_alive_start(priv);
b481de9c
ZY
2785 mutex_unlock(&priv->mutex);
2786}
2787
743cdf1b
BC
2788/*
2789 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2790 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2791 * *is* readable even when device has been SW_RESET into low power mode
2792 * (e.g. during RF KILL).
2793 */
2663516d
HS
2794static void iwl3945_rfkill_poll(struct work_struct *data)
2795{
2796 struct iwl_priv *priv =
2797 container_of(data, struct iwl_priv, rfkill_poll.work);
743cdf1b
BC
2798 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
2799 bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
2800 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2663516d 2801
743cdf1b
BC
2802 if (new_rfkill != old_rfkill) {
2803 if (new_rfkill)
2804 set_bit(STATUS_RF_KILL_HW, &priv->status);
2805 else
2806 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2663516d 2807
743cdf1b
BC
2808 wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
2809
2810 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
2811 new_rfkill ? "disable radio" : "enable radio");
2812 }
2663516d 2813
743cdf1b
BC
2814 /* Keep this running, even if radio now enabled. This will be
2815 * cancelled in mac_start() if system decides to start again */
2663516d
HS
2816 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2817 round_jiffies_relative(2 * HZ));
2818
2819}
2820
b481de9c 2821#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2822static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2823{
4a8a4322
AK
2824 struct iwl_priv *priv =
2825 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2826 struct iwl_host_cmd cmd = {
b481de9c 2827 .id = REPLY_SCAN_CMD,
bb8c093b 2828 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2829 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2830 };
2831 int rc = 0;
bb8c093b 2832 struct iwl3945_scan_cmd *scan;
b481de9c 2833 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2834 u8 n_probes = 0;
8318d78a 2835 enum ieee80211_band band;
1ecf9fc1 2836 bool is_active = false;
b481de9c
ZY
2837
2838 conf = ieee80211_get_hw_conf(priv->hw);
2839
2840 mutex_lock(&priv->mutex);
2841
fbc9f97b
RC
2842 cancel_delayed_work(&priv->scan_check);
2843
775a6e27 2844 if (!iwl_is_ready(priv)) {
39aadf8c 2845 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2846 goto done;
2847 }
2848
a96a27f9 2849 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2850 * was given the chance to run... */
2851 if (!test_bit(STATUS_SCANNING, &priv->status))
2852 goto done;
2853
2854 /* This should never be called or scheduled if there is currently
2855 * a scan active in the hardware. */
2856 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2857 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2858 "Ignoring second request.\n");
b481de9c
ZY
2859 rc = -EIO;
2860 goto done;
2861 }
2862
2863 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2864 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2865 goto done;
2866 }
2867
2868 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2869 IWL_DEBUG_HC(priv,
2870 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2871 goto done;
2872 }
2873
775a6e27 2874 if (iwl_is_rfkill(priv)) {
e1623446 2875 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2876 goto done;
2877 }
2878
2879 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2880 IWL_DEBUG_HC(priv,
2881 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2882 goto done;
2883 }
2884
2885 if (!priv->scan_bands) {
e1623446 2886 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2887 goto done;
2888 }
2889
805cee5b
WT
2890 if (!priv->scan) {
2891 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2892 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2893 if (!priv->scan) {
b481de9c
ZY
2894 rc = -ENOMEM;
2895 goto done;
2896 }
2897 }
805cee5b 2898 scan = priv->scan;
bb8c093b 2899 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2900
2901 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2902 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2903
8ccde88a 2904 if (iwl_is_associated(priv)) {
b481de9c
ZY
2905 u16 interval = 0;
2906 u32 extra;
2907 u32 suspend_time = 100;
2908 u32 scan_suspend_time = 100;
2909 unsigned long flags;
2910
e1623446 2911 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2912
2913 spin_lock_irqsave(&priv->lock, flags);
2914 interval = priv->beacon_int;
2915 spin_unlock_irqrestore(&priv->lock, flags);
2916
2917 scan->suspend_time = 0;
15e869d8 2918 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2919 if (!interval)
2920 interval = suspend_time;
2921 /*
2922 * suspend time format:
2923 * 0-19: beacon interval in usec (time before exec.)
2924 * 20-23: 0
2925 * 24-31: number of beacons (suspend between channels)
2926 */
2927
2928 extra = (suspend_time / interval) << 24;
2929 scan_suspend_time = 0xFF0FFFFF &
2930 (extra | ((suspend_time % interval) * 1024));
2931
2932 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2933 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2934 scan_suspend_time, interval);
2935 }
2936
1ecf9fc1
JB
2937 if (priv->scan_request->n_ssids) {
2938 int i, p = 0;
2939 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2940 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2941 /* always does wildcard anyway */
2942 if (!priv->scan_request->ssids[i].ssid_len)
2943 continue;
2944 scan->direct_scan[p].id = WLAN_EID_SSID;
2945 scan->direct_scan[p].len =
2946 priv->scan_request->ssids[i].ssid_len;
2947 memcpy(scan->direct_scan[p].ssid,
2948 priv->scan_request->ssids[i].ssid,
2949 priv->scan_request->ssids[i].ssid_len);
2950 n_probes++;
2951 p++;
2952 }
2953 is_active = true;
f9340520 2954 } else
1ecf9fc1 2955 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2956
2957 /* We don't build a direct scan probe request; the uCode will do
2958 * that based on the direct_mask added to each channel entry */
b481de9c 2959 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2960 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2961 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2962
2963 /* flags + rate selection */
2964
66b5004d 2965 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2966 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2967 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2968 scan->good_CRC_th = 0;
8318d78a 2969 band = IEEE80211_BAND_2GHZ;
66b5004d 2970 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2971 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2972 /*
2973 * If active scaning is requested but a certain channel
2974 * is marked passive, we can do active scanning if we
2975 * detect transmissions.
2976 */
2977 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2978 band = IEEE80211_BAND_5GHZ;
66b5004d 2979 } else {
39aadf8c 2980 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2981 goto done;
2982 }
2983
77fecfb8 2984 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2985 iwl_fill_probe_req(priv,
2986 (struct ieee80211_mgmt *)scan->data,
2987 priv->scan_request->ie,
2988 priv->scan_request->ie_len,
2989 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2990
b481de9c
ZY
2991 /* select Rx antennas */
2992 scan->flags |= iwl3945_get_antenna_flags(priv);
2993
279b05d4 2994 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2995 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2996
f9340520 2997 scan->channel_count =
1ecf9fc1 2998 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2999 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 3000
14b54336 3001 if (scan->channel_count == 0) {
e1623446 3002 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
3003 goto done;
3004 }
3005
b481de9c 3006 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 3007 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
3008 cmd.data = scan;
3009 scan->len = cpu_to_le16(cmd.len);
3010
3011 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 3012 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3013 if (rc)
3014 goto done;
3015
3016 queue_delayed_work(priv->workqueue, &priv->scan_check,
3017 IWL_SCAN_CHECK_WATCHDOG);
3018
3019 mutex_unlock(&priv->mutex);
3020 return;
3021
3022 done:
2420ebc1
MA
3023 /* can not perform scan make sure we clear scanning
3024 * bits from status so next scan request can be performed.
3025 * if we dont clear scanning status bit here all next scan
3026 * will fail
3027 */
3028 clear_bit(STATUS_SCAN_HW, &priv->status);
3029 clear_bit(STATUS_SCANNING, &priv->status);
3030
01ebd063 3031 /* inform mac80211 scan aborted */
b481de9c
ZY
3032 queue_work(priv->workqueue, &priv->scan_completed);
3033 mutex_unlock(&priv->mutex);
3034}
3035
bb8c093b 3036static void iwl3945_bg_up(struct work_struct *data)
b481de9c 3037{
4a8a4322 3038 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
3039
3040 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3041 return;
3042
3043 mutex_lock(&priv->mutex);
bb8c093b 3044 __iwl3945_up(priv);
b481de9c
ZY
3045 mutex_unlock(&priv->mutex);
3046}
3047
bb8c093b 3048static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3049{
4a8a4322 3050 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3051
3052 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3053 return;
3054
19cc1087
JB
3055 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3056 mutex_lock(&priv->mutex);
3057 priv->vif = NULL;
3058 priv->is_open = 0;
3059 mutex_unlock(&priv->mutex);
3060 iwl3945_down(priv);
3061 ieee80211_restart_hw(priv->hw);
3062 } else {
3063 iwl3945_down(priv);
3064 queue_work(priv->workqueue, &priv->up);
3065 }
b481de9c
ZY
3066}
3067
bb8c093b 3068static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3069{
4a8a4322
AK
3070 struct iwl_priv *priv =
3071 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3072
3073 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3074 return;
3075
3076 mutex_lock(&priv->mutex);
bb8c093b 3077 iwl3945_rx_replenish(priv);
b481de9c
ZY
3078 mutex_unlock(&priv->mutex);
3079}
3080
7878a5a4
MA
3081#define IWL_DELAY_NEXT_SCAN (HZ*2)
3082
5bbe233b 3083void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3084{
b481de9c
ZY
3085 int rc = 0;
3086 struct ieee80211_conf *conf = NULL;
3087
05c914fe 3088 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3089 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3090 return;
3091 }
3092
3093
e1623446 3094 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3095 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3096
3097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3098 return;
3099
322a9811 3100 if (!priv->vif || !priv->is_open)
6ef89d0a 3101 return;
322a9811 3102
af0053d6 3103 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3104
b481de9c
ZY
3105 conf = ieee80211_get_hw_conf(priv->hw);
3106
8ccde88a 3107 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3108 iwlcore_commit_rxon(priv);
b481de9c 3109
28afaf91 3110 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3111 iwl_setup_rxon_timing(priv);
518099a8 3112 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3113 sizeof(priv->rxon_timing), &priv->rxon_timing);
3114 if (rc)
39aadf8c 3115 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3116 "Attempting to continue.\n");
3117
8ccde88a 3118 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3119
8ccde88a 3120 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3121
e1623446 3122 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3123 priv->assoc_id, priv->beacon_int);
3124
3125 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3126 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3127 else
8ccde88a 3128 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3129
8ccde88a 3130 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3131 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3132 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3133 else
8ccde88a 3134 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3135
05c914fe 3136 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3137 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3138
3139 }
3140
e0158e61 3141 iwlcore_commit_rxon(priv);
b481de9c
ZY
3142
3143 switch (priv->iw_mode) {
05c914fe 3144 case NL80211_IFTYPE_STATION:
bb8c093b 3145 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3146 break;
3147
05c914fe 3148 case NL80211_IFTYPE_ADHOC:
b481de9c 3149
ce546fd2 3150 priv->assoc_id = 1;
c587de0b 3151 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3152 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3153 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3154 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3155 CMD_ASYNC);
bb8c093b
CH
3156 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3157 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3158
3159 break;
3160
3161 default:
15b1687c 3162 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3163 __func__, priv->iw_mode);
b481de9c
ZY
3164 break;
3165 }
3166
14d2aac5 3167 iwl_activate_qos(priv, 0);
292ae174 3168
7878a5a4
MA
3169 /* we have just associated, don't start scan too early */
3170 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3171}
3172
b481de9c
ZY
3173/*****************************************************************************
3174 *
3175 * mac80211 entry point functions
3176 *
3177 *****************************************************************************/
3178
5a66926a
ZY
3179#define UCODE_READY_TIMEOUT (2 * HZ)
3180
bb8c093b 3181static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3182{
4a8a4322 3183 struct iwl_priv *priv = hw->priv;
5a66926a 3184 int ret;
b481de9c 3185
e1623446 3186 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3187
3188 /* we should be verifying the device is ready to be opened */
3189 mutex_lock(&priv->mutex);
3190
5a66926a
ZY
3191 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3192 * ucode filename and max sizes are card-specific. */
3193
3194 if (!priv->ucode_code.len) {
3195 ret = iwl3945_read_ucode(priv);
3196 if (ret) {
15b1687c 3197 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3198 mutex_unlock(&priv->mutex);
3199 goto out_release_irq;
3200 }
3201 }
b481de9c 3202
e655b9f0 3203 ret = __iwl3945_up(priv);
b481de9c
ZY
3204
3205 mutex_unlock(&priv->mutex);
5a66926a 3206
e655b9f0
ZY
3207 if (ret)
3208 goto out_release_irq;
3209
e1623446 3210 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3211
5a66926a
ZY
3212 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3213 * mac80211 will not be run successfully. */
3214 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3215 test_bit(STATUS_READY, &priv->status),
3216 UCODE_READY_TIMEOUT);
3217 if (!ret) {
3218 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3219 IWL_ERR(priv,
3220 "Wait for START_ALIVE timeout after %dms.\n",
3221 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3222 ret = -ETIMEDOUT;
3223 goto out_release_irq;
3224 }
3225 }
3226
2663516d
HS
3227 /* ucode is running and will send rfkill notifications,
3228 * no need to poll the killswitch state anymore */
3229 cancel_delayed_work(&priv->rfkill_poll);
3230
e932a609
JB
3231 iwl_led_start(priv);
3232
e655b9f0 3233 priv->is_open = 1;
e1623446 3234 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3235 return 0;
5a66926a
ZY
3236
3237out_release_irq:
e655b9f0 3238 priv->is_open = 0;
e1623446 3239 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3240 return ret;
b481de9c
ZY
3241}
3242
bb8c093b 3243static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3244{
4a8a4322 3245 struct iwl_priv *priv = hw->priv;
b481de9c 3246
e1623446 3247 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3248
e655b9f0 3249 if (!priv->is_open) {
e1623446 3250 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3251 return;
3252 }
3253
b481de9c 3254 priv->is_open = 0;
5a66926a 3255
775a6e27 3256 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3257 /* stop mac, cancel any scan request and clear
3258 * RXON_FILTER_ASSOC_MSK BIT
3259 */
5a66926a 3260 mutex_lock(&priv->mutex);
af0053d6 3261 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3262 mutex_unlock(&priv->mutex);
fde3571f
MA
3263 }
3264
5a66926a
ZY
3265 iwl3945_down(priv);
3266
3267 flush_workqueue(priv->workqueue);
2663516d
HS
3268
3269 /* start polling the killswitch state again */
3270 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3271 round_jiffies_relative(2 * HZ));
6ef89d0a 3272
e1623446 3273 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3274}
3275
e039fa4a 3276static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3277{
4a8a4322 3278 struct iwl_priv *priv = hw->priv;
b481de9c 3279
e1623446 3280 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3281
e1623446 3282 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3283 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3284
e039fa4a 3285 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3286 dev_kfree_skb_any(skb);
3287
e1623446 3288 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3289 return NETDEV_TX_OK;
b481de9c
ZY
3290}
3291
60690a6a 3292void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3293{
3294 int rc = 0;
3295
d986bcd1 3296 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3297 return;
3298
3299 /* The following should be done only at AP bring up */
8ccde88a 3300 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3301
3302 /* RXON - unassoc (to set timing command) */
8ccde88a 3303 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3304 iwlcore_commit_rxon(priv);
b481de9c
ZY
3305
3306 /* RXON Timing */
28afaf91 3307 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3308 iwl_setup_rxon_timing(priv);
518099a8
SO
3309 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3310 sizeof(priv->rxon_timing),
3311 &priv->rxon_timing);
b481de9c 3312 if (rc)
39aadf8c 3313 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3314 "Attempting to continue.\n");
3315
3316 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3317 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3318 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3319 priv->staging_rxon.flags |=
b481de9c
ZY
3320 RXON_FLG_SHORT_PREAMBLE_MSK;
3321 else
8ccde88a 3322 priv->staging_rxon.flags &=
b481de9c
ZY
3323 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3324
8ccde88a 3325 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3326 if (priv->assoc_capability &
3327 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3328 priv->staging_rxon.flags |=
b481de9c
ZY
3329 RXON_FLG_SHORT_SLOT_MSK;
3330 else
8ccde88a 3331 priv->staging_rxon.flags &=
b481de9c
ZY
3332 ~RXON_FLG_SHORT_SLOT_MSK;
3333
05c914fe 3334 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3335 priv->staging_rxon.flags &=
b481de9c
ZY
3336 ~RXON_FLG_SHORT_SLOT_MSK;
3337 }
3338 /* restore RXON assoc */
8ccde88a 3339 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3340 iwlcore_commit_rxon(priv);
c587de0b 3341 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3342 }
bb8c093b 3343 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3344
3345 /* FIXME - we need to add code here to detect a totally new
3346 * configuration, reset the AP, unassoc, rxon timing, assoc,
3347 * clear sta table, add BCAST sta... */
3348}
3349
bb8c093b 3350static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3351 struct ieee80211_vif *vif,
3352 struct ieee80211_sta *sta,
3353 struct ieee80211_key_conf *key)
b481de9c 3354{
4a8a4322 3355 struct iwl_priv *priv = hw->priv;
dc822b5d 3356 const u8 *addr;
6e21f15c
AK
3357 int ret = 0;
3358 u8 sta_id = IWL_INVALID_STATION;
3359 u8 static_key;
b481de9c 3360
e1623446 3361 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3362
df878d8f 3363 if (iwl3945_mod_params.sw_crypto) {
e1623446 3364 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3365 return -EOPNOTSUPP;
3366 }
3367
42986796 3368 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3369 static_key = !iwl_is_associated(priv);
3370
3371 if (!static_key) {
c587de0b 3372 sta_id = iwl_find_station(priv, addr);
6e21f15c 3373 if (sta_id == IWL_INVALID_STATION) {
12514396 3374 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3375 addr);
3376 return -EINVAL;
3377 }
b481de9c
ZY
3378 }
3379
3380 mutex_lock(&priv->mutex);
af0053d6 3381 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3382 mutex_unlock(&priv->mutex);
15e869d8 3383
b481de9c 3384 switch (cmd) {
6e21f15c
AK
3385 case SET_KEY:
3386 if (static_key)
3387 ret = iwl3945_set_static_key(priv, key);
3388 else
3389 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3390 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3391 break;
3392 case DISABLE_KEY:
6e21f15c
AK
3393 if (static_key)
3394 ret = iwl3945_remove_static_key(priv);
3395 else
3396 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3397 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3398 break;
3399 default:
42986796 3400 ret = -EINVAL;
b481de9c
ZY
3401 }
3402
e1623446 3403 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3404
42986796 3405 return ret;
b481de9c
ZY
3406}
3407
b481de9c
ZY
3408/*****************************************************************************
3409 *
3410 * sysfs attributes
3411 *
3412 *****************************************************************************/
3413
d08853a3 3414#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3415
3416/*
3417 * The following adds a new attribute to the sysfs representation
3418 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3419 * used for controlling the debug level.
3420 *
3421 * See the level definitions in iwl for details.
a562a9dd 3422 *
3d816c77
RC
3423 * The debug_level being managed using sysfs below is a per device debug
3424 * level that is used instead of the global debug level if it (the per
3425 * device debug level) is set.
b481de9c 3426 */
40b8ec0b
SO
3427static ssize_t show_debug_level(struct device *d,
3428 struct device_attribute *attr, char *buf)
b481de9c 3429{
3d816c77
RC
3430 struct iwl_priv *priv = dev_get_drvdata(d);
3431 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3432}
40b8ec0b
SO
3433static ssize_t store_debug_level(struct device *d,
3434 struct device_attribute *attr,
b481de9c
ZY
3435 const char *buf, size_t count)
3436{
928841b1 3437 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3438 unsigned long val;
3439 int ret;
b481de9c 3440
40b8ec0b
SO
3441 ret = strict_strtoul(buf, 0, &val);
3442 if (ret)
978785a3 3443 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3444 else {
3d816c77 3445 priv->debug_level = val;
20594eb0
WYG
3446 if (iwl_alloc_traffic_mem(priv))
3447 IWL_ERR(priv,
3448 "Not enough memory to generate traffic log\n");
3449 }
b481de9c
ZY
3450 return strnlen(buf, count);
3451}
3452
40b8ec0b
SO
3453static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3454 show_debug_level, store_debug_level);
b481de9c 3455
d08853a3 3456#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3457
b481de9c
ZY
3458static ssize_t show_temperature(struct device *d,
3459 struct device_attribute *attr, char *buf)
3460{
928841b1 3461 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3462
775a6e27 3463 if (!iwl_is_alive(priv))
b481de9c
ZY
3464 return -EAGAIN;
3465
bb8c093b 3466 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3467}
3468
3469static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3470
b481de9c
ZY
3471static ssize_t show_tx_power(struct device *d,
3472 struct device_attribute *attr, char *buf)
3473{
928841b1 3474 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3475 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3476}
3477
3478static ssize_t store_tx_power(struct device *d,
3479 struct device_attribute *attr,
3480 const char *buf, size_t count)
3481{
928841b1 3482 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3483 char *p = (char *)buf;
3484 u32 val;
3485
3486 val = simple_strtoul(p, &p, 10);
3487 if (p == buf)
978785a3 3488 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3489 else
bb8c093b 3490 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3491
3492 return count;
3493}
3494
3495static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3496
3497static ssize_t show_flags(struct device *d,
3498 struct device_attribute *attr, char *buf)
3499{
928841b1 3500 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3501
8ccde88a 3502 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3503}
3504
3505static ssize_t store_flags(struct device *d,
3506 struct device_attribute *attr,
3507 const char *buf, size_t count)
3508{
928841b1 3509 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3510 u32 flags = simple_strtoul(buf, NULL, 0);
3511
3512 mutex_lock(&priv->mutex);
8ccde88a 3513 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3514 /* Cancel any currently running scans... */
af0053d6 3515 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3516 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3517 else {
e1623446 3518 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3519 flags);
8ccde88a 3520 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3521 iwlcore_commit_rxon(priv);
b481de9c
ZY
3522 }
3523 }
3524 mutex_unlock(&priv->mutex);
3525
3526 return count;
3527}
3528
3529static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3530
3531static ssize_t show_filter_flags(struct device *d,
3532 struct device_attribute *attr, char *buf)
3533{
928841b1 3534 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3535
3536 return sprintf(buf, "0x%04X\n",
8ccde88a 3537 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3538}
3539
3540static ssize_t store_filter_flags(struct device *d,
3541 struct device_attribute *attr,
3542 const char *buf, size_t count)
3543{
928841b1 3544 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3545 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3546
3547 mutex_lock(&priv->mutex);
8ccde88a 3548 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3549 /* Cancel any currently running scans... */
af0053d6 3550 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3551 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3552 else {
e1623446 3553 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3554 "0x%04X\n", filter_flags);
8ccde88a 3555 priv->staging_rxon.filter_flags =
b481de9c 3556 cpu_to_le32(filter_flags);
e0158e61 3557 iwlcore_commit_rxon(priv);
b481de9c
ZY
3558 }
3559 }
3560 mutex_unlock(&priv->mutex);
3561
3562 return count;
3563}
3564
3565static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3566 store_filter_flags);
3567
b481de9c
ZY
3568static ssize_t show_measurement(struct device *d,
3569 struct device_attribute *attr, char *buf)
3570{
4a8a4322 3571 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3572 struct iwl_spectrum_notification measure_report;
b481de9c 3573 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3574 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3575 unsigned long flags;
3576
3577 spin_lock_irqsave(&priv->lock, flags);
3578 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3579 spin_unlock_irqrestore(&priv->lock, flags);
3580 return 0;
3581 }
3582 memcpy(&measure_report, &priv->measure_report, size);
3583 priv->measurement_status = 0;
3584 spin_unlock_irqrestore(&priv->lock, flags);
3585
3586 while (size && (PAGE_SIZE - len)) {
3587 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3588 PAGE_SIZE - len, 1);
3589 len = strlen(buf);
3590 if (PAGE_SIZE - len)
3591 buf[len++] = '\n';
3592
3593 ofs += 16;
3594 size -= min(size, 16U);
3595 }
3596
3597 return len;
3598}
3599
3600static ssize_t store_measurement(struct device *d,
3601 struct device_attribute *attr,
3602 const char *buf, size_t count)
3603{
4a8a4322 3604 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3605 struct ieee80211_measurement_params params = {
8ccde88a 3606 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3607 .start_time = cpu_to_le64(priv->last_tsf),
3608 .duration = cpu_to_le16(1),
3609 };
3610 u8 type = IWL_MEASURE_BASIC;
3611 u8 buffer[32];
3612 u8 channel;
3613
3614 if (count) {
3615 char *p = buffer;
3616 strncpy(buffer, buf, min(sizeof(buffer), count));
3617 channel = simple_strtoul(p, NULL, 0);
3618 if (channel)
3619 params.channel = channel;
3620
3621 p = buffer;
3622 while (*p && *p != ' ')
3623 p++;
3624 if (*p)
3625 type = simple_strtoul(p + 1, NULL, 0);
3626 }
3627
e1623446 3628 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3629 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3630 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3631
3632 return count;
3633}
3634
3635static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3636 show_measurement, store_measurement);
b481de9c 3637
b481de9c
ZY
3638static ssize_t store_retry_rate(struct device *d,
3639 struct device_attribute *attr,
3640 const char *buf, size_t count)
3641{
4a8a4322 3642 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3643
3644 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3645 if (priv->retry_rate <= 0)
3646 priv->retry_rate = 1;
3647
3648 return count;
3649}
3650
3651static ssize_t show_retry_rate(struct device *d,
3652 struct device_attribute *attr, char *buf)
3653{
4a8a4322 3654 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3655 return sprintf(buf, "%d", priv->retry_rate);
3656}
3657
3658static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3659 store_retry_rate);
3660
d25aabb0 3661
b481de9c
ZY
3662static ssize_t show_channels(struct device *d,
3663 struct device_attribute *attr, char *buf)
3664{
8318d78a
JB
3665 /* all this shit doesn't belong into sysfs anyway */
3666 return 0;
b481de9c
ZY
3667}
3668
3669static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3670
3671static ssize_t show_statistics(struct device *d,
3672 struct device_attribute *attr, char *buf)
3673{
4a8a4322 3674 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3675 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3676 u32 len = 0, ofs = 0;
f2c7e521 3677 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3678 int rc = 0;
3679
775a6e27 3680 if (!iwl_is_alive(priv))
b481de9c
ZY
3681 return -EAGAIN;
3682
3683 mutex_lock(&priv->mutex);
ef8d5529 3684 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3685 mutex_unlock(&priv->mutex);
3686
3687 if (rc) {
3688 len = sprintf(buf,
3689 "Error sending statistics request: 0x%08X\n", rc);
3690 return len;
3691 }
3692
3693 while (size && (PAGE_SIZE - len)) {
3694 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3695 PAGE_SIZE - len, 1);
3696 len = strlen(buf);
3697 if (PAGE_SIZE - len)
3698 buf[len++] = '\n';
3699
3700 ofs += 16;
3701 size -= min(size, 16U);
3702 }
3703
3704 return len;
3705}
3706
3707static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3708
3709static ssize_t show_antenna(struct device *d,
3710 struct device_attribute *attr, char *buf)
3711{
4a8a4322 3712 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3713
775a6e27 3714 if (!iwl_is_alive(priv))
b481de9c
ZY
3715 return -EAGAIN;
3716
7e4bca5e 3717 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3718}
3719
3720static ssize_t store_antenna(struct device *d,
3721 struct device_attribute *attr,
3722 const char *buf, size_t count)
3723{
7530f85f 3724 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3725 int ant;
b481de9c
ZY
3726
3727 if (count == 0)
3728 return 0;
3729
3730 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3731 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3732 return count;
3733 }
3734
3735 if ((ant >= 0) && (ant <= 2)) {
e1623446 3736 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3737 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3738 } else
e1623446 3739 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3740
3741
3742 return count;
3743}
3744
3745static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3746
3747static ssize_t show_status(struct device *d,
3748 struct device_attribute *attr, char *buf)
3749{
928841b1 3750 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3751 if (!iwl_is_alive(priv))
b481de9c
ZY
3752 return -EAGAIN;
3753 return sprintf(buf, "0x%08x\n", (int)priv->status);
3754}
3755
3756static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3757
3758static ssize_t dump_error_log(struct device *d,
3759 struct device_attribute *attr,
3760 const char *buf, size_t count)
3761{
928841b1 3762 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3763 char *p = (char *)buf;
3764
3765 if (p[0] == '1')
928841b1 3766 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3767
3768 return strnlen(buf, count);
3769}
3770
3771static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3772
b481de9c
ZY
3773/*****************************************************************************
3774 *
a96a27f9 3775 * driver setup and tear down
b481de9c
ZY
3776 *
3777 *****************************************************************************/
3778
4a8a4322 3779static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3780{
d21050c7 3781 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3782
3783 init_waitqueue_head(&priv->wait_command_queue);
3784
bb8c093b
CH
3785 INIT_WORK(&priv->up, iwl3945_bg_up);
3786 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3787 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3788 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3789 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3790 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3791 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3792 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3793 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3794 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3795 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3796
3797 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3798
3799 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3800 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3801}
3802
4a8a4322 3803static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3804{
bb8c093b 3805 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3806
e47eb6ad 3807 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3808 cancel_delayed_work(&priv->scan_check);
3809 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3810 cancel_work_sync(&priv->beacon_update);
3811}
3812
bb8c093b 3813static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3814 &dev_attr_antenna.attr,
3815 &dev_attr_channels.attr,
3816 &dev_attr_dump_errors.attr,
b481de9c
ZY
3817 &dev_attr_flags.attr,
3818 &dev_attr_filter_flags.attr,
b481de9c 3819 &dev_attr_measurement.attr,
b481de9c 3820 &dev_attr_retry_rate.attr,
b481de9c
ZY
3821 &dev_attr_statistics.attr,
3822 &dev_attr_status.attr,
3823 &dev_attr_temperature.attr,
b481de9c 3824 &dev_attr_tx_power.attr,
d08853a3 3825#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3826 &dev_attr_debug_level.attr,
3827#endif
b481de9c
ZY
3828 NULL
3829};
3830
bb8c093b 3831static struct attribute_group iwl3945_attribute_group = {
b481de9c 3832 .name = NULL, /* put in device directory */
bb8c093b 3833 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3834};
3835
bb8c093b
CH
3836static struct ieee80211_ops iwl3945_hw_ops = {
3837 .tx = iwl3945_mac_tx,
3838 .start = iwl3945_mac_start,
3839 .stop = iwl3945_mac_stop,
cbb6ab94 3840 .add_interface = iwl_mac_add_interface,
d8052319 3841 .remove_interface = iwl_mac_remove_interface,
4808368d 3842 .config = iwl_mac_config,
8ccde88a 3843 .configure_filter = iwl_configure_filter,
bb8c093b 3844 .set_key = iwl3945_mac_set_key,
aa89f31e 3845 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 3846 .conf_tx = iwl_mac_conf_tx,
bd564261 3847 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3848 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3849 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3850};
3851
e52119c5 3852static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3853{
3854 int ret;
e6148917 3855 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3856
3857 priv->retry_rate = 1;
3858 priv->ibss_beacon = NULL;
3859
90a30a02
KA
3860 spin_lock_init(&priv->sta_lock);
3861 spin_lock_init(&priv->hcmd_lock);
3862
3863 INIT_LIST_HEAD(&priv->free_frames);
3864
3865 mutex_init(&priv->mutex);
3866
3867 /* Clear the driver's (not device's) station table */
c587de0b 3868 iwl_clear_stations_table(priv);
90a30a02 3869
90a30a02
KA
3870 priv->ieee_channels = NULL;
3871 priv->ieee_rates = NULL;
3872 priv->band = IEEE80211_BAND_2GHZ;
3873
3874 priv->iw_mode = NL80211_IFTYPE_STATION;
a13d276f 3875 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
90a30a02
KA
3876
3877 iwl_reset_qos(priv);
3878
3879 priv->qos_data.qos_active = 0;
3880 priv->qos_data.qos_cap.val = 0;
3881
3882 priv->rates_mask = IWL_RATES_MASK;
62ea9c5b 3883 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3884
e6148917
SO
3885 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3886 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3887 eeprom->version);
3888 ret = -EINVAL;
3889 goto err;
3890 }
3891 ret = iwl_init_channel_map(priv);
90a30a02
KA
3892 if (ret) {
3893 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3894 goto err;
3895 }
3896
e6148917
SO
3897 /* Set up txpower settings in driver for all channels */
3898 if (iwl3945_txpower_set_from_eeprom(priv)) {
3899 ret = -EIO;
3900 goto err_free_channel_map;
3901 }
3902
534166de 3903 ret = iwlcore_init_geos(priv);
90a30a02
KA
3904 if (ret) {
3905 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3906 goto err_free_channel_map;
3907 }
534166de
SO
3908 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3909
2a4ddaab
AK
3910 return 0;
3911
3912err_free_channel_map:
3913 iwl_free_channel_map(priv);
3914err:
3915 return ret;
3916}
3917
3918static int iwl3945_setup_mac(struct iwl_priv *priv)
3919{
3920 int ret;
3921 struct ieee80211_hw *hw = priv->hw;
3922
3923 hw->rate_control_algorithm = "iwl-3945-rs";
3924 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3925
3926 /* Tell mac80211 our characteristics */
3927 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b 3928 IEEE80211_HW_NOISE_DBM |
bc45a670
RC
3929 IEEE80211_HW_SPECTRUM_MGMT;
3930
3931 if (!priv->cfg->broken_powersave)
3932 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3933 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3934
3935 hw->wiphy->interface_modes =
3936 BIT(NL80211_IFTYPE_STATION) |
3937 BIT(NL80211_IFTYPE_ADHOC);
3938
5be83de5
JB
3939 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
3940 WIPHY_FLAG_DISABLE_BEACON_HINTS;
37184244 3941
1ecf9fc1
JB
3942 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3943 /* we create the 802.11 header and a zero-length SSID element */
3944 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3945
2a4ddaab
AK
3946 /* Default value; 4 EDCA QOS priorities */
3947 hw->queues = 4;
3948
534166de
SO
3949 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3950 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3951 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3952
534166de
SO
3953 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3954 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3955 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3956
2a4ddaab
AK
3957 ret = ieee80211_register_hw(priv->hw);
3958 if (ret) {
3959 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3960 return ret;
3961 }
3962 priv->mac80211_registered = 1;
90a30a02 3963
2a4ddaab 3964 return 0;
90a30a02
KA
3965}
3966
bb8c093b 3967static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3968{
3969 int err = 0;
4a8a4322 3970 struct iwl_priv *priv;
b481de9c 3971 struct ieee80211_hw *hw;
c0f20d91 3972 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3973 struct iwl3945_eeprom *eeprom;
0359facc 3974 unsigned long flags;
b481de9c 3975
cee53ddb
KA
3976 /***********************
3977 * 1. Allocating HW data
3978 * ********************/
3979
b481de9c
ZY
3980 /* mac80211 allocates memory for this device instance, including
3981 * space for this driver's private structure */
90a30a02 3982 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3983 if (hw == NULL) {
a3139c59 3984 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3985 err = -ENOMEM;
3986 goto out;
3987 }
b481de9c 3988 priv = hw->priv;
90a30a02 3989 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3990
90a30a02
KA
3991 /*
3992 * Disabling hardware scan means that mac80211 will perform scans
3993 * "the hard way", rather than using device's scan.
3994 */
df878d8f 3995 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3996 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3997 iwl3945_hw_ops.hw_scan = NULL;
3998 }
3999
90a30a02 4000
e1623446 4001 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
4002 priv->cfg = cfg;
4003 priv->pci_dev = pdev;
40cefda9 4004 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 4005
d08853a3 4006#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
4007 atomic_set(&priv->restrict_refcnt, 0);
4008#endif
20594eb0
WYG
4009 if (iwl_alloc_traffic_mem(priv))
4010 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4011
cee53ddb
KA
4012 /***************************
4013 * 2. Initializing PCI bus
4014 * *************************/
b481de9c
ZY
4015 if (pci_enable_device(pdev)) {
4016 err = -ENODEV;
4017 goto out_ieee80211_free_hw;
4018 }
4019
4020 pci_set_master(pdev);
4021
284901a9 4022 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4023 if (!err)
284901a9 4024 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4025 if (err) {
978785a3 4026 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
4027 goto out_pci_disable_device;
4028 }
4029
4030 pci_set_drvdata(pdev, priv);
4031 err = pci_request_regions(pdev, DRV_NAME);
4032 if (err)
4033 goto out_pci_disable_device;
6440adb5 4034
cee53ddb
KA
4035 /***********************
4036 * 3. Read REV Register
4037 * ********************/
b481de9c
ZY
4038 priv->hw_base = pci_iomap(pdev, 0, 0);
4039 if (!priv->hw_base) {
4040 err = -ENODEV;
4041 goto out_pci_release_regions;
4042 }
4043
e1623446 4044 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4045 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4046 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4047
cee53ddb
KA
4048 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4049 * PCI Tx retries from interfering with C3 CPU state */
4050 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4051
731a29b7 4052 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
4053 * we should init now
4054 */
4055 spin_lock_init(&priv->reg_lock);
731a29b7 4056 spin_lock_init(&priv->lock);
a8b50a0a 4057
cee53ddb
KA
4058 /***********************
4059 * 4. Read EEPROM
4060 * ********************/
90a30a02 4061
cee53ddb 4062 /* Read the EEPROM */
e6148917 4063 err = iwl_eeprom_init(priv);
cee53ddb 4064 if (err) {
15b1687c 4065 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4066 goto out_iounmap;
cee53ddb
KA
4067 }
4068 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4069 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4070 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4071 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4072 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4073
cee53ddb
KA
4074 /***********************
4075 * 5. Setup HW Constants
4076 * ********************/
b481de9c 4077 /* Device-specific setup */
3832ec9d 4078 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4079 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4080 goto out_eeprom_free;
b481de9c
ZY
4081 }
4082
cee53ddb
KA
4083 /***********************
4084 * 6. Setup priv
4085 * ********************/
cee53ddb 4086
90a30a02 4087 err = iwl3945_init_drv(priv);
b481de9c 4088 if (err) {
90a30a02 4089 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4090 goto out_unset_hw_params;
b481de9c
ZY
4091 }
4092
978785a3
TW
4093 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4094 priv->cfg->name);
cee53ddb 4095
cee53ddb 4096 /***********************
09f9bf79 4097 * 7. Setup Services
cee53ddb
KA
4098 * ********************/
4099
4100 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4101 iwl_disable_interrupts(priv);
cee53ddb
KA
4102 spin_unlock_irqrestore(&priv->lock, flags);
4103
2663516d
HS
4104 pci_enable_msi(priv->pci_dev);
4105
ef850d7c
MA
4106 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4107 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4108 if (err) {
4109 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4110 goto out_disable_msi;
4111 }
4112
cee53ddb 4113 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4114 if (err) {
15b1687c 4115 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4116 goto out_release_irq;
849e0dce 4117 }
849e0dce 4118
8ccde88a
SO
4119 iwl_set_rxon_channel(priv,
4120 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4121 iwl3945_setup_deferred_work(priv);
4122 iwl3945_setup_rx_handlers(priv);
008a9e3e 4123 iwl_power_initialize(priv);
cee53ddb 4124
cee53ddb 4125 /*********************************
09f9bf79 4126 * 8. Setup and Register mac80211
cee53ddb
KA
4127 * *******************************/
4128
2a4ddaab 4129 iwl_enable_interrupts(priv);
b481de9c 4130
2a4ddaab
AK
4131 err = iwl3945_setup_mac(priv);
4132 if (err)
4133 goto out_remove_sysfs;
cee53ddb 4134
a75fbe8d
AK
4135 err = iwl_dbgfs_register(priv, DRV_NAME);
4136 if (err)
4137 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4138
2663516d
HS
4139 /* Start monitoring the killswitch */
4140 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4141 2 * HZ);
4142
b481de9c
ZY
4143 return 0;
4144
cee53ddb 4145 out_remove_sysfs:
c8f16138
RC
4146 destroy_workqueue(priv->workqueue);
4147 priv->workqueue = NULL;
cee53ddb 4148 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4149 out_release_irq:
2663516d 4150 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4151 out_disable_msi:
4152 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4153 iwlcore_free_geos(priv);
4154 iwl_free_channel_map(priv);
4155 out_unset_hw_params:
4156 iwl3945_unset_hw_params(priv);
4157 out_eeprom_free:
4158 iwl_eeprom_free(priv);
b481de9c
ZY
4159 out_iounmap:
4160 pci_iounmap(pdev, priv->hw_base);
4161 out_pci_release_regions:
4162 pci_release_regions(pdev);
4163 out_pci_disable_device:
b481de9c 4164 pci_set_drvdata(pdev, NULL);
623d563e 4165 pci_disable_device(pdev);
b481de9c 4166 out_ieee80211_free_hw:
20594eb0 4167 iwl_free_traffic_mem(priv);
d7c76f4c 4168 ieee80211_free_hw(priv->hw);
b481de9c
ZY
4169 out:
4170 return err;
4171}
4172
c83dbf68 4173static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4174{
4a8a4322 4175 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4176 unsigned long flags;
b481de9c
ZY
4177
4178 if (!priv)
4179 return;
4180
e1623446 4181 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4182
a75fbe8d
AK
4183 iwl_dbgfs_unregister(priv);
4184
b481de9c 4185 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4186
d552bfb6
KA
4187 if (priv->mac80211_registered) {
4188 ieee80211_unregister_hw(priv->hw);
4189 priv->mac80211_registered = 0;
4190 } else {
4191 iwl3945_down(priv);
4192 }
b481de9c 4193
c166b25a
BC
4194 /*
4195 * Make sure device is reset to low power before unloading driver.
4196 * This may be redundant with iwl_down(), but there are paths to
4197 * run iwl_down() without calling apm_ops.stop(), and there are
4198 * paths to avoid running iwl_down() at all before leaving driver.
4199 * This (inexpensive) call *makes sure* device is reset.
4200 */
4201 priv->cfg->ops->lib->apm_ops.stop(priv);
4202
0359facc
MA
4203 /* make sure we flush any pending irq or
4204 * tasklet for the driver
4205 */
4206 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4207 iwl_disable_interrupts(priv);
0359facc
MA
4208 spin_unlock_irqrestore(&priv->lock, flags);
4209
4210 iwl_synchronize_irq(priv);
4211
bb8c093b 4212 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4213
71d449b5 4214 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4215
bb8c093b 4216 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4217
4218 if (priv->rxq.bd)
df833b1d 4219 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4220 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4221
3832ec9d 4222 iwl3945_unset_hw_params(priv);
c587de0b 4223 iwl_clear_stations_table(priv);
b481de9c 4224
6ef89d0a
MA
4225 /*netif_stop_queue(dev); */
4226 flush_workqueue(priv->workqueue);
4227
bb8c093b 4228 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4229 * priv->workqueue... so we can't take down the workqueue
4230 * until now... */
4231 destroy_workqueue(priv->workqueue);
4232 priv->workqueue = NULL;
20594eb0 4233 iwl_free_traffic_mem(priv);
b481de9c 4234
2663516d
HS
4235 free_irq(pdev->irq, priv);
4236 pci_disable_msi(pdev);
4237
b481de9c
ZY
4238 pci_iounmap(pdev, priv->hw_base);
4239 pci_release_regions(pdev);
4240 pci_disable_device(pdev);
4241 pci_set_drvdata(pdev, NULL);
4242
e6148917 4243 iwl_free_channel_map(priv);
534166de 4244 iwlcore_free_geos(priv);
805cee5b 4245 kfree(priv->scan);
b481de9c
ZY
4246 if (priv->ibss_beacon)
4247 dev_kfree_skb(priv->ibss_beacon);
4248
4249 ieee80211_free_hw(priv->hw);
4250}
4251
b481de9c
ZY
4252
4253/*****************************************************************************
4254 *
4255 * driver and module entry point
4256 *
4257 *****************************************************************************/
4258
bb8c093b 4259static struct pci_driver iwl3945_driver = {
b481de9c 4260 .name = DRV_NAME,
bb8c093b
CH
4261 .id_table = iwl3945_hw_card_ids,
4262 .probe = iwl3945_pci_probe,
4263 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4264#ifdef CONFIG_PM
6da3a13e
WYG
4265 .suspend = iwl_pci_suspend,
4266 .resume = iwl_pci_resume,
b481de9c
ZY
4267#endif
4268};
4269
bb8c093b 4270static int __init iwl3945_init(void)
b481de9c
ZY
4271{
4272
4273 int ret;
4274 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4275 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4276
4277 ret = iwl3945_rate_control_register();
4278 if (ret) {
a3139c59
SO
4279 printk(KERN_ERR DRV_NAME
4280 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4281 return ret;
4282 }
4283
bb8c093b 4284 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4285 if (ret) {
a3139c59 4286 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4287 goto error_register;
b481de9c 4288 }
b481de9c
ZY
4289
4290 return ret;
897e1cf2 4291
897e1cf2
RC
4292error_register:
4293 iwl3945_rate_control_unregister();
4294 return ret;
b481de9c
ZY
4295}
4296
bb8c093b 4297static void __exit iwl3945_exit(void)
b481de9c 4298{
bb8c093b 4299 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4300 iwl3945_rate_control_unregister();
b481de9c
ZY
4301}
4302
a0987a8d 4303MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4304
4e30cb69 4305module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
b481de9c 4306MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4e30cb69 4307module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
9c74d9fb
SO
4308MODULE_PARM_DESC(swcrypto,
4309 "using software crypto (default 1 [software])\n");
a562a9dd 4310#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4311module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
b481de9c 4312MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4313#endif
4e30cb69
WYG
4314module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
4315 int, S_IRUGO);
b481de9c 4316MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4e30cb69 4317module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
af48d048
SO
4318MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4319
bb8c093b
CH
4320module_exit(iwl3945_exit);
4321module_init(iwl3945_init);