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iwlwifi: make sure device is reset when unloading driver
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
a3139c59
SO
48#define DRV_NAME "iwl3945"
49
dbb6654c
WT
50#include "iwl-fh.h"
51#include "iwl-3945-fh.h"
600c0e11 52#include "iwl-commands.h"
17f841cd 53#include "iwl-sta.h"
b481de9c
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54#include "iwl-3945.h"
55#include "iwl-helpers.h"
5747d47f 56#include "iwl-core.h"
d20b3c65 57#include "iwl-dev.h"
b481de9c 58
b481de9c
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59/*
60 * module name, copyright, version, etc.
b481de9c
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61 */
62
63#define DRV_DESCRIPTION \
64"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
65
d08853a3 66#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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67#define VD "d"
68#else
69#define VD
70#endif
71
c8b0e6e1 72#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
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73#define VS "s"
74#else
75#define VS
76#endif
77
eaa686c3 78#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 79#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 80#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 81#define DRV_VERSION IWL39_VERSION
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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87MODULE_LICENSE("GPL");
88
df878d8f
KA
89 /* module parameters */
90struct iwl_mod_params iwl3945_mod_params = {
9c74d9fb 91 .sw_crypto = 1,
af48d048 92 .restart_fw = 1,
df878d8f
KA
93 /* the rest are 0 by default */
94};
95
7e4bca5e
SO
96/**
97 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
98 * @priv: eeprom and antenna fields are used to determine antenna flags
99 *
100 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
101 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
102 *
103 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
104 * IWL_ANTENNA_MAIN - Force MAIN antenna
105 * IWL_ANTENNA_AUX - Force AUX antenna
106 */
107__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
108{
109 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
110
111 switch (iwl3945_mod_params.antenna) {
112 case IWL_ANTENNA_DIVERSITY:
113 return 0;
114
115 case IWL_ANTENNA_MAIN:
116 if (eeprom->antenna_switch_type)
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
118 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
119
120 case IWL_ANTENNA_AUX:
121 if (eeprom->antenna_switch_type)
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
123 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
124 }
125
126 /* bad antenna selector value */
127 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
128 iwl3945_mod_params.antenna);
129
130 return 0; /* "diversity" is default if error */
131}
132
6e21f15c 133static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
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134 struct ieee80211_key_conf *keyconf,
135 u8 sta_id)
136{
137 unsigned long flags;
138 __le16 key_flags = 0;
6e21f15c
AK
139 int ret;
140
141 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
142 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
143
144 if (sta_id == priv->hw_params.bcast_sta_id)
145 key_flags |= STA_KEY_MULTICAST_MSK;
146
147 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
148 keyconf->hw_key_idx = keyconf->keyidx;
149 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 150
b481de9c 151 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
152 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
153 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
154 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
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155 keyconf->keylen);
156
c587de0b 157 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 158 keyconf->keylen);
6e21f15c 159
c587de0b 160 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 161 == STA_KEY_FLG_NO_ENC)
c587de0b 162 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
163 iwl_get_free_ucode_key_index(priv);
164 /* else, we are overriding an existing key => no need to allocated room
165 * in uCode. */
166
c587de0b 167 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
168 "no space for a new key");
169
c587de0b
TW
170 priv->stations[sta_id].sta.key.key_flags = key_flags;
171 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
172 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 173
6e21f15c
AK
174 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
175
c587de0b 176 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 177
b481de9c
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178 spin_unlock_irqrestore(&priv->sta_lock, flags);
179
6e21f15c
AK
180 return ret;
181}
182
183static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
184 struct ieee80211_key_conf *keyconf,
185 u8 sta_id)
186{
187 return -EOPNOTSUPP;
188}
189
190static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
191 struct ieee80211_key_conf *keyconf,
192 u8 sta_id)
193{
194 return -EOPNOTSUPP;
b481de9c
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195}
196
4a8a4322 197static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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198{
199 unsigned long flags;
200
201 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
202 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
203 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 204 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
205 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
206 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
207 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
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208 spin_unlock_irqrestore(&priv->sta_lock, flags);
209
e1623446 210 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 211 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
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212 return 0;
213}
214
fa11d525 215static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
216 struct ieee80211_key_conf *keyconf, u8 sta_id)
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->alg) {
223 case ALG_CCMP:
224 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
225 break;
226 case ALG_TKIP:
227 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
228 break;
229 case ALG_WEP:
230 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
231 break;
232 default:
1e680233 233 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
234 ret = -EINVAL;
235 }
236
237 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
238 keyconf->alg, keyconf->keylen, keyconf->keyidx,
239 sta_id, ret);
240
241 return ret;
242}
243
244static int iwl3945_remove_static_key(struct iwl_priv *priv)
245{
246 int ret = -EOPNOTSUPP;
247
248 return ret;
249}
250
251static int iwl3945_set_static_key(struct iwl_priv *priv,
252 struct ieee80211_key_conf *key)
253{
254 if (key->alg == ALG_WEP)
255 return -EOPNOTSUPP;
256
257 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
258 return -EINVAL;
259}
260
4a8a4322 261static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
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262{
263 struct list_head *element;
264
e1623446 265 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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266 priv->frames_count);
267
268 while (!list_empty(&priv->free_frames)) {
269 element = priv->free_frames.next;
270 list_del(element);
bb8c093b 271 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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272 priv->frames_count--;
273 }
274
275 if (priv->frames_count) {
39aadf8c 276 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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277 priv->frames_count);
278 priv->frames_count = 0;
279 }
280}
281
4a8a4322 282static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 283{
bb8c093b 284 struct iwl3945_frame *frame;
b481de9c
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285 struct list_head *element;
286 if (list_empty(&priv->free_frames)) {
287 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
288 if (!frame) {
15b1687c 289 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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290 return NULL;
291 }
292
293 priv->frames_count++;
294 return frame;
295 }
296
297 element = priv->free_frames.next;
298 list_del(element);
bb8c093b 299 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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300}
301
4a8a4322 302static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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303{
304 memset(frame, 0, sizeof(*frame));
305 list_add(&frame->list, &priv->free_frames);
306}
307
4a8a4322 308unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 309 struct ieee80211_hdr *hdr,
73ec1cc2 310 int left)
b481de9c
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311{
312
8ccde88a 313 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
314 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
315 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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316 return 0;
317
318 if (priv->ibss_beacon->len > left)
319 return 0;
320
321 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
322
323 return priv->ibss_beacon->len;
324}
325
4a8a4322 326static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 327{
bb8c093b 328 struct iwl3945_frame *frame;
b481de9c
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329 unsigned int frame_size;
330 int rc;
331 u8 rate;
332
bb8c093b 333 frame = iwl3945_get_free_frame(priv);
b481de9c
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334
335 if (!frame) {
15b1687c 336 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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337 "command.\n");
338 return -ENOMEM;
339 }
340
8ccde88a 341 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 342
bb8c093b 343 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 344
518099a8 345 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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346 &frame->u.cmd[0]);
347
bb8c093b 348 iwl3945_free_frame(priv, frame);
b481de9c
ZY
349
350 return rc;
351}
352
4a8a4322 353static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 354{
3832ec9d 355 if (priv->shared_virt)
b481de9c 356 pci_free_consistent(priv->pci_dev,
bb8c093b 357 sizeof(struct iwl3945_shared),
3832ec9d
AK
358 priv->shared_virt,
359 priv->shared_phys);
b481de9c
ZY
360}
361
4a8a4322 362static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 363 struct ieee80211_tx_info *info,
c2acea8e 364 struct iwl_device_cmd *cmd,
b481de9c 365 struct sk_buff *skb_frag,
6e21f15c 366 int sta_id)
b481de9c 367{
9744c91f 368 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 369 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
370
371 switch (keyinfo->alg) {
372 case ALG_CCMP:
9744c91f
AK
373 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
374 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
e1623446 375 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
376 break;
377
378 case ALG_TKIP:
b481de9c
ZY
379 break;
380
381 case ALG_WEP:
9744c91f 382 tx_cmd->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 383 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
384
385 if (keyinfo->keylen == 13)
9744c91f 386 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 387
9744c91f 388 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 389
e1623446 390 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 391 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
392 break;
393
b481de9c 394 default:
978785a3 395 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
396 break;
397 }
398}
399
400/*
401 * handle build REPLY_TX command notification.
402 */
4a8a4322 403static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 404 struct iwl_device_cmd *cmd,
e039fa4a 405 struct ieee80211_tx_info *info,
e52119c5 406 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 407{
9744c91f
AK
408 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
409 __le32 tx_flags = tx_cmd->tx_flags;
fd7c8a40 410 __le16 fc = hdr->frame_control;
b481de9c 411
9744c91f 412 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 413 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 414 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 415 if (ieee80211_is_mgmt(fc))
b481de9c 416 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 417 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
418 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
419 tx_flags |= TX_CMD_FLG_TSF_MSK;
420 } else {
421 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
422 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
423 }
424
9744c91f 425 tx_cmd->sta_id = std_id;
8b7b1e05 426 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
427 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
428
fd7c8a40
HH
429 if (ieee80211_is_data_qos(fc)) {
430 u8 *qc = ieee80211_get_qos_ctl(hdr);
9744c91f 431 tx_cmd->tid_tspec = qc[0] & 0xf;
b481de9c 432 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 433 } else {
b481de9c 434 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 435 }
b481de9c 436
37dc70fe 437 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
b481de9c
ZY
438
439 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
440 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
441
442 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
443 if (ieee80211_is_mgmt(fc)) {
444 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
9744c91f 445 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 446 else
9744c91f 447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 448 } else {
9744c91f 449 tx_cmd->timeout.pm_frame_timeout = 0;
ab53d8af 450 }
b481de9c 451
9744c91f
AK
452 tx_cmd->driver_txop = 0;
453 tx_cmd->tx_flags = tx_flags;
454 tx_cmd->next_frame_len = 0;
b481de9c
ZY
455}
456
b481de9c
ZY
457/*
458 * start REPLY_TX command process
459 */
4a8a4322 460static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
461{
462 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 463 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9744c91f 464 struct iwl3945_tx_cmd *tx_cmd;
188cf6c7 465 struct iwl_tx_queue *txq = NULL;
d20b3c65 466 struct iwl_queue *q = NULL;
c2acea8e
JB
467 struct iwl_device_cmd *out_cmd;
468 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
469 dma_addr_t phys_addr;
470 dma_addr_t txcmd_phys;
e52119c5 471 int txq_id = skb_get_queue_mapping(skb);
df833b1d 472 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
473 u8 id;
474 u8 unicast;
b481de9c 475 u8 sta_id;
54dbb525 476 u8 tid = 0;
b481de9c 477 u16 seq_number = 0;
fd7c8a40 478 __le16 fc;
b481de9c 479 u8 wait_write_ptr = 0;
54dbb525 480 u8 *qc = NULL;
b481de9c
ZY
481 unsigned long flags;
482 int rc;
483
484 spin_lock_irqsave(&priv->lock, flags);
775a6e27 485 if (iwl_is_rfkill(priv)) {
e1623446 486 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
487 goto drop_unlock;
488 }
489
e039fa4a 490 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 491 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
492 goto drop_unlock;
493 }
494
495 unicast = !is_multicast_ether_addr(hdr->addr1);
496 id = 0;
497
fd7c8a40 498 fc = hdr->frame_control;
b481de9c 499
d08853a3 500#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 501 if (ieee80211_is_auth(fc))
e1623446 502 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 503 else if (ieee80211_is_assoc_req(fc))
e1623446 504 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 505 else if (ieee80211_is_reassoc_req(fc))
e1623446 506 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
507#endif
508
aa065263 509 /* drop all non-injected data frame if we are not associated */
914233d6 510 if (ieee80211_is_data(fc) &&
aa065263 511 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
8ccde88a 512 (!iwl_is_associated(priv) ||
05c914fe 513 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 514 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
515 goto drop_unlock;
516 }
517
518 spin_unlock_irqrestore(&priv->lock, flags);
519
7294ec95 520 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
521
522 /* Find (or create) index into station table for destination station */
aa065263
GS
523 if (info->flags & IEEE80211_TX_CTL_INJECTED)
524 sta_id = priv->hw_params.bcast_sta_id;
525 else
526 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 527 if (sta_id == IWL_INVALID_STATION) {
e1623446 528 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 529 hdr->addr1);
b481de9c
ZY
530 goto drop;
531 }
532
e1623446 533 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 534
fd7c8a40
HH
535 if (ieee80211_is_data_qos(fc)) {
536 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 537 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
538 if (unlikely(tid >= MAX_TID_COUNT))
539 goto drop;
c587de0b 540 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
541 IEEE80211_SCTL_SEQ;
542 hdr->seq_ctrl = cpu_to_le16(seq_number) |
543 (hdr->seq_ctrl &
c1b4aa3f 544 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
545 seq_number += 0x10;
546 }
6440adb5
BC
547
548 /* Descriptor for chosen Tx queue */
188cf6c7 549 txq = &priv->txq[txq_id];
b481de9c
ZY
550 q = &txq->q;
551
552 spin_lock_irqsave(&priv->lock, flags);
553
fc4b6853 554 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 555
6440adb5 556 /* Set up driver data for this TFD */
dbb6654c 557 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 558 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
559
560 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 561 out_cmd = txq->cmd[idx];
c2acea8e 562 out_meta = &txq->meta[idx];
9744c91f 563 tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 564 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
9744c91f 565 memset(tx_cmd, 0, sizeof(*tx_cmd));
6440adb5
BC
566
567 /*
568 * Set up the Tx-command (not MAC!) header.
569 * Store the chosen Tx queue and TFD index within the sequence field;
570 * after Tx, uCode's Tx response will return this value so driver can
571 * locate the frame within the tx queue and do post-tx processing.
572 */
b481de9c
ZY
573 out_cmd->hdr.cmd = REPLY_TX;
574 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 575 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
576
577 /* Copy MAC header from skb into command buffer */
9744c91f 578 memcpy(tx_cmd->hdr, hdr, hdr_len);
b481de9c 579
df833b1d
RC
580
581 if (info->control.hw_key)
582 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
583
584 /* TODO need this for burst mode later on */
585 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
586
587 /* set is_hcca to 0; it probably will never be implemented */
588 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
589
590 /* Total # bytes to be transmitted */
591 len = (u16)skb->len;
9744c91f 592 tx_cmd->len = cpu_to_le16(len);
df833b1d 593
20594eb0 594 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 595 iwl_update_stats(priv, true, fc, len);
9744c91f
AK
596 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
597 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
df833b1d
RC
598
599 if (!ieee80211_has_morefrags(hdr->frame_control)) {
600 txq->need_update = 1;
601 if (qc)
c587de0b 602 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
603 } else {
604 wait_write_ptr = 1;
605 txq->need_update = 0;
606 }
607
608 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
609 le16_to_cpu(out_cmd->hdr.sequence));
9744c91f
AK
610 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
611 iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
612 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
df833b1d
RC
613 ieee80211_hdrlen(fc));
614
6440adb5
BC
615 /*
616 * Use the first empty entry in this queue's command buffer array
617 * to contain the Tx command and MAC header concatenated together
618 * (payload data will be in another buffer).
619 * Size of this varies, due to varying MAC header length.
620 * If end is not dword aligned, we'll have 2 extra bytes at the end
621 * of the MAC header (device reads on dword boundaries).
622 * We'll tell device about this padding later.
623 */
3832ec9d 624 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 625 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
626
627 len_org = len;
628 len = (len + 3) & ~3;
629
630 if (len_org != len)
631 len_org = 1;
632 else
633 len_org = 0;
634
6440adb5
BC
635 /* Physical address of this Tx command's header (not MAC header!),
636 * within command buffer array. */
df833b1d
RC
637 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
638 len, PCI_DMA_TODEVICE);
639 /* we do not map meta data ... so we can safely access address to
640 * provide to unmap command*/
c2acea8e
JB
641 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
642 pci_unmap_len_set(out_meta, len, len);
b481de9c 643
6440adb5
BC
644 /* Add buffer containing Tx command and MAC(!) header to TFD's
645 * first entry */
7aaa1d79
SO
646 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
647 txcmd_phys, len, 1, 0);
b481de9c 648
b481de9c 649
6440adb5
BC
650 /* Set up TFD's 2nd entry to point directly to remainder of skb,
651 * if any (802.11 null frames have no payload). */
b481de9c
ZY
652 len = skb->len - hdr_len;
653 if (len) {
654 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
655 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
656 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
657 phys_addr, len,
658 0, U32_PAD(len));
b481de9c
ZY
659 }
660
b481de9c 661
6440adb5 662 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 663 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
4f3602c8 664 rc = iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
665 spin_unlock_irqrestore(&priv->lock, flags);
666
667 if (rc)
668 return rc;
669
d20b3c65 670 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
671 && priv->mac80211_registered) {
672 if (wait_write_ptr) {
673 spin_lock_irqsave(&priv->lock, flags);
674 txq->need_update = 1;
4f3602c8 675 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
676 spin_unlock_irqrestore(&priv->lock, flags);
677 }
678
e4e72fb4 679 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
680 }
681
682 return 0;
683
684drop_unlock:
685 spin_unlock_irqrestore(&priv->lock, flags);
686drop:
687 return -1;
688}
689
c8b0e6e1 690#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
691
692#include "iwl-spectrum.h"
693
694#define BEACON_TIME_MASK_LOW 0x00FFFFFF
695#define BEACON_TIME_MASK_HIGH 0xFF000000
696#define TIME_UNIT 1024
697
698/*
699 * extended beacon time format
700 * time in usec will be changed into a 32-bit value in 8:24 format
701 * the high 1 byte is the beacon counts
702 * the lower 3 bytes is the time in usec within one beacon interval
703 */
704
bb8c093b 705static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
706{
707 u32 quot;
708 u32 rem;
709 u32 interval = beacon_interval * 1024;
710
711 if (!interval || !usec)
712 return 0;
713
714 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
715 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
716
717 return (quot << 24) + rem;
718}
719
720/* base is usually what we get from ucode with each received frame,
721 * the same as HW timer counter counting down
722 */
723
bb8c093b 724static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
725{
726 u32 base_low = base & BEACON_TIME_MASK_LOW;
727 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
728 u32 interval = beacon_interval * TIME_UNIT;
729 u32 res = (base & BEACON_TIME_MASK_HIGH) +
730 (addon & BEACON_TIME_MASK_HIGH);
731
732 if (base_low > addon_low)
733 res += base_low - addon_low;
734 else if (base_low < addon_low) {
735 res += interval + base_low - addon_low;
736 res += (1 << 24);
737 } else
738 res += (1 << 24);
739
740 return cpu_to_le32(res);
741}
742
4a8a4322 743static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
744 struct ieee80211_measurement_params *params,
745 u8 type)
746{
600c0e11 747 struct iwl_spectrum_cmd spectrum;
2f301227 748 struct iwl_rx_packet *pkt;
c2d79b48 749 struct iwl_host_cmd cmd = {
b481de9c
ZY
750 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
751 .data = (void *)&spectrum,
c2acea8e 752 .flags = CMD_WANT_SKB,
b481de9c
ZY
753 };
754 u32 add_time = le64_to_cpu(params->start_time);
755 int rc;
756 int spectrum_resp_status;
757 int duration = le16_to_cpu(params->duration);
758
8ccde88a 759 if (iwl_is_associated(priv))
b481de9c 760 add_time =
bb8c093b 761 iwl3945_usecs_to_beacons(
b481de9c
ZY
762 le64_to_cpu(params->start_time) - priv->last_tsf,
763 le16_to_cpu(priv->rxon_timing.beacon_interval));
764
765 memset(&spectrum, 0, sizeof(spectrum));
766
767 spectrum.channel_count = cpu_to_le16(1);
768 spectrum.flags =
769 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
770 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
771 cmd.len = sizeof(spectrum);
772 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
773
8ccde88a 774 if (iwl_is_associated(priv))
b481de9c 775 spectrum.start_time =
bb8c093b 776 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
777 add_time,
778 le16_to_cpu(priv->rxon_timing.beacon_interval));
779 else
780 spectrum.start_time = 0;
781
782 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
783 spectrum.channels[0].channel = params->channel;
784 spectrum.channels[0].type = type;
8ccde88a 785 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
786 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
787 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
788
518099a8 789 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
790 if (rc)
791 return rc;
792
2f301227
ZY
793 pkt = (struct iwl_rx_packet *)cmd.reply_page;
794 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 795 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
796 rc = -EIO;
797 }
798
2f301227 799 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
b481de9c
ZY
800 switch (spectrum_resp_status) {
801 case 0: /* Command will be handled */
2f301227 802 if (pkt->u.spectrum.id != 0xff) {
e1623446 803 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
2f301227 804 pkt->u.spectrum.id);
b481de9c
ZY
805 priv->measurement_status &= ~MEASUREMENT_READY;
806 }
807 priv->measurement_status |= MEASUREMENT_ACTIVE;
808 rc = 0;
809 break;
810
811 case 1: /* Command will not be handled */
812 rc = -EAGAIN;
813 break;
814 }
815
2f301227 816 free_pages(cmd.reply_page, priv->hw_params.rx_page_order);
b481de9c
ZY
817
818 return rc;
819}
820#endif
821
4a8a4322 822static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 823 struct iwl_rx_mem_buffer *rxb)
b481de9c 824{
2f301227 825 struct iwl_rx_packet *pkt = rxb_addr(rxb);
3d24a9f7 826 struct iwl_alive_resp *palive;
b481de9c
ZY
827 struct delayed_work *pwork;
828
829 palive = &pkt->u.alive_frame;
830
e1623446 831 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
832 "0x%01X 0x%01X\n",
833 palive->is_valid, palive->ver_type,
834 palive->ver_subtype);
835
836 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 837 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
838 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
839 sizeof(struct iwl_alive_resp));
b481de9c
ZY
840 pwork = &priv->init_alive_start;
841 } else {
e1623446 842 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 843 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 844 sizeof(struct iwl_alive_resp));
b481de9c 845 pwork = &priv->alive_start;
bb8c093b 846 iwl3945_disable_events(priv);
b481de9c
ZY
847 }
848
849 /* We delay the ALIVE response by 5ms to
850 * give the HW RF Kill time to activate... */
851 if (palive->is_valid == UCODE_VALID_OK)
852 queue_delayed_work(priv->workqueue, pwork,
853 msecs_to_jiffies(5));
854 else
39aadf8c 855 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
856}
857
4a8a4322 858static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 859 struct iwl_rx_mem_buffer *rxb)
b481de9c 860{
c7e035a9 861#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 862 struct iwl_rx_packet *pkt = rxb_addr(rxb);
c7e035a9 863#endif
b481de9c 864
e1623446 865 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
866 return;
867}
868
bb8c093b 869static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 870{
4a8a4322
AK
871 struct iwl_priv *priv =
872 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
873 struct sk_buff *beacon;
874
875 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 876 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
877
878 if (!beacon) {
15b1687c 879 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
880 return;
881 }
882
883 mutex_lock(&priv->mutex);
884 /* new beacon skb is allocated every time; dispose previous.*/
885 if (priv->ibss_beacon)
886 dev_kfree_skb(priv->ibss_beacon);
887
888 priv->ibss_beacon = beacon;
889 mutex_unlock(&priv->mutex);
890
bb8c093b 891 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
892}
893
4a8a4322 894static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 895 struct iwl_rx_mem_buffer *rxb)
b481de9c 896{
d08853a3 897#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 898 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b 899 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
900 u8 rate = beacon->beacon_notify_hdr.rate;
901
e1623446 902 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
903 "tsf %d %d rate %d\n",
904 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
905 beacon->beacon_notify_hdr.failure_frame,
906 le32_to_cpu(beacon->ibss_mgr_status),
907 le32_to_cpu(beacon->high_tsf),
908 le32_to_cpu(beacon->low_tsf), rate);
909#endif
910
05c914fe 911 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
912 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
913 queue_work(priv->workqueue, &priv->beacon_update);
914}
915
b481de9c
ZY
916/* Handle notification from uCode that card's power state is changing
917 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 918static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 919 struct iwl_rx_mem_buffer *rxb)
b481de9c 920{
2f301227 921 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
922 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
923 unsigned long status = priv->status;
924
4c423a2b 925 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
926 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
927 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
928
5d49f498 929 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
930 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
931
932 if (flags & HW_CARD_DISABLED)
933 set_bit(STATUS_RF_KILL_HW, &priv->status);
934 else
935 clear_bit(STATUS_RF_KILL_HW, &priv->status);
936
937
af0053d6 938 iwl_scan_cancel(priv);
b481de9c
ZY
939
940 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
941 test_bit(STATUS_RF_KILL_HW, &priv->status)))
942 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
943 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
944 else
945 wake_up_interruptible(&priv->wait_command_queue);
946}
947
948/**
bb8c093b 949 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
950 *
951 * Setup the RX handlers for each of the reply types sent from the uCode
952 * to the host.
953 *
954 * This function chains into the hardware specific files for them to setup
955 * any hardware specific handlers as well.
956 */
4a8a4322 957static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 958{
bb8c093b
CH
959 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
960 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 961 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 962 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
030f05ed 963 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 964 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 965 iwl_rx_pm_debug_statistics_notif;
bb8c093b 966 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 967
9fbab516
BC
968 /*
969 * The same handler is used for both the REPLY to a discrete
970 * statistics request from the host as well as for the periodic
971 * statistics notifications (after received beacons) from the uCode.
b481de9c 972 */
bb8c093b
CH
973 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
974 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 975
261b9c33 976 iwl_setup_spectrum_handlers(priv);
cade0eb2 977 iwl_setup_rx_scan_handlers(priv);
bb8c093b 978 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 979
9fbab516 980 /* Set up hardware specific Rx handlers */
bb8c093b 981 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
982}
983
b481de9c
ZY
984/************************** RX-FUNCTIONS ****************************/
985/*
986 * Rx theory of operation
987 *
988 * The host allocates 32 DMA target addresses and passes the host address
989 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
990 * 0 to 31
991 *
992 * Rx Queue Indexes
993 * The host/firmware share two index registers for managing the Rx buffers.
994 *
995 * The READ index maps to the first position that the firmware may be writing
996 * to -- the driver can read up to (but not including) this position and get
997 * good data.
998 * The READ index is managed by the firmware once the card is enabled.
999 *
1000 * The WRITE index maps to the last position the driver has read from -- the
1001 * position preceding WRITE is the last slot the firmware can place a packet.
1002 *
1003 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
1004 * WRITE = READ.
1005 *
9fbab516 1006 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1007 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1008 *
9fbab516 1009 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1010 * and fire the RX interrupt. The driver can then query the READ index and
1011 * process as many packets as possible, moving the WRITE index forward as it
1012 * resets the Rx queue buffers with new memory.
1013 *
1014 * The management in the driver is as follows:
1015 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1016 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1017 * to replenish the iwl->rxq->rx_free.
bb8c093b 1018 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1019 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1020 * 'processed' and 'read' driver indexes as well)
1021 * + A received packet is processed and handed to the kernel network stack,
1022 * detached from the iwl->rxq. The driver 'processed' index is updated.
1023 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1024 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1025 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1026 * were enough free buffers and RX_STALLED is set it is cleared.
1027 *
1028 *
1029 * Driver sequence:
1030 *
9fbab516 1031 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1032 * iwl3945_rx_queue_restock
9fbab516 1033 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1034 * queue, updates firmware pointers, and updates
1035 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1036 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1037 *
1038 * -- enable interrupts --
6100b588 1039 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1040 * READ INDEX, detaching the SKB from the pool.
1041 * Moves the packet buffer from queue to rx_used.
bb8c093b 1042 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1043 * slots.
1044 * ...
1045 *
1046 */
1047
b481de9c 1048/**
9fbab516 1049 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1050 */
4a8a4322 1051static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1052 dma_addr_t dma_addr)
1053{
1054 return cpu_to_le32((u32)dma_addr);
1055}
1056
1057/**
bb8c093b 1058 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1059 *
9fbab516 1060 * If there are slots in the RX queue that need to be restocked,
b481de9c 1061 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1062 * as we can, pulling from rx_free.
b481de9c
ZY
1063 *
1064 * This moves the 'write' index forward to catch up with 'processed', and
1065 * also updates the memory address in the firmware to reference the new
1066 * target buffer.
1067 */
4a8a4322 1068static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1069{
cc2f362c 1070 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1071 struct list_head *element;
6100b588 1072 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
1073 unsigned long flags;
1074 int write, rc;
1075
1076 spin_lock_irqsave(&rxq->lock, flags);
1077 write = rxq->write & ~0x7;
37d68317 1078 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1079 /* Get next free Rx buffer, remove from free list */
b481de9c 1080 element = rxq->rx_free.next;
6100b588 1081 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1082 list_del(element);
6440adb5
BC
1083
1084 /* Point to Rx buffer via next RBD in circular buffer */
2f301227 1085 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
b481de9c
ZY
1086 rxq->queue[rxq->write] = rxb;
1087 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1088 rxq->free_count--;
1089 }
1090 spin_unlock_irqrestore(&rxq->lock, flags);
1091 /* If the pre-allocated buffer pool is dropping low, schedule to
1092 * refill it */
1093 if (rxq->free_count <= RX_LOW_WATERMARK)
1094 queue_work(priv->workqueue, &priv->rx_replenish);
1095
1096
6440adb5
BC
1097 /* If we've added more space for the firmware to place data, tell it.
1098 * Increment device's write pointer in multiples of 8. */
d14d4440 1099 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1100 || (abs(rxq->write - rxq->read) > 7)) {
1101 spin_lock_irqsave(&rxq->lock, flags);
1102 rxq->need_update = 1;
1103 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 1104 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
1105 if (rc)
1106 return rc;
1107 }
1108
1109 return 0;
1110}
1111
1112/**
bb8c093b 1113 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1114 *
1115 * When moving to rx_free an SKB is allocated for the slot.
1116 *
bb8c093b 1117 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1118 * This is called as a scheduled work item (except for during initialization)
b481de9c 1119 */
d14d4440 1120static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1121{
cc2f362c 1122 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1123 struct list_head *element;
6100b588 1124 struct iwl_rx_mem_buffer *rxb;
2f301227 1125 struct page *page;
b481de9c 1126 unsigned long flags;
29b1b268 1127 gfp_t gfp_mask = priority;
72240498
AK
1128
1129 while (1) {
1130 spin_lock_irqsave(&rxq->lock, flags);
1131
1132 if (list_empty(&rxq->rx_used)) {
1133 spin_unlock_irqrestore(&rxq->lock, flags);
1134 return;
1135 }
72240498 1136 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1137
f82a924c 1138 if (rxq->free_count > RX_LOW_WATERMARK)
29b1b268 1139 gfp_mask |= __GFP_NOWARN;
2f301227
ZY
1140
1141 if (priv->hw_params.rx_page_order > 0)
29b1b268 1142 gfp_mask |= __GFP_COMP;
2f301227 1143
6440adb5 1144 /* Alloc a new receive buffer */
29b1b268 1145 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
2f301227 1146 if (!page) {
b481de9c 1147 if (net_ratelimit())
f82a924c
RC
1148 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1149 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1150 net_ratelimit())
1151 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1152 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1153 rxq->free_count);
b481de9c
ZY
1154 /* We don't reschedule replenish work here -- we will
1155 * call the restock method and if it still needs
1156 * more buffers it will schedule replenish */
1157 break;
1158 }
12342c47 1159
de0bd508
RC
1160 spin_lock_irqsave(&rxq->lock, flags);
1161 if (list_empty(&rxq->rx_used)) {
1162 spin_unlock_irqrestore(&rxq->lock, flags);
2f301227 1163 __free_pages(page, priv->hw_params.rx_page_order);
de0bd508
RC
1164 return;
1165 }
1166 element = rxq->rx_used.next;
1167 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1168 list_del(element);
1169 spin_unlock_irqrestore(&rxq->lock, flags);
1170
2f301227 1171 rxb->page = page;
6440adb5 1172 /* Get physical address of RB/SKB */
2f301227
ZY
1173 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
1174 PAGE_SIZE << priv->hw_params.rx_page_order,
1175 PCI_DMA_FROMDEVICE);
72240498
AK
1176
1177 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1178
b481de9c
ZY
1179 list_add_tail(&rxb->list, &rxq->rx_free);
1180 rxq->free_count++;
2f301227
ZY
1181 priv->alloc_rxb_page++;
1182
72240498 1183 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1184 }
5c0eef96
MA
1185}
1186
df833b1d
RC
1187void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1188{
1189 unsigned long flags;
1190 int i;
1191 spin_lock_irqsave(&rxq->lock, flags);
1192 INIT_LIST_HEAD(&rxq->rx_free);
1193 INIT_LIST_HEAD(&rxq->rx_used);
1194 /* Fill the rx_used queue with _all_ of the Rx buffers */
1195 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1196 /* In the reset function, these buffers may have been allocated
1197 * to an SKB, so we need to unmap and free potential storage */
2f301227
ZY
1198 if (rxq->pool[i].page != NULL) {
1199 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1200 PAGE_SIZE << priv->hw_params.rx_page_order,
1201 PCI_DMA_FROMDEVICE);
1202 priv->alloc_rxb_page--;
1203 __free_pages(rxq->pool[i].page,
1204 priv->hw_params.rx_page_order);
1205 rxq->pool[i].page = NULL;
df833b1d
RC
1206 }
1207 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1208 }
1209
1210 /* Set us so that we have processed and used all buffers, but have
1211 * not restocked the Rx queue with fresh buffers */
1212 rxq->read = rxq->write = 0;
d14d4440 1213 rxq->write_actual = 0;
2f301227 1214 rxq->free_count = 0;
df833b1d
RC
1215 spin_unlock_irqrestore(&rxq->lock, flags);
1216}
df833b1d 1217
5c0eef96
MA
1218void iwl3945_rx_replenish(void *data)
1219{
4a8a4322 1220 struct iwl_priv *priv = data;
5c0eef96
MA
1221 unsigned long flags;
1222
d14d4440 1223 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1224
1225 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1226 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1227 spin_unlock_irqrestore(&priv->lock, flags);
1228}
1229
d14d4440
AK
1230static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1231{
1232 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1233
1234 iwl3945_rx_queue_restock(priv);
1235}
1236
1237
df833b1d
RC
1238/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1239 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1240 * This free routine walks the list of POOL entries and if SKB is set to
1241 * non NULL it is unmapped and freed
1242 */
1243static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1244{
1245 int i;
1246 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
2f301227
ZY
1247 if (rxq->pool[i].page != NULL) {
1248 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1249 PAGE_SIZE << priv->hw_params.rx_page_order,
1250 PCI_DMA_FROMDEVICE);
1251 __free_pages(rxq->pool[i].page,
1252 priv->hw_params.rx_page_order);
1253 rxq->pool[i].page = NULL;
1254 priv->alloc_rxb_page--;
df833b1d
RC
1255 }
1256 }
1257
1258 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1259 rxq->dma_addr);
1260 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1261 rxq->rb_stts, rxq->rb_stts_dma);
1262 rxq->bd = NULL;
1263 rxq->rb_stts = NULL;
1264}
df833b1d
RC
1265
1266
b481de9c
ZY
1267/* Convert linear signal-to-noise ratio into dB */
1268static u8 ratio2dB[100] = {
1269/* 0 1 2 3 4 5 6 7 8 9 */
1270 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1271 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1272 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1273 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1274 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1275 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1276 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1277 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1278 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1279 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1280};
1281
1282/* Calculates a relative dB value from a ratio of linear
1283 * (i.e. not dB) signal levels.
1284 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1285int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1286{
221c80cf
AB
1287 /* 1000:1 or higher just report as 60 dB */
1288 if (sig_ratio >= 1000)
b481de9c
ZY
1289 return 60;
1290
221c80cf 1291 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1292 * add 20 dB to make up for divide by 10 */
221c80cf 1293 if (sig_ratio >= 100)
3ac7f146 1294 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1295
1296 /* We shouldn't see this */
1297 if (sig_ratio < 1)
1298 return 0;
1299
1300 /* Use table for ratios 1:1 - 99:1 */
1301 return (int)ratio2dB[sig_ratio];
1302}
1303
1304#define PERFECT_RSSI (-20) /* dBm */
1305#define WORST_RSSI (-95) /* dBm */
1306#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1307
1308/* Calculate an indication of rx signal quality (a percentage, not dBm!).
1309 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
1310 * about formulas used below. */
bb8c093b 1311int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
1312{
1313 int sig_qual;
1314 int degradation = PERFECT_RSSI - rssi_dbm;
1315
1316 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
1317 * as indicator; formula is (signal dbm - noise dbm).
1318 * SNR at or above 40 is a great signal (100%).
1319 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
1320 * Weakest usable signal is usually 10 - 15 dB SNR. */
1321 if (noise_dbm) {
1322 if (rssi_dbm - noise_dbm >= 40)
1323 return 100;
1324 else if (rssi_dbm < noise_dbm)
1325 return 0;
1326 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1327
1328 /* Else use just the signal level.
1329 * This formula is a least squares fit of data points collected and
1330 * compared with a reference system that had a percentage (%) display
1331 * for signal quality. */
1332 } else
1333 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1334 (15 * RSSI_RANGE + 62 * degradation)) /
1335 (RSSI_RANGE * RSSI_RANGE);
1336
1337 if (sig_qual > 100)
1338 sig_qual = 100;
1339 else if (sig_qual < 1)
1340 sig_qual = 0;
1341
1342 return sig_qual;
1343}
1344
1345/**
9fbab516 1346 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1347 *
1348 * Uses the priv->rx_handlers callback function array to invoke
1349 * the appropriate handlers, including command responses,
1350 * frame-received notifications, and other notifications.
1351 */
4a8a4322 1352static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1353{
6100b588 1354 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1355 struct iwl_rx_packet *pkt;
cc2f362c 1356 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1357 u32 r, i;
1358 int reclaim;
1359 unsigned long flags;
5c0eef96 1360 u8 fill_rx = 0;
d68ab680 1361 u32 count = 8;
d14d4440 1362 int total_empty = 0;
b481de9c 1363
6440adb5
BC
1364 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1365 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1366 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1367 i = rxq->read;
1368
d14d4440 1369 /* calculate total frames need to be restock after handling RX */
7300515d 1370 total_empty = r - rxq->write_actual;
d14d4440
AK
1371 if (total_empty < 0)
1372 total_empty += RX_QUEUE_SIZE;
1373
1374 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1375 fill_rx = 1;
b481de9c
ZY
1376 /* Rx interrupt, but nothing sent from uCode */
1377 if (i == r)
af472a95 1378 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1379
1380 while (i != r) {
1381 rxb = rxq->queue[i];
1382
9fbab516 1383 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1384 * then a bug has been introduced in the queue refilling
1385 * routines -- catch it here */
1386 BUG_ON(rxb == NULL);
1387
1388 rxq->queue[i] = NULL;
1389
2f301227
ZY
1390 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1391 PAGE_SIZE << priv->hw_params.rx_page_order,
1392 PCI_DMA_FROMDEVICE);
1393 pkt = rxb_addr(rxb);
b481de9c 1394
be1a71a1
JB
1395 trace_iwlwifi_dev_rx(priv, pkt,
1396 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
1397
b481de9c
ZY
1398 /* Reclaim a command buffer only if this packet is a response
1399 * to a (driver-originated) command.
1400 * If the packet (e.g. Rx frame) originated from uCode,
1401 * there is no command buffer to reclaim.
1402 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1403 * but apparently a few don't get set; catch them here. */
1404 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1405 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1406 (pkt->hdr.cmd != REPLY_TX);
1407
1408 /* Based on type of command response or notification,
1409 * handle those that need handling via function in
bb8c093b 1410 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1411 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1412 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c 1413 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
86ddbf62 1414 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1415 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
1416 } else {
1417 /* No handling needed */
2f301227
ZY
1418 IWL_DEBUG_RX(priv,
1419 "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1420 r, i, get_cmd_string(pkt->hdr.cmd),
1421 pkt->hdr.cmd);
1422 }
1423
29b1b268
ZY
1424 /*
1425 * XXX: After here, we should always check rxb->page
1426 * against NULL before touching it or its virtual
1427 * memory (pkt). Because some rx_handler might have
1428 * already taken or freed the pages.
1429 */
1430
b481de9c 1431 if (reclaim) {
2f301227
ZY
1432 /* Invoke any callbacks, transfer the buffer to caller,
1433 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1434 * as we reclaim the driver command queue */
29b1b268 1435 if (rxb->page)
732587ab 1436 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1437 else
39aadf8c 1438 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1439 }
1440
7300515d
ZY
1441 /* Reuse the page if possible. For notification packets and
1442 * SKBs that fail to Rx correctly, add them back into the
1443 * rx_free list for reuse later. */
1444 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1445 if (rxb->page != NULL) {
7300515d
ZY
1446 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1447 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1448 PCI_DMA_FROMDEVICE);
1449 list_add_tail(&rxb->list, &rxq->rx_free);
1450 rxq->free_count++;
1451 } else
1452 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1453
b481de9c 1454 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1455
b481de9c 1456 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1457 /* If there are a lot of unused frames,
1458 * restock the Rx queue so ucode won't assert. */
1459 if (fill_rx) {
1460 count++;
1461 if (count >= 8) {
7300515d 1462 rxq->read = i;
d14d4440 1463 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1464 count = 0;
1465 }
1466 }
b481de9c
ZY
1467 }
1468
1469 /* Backtrack one entry */
7300515d 1470 rxq->read = i;
d14d4440
AK
1471 if (fill_rx)
1472 iwl3945_rx_replenish_now(priv);
1473 else
1474 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1475}
1476
0359facc 1477/* call this function to flush any scheduled tasklet */
4a8a4322 1478static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1479{
a96a27f9 1480 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1481 synchronize_irq(priv->pci_dev->irq);
1482 tasklet_kill(&priv->irq_tasklet);
1483}
1484
b7a79404 1485#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1486static const char *desc_lookup(int i)
1487{
1488 switch (i) {
1489 case 1:
1490 return "FAIL";
1491 case 2:
1492 return "BAD_PARAM";
1493 case 3:
1494 return "BAD_CHECKSUM";
1495 case 4:
1496 return "NMI_INTERRUPT";
1497 case 5:
1498 return "SYSASSERT";
1499 case 6:
1500 return "FATAL_ERROR";
1501 }
1502
1503 return "UNKNOWN";
1504}
1505
1506#define ERROR_START_OFFSET (1 * sizeof(u32))
1507#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1508
b7a79404 1509void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1510{
1511 u32 i;
1512 u32 desc, time, count, base, data1;
1513 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1514
1515 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1516
bb8c093b 1517 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1518 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1519 return;
1520 }
1521
b481de9c 1522
5d49f498 1523 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1524
1525 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1526 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1527 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1528 priv->status, count);
b481de9c
ZY
1529 }
1530
15b1687c 1531 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1532 "ilink1 nmiPC Line\n");
1533 for (i = ERROR_START_OFFSET;
1534 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1535 i += ERROR_ELEM_SIZE) {
5d49f498 1536 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1537 time =
5d49f498 1538 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1539 blink1 =
5d49f498 1540 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1541 blink2 =
5d49f498 1542 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1543 ilink1 =
5d49f498 1544 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1545 ilink2 =
5d49f498 1546 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1547 data1 =
5d49f498 1548 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1549
15b1687c
WT
1550 IWL_ERR(priv,
1551 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1552 desc_lookup(desc), desc, time, blink1, blink2,
1553 ilink1, ilink2, data1);
be1a71a1
JB
1554 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
1555 0, blink1, blink2, ilink1, ilink2);
b481de9c 1556 }
b481de9c
ZY
1557}
1558
f58177b9 1559#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1560
1561/**
bb8c093b 1562 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1563 *
b481de9c 1564 */
4a8a4322 1565static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
1566 u32 num_events, u32 mode)
1567{
1568 u32 i;
1569 u32 base; /* SRAM byte address of event log header */
1570 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1571 u32 ptr; /* SRAM byte address of log data */
1572 u32 ev, time, data; /* event log data */
1573
1574 if (num_events == 0)
1575 return;
1576
1577 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1578
1579 if (mode == 0)
1580 event_size = 2 * sizeof(u32);
1581 else
1582 event_size = 3 * sizeof(u32);
1583
1584 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1585
1586 /* "time" is actually "data" for mode 0 (no timestamp).
1587 * place event id # at far right for easier visual parsing. */
1588 for (i = 0; i < num_events; i++) {
5d49f498 1589 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 1590 ptr += sizeof(u32);
5d49f498 1591 time = iwl_read_targ_mem(priv, ptr);
b481de9c 1592 ptr += sizeof(u32);
15b1687c
WT
1593 if (mode == 0) {
1594 /* data, ev */
1595 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
be1a71a1 1596 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
15b1687c 1597 } else {
5d49f498 1598 data = iwl_read_targ_mem(priv, ptr);
b481de9c 1599 ptr += sizeof(u32);
15b1687c 1600 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
be1a71a1 1601 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b481de9c
ZY
1602 }
1603 }
1604}
1605
b7a79404 1606void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c 1607{
b481de9c
ZY
1608 u32 base; /* SRAM byte address of event log header */
1609 u32 capacity; /* event log capacity in # entries */
1610 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1611 u32 num_wraps; /* # times uCode wrapped to top of log */
1612 u32 next_entry; /* index of next entry to be written by uCode */
1613 u32 size; /* # entries that we'll print */
1614
1615 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1616 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1617 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
1618 return;
1619 }
1620
b481de9c 1621 /* event log header */
5d49f498
AK
1622 capacity = iwl_read_targ_mem(priv, base);
1623 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1624 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1625 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
1626
1627 size = num_wraps ? capacity : next_entry;
1628
1629 /* bail out if nothing in log */
1630 if (size == 0) {
15b1687c 1631 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b481de9c
ZY
1632 return;
1633 }
1634
15b1687c 1635 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
1636 size, num_wraps);
1637
1638 /* if uCode has wrapped back to top of log, start at the oldest entry,
1639 * i.e the next one that uCode would fill. */
1640 if (num_wraps)
bb8c093b 1641 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
1642 capacity - next_entry, mode);
1643
1644 /* (then/else) start at top of log */
bb8c093b 1645 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 1646
b481de9c 1647}
b7a79404
RC
1648#else
1649void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1650{
1651}
1652
1653void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1654{
1655}
1656
1657#endif
b481de9c 1658
4a8a4322 1659static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1660{
1661 u32 inta, handled = 0;
1662 u32 inta_fh;
1663 unsigned long flags;
d08853a3 1664#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1665 u32 inta_mask;
1666#endif
1667
1668 spin_lock_irqsave(&priv->lock, flags);
1669
1670 /* Ack/clear/reset pending uCode interrupts.
1671 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1672 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1673 inta = iwl_read32(priv, CSR_INT);
1674 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1675
1676 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1677 * Any new interrupts that happen after this, either while we're
1678 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1679 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1680 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1681
d08853a3 1682#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1683 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1684 /* just for debug */
5d49f498 1685 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1686 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1687 inta, inta_mask, inta_fh);
1688 }
1689#endif
1690
2f301227
ZY
1691 spin_unlock_irqrestore(&priv->lock, flags);
1692
b481de9c
ZY
1693 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1694 * atomic, make sure that inta covers all the interrupts that
1695 * we've discovered, even if FH interrupt came in just after
1696 * reading CSR_INT. */
6f83eaa1 1697 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1698 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1699 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1700 inta |= CSR_INT_BIT_FH_TX;
1701
1702 /* Now service all interrupt bits discovered above. */
1703 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1704 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1705
1706 /* Tell the device to stop sending interrupts */
ed3b932e 1707 iwl_disable_interrupts(priv);
b481de9c 1708
86ddbf62 1709 priv->isr_stats.hw++;
8ccde88a 1710 iwl_irq_handle_error(priv);
b481de9c
ZY
1711
1712 handled |= CSR_INT_BIT_HW_ERR;
1713
b481de9c
ZY
1714 return;
1715 }
1716
d08853a3 1717#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1718 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1719 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1720 if (inta & CSR_INT_BIT_SCD) {
e1623446 1721 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1722 "the frame/frames.\n");
86ddbf62
AK
1723 priv->isr_stats.sch++;
1724 }
b481de9c
ZY
1725
1726 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1727 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1728 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1729 priv->isr_stats.alive++;
1730 }
b481de9c
ZY
1731 }
1732#endif
1733 /* Safely ignore these bits for debug checks below */
25c03d8e 1734 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1735
b481de9c
ZY
1736 /* Error detected by uCode */
1737 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1738 IWL_ERR(priv, "Microcode SW error detected. "
1739 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1740 priv->isr_stats.sw++;
1741 priv->isr_stats.sw_err = inta;
8ccde88a 1742 iwl_irq_handle_error(priv);
b481de9c
ZY
1743 handled |= CSR_INT_BIT_SW_ERR;
1744 }
1745
1746 /* uCode wakes up after power-down sleep */
1747 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1748 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1749 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1750 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1751 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1752 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1753 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1754 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1755 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1756
86ddbf62 1757 priv->isr_stats.wakeup++;
b481de9c
ZY
1758 handled |= CSR_INT_BIT_WAKEUP;
1759 }
1760
1761 /* All uCode command responses, including Tx command responses,
1762 * Rx "responses" (frame-received notification), and other
1763 * notifications from uCode come through here*/
1764 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1765 iwl3945_rx_handle(priv);
86ddbf62 1766 priv->isr_stats.rx++;
b481de9c
ZY
1767 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1768 }
1769
1770 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1771 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1772 priv->isr_stats.tx++;
b481de9c 1773
5d49f498 1774 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1775 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1776 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1777 handled |= CSR_INT_BIT_FH_TX;
1778 }
1779
86ddbf62 1780 if (inta & ~handled) {
15b1687c 1781 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1782 priv->isr_stats.unhandled++;
1783 }
b481de9c 1784
40cefda9 1785 if (inta & ~priv->inta_mask) {
39aadf8c 1786 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1787 inta & ~priv->inta_mask);
39aadf8c 1788 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1789 }
1790
1791 /* Re-enable all interrupts */
0359facc
MA
1792 /* only Re-enable if disabled by irq */
1793 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1794 iwl_enable_interrupts(priv);
b481de9c 1795
d08853a3 1796#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1797 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1798 inta = iwl_read32(priv, CSR_INT);
1799 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1800 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1801 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1802 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1803 }
1804#endif
b481de9c
ZY
1805}
1806
4a8a4322 1807static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1808 enum ieee80211_band band,
f9340520 1809 u8 is_active, u8 n_probes,
bb8c093b 1810 struct iwl3945_scan_channel *scan_ch)
b481de9c 1811{
4e05c234 1812 struct ieee80211_channel *chan;
8318d78a 1813 const struct ieee80211_supported_band *sband;
d20b3c65 1814 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1815 u16 passive_dwell = 0;
1816 u16 active_dwell = 0;
1817 int added, i;
1818
cbba18c6 1819 sband = iwl_get_hw_mode(priv, band);
8318d78a 1820 if (!sband)
b481de9c
ZY
1821 return 0;
1822
77fecfb8
SO
1823 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1824 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1825
8f4807a1
AK
1826 if (passive_dwell <= active_dwell)
1827 passive_dwell = active_dwell + 1;
1828
4e05c234
JB
1829 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1830 chan = priv->scan_request->channels[i];
1831
1832 if (chan->band != band)
182e2e66
JB
1833 continue;
1834
4e05c234 1835 scan_ch->channel = chan->hw_value;
b481de9c 1836
e6148917 1837 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1838 if (!is_channel_valid(ch_info)) {
e1623446 1839 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1840 scan_ch->channel);
1841 continue;
1842 }
1843
011a0330
AK
1844 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1845 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1846 /* If passive , set up for auto-switch
1847 * and use long active_dwell time.
1848 */
b481de9c 1849 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1850 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1851 scan_ch->type = 0; /* passive */
011a0330
AK
1852 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1853 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1854 } else {
b481de9c 1855 scan_ch->type = 1; /* active */
011a0330 1856 }
b481de9c 1857
011a0330
AK
1858 /* Set direct probe bits. These may be used both for active
1859 * scan channels (probes gets sent right away),
1860 * or for passive channels (probes get se sent only after
1861 * hearing clear Rx packet).*/
1862 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1863 if (n_probes)
0d21044e 1864 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1865 } else {
1866 /* uCode v1 does not allow setting direct probe bits on
1867 * passive channel. */
1868 if ((scan_ch->type & 1) && n_probes)
0d21044e 1869 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1870 }
b481de9c 1871
9fbab516 1872 /* Set txpower levels to defaults */
b481de9c
ZY
1873 scan_ch->tpc.dsp_atten = 110;
1874 /* scan_pwr_info->tpc.dsp_atten; */
1875
1876 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1877 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1878 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1879 else {
1880 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1881 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1882 * power level:
8a1b0245 1883 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1884 */
1885 }
1886
e1623446 1887 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1888 scan_ch->channel,
1889 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1890 (scan_ch->type & 1) ?
1891 active_dwell : passive_dwell);
1892
1893 scan_ch++;
1894 added++;
1895 }
1896
e1623446 1897 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1898 return added;
1899}
1900
4a8a4322 1901static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1902 struct ieee80211_rate *rates)
1903{
1904 int i;
1905
1906 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1907 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1908 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1909 rates[i].hw_value_short = i;
1910 rates[i].flags = 0;
d9829a67 1911 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1912 /*
8318d78a 1913 * If CCK != 1M then set short preamble rate flag.
b481de9c 1914 */
bb8c093b 1915 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1916 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1917 }
b481de9c
ZY
1918 }
1919}
1920
b481de9c
ZY
1921/******************************************************************************
1922 *
1923 * uCode download functions
1924 *
1925 ******************************************************************************/
1926
4a8a4322 1927static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1928{
98c92211
TW
1929 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1930 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1931 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1932 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1933 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1934 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1935}
1936
1937/**
bb8c093b 1938 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1939 * looking at all data.
1940 */
4a8a4322 1941static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1942{
1943 u32 val;
1944 u32 save_len = len;
1945 int rc = 0;
1946 u32 errcnt;
1947
e1623446 1948 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1949
5d49f498 1950 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1951 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1952
1953 errcnt = 0;
1954 for (; len > 0; len -= sizeof(u32), image++) {
1955 /* read data comes through single port, auto-incr addr */
1956 /* NOTE: Use the debugless read so we don't flood kernel log
1957 * if IWL_DL_IO is set */
5d49f498 1958 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1959 if (val != le32_to_cpu(*image)) {
15b1687c 1960 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
1961 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1962 save_len - len, val, le32_to_cpu(*image));
1963 rc = -EIO;
1964 errcnt++;
1965 if (errcnt >= 20)
1966 break;
1967 }
1968 }
1969
b481de9c
ZY
1970
1971 if (!errcnt)
e1623446
TW
1972 IWL_DEBUG_INFO(priv,
1973 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
1974
1975 return rc;
1976}
1977
1978
1979/**
bb8c093b 1980 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
1981 * using sample data 100 bytes apart. If these sample points are good,
1982 * it's a pretty good bet that everything between them is good, too.
1983 */
4a8a4322 1984static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1985{
1986 u32 val;
1987 int rc = 0;
1988 u32 errcnt = 0;
1989 u32 i;
1990
e1623446 1991 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1992
b481de9c
ZY
1993 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1994 /* read data comes through single port, auto-incr addr */
1995 /* NOTE: Use the debugless read so we don't flood kernel log
1996 * if IWL_DL_IO is set */
5d49f498 1997 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1998 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 1999 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2000 if (val != le32_to_cpu(*image)) {
2001#if 0 /* Enable this if you want to see details */
15b1687c 2002 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2003 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2004 i, val, *image);
2005#endif
2006 rc = -EIO;
2007 errcnt++;
2008 if (errcnt >= 3)
2009 break;
2010 }
2011 }
2012
b481de9c
ZY
2013 return rc;
2014}
2015
2016
2017/**
bb8c093b 2018 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2019 * and verify its contents
2020 */
4a8a4322 2021static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2022{
2023 __le32 *image;
2024 u32 len;
2025 int rc = 0;
2026
2027 /* Try bootstrap */
2028 image = (__le32 *)priv->ucode_boot.v_addr;
2029 len = priv->ucode_boot.len;
bb8c093b 2030 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2031 if (rc == 0) {
e1623446 2032 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2033 return 0;
2034 }
2035
2036 /* Try initialize */
2037 image = (__le32 *)priv->ucode_init.v_addr;
2038 len = priv->ucode_init.len;
bb8c093b 2039 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2040 if (rc == 0) {
e1623446 2041 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2042 return 0;
2043 }
2044
2045 /* Try runtime/protocol */
2046 image = (__le32 *)priv->ucode_code.v_addr;
2047 len = priv->ucode_code.len;
bb8c093b 2048 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2049 if (rc == 0) {
e1623446 2050 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2051 return 0;
2052 }
2053
15b1687c 2054 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2055
9fbab516
BC
2056 /* Since nothing seems to match, show first several data entries in
2057 * instruction SRAM, so maybe visual inspection will give a clue.
2058 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2059 image = (__le32 *)priv->ucode_boot.v_addr;
2060 len = priv->ucode_boot.len;
bb8c093b 2061 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2062
2063 return rc;
2064}
2065
4a8a4322 2066static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2067{
2068 /* Remove all resets to allow NIC to operate */
5d49f498 2069 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2070}
2071
2072/**
bb8c093b 2073 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2074 *
2075 * Copy into buffers for card to fetch via bus-mastering
2076 */
4a8a4322 2077static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2078{
cc0f555d 2079 const struct iwl_ucode_header *ucode;
a0987a8d 2080 int ret = -EINVAL, index;
b481de9c
ZY
2081 const struct firmware *ucode_raw;
2082 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2083 const char *name_pre = priv->cfg->fw_name_pre;
2084 const unsigned int api_max = priv->cfg->ucode_api_max;
2085 const unsigned int api_min = priv->cfg->ucode_api_min;
2086 char buf[25];
b481de9c
ZY
2087 u8 *src;
2088 size_t len;
a0987a8d 2089 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2090
2091 /* Ask kernel firmware_class module to get the boot firmware off disk.
2092 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2093 for (index = api_max; index >= api_min; index--) {
2094 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2095 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2096 if (ret < 0) {
15b1687c 2097 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2098 buf, ret);
2099 if (ret == -ENOENT)
2100 continue;
2101 else
2102 goto error;
2103 } else {
2104 if (index < api_max)
15b1687c
WT
2105 IWL_ERR(priv, "Loaded firmware %s, "
2106 "which is deprecated. "
2107 " Please use API v%u instead.\n",
a0987a8d 2108 buf, api_max);
e1623446
TW
2109 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2110 "(%zd bytes) from disk\n",
a0987a8d
RC
2111 buf, ucode_raw->size);
2112 break;
2113 }
b481de9c
ZY
2114 }
2115
a0987a8d
RC
2116 if (ret < 0)
2117 goto error;
b481de9c
ZY
2118
2119 /* Make sure that we got at least our header! */
cc0f555d 2120 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2121 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2122 ret = -EINVAL;
b481de9c
ZY
2123 goto err_release;
2124 }
2125
2126 /* Data from ucode file: header followed by uCode images */
cc0f555d 2127 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2128
c02b3acd 2129 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2130 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2131 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2132 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2133 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2134 init_data_size =
2135 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2136 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2137 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2138
a0987a8d
RC
2139 /* api_ver should match the api version forming part of the
2140 * firmware filename ... but we don't check for that and only rely
877d0310 2141 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2142
2143 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2144 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2145 "Driver supports v%u, firmware is v%u.\n",
2146 api_max, api_ver);
2147 priv->ucode_ver = 0;
2148 ret = -EINVAL;
2149 goto err_release;
2150 }
2151 if (api_ver != api_max)
15b1687c 2152 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2153 "got %u. New firmware can be obtained "
2154 "from http://www.intellinuxwireless.org.\n",
2155 api_max, api_ver);
2156
978785a3
TW
2157 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2158 IWL_UCODE_MAJOR(priv->ucode_ver),
2159 IWL_UCODE_MINOR(priv->ucode_ver),
2160 IWL_UCODE_API(priv->ucode_ver),
2161 IWL_UCODE_SERIAL(priv->ucode_ver));
2162
e1623446 2163 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2164 priv->ucode_ver);
e1623446
TW
2165 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2166 inst_size);
2167 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2168 data_size);
2169 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2170 init_size);
2171 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2172 init_data_size);
2173 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2174 boot_size);
b481de9c 2175
a0987a8d 2176
b481de9c 2177 /* Verify size of file vs. image size info in file's header */
cc0f555d 2178 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2179 inst_size + data_size + init_size +
2180 init_data_size + boot_size) {
2181
cc0f555d
JS
2182 IWL_DEBUG_INFO(priv,
2183 "uCode file size %zd does not match expected size\n",
2184 ucode_raw->size);
90e759d1 2185 ret = -EINVAL;
b481de9c
ZY
2186 goto err_release;
2187 }
2188
2189 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2190 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2191 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2192 inst_size);
2193 ret = -EINVAL;
b481de9c
ZY
2194 goto err_release;
2195 }
2196
250bdd21 2197 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2198 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2199 data_size);
2200 ret = -EINVAL;
b481de9c
ZY
2201 goto err_release;
2202 }
250bdd21 2203 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2204 IWL_DEBUG_INFO(priv,
2205 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2206 init_size);
2207 ret = -EINVAL;
b481de9c
ZY
2208 goto err_release;
2209 }
250bdd21 2210 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2211 IWL_DEBUG_INFO(priv,
2212 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2213 init_data_size);
2214 ret = -EINVAL;
b481de9c
ZY
2215 goto err_release;
2216 }
250bdd21 2217 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2218 IWL_DEBUG_INFO(priv,
2219 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2220 boot_size);
2221 ret = -EINVAL;
b481de9c
ZY
2222 goto err_release;
2223 }
2224
2225 /* Allocate ucode buffers for card's bus-master loading ... */
2226
2227 /* Runtime instructions and 2 copies of data:
2228 * 1) unmodified from disk
2229 * 2) backup cache for save/restore during power-downs */
2230 priv->ucode_code.len = inst_size;
98c92211 2231 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2232
2233 priv->ucode_data.len = data_size;
98c92211 2234 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2235
2236 priv->ucode_data_backup.len = data_size;
98c92211 2237 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2238
90e759d1
TW
2239 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2240 !priv->ucode_data_backup.v_addr)
2241 goto err_pci_alloc;
b481de9c
ZY
2242
2243 /* Initialization instructions and data */
90e759d1
TW
2244 if (init_size && init_data_size) {
2245 priv->ucode_init.len = init_size;
98c92211 2246 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2247
2248 priv->ucode_init_data.len = init_data_size;
98c92211 2249 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2250
2251 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2252 goto err_pci_alloc;
2253 }
b481de9c
ZY
2254
2255 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2256 if (boot_size) {
2257 priv->ucode_boot.len = boot_size;
98c92211 2258 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2259
90e759d1
TW
2260 if (!priv->ucode_boot.v_addr)
2261 goto err_pci_alloc;
2262 }
b481de9c
ZY
2263
2264 /* Copy images into buffers for card's bus-master reads ... */
2265
2266 /* Runtime instructions (first block of data in file) */
cc0f555d 2267 len = inst_size;
e1623446
TW
2268 IWL_DEBUG_INFO(priv,
2269 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2270 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2271 src += len;
2272
e1623446 2273 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2274 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2275
2276 /* Runtime data (2nd block)
bb8c093b 2277 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2278 len = data_size;
e1623446
TW
2279 IWL_DEBUG_INFO(priv,
2280 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2281 memcpy(priv->ucode_data.v_addr, src, len);
2282 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2283 src += len;
b481de9c
ZY
2284
2285 /* Initialization instructions (3rd block) */
2286 if (init_size) {
cc0f555d 2287 len = init_size;
e1623446
TW
2288 IWL_DEBUG_INFO(priv,
2289 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2290 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2291 src += len;
b481de9c
ZY
2292 }
2293
2294 /* Initialization data (4th block) */
2295 if (init_data_size) {
cc0f555d 2296 len = init_data_size;
e1623446
TW
2297 IWL_DEBUG_INFO(priv,
2298 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2299 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2300 src += len;
b481de9c
ZY
2301 }
2302
2303 /* Bootstrap instructions (5th block) */
cc0f555d 2304 len = boot_size;
e1623446
TW
2305 IWL_DEBUG_INFO(priv,
2306 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2307 memcpy(priv->ucode_boot.v_addr, src, len);
2308
2309 /* We have our copies now, allow OS release its copies */
2310 release_firmware(ucode_raw);
2311 return 0;
2312
2313 err_pci_alloc:
15b1687c 2314 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2315 ret = -ENOMEM;
bb8c093b 2316 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2317
2318 err_release:
2319 release_firmware(ucode_raw);
2320
2321 error:
90e759d1 2322 return ret;
b481de9c
ZY
2323}
2324
2325
2326/**
bb8c093b 2327 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2328 *
2329 * Tell initialization uCode where to find runtime uCode.
2330 *
2331 * BSM registers initially contain pointers to initialization uCode.
2332 * We need to replace them to load runtime uCode inst and data,
2333 * and to save runtime data when powering down.
2334 */
4a8a4322 2335static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2336{
2337 dma_addr_t pinst;
2338 dma_addr_t pdata;
b481de9c
ZY
2339
2340 /* bits 31:0 for 3945 */
2341 pinst = priv->ucode_code.p_addr;
2342 pdata = priv->ucode_data_backup.p_addr;
2343
b481de9c 2344 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2345 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2346 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2347 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2348 priv->ucode_data.len);
2349
a96a27f9 2350 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2351 * that all new ptr/size info is in place */
5d49f498 2352 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2353 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2354
e1623446 2355 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2356
a8b50a0a 2357 return 0;
b481de9c
ZY
2358}
2359
2360/**
bb8c093b 2361 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2362 *
2363 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2364 *
b481de9c 2365 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2366 */
4a8a4322 2367static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2368{
2369 /* Check alive response for "valid" sign from uCode */
2370 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2371 /* We had an error bringing up the hardware, so take it
2372 * all the way back down so we can try again */
e1623446 2373 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2374 goto restart;
2375 }
2376
2377 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2378 * This is a paranoid check, because we would not have gotten the
2379 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2380 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2381 /* Runtime instruction load was bad;
2382 * take it all the way back down so we can try again */
e1623446 2383 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2384 goto restart;
2385 }
2386
2387 /* Send pointers to protocol/runtime uCode image ... init code will
2388 * load and launch runtime uCode, which will send us another "Alive"
2389 * notification. */
e1623446 2390 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2391 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2392 /* Runtime instruction load won't happen;
2393 * take it all the way back down so we can try again */
e1623446 2394 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2395 goto restart;
2396 }
2397 return;
2398
2399 restart:
2400 queue_work(priv->workqueue, &priv->restart);
2401}
2402
b481de9c 2403/**
bb8c093b 2404 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2405 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2406 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2407 */
4a8a4322 2408static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2409{
b481de9c
ZY
2410 int thermal_spin = 0;
2411 u32 rfkill;
2412
e1623446 2413 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2414
2415 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2416 /* We had an error bringing up the hardware, so take it
2417 * all the way back down so we can try again */
e1623446 2418 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2419 goto restart;
2420 }
2421
2422 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2423 * This is a paranoid check, because we would not have gotten the
2424 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2425 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2426 /* Runtime instruction load was bad;
2427 * take it all the way back down so we can try again */
e1623446 2428 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2429 goto restart;
2430 }
2431
c587de0b 2432 iwl_clear_stations_table(priv);
b481de9c 2433
5d49f498 2434 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2435 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2436
2437 if (rfkill & 0x1) {
2438 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2439 /* if RFKILL is not on, then wait for thermal
b481de9c 2440 * sensor in adapter to kick in */
bb8c093b 2441 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2442 thermal_spin++;
2443 udelay(10);
2444 }
2445
2446 if (thermal_spin)
e1623446 2447 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2448 thermal_spin * 10);
2449 } else
2450 set_bit(STATUS_RF_KILL_HW, &priv->status);
2451
9fbab516 2452 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2453 set_bit(STATUS_ALIVE, &priv->status);
2454
775a6e27 2455 if (iwl_is_rfkill(priv))
b481de9c
ZY
2456 return;
2457
36d6825b 2458 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2459
2460 priv->active_rate = priv->rates_mask;
2461 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2462
d25aabb0 2463 iwl_power_update_mode(priv, false);
b481de9c 2464
8ccde88a 2465 if (iwl_is_associated(priv)) {
bb8c093b 2466 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2467 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2468
8a9b9926 2469 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2470 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2471 } else {
2472 /* Initialize our rx_config data */
8ccde88a 2473 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2474 }
2475
9fbab516 2476 /* Configure Bluetooth device coexistence support */
17f841cd 2477 iwl_send_bt_config(priv);
b481de9c
ZY
2478
2479 /* Configure the adapter for unassociated operation */
e0158e61 2480 iwlcore_commit_rxon(priv);
b481de9c 2481
b481de9c
ZY
2482 iwl3945_reg_txpower_periodic(priv);
2483
e932a609 2484 iwl_leds_init(priv);
fe00b5a5 2485
e1623446 2486 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2487 set_bit(STATUS_READY, &priv->status);
5a66926a 2488 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2489
9bdf5eca
MA
2490 /* reassociate for ADHOC mode */
2491 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2492 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2493 priv->vif);
2494 if (beacon)
9944b938 2495 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2496 }
2497
f45c2714 2498 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2499 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2500
b481de9c
ZY
2501 return;
2502
2503 restart:
2504 queue_work(priv->workqueue, &priv->restart);
2505}
2506
4a8a4322 2507static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2508
4a8a4322 2509static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2510{
2511 unsigned long flags;
2512 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2513 struct ieee80211_conf *conf = NULL;
2514
e1623446 2515 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2516
2517 conf = ieee80211_get_hw_conf(priv->hw);
2518
2519 if (!exit_pending)
2520 set_bit(STATUS_EXIT_PENDING, &priv->status);
2521
c587de0b 2522 iwl_clear_stations_table(priv);
b481de9c
ZY
2523
2524 /* Unblock any waiting calls */
2525 wake_up_interruptible_all(&priv->wait_command_queue);
2526
b481de9c
ZY
2527 /* Wipe out the EXIT_PENDING status bit if we are not actually
2528 * exiting the module */
2529 if (!exit_pending)
2530 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2531
2532 /* stop and reset the on-board processor */
5d49f498 2533 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2534
2535 /* tell the device to stop sending interrupts */
0359facc 2536 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2537 iwl_disable_interrupts(priv);
0359facc
MA
2538 spin_unlock_irqrestore(&priv->lock, flags);
2539 iwl_synchronize_irq(priv);
b481de9c
ZY
2540
2541 if (priv->mac80211_registered)
2542 ieee80211_stop_queues(priv->hw);
2543
bb8c093b 2544 /* If we have not previously called iwl3945_init() then
6da3a13e 2545 * clear all bits but the RF Kill bits and return */
775a6e27 2546 if (!iwl_is_init(priv)) {
b481de9c
ZY
2547 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2548 STATUS_RF_KILL_HW |
9788864e
RC
2549 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2550 STATUS_GEO_CONFIGURED |
ebef2008
AK
2551 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2552 STATUS_EXIT_PENDING;
b481de9c
ZY
2553 goto exit;
2554 }
2555
6da3a13e 2556 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2557 * bit and continue taking the NIC down. */
b481de9c
ZY
2558 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2559 STATUS_RF_KILL_HW |
9788864e
RC
2560 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2561 STATUS_GEO_CONFIGURED |
b481de9c 2562 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2563 STATUS_FW_ERROR |
2564 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2565 STATUS_EXIT_PENDING;
b481de9c 2566
bb8c093b
CH
2567 iwl3945_hw_txq_ctx_stop(priv);
2568 iwl3945_hw_rxq_stop(priv);
b481de9c 2569
a8b50a0a
MA
2570 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2571 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2572
2573 udelay(5);
2574
4d2ccdb9
BC
2575 /* Stop the device, and put it in low power state */
2576 priv->cfg->ops->lib->apm_ops.stop(priv);
e9414b6b 2577
b481de9c 2578 exit:
3d24a9f7 2579 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2580
2581 if (priv->ibss_beacon)
2582 dev_kfree_skb(priv->ibss_beacon);
2583 priv->ibss_beacon = NULL;
2584
2585 /* clear out any free frames */
bb8c093b 2586 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2587}
2588
4a8a4322 2589static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2590{
2591 mutex_lock(&priv->mutex);
bb8c093b 2592 __iwl3945_down(priv);
b481de9c 2593 mutex_unlock(&priv->mutex);
b24d22b1 2594
bb8c093b 2595 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2596}
2597
2598#define MAX_HW_RESTARTS 5
2599
4a8a4322 2600static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2601{
2602 int rc, i;
2603
2604 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2605 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2606 return -EIO;
2607 }
2608
e903fbd4 2609 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2610 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2611 return -EIO;
2612 }
2613
e655b9f0 2614 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2615 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2616 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2617 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2618 else {
2619 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2620 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2621 return -ENODEV;
b481de9c 2622 }
80fcc9e2 2623
5d49f498 2624 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2625
bb8c093b 2626 rc = iwl3945_hw_nic_init(priv);
b481de9c 2627 if (rc) {
15b1687c 2628 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2629 return rc;
2630 }
2631
2632 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2633 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2634 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2635 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2636
2637 /* clear (again), then enable host interrupts */
5d49f498 2638 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2639 iwl_enable_interrupts(priv);
b481de9c
ZY
2640
2641 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2642 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2643 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2644
2645 /* Copy original ucode data image from disk into backup cache.
2646 * This will be used to initialize the on-board processor's
2647 * data SRAM for a clean start when the runtime program first loads. */
2648 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2649 priv->ucode_data.len);
b481de9c 2650
e655b9f0
ZY
2651 /* We return success when we resume from suspend and rf_kill is on. */
2652 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2653 return 0;
2654
b481de9c
ZY
2655 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2656
c587de0b 2657 iwl_clear_stations_table(priv);
b481de9c
ZY
2658
2659 /* load bootstrap state machine,
2660 * load bootstrap program into processor's memory,
2661 * prepare to load the "initialize" uCode */
0164b9b4 2662 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2663
2664 if (rc) {
15b1687c
WT
2665 IWL_ERR(priv,
2666 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2667 continue;
2668 }
2669
2670 /* start card; "initialize" will load runtime ucode */
bb8c093b 2671 iwl3945_nic_start(priv);
b481de9c 2672
e1623446 2673 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2674
2675 return 0;
2676 }
2677
2678 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2679 __iwl3945_down(priv);
ebef2008 2680 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2681
2682 /* tried to restart and config the device for as long as our
2683 * patience could withstand */
15b1687c 2684 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2685 return -EIO;
2686}
2687
2688
2689/*****************************************************************************
2690 *
2691 * Workqueue callbacks
2692 *
2693 *****************************************************************************/
2694
bb8c093b 2695static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2696{
4a8a4322
AK
2697 struct iwl_priv *priv =
2698 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2699
2700 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2701 return;
2702
2703 mutex_lock(&priv->mutex);
bb8c093b 2704 iwl3945_init_alive_start(priv);
b481de9c
ZY
2705 mutex_unlock(&priv->mutex);
2706}
2707
bb8c093b 2708static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2709{
4a8a4322
AK
2710 struct iwl_priv *priv =
2711 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2712
2713 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2714 return;
2715
2716 mutex_lock(&priv->mutex);
bb8c093b 2717 iwl3945_alive_start(priv);
b481de9c
ZY
2718 mutex_unlock(&priv->mutex);
2719}
2720
743cdf1b
BC
2721/*
2722 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2723 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2724 * *is* readable even when device has been SW_RESET into low power mode
2725 * (e.g. during RF KILL).
2726 */
2663516d
HS
2727static void iwl3945_rfkill_poll(struct work_struct *data)
2728{
2729 struct iwl_priv *priv =
2730 container_of(data, struct iwl_priv, rfkill_poll.work);
743cdf1b
BC
2731 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
2732 bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
2733 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2663516d 2734
743cdf1b
BC
2735 if (new_rfkill != old_rfkill) {
2736 if (new_rfkill)
2737 set_bit(STATUS_RF_KILL_HW, &priv->status);
2738 else
2739 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2663516d 2740
743cdf1b
BC
2741 wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
2742
2743 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
2744 new_rfkill ? "disable radio" : "enable radio");
2745 }
2663516d 2746
743cdf1b
BC
2747 /* Keep this running, even if radio now enabled. This will be
2748 * cancelled in mac_start() if system decides to start again */
2663516d
HS
2749 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2750 round_jiffies_relative(2 * HZ));
2751
2752}
2753
b481de9c 2754#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2755static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2756{
4a8a4322
AK
2757 struct iwl_priv *priv =
2758 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2759 struct iwl_host_cmd cmd = {
b481de9c 2760 .id = REPLY_SCAN_CMD,
bb8c093b 2761 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2762 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2763 };
2764 int rc = 0;
bb8c093b 2765 struct iwl3945_scan_cmd *scan;
b481de9c 2766 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2767 u8 n_probes = 0;
8318d78a 2768 enum ieee80211_band band;
1ecf9fc1 2769 bool is_active = false;
b481de9c
ZY
2770
2771 conf = ieee80211_get_hw_conf(priv->hw);
2772
2773 mutex_lock(&priv->mutex);
2774
fbc9f97b
RC
2775 cancel_delayed_work(&priv->scan_check);
2776
775a6e27 2777 if (!iwl_is_ready(priv)) {
39aadf8c 2778 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2779 goto done;
2780 }
2781
a96a27f9 2782 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2783 * was given the chance to run... */
2784 if (!test_bit(STATUS_SCANNING, &priv->status))
2785 goto done;
2786
2787 /* This should never be called or scheduled if there is currently
2788 * a scan active in the hardware. */
2789 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2790 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2791 "Ignoring second request.\n");
b481de9c
ZY
2792 rc = -EIO;
2793 goto done;
2794 }
2795
2796 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2797 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2798 goto done;
2799 }
2800
2801 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2802 IWL_DEBUG_HC(priv,
2803 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2804 goto done;
2805 }
2806
775a6e27 2807 if (iwl_is_rfkill(priv)) {
e1623446 2808 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2809 goto done;
2810 }
2811
2812 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2813 IWL_DEBUG_HC(priv,
2814 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2815 goto done;
2816 }
2817
2818 if (!priv->scan_bands) {
e1623446 2819 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2820 goto done;
2821 }
2822
805cee5b
WT
2823 if (!priv->scan) {
2824 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2825 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2826 if (!priv->scan) {
b481de9c
ZY
2827 rc = -ENOMEM;
2828 goto done;
2829 }
2830 }
805cee5b 2831 scan = priv->scan;
bb8c093b 2832 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2833
2834 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2835 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2836
8ccde88a 2837 if (iwl_is_associated(priv)) {
b481de9c
ZY
2838 u16 interval = 0;
2839 u32 extra;
2840 u32 suspend_time = 100;
2841 u32 scan_suspend_time = 100;
2842 unsigned long flags;
2843
e1623446 2844 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2845
2846 spin_lock_irqsave(&priv->lock, flags);
2847 interval = priv->beacon_int;
2848 spin_unlock_irqrestore(&priv->lock, flags);
2849
2850 scan->suspend_time = 0;
15e869d8 2851 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2852 if (!interval)
2853 interval = suspend_time;
2854 /*
2855 * suspend time format:
2856 * 0-19: beacon interval in usec (time before exec.)
2857 * 20-23: 0
2858 * 24-31: number of beacons (suspend between channels)
2859 */
2860
2861 extra = (suspend_time / interval) << 24;
2862 scan_suspend_time = 0xFF0FFFFF &
2863 (extra | ((suspend_time % interval) * 1024));
2864
2865 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2866 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2867 scan_suspend_time, interval);
2868 }
2869
1ecf9fc1
JB
2870 if (priv->scan_request->n_ssids) {
2871 int i, p = 0;
2872 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2873 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2874 /* always does wildcard anyway */
2875 if (!priv->scan_request->ssids[i].ssid_len)
2876 continue;
2877 scan->direct_scan[p].id = WLAN_EID_SSID;
2878 scan->direct_scan[p].len =
2879 priv->scan_request->ssids[i].ssid_len;
2880 memcpy(scan->direct_scan[p].ssid,
2881 priv->scan_request->ssids[i].ssid,
2882 priv->scan_request->ssids[i].ssid_len);
2883 n_probes++;
2884 p++;
2885 }
2886 is_active = true;
f9340520 2887 } else
1ecf9fc1 2888 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2889
2890 /* We don't build a direct scan probe request; the uCode will do
2891 * that based on the direct_mask added to each channel entry */
b481de9c 2892 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2893 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2894 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2895
2896 /* flags + rate selection */
2897
66b5004d 2898 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2899 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2900 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2901 scan->good_CRC_th = 0;
8318d78a 2902 band = IEEE80211_BAND_2GHZ;
66b5004d 2903 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2904 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2905 /*
2906 * If active scaning is requested but a certain channel
2907 * is marked passive, we can do active scanning if we
2908 * detect transmissions.
2909 */
2910 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2911 band = IEEE80211_BAND_5GHZ;
66b5004d 2912 } else {
39aadf8c 2913 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2914 goto done;
2915 }
2916
77fecfb8 2917 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2918 iwl_fill_probe_req(priv,
2919 (struct ieee80211_mgmt *)scan->data,
2920 priv->scan_request->ie,
2921 priv->scan_request->ie_len,
2922 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2923
b481de9c
ZY
2924 /* select Rx antennas */
2925 scan->flags |= iwl3945_get_antenna_flags(priv);
2926
279b05d4 2927 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2928 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2929
f9340520 2930 scan->channel_count =
1ecf9fc1 2931 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2932 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2933
14b54336 2934 if (scan->channel_count == 0) {
e1623446 2935 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2936 goto done;
2937 }
2938
b481de9c 2939 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2940 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2941 cmd.data = scan;
2942 scan->len = cpu_to_le16(cmd.len);
2943
2944 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 2945 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2946 if (rc)
2947 goto done;
2948
2949 queue_delayed_work(priv->workqueue, &priv->scan_check,
2950 IWL_SCAN_CHECK_WATCHDOG);
2951
2952 mutex_unlock(&priv->mutex);
2953 return;
2954
2955 done:
2420ebc1
MA
2956 /* can not perform scan make sure we clear scanning
2957 * bits from status so next scan request can be performed.
2958 * if we dont clear scanning status bit here all next scan
2959 * will fail
2960 */
2961 clear_bit(STATUS_SCAN_HW, &priv->status);
2962 clear_bit(STATUS_SCANNING, &priv->status);
2963
01ebd063 2964 /* inform mac80211 scan aborted */
b481de9c
ZY
2965 queue_work(priv->workqueue, &priv->scan_completed);
2966 mutex_unlock(&priv->mutex);
2967}
2968
bb8c093b 2969static void iwl3945_bg_up(struct work_struct *data)
b481de9c 2970{
4a8a4322 2971 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2972
2973 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2974 return;
2975
2976 mutex_lock(&priv->mutex);
bb8c093b 2977 __iwl3945_up(priv);
b481de9c
ZY
2978 mutex_unlock(&priv->mutex);
2979}
2980
bb8c093b 2981static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 2982{
4a8a4322 2983 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2984
2985 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2986 return;
2987
19cc1087
JB
2988 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2989 mutex_lock(&priv->mutex);
2990 priv->vif = NULL;
2991 priv->is_open = 0;
2992 mutex_unlock(&priv->mutex);
2993 iwl3945_down(priv);
2994 ieee80211_restart_hw(priv->hw);
2995 } else {
2996 iwl3945_down(priv);
2997 queue_work(priv->workqueue, &priv->up);
2998 }
b481de9c
ZY
2999}
3000
bb8c093b 3001static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3002{
4a8a4322
AK
3003 struct iwl_priv *priv =
3004 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3005
3006 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3007 return;
3008
3009 mutex_lock(&priv->mutex);
bb8c093b 3010 iwl3945_rx_replenish(priv);
b481de9c
ZY
3011 mutex_unlock(&priv->mutex);
3012}
3013
7878a5a4
MA
3014#define IWL_DELAY_NEXT_SCAN (HZ*2)
3015
5bbe233b 3016void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3017{
b481de9c
ZY
3018 int rc = 0;
3019 struct ieee80211_conf *conf = NULL;
3020
05c914fe 3021 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3022 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3023 return;
3024 }
3025
3026
e1623446 3027 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3028 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3029
3030 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3031 return;
3032
322a9811 3033 if (!priv->vif || !priv->is_open)
6ef89d0a 3034 return;
322a9811 3035
af0053d6 3036 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3037
b481de9c
ZY
3038 conf = ieee80211_get_hw_conf(priv->hw);
3039
8ccde88a 3040 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3041 iwlcore_commit_rxon(priv);
b481de9c 3042
28afaf91 3043 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3044 iwl_setup_rxon_timing(priv);
518099a8 3045 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3046 sizeof(priv->rxon_timing), &priv->rxon_timing);
3047 if (rc)
39aadf8c 3048 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3049 "Attempting to continue.\n");
3050
8ccde88a 3051 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3052
8ccde88a 3053 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3054
e1623446 3055 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3056 priv->assoc_id, priv->beacon_int);
3057
3058 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3059 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3060 else
8ccde88a 3061 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3062
8ccde88a 3063 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3064 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3065 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3066 else
8ccde88a 3067 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3068
05c914fe 3069 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3070 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3071
3072 }
3073
e0158e61 3074 iwlcore_commit_rxon(priv);
b481de9c
ZY
3075
3076 switch (priv->iw_mode) {
05c914fe 3077 case NL80211_IFTYPE_STATION:
bb8c093b 3078 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3079 break;
3080
05c914fe 3081 case NL80211_IFTYPE_ADHOC:
b481de9c 3082
ce546fd2 3083 priv->assoc_id = 1;
c587de0b 3084 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3085 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3086 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3087 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3088 CMD_ASYNC);
bb8c093b
CH
3089 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3090 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3091
3092 break;
3093
3094 default:
15b1687c 3095 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3096 __func__, priv->iw_mode);
b481de9c
ZY
3097 break;
3098 }
3099
14d2aac5 3100 iwl_activate_qos(priv, 0);
292ae174 3101
7878a5a4
MA
3102 /* we have just associated, don't start scan too early */
3103 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3104}
3105
b481de9c
ZY
3106/*****************************************************************************
3107 *
3108 * mac80211 entry point functions
3109 *
3110 *****************************************************************************/
3111
5a66926a
ZY
3112#define UCODE_READY_TIMEOUT (2 * HZ)
3113
bb8c093b 3114static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3115{
4a8a4322 3116 struct iwl_priv *priv = hw->priv;
5a66926a 3117 int ret;
b481de9c 3118
e1623446 3119 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3120
3121 /* we should be verifying the device is ready to be opened */
3122 mutex_lock(&priv->mutex);
3123
5a66926a
ZY
3124 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3125 * ucode filename and max sizes are card-specific. */
3126
3127 if (!priv->ucode_code.len) {
3128 ret = iwl3945_read_ucode(priv);
3129 if (ret) {
15b1687c 3130 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3131 mutex_unlock(&priv->mutex);
3132 goto out_release_irq;
3133 }
3134 }
b481de9c 3135
e655b9f0 3136 ret = __iwl3945_up(priv);
b481de9c
ZY
3137
3138 mutex_unlock(&priv->mutex);
5a66926a 3139
e655b9f0
ZY
3140 if (ret)
3141 goto out_release_irq;
3142
e1623446 3143 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3144
5a66926a
ZY
3145 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3146 * mac80211 will not be run successfully. */
3147 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3148 test_bit(STATUS_READY, &priv->status),
3149 UCODE_READY_TIMEOUT);
3150 if (!ret) {
3151 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3152 IWL_ERR(priv,
3153 "Wait for START_ALIVE timeout after %dms.\n",
3154 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3155 ret = -ETIMEDOUT;
3156 goto out_release_irq;
3157 }
3158 }
3159
2663516d
HS
3160 /* ucode is running and will send rfkill notifications,
3161 * no need to poll the killswitch state anymore */
3162 cancel_delayed_work(&priv->rfkill_poll);
3163
e932a609
JB
3164 iwl_led_start(priv);
3165
e655b9f0 3166 priv->is_open = 1;
e1623446 3167 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3168 return 0;
5a66926a
ZY
3169
3170out_release_irq:
e655b9f0 3171 priv->is_open = 0;
e1623446 3172 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3173 return ret;
b481de9c
ZY
3174}
3175
bb8c093b 3176static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3177{
4a8a4322 3178 struct iwl_priv *priv = hw->priv;
b481de9c 3179
e1623446 3180 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3181
e655b9f0 3182 if (!priv->is_open) {
e1623446 3183 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3184 return;
3185 }
3186
b481de9c 3187 priv->is_open = 0;
5a66926a 3188
775a6e27 3189 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3190 /* stop mac, cancel any scan request and clear
3191 * RXON_FILTER_ASSOC_MSK BIT
3192 */
5a66926a 3193 mutex_lock(&priv->mutex);
af0053d6 3194 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3195 mutex_unlock(&priv->mutex);
fde3571f
MA
3196 }
3197
5a66926a
ZY
3198 iwl3945_down(priv);
3199
3200 flush_workqueue(priv->workqueue);
2663516d
HS
3201
3202 /* start polling the killswitch state again */
3203 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3204 round_jiffies_relative(2 * HZ));
6ef89d0a 3205
e1623446 3206 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3207}
3208
e039fa4a 3209static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3210{
4a8a4322 3211 struct iwl_priv *priv = hw->priv;
b481de9c 3212
e1623446 3213 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3214
e1623446 3215 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3216 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3217
e039fa4a 3218 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3219 dev_kfree_skb_any(skb);
3220
e1623446 3221 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3222 return NETDEV_TX_OK;
b481de9c
ZY
3223}
3224
60690a6a 3225void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3226{
3227 int rc = 0;
3228
d986bcd1 3229 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3230 return;
3231
3232 /* The following should be done only at AP bring up */
8ccde88a 3233 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3234
3235 /* RXON - unassoc (to set timing command) */
8ccde88a 3236 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3237 iwlcore_commit_rxon(priv);
b481de9c
ZY
3238
3239 /* RXON Timing */
28afaf91 3240 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3241 iwl_setup_rxon_timing(priv);
518099a8
SO
3242 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3243 sizeof(priv->rxon_timing),
3244 &priv->rxon_timing);
b481de9c 3245 if (rc)
39aadf8c 3246 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3247 "Attempting to continue.\n");
3248
3249 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3250 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3251 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3252 priv->staging_rxon.flags |=
b481de9c
ZY
3253 RXON_FLG_SHORT_PREAMBLE_MSK;
3254 else
8ccde88a 3255 priv->staging_rxon.flags &=
b481de9c
ZY
3256 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3257
8ccde88a 3258 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3259 if (priv->assoc_capability &
3260 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3261 priv->staging_rxon.flags |=
b481de9c
ZY
3262 RXON_FLG_SHORT_SLOT_MSK;
3263 else
8ccde88a 3264 priv->staging_rxon.flags &=
b481de9c
ZY
3265 ~RXON_FLG_SHORT_SLOT_MSK;
3266
05c914fe 3267 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3268 priv->staging_rxon.flags &=
b481de9c
ZY
3269 ~RXON_FLG_SHORT_SLOT_MSK;
3270 }
3271 /* restore RXON assoc */
8ccde88a 3272 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3273 iwlcore_commit_rxon(priv);
c587de0b 3274 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3275 }
bb8c093b 3276 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3277
3278 /* FIXME - we need to add code here to detect a totally new
3279 * configuration, reset the AP, unassoc, rxon timing, assoc,
3280 * clear sta table, add BCAST sta... */
3281}
3282
bb8c093b 3283static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3284 struct ieee80211_vif *vif,
3285 struct ieee80211_sta *sta,
3286 struct ieee80211_key_conf *key)
b481de9c 3287{
4a8a4322 3288 struct iwl_priv *priv = hw->priv;
dc822b5d 3289 const u8 *addr;
6e21f15c
AK
3290 int ret = 0;
3291 u8 sta_id = IWL_INVALID_STATION;
3292 u8 static_key;
b481de9c 3293
e1623446 3294 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3295
df878d8f 3296 if (iwl3945_mod_params.sw_crypto) {
e1623446 3297 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3298 return -EOPNOTSUPP;
3299 }
3300
42986796 3301 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3302 static_key = !iwl_is_associated(priv);
3303
3304 if (!static_key) {
c587de0b 3305 sta_id = iwl_find_station(priv, addr);
6e21f15c 3306 if (sta_id == IWL_INVALID_STATION) {
12514396 3307 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3308 addr);
3309 return -EINVAL;
3310 }
b481de9c
ZY
3311 }
3312
3313 mutex_lock(&priv->mutex);
af0053d6 3314 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3315 mutex_unlock(&priv->mutex);
15e869d8 3316
b481de9c 3317 switch (cmd) {
6e21f15c
AK
3318 case SET_KEY:
3319 if (static_key)
3320 ret = iwl3945_set_static_key(priv, key);
3321 else
3322 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3323 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3324 break;
3325 case DISABLE_KEY:
6e21f15c
AK
3326 if (static_key)
3327 ret = iwl3945_remove_static_key(priv);
3328 else
3329 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3330 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3331 break;
3332 default:
42986796 3333 ret = -EINVAL;
b481de9c
ZY
3334 }
3335
e1623446 3336 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3337
42986796 3338 return ret;
b481de9c
ZY
3339}
3340
b481de9c
ZY
3341/*****************************************************************************
3342 *
3343 * sysfs attributes
3344 *
3345 *****************************************************************************/
3346
d08853a3 3347#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3348
3349/*
3350 * The following adds a new attribute to the sysfs representation
3351 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3352 * used for controlling the debug level.
3353 *
3354 * See the level definitions in iwl for details.
a562a9dd 3355 *
3d816c77
RC
3356 * The debug_level being managed using sysfs below is a per device debug
3357 * level that is used instead of the global debug level if it (the per
3358 * device debug level) is set.
b481de9c 3359 */
40b8ec0b
SO
3360static ssize_t show_debug_level(struct device *d,
3361 struct device_attribute *attr, char *buf)
b481de9c 3362{
3d816c77
RC
3363 struct iwl_priv *priv = dev_get_drvdata(d);
3364 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3365}
40b8ec0b
SO
3366static ssize_t store_debug_level(struct device *d,
3367 struct device_attribute *attr,
b481de9c
ZY
3368 const char *buf, size_t count)
3369{
928841b1 3370 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3371 unsigned long val;
3372 int ret;
b481de9c 3373
40b8ec0b
SO
3374 ret = strict_strtoul(buf, 0, &val);
3375 if (ret)
978785a3 3376 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3377 else {
3d816c77 3378 priv->debug_level = val;
20594eb0
WYG
3379 if (iwl_alloc_traffic_mem(priv))
3380 IWL_ERR(priv,
3381 "Not enough memory to generate traffic log\n");
3382 }
b481de9c
ZY
3383 return strnlen(buf, count);
3384}
3385
40b8ec0b
SO
3386static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3387 show_debug_level, store_debug_level);
b481de9c 3388
d08853a3 3389#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3390
b481de9c
ZY
3391static ssize_t show_temperature(struct device *d,
3392 struct device_attribute *attr, char *buf)
3393{
928841b1 3394 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3395
775a6e27 3396 if (!iwl_is_alive(priv))
b481de9c
ZY
3397 return -EAGAIN;
3398
bb8c093b 3399 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3400}
3401
3402static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3403
b481de9c
ZY
3404static ssize_t show_tx_power(struct device *d,
3405 struct device_attribute *attr, char *buf)
3406{
928841b1 3407 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3408 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3409}
3410
3411static ssize_t store_tx_power(struct device *d,
3412 struct device_attribute *attr,
3413 const char *buf, size_t count)
3414{
928841b1 3415 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3416 char *p = (char *)buf;
3417 u32 val;
3418
3419 val = simple_strtoul(p, &p, 10);
3420 if (p == buf)
978785a3 3421 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3422 else
bb8c093b 3423 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3424
3425 return count;
3426}
3427
3428static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3429
3430static ssize_t show_flags(struct device *d,
3431 struct device_attribute *attr, char *buf)
3432{
928841b1 3433 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3434
8ccde88a 3435 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3436}
3437
3438static ssize_t store_flags(struct device *d,
3439 struct device_attribute *attr,
3440 const char *buf, size_t count)
3441{
928841b1 3442 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3443 u32 flags = simple_strtoul(buf, NULL, 0);
3444
3445 mutex_lock(&priv->mutex);
8ccde88a 3446 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3447 /* Cancel any currently running scans... */
af0053d6 3448 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3449 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3450 else {
e1623446 3451 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3452 flags);
8ccde88a 3453 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3454 iwlcore_commit_rxon(priv);
b481de9c
ZY
3455 }
3456 }
3457 mutex_unlock(&priv->mutex);
3458
3459 return count;
3460}
3461
3462static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3463
3464static ssize_t show_filter_flags(struct device *d,
3465 struct device_attribute *attr, char *buf)
3466{
928841b1 3467 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3468
3469 return sprintf(buf, "0x%04X\n",
8ccde88a 3470 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3471}
3472
3473static ssize_t store_filter_flags(struct device *d,
3474 struct device_attribute *attr,
3475 const char *buf, size_t count)
3476{
928841b1 3477 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3478 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3479
3480 mutex_lock(&priv->mutex);
8ccde88a 3481 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3482 /* Cancel any currently running scans... */
af0053d6 3483 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3484 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3485 else {
e1623446 3486 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3487 "0x%04X\n", filter_flags);
8ccde88a 3488 priv->staging_rxon.filter_flags =
b481de9c 3489 cpu_to_le32(filter_flags);
e0158e61 3490 iwlcore_commit_rxon(priv);
b481de9c
ZY
3491 }
3492 }
3493 mutex_unlock(&priv->mutex);
3494
3495 return count;
3496}
3497
3498static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3499 store_filter_flags);
3500
c8b0e6e1 3501#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3502
3503static ssize_t show_measurement(struct device *d,
3504 struct device_attribute *attr, char *buf)
3505{
4a8a4322 3506 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3507 struct iwl_spectrum_notification measure_report;
b481de9c 3508 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3509 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3510 unsigned long flags;
3511
3512 spin_lock_irqsave(&priv->lock, flags);
3513 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3514 spin_unlock_irqrestore(&priv->lock, flags);
3515 return 0;
3516 }
3517 memcpy(&measure_report, &priv->measure_report, size);
3518 priv->measurement_status = 0;
3519 spin_unlock_irqrestore(&priv->lock, flags);
3520
3521 while (size && (PAGE_SIZE - len)) {
3522 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3523 PAGE_SIZE - len, 1);
3524 len = strlen(buf);
3525 if (PAGE_SIZE - len)
3526 buf[len++] = '\n';
3527
3528 ofs += 16;
3529 size -= min(size, 16U);
3530 }
3531
3532 return len;
3533}
3534
3535static ssize_t store_measurement(struct device *d,
3536 struct device_attribute *attr,
3537 const char *buf, size_t count)
3538{
4a8a4322 3539 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3540 struct ieee80211_measurement_params params = {
8ccde88a 3541 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3542 .start_time = cpu_to_le64(priv->last_tsf),
3543 .duration = cpu_to_le16(1),
3544 };
3545 u8 type = IWL_MEASURE_BASIC;
3546 u8 buffer[32];
3547 u8 channel;
3548
3549 if (count) {
3550 char *p = buffer;
3551 strncpy(buffer, buf, min(sizeof(buffer), count));
3552 channel = simple_strtoul(p, NULL, 0);
3553 if (channel)
3554 params.channel = channel;
3555
3556 p = buffer;
3557 while (*p && *p != ' ')
3558 p++;
3559 if (*p)
3560 type = simple_strtoul(p + 1, NULL, 0);
3561 }
3562
e1623446 3563 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3564 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3565 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3566
3567 return count;
3568}
3569
3570static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3571 show_measurement, store_measurement);
c8b0e6e1 3572#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 3573
b481de9c
ZY
3574static ssize_t store_retry_rate(struct device *d,
3575 struct device_attribute *attr,
3576 const char *buf, size_t count)
3577{
4a8a4322 3578 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3579
3580 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3581 if (priv->retry_rate <= 0)
3582 priv->retry_rate = 1;
3583
3584 return count;
3585}
3586
3587static ssize_t show_retry_rate(struct device *d,
3588 struct device_attribute *attr, char *buf)
3589{
4a8a4322 3590 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3591 return sprintf(buf, "%d", priv->retry_rate);
3592}
3593
3594static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3595 store_retry_rate);
3596
d25aabb0 3597
b481de9c
ZY
3598static ssize_t show_channels(struct device *d,
3599 struct device_attribute *attr, char *buf)
3600{
8318d78a
JB
3601 /* all this shit doesn't belong into sysfs anyway */
3602 return 0;
b481de9c
ZY
3603}
3604
3605static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3606
3607static ssize_t show_statistics(struct device *d,
3608 struct device_attribute *attr, char *buf)
3609{
4a8a4322 3610 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3611 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3612 u32 len = 0, ofs = 0;
f2c7e521 3613 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3614 int rc = 0;
3615
775a6e27 3616 if (!iwl_is_alive(priv))
b481de9c
ZY
3617 return -EAGAIN;
3618
3619 mutex_lock(&priv->mutex);
17f841cd 3620 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
3621 mutex_unlock(&priv->mutex);
3622
3623 if (rc) {
3624 len = sprintf(buf,
3625 "Error sending statistics request: 0x%08X\n", rc);
3626 return len;
3627 }
3628
3629 while (size && (PAGE_SIZE - len)) {
3630 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3631 PAGE_SIZE - len, 1);
3632 len = strlen(buf);
3633 if (PAGE_SIZE - len)
3634 buf[len++] = '\n';
3635
3636 ofs += 16;
3637 size -= min(size, 16U);
3638 }
3639
3640 return len;
3641}
3642
3643static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3644
3645static ssize_t show_antenna(struct device *d,
3646 struct device_attribute *attr, char *buf)
3647{
4a8a4322 3648 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3649
775a6e27 3650 if (!iwl_is_alive(priv))
b481de9c
ZY
3651 return -EAGAIN;
3652
7e4bca5e 3653 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3654}
3655
3656static ssize_t store_antenna(struct device *d,
3657 struct device_attribute *attr,
3658 const char *buf, size_t count)
3659{
7530f85f 3660 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3661 int ant;
b481de9c
ZY
3662
3663 if (count == 0)
3664 return 0;
3665
3666 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3667 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3668 return count;
3669 }
3670
3671 if ((ant >= 0) && (ant <= 2)) {
e1623446 3672 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3673 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3674 } else
e1623446 3675 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3676
3677
3678 return count;
3679}
3680
3681static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3682
3683static ssize_t show_status(struct device *d,
3684 struct device_attribute *attr, char *buf)
3685{
928841b1 3686 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3687 if (!iwl_is_alive(priv))
b481de9c
ZY
3688 return -EAGAIN;
3689 return sprintf(buf, "0x%08x\n", (int)priv->status);
3690}
3691
3692static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3693
3694static ssize_t dump_error_log(struct device *d,
3695 struct device_attribute *attr,
3696 const char *buf, size_t count)
3697{
928841b1 3698 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3699 char *p = (char *)buf;
3700
3701 if (p[0] == '1')
928841b1 3702 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3703
3704 return strnlen(buf, count);
3705}
3706
3707static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3708
b481de9c
ZY
3709/*****************************************************************************
3710 *
a96a27f9 3711 * driver setup and tear down
b481de9c
ZY
3712 *
3713 *****************************************************************************/
3714
4a8a4322 3715static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3716{
d21050c7 3717 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3718
3719 init_waitqueue_head(&priv->wait_command_queue);
3720
bb8c093b
CH
3721 INIT_WORK(&priv->up, iwl3945_bg_up);
3722 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3723 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3724 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3725 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3726 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3727 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3728 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3729 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3730 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3731 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3732
3733 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3734
3735 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3736 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3737}
3738
4a8a4322 3739static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3740{
bb8c093b 3741 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3742
e47eb6ad 3743 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3744 cancel_delayed_work(&priv->scan_check);
3745 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3746 cancel_work_sync(&priv->beacon_update);
3747}
3748
bb8c093b 3749static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3750 &dev_attr_antenna.attr,
3751 &dev_attr_channels.attr,
3752 &dev_attr_dump_errors.attr,
b481de9c
ZY
3753 &dev_attr_flags.attr,
3754 &dev_attr_filter_flags.attr,
c8b0e6e1 3755#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
3756 &dev_attr_measurement.attr,
3757#endif
b481de9c 3758 &dev_attr_retry_rate.attr,
b481de9c
ZY
3759 &dev_attr_statistics.attr,
3760 &dev_attr_status.attr,
3761 &dev_attr_temperature.attr,
b481de9c 3762 &dev_attr_tx_power.attr,
d08853a3 3763#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3764 &dev_attr_debug_level.attr,
3765#endif
b481de9c
ZY
3766 NULL
3767};
3768
bb8c093b 3769static struct attribute_group iwl3945_attribute_group = {
b481de9c 3770 .name = NULL, /* put in device directory */
bb8c093b 3771 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3772};
3773
bb8c093b
CH
3774static struct ieee80211_ops iwl3945_hw_ops = {
3775 .tx = iwl3945_mac_tx,
3776 .start = iwl3945_mac_start,
3777 .stop = iwl3945_mac_stop,
cbb6ab94 3778 .add_interface = iwl_mac_add_interface,
d8052319 3779 .remove_interface = iwl_mac_remove_interface,
4808368d 3780 .config = iwl_mac_config,
8ccde88a 3781 .configure_filter = iwl_configure_filter,
bb8c093b 3782 .set_key = iwl3945_mac_set_key,
aa89f31e 3783 .get_tx_stats = iwl_mac_get_tx_stats,
488829f1 3784 .conf_tx = iwl_mac_conf_tx,
bd564261 3785 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3786 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3787 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3788};
3789
e52119c5 3790static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3791{
3792 int ret;
e6148917 3793 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3794
3795 priv->retry_rate = 1;
3796 priv->ibss_beacon = NULL;
3797
3798 spin_lock_init(&priv->lock);
90a30a02
KA
3799 spin_lock_init(&priv->sta_lock);
3800 spin_lock_init(&priv->hcmd_lock);
3801
3802 INIT_LIST_HEAD(&priv->free_frames);
3803
3804 mutex_init(&priv->mutex);
3805
3806 /* Clear the driver's (not device's) station table */
c587de0b 3807 iwl_clear_stations_table(priv);
90a30a02 3808
90a30a02
KA
3809 priv->ieee_channels = NULL;
3810 priv->ieee_rates = NULL;
3811 priv->band = IEEE80211_BAND_2GHZ;
3812
3813 priv->iw_mode = NL80211_IFTYPE_STATION;
3814
3815 iwl_reset_qos(priv);
3816
3817 priv->qos_data.qos_active = 0;
3818 priv->qos_data.qos_cap.val = 0;
3819
3820 priv->rates_mask = IWL_RATES_MASK;
62ea9c5b 3821 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3822
e6148917
SO
3823 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3824 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3825 eeprom->version);
3826 ret = -EINVAL;
3827 goto err;
3828 }
3829 ret = iwl_init_channel_map(priv);
90a30a02
KA
3830 if (ret) {
3831 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3832 goto err;
3833 }
3834
e6148917
SO
3835 /* Set up txpower settings in driver for all channels */
3836 if (iwl3945_txpower_set_from_eeprom(priv)) {
3837 ret = -EIO;
3838 goto err_free_channel_map;
3839 }
3840
534166de 3841 ret = iwlcore_init_geos(priv);
90a30a02
KA
3842 if (ret) {
3843 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3844 goto err_free_channel_map;
3845 }
534166de
SO
3846 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3847
2a4ddaab
AK
3848 return 0;
3849
3850err_free_channel_map:
3851 iwl_free_channel_map(priv);
3852err:
3853 return ret;
3854}
3855
3856static int iwl3945_setup_mac(struct iwl_priv *priv)
3857{
3858 int ret;
3859 struct ieee80211_hw *hw = priv->hw;
3860
3861 hw->rate_control_algorithm = "iwl-3945-rs";
3862 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3863
3864 /* Tell mac80211 our characteristics */
3865 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b 3866 IEEE80211_HW_NOISE_DBM |
e312c24c
JB
3867 IEEE80211_HW_SPECTRUM_MGMT |
3868 IEEE80211_HW_SUPPORTS_PS |
3869 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3870
3871 hw->wiphy->interface_modes =
3872 BIT(NL80211_IFTYPE_STATION) |
3873 BIT(NL80211_IFTYPE_ADHOC);
3874
3875 hw->wiphy->custom_regulatory = true;
3876
37184244
LR
3877 /* Firmware does not support this */
3878 hw->wiphy->disable_beacon_hints = true;
3879
1ecf9fc1
JB
3880 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3881 /* we create the 802.11 header and a zero-length SSID element */
3882 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3883
2a4ddaab
AK
3884 /* Default value; 4 EDCA QOS priorities */
3885 hw->queues = 4;
3886
534166de
SO
3887 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3888 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3889 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3890
534166de
SO
3891 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3892 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3893 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3894
2a4ddaab
AK
3895 ret = ieee80211_register_hw(priv->hw);
3896 if (ret) {
3897 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3898 return ret;
3899 }
3900 priv->mac80211_registered = 1;
90a30a02 3901
2a4ddaab 3902 return 0;
90a30a02
KA
3903}
3904
bb8c093b 3905static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3906{
3907 int err = 0;
4a8a4322 3908 struct iwl_priv *priv;
b481de9c 3909 struct ieee80211_hw *hw;
c0f20d91 3910 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3911 struct iwl3945_eeprom *eeprom;
0359facc 3912 unsigned long flags;
b481de9c 3913
cee53ddb
KA
3914 /***********************
3915 * 1. Allocating HW data
3916 * ********************/
3917
b481de9c
ZY
3918 /* mac80211 allocates memory for this device instance, including
3919 * space for this driver's private structure */
90a30a02 3920 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3921 if (hw == NULL) {
a3139c59 3922 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3923 err = -ENOMEM;
3924 goto out;
3925 }
b481de9c 3926 priv = hw->priv;
90a30a02 3927 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3928
90a30a02
KA
3929 /*
3930 * Disabling hardware scan means that mac80211 will perform scans
3931 * "the hard way", rather than using device's scan.
3932 */
df878d8f 3933 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3934 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3935 iwl3945_hw_ops.hw_scan = NULL;
3936 }
3937
90a30a02 3938
e1623446 3939 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3940 priv->cfg = cfg;
3941 priv->pci_dev = pdev;
40cefda9 3942 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3943
d08853a3 3944#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3945 atomic_set(&priv->restrict_refcnt, 0);
3946#endif
20594eb0
WYG
3947 if (iwl_alloc_traffic_mem(priv))
3948 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3949
cee53ddb
KA
3950 /***************************
3951 * 2. Initializing PCI bus
3952 * *************************/
b481de9c
ZY
3953 if (pci_enable_device(pdev)) {
3954 err = -ENODEV;
3955 goto out_ieee80211_free_hw;
3956 }
3957
3958 pci_set_master(pdev);
3959
284901a9 3960 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3961 if (!err)
284901a9 3962 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3963 if (err) {
978785a3 3964 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
3965 goto out_pci_disable_device;
3966 }
3967
3968 pci_set_drvdata(pdev, priv);
3969 err = pci_request_regions(pdev, DRV_NAME);
3970 if (err)
3971 goto out_pci_disable_device;
6440adb5 3972
cee53ddb
KA
3973 /***********************
3974 * 3. Read REV Register
3975 * ********************/
b481de9c
ZY
3976 priv->hw_base = pci_iomap(pdev, 0, 0);
3977 if (!priv->hw_base) {
3978 err = -ENODEV;
3979 goto out_pci_release_regions;
3980 }
3981
e1623446 3982 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 3983 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3984 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 3985
cee53ddb
KA
3986 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3987 * PCI Tx retries from interfering with C3 CPU state */
3988 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 3989
a8b50a0a
MA
3990 /* this spin lock will be used in apm_ops.init and EEPROM access
3991 * we should init now
3992 */
3993 spin_lock_init(&priv->reg_lock);
3994
90a30a02
KA
3995 /* amp init */
3996 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 3997 if (err < 0) {
d5df2a16 3998 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
90a30a02 3999 goto out_iounmap;
cee53ddb 4000 }
b481de9c 4001
cee53ddb
KA
4002 /***********************
4003 * 4. Read EEPROM
4004 * ********************/
90a30a02 4005
cee53ddb 4006 /* Read the EEPROM */
e6148917 4007 err = iwl_eeprom_init(priv);
cee53ddb 4008 if (err) {
15b1687c 4009 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4010 goto out_iounmap;
cee53ddb
KA
4011 }
4012 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4013 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4014 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4015 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4016 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4017
cee53ddb
KA
4018 /***********************
4019 * 5. Setup HW Constants
4020 * ********************/
b481de9c 4021 /* Device-specific setup */
3832ec9d 4022 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4023 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4024 goto out_eeprom_free;
b481de9c
ZY
4025 }
4026
cee53ddb
KA
4027 /***********************
4028 * 6. Setup priv
4029 * ********************/
cee53ddb 4030
90a30a02 4031 err = iwl3945_init_drv(priv);
b481de9c 4032 if (err) {
90a30a02 4033 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4034 goto out_unset_hw_params;
b481de9c
ZY
4035 }
4036
978785a3
TW
4037 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4038 priv->cfg->name);
cee53ddb 4039
cee53ddb 4040 /***********************
09f9bf79 4041 * 7. Setup Services
cee53ddb
KA
4042 * ********************/
4043
4044 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4045 iwl_disable_interrupts(priv);
cee53ddb
KA
4046 spin_unlock_irqrestore(&priv->lock, flags);
4047
2663516d
HS
4048 pci_enable_msi(priv->pci_dev);
4049
ef850d7c
MA
4050 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4051 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4052 if (err) {
4053 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4054 goto out_disable_msi;
4055 }
4056
cee53ddb 4057 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4058 if (err) {
15b1687c 4059 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4060 goto out_release_irq;
849e0dce 4061 }
849e0dce 4062
8ccde88a
SO
4063 iwl_set_rxon_channel(priv,
4064 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4065 iwl3945_setup_deferred_work(priv);
4066 iwl3945_setup_rx_handlers(priv);
008a9e3e 4067 iwl_power_initialize(priv);
cee53ddb 4068
cee53ddb 4069 /*********************************
09f9bf79 4070 * 8. Setup and Register mac80211
cee53ddb
KA
4071 * *******************************/
4072
2a4ddaab 4073 iwl_enable_interrupts(priv);
b481de9c 4074
2a4ddaab
AK
4075 err = iwl3945_setup_mac(priv);
4076 if (err)
4077 goto out_remove_sysfs;
cee53ddb 4078
a75fbe8d
AK
4079 err = iwl_dbgfs_register(priv, DRV_NAME);
4080 if (err)
4081 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4082
2663516d
HS
4083 /* Start monitoring the killswitch */
4084 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4085 2 * HZ);
4086
b481de9c
ZY
4087 return 0;
4088
cee53ddb 4089 out_remove_sysfs:
c8f16138
RC
4090 destroy_workqueue(priv->workqueue);
4091 priv->workqueue = NULL;
cee53ddb 4092 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4093 out_release_irq:
2663516d 4094 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4095 out_disable_msi:
4096 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4097 iwlcore_free_geos(priv);
4098 iwl_free_channel_map(priv);
4099 out_unset_hw_params:
4100 iwl3945_unset_hw_params(priv);
4101 out_eeprom_free:
4102 iwl_eeprom_free(priv);
b481de9c
ZY
4103 out_iounmap:
4104 pci_iounmap(pdev, priv->hw_base);
4105 out_pci_release_regions:
4106 pci_release_regions(pdev);
4107 out_pci_disable_device:
b481de9c 4108 pci_set_drvdata(pdev, NULL);
623d563e 4109 pci_disable_device(pdev);
b481de9c 4110 out_ieee80211_free_hw:
20594eb0 4111 iwl_free_traffic_mem(priv);
d7c76f4c 4112 ieee80211_free_hw(priv->hw);
b481de9c
ZY
4113 out:
4114 return err;
4115}
4116
c83dbf68 4117static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4118{
4a8a4322 4119 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4120 unsigned long flags;
b481de9c
ZY
4121
4122 if (!priv)
4123 return;
4124
e1623446 4125 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4126
a75fbe8d
AK
4127 iwl_dbgfs_unregister(priv);
4128
b481de9c 4129 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4130
d552bfb6
KA
4131 if (priv->mac80211_registered) {
4132 ieee80211_unregister_hw(priv->hw);
4133 priv->mac80211_registered = 0;
4134 } else {
4135 iwl3945_down(priv);
4136 }
b481de9c 4137
c166b25a
BC
4138 /*
4139 * Make sure device is reset to low power before unloading driver.
4140 * This may be redundant with iwl_down(), but there are paths to
4141 * run iwl_down() without calling apm_ops.stop(), and there are
4142 * paths to avoid running iwl_down() at all before leaving driver.
4143 * This (inexpensive) call *makes sure* device is reset.
4144 */
4145 priv->cfg->ops->lib->apm_ops.stop(priv);
4146
0359facc
MA
4147 /* make sure we flush any pending irq or
4148 * tasklet for the driver
4149 */
4150 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4151 iwl_disable_interrupts(priv);
0359facc
MA
4152 spin_unlock_irqrestore(&priv->lock, flags);
4153
4154 iwl_synchronize_irq(priv);
4155
bb8c093b 4156 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4157
71d449b5 4158 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4159
bb8c093b 4160 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4161
4162 if (priv->rxq.bd)
df833b1d 4163 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4164 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4165
3832ec9d 4166 iwl3945_unset_hw_params(priv);
c587de0b 4167 iwl_clear_stations_table(priv);
b481de9c 4168
6ef89d0a
MA
4169 /*netif_stop_queue(dev); */
4170 flush_workqueue(priv->workqueue);
4171
bb8c093b 4172 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4173 * priv->workqueue... so we can't take down the workqueue
4174 * until now... */
4175 destroy_workqueue(priv->workqueue);
4176 priv->workqueue = NULL;
20594eb0 4177 iwl_free_traffic_mem(priv);
b481de9c 4178
2663516d
HS
4179 free_irq(pdev->irq, priv);
4180 pci_disable_msi(pdev);
4181
b481de9c
ZY
4182 pci_iounmap(pdev, priv->hw_base);
4183 pci_release_regions(pdev);
4184 pci_disable_device(pdev);
4185 pci_set_drvdata(pdev, NULL);
4186
e6148917 4187 iwl_free_channel_map(priv);
534166de 4188 iwlcore_free_geos(priv);
805cee5b 4189 kfree(priv->scan);
b481de9c
ZY
4190 if (priv->ibss_beacon)
4191 dev_kfree_skb(priv->ibss_beacon);
4192
4193 ieee80211_free_hw(priv->hw);
4194}
4195
b481de9c
ZY
4196
4197/*****************************************************************************
4198 *
4199 * driver and module entry point
4200 *
4201 *****************************************************************************/
4202
bb8c093b 4203static struct pci_driver iwl3945_driver = {
b481de9c 4204 .name = DRV_NAME,
bb8c093b
CH
4205 .id_table = iwl3945_hw_card_ids,
4206 .probe = iwl3945_pci_probe,
4207 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4208#ifdef CONFIG_PM
6da3a13e
WYG
4209 .suspend = iwl_pci_suspend,
4210 .resume = iwl_pci_resume,
b481de9c
ZY
4211#endif
4212};
4213
bb8c093b 4214static int __init iwl3945_init(void)
b481de9c
ZY
4215{
4216
4217 int ret;
4218 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4219 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4220
4221 ret = iwl3945_rate_control_register();
4222 if (ret) {
a3139c59
SO
4223 printk(KERN_ERR DRV_NAME
4224 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4225 return ret;
4226 }
4227
bb8c093b 4228 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4229 if (ret) {
a3139c59 4230 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4231 goto error_register;
b481de9c 4232 }
b481de9c
ZY
4233
4234 return ret;
897e1cf2 4235
897e1cf2
RC
4236error_register:
4237 iwl3945_rate_control_unregister();
4238 return ret;
b481de9c
ZY
4239}
4240
bb8c093b 4241static void __exit iwl3945_exit(void)
b481de9c 4242{
bb8c093b 4243 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4244 iwl3945_rate_control_unregister();
b481de9c
ZY
4245}
4246
a0987a8d 4247MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4248
4e30cb69 4249module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
b481de9c 4250MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4e30cb69 4251module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
9c74d9fb
SO
4252MODULE_PARM_DESC(swcrypto,
4253 "using software crypto (default 1 [software])\n");
a562a9dd 4254#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4255module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
b481de9c 4256MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4257#endif
4e30cb69
WYG
4258module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
4259 int, S_IRUGO);
b481de9c 4260MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4e30cb69 4261module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
af48d048
SO
4262MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4263
bb8c093b
CH
4264module_exit(iwl3945_exit);
4265module_init(iwl3945_init);