]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/net/wireless/iwlwifi/iwl3945-base.c
iwl3945: use iwl3945_tx_cmd instead of iwl_tx_cmd
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY
1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY
30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY
40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
ZY
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO
49#define DRV_NAME "iwl3945"
50
dbb6654c
WT
51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
b481de9c
ZY
54#include "iwl-3945.h"
55#include "iwl-helpers.h"
5747d47f 56#include "iwl-core.h"
d20b3c65 57#include "iwl-dev.h"
b481de9c 58
4a8a4322 59static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
188cf6c7 60 struct iwl_tx_queue *txq);
416e1438 61
b481de9c
ZY
62/*
63 * module name, copyright, version, etc.
b481de9c
ZY
64 */
65
66#define DRV_DESCRIPTION \
67"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
68
c8b0e6e1 69#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
70#define VD "d"
71#else
72#define VD
73#endif
74
c8b0e6e1 75#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
76#define VS "s"
77#else
78#define VS
79#endif
80
eaa686c3 81#define IWL39_VERSION "1.2.26k" VD VS
eb7ae89c 82#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
a7b75207 83#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 84#define DRV_VERSION IWL39_VERSION
b481de9c 85
b481de9c
ZY
86
87MODULE_DESCRIPTION(DRV_DESCRIPTION);
88MODULE_VERSION(DRV_VERSION);
a7b75207 89MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
ZY
90MODULE_LICENSE("GPL");
91
df878d8f
KA
92 /* module parameters */
93struct iwl_mod_params iwl3945_mod_params = {
94 .num_of_queues = IWL39_MAX_NUM_QUEUES,
95 /* the rest are 0 by default */
96};
97
b481de9c
ZY
98/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
99 * DMA services
100 *
101 * Theory of operation
102 *
6440adb5
BC
103 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
104 * of buffer descriptors, each of which points to one or more data buffers for
105 * the device to read from or fill. Driver and device exchange status of each
106 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
107 * entries in each circular buffer, to protect against confusing empty and full
108 * queue states.
109 *
110 * The device reads or writes the data in the queues via the device's several
111 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY
112 *
113 * For Tx queue, there are low mark and high mark limits. If, after queuing
114 * the packet for Tx, free space become < low mark, Tx queue stopped. When
115 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
116 * Tx queue resumed.
117 *
6440adb5
BC
118 * The 3945 operates with six queues: One receive queue, one transmit queue
119 * (#4) for sending commands to the device firmware, and four transmit queues
120 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY
121 ***************************************************/
122
d20b3c65 123int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
b481de9c 124{
fc4b6853
TW
125 return q->write_ptr > q->read_ptr ?
126 (i >= q->read_ptr && i < q->write_ptr) :
127 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY
128}
129
6440adb5
BC
130/**
131 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
132 */
4a8a4322 133static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
b481de9c
ZY
134 int count, int slots_num, u32 id)
135{
136 q->n_bd = count;
137 q->n_window = slots_num;
138 q->id = id;
139
c54b679d
TW
140 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
141 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY
142 BUG_ON(!is_power_of_2(count));
143
144 /* slots_num must be power-of-two size, otherwise
145 * get_cmd_index is broken. */
146 BUG_ON(!is_power_of_2(slots_num));
147
148 q->low_mark = q->n_window / 4;
149 if (q->low_mark < 4)
150 q->low_mark = 4;
151
152 q->high_mark = q->n_window / 8;
153 if (q->high_mark < 2)
154 q->high_mark = 2;
155
fc4b6853 156 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY
157
158 return 0;
159}
160
6440adb5
BC
161/**
162 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
163 */
4a8a4322 164static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
188cf6c7 165 struct iwl_tx_queue *txq, u32 id)
b481de9c
ZY
166{
167 struct pci_dev *dev = priv->pci_dev;
168
6440adb5
BC
169 /* Driver private data, only for Tx (not command) queues,
170 * not shared with device. */
b481de9c
ZY
171 if (id != IWL_CMD_QUEUE_NUM) {
172 txq->txb = kmalloc(sizeof(txq->txb[0]) *
173 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
174 if (!txq->txb) {
15b1687c 175 IWL_ERR(priv, "kmalloc for auxiliary BD "
b481de9c
ZY
176 "structures failed\n");
177 goto error;
178 }
179 } else
180 txq->txb = NULL;
181
6440adb5
BC
182 /* Circular buffer of transmit frame descriptors (TFDs),
183 * shared with device */
188cf6c7
SO
184 txq->tfds39 = pci_alloc_consistent(dev,
185 sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
b481de9c
ZY
186 &txq->q.dma_addr);
187
188cf6c7 188 if (!txq->tfds39) {
15b1687c 189 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
188cf6c7 190 sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
b481de9c
ZY
191 goto error;
192 }
193 txq->q.id = id;
194
195 return 0;
196
197 error:
3ac7f146
TW
198 kfree(txq->txb);
199 txq->txb = NULL;
b481de9c
ZY
200
201 return -ENOMEM;
202}
203
6440adb5
BC
204/**
205 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
206 */
4a8a4322 207int iwl3945_tx_queue_init(struct iwl_priv *priv,
188cf6c7 208 struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c 209{
188cf6c7 210 int len, i;
b481de9c
ZY
211 int rc = 0;
212
6440adb5
BC
213 /*
214 * Alloc buffer array for commands (Tx or other types of commands).
215 * For the command queue (#4), allocate command space + one big
216 * command for scan, since scan command is very huge; the system will
217 * not have two scans at the same time, so only one is needed.
218 * For data Tx queues (all other queues), no super-size command
219 * space is needed.
220 */
188cf6c7
SO
221 len = sizeof(struct iwl_cmd);
222 for (i = 0; i <= slots_num; i++) {
223 if (i == slots_num) {
224 if (txq_id == IWL_CMD_QUEUE_NUM)
225 len += IWL_MAX_SCAN_SIZE;
226 else
227 continue;
228 }
229
230 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
231 if (!txq->cmd[i])
232 goto err;
233 }
b481de9c 234
6440adb5 235 /* Alloc driver data array and TFD circular buffer */
bb8c093b 236 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
188cf6c7
SO
237 if (rc)
238 goto err;
b481de9c 239
b481de9c
ZY
240 txq->need_update = 0;
241
242 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 243 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 244 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
BC
245
246 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 247 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 248
6440adb5 249 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 250 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY
251
252 return 0;
188cf6c7
SO
253err:
254 for (i = 0; i < slots_num; i++) {
255 kfree(txq->cmd[i]);
256 txq->cmd[i] = NULL;
257 }
258
259 if (txq_id == IWL_CMD_QUEUE_NUM) {
260 kfree(txq->cmd[slots_num]);
261 txq->cmd[slots_num] = NULL;
262 }
263 return -ENOMEM;
b481de9c
ZY
264}
265
266/**
bb8c093b 267 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY
268 * @txq: Transmit queue to deallocate.
269 *
270 * Empty queue by removing and destroying all BD's.
6440adb5
BC
271 * Free all buffers.
272 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 273 */
188cf6c7 274void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 275{
d20b3c65 276 struct iwl_queue *q = &txq->q;
b481de9c 277 struct pci_dev *dev = priv->pci_dev;
188cf6c7 278 int len, i;
b481de9c
ZY
279
280 if (q->n_bd == 0)
281 return;
282
283 /* first, empty all BD's */
fc4b6853 284 for (; q->write_ptr != q->read_ptr;
c54b679d 285 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 286 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 287
c2d79b48 288 len = sizeof(struct iwl_cmd) * q->n_window;
b481de9c
ZY
289 if (q->id == IWL_CMD_QUEUE_NUM)
290 len += IWL_MAX_SCAN_SIZE;
291
6440adb5 292 /* De-alloc array of command/tx buffers */
188cf6c7
SO
293 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
294 kfree(txq->cmd[i]);
b481de9c 295
6440adb5 296 /* De-alloc circular buffer of TFDs */
b481de9c 297 if (txq->q.n_bd)
dbb6654c 298 pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
188cf6c7 299 txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
b481de9c 300
6440adb5 301 /* De-alloc array of per-TFD driver data */
3ac7f146
TW
302 kfree(txq->txb);
303 txq->txb = NULL;
b481de9c 304
6440adb5 305 /* 0-fill queue descriptor structure */
b481de9c
ZY
306 memset(txq, 0, sizeof(*txq));
307}
308
b481de9c 309/*************** STATION TABLE MANAGEMENT ****
9fbab516 310 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY
311 * the functionality provided here
312 */
313
314/**************************************************************/
01ebd063 315#if 0 /* temporary disable till we add real remove station */
6440adb5
BC
316/**
317 * iwl3945_remove_station - Remove driver's knowledge of station.
318 *
319 * NOTE: This does not remove station from device's station table.
320 */
4a8a4322 321static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY
322{
323 int index = IWL_INVALID_STATION;
324 int i;
325 unsigned long flags;
326
327 spin_lock_irqsave(&priv->sta_lock, flags);
328
329 if (is_ap)
330 index = IWL_AP_ID;
331 else if (is_broadcast_ether_addr(addr))
3832ec9d 332 index = priv->hw_params.bcast_sta_id;
b481de9c 333 else
3832ec9d 334 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
f2c7e521
AK
335 if (priv->stations_39[i].used &&
336 !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
b481de9c
ZY
337 addr)) {
338 index = i;
339 break;
340 }
341
342 if (unlikely(index == IWL_INVALID_STATION))
343 goto out;
344
f2c7e521
AK
345 if (priv->stations_39[index].used) {
346 priv->stations_39[index].used = 0;
b481de9c
ZY
347 priv->num_stations--;
348 }
349
350 BUG_ON(priv->num_stations < 0);
351
352out:
353 spin_unlock_irqrestore(&priv->sta_lock, flags);
354 return 0;
355}
556f8db7 356#endif
6440adb5
BC
357
358/**
359 * iwl3945_clear_stations_table - Clear the driver's station table
360 *
361 * NOTE: This does not clear or otherwise alter the device's station table.
362 */
4a8a4322 363static void iwl3945_clear_stations_table(struct iwl_priv *priv)
b481de9c
ZY
364{
365 unsigned long flags;
366
367 spin_lock_irqsave(&priv->sta_lock, flags);
368
369 priv->num_stations = 0;
f2c7e521 370 memset(priv->stations_39, 0, sizeof(priv->stations_39));
b481de9c
ZY
371
372 spin_unlock_irqrestore(&priv->sta_lock, flags);
373}
374
6440adb5
BC
375/**
376 * iwl3945_add_station - Add station to station tables in driver and device
377 */
4a8a4322 378u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY
379{
380 int i;
381 int index = IWL_INVALID_STATION;
bb8c093b 382 struct iwl3945_station_entry *station;
b481de9c 383 unsigned long flags_spin;
c14c521e 384 u8 rate;
b481de9c
ZY
385
386 spin_lock_irqsave(&priv->sta_lock, flags_spin);
387 if (is_ap)
388 index = IWL_AP_ID;
389 else if (is_broadcast_ether_addr(addr))
3832ec9d 390 index = priv->hw_params.bcast_sta_id;
b481de9c 391 else
3832ec9d 392 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
f2c7e521 393 if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
b481de9c
ZY
394 addr)) {
395 index = i;
396 break;
397 }
398
f2c7e521 399 if (!priv->stations_39[i].used &&
b481de9c
ZY
400 index == IWL_INVALID_STATION)
401 index = i;
402 }
403
01ebd063 404 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY
405 since they have different meaning */
406 if (unlikely(index == IWL_INVALID_STATION)) {
407 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
408 return index;
409 }
410
f2c7e521
AK
411 if (priv->stations_39[index].used &&
412 !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
b481de9c
ZY
413 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
414 return index;
415 }
416
e174961c 417 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
f2c7e521 418 station = &priv->stations_39[index];
b481de9c
ZY
419 station->used = 1;
420 priv->num_stations++;
421
6440adb5 422 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 423 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY
424 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
425 station->sta.mode = 0;
426 station->sta.sta.sta_id = index;
427 station->sta.station_flags = 0;
428
8318d78a 429 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW
430 rate = IWL_RATE_6M_PLCP;
431 else
432 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY
433
434 /* Turn on both antennas for the station... */
435 station->sta.rate_n_flags =
bb8c093b 436 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e 437
b481de9c 438 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
BC
439
440 /* Add station to device's station table */
bb8c093b 441 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY
442 return index;
443
444}
445
b481de9c
ZY
446
447/*************** HOST COMMAND QUEUE FUNCTIONS *****/
448
c3056065 449#define IWL_CMD(x) case x: return #x
b481de9c
ZY
450#define HOST_COMPLETE_TIMEOUT (HZ / 2)
451
452/**
bb8c093b 453 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY
454 * @priv: device private data point
455 * @cmd: a point to the ucode command structure
456 *
457 * The function returns < 0 values to indicate the operation is
458 * failed. On success, it turns the index (> 0) of command in the
459 * command queue.
460 */
c2d79b48 461static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 462{
188cf6c7 463 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
d20b3c65 464 struct iwl_queue *q = &txq->q;
dbb6654c 465 struct iwl3945_tfd *tfd;
c2d79b48 466 struct iwl_cmd *out_cmd;
b481de9c
ZY
467 u32 idx;
468 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
469 dma_addr_t phys_addr;
470 int pad;
188cf6c7 471 int ret, len;
b481de9c
ZY
472 unsigned long flags;
473
474 /* If any of the command structures end up being larger than
475 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
476 * we will need to increase the size of the TFD entries */
c2d79b48 477 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
b481de9c
ZY
478 !(cmd->meta.flags & CMD_SIZE_HUGE));
479
c342a1b9 480
775a6e27 481 if (iwl_is_rfkill(priv)) {
c342a1b9
GG
482 IWL_DEBUG_INFO("Not sending command - RF KILL");
483 return -EIO;
484 }
485
d20b3c65 486 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
15b1687c 487 IWL_ERR(priv, "No space for Tx\n");
b481de9c
ZY
488 return -ENOSPC;
489 }
490
491 spin_lock_irqsave(&priv->hcmd_lock, flags);
492
188cf6c7 493 tfd = &txq->tfds39[q->write_ptr];
b481de9c
ZY
494 memset(tfd, 0, sizeof(*tfd));
495
fc4b6853 496 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
188cf6c7 497 out_cmd = txq->cmd[idx];
b481de9c
ZY
498
499 out_cmd->hdr.cmd = cmd->id;
500 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
501 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
502
503 /* At this point, the out_cmd now has all of the incoming cmd
504 * information */
505
506 out_cmd->hdr.flags = 0;
507 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 508 INDEX_TO_SEQ(q->write_ptr));
b481de9c 509 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
600c0e11 510 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
b481de9c 511
188cf6c7
SO
512 len = (idx == TFD_CMD_SLOTS) ?
513 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
514
515 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
516 len, PCI_DMA_TODEVICE);
517 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
518 pci_unmap_len_set(&out_cmd->meta, len, len);
519 phys_addr += offsetof(struct iwl_cmd, hdr);
520
bb8c093b 521 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY
522
523 pad = U32_PAD(cmd->len);
dbb6654c 524 tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
b481de9c
ZY
525
526 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
527 "%d bytes at %d[%d]:%d\n",
528 get_cmd_string(out_cmd->hdr.cmd),
529 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 530 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY
531
532 txq->need_update = 1;
6440adb5
BC
533
534 /* Increment and update queue's write index */
c54b679d 535 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 536 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
537
538 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
539 return ret ? ret : idx;
540}
541
c2d79b48
WT
542static int iwl3945_send_cmd_async(struct iwl_priv *priv,
543 struct iwl_host_cmd *cmd)
b481de9c
ZY
544{
545 int ret;
546
547 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
548
549 /* An asynchronous command can not expect an SKB to be set. */
550 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
551
552 /* An asynchronous command MUST have a callback. */
553 BUG_ON(!cmd->meta.u.callback);
554
555 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
556 return -EBUSY;
557
bb8c093b 558 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 559 if (ret < 0) {
15b1687c
WT
560 IWL_ERR(priv,
561 "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
562 get_cmd_string(cmd->id), ret);
b481de9c
ZY
563 return ret;
564 }
565 return 0;
566}
567
c2d79b48
WT
568static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
569 struct iwl_host_cmd *cmd)
b481de9c
ZY
570{
571 int cmd_idx;
572 int ret;
b481de9c
ZY
573
574 BUG_ON(cmd->meta.flags & CMD_ASYNC);
575
576 /* A synchronous command can not have a callback set. */
577 BUG_ON(cmd->meta.u.callback != NULL);
578
e5472978 579 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
15b1687c
WT
580 IWL_ERR(priv,
581 "Error sending %s: Already sending a host command\n",
582 get_cmd_string(cmd->id));
e5472978
TW
583 ret = -EBUSY;
584 goto out;
b481de9c
ZY
585 }
586
587 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
588
589 if (cmd->meta.flags & CMD_WANT_SKB)
590 cmd->meta.source = &cmd->meta;
591
bb8c093b 592 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY
593 if (cmd_idx < 0) {
594 ret = cmd_idx;
15b1687c
WT
595 IWL_ERR(priv,
596 "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
597 get_cmd_string(cmd->id), ret);
b481de9c
ZY
598 goto out;
599 }
600
601 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
602 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
603 HOST_COMPLETE_TIMEOUT);
604 if (!ret) {
605 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
15b1687c 606 IWL_ERR(priv, "Error sending %s: time out after %dms\n",
b481de9c
ZY
607 get_cmd_string(cmd->id),
608 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
609
610 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
611 ret = -ETIMEDOUT;
612 goto cancel;
613 }
614 }
615
616 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
617 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
618 get_cmd_string(cmd->id));
619 ret = -ECANCELED;
620 goto fail;
621 }
622 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
623 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
624 get_cmd_string(cmd->id));
625 ret = -EIO;
626 goto fail;
627 }
628 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
15b1687c 629 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
b481de9c
ZY
630 get_cmd_string(cmd->id));
631 ret = -EIO;
73e1a65d 632 goto cancel;
b481de9c
ZY
633 }
634
635 ret = 0;
636 goto out;
637
638cancel:
639 if (cmd->meta.flags & CMD_WANT_SKB) {
c2d79b48 640 struct iwl_cmd *qcmd;
b481de9c
ZY
641
642 /* Cancel the CMD_WANT_SKB flag for the cmd in the
643 * TX cmd queue. Otherwise in case the cmd comes
644 * in later, it will possibly set an invalid
645 * address (cmd->meta.source). */
188cf6c7 646 qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
b481de9c
ZY
647 qcmd->meta.flags &= ~CMD_WANT_SKB;
648 }
649fail:
650 if (cmd->meta.u.skb) {
651 dev_kfree_skb_any(cmd->meta.u.skb);
652 cmd->meta.u.skb = NULL;
653 }
654out:
e5472978 655 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY
656 return ret;
657}
658
c2d79b48 659int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 660{
b481de9c 661 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 662 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 663
bb8c093b 664 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY
665}
666
4a8a4322 667int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
b481de9c 668{
c2d79b48 669 struct iwl_host_cmd cmd = {
b481de9c
ZY
670 .id = id,
671 .len = len,
672 .data = data,
673 };
674
bb8c093b 675 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
676}
677
4a8a4322 678static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
b481de9c 679{
c2d79b48 680 struct iwl_host_cmd cmd = {
b481de9c
ZY
681 .id = id,
682 .len = sizeof(val),
683 .data = &val,
684 };
685
bb8c093b 686 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
687}
688
4a8a4322 689int iwl3945_send_statistics_request(struct iwl_priv *priv)
b481de9c 690{
bb8c093b 691 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY
692}
693
b481de9c 694/**
bb8c093b 695 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB
696 * @band: 2.4 or 5 GHz band
697 * @channel: Any channel valid for the requested band
b481de9c 698
8318d78a 699 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY
700 *
701 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 702 * in the staging RXON flag structure based on the band
b481de9c 703 */
4a8a4322 704static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
8318d78a
JB
705 enum ieee80211_band band,
706 u16 channel)
b481de9c 707{
8318d78a 708 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 709 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 710 channel, band);
b481de9c
ZY
711 return -EINVAL;
712 }
713
f2c7e521 714 if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
8318d78a 715 (priv->band == band))
b481de9c
ZY
716 return 0;
717
f2c7e521 718 priv->staging39_rxon.channel = cpu_to_le16(channel);
8318d78a 719 if (band == IEEE80211_BAND_5GHZ)
f2c7e521 720 priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
b481de9c 721 else
f2c7e521 722 priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
b481de9c 723
8318d78a 724 priv->band = band;
b481de9c 725
8318d78a 726 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY
727
728 return 0;
729}
730
731/**
bb8c093b 732 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY
733 *
734 * NOTE: This is really only useful during development and can eventually
735 * be #ifdef'd out once the driver is stable and folks aren't actively
736 * making changes
737 */
4a8a4322 738static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
b481de9c
ZY
739{
740 int error = 0;
741 int counter = 1;
f2c7e521 742 struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
b481de9c
ZY
743
744 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
745 error |= le32_to_cpu(rxon->flags &
746 (RXON_FLG_TGJ_NARROW_BAND_MSK |
747 RXON_FLG_RADAR_DETECT_MSK));
748 if (error)
39aadf8c 749 IWL_WARN(priv, "check 24G fields %d | %d\n",
b481de9c
ZY
750 counter++, error);
751 } else {
752 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
753 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
754 if (error)
39aadf8c 755 IWL_WARN(priv, "check 52 fields %d | %d\n",
b481de9c
ZY
756 counter++, error);
757 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
758 if (error)
39aadf8c 759 IWL_WARN(priv, "check 52 CCK %d | %d\n",
b481de9c
ZY
760 counter++, error);
761 }
762 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
763 if (error)
39aadf8c 764 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
b481de9c
ZY
765
766 /* make sure basic rates 6Mbps and 1Mbps are supported */
767 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
768 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
769 if (error)
39aadf8c 770 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
b481de9c
ZY
771
772 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
773 if (error)
39aadf8c 774 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
b481de9c
ZY
775
776 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
777 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
778 if (error)
39aadf8c 779 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
b481de9c
ZY
780 counter++, error);
781
782 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
783 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
784 if (error)
39aadf8c 785 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
b481de9c
ZY
786 counter++, error);
787
788 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
789 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
790 if (error)
39aadf8c 791 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
b481de9c
ZY
792 counter++, error);
793
794 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
795 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
796 RXON_FLG_ANT_A_MSK)) == 0);
797 if (error)
39aadf8c 798 IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
b481de9c
ZY
799
800 if (error)
39aadf8c 801 IWL_WARN(priv, "Tuning to channel %d\n",
b481de9c
ZY
802 le16_to_cpu(rxon->channel));
803
804 if (error) {
15b1687c 805 IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
b481de9c
ZY
806 return -1;
807 }
808 return 0;
809}
810
811/**
9fbab516 812 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 813 * @priv: staging_rxon is compared to active_rxon
b481de9c 814 *
9fbab516
BC
815 * If the RXON structure is changing enough to require a new tune,
816 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
817 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 818 */
4a8a4322 819static int iwl3945_full_rxon_required(struct iwl_priv *priv)
b481de9c
ZY
820{
821
822 /* These items are only settable from the full RXON command */
5d1e2325 823 if (!(iwl3945_is_associated(priv)) ||
f2c7e521
AK
824 compare_ether_addr(priv->staging39_rxon.bssid_addr,
825 priv->active39_rxon.bssid_addr) ||
826 compare_ether_addr(priv->staging39_rxon.node_addr,
827 priv->active39_rxon.node_addr) ||
828 compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
829 priv->active39_rxon.wlap_bssid_addr) ||
830 (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
831 (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
832 (priv->staging39_rxon.air_propagation !=
833 priv->active39_rxon.air_propagation) ||
834 (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
b481de9c
ZY
835 return 1;
836
837 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
838 * be updated with the RXON_ASSOC command -- however only some
839 * flag transitions are allowed using RXON_ASSOC */
840
841 /* Check if we are not switching bands */
f2c7e521
AK
842 if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
843 (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
b481de9c
ZY
844 return 1;
845
846 /* Check if we are switching association toggle */
f2c7e521
AK
847 if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
848 (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
b481de9c
ZY
849 return 1;
850
851 return 0;
852}
853
4a8a4322 854static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
b481de9c
ZY
855{
856 int rc = 0;
3d24a9f7 857 struct iwl_rx_packet *res = NULL;
bb8c093b 858 struct iwl3945_rxon_assoc_cmd rxon_assoc;
c2d79b48 859 struct iwl_host_cmd cmd = {
b481de9c
ZY
860 .id = REPLY_RXON_ASSOC,
861 .len = sizeof(rxon_assoc),
862 .meta.flags = CMD_WANT_SKB,
863 .data = &rxon_assoc,
864 };
f2c7e521
AK
865 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
866 const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
b481de9c
ZY
867
868 if ((rxon1->flags == rxon2->flags) &&
869 (rxon1->filter_flags == rxon2->filter_flags) &&
870 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
871 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
872 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
873 return 0;
874 }
875
f2c7e521
AK
876 rxon_assoc.flags = priv->staging39_rxon.flags;
877 rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
878 rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
879 rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
b481de9c
ZY
880 rxon_assoc.reserved = 0;
881
bb8c093b 882 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
883 if (rc)
884 return rc;
885
3d24a9f7 886 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 887 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 888 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
b481de9c
ZY
889 rc = -EIO;
890 }
891
892 priv->alloc_rxb_skb--;
893 dev_kfree_skb_any(cmd.meta.u.skb);
894
895 return rc;
896}
897
898/**
bb8c093b 899 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 900 *
01ebd063 901 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY
902 * the active_rxon structure is updated with the new data. This
903 * function correctly transitions out of the RXON_ASSOC_MSK state if
904 * a HW tune is required based on the RXON structure changes.
905 */
4a8a4322 906static int iwl3945_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY
907{
908 /* cast away the const for active_rxon in this function */
f2c7e521 909 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
b481de9c
ZY
910 int rc = 0;
911
775a6e27 912 if (!iwl_is_alive(priv))
b481de9c
ZY
913 return -1;
914
915 /* always get timestamp with Rx frame */
f2c7e521 916 priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c
ZY
917
918 /* select antenna */
f2c7e521 919 priv->staging39_rxon.flags &=
b481de9c 920 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
f2c7e521 921 priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
b481de9c 922
a3139c59 923 rc = iwl3945_check_rxon_cmd(priv);
b481de9c 924 if (rc) {
15b1687c 925 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY
926 return -EINVAL;
927 }
928
929 /* If we don't need to send a full RXON, we can use
bb8c093b 930 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 931 * and other flags for the current radio configuration. */
bb8c093b
CH
932 if (!iwl3945_full_rxon_required(priv)) {
933 rc = iwl3945_send_rxon_assoc(priv);
b481de9c 934 if (rc) {
15b1687c 935 IWL_ERR(priv, "Error setting RXON_ASSOC "
b481de9c
ZY
936 "configuration (%d).\n", rc);
937 return rc;
938 }
939
f2c7e521 940 memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
b481de9c
ZY
941
942 return 0;
943 }
944
945 /* If we are currently associated and the new config requires
946 * an RXON_ASSOC and the new config wants the associated mask enabled,
947 * we must clear the associated from the active configuration
948 * before we apply the new config */
bb8c093b 949 if (iwl3945_is_associated(priv) &&
f2c7e521 950 (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
b481de9c
ZY
951 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
952 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
953
bb8c093b
CH
954 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
955 sizeof(struct iwl3945_rxon_cmd),
f2c7e521 956 &priv->active39_rxon);
b481de9c
ZY
957
958 /* If the mask clearing failed then we set
959 * active_rxon back to what it was previously */
960 if (rc) {
961 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 962 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
b481de9c
ZY
963 "configuration (%d).\n", rc);
964 return rc;
965 }
b481de9c
ZY
966 }
967
968 IWL_DEBUG_INFO("Sending RXON\n"
969 "* with%s RXON_FILTER_ASSOC_MSK\n"
970 "* channel = %d\n"
e174961c 971 "* bssid = %pM\n",
f2c7e521 972 ((priv->staging39_rxon.filter_flags &
b481de9c 973 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
f2c7e521 974 le16_to_cpu(priv->staging39_rxon.channel),
e174961c 975 priv->staging_rxon.bssid_addr);
b481de9c
ZY
976
977 /* Apply the new configuration */
bb8c093b 978 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
f2c7e521 979 sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
b481de9c 980 if (rc) {
15b1687c 981 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
b481de9c
ZY
982 return rc;
983 }
984
f2c7e521 985 memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
b481de9c 986
bb8c093b 987 iwl3945_clear_stations_table(priv);
556f8db7 988
b481de9c
ZY
989 /* If we issue a new RXON command which required a tune then we must
990 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 991 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c 992 if (rc) {
15b1687c 993 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
b481de9c
ZY
994 return rc;
995 }
996
997 /* Add the broadcast address so we can send broadcast frames */
b5323d36 998 if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
b481de9c 999 IWL_INVALID_STATION) {
15b1687c 1000 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
b481de9c
ZY
1001 return -EIO;
1002 }
1003
1004 /* If we have set the ASSOC_MSK and we are in BSS mode then
1005 * add the IWL_AP_ID to the station rate table */
bb8c093b 1006 if (iwl3945_is_associated(priv) &&
05c914fe 1007 (priv->iw_mode == NL80211_IFTYPE_STATION))
f2c7e521 1008 if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
b481de9c 1009 == IWL_INVALID_STATION) {
15b1687c 1010 IWL_ERR(priv, "Error adding AP address for transmit\n");
b481de9c
ZY
1011 return -EIO;
1012 }
1013
8318d78a 1014 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY
1015 rc = iwl3945_init_hw_rate_table(priv);
1016 if (rc) {
15b1687c 1017 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
b481de9c
ZY
1018 return -EIO;
1019 }
1020
1021 return 0;
1022}
1023
4a8a4322 1024static int iwl3945_send_bt_config(struct iwl_priv *priv)
b481de9c 1025{
4c897253 1026 struct iwl_bt_cmd bt_cmd = {
b481de9c
ZY
1027 .flags = 3,
1028 .lead_time = 0xAA,
1029 .max_kill = 1,
1030 .kill_ack_mask = 0,
1031 .kill_cts_mask = 0,
1032 };
1033
bb8c093b 1034 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
4c897253 1035 sizeof(bt_cmd), &bt_cmd);
b481de9c
ZY
1036}
1037
4a8a4322 1038static int iwl3945_send_scan_abort(struct iwl_priv *priv)
b481de9c
ZY
1039{
1040 int rc = 0;
3d24a9f7 1041 struct iwl_rx_packet *res;
c2d79b48 1042 struct iwl_host_cmd cmd = {
b481de9c
ZY
1043 .id = REPLY_SCAN_ABORT_CMD,
1044 .meta.flags = CMD_WANT_SKB,
1045 };
1046
1047 /* If there isn't a scan actively going on in the hardware
1048 * then we are in between scan bands and not actually
1049 * actively scanning, so don't send the abort command */
1050 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1051 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1052 return 0;
1053 }
1054
bb8c093b 1055 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1056 if (rc) {
1057 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1058 return rc;
1059 }
1060
3d24a9f7 1061 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1062 if (res->u.status != CAN_ABORT_STATUS) {
1063 /* The scan abort will return 1 for success or
1064 * 2 for "failure". A failure condition can be
1065 * due to simply not being in an active scan which
1066 * can occur if we send the scan abort before we
1067 * the microcode has notified us that a scan is
1068 * completed. */
1069 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1070 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1071 clear_bit(STATUS_SCAN_HW, &priv->status);
1072 }
1073
1074 dev_kfree_skb_any(cmd.meta.u.skb);
1075
1076 return rc;
1077}
1078
4a8a4322 1079static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
c2d79b48 1080 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c 1081{
3d24a9f7 1082 struct iwl_rx_packet *res = NULL;
b481de9c
ZY
1083
1084 if (!skb) {
15b1687c 1085 IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
b481de9c
ZY
1086 return 1;
1087 }
1088
3d24a9f7 1089 res = (struct iwl_rx_packet *)skb->data;
b481de9c 1090 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1091 IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
b481de9c
ZY
1092 res->hdr.flags);
1093 return 1;
1094 }
1095
1096 switch (res->u.add_sta.status) {
1097 case ADD_STA_SUCCESS_MSK:
1098 break;
1099 default:
1100 break;
1101 }
1102
1103 /* We didn't cache the SKB; let the caller free it */
1104 return 1;
1105}
1106
4a8a4322 1107int iwl3945_send_add_station(struct iwl_priv *priv,
bb8c093b 1108 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1109{
3d24a9f7 1110 struct iwl_rx_packet *res = NULL;
b481de9c 1111 int rc = 0;
c2d79b48 1112 struct iwl_host_cmd cmd = {
b481de9c 1113 .id = REPLY_ADD_STA,
bb8c093b 1114 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY
1115 .meta.flags = flags,
1116 .data = sta,
1117 };
1118
1119 if (flags & CMD_ASYNC)
bb8c093b 1120 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY
1121 else
1122 cmd.meta.flags |= CMD_WANT_SKB;
1123
bb8c093b 1124 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1125
1126 if (rc || (flags & CMD_ASYNC))
1127 return rc;
1128
3d24a9f7 1129 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 1130 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1131 IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
b481de9c
ZY
1132 res->hdr.flags);
1133 rc = -EIO;
1134 }
1135
1136 if (rc == 0) {
1137 switch (res->u.add_sta.status) {
1138 case ADD_STA_SUCCESS_MSK:
1139 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1140 break;
1141 default:
1142 rc = -EIO;
39aadf8c 1143 IWL_WARN(priv, "REPLY_ADD_STA failed\n");
b481de9c
ZY
1144 break;
1145 }
1146 }
1147
1148 priv->alloc_rxb_skb--;
1149 dev_kfree_skb_any(cmd.meta.u.skb);
1150
1151 return rc;
1152}
1153
4a8a4322 1154static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
b481de9c
ZY
1155 struct ieee80211_key_conf *keyconf,
1156 u8 sta_id)
1157{
1158 unsigned long flags;
1159 __le16 key_flags = 0;
1160
1161 switch (keyconf->alg) {
1162 case ALG_CCMP:
1163 key_flags |= STA_KEY_FLG_CCMP;
1164 key_flags |= cpu_to_le16(
1165 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1166 key_flags &= ~STA_KEY_FLG_INVALID;
1167 break;
1168 case ALG_TKIP:
1169 case ALG_WEP:
b481de9c
ZY
1170 default:
1171 return -EINVAL;
1172 }
1173 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
AK
1174 priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
1175 priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
1176 memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
b481de9c
ZY
1177 keyconf->keylen);
1178
f2c7e521 1179 memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
b481de9c 1180 keyconf->keylen);
f2c7e521
AK
1181 priv->stations_39[sta_id].sta.key.key_flags = key_flags;
1182 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1183 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY
1184
1185 spin_unlock_irqrestore(&priv->sta_lock, flags);
1186
1187 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
f2c7e521 1188 iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
b481de9c
ZY
1189 return 0;
1190}
1191
4a8a4322 1192static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
ZY
1193{
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
AK
1197 memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1198 memset(&priv->stations_39[sta_id].sta.key, 0,
4c897253 1199 sizeof(struct iwl4965_keyinfo));
f2c7e521
AK
1200 priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1201 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1202 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY
1203 spin_unlock_irqrestore(&priv->sta_lock, flags);
1204
1205 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
f2c7e521 1206 iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
b481de9c
ZY
1207 return 0;
1208}
1209
4a8a4322 1210static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
1211{
1212 struct list_head *element;
1213
1214 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1215 priv->frames_count);
1216
1217 while (!list_empty(&priv->free_frames)) {
1218 element = priv->free_frames.next;
1219 list_del(element);
bb8c093b 1220 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY
1221 priv->frames_count--;
1222 }
1223
1224 if (priv->frames_count) {
39aadf8c 1225 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY
1226 priv->frames_count);
1227 priv->frames_count = 0;
1228 }
1229}
1230
4a8a4322 1231static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 1232{
bb8c093b 1233 struct iwl3945_frame *frame;
b481de9c
ZY
1234 struct list_head *element;
1235 if (list_empty(&priv->free_frames)) {
1236 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1237 if (!frame) {
15b1687c 1238 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY
1239 return NULL;
1240 }
1241
1242 priv->frames_count++;
1243 return frame;
1244 }
1245
1246 element = priv->free_frames.next;
1247 list_del(element);
bb8c093b 1248 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
1249}
1250
4a8a4322 1251static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY
1252{
1253 memset(frame, 0, sizeof(*frame));
1254 list_add(&frame->list, &priv->free_frames);
1255}
1256
4a8a4322 1257unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 1258 struct ieee80211_hdr *hdr,
73ec1cc2 1259 int left)
b481de9c
ZY
1260{
1261
bb8c093b 1262 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
1263 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1264 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
1265 return 0;
1266
1267 if (priv->ibss_beacon->len > left)
1268 return 0;
1269
1270 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1271
1272 return priv->ibss_beacon->len;
1273}
1274
4a8a4322 1275static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
b481de9c
ZY
1276{
1277 u8 i;
c24f0817
KA
1278 int rate_mask;
1279
1280 /* Set rate mask*/
f2c7e521 1281 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
dbce56a4 1282 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
c24f0817 1283 else
dbce56a4 1284 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
b481de9c
ZY
1285
1286 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1287 i = iwl3945_rates[i].next_ieee) {
b481de9c 1288 if (rate_mask & (1 << i))
bb8c093b 1289 return iwl3945_rates[i].plcp;
b481de9c
ZY
1290 }
1291
c24f0817 1292 /* No valid rate was found. Assign the lowest one */
f2c7e521 1293 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
c24f0817
KA
1294 return IWL_RATE_1M_PLCP;
1295 else
1296 return IWL_RATE_6M_PLCP;
b481de9c
ZY
1297}
1298
4a8a4322 1299static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 1300{
bb8c093b 1301 struct iwl3945_frame *frame;
b481de9c
ZY
1302 unsigned int frame_size;
1303 int rc;
1304 u8 rate;
1305
bb8c093b 1306 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
1307
1308 if (!frame) {
15b1687c 1309 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
1310 "command.\n");
1311 return -ENOMEM;
1312 }
1313
c24f0817 1314 rate = iwl3945_rate_get_lowest_plcp(priv);
b481de9c 1315
bb8c093b 1316 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1317
bb8c093b 1318 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
1319 &frame->u.cmd[0]);
1320
bb8c093b 1321 iwl3945_free_frame(priv, frame);
b481de9c
ZY
1322
1323 return rc;
1324}
1325
1326/******************************************************************************
1327 *
1328 * EEPROM related functions
1329 *
1330 ******************************************************************************/
1331
4a8a4322 1332static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
b481de9c 1333{
f2c7e521 1334 memcpy(mac, priv->eeprom39.mac_address, 6);
b481de9c
ZY
1335}
1336
74a3a250
RC
1337/*
1338 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1339 * embedded controller) as EEPROM reader; each read is a series of pulses
1340 * to/from the EEPROM chip, not a single event, so even reads could conflict
1341 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1342 * simply claims ownership, which should be safe when this function is called
1343 * (i.e. before loading uCode!).
1344 */
4a8a4322 1345static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
74a3a250 1346{
5d49f498 1347 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
74a3a250
RC
1348 return 0;
1349}
1350
b481de9c 1351/**
bb8c093b 1352 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1353 *
f2c7e521 1354 * Load the EEPROM contents from adapter into priv->eeprom39
b481de9c
ZY
1355 *
1356 * NOTE: This routine uses the non-debug IO access functions.
1357 */
4a8a4322 1358int iwl3945_eeprom_init(struct iwl_priv *priv)
b481de9c 1359{
f2c7e521 1360 u16 *e = (u16 *)&priv->eeprom39;
5d49f498 1361 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
f2c7e521 1362 int sz = sizeof(priv->eeprom39);
3d5717ad 1363 int ret;
b481de9c
ZY
1364 u16 addr;
1365
1366 /* The EEPROM structure has several padding buffers within it
1367 * and when adding new EEPROM maps is subject to programmer errors
1368 * which may be very difficult to identify without explicitly
1369 * checking the resulting size of the eeprom map. */
f2c7e521 1370 BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
b481de9c
ZY
1371
1372 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
15b1687c 1373 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY
1374 return -ENOENT;
1375 }
1376
6440adb5 1377 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
3d5717ad
ZY
1378 ret = iwl3945_eeprom_acquire_semaphore(priv);
1379 if (ret < 0) {
15b1687c 1380 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY
1381 return -ENOENT;
1382 }
1383
1384 /* eeprom is an array of 16bit values */
1385 for (addr = 0; addr < sz; addr += sizeof(u16)) {
3d5717ad 1386 u32 r;
b481de9c 1387
5d49f498 1388 _iwl_write32(priv, CSR_EEPROM_REG,
3d5717ad 1389 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
5d49f498
AK
1390 _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1391 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
3d5717ad
ZY
1392 CSR_EEPROM_REG_READ_VALID_MSK,
1393 IWL_EEPROM_ACCESS_TIMEOUT);
1394 if (ret < 0) {
15b1687c 1395 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
3d5717ad 1396 return ret;
b481de9c 1397 }
3d5717ad 1398
5d49f498 1399 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
58ff6d4d 1400 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY
1401 }
1402
1403 return 0;
1404}
1405
4a8a4322 1406static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 1407{
3832ec9d 1408 if (priv->shared_virt)
b481de9c 1409 pci_free_consistent(priv->pci_dev,
bb8c093b 1410 sizeof(struct iwl3945_shared),
3832ec9d
AK
1411 priv->shared_virt,
1412 priv->shared_phys);
b481de9c
ZY
1413}
1414
1415/**
bb8c093b 1416 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY
1417 *
1418 * return : set the bit for each supported rate insert in ie
1419 */
bb8c093b 1420static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1421 u16 basic_rate, int *left)
b481de9c
ZY
1422{
1423 u16 ret_rates = 0, bit;
1424 int i;
c7c46676
TW
1425 u8 *cnt = ie;
1426 u8 *rates = ie + 1;
b481de9c
ZY
1427
1428 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1429 if (bit & supported_rate) {
1430 ret_rates |= bit;
bb8c093b 1431 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW
1432 ((bit & basic_rate) ? 0x80 : 0x00);
1433 (*cnt)++;
1434 (*left)--;
1435 if ((*left <= 0) ||
1436 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY
1437 break;
1438 }
1439 }
1440
1441 return ret_rates;
1442}
1443
1444/**
bb8c093b 1445 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1446 */
4a8a4322 1447static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
b481de9c 1448 struct ieee80211_mgmt *frame,
430cfe95 1449 int left)
b481de9c
ZY
1450{
1451 int len = 0;
1452 u8 *pos = NULL;
c7c46676 1453 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY
1454
1455 /* Make sure there is enough space for the probe request,
1456 * two mandatory IEs and the data */
1457 left -= 24;
1458 if (left < 0)
1459 return 0;
1460 len += 24;
1461
1462 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
b5323d36 1463 memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
b481de9c 1464 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
b5323d36 1465 memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
b481de9c
ZY
1466 frame->seq_ctrl = 0;
1467
1468 /* fill in our indirect SSID IE */
1469 /* ...next IE... */
1470
1471 left -= 2;
1472 if (left < 0)
1473 return 0;
1474 len += 2;
1475 pos = &(frame->u.probe_req.variable[0]);
1476 *pos++ = WLAN_EID_SSID;
1477 *pos++ = 0;
1478
b481de9c
ZY
1479 /* fill in supported rate */
1480 /* ...next IE... */
1481 left -= 2;
1482 if (left < 0)
1483 return 0;
c7c46676 1484
b481de9c
ZY
1485 /* ... fill it in... */
1486 *pos++ = WLAN_EID_SUPP_RATES;
1487 *pos = 0;
c7c46676
TW
1488
1489 priv->active_rate = priv->rates_mask;
1490 active_rates = priv->active_rate;
b481de9c
ZY
1491 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1492
c7c46676 1493 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1494 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW
1495 priv->active_rate_basic, &left);
1496 active_rates &= ~ret_rates;
1497
bb8c093b 1498 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW
1499 priv->active_rate_basic, &left);
1500 active_rates &= ~ret_rates;
1501
b481de9c
ZY
1502 len += 2 + *pos;
1503 pos += (*pos) + 1;
c7c46676 1504 if (active_rates == 0)
b481de9c
ZY
1505 goto fill_end;
1506
1507 /* fill in supported extended rate */
1508 /* ...next IE... */
1509 left -= 2;
1510 if (left < 0)
1511 return 0;
1512 /* ... fill it in... */
1513 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1514 *pos = 0;
bb8c093b 1515 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1516 priv->active_rate_basic, &left);
b481de9c
ZY
1517 if (*pos > 0)
1518 len += 2 + *pos;
1519
1520 fill_end:
1521 return (u16)len;
1522}
1523
1524/*
1525 * QoS support
1526*/
4a8a4322 1527static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
4c897253 1528 struct iwl_qosparam_cmd *qos)
b481de9c
ZY
1529{
1530
bb8c093b 1531 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
4c897253 1532 sizeof(struct iwl_qosparam_cmd), qos);
b481de9c
ZY
1533}
1534
4a8a4322 1535static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
b481de9c
ZY
1536{
1537 unsigned long flags;
1538
b481de9c
ZY
1539 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1540 return;
1541
b481de9c
ZY
1542 spin_lock_irqsave(&priv->lock, flags);
1543 priv->qos_data.def_qos_parm.qos_flags = 0;
1544
1545 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1546 !priv->qos_data.qos_cap.q_AP.txop_request)
1547 priv->qos_data.def_qos_parm.qos_flags |=
1548 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1549
1550 if (priv->qos_data.qos_active)
1551 priv->qos_data.def_qos_parm.qos_flags |=
1552 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1553
1554 spin_unlock_irqrestore(&priv->lock, flags);
1555
bb8c093b 1556 if (force || iwl3945_is_associated(priv)) {
a96a27f9 1557 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
b481de9c
ZY
1558 priv->qos_data.qos_active);
1559
bb8c093b 1560 iwl3945_send_qos_params_command(priv,
b481de9c
ZY
1561 &(priv->qos_data.def_qos_parm));
1562 }
1563}
1564
b481de9c
ZY
1565/*
1566 * Power management (not Tx power!) functions
1567 */
1568#define MSEC_TO_USEC 1024
1569
600c0e11
TW
1570
1571#define NOSLP __constant_cpu_to_le16(0), 0, 0
1572#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
b481de9c
ZY
1573#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1574#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1575 __constant_cpu_to_le32(X1), \
1576 __constant_cpu_to_le32(X2), \
1577 __constant_cpu_to_le32(X3), \
1578 __constant_cpu_to_le32(X4)}
1579
b481de9c 1580/* default power management (not Tx power) table values */
a96a27f9 1581/* for TIM 0-10 */
1125eff3 1582static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
b481de9c
ZY
1583 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1584 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1585 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1586 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1587 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1588 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1589};
1590
a96a27f9 1591/* for TIM > 10 */
1125eff3 1592static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
b481de9c
ZY
1593 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1594 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1595 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1596 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1597 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1598 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1599 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1600 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1601 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1602 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1603};
1604
4a8a4322 1605int iwl3945_power_init_handle(struct iwl_priv *priv)
b481de9c
ZY
1606{
1607 int rc = 0, i;
bb8c093b 1608 struct iwl3945_power_mgr *pow_data;
1125eff3 1609 int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
b481de9c
ZY
1610 u16 pci_pm;
1611
1612 IWL_DEBUG_POWER("Initialize power \n");
1613
f2c7e521 1614 pow_data = &(priv->power_data_39);
b481de9c
ZY
1615
1616 memset(pow_data, 0, sizeof(*pow_data));
1617
1618 pow_data->active_index = IWL_POWER_RANGE_0;
1619 pow_data->dtim_val = 0xffff;
1620
1621 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1622 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1623
1624 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1625 if (rc != 0)
1626 return 0;
1627 else {
600c0e11 1628 struct iwl_powertable_cmd *cmd;
b481de9c
ZY
1629
1630 IWL_DEBUG_POWER("adjust power command flags\n");
1631
1125eff3 1632 for (i = 0; i < IWL39_POWER_AC; i++) {
b481de9c
ZY
1633 cmd = &pow_data->pwr_range_0[i].cmd;
1634
1635 if (pci_pm & 0x1)
1636 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1637 else
1638 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1639 }
1640 }
1641 return rc;
1642}
1643
4a8a4322 1644static int iwl3945_update_power_cmd(struct iwl_priv *priv,
600c0e11 1645 struct iwl_powertable_cmd *cmd, u32 mode)
b481de9c
ZY
1646{
1647 int rc = 0, i;
1648 u8 skip;
1649 u32 max_sleep = 0;
1125eff3 1650 struct iwl_power_vec_entry *range;
b481de9c 1651 u8 period = 0;
bb8c093b 1652 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY
1653
1654 if (mode > IWL_POWER_INDEX_5) {
1655 IWL_DEBUG_POWER("Error invalid power mode \n");
1656 return -1;
1657 }
f2c7e521 1658 pow_data = &(priv->power_data_39);
b481de9c
ZY
1659
1660 if (pow_data->active_index == IWL_POWER_RANGE_0)
1661 range = &pow_data->pwr_range_0[0];
1662 else
1663 range = &pow_data->pwr_range_1[1];
1664
bb8c093b 1665 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY
1666
1667#ifdef IWL_MAC80211_DISABLE
1668 if (priv->assoc_network != NULL) {
1669 unsigned long flags;
1670
1671 period = priv->assoc_network->tim.tim_period;
1672 }
1673#endif /*IWL_MAC80211_DISABLE */
1674 skip = range[mode].no_dtim;
1675
1676 if (period == 0) {
1677 period = 1;
1678 skip = 0;
1679 }
1680
1681 if (skip == 0) {
1682 max_sleep = period;
1683 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1684 } else {
1685 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1686 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1687 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1688 }
1689
1690 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1691 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1692 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1693 }
1694
1695 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1696 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1697 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1698 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1699 le32_to_cpu(cmd->sleep_interval[0]),
1700 le32_to_cpu(cmd->sleep_interval[1]),
1701 le32_to_cpu(cmd->sleep_interval[2]),
1702 le32_to_cpu(cmd->sleep_interval[3]),
1703 le32_to_cpu(cmd->sleep_interval[4]));
1704
1705 return rc;
1706}
1707
4a8a4322 1708static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
b481de9c 1709{
9a62f73b 1710 u32 uninitialized_var(final_mode);
b481de9c 1711 int rc;
600c0e11 1712 struct iwl_powertable_cmd cmd;
b481de9c
ZY
1713
1714 /* If on battery, set to 3,
01ebd063 1715 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY
1716 * else user level */
1717 switch (mode) {
1125eff3 1718 case IWL39_POWER_BATTERY:
b481de9c
ZY
1719 final_mode = IWL_POWER_INDEX_3;
1720 break;
1125eff3 1721 case IWL39_POWER_AC:
b481de9c
ZY
1722 final_mode = IWL_POWER_MODE_CAM;
1723 break;
1724 default:
1725 final_mode = mode;
1726 break;
1727 }
1728
bb8c093b 1729 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1730
600c0e11
TW
1731 /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
1732 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
1733 sizeof(struct iwl3945_powertable_cmd), &cmd);
b481de9c
ZY
1734
1735 if (final_mode == IWL_POWER_MODE_CAM)
1736 clear_bit(STATUS_POWER_PMI, &priv->status);
1737 else
1738 set_bit(STATUS_POWER_PMI, &priv->status);
1739
1740 return rc;
1741}
1742
b481de9c 1743/**
bb8c093b 1744 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY
1745 *
1746 * NOTE: priv->mutex is not required before calling this function
1747 */
4a8a4322 1748static int iwl3945_scan_cancel(struct iwl_priv *priv)
b481de9c
ZY
1749{
1750 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1751 clear_bit(STATUS_SCANNING, &priv->status);
1752 return 0;
1753 }
1754
1755 if (test_bit(STATUS_SCANNING, &priv->status)) {
1756 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1757 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1758 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1759 queue_work(priv->workqueue, &priv->abort_scan);
1760
1761 } else
1762 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1763
1764 return test_bit(STATUS_SCANNING, &priv->status);
1765 }
1766
1767 return 0;
1768}
1769
1770/**
bb8c093b 1771 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY
1772 * @ms: amount of time to wait (in milliseconds) for scan to abort
1773 *
1774 * NOTE: priv->mutex must be held before calling this function
1775 */
4a8a4322 1776static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
b481de9c
ZY
1777{
1778 unsigned long now = jiffies;
1779 int ret;
1780
bb8c093b 1781 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY
1782 if (ret && ms) {
1783 mutex_unlock(&priv->mutex);
1784 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
1785 test_bit(STATUS_SCANNING, &priv->status))
1786 msleep(1);
1787 mutex_lock(&priv->mutex);
1788
1789 return test_bit(STATUS_SCANNING, &priv->status);
1790 }
1791
1792 return ret;
1793}
1794
b481de9c
ZY
1795#define MAX_UCODE_BEACON_INTERVAL 1024
1796#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
1797
bb8c093b 1798static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
1799{
1800 u16 new_val = 0;
1801 u16 beacon_factor = 0;
1802
1803 beacon_factor =
1804 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
1805 / MAX_UCODE_BEACON_INTERVAL;
1806 new_val = beacon_val / beacon_factor;
1807
1808 return cpu_to_le16(new_val);
1809}
1810
4a8a4322 1811static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
b481de9c
ZY
1812{
1813 u64 interval_tm_unit;
1814 u64 tsf, result;
1815 unsigned long flags;
1816 struct ieee80211_conf *conf = NULL;
1817 u16 beacon_int = 0;
1818
1819 conf = ieee80211_get_hw_conf(priv->hw);
1820
1821 spin_lock_irqsave(&priv->lock, flags);
28afaf91 1822 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b481de9c
ZY
1823 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
1824
28afaf91 1825 tsf = priv->timestamp;
b481de9c
ZY
1826
1827 beacon_int = priv->beacon_int;
1828 spin_unlock_irqrestore(&priv->lock, flags);
1829
05c914fe 1830 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY
1831 if (beacon_int == 0) {
1832 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
1833 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
1834 } else {
1835 priv->rxon_timing.beacon_interval =
1836 cpu_to_le16(beacon_int);
1837 priv->rxon_timing.beacon_interval =
bb8c093b 1838 iwl3945_adjust_beacon_interval(
b481de9c
ZY
1839 le16_to_cpu(priv->rxon_timing.beacon_interval));
1840 }
1841
1842 priv->rxon_timing.atim_window = 0;
1843 } else {
1844 priv->rxon_timing.beacon_interval =
bb8c093b 1845 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY
1846 /* TODO: we need to get atim_window from upper stack
1847 * for now we set to 0 */
1848 priv->rxon_timing.atim_window = 0;
1849 }
1850
1851 interval_tm_unit =
1852 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
1853 result = do_div(tsf, interval_tm_unit);
1854 priv->rxon_timing.beacon_init_val =
1855 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
1856
1857 IWL_DEBUG_ASSOC
1858 ("beacon interval %d beacon timer %d beacon tim %d\n",
1859 le16_to_cpu(priv->rxon_timing.beacon_interval),
1860 le32_to_cpu(priv->rxon_timing.beacon_init_val),
1861 le16_to_cpu(priv->rxon_timing.atim_window));
1862}
1863
4a8a4322 1864static int iwl3945_scan_initiate(struct iwl_priv *priv)
b481de9c 1865{
775a6e27 1866 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
1867 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
1868 return -EIO;
1869 }
1870
1871 if (test_bit(STATUS_SCANNING, &priv->status)) {
1872 IWL_DEBUG_SCAN("Scan already in progress.\n");
1873 return -EAGAIN;
1874 }
1875
1876 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1877 IWL_DEBUG_SCAN("Scan request while abort pending. "
1878 "Queuing.\n");
1879 return -EAGAIN;
1880 }
1881
1882 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR
1883 if (priv->cfg->sku & IWL_SKU_G)
1884 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
1885 if (priv->cfg->sku & IWL_SKU_A)
1886 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY
1887 set_bit(STATUS_SCANNING, &priv->status);
1888 priv->scan_start = jiffies;
1889 priv->scan_pass_start = priv->scan_start;
1890
1891 queue_work(priv->workqueue, &priv->request_scan);
1892
1893 return 0;
1894}
1895
4a8a4322 1896static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
b481de9c 1897{
f2c7e521 1898 struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
b481de9c
ZY
1899
1900 if (hw_decrypt)
1901 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
1902 else
1903 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
1904
1905 return 0;
1906}
1907
4a8a4322 1908static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
8318d78a 1909 enum ieee80211_band band)
b481de9c 1910{
8318d78a 1911 if (band == IEEE80211_BAND_5GHZ) {
f2c7e521 1912 priv->staging39_rxon.flags &=
b481de9c
ZY
1913 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1914 | RXON_FLG_CCK_MSK);
f2c7e521 1915 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1916 } else {
bb8c093b 1917 /* Copied from iwl3945_bg_post_associate() */
b481de9c 1918 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 1919 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1920 else
f2c7e521 1921 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1922
05c914fe 1923 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 1924 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1925
f2c7e521
AK
1926 priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1927 priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1928 priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
b481de9c
ZY
1929 }
1930}
1931
1932/*
01ebd063 1933 * initialize rxon structure with default values from eeprom
b481de9c 1934 */
4a8a4322 1935static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
60294de3 1936 int mode)
b481de9c 1937{
d20b3c65 1938 const struct iwl_channel_info *ch_info;
b481de9c 1939
f2c7e521 1940 memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
b481de9c 1941
60294de3 1942 switch (mode) {
05c914fe 1943 case NL80211_IFTYPE_AP:
f2c7e521 1944 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
b481de9c
ZY
1945 break;
1946
05c914fe 1947 case NL80211_IFTYPE_STATION:
f2c7e521
AK
1948 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
1949 priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
b481de9c
ZY
1950 break;
1951
05c914fe 1952 case NL80211_IFTYPE_ADHOC:
f2c7e521
AK
1953 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1954 priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1955 priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
b481de9c
ZY
1956 RXON_FILTER_ACCEPT_GRP_MSK;
1957 break;
1958
05c914fe 1959 case NL80211_IFTYPE_MONITOR:
f2c7e521
AK
1960 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
1961 priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
b481de9c
ZY
1962 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
1963 break;
69dc5d9d 1964 default:
15b1687c 1965 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
69dc5d9d 1966 break;
b481de9c
ZY
1967 }
1968
1969#if 0
1970 /* TODO: Figure out when short_preamble would be set and cache from
1971 * that */
1972 if (!hw_to_local(priv->hw)->short_preamble)
f2c7e521 1973 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 1974 else
f2c7e521 1975 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c
ZY
1976#endif
1977
8318d78a 1978 ch_info = iwl3945_get_channel_info(priv, priv->band,
f2c7e521 1979 le16_to_cpu(priv->active39_rxon.channel));
b481de9c
ZY
1980
1981 if (!ch_info)
1982 ch_info = &priv->channel_info[0];
1983
1984 /*
1985 * in some case A channels are all non IBSS
1986 * in this case force B/G channel
1987 */
60294de3 1988 if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
b481de9c
ZY
1989 ch_info = &priv->channel_info[0];
1990
f2c7e521 1991 priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
b481de9c 1992 if (is_channel_a_band(ch_info))
8318d78a 1993 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 1994 else
8318d78a 1995 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 1996
8318d78a 1997 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c 1998
f2c7e521 1999 priv->staging39_rxon.ofdm_basic_rates =
b481de9c 2000 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
f2c7e521 2001 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY
2002 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2003}
2004
4a8a4322 2005static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
b481de9c 2006{
05c914fe 2007 if (mode == NL80211_IFTYPE_ADHOC) {
d20b3c65 2008 const struct iwl_channel_info *ch_info;
b481de9c 2009
bb8c093b 2010 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2011 priv->band,
f2c7e521 2012 le16_to_cpu(priv->staging39_rxon.channel));
b481de9c
ZY
2013
2014 if (!ch_info || !is_channel_ibss(ch_info)) {
15b1687c 2015 IWL_ERR(priv, "channel %d not IBSS channel\n",
f2c7e521 2016 le16_to_cpu(priv->staging39_rxon.channel));
b481de9c
ZY
2017 return -EINVAL;
2018 }
2019 }
2020
60294de3 2021 iwl3945_connection_init_rx_config(priv, mode);
f2c7e521 2022 memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
b481de9c 2023
bb8c093b 2024 iwl3945_clear_stations_table(priv);
b481de9c 2025
a96a27f9 2026 /* don't commit rxon if rf-kill is on*/
775a6e27 2027 if (!iwl_is_ready_rf(priv))
fde3571f
MA
2028 return -EAGAIN;
2029
2030 cancel_delayed_work(&priv->scan_check);
2031 if (iwl3945_scan_cancel_timeout(priv, 100)) {
39aadf8c 2032 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
fde3571f
MA
2033 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2034 return -EAGAIN;
2035 }
2036
bb8c093b 2037 iwl3945_commit_rxon(priv);
b481de9c
ZY
2038
2039 return 0;
2040}
2041
4a8a4322 2042static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 2043 struct ieee80211_tx_info *info,
c2d79b48 2044 struct iwl_cmd *cmd,
b481de9c
ZY
2045 struct sk_buff *skb_frag,
2046 int last_frag)
2047{
e52119c5 2048 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
1c014420 2049 struct iwl3945_hw_key *keyinfo =
f2c7e521 2050 &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY
2051
2052 switch (keyinfo->alg) {
2053 case ALG_CCMP:
e52119c5
WT
2054 tx->sec_ctl = TX_CMD_SEC_CCM;
2055 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
a96a27f9 2056 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
b481de9c
ZY
2057 break;
2058
2059 case ALG_TKIP:
2060#if 0
e52119c5 2061 tx->sec_ctl = TX_CMD_SEC_TKIP;
b481de9c
ZY
2062
2063 if (last_frag)
e52119c5 2064 memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
b481de9c
ZY
2065 8);
2066 else
e52119c5 2067 memset(tx->tkip_mic.byte, 0, 8);
b481de9c
ZY
2068#endif
2069 break;
2070
2071 case ALG_WEP:
e52119c5 2072 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2073 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
2074
2075 if (keyinfo->keylen == 13)
e52119c5 2076 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 2077
e52119c5 2078 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c
ZY
2079
2080 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2081 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
2082 break;
2083
b481de9c 2084 default:
978785a3 2085 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
2086 break;
2087 }
2088}
2089
2090/*
2091 * handle build REPLY_TX command notification.
2092 */
4a8a4322 2093static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2d79b48 2094 struct iwl_cmd *cmd,
e039fa4a 2095 struct ieee80211_tx_info *info,
e52119c5 2096 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 2097{
e52119c5
WT
2098 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
2099 __le32 tx_flags = tx->tx_flags;
fd7c8a40 2100 __le16 fc = hdr->frame_control;
e6a9854b 2101 u8 rc_flags = info->control.rates[0].flags;
b481de9c 2102
e52119c5 2103 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2104 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2105 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2106 if (ieee80211_is_mgmt(fc))
b481de9c 2107 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2108 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
2109 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2110 tx_flags |= TX_CMD_FLG_TSF_MSK;
2111 } else {
2112 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2113 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2114 }
2115
e52119c5 2116 tx->sta_id = std_id;
8b7b1e05 2117 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
2118 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2119
fd7c8a40
HH
2120 if (ieee80211_is_data_qos(fc)) {
2121 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 2122 tx->tid_tspec = qc[0] & 0xf;
b481de9c 2123 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2124 } else {
b481de9c 2125 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2126 }
b481de9c 2127
e6a9854b 2128 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
2129 tx_flags |= TX_CMD_FLG_RTS_MSK;
2130 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2131 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY
2132 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2133 tx_flags |= TX_CMD_FLG_CTS_MSK;
2134 }
2135
2136 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2137 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2138
2139 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
2140 if (ieee80211_is_mgmt(fc)) {
2141 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 2142 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2143 else
e52119c5 2144 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2145 } else {
e52119c5 2146 tx->timeout.pm_frame_timeout = 0;
ab53d8af
MA
2147#ifdef CONFIG_IWL3945_LEDS
2148 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2149#endif
2150 }
b481de9c 2151
e52119c5
WT
2152 tx->driver_txop = 0;
2153 tx->tx_flags = tx_flags;
2154 tx->next_frame_len = 0;
b481de9c
ZY
2155}
2156
6440adb5
BC
2157/**
2158 * iwl3945_get_sta_id - Find station's index within station table
2159 */
4a8a4322 2160static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY
2161{
2162 int sta_id;
2163 u16 fc = le16_to_cpu(hdr->frame_control);
2164
6440adb5 2165 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY
2166 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2167 is_multicast_ether_addr(hdr->addr1))
3832ec9d 2168 return priv->hw_params.bcast_sta_id;
b481de9c
ZY
2169
2170 switch (priv->iw_mode) {
2171
6440adb5
BC
2172 /* If we are a client station in a BSS network, use the special
2173 * AP station entry (that's the only station we communicate with) */
05c914fe 2174 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2175 return IWL_AP_ID;
2176
2177 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2178 case NL80211_IFTYPE_AP:
bb8c093b 2179 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2180 if (sta_id != IWL_INVALID_STATION)
2181 return sta_id;
3832ec9d 2182 return priv->hw_params.bcast_sta_id;
b481de9c 2183
6440adb5
BC
2184 /* If this frame is going out to an IBSS network, find the station,
2185 * or create a new station table entry */
05c914fe 2186 case NL80211_IFTYPE_ADHOC: {
6440adb5 2187 /* Create new station table entry */
bb8c093b 2188 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2189 if (sta_id != IWL_INVALID_STATION)
2190 return sta_id;
2191
bb8c093b 2192 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY
2193
2194 if (sta_id != IWL_INVALID_STATION)
2195 return sta_id;
2196
e174961c 2197 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2198 "Defaulting to broadcast...\n",
e174961c 2199 hdr->addr1);
40b8ec0b 2200 iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
3832ec9d 2201 return priv->hw_params.bcast_sta_id;
0795af57 2202 }
914233d6
SG
2203 /* If we are in monitor mode, use BCAST. This is required for
2204 * packet injection. */
05c914fe 2205 case NL80211_IFTYPE_MONITOR:
3832ec9d 2206 return priv->hw_params.bcast_sta_id;
914233d6 2207
b481de9c 2208 default:
39aadf8c
WT
2209 IWL_WARN(priv, "Unknown mode of operation: %d\n",
2210 priv->iw_mode);
3832ec9d 2211 return priv->hw_params.bcast_sta_id;
b481de9c
ZY
2212 }
2213}
2214
2215/*
2216 * start REPLY_TX command process
2217 */
4a8a4322 2218static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
2219{
2220 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2221 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
dbb6654c 2222 struct iwl3945_tfd *tfd;
e52119c5 2223 struct iwl3945_tx_cmd *tx;
188cf6c7 2224 struct iwl_tx_queue *txq = NULL;
d20b3c65 2225 struct iwl_queue *q = NULL;
e52119c5 2226 struct iwl_cmd *out_cmd = NULL;
b481de9c
ZY
2227 dma_addr_t phys_addr;
2228 dma_addr_t txcmd_phys;
e52119c5 2229 int txq_id = skb_get_queue_mapping(skb);
54dbb525
TW
2230 u16 len, idx, len_org, hdr_len;
2231 u8 id;
2232 u8 unicast;
b481de9c 2233 u8 sta_id;
54dbb525 2234 u8 tid = 0;
b481de9c 2235 u16 seq_number = 0;
fd7c8a40 2236 __le16 fc;
b481de9c 2237 u8 wait_write_ptr = 0;
54dbb525 2238 u8 *qc = NULL;
b481de9c
ZY
2239 unsigned long flags;
2240 int rc;
2241
2242 spin_lock_irqsave(&priv->lock, flags);
775a6e27 2243 if (iwl_is_rfkill(priv)) {
b481de9c
ZY
2244 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2245 goto drop_unlock;
2246 }
2247
e039fa4a 2248 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 2249 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
2250 goto drop_unlock;
2251 }
2252
2253 unicast = !is_multicast_ether_addr(hdr->addr1);
2254 id = 0;
2255
fd7c8a40 2256 fc = hdr->frame_control;
b481de9c 2257
c8b0e6e1 2258#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
2259 if (ieee80211_is_auth(fc))
2260 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2261 else if (ieee80211_is_assoc_req(fc))
b481de9c 2262 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2263 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY
2264 IWL_DEBUG_TX("Sending REASSOC frame\n");
2265#endif
2266
7878a5a4 2267 /* drop all data frame if we are not associated */
914233d6 2268 if (ieee80211_is_data(fc) &&
05c914fe 2269 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2270 (!iwl3945_is_associated(priv) ||
05c914fe 2271 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2272 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY
2273 goto drop_unlock;
2274 }
2275
2276 spin_unlock_irqrestore(&priv->lock, flags);
2277
7294ec95 2278 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
2279
2280 /* Find (or create) index into station table for destination station */
bb8c093b 2281 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2282 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB
2283 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2284 hdr->addr1);
b481de9c
ZY
2285 goto drop;
2286 }
2287
2288 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2289
fd7c8a40
HH
2290 if (ieee80211_is_data_qos(fc)) {
2291 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2292 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f2c7e521 2293 seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
b481de9c
ZY
2294 IEEE80211_SCTL_SEQ;
2295 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2296 (hdr->seq_ctrl &
2297 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2298 seq_number += 0x10;
2299 }
6440adb5
BC
2300
2301 /* Descriptor for chosen Tx queue */
188cf6c7 2302 txq = &priv->txq[txq_id];
b481de9c
ZY
2303 q = &txq->q;
2304
2305 spin_lock_irqsave(&priv->lock, flags);
2306
6440adb5 2307 /* Set up first empty TFD within this queue's circular TFD buffer */
188cf6c7 2308 tfd = &txq->tfds39[q->write_ptr];
b481de9c 2309 memset(tfd, 0, sizeof(*tfd));
fc4b6853 2310 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2311
6440adb5 2312 /* Set up driver data for this TFD */
dbb6654c 2313 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 2314 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
2315
2316 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 2317 out_cmd = txq->cmd[idx];
e52119c5 2318 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 2319 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 2320 memset(tx, 0, sizeof(*tx));
6440adb5
BC
2321
2322 /*
2323 * Set up the Tx-command (not MAC!) header.
2324 * Store the chosen Tx queue and TFD index within the sequence field;
2325 * after Tx, uCode's Tx response will return this value so driver can
2326 * locate the frame within the tx queue and do post-tx processing.
2327 */
b481de9c
ZY
2328 out_cmd->hdr.cmd = REPLY_TX;
2329 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2330 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
2331
2332 /* Copy MAC header from skb into command buffer */
e52119c5 2333 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 2334
6440adb5
BC
2335 /*
2336 * Use the first empty entry in this queue's command buffer array
2337 * to contain the Tx command and MAC header concatenated together
2338 * (payload data will be in another buffer).
2339 * Size of this varies, due to varying MAC header length.
2340 * If end is not dword aligned, we'll have 2 extra bytes at the end
2341 * of the MAC header (device reads on dword boundaries).
2342 * We'll tell device about this padding later.
2343 */
3832ec9d 2344 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 2345 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
2346
2347 len_org = len;
2348 len = (len + 3) & ~3;
2349
2350 if (len_org != len)
2351 len_org = 1;
2352 else
2353 len_org = 0;
2354
6440adb5
BC
2355 /* Physical address of this Tx command's header (not MAC header!),
2356 * within command buffer array. */
188cf6c7
SO
2357 txcmd_phys = pci_map_single(priv->pci_dev,
2358 out_cmd, sizeof(struct iwl_cmd),
2359 PCI_DMA_TODEVICE);
2360 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
2361 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
2362 /* Add buffer containing Tx command and MAC(!) header to TFD's
2363 * first entry */
2364 txcmd_phys += offsetof(struct iwl_cmd, hdr);
b481de9c 2365
6440adb5
BC
2366 /* Add buffer containing Tx command and MAC(!) header to TFD's
2367 * first entry */
bb8c093b 2368 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2369
d0f09804 2370 if (info->control.hw_key)
e039fa4a 2371 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2372
6440adb5
BC
2373 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2374 * if any (802.11 null frames have no payload). */
b481de9c
ZY
2375 len = skb->len - hdr_len;
2376 if (len) {
2377 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2378 len, PCI_DMA_TODEVICE);
bb8c093b 2379 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY
2380 }
2381
b481de9c 2382 if (!len)
6440adb5 2383 /* If there is no payload, then we use only one Tx buffer */
dbb6654c 2384 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
b481de9c 2385 else
6440adb5
BC
2386 /* Else use 2 buffers.
2387 * Tell 3945 about any padding after MAC header */
dbb6654c
WT
2388 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
2389 TFD_CTL_PAD_SET(U32_PAD(len)));
b481de9c 2390
6440adb5 2391 /* Total # bytes to be transmitted */
b481de9c 2392 len = (u16)skb->len;
e52119c5 2393 tx->len = cpu_to_le16(len);
b481de9c
ZY
2394
2395 /* TODO need this for burst mode later on */
e52119c5 2396 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
b481de9c
ZY
2397
2398 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2399 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c 2400
e52119c5
WT
2401 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2402 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
b481de9c 2403
8b7b1e05 2404 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2405 txq->need_update = 1;
3ac7f146 2406 if (qc)
f2c7e521 2407 priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY
2408 } else {
2409 wait_write_ptr = 1;
2410 txq->need_update = 0;
2411 }
2412
e52119c5 2413 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
b481de9c 2414
e52119c5 2415 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
7294ec95 2416 ieee80211_hdrlen(fc));
b481de9c 2417
6440adb5 2418 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2419 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2420 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2421 spin_unlock_irqrestore(&priv->lock, flags);
2422
2423 if (rc)
2424 return rc;
2425
d20b3c65 2426 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
2427 && priv->mac80211_registered) {
2428 if (wait_write_ptr) {
2429 spin_lock_irqsave(&priv->lock, flags);
2430 txq->need_update = 1;
bb8c093b 2431 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2432 spin_unlock_irqrestore(&priv->lock, flags);
2433 }
2434
e2530083 2435 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY
2436 }
2437
2438 return 0;
2439
2440drop_unlock:
2441 spin_unlock_irqrestore(&priv->lock, flags);
2442drop:
2443 return -1;
2444}
2445
4a8a4322 2446static void iwl3945_set_rate(struct iwl_priv *priv)
b481de9c 2447{
8318d78a 2448 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY
2449 struct ieee80211_rate *rate;
2450 int i;
2451
cbba18c6 2452 sband = iwl_get_hw_mode(priv, priv->band);
8318d78a 2453 if (!sband) {
15b1687c 2454 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
c4ba9621
SA
2455 return;
2456 }
b481de9c
ZY
2457
2458 priv->active_rate = 0;
2459 priv->active_rate_basic = 0;
2460
8318d78a
JB
2461 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2462 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2463
2464 for (i = 0; i < sband->n_bitrates; i++) {
2465 rate = &sband->bitrates[i];
2466 if ((rate->hw_value < IWL_RATE_COUNT) &&
2467 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2468 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2469 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2470 priv->active_rate |= (1 << rate->hw_value);
2471 }
b481de9c
ZY
2472 }
2473
2474 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2475 priv->active_rate, priv->active_rate_basic);
2476
2477 /*
2478 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2479 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2480 * OFDM
2481 */
2482 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
f2c7e521 2483 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY
2484 ((priv->active_rate_basic &
2485 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2486 else
f2c7e521 2487 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY
2488 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2489
2490 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
f2c7e521 2491 priv->staging39_rxon.ofdm_basic_rates =
b481de9c
ZY
2492 ((priv->active_rate_basic &
2493 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2494 IWL_FIRST_OFDM_RATE) & 0xFF;
2495 else
f2c7e521 2496 priv->staging39_rxon.ofdm_basic_rates =
b481de9c
ZY
2497 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2498}
2499
4a8a4322 2500static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
b481de9c
ZY
2501{
2502 unsigned long flags;
2503
2504 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2505 return;
2506
2507 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2508 disable_radio ? "OFF" : "ON");
2509
2510 if (disable_radio) {
bb8c093b 2511 iwl3945_scan_cancel(priv);
b481de9c 2512 /* FIXME: This is a workaround for AP */
05c914fe 2513 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2514 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2515 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
2516 CSR_UCODE_SW_BIT_RFKILL);
2517 spin_unlock_irqrestore(&priv->lock, flags);
c496294e 2518 iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY
2519 set_bit(STATUS_RF_KILL_SW, &priv->status);
2520 }
2521 return;
2522 }
2523
2524 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2525 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2526
2527 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2528 spin_unlock_irqrestore(&priv->lock, flags);
2529
2530 /* wake up ucode */
2531 msleep(10);
2532
2533 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK
2534 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2535 if (!iwl_grab_nic_access(priv))
2536 iwl_release_nic_access(priv);
b481de9c
ZY
2537 spin_unlock_irqrestore(&priv->lock, flags);
2538
2539 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2540 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2541 "disabled by HW switch\n");
2542 return;
2543 }
2544
808e72a0
ZY
2545 if (priv->is_open)
2546 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY
2547 return;
2548}
2549
4a8a4322 2550void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
b481de9c
ZY
2551 u32 decrypt_res, struct ieee80211_rx_status *stats)
2552{
2553 u16 fc =
2554 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2555
f2c7e521 2556 if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
b481de9c
ZY
2557 return;
2558
2559 if (!(fc & IEEE80211_FCTL_PROTECTED))
2560 return;
2561
2562 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2563 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2564 case RX_RES_STATUS_SEC_TYPE_TKIP:
2565 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2566 RX_RES_STATUS_BAD_ICV_MIC)
2567 stats->flag |= RX_FLAG_MMIC_ERROR;
2568 case RX_RES_STATUS_SEC_TYPE_WEP:
2569 case RX_RES_STATUS_SEC_TYPE_CCMP:
2570 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2571 RX_RES_STATUS_DECRYPT_OK) {
2572 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2573 stats->flag |= RX_FLAG_DECRYPTED;
2574 }
2575 break;
2576
2577 default:
2578 break;
2579 }
2580}
2581
c8b0e6e1 2582#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
2583
2584#include "iwl-spectrum.h"
2585
2586#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2587#define BEACON_TIME_MASK_HIGH 0xFF000000
2588#define TIME_UNIT 1024
2589
2590/*
2591 * extended beacon time format
2592 * time in usec will be changed into a 32-bit value in 8:24 format
2593 * the high 1 byte is the beacon counts
2594 * the lower 3 bytes is the time in usec within one beacon interval
2595 */
2596
bb8c093b 2597static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
2598{
2599 u32 quot;
2600 u32 rem;
2601 u32 interval = beacon_interval * 1024;
2602
2603 if (!interval || !usec)
2604 return 0;
2605
2606 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2607 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2608
2609 return (quot << 24) + rem;
2610}
2611
2612/* base is usually what we get from ucode with each received frame,
2613 * the same as HW timer counter counting down
2614 */
2615
bb8c093b 2616static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
2617{
2618 u32 base_low = base & BEACON_TIME_MASK_LOW;
2619 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2620 u32 interval = beacon_interval * TIME_UNIT;
2621 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2622 (addon & BEACON_TIME_MASK_HIGH);
2623
2624 if (base_low > addon_low)
2625 res += base_low - addon_low;
2626 else if (base_low < addon_low) {
2627 res += interval + base_low - addon_low;
2628 res += (1 << 24);
2629 } else
2630 res += (1 << 24);
2631
2632 return cpu_to_le32(res);
2633}
2634
4a8a4322 2635static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
2636 struct ieee80211_measurement_params *params,
2637 u8 type)
2638{
600c0e11 2639 struct iwl_spectrum_cmd spectrum;
3d24a9f7 2640 struct iwl_rx_packet *res;
c2d79b48 2641 struct iwl_host_cmd cmd = {
b481de9c
ZY
2642 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2643 .data = (void *)&spectrum,
2644 .meta.flags = CMD_WANT_SKB,
2645 };
2646 u32 add_time = le64_to_cpu(params->start_time);
2647 int rc;
2648 int spectrum_resp_status;
2649 int duration = le16_to_cpu(params->duration);
2650
bb8c093b 2651 if (iwl3945_is_associated(priv))
b481de9c 2652 add_time =
bb8c093b 2653 iwl3945_usecs_to_beacons(
b481de9c
ZY
2654 le64_to_cpu(params->start_time) - priv->last_tsf,
2655 le16_to_cpu(priv->rxon_timing.beacon_interval));
2656
2657 memset(&spectrum, 0, sizeof(spectrum));
2658
2659 spectrum.channel_count = cpu_to_le16(1);
2660 spectrum.flags =
2661 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2662 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2663 cmd.len = sizeof(spectrum);
2664 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2665
bb8c093b 2666 if (iwl3945_is_associated(priv))
b481de9c 2667 spectrum.start_time =
bb8c093b 2668 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
2669 add_time,
2670 le16_to_cpu(priv->rxon_timing.beacon_interval));
2671 else
2672 spectrum.start_time = 0;
2673
2674 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2675 spectrum.channels[0].channel = params->channel;
2676 spectrum.channels[0].type = type;
f2c7e521 2677 if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
2678 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2679 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2680
bb8c093b 2681 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2682 if (rc)
2683 return rc;
2684
3d24a9f7 2685 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 2686 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 2687 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
2688 rc = -EIO;
2689 }
2690
2691 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2692 switch (spectrum_resp_status) {
2693 case 0: /* Command will be handled */
2694 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS
2695 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2696 res->u.spectrum.id);
b481de9c
ZY
2697 priv->measurement_status &= ~MEASUREMENT_READY;
2698 }
2699 priv->measurement_status |= MEASUREMENT_ACTIVE;
2700 rc = 0;
2701 break;
2702
2703 case 1: /* Command will not be handled */
2704 rc = -EAGAIN;
2705 break;
2706 }
2707
2708 dev_kfree_skb_any(cmd.meta.u.skb);
2709
2710 return rc;
2711}
2712#endif
2713
4a8a4322 2714static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 2715 struct iwl_rx_mem_buffer *rxb)
b481de9c 2716{
3d24a9f7
TW
2717 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
2718 struct iwl_alive_resp *palive;
b481de9c
ZY
2719 struct delayed_work *pwork;
2720
2721 palive = &pkt->u.alive_frame;
2722
2723 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2724 "0x%01X 0x%01X\n",
2725 palive->is_valid, palive->ver_type,
2726 palive->ver_subtype);
2727
2728 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2729 IWL_DEBUG_INFO("Initialization Alive received.\n");
3d24a9f7
TW
2730 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
2731 sizeof(struct iwl_alive_resp));
b481de9c
ZY
2732 pwork = &priv->init_alive_start;
2733 } else {
2734 IWL_DEBUG_INFO("Runtime Alive received.\n");
2735 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 2736 sizeof(struct iwl_alive_resp));
b481de9c 2737 pwork = &priv->alive_start;
bb8c093b 2738 iwl3945_disable_events(priv);
b481de9c
ZY
2739 }
2740
2741 /* We delay the ALIVE response by 5ms to
2742 * give the HW RF Kill time to activate... */
2743 if (palive->is_valid == UCODE_VALID_OK)
2744 queue_delayed_work(priv->workqueue, pwork,
2745 msecs_to_jiffies(5));
2746 else
39aadf8c 2747 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
2748}
2749
4a8a4322 2750static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 2751 struct iwl_rx_mem_buffer *rxb)
b481de9c 2752{
3d24a9f7 2753 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2754
2755 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2756 return;
2757}
2758
4a8a4322 2759static void iwl3945_rx_reply_error(struct iwl_priv *priv,
6100b588 2760 struct iwl_rx_mem_buffer *rxb)
b481de9c 2761{
3d24a9f7 2762 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 2763
15b1687c 2764 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
b481de9c
ZY
2765 "seq 0x%04X ser 0x%08X\n",
2766 le32_to_cpu(pkt->u.err_resp.error_type),
2767 get_cmd_string(pkt->u.err_resp.cmd_id),
2768 pkt->u.err_resp.cmd_id,
2769 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2770 le32_to_cpu(pkt->u.err_resp.error_info));
2771}
2772
2773#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2774
4a8a4322 2775static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 2776{
3d24a9f7 2777 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f2c7e521 2778 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
600c0e11 2779 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY
2780 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
2781 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
2782 rxon->channel = csa->channel;
f2c7e521 2783 priv->staging39_rxon.channel = csa->channel;
b481de9c
ZY
2784}
2785
4a8a4322 2786static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
6100b588 2787 struct iwl_rx_mem_buffer *rxb)
b481de9c 2788{
c8b0e6e1 2789#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3d24a9f7 2790 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 2791 struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY
2792
2793 if (!report->state) {
2794 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
2795 "Spectrum Measure Notification: Start\n");
2796 return;
2797 }
2798
2799 memcpy(&priv->measure_report, report, sizeof(*report));
2800 priv->measurement_status |= MEASUREMENT_READY;
2801#endif
2802}
2803
4a8a4322 2804static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
6100b588 2805 struct iwl_rx_mem_buffer *rxb)
b481de9c 2806{
c8b0e6e1 2807#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2808 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 2809 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY
2810 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
2811 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2812#endif
2813}
2814
4a8a4322 2815static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
6100b588 2816 struct iwl_rx_mem_buffer *rxb)
b481de9c 2817{
3d24a9f7 2818 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2819 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
2820 "notification for %s:\n",
2821 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
40b8ec0b
SO
2822 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
2823 le32_to_cpu(pkt->len));
b481de9c
ZY
2824}
2825
bb8c093b 2826static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 2827{
4a8a4322
AK
2828 struct iwl_priv *priv =
2829 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
2830 struct sk_buff *beacon;
2831
2832 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 2833 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
2834
2835 if (!beacon) {
15b1687c 2836 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
2837 return;
2838 }
2839
2840 mutex_lock(&priv->mutex);
2841 /* new beacon skb is allocated every time; dispose previous.*/
2842 if (priv->ibss_beacon)
2843 dev_kfree_skb(priv->ibss_beacon);
2844
2845 priv->ibss_beacon = beacon;
2846 mutex_unlock(&priv->mutex);
2847
bb8c093b 2848 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
2849}
2850
4a8a4322 2851static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 2852 struct iwl_rx_mem_buffer *rxb)
b481de9c 2853{
c8b0e6e1 2854#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2855 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 2856 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
2857 u8 rate = beacon->beacon_notify_hdr.rate;
2858
2859 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
2860 "tsf %d %d rate %d\n",
2861 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
2862 beacon->beacon_notify_hdr.failure_frame,
2863 le32_to_cpu(beacon->ibss_mgr_status),
2864 le32_to_cpu(beacon->high_tsf),
2865 le32_to_cpu(beacon->low_tsf), rate);
2866#endif
2867
05c914fe 2868 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
2869 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
2870 queue_work(priv->workqueue, &priv->beacon_update);
2871}
2872
2873/* Service response to REPLY_SCAN_CMD (0x80) */
4a8a4322 2874static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
6100b588 2875 struct iwl_rx_mem_buffer *rxb)
b481de9c 2876{
c8b0e6e1 2877#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2878 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
2879 struct iwl_scanreq_notification *notif =
2880 (struct iwl_scanreq_notification *)pkt->u.raw;
b481de9c
ZY
2881
2882 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
2883#endif
2884}
2885
2886/* Service SCAN_START_NOTIFICATION (0x82) */
4a8a4322 2887static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
6100b588 2888 struct iwl_rx_mem_buffer *rxb)
b481de9c 2889{
3d24a9f7 2890 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
2891 struct iwl_scanstart_notification *notif =
2892 (struct iwl_scanstart_notification *)pkt->u.raw;
b481de9c
ZY
2893 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
2894 IWL_DEBUG_SCAN("Scan start: "
2895 "%d [802.11%s] "
2896 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
2897 notif->channel,
2898 notif->band ? "bg" : "a",
2899 notif->tsf_high,
2900 notif->tsf_low, notif->status, notif->beacon_timer);
2901}
2902
2903/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
4a8a4322 2904static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
6100b588 2905 struct iwl_rx_mem_buffer *rxb)
b481de9c 2906{
3d24a9f7 2907 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
2908 struct iwl_scanresults_notification *notif =
2909 (struct iwl_scanresults_notification *)pkt->u.raw;
b481de9c
ZY
2910
2911 IWL_DEBUG_SCAN("Scan ch.res: "
2912 "%d [802.11%s] "
2913 "(TSF: 0x%08X:%08X) - %d "
2914 "elapsed=%lu usec (%dms since last)\n",
2915 notif->channel,
2916 notif->band ? "bg" : "a",
2917 le32_to_cpu(notif->tsf_high),
2918 le32_to_cpu(notif->tsf_low),
2919 le32_to_cpu(notif->statistics[0]),
2920 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
2921 jiffies_to_msecs(elapsed_jiffies
2922 (priv->last_scan_jiffies, jiffies)));
2923
2924 priv->last_scan_jiffies = jiffies;
7878a5a4 2925 priv->next_scan_jiffies = 0;
b481de9c
ZY
2926}
2927
2928/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
4a8a4322 2929static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
6100b588 2930 struct iwl_rx_mem_buffer *rxb)
b481de9c 2931{
3d24a9f7 2932 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253 2933 struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY
2934
2935 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
2936 scan_notif->scanned_channels,
2937 scan_notif->tsf_low,
2938 scan_notif->tsf_high, scan_notif->status);
2939
2940 /* The HW is no longer scanning */
2941 clear_bit(STATUS_SCAN_HW, &priv->status);
2942
2943 /* The scan completion notification came in, so kill that timer... */
2944 cancel_delayed_work(&priv->scan_check);
2945
2946 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR
2947 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
2948 "2.4" : "5.2",
b481de9c
ZY
2949 jiffies_to_msecs(elapsed_jiffies
2950 (priv->scan_pass_start, jiffies)));
2951
66b5004d
RR
2952 /* Remove this scanned band from the list of pending
2953 * bands to scan, band G precedes A in order of scanning
2954 * as seen in iwl3945_bg_request_scan */
2955 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
2956 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
2957 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
2958 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY
2959
2960 /* If a request to abort was given, or the scan did not succeed
2961 * then we reset the scan state machine and terminate,
2962 * re-queuing another scan if one has been requested */
2963 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2964 IWL_DEBUG_INFO("Aborted scan completed.\n");
2965 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
2966 } else {
2967 /* If there are more bands on this scan pass reschedule */
2968 if (priv->scan_bands > 0)
2969 goto reschedule;
2970 }
2971
2972 priv->last_scan_jiffies = jiffies;
7878a5a4 2973 priv->next_scan_jiffies = 0;
b481de9c
ZY
2974 IWL_DEBUG_INFO("Setting scan to off\n");
2975
2976 clear_bit(STATUS_SCANNING, &priv->status);
2977
2978 IWL_DEBUG_INFO("Scan took %dms\n",
2979 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
2980
2981 queue_work(priv->workqueue, &priv->scan_completed);
2982
2983 return;
2984
2985reschedule:
2986 priv->scan_pass_start = jiffies;
2987 queue_work(priv->workqueue, &priv->request_scan);
2988}
2989
2990/* Handle notification from uCode that card's power state is changing
2991 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 2992static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 2993 struct iwl_rx_mem_buffer *rxb)
b481de9c 2994{
3d24a9f7 2995 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2996 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
2997 unsigned long status = priv->status;
2998
2999 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3000 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3001 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3002
5d49f498 3003 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3004 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3005
3006 if (flags & HW_CARD_DISABLED)
3007 set_bit(STATUS_RF_KILL_HW, &priv->status);
3008 else
3009 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3010
3011
3012 if (flags & SW_CARD_DISABLED)
3013 set_bit(STATUS_RF_KILL_SW, &priv->status);
3014 else
3015 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3016
bb8c093b 3017 iwl3945_scan_cancel(priv);
b481de9c
ZY
3018
3019 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3020 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3021 (test_bit(STATUS_RF_KILL_SW, &status) !=
3022 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3023 queue_work(priv->workqueue, &priv->rf_kill);
3024 else
3025 wake_up_interruptible(&priv->wait_command_queue);
3026}
3027
3028/**
bb8c093b 3029 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
3030 *
3031 * Setup the RX handlers for each of the reply types sent from the uCode
3032 * to the host.
3033 *
3034 * This function chains into the hardware specific files for them to setup
3035 * any hardware specific handlers as well.
3036 */
4a8a4322 3037static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 3038{
bb8c093b
CH
3039 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3040 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3041 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3042 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3043 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH
3044 iwl3945_rx_spectrum_measure_notif;
3045 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3046 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH
3047 iwl3945_rx_pm_debug_statistics_notif;
3048 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3049
9fbab516
BC
3050 /*
3051 * The same handler is used for both the REPLY to a discrete
3052 * statistics request from the host as well as for the periodic
3053 * statistics notifications (after received beacons) from the uCode.
b481de9c 3054 */
bb8c093b
CH
3055 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3056 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3057
bb8c093b
CH
3058 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3059 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3060 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3061 iwl3945_rx_scan_results_notif;
b481de9c 3062 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH
3063 iwl3945_rx_scan_complete_notif;
3064 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3065
9fbab516 3066 /* Set up hardware specific Rx handlers */
bb8c093b 3067 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
3068}
3069
91c066f2
TW
3070/**
3071 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3072 * When FW advances 'R' index, all entries between old and new 'R' index
3073 * need to be reclaimed.
3074 */
4a8a4322 3075static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW
3076 int txq_id, int index)
3077{
188cf6c7 3078 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 3079 struct iwl_queue *q = &txq->q;
91c066f2
TW
3080 int nfreed = 0;
3081
3082 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
15b1687c 3083 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
91c066f2
TW
3084 "is out of range [0-%d] %d %d.\n", txq_id,
3085 index, q->n_bd, q->write_ptr, q->read_ptr);
3086 return;
3087 }
3088
3089 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3090 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3091 if (nfreed > 1) {
15b1687c 3092 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
91c066f2
TW
3093 q->write_ptr, q->read_ptr);
3094 queue_work(priv->workqueue, &priv->restart);
3095 break;
3096 }
3097 nfreed++;
3098 }
3099}
3100
3101
b481de9c 3102/**
bb8c093b 3103 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY
3104 * @rxb: Rx buffer to reclaim
3105 *
3106 * If an Rx buffer has an async callback associated with it the callback
3107 * will be executed. The attached skb (if present) will only be freed
3108 * if the callback returns 1
3109 */
4a8a4322 3110static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
6100b588 3111 struct iwl_rx_mem_buffer *rxb)
b481de9c 3112{
3d24a9f7 3113 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
3114 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3115 int txq_id = SEQ_TO_QUEUE(sequence);
3116 int index = SEQ_TO_INDEX(sequence);
600c0e11 3117 int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
b481de9c 3118 int cmd_index;
c2d79b48 3119 struct iwl_cmd *cmd;
b481de9c 3120
b481de9c
ZY
3121 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3122
188cf6c7
SO
3123 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3124 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
b481de9c
ZY
3125
3126 /* Input error checking is done when commands are added to queue. */
3127 if (cmd->meta.flags & CMD_WANT_SKB) {
3128 cmd->meta.source->u.skb = rxb->skb;
3129 rxb->skb = NULL;
3130 } else if (cmd->meta.u.callback &&
3131 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3132 rxb->skb = NULL;
3133
91c066f2 3134 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3135
3136 if (!(cmd->meta.flags & CMD_ASYNC)) {
3137 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3138 wake_up_interruptible(&priv->wait_command_queue);
3139 }
3140}
3141
3142/************************** RX-FUNCTIONS ****************************/
3143/*
3144 * Rx theory of operation
3145 *
3146 * The host allocates 32 DMA target addresses and passes the host address
3147 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3148 * 0 to 31
3149 *
3150 * Rx Queue Indexes
3151 * The host/firmware share two index registers for managing the Rx buffers.
3152 *
3153 * The READ index maps to the first position that the firmware may be writing
3154 * to -- the driver can read up to (but not including) this position and get
3155 * good data.
3156 * The READ index is managed by the firmware once the card is enabled.
3157 *
3158 * The WRITE index maps to the last position the driver has read from -- the
3159 * position preceding WRITE is the last slot the firmware can place a packet.
3160 *
3161 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3162 * WRITE = READ.
3163 *
9fbab516 3164 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
3165 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3166 *
9fbab516 3167 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
3168 * and fire the RX interrupt. The driver can then query the READ index and
3169 * process as many packets as possible, moving the WRITE index forward as it
3170 * resets the Rx queue buffers with new memory.
3171 *
3172 * The management in the driver is as follows:
3173 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3174 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3175 * to replenish the iwl->rxq->rx_free.
bb8c093b 3176 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
3177 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3178 * 'processed' and 'read' driver indexes as well)
3179 * + A received packet is processed and handed to the kernel network stack,
3180 * detached from the iwl->rxq. The driver 'processed' index is updated.
3181 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3182 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3183 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3184 * were enough free buffers and RX_STALLED is set it is cleared.
3185 *
3186 *
3187 * Driver sequence:
3188 *
9fbab516
BC
3189 * iwl3945_rx_queue_alloc() Allocates rx_free
3190 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3191 * iwl3945_rx_queue_restock
9fbab516 3192 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
3193 * queue, updates firmware pointers, and updates
3194 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3195 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
3196 *
3197 * -- enable interrupts --
6100b588 3198 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
3199 * READ INDEX, detaching the SKB from the pool.
3200 * Moves the packet buffer from queue to rx_used.
bb8c093b 3201 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
3202 * slots.
3203 * ...
3204 *
3205 */
3206
3207/**
bb8c093b 3208 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3209 */
cc2f362c 3210static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
b481de9c
ZY
3211{
3212 int s = q->read - q->write;
3213 if (s <= 0)
3214 s += RX_QUEUE_SIZE;
3215 /* keep some buffer to not confuse full and empty queue */
3216 s -= 2;
3217 if (s < 0)
3218 s = 0;
3219 return s;
3220}
3221
3222/**
bb8c093b 3223 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3224 */
4a8a4322 3225int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
b481de9c
ZY
3226{
3227 u32 reg = 0;
3228 int rc = 0;
3229 unsigned long flags;
3230
3231 spin_lock_irqsave(&q->lock, flags);
3232
3233 if (q->need_update == 0)
3234 goto exit_unlock;
3235
6440adb5 3236 /* If power-saving is in use, make sure device is awake */
b481de9c 3237 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
5d49f498 3238 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3239
3240 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
5d49f498 3241 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3242 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3243 goto exit_unlock;
3244 }
3245
5d49f498 3246 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
3247 if (rc)
3248 goto exit_unlock;
3249
6440adb5 3250 /* Device expects a multiple of 8 */
5d49f498 3251 iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
b481de9c 3252 q->write & ~0x7);
5d49f498 3253 iwl_release_nic_access(priv);
6440adb5
BC
3254
3255 /* Else device is assumed to be awake */
b481de9c 3256 } else
6440adb5 3257 /* Device expects a multiple of 8 */
5d49f498 3258 iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY
3259
3260
3261 q->need_update = 0;
3262
3263 exit_unlock:
3264 spin_unlock_irqrestore(&q->lock, flags);
3265 return rc;
3266}
3267
3268/**
9fbab516 3269 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3270 */
4a8a4322 3271static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
3272 dma_addr_t dma_addr)
3273{
3274 return cpu_to_le32((u32)dma_addr);
3275}
3276
3277/**
bb8c093b 3278 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3279 *
9fbab516 3280 * If there are slots in the RX queue that need to be restocked,
b481de9c 3281 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3282 * as we can, pulling from rx_free.
b481de9c
ZY
3283 *
3284 * This moves the 'write' index forward to catch up with 'processed', and
3285 * also updates the memory address in the firmware to reference the new
3286 * target buffer.
3287 */
4a8a4322 3288static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 3289{
cc2f362c 3290 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 3291 struct list_head *element;
6100b588 3292 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
3293 unsigned long flags;
3294 int write, rc;
3295
3296 spin_lock_irqsave(&rxq->lock, flags);
3297 write = rxq->write & ~0x7;
bb8c093b 3298 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3299 /* Get next free Rx buffer, remove from free list */
b481de9c 3300 element = rxq->rx_free.next;
6100b588 3301 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 3302 list_del(element);
6440adb5
BC
3303
3304 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 3305 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
3306 rxq->queue[rxq->write] = rxb;
3307 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3308 rxq->free_count--;
3309 }
3310 spin_unlock_irqrestore(&rxq->lock, flags);
3311 /* If the pre-allocated buffer pool is dropping low, schedule to
3312 * refill it */
3313 if (rxq->free_count <= RX_LOW_WATERMARK)
3314 queue_work(priv->workqueue, &priv->rx_replenish);
3315
3316
6440adb5
BC
3317 /* If we've added more space for the firmware to place data, tell it.
3318 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
3319 if ((write != (rxq->write & ~0x7))
3320 || (abs(rxq->write - rxq->read) > 7)) {
3321 spin_lock_irqsave(&rxq->lock, flags);
3322 rxq->need_update = 1;
3323 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3324 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
3325 if (rc)
3326 return rc;
3327 }
3328
3329 return 0;
3330}
3331
3332/**
bb8c093b 3333 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
3334 *
3335 * When moving to rx_free an SKB is allocated for the slot.
3336 *
bb8c093b 3337 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3338 * This is called as a scheduled work item (except for during initialization)
b481de9c 3339 */
4a8a4322 3340static void iwl3945_rx_allocate(struct iwl_priv *priv)
b481de9c 3341{
cc2f362c 3342 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 3343 struct list_head *element;
6100b588 3344 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
3345 unsigned long flags;
3346 spin_lock_irqsave(&rxq->lock, flags);
3347 while (!list_empty(&rxq->rx_used)) {
3348 element = rxq->rx_used.next;
6100b588 3349 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
6440adb5
BC
3350
3351 /* Alloc a new receive buffer */
b481de9c
ZY
3352 rxb->skb =
3353 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3354 if (!rxb->skb) {
3355 if (net_ratelimit())
978785a3 3356 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY
3357 /* We don't reschedule replenish work here -- we will
3358 * call the restock method and if it still needs
3359 * more buffers it will schedule replenish */
3360 break;
3361 }
12342c47
ZY
3362
3363 /* If radiotap head is required, reserve some headroom here.
3364 * The physical head count is a variable rx_stats->phy_count.
3365 * We reserve 4 bytes here. Plus these extra bytes, the
3366 * headroom of the physical head should be enough for the
3367 * radiotap head that iwl3945 supported. See iwl3945_rt.
3368 */
3369 skb_reserve(rxb->skb, 4);
3370
b481de9c
ZY
3371 priv->alloc_rxb_skb++;
3372 list_del(element);
6440adb5
BC
3373
3374 /* Get physical address of RB/SKB */
6100b588 3375 rxb->real_dma_addr =
b481de9c
ZY
3376 pci_map_single(priv->pci_dev, rxb->skb->data,
3377 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3378 list_add_tail(&rxb->list, &rxq->rx_free);
3379 rxq->free_count++;
3380 }
3381 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA
3382}
3383
3384/*
3385 * this should be called while priv->lock is locked
3386 */
4fd1f841 3387static void __iwl3945_rx_replenish(void *data)
5c0eef96 3388{
4a8a4322 3389 struct iwl_priv *priv = data;
5c0eef96
MA
3390
3391 iwl3945_rx_allocate(priv);
3392 iwl3945_rx_queue_restock(priv);
3393}
3394
3395
3396void iwl3945_rx_replenish(void *data)
3397{
4a8a4322 3398 struct iwl_priv *priv = data;
5c0eef96
MA
3399 unsigned long flags;
3400
3401 iwl3945_rx_allocate(priv);
b481de9c
ZY
3402
3403 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3404 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
3405 spin_unlock_irqrestore(&priv->lock, flags);
3406}
3407
3408/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3409 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY
3410 * This free routine walks the list of POOL entries and if SKB is set to
3411 * non NULL it is unmapped and freed
3412 */
4a8a4322 3413static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY
3414{
3415 int i;
3416 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3417 if (rxq->pool[i].skb != NULL) {
3418 pci_unmap_single(priv->pci_dev,
6100b588 3419 rxq->pool[i].real_dma_addr,
b481de9c
ZY
3420 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3421 dev_kfree_skb(rxq->pool[i].skb);
3422 }
3423 }
3424
3425 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3426 rxq->dma_addr);
3427 rxq->bd = NULL;
3428}
3429
4a8a4322 3430int iwl3945_rx_queue_alloc(struct iwl_priv *priv)
b481de9c 3431{
cc2f362c 3432 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
3433 struct pci_dev *dev = priv->pci_dev;
3434 int i;
3435
3436 spin_lock_init(&rxq->lock);
3437 INIT_LIST_HEAD(&rxq->rx_free);
3438 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
BC
3439
3440 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY
3441 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3442 if (!rxq->bd)
3443 return -ENOMEM;
6440adb5 3444
b481de9c
ZY
3445 /* Fill the rx_used queue with _all_ of the Rx buffers */
3446 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3447 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3448
b481de9c
ZY
3449 /* Set us so that we have processed and used all buffers, but have
3450 * not restocked the Rx queue with fresh buffers */
3451 rxq->read = rxq->write = 0;
3452 rxq->free_count = 0;
3453 rxq->need_update = 0;
3454 return 0;
3455}
3456
4a8a4322 3457void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY
3458{
3459 unsigned long flags;
3460 int i;
3461 spin_lock_irqsave(&rxq->lock, flags);
3462 INIT_LIST_HEAD(&rxq->rx_free);
3463 INIT_LIST_HEAD(&rxq->rx_used);
3464 /* Fill the rx_used queue with _all_ of the Rx buffers */
3465 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3466 /* In the reset function, these buffers may have been allocated
3467 * to an SKB, so we need to unmap and free potential storage */
3468 if (rxq->pool[i].skb != NULL) {
3469 pci_unmap_single(priv->pci_dev,
6100b588 3470 rxq->pool[i].real_dma_addr,
b481de9c
ZY
3471 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3472 priv->alloc_rxb_skb--;
3473 dev_kfree_skb(rxq->pool[i].skb);
3474 rxq->pool[i].skb = NULL;
3475 }
3476 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3477 }
3478
3479 /* Set us so that we have processed and used all buffers, but have
3480 * not restocked the Rx queue with fresh buffers */
3481 rxq->read = rxq->write = 0;
3482 rxq->free_count = 0;
3483 spin_unlock_irqrestore(&rxq->lock, flags);
3484}
3485
3486/* Convert linear signal-to-noise ratio into dB */
3487static u8 ratio2dB[100] = {
3488/* 0 1 2 3 4 5 6 7 8 9 */
3489 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3490 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3491 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3492 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3493 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3494 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3495 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3496 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3497 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3498 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3499};
3500
3501/* Calculates a relative dB value from a ratio of linear
3502 * (i.e. not dB) signal levels.
3503 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3504int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3505{
221c80cf
AB
3506 /* 1000:1 or higher just report as 60 dB */
3507 if (sig_ratio >= 1000)
b481de9c
ZY
3508 return 60;
3509
221c80cf 3510 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3511 * add 20 dB to make up for divide by 10 */
221c80cf 3512 if (sig_ratio >= 100)
3ac7f146 3513 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
3514
3515 /* We shouldn't see this */
3516 if (sig_ratio < 1)
3517 return 0;
3518
3519 /* Use table for ratios 1:1 - 99:1 */
3520 return (int)ratio2dB[sig_ratio];
3521}
3522
3523#define PERFECT_RSSI (-20) /* dBm */
3524#define WORST_RSSI (-95) /* dBm */
3525#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3526
3527/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3528 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3529 * about formulas used below. */
bb8c093b 3530int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
3531{
3532 int sig_qual;
3533 int degradation = PERFECT_RSSI - rssi_dbm;
3534
3535 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3536 * as indicator; formula is (signal dbm - noise dbm).
3537 * SNR at or above 40 is a great signal (100%).
3538 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3539 * Weakest usable signal is usually 10 - 15 dB SNR. */
3540 if (noise_dbm) {
3541 if (rssi_dbm - noise_dbm >= 40)
3542 return 100;
3543 else if (rssi_dbm < noise_dbm)
3544 return 0;
3545 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3546
3547 /* Else use just the signal level.
3548 * This formula is a least squares fit of data points collected and
3549 * compared with a reference system that had a percentage (%) display
3550 * for signal quality. */
3551 } else
3552 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3553 (15 * RSSI_RANGE + 62 * degradation)) /
3554 (RSSI_RANGE * RSSI_RANGE);
3555
3556 if (sig_qual > 100)
3557 sig_qual = 100;
3558 else if (sig_qual < 1)
3559 sig_qual = 0;
3560
3561 return sig_qual;
3562}
3563
3564/**
9fbab516 3565 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
3566 *
3567 * Uses the priv->rx_handlers callback function array to invoke
3568 * the appropriate handlers, including command responses,
3569 * frame-received notifications, and other notifications.
3570 */
4a8a4322 3571static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 3572{
6100b588 3573 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 3574 struct iwl_rx_packet *pkt;
cc2f362c 3575 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
3576 u32 r, i;
3577 int reclaim;
3578 unsigned long flags;
5c0eef96 3579 u8 fill_rx = 0;
d68ab680 3580 u32 count = 8;
b481de9c 3581
6440adb5
BC
3582 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3583 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 3584 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
3585 i = rxq->read;
3586
5c0eef96
MA
3587 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3588 fill_rx = 1;
b481de9c
ZY
3589 /* Rx interrupt, but nothing sent from uCode */
3590 if (i == r)
3591 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3592
3593 while (i != r) {
3594 rxb = rxq->queue[i];
3595
9fbab516 3596 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
3597 * then a bug has been introduced in the queue refilling
3598 * routines -- catch it here */
3599 BUG_ON(rxb == NULL);
3600
3601 rxq->queue[i] = NULL;
3602
6100b588 3603 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
b481de9c
ZY
3604 IWL_RX_BUF_SIZE,
3605 PCI_DMA_FROMDEVICE);
3d24a9f7 3606 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
3607
3608 /* Reclaim a command buffer only if this packet is a response
3609 * to a (driver-originated) command.
3610 * If the packet (e.g. Rx frame) originated from uCode,
3611 * there is no command buffer to reclaim.
3612 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3613 * but apparently a few don't get set; catch them here. */
3614 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3615 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3616 (pkt->hdr.cmd != REPLY_TX);
3617
3618 /* Based on type of command response or notification,
3619 * handle those that need handling via function in
bb8c093b 3620 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 3621 if (priv->rx_handlers[pkt->hdr.cmd]) {
40b8ec0b 3622 IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
3623 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3624 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3625 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3626 } else {
3627 /* No handling needed */
40b8ec0b 3628 IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
3629 "r %d i %d No handler needed for %s, 0x%02x\n",
3630 r, i, get_cmd_string(pkt->hdr.cmd),
3631 pkt->hdr.cmd);
3632 }
3633
3634 if (reclaim) {
9fbab516
BC
3635 /* Invoke any callbacks, transfer the skb to caller, and
3636 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY
3637 * as we reclaim the driver command queue */
3638 if (rxb && rxb->skb)
bb8c093b 3639 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c 3640 else
39aadf8c 3641 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
3642 }
3643
3644 /* For now we just don't re-use anything. We can tweak this
3645 * later to try and re-use notification packets and SKBs that
3646 * fail to Rx correctly */
3647 if (rxb->skb != NULL) {
3648 priv->alloc_rxb_skb--;
3649 dev_kfree_skb_any(rxb->skb);
3650 rxb->skb = NULL;
3651 }
3652
6100b588 3653 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
b481de9c
ZY
3654 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3655 spin_lock_irqsave(&rxq->lock, flags);
3656 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3657 spin_unlock_irqrestore(&rxq->lock, flags);
3658 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
3659 /* If there are a lot of unused frames,
3660 * restock the Rx queue so ucode won't assert. */
3661 if (fill_rx) {
3662 count++;
3663 if (count >= 8) {
3664 priv->rxq.read = i;
3665 __iwl3945_rx_replenish(priv);
3666 count = 0;
3667 }
3668 }
b481de9c
ZY
3669 }
3670
3671 /* Backtrack one entry */
3672 priv->rxq.read = i;
bb8c093b 3673 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
3674}
3675
6440adb5
BC
3676/**
3677 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3678 */
4a8a4322 3679static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
188cf6c7 3680 struct iwl_tx_queue *txq)
b481de9c
ZY
3681{
3682 u32 reg = 0;
3683 int rc = 0;
3684 int txq_id = txq->q.id;
3685
3686 if (txq->need_update == 0)
3687 return rc;
3688
3689 /* if we're trying to save power */
3690 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3691 /* wake up nic if it's powered down ...
3692 * uCode will wake up, and interrupt us again, so next
3693 * time we'll skip this part. */
5d49f498 3694 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3695
3696 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3697 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
5d49f498 3698 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3699 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3700 return rc;
3701 }
3702
3703 /* restore this queue's parameters in nic hardware. */
5d49f498 3704 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
3705 if (rc)
3706 return rc;
5d49f498 3707 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3708 txq->q.write_ptr | (txq_id << 8));
5d49f498 3709 iwl_release_nic_access(priv);
b481de9c
ZY
3710
3711 /* else not in power-save mode, uCode will never sleep when we're
3712 * trying to tx (during RFKILL, we're not trying to tx). */
3713 } else
5d49f498 3714 iwl_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3715 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY
3716
3717 txq->need_update = 0;
3718
3719 return rc;
3720}
3721
c8b0e6e1 3722#ifdef CONFIG_IWL3945_DEBUG
4a8a4322 3723static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
40b8ec0b 3724 struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY
3725{
3726 IWL_DEBUG_RADIO("RX CONFIG:\n");
40b8ec0b 3727 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY
3728 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3729 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3730 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3731 le32_to_cpu(rxon->filter_flags));
3732 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3733 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3734 rxon->ofdm_basic_rates);
3735 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB
3736 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3737 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY
3738 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3739}
3740#endif
3741
4a8a4322 3742static void iwl3945_enable_interrupts(struct iwl_priv *priv)
b481de9c
ZY
3743{
3744 IWL_DEBUG_ISR("Enabling interrupts\n");
3745 set_bit(STATUS_INT_ENABLED, &priv->status);
5d49f498 3746 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY
3747}
3748
0359facc
MA
3749
3750/* call this function to flush any scheduled tasklet */
4a8a4322 3751static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 3752{
a96a27f9 3753 /* wait to make sure we flush pending tasklet*/
0359facc
MA
3754 synchronize_irq(priv->pci_dev->irq);
3755 tasklet_kill(&priv->irq_tasklet);
3756}
3757
3758
4a8a4322 3759static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
b481de9c
ZY
3760{
3761 clear_bit(STATUS_INT_ENABLED, &priv->status);
3762
3763 /* disable interrupts from uCode/NIC to host */
5d49f498 3764 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
3765
3766 /* acknowledge/clear/reset any interrupts still pending
3767 * from uCode or flow handler (Rx/Tx DMA) */
5d49f498
AK
3768 iwl_write32(priv, CSR_INT, 0xffffffff);
3769 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY
3770 IWL_DEBUG_ISR("Disabled interrupts\n");
3771}
3772
3773static const char *desc_lookup(int i)
3774{
3775 switch (i) {
3776 case 1:
3777 return "FAIL";
3778 case 2:
3779 return "BAD_PARAM";
3780 case 3:
3781 return "BAD_CHECKSUM";
3782 case 4:
3783 return "NMI_INTERRUPT";
3784 case 5:
3785 return "SYSASSERT";
3786 case 6:
3787 return "FATAL_ERROR";
3788 }
3789
3790 return "UNKNOWN";
3791}
3792
3793#define ERROR_START_OFFSET (1 * sizeof(u32))
3794#define ERROR_ELEM_SIZE (7 * sizeof(u32))
3795
4a8a4322 3796static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
3797{
3798 u32 i;
3799 u32 desc, time, count, base, data1;
3800 u32 blink1, blink2, ilink1, ilink2;
3801 int rc;
3802
3803 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
3804
bb8c093b 3805 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 3806 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
3807 return;
3808 }
3809
5d49f498 3810 rc = iwl_grab_nic_access(priv);
b481de9c 3811 if (rc) {
39aadf8c 3812 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY
3813 return;
3814 }
3815
5d49f498 3816 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
3817
3818 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
3819 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
3820 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
3821 priv->status, count);
b481de9c
ZY
3822 }
3823
15b1687c 3824 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
3825 "ilink1 nmiPC Line\n");
3826 for (i = ERROR_START_OFFSET;
3827 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
3828 i += ERROR_ELEM_SIZE) {
5d49f498 3829 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 3830 time =
5d49f498 3831 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 3832 blink1 =
5d49f498 3833 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 3834 blink2 =
5d49f498 3835 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 3836 ilink1 =
5d49f498 3837 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 3838 ilink2 =
5d49f498 3839 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 3840 data1 =
5d49f498 3841 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 3842
15b1687c
WT
3843 IWL_ERR(priv,
3844 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
3845 desc_lookup(desc), desc, time, blink1, blink2,
3846 ilink1, ilink2, data1);
b481de9c
ZY
3847 }
3848
5d49f498 3849 iwl_release_nic_access(priv);
b481de9c
ZY
3850
3851}
3852
f58177b9 3853#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
3854
3855/**
bb8c093b 3856 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 3857 *
5d49f498 3858 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
b481de9c 3859 */
4a8a4322 3860static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
3861 u32 num_events, u32 mode)
3862{
3863 u32 i;
3864 u32 base; /* SRAM byte address of event log header */
3865 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
3866 u32 ptr; /* SRAM byte address of log data */
3867 u32 ev, time, data; /* event log data */
3868
3869 if (num_events == 0)
3870 return;
3871
3872 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
3873
3874 if (mode == 0)
3875 event_size = 2 * sizeof(u32);
3876 else
3877 event_size = 3 * sizeof(u32);
3878
3879 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
3880
3881 /* "time" is actually "data" for mode 0 (no timestamp).
3882 * place event id # at far right for easier visual parsing. */
3883 for (i = 0; i < num_events; i++) {
5d49f498 3884 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 3885 ptr += sizeof(u32);
5d49f498 3886 time = iwl_read_targ_mem(priv, ptr);
b481de9c 3887 ptr += sizeof(u32);
15b1687c
WT
3888 if (mode == 0) {
3889 /* data, ev */
3890 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
3891 } else {
5d49f498 3892 data = iwl_read_targ_mem(priv, ptr);
b481de9c 3893 ptr += sizeof(u32);
15b1687c 3894 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
3895 }
3896 }
3897}
3898
4a8a4322 3899static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c
ZY
3900{
3901 int rc;
3902 u32 base; /* SRAM byte address of event log header */
3903 u32 capacity; /* event log capacity in # entries */
3904 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
3905 u32 num_wraps; /* # times uCode wrapped to top of log */
3906 u32 next_entry; /* index of next entry to be written by uCode */
3907 u32 size; /* # entries that we'll print */
3908
3909 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 3910 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 3911 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
3912 return;
3913 }
3914
5d49f498 3915 rc = iwl_grab_nic_access(priv);
b481de9c 3916 if (rc) {
39aadf8c 3917 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY
3918 return;
3919 }
3920
3921 /* event log header */
5d49f498
AK
3922 capacity = iwl_read_targ_mem(priv, base);
3923 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
3924 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
3925 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
3926
3927 size = num_wraps ? capacity : next_entry;
3928
3929 /* bail out if nothing in log */
3930 if (size == 0) {
15b1687c 3931 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
5d49f498 3932 iwl_release_nic_access(priv);
b481de9c
ZY
3933 return;
3934 }
3935
15b1687c 3936 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
3937 size, num_wraps);
3938
3939 /* if uCode has wrapped back to top of log, start at the oldest entry,
3940 * i.e the next one that uCode would fill. */
3941 if (num_wraps)
bb8c093b 3942 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
3943 capacity - next_entry, mode);
3944
3945 /* (then/else) start at top of log */
bb8c093b 3946 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 3947
5d49f498 3948 iwl_release_nic_access(priv);
b481de9c
ZY
3949}
3950
3951/**
bb8c093b 3952 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 3953 */
4a8a4322 3954static void iwl3945_irq_handle_error(struct iwl_priv *priv)
b481de9c 3955{
bb8c093b 3956 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY
3957 set_bit(STATUS_FW_ERROR, &priv->status);
3958
3959 /* Cancel currently queued command. */
3960 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3961
c8b0e6e1 3962#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3963 if (priv->debug_level & IWL_DL_FW_ERRORS) {
bb8c093b
CH
3964 iwl3945_dump_nic_error_log(priv);
3965 iwl3945_dump_nic_event_log(priv);
f2c7e521 3966 iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
b481de9c
ZY
3967 }
3968#endif
3969
3970 wake_up_interruptible(&priv->wait_command_queue);
3971
3972 /* Keep the restart process from trying to send host
3973 * commands by clearing the INIT status bit */
3974 clear_bit(STATUS_READY, &priv->status);
3975
3976 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3977 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
3978 "Restarting adapter due to uCode error.\n");
3979
bb8c093b 3980 if (iwl3945_is_associated(priv)) {
f2c7e521
AK
3981 memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
3982 sizeof(priv->recovery39_rxon));
b481de9c
ZY
3983 priv->error_recovering = 1;
3984 }
3985 queue_work(priv->workqueue, &priv->restart);
3986 }
3987}
3988
4a8a4322 3989static void iwl3945_error_recovery(struct iwl_priv *priv)
b481de9c
ZY
3990{
3991 unsigned long flags;
3992
f2c7e521
AK
3993 memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
3994 sizeof(priv->staging39_rxon));
3995 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 3996 iwl3945_commit_rxon(priv);
b481de9c 3997
bb8c093b 3998 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY
3999
4000 spin_lock_irqsave(&priv->lock, flags);
f2c7e521 4001 priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
b481de9c
ZY
4002 priv->error_recovering = 0;
4003 spin_unlock_irqrestore(&priv->lock, flags);
4004}
4005
4a8a4322 4006static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
4007{
4008 u32 inta, handled = 0;
4009 u32 inta_fh;
4010 unsigned long flags;
c8b0e6e1 4011#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
4012 u32 inta_mask;
4013#endif
4014
4015 spin_lock_irqsave(&priv->lock, flags);
4016
4017 /* Ack/clear/reset pending uCode interrupts.
4018 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4019 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
4020 inta = iwl_read32(priv, CSR_INT);
4021 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
4022
4023 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4024 * Any new interrupts that happen after this, either while we're
4025 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
4026 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4027 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4028
c8b0e6e1 4029#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 4030 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 4031 /* just for debug */
5d49f498 4032 inta_mask = iwl_read32(priv, CSR_INT_MASK);
b481de9c
ZY
4033 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4034 inta, inta_mask, inta_fh);
4035 }
4036#endif
4037
4038 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4039 * atomic, make sure that inta covers all the interrupts that
4040 * we've discovered, even if FH interrupt came in just after
4041 * reading CSR_INT. */
6f83eaa1 4042 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4043 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4044 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
4045 inta |= CSR_INT_BIT_FH_TX;
4046
4047 /* Now service all interrupt bits discovered above. */
4048 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 4049 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
4050
4051 /* Tell the device to stop sending interrupts */
bb8c093b 4052 iwl3945_disable_interrupts(priv);
b481de9c 4053
bb8c093b 4054 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4055
4056 handled |= CSR_INT_BIT_HW_ERR;
4057
4058 spin_unlock_irqrestore(&priv->lock, flags);
4059
4060 return;
4061 }
4062
c8b0e6e1 4063#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 4064 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 4065 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP
4066 if (inta & CSR_INT_BIT_SCD)
4067 IWL_DEBUG_ISR("Scheduler finished to transmit "
4068 "the frame/frames.\n");
b481de9c
ZY
4069
4070 /* Alive notification via Rx interrupt will do the real work */
4071 if (inta & CSR_INT_BIT_ALIVE)
4072 IWL_DEBUG_ISR("Alive interrupt\n");
4073 }
4074#endif
4075 /* Safely ignore these bits for debug checks below */
25c03d8e 4076 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 4077
b481de9c
ZY
4078 /* Error detected by uCode */
4079 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
4080 IWL_ERR(priv, "Microcode SW error detected. "
4081 "Restarting 0x%X.\n", inta);
bb8c093b 4082 iwl3945_irq_handle_error(priv);
b481de9c
ZY
4083 handled |= CSR_INT_BIT_SW_ERR;
4084 }
4085
4086 /* uCode wakes up after power-down sleep */
4087 if (inta & CSR_INT_BIT_WAKEUP) {
4088 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b 4089 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
188cf6c7
SO
4090 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4091 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4092 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4093 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4094 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4095 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
4096
4097 handled |= CSR_INT_BIT_WAKEUP;
4098 }
4099
4100 /* All uCode command responses, including Tx command responses,
4101 * Rx "responses" (frame-received notification), and other
4102 * notifications from uCode come through here*/
4103 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4104 iwl3945_rx_handle(priv);
b481de9c
ZY
4105 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4106 }
4107
4108 if (inta & CSR_INT_BIT_FH_TX) {
4109 IWL_DEBUG_ISR("Tx interrupt\n");
4110
5d49f498
AK
4111 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4112 if (!iwl_grab_nic_access(priv)) {
4113 iwl_write_direct32(priv, FH39_TCSR_CREDIT
bddadf86 4114 (FH39_SRVC_CHNL), 0x0);
5d49f498 4115 iwl_release_nic_access(priv);
b481de9c
ZY
4116 }
4117 handled |= CSR_INT_BIT_FH_TX;
4118 }
4119
4120 if (inta & ~handled)
15b1687c 4121 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
b481de9c
ZY
4122
4123 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 4124 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 4125 inta & ~CSR_INI_SET_MASK);
39aadf8c 4126 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
4127 }
4128
4129 /* Re-enable all interrupts */
0359facc
MA
4130 /* only Re-enable if disabled by irq */
4131 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4132 iwl3945_enable_interrupts(priv);
b481de9c 4133
c8b0e6e1 4134#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 4135 if (priv->debug_level & (IWL_DL_ISR)) {
5d49f498
AK
4136 inta = iwl_read32(priv, CSR_INT);
4137 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4138 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4139 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4140 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4141 }
4142#endif
4143 spin_unlock_irqrestore(&priv->lock, flags);
4144}
4145
bb8c093b 4146static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4147{
4a8a4322 4148 struct iwl_priv *priv = data;
b481de9c
ZY
4149 u32 inta, inta_mask;
4150 u32 inta_fh;
4151 if (!priv)
4152 return IRQ_NONE;
4153
4154 spin_lock(&priv->lock);
4155
4156 /* Disable (but don't clear!) interrupts here to avoid
4157 * back-to-back ISRs and sporadic interrupts from our NIC.
4158 * If we have something to service, the tasklet will re-enable ints.
4159 * If we *don't* have something, we'll re-enable before leaving here. */
5d49f498
AK
4160 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
4161 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4162
4163 /* Discover which interrupts are active/pending */
5d49f498
AK
4164 inta = iwl_read32(priv, CSR_INT);
4165 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4166
4167 /* Ignore interrupt if there's nothing in NIC to service.
4168 * This may be due to IRQ shared with another device,
4169 * or due to sporadic interrupts thrown from our NIC. */
4170 if (!inta && !inta_fh) {
4171 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4172 goto none;
4173 }
4174
4175 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4176 /* Hardware disappeared */
39aadf8c 4177 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
cb4da1a3 4178 goto unplugged;
b481de9c
ZY
4179 }
4180
4181 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4182 inta, inta_mask, inta_fh);
4183
25c03d8e
JP
4184 inta &= ~CSR_INT_BIT_SCD;
4185
bb8c093b 4186 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP
4187 if (likely(inta || inta_fh))
4188 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4189unplugged:
b481de9c
ZY
4190 spin_unlock(&priv->lock);
4191
4192 return IRQ_HANDLED;
4193
4194 none:
4195 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA
4196 /* only Re-enable if disabled by irq */
4197 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4198 iwl3945_enable_interrupts(priv);
b481de9c
ZY
4199 spin_unlock(&priv->lock);
4200 return IRQ_NONE;
4201}
4202
4203/************************** EEPROM BANDS ****************************
4204 *
bb8c093b 4205 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY
4206 * EEPROM contents to the specific channel number supported for each
4207 * band.
4208 *
f2c7e521 4209 * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
b481de9c
ZY
4210 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4211 * The specific geography and calibration information for that channel
4212 * is contained in the eeprom map itself.
4213 *
4214 * During init, we copy the eeprom information and channel map
4215 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4216 *
4217 * channel_map_24/52 provides the index in the channel_info array for a
4218 * given channel. We have to have two separate maps as there is channel
4219 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4220 * band_2
4221 *
4222 * A value of 0xff stored in the channel_map indicates that the channel
4223 * is not supported by the hardware at all.
4224 *
4225 * A value of 0xfe in the channel_map indicates that the channel is not
4226 * valid for Tx with the current hardware. This means that
4227 * while the system can tune and receive on a given channel, it may not
4228 * be able to associate or transmit any frames on that
4229 * channel. There is no corresponding channel information for that
4230 * entry.
4231 *
4232 *********************************************************************/
4233
4234/* 2.4 GHz */
bb8c093b 4235static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY
4236 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4237};
4238
4239/* 5.2 GHz bands */
9fbab516 4240static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY
4241 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4242};
4243
9fbab516 4244static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY
4245 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4246};
4247
bb8c093b 4248static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY
4249 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4250};
4251
bb8c093b 4252static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY
4253 145, 149, 153, 157, 161, 165
4254};
4255
4a8a4322 4256static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
b481de9c 4257 int *eeprom_ch_count,
0f741d99 4258 const struct iwl_eeprom_channel
b481de9c
ZY
4259 **eeprom_ch_info,
4260 const u8 **eeprom_ch_index)
4261{
4262 switch (band) {
4263 case 1: /* 2.4GHz band */
bb8c093b 4264 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
f2c7e521 4265 *eeprom_ch_info = priv->eeprom39.band_1_channels;
bb8c093b 4266 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4267 break;
9fbab516 4268 case 2: /* 4.9GHz band */
bb8c093b 4269 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
f2c7e521 4270 *eeprom_ch_info = priv->eeprom39.band_2_channels;
bb8c093b 4271 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY
4272 break;
4273 case 3: /* 5.2GHz band */
bb8c093b 4274 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
f2c7e521 4275 *eeprom_ch_info = priv->eeprom39.band_3_channels;
bb8c093b 4276 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4277 break;
9fbab516 4278 case 4: /* 5.5GHz band */
bb8c093b 4279 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
f2c7e521 4280 *eeprom_ch_info = priv->eeprom39.band_4_channels;
bb8c093b 4281 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4282 break;
9fbab516 4283 case 5: /* 5.7GHz band */
bb8c093b 4284 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
f2c7e521 4285 *eeprom_ch_info = priv->eeprom39.band_5_channels;
bb8c093b 4286 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY
4287 break;
4288 default:
4289 BUG();
4290 return;
4291 }
4292}
4293
6440adb5
BC
4294/**
4295 * iwl3945_get_channel_info - Find driver's private channel info
4296 *
4297 * Based on band and channel number.
4298 */
d20b3c65 4299const struct iwl_channel_info *
4a8a4322 4300iwl3945_get_channel_info(const struct iwl_priv *priv,
d20b3c65 4301 enum ieee80211_band band, u16 channel)
b481de9c
ZY
4302{
4303 int i;
4304
8318d78a
JB
4305 switch (band) {
4306 case IEEE80211_BAND_5GHZ:
b481de9c
ZY
4307 for (i = 14; i < priv->channel_count; i++) {
4308 if (priv->channel_info[i].channel == channel)
4309 return &priv->channel_info[i];
4310 }
4311 break;
4312
8318d78a 4313 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
4314 if (channel >= 1 && channel <= 14)
4315 return &priv->channel_info[channel - 1];
4316 break;
8318d78a
JB
4317 case IEEE80211_NUM_BANDS:
4318 WARN_ON(1);
b481de9c
ZY
4319 }
4320
4321 return NULL;
4322}
4323
4324#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4325 ? # x " " : "")
4326
6440adb5
BC
4327/**
4328 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4329 */
4a8a4322 4330static int iwl3945_init_channel_map(struct iwl_priv *priv)
b481de9c
ZY
4331{
4332 int eeprom_ch_count = 0;
4333 const u8 *eeprom_ch_index = NULL;
0f741d99 4334 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4335 int band, ch;
d20b3c65 4336 struct iwl_channel_info *ch_info;
b481de9c
ZY
4337
4338 if (priv->channel_count) {
4339 IWL_DEBUG_INFO("Channel map already initialized.\n");
4340 return 0;
4341 }
4342
f2c7e521 4343 if (priv->eeprom39.version < 0x2f) {
39aadf8c 4344 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
f2c7e521 4345 priv->eeprom39.version);
b481de9c
ZY
4346 return -EINVAL;
4347 }
4348
4349 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4350
4351 priv->channel_count =
bb8c093b
CH
4352 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4353 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4354 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4355 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4356 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY
4357
4358 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4359
d20b3c65 4360 priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
b481de9c
ZY
4361 priv->channel_count, GFP_KERNEL);
4362 if (!priv->channel_info) {
15b1687c 4363 IWL_ERR(priv, "Could not allocate channel_info\n");
b481de9c
ZY
4364 priv->channel_count = 0;
4365 return -ENOMEM;
4366 }
4367
4368 ch_info = priv->channel_info;
4369
4370 /* Loop through the 5 EEPROM bands adding them in order to the
4371 * channel map we maintain (that contains additional information than
4372 * what just in the EEPROM) */
4373 for (band = 1; band <= 5; band++) {
4374
bb8c093b 4375 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
4376 &eeprom_ch_info, &eeprom_ch_index);
4377
4378 /* Loop through each band adding each of the channels */
4379 for (ch = 0; ch < eeprom_ch_count; ch++) {
4380 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB
4381 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4382 IEEE80211_BAND_5GHZ;
b481de9c
ZY
4383
4384 /* permanently store EEPROM's channel regulatory flags
4385 * and max power in channel info database. */
4386 ch_info->eeprom = eeprom_ch_info[ch];
4387
4388 /* Copy the run-time flags so they are there even on
4389 * invalid channels */
4390 ch_info->flags = eeprom_ch_info[ch].flags;
4391
4392 if (!(is_channel_valid(ch_info))) {
4393 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4394 "No traffic\n",
4395 ch_info->channel,
4396 ch_info->flags,
4397 is_channel_a_band(ch_info) ?
4398 "5.2" : "2.4");
4399 ch_info++;
4400 continue;
4401 }
4402
4403 /* Initialize regulatory-based run-time data */
4404 ch_info->max_power_avg = ch_info->curr_txpow =
4405 eeprom_ch_info[ch].max_power_avg;
4406 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4407 ch_info->min_power = 0;
4408
fe7c4040 4409 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY
4410 " %ddBm): Ad-Hoc %ssupported\n",
4411 ch_info->channel,
4412 is_channel_a_band(ch_info) ?
4413 "5.2" : "2.4",
8211ef78 4414 CHECK_AND_PRINT(VALID),
b481de9c
ZY
4415 CHECK_AND_PRINT(IBSS),
4416 CHECK_AND_PRINT(ACTIVE),
4417 CHECK_AND_PRINT(RADAR),
4418 CHECK_AND_PRINT(WIDE),
b481de9c
ZY
4419 CHECK_AND_PRINT(DFS),
4420 eeprom_ch_info[ch].flags,
4421 eeprom_ch_info[ch].max_power_avg,
4422 ((eeprom_ch_info[ch].
4423 flags & EEPROM_CHANNEL_IBSS)
4424 && !(eeprom_ch_info[ch].
4425 flags & EEPROM_CHANNEL_RADAR))
4426 ? "" : "not ");
4427
4428 /* Set the user_txpower_limit to the highest power
4429 * supported by any channel */
4430 if (eeprom_ch_info[ch].max_power_avg >
4431 priv->user_txpower_limit)
4432 priv->user_txpower_limit =
4433 eeprom_ch_info[ch].max_power_avg;
4434
4435 ch_info++;
4436 }
4437 }
4438
6440adb5 4439 /* Set up txpower settings in driver for all channels */
b481de9c
ZY
4440 if (iwl3945_txpower_set_from_eeprom(priv))
4441 return -EIO;
4442
4443 return 0;
4444}
4445
849e0dce
RC
4446/*
4447 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4448 */
4a8a4322 4449static void iwl3945_free_channel_map(struct iwl_priv *priv)
849e0dce
RC
4450{
4451 kfree(priv->channel_info);
4452 priv->channel_count = 0;
4453}
4454
b481de9c
ZY
4455/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4456 * sending probe req. This should be set long enough to hear probe responses
4457 * from more than one AP. */
f9340520
AK
4458#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4459#define IWL_ACTIVE_DWELL_TIME_52 (20)
4460
4461#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4462#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY
4463
4464/* For faster active scanning, scan will move to the next channel if fewer than
4465 * PLCP_QUIET_THRESH packets are heard on this channel within
4466 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4467 * time if it's a quiet channel (nothing responded to our probe, and there's
4468 * no other traffic).
4469 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4470#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4471#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY
4472
4473/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4474 * Must be set longer than active dwell time.
4475 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4476#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4477#define IWL_PASSIVE_DWELL_TIME_52 (10)
4478#define IWL_PASSIVE_DWELL_BASE (100)
4479#define IWL_CHANNEL_TUNE_TIME 5
4480
e720ce9d 4481#define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
f9340520 4482
4a8a4322 4483static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
f9340520
AK
4484 enum ieee80211_band band,
4485 u8 n_probes)
b481de9c 4486{
8318d78a 4487 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK
4488 return IWL_ACTIVE_DWELL_TIME_52 +
4489 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4490 else
f9340520
AK
4491 return IWL_ACTIVE_DWELL_TIME_24 +
4492 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY
4493}
4494
4a8a4322 4495static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
8318d78a 4496 enum ieee80211_band band)
b481de9c 4497{
8318d78a 4498 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY
4499 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4500 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4501
bb8c093b 4502 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
4503 /* If we're associated, we clamp the maximum passive
4504 * dwell time to be 98% of the beacon interval (minus
4505 * 2 * channel tune time) */
4506 passive = priv->beacon_int;
4507 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4508 passive = IWL_PASSIVE_DWELL_BASE;
4509 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4510 }
4511
b481de9c
ZY
4512 return passive;
4513}
4514
4a8a4322 4515static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 4516 enum ieee80211_band band,
f9340520 4517 u8 is_active, u8 n_probes,
bb8c093b 4518 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
4519{
4520 const struct ieee80211_channel *channels = NULL;
8318d78a 4521 const struct ieee80211_supported_band *sband;
d20b3c65 4522 const struct iwl_channel_info *ch_info;
b481de9c
ZY
4523 u16 passive_dwell = 0;
4524 u16 active_dwell = 0;
4525 int added, i;
4526
cbba18c6 4527 sband = iwl_get_hw_mode(priv, band);
8318d78a 4528 if (!sband)
b481de9c
ZY
4529 return 0;
4530
8318d78a 4531 channels = sband->channels;
b481de9c 4532
f9340520 4533 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4534 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4535
8f4807a1
AK
4536 if (passive_dwell <= active_dwell)
4537 passive_dwell = active_dwell + 1;
4538
8318d78a 4539 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB
4540 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4541 continue;
4542
8318d78a 4543 scan_ch->channel = channels[i].hw_value;
b481de9c 4544
8318d78a 4545 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4546 if (!is_channel_valid(ch_info)) {
66b5004d 4547 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY
4548 scan_ch->channel);
4549 continue;
4550 }
4551
011a0330
AK
4552 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4553 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4554 /* If passive , set up for auto-switch
4555 * and use long active_dwell time.
4556 */
b481de9c 4557 if (!is_active || is_channel_passive(ch_info) ||
011a0330 4558 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 4559 scan_ch->type = 0; /* passive */
011a0330
AK
4560 if (IWL_UCODE_API(priv->ucode_ver) == 1)
4561 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
4562 } else {
b481de9c 4563 scan_ch->type = 1; /* active */
011a0330 4564 }
b481de9c 4565
011a0330
AK
4566 /* Set direct probe bits. These may be used both for active
4567 * scan channels (probes gets sent right away),
4568 * or for passive channels (probes get se sent only after
4569 * hearing clear Rx packet).*/
4570 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
4571 if (n_probes)
4572 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4573 } else {
4574 /* uCode v1 does not allow setting direct probe bits on
4575 * passive channel. */
4576 if ((scan_ch->type & 1) && n_probes)
4577 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4578 }
b481de9c 4579
9fbab516 4580 /* Set txpower levels to defaults */
b481de9c
ZY
4581 scan_ch->tpc.dsp_atten = 110;
4582 /* scan_pwr_info->tpc.dsp_atten; */
4583
4584 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4585 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
4586 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4587 else {
4588 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4589 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4590 * power level:
8a1b0245 4591 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
4592 */
4593 }
4594
4595 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4596 scan_ch->channel,
4597 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4598 (scan_ch->type & 1) ?
4599 active_dwell : passive_dwell);
4600
4601 scan_ch++;
4602 added++;
4603 }
4604
4605 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4606 return added;
4607}
4608
4a8a4322 4609static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
4610 struct ieee80211_rate *rates)
4611{
4612 int i;
4613
4614 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
4615 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4616 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4617 rates[i].hw_value_short = i;
4618 rates[i].flags = 0;
d9829a67 4619 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4620 /*
8318d78a 4621 * If CCK != 1M then set short preamble rate flag.
b481de9c 4622 */
bb8c093b 4623 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4624 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4625 }
b481de9c
ZY
4626 }
4627}
4628
4629/**
bb8c093b 4630 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4631 */
4a8a4322 4632static int iwl3945_init_geos(struct iwl_priv *priv)
b481de9c 4633{
d20b3c65 4634 struct iwl_channel_info *ch;
8211ef78 4635 struct ieee80211_supported_band *sband;
b481de9c
ZY
4636 struct ieee80211_channel *channels;
4637 struct ieee80211_channel *geo_ch;
4638 struct ieee80211_rate *rates;
4639 int i = 0;
b481de9c 4640
8318d78a
JB
4641 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4642 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY
4643 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4644 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4645 return 0;
4646 }
4647
b481de9c
ZY
4648 channels = kzalloc(sizeof(struct ieee80211_channel) *
4649 priv->channel_count, GFP_KERNEL);
8318d78a 4650 if (!channels)
b481de9c 4651 return -ENOMEM;
b481de9c 4652
8211ef78 4653 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY
4654 GFP_KERNEL);
4655 if (!rates) {
b481de9c
ZY
4656 kfree(channels);
4657 return -ENOMEM;
4658 }
4659
b481de9c 4660 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW
4661 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4662 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4663 /* just OFDM */
4664 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4665 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4666
4667 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4668 sband->channels = channels;
4669 /* OFDM & CCK */
4670 sband->bitrates = rates;
4671 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY
4672
4673 priv->ieee_channels = channels;
4674 priv->ieee_rates = rates;
4675
bb8c093b 4676 iwl3945_init_hw_rates(priv, rates);
b481de9c 4677
8211ef78 4678 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY
4679 ch = &priv->channel_info[i];
4680
8211ef78
TW
4681 /* FIXME: might be removed if scan is OK*/
4682 if (!is_channel_valid(ch))
b481de9c 4683 continue;
b481de9c
ZY
4684
4685 if (is_channel_a_band(ch))
8211ef78 4686 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4687 else
8211ef78 4688 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4689
8211ef78
TW
4690 geo_ch = &sband->channels[sband->n_channels++];
4691
4692 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB
4693 geo_ch->max_power = ch->max_power_avg;
4694 geo_ch->max_antenna_gain = 0xff;
7b72304d 4695 geo_ch->hw_value = ch->channel;
b481de9c
ZY
4696
4697 if (is_channel_valid(ch)) {
8318d78a
JB
4698 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4699 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4700
8318d78a
JB
4701 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4702 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY
4703
4704 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4705 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY
4706
4707 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4708 priv->max_channel_txpower_limit =
4709 ch->max_power_avg;
8211ef78 4710 } else {
8318d78a 4711 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW
4712 }
4713
4714 /* Save flags for reg domain usage */
4715 geo_ch->orig_flags = geo_ch->flags;
4716
4717 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4718 ch->channel, geo_ch->center_freq,
4719 is_channel_a_band(ch) ? "5.2" : "2.4",
4720 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4721 "restricted" : "valid",
4722 geo_ch->flags);
b481de9c
ZY
4723 }
4724
82b9a121
TW
4725 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4726 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW
4727 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
4728 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
4729 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4730 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY
4731 }
4732
978785a3 4733 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB
4734 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4735 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 4736
e0e0a67e
JL
4737 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4738 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4739 &priv->bands[IEEE80211_BAND_2GHZ];
4740 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4741 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4742 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 4743
b481de9c
ZY
4744 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4745
4746 return 0;
4747}
4748
849e0dce
RC
4749/*
4750 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
4751 */
4a8a4322 4752static void iwl3945_free_geos(struct iwl_priv *priv)
849e0dce 4753{
849e0dce
RC
4754 kfree(priv->ieee_channels);
4755 kfree(priv->ieee_rates);
4756 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4757}
4758
b481de9c
ZY
4759/******************************************************************************
4760 *
4761 * uCode download functions
4762 *
4763 ******************************************************************************/
4764
4a8a4322 4765static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 4766{
98c92211
TW
4767 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
4768 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
4769 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
4770 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
4771 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
4772 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
4773}
4774
4775/**
bb8c093b 4776 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
4777 * looking at all data.
4778 */
4a8a4322 4779static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
4780{
4781 u32 val;
4782 u32 save_len = len;
4783 int rc = 0;
4784 u32 errcnt;
4785
4786 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4787
5d49f498 4788 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
4789 if (rc)
4790 return rc;
4791
5d49f498 4792 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 4793 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
4794
4795 errcnt = 0;
4796 for (; len > 0; len -= sizeof(u32), image++) {
4797 /* read data comes through single port, auto-incr addr */
4798 /* NOTE: Use the debugless read so we don't flood kernel log
4799 * if IWL_DL_IO is set */
5d49f498 4800 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 4801 if (val != le32_to_cpu(*image)) {
15b1687c 4802 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
4803 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4804 save_len - len, val, le32_to_cpu(*image));
4805 rc = -EIO;
4806 errcnt++;
4807 if (errcnt >= 20)
4808 break;
4809 }
4810 }
4811
5d49f498 4812 iwl_release_nic_access(priv);
b481de9c
ZY
4813
4814 if (!errcnt)
bc434dd2 4815 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
4816
4817 return rc;
4818}
4819
4820
4821/**
bb8c093b 4822 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
4823 * using sample data 100 bytes apart. If these sample points are good,
4824 * it's a pretty good bet that everything between them is good, too.
4825 */
4a8a4322 4826static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
4827{
4828 u32 val;
4829 int rc = 0;
4830 u32 errcnt = 0;
4831 u32 i;
4832
4833 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4834
5d49f498 4835 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
4836 if (rc)
4837 return rc;
4838
4839 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
4840 /* read data comes through single port, auto-incr addr */
4841 /* NOTE: Use the debugless read so we don't flood kernel log
4842 * if IWL_DL_IO is set */
5d49f498 4843 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 4844 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 4845 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
4846 if (val != le32_to_cpu(*image)) {
4847#if 0 /* Enable this if you want to see details */
15b1687c 4848 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
4849 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4850 i, val, *image);
4851#endif
4852 rc = -EIO;
4853 errcnt++;
4854 if (errcnt >= 3)
4855 break;
4856 }
4857 }
4858
5d49f498 4859 iwl_release_nic_access(priv);
b481de9c
ZY
4860
4861 return rc;
4862}
4863
4864
4865/**
bb8c093b 4866 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
4867 * and verify its contents
4868 */
4a8a4322 4869static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
4870{
4871 __le32 *image;
4872 u32 len;
4873 int rc = 0;
4874
4875 /* Try bootstrap */
4876 image = (__le32 *)priv->ucode_boot.v_addr;
4877 len = priv->ucode_boot.len;
bb8c093b 4878 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
4879 if (rc == 0) {
4880 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
4881 return 0;
4882 }
4883
4884 /* Try initialize */
4885 image = (__le32 *)priv->ucode_init.v_addr;
4886 len = priv->ucode_init.len;
bb8c093b 4887 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
4888 if (rc == 0) {
4889 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
4890 return 0;
4891 }
4892
4893 /* Try runtime/protocol */
4894 image = (__le32 *)priv->ucode_code.v_addr;
4895 len = priv->ucode_code.len;
bb8c093b 4896 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
4897 if (rc == 0) {
4898 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
4899 return 0;
4900 }
4901
15b1687c 4902 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 4903
9fbab516
BC
4904 /* Since nothing seems to match, show first several data entries in
4905 * instruction SRAM, so maybe visual inspection will give a clue.
4906 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
4907 image = (__le32 *)priv->ucode_boot.v_addr;
4908 len = priv->ucode_boot.len;
bb8c093b 4909 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
4910
4911 return rc;
4912}
4913
4a8a4322 4914static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
4915{
4916 /* Remove all resets to allow NIC to operate */
5d49f498 4917 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
4918}
4919
4920/**
bb8c093b 4921 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
4922 *
4923 * Copy into buffers for card to fetch via bus-mastering
4924 */
4a8a4322 4925static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 4926{
a78fe754 4927 struct iwl_ucode *ucode;
a0987a8d 4928 int ret = -EINVAL, index;
b481de9c
ZY
4929 const struct firmware *ucode_raw;
4930 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
4931 const char *name_pre = priv->cfg->fw_name_pre;
4932 const unsigned int api_max = priv->cfg->ucode_api_max;
4933 const unsigned int api_min = priv->cfg->ucode_api_min;
4934 char buf[25];
b481de9c
ZY
4935 u8 *src;
4936 size_t len;
a0987a8d 4937 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
4938
4939 /* Ask kernel firmware_class module to get the boot firmware off disk.
4940 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
4941 for (index = api_max; index >= api_min; index--) {
4942 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
4943 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
4944 if (ret < 0) {
15b1687c 4945 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
4946 buf, ret);
4947 if (ret == -ENOENT)
4948 continue;
4949 else
4950 goto error;
4951 } else {
4952 if (index < api_max)
15b1687c
WT
4953 IWL_ERR(priv, "Loaded firmware %s, "
4954 "which is deprecated. "
4955 " Please use API v%u instead.\n",
a0987a8d
RC
4956 buf, api_max);
4957 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
4958 buf, ucode_raw->size);
4959 break;
4960 }
b481de9c
ZY
4961 }
4962
a0987a8d
RC
4963 if (ret < 0)
4964 goto error;
b481de9c
ZY
4965
4966 /* Make sure that we got at least our header! */
4967 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 4968 IWL_ERR(priv, "File size way too small!\n");
90e759d1 4969 ret = -EINVAL;
b481de9c
ZY
4970 goto err_release;
4971 }
4972
4973 /* Data from ucode file: header followed by uCode images */
4974 ucode = (void *)ucode_raw->data;
4975
c02b3acd 4976 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 4977 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
4978 inst_size = le32_to_cpu(ucode->inst_size);
4979 data_size = le32_to_cpu(ucode->data_size);
4980 init_size = le32_to_cpu(ucode->init_size);
4981 init_data_size = le32_to_cpu(ucode->init_data_size);
4982 boot_size = le32_to_cpu(ucode->boot_size);
4983
a0987a8d
RC
4984 /* api_ver should match the api version forming part of the
4985 * firmware filename ... but we don't check for that and only rely
4986 * on the API version read from firware header from here on forward */
4987
4988 if (api_ver < api_min || api_ver > api_max) {
15b1687c 4989 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
4990 "Driver supports v%u, firmware is v%u.\n",
4991 api_max, api_ver);
4992 priv->ucode_ver = 0;
4993 ret = -EINVAL;
4994 goto err_release;
4995 }
4996 if (api_ver != api_max)
15b1687c 4997 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
4998 "got %u. New firmware can be obtained "
4999 "from http://www.intellinuxwireless.org.\n",
5000 api_max, api_ver);
5001
978785a3
TW
5002 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
5003 IWL_UCODE_MAJOR(priv->ucode_ver),
5004 IWL_UCODE_MINOR(priv->ucode_ver),
5005 IWL_UCODE_API(priv->ucode_ver),
5006 IWL_UCODE_SERIAL(priv->ucode_ver));
5007
a0987a8d
RC
5008 IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
5009 priv->ucode_ver);
bc434dd2
IS
5010 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5011 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5012 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5013 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5014 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c 5015
a0987a8d 5016
b481de9c
ZY
5017 /* Verify size of file vs. image size info in file's header */
5018 if (ucode_raw->size < sizeof(*ucode) +
5019 inst_size + data_size + init_size +
5020 init_data_size + boot_size) {
5021
5022 IWL_DEBUG_INFO("uCode file size %d too small\n",
5023 (int)ucode_raw->size);
90e759d1 5024 ret = -EINVAL;
b481de9c
ZY
5025 goto err_release;
5026 }
5027
5028 /* Verify that uCode images will fit in card's SRAM */
250bdd21 5029 if (inst_size > IWL39_MAX_INST_SIZE) {
90e759d1
TW
5030 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5031 inst_size);
5032 ret = -EINVAL;
b481de9c
ZY
5033 goto err_release;
5034 }
5035
250bdd21 5036 if (data_size > IWL39_MAX_DATA_SIZE) {
90e759d1
TW
5037 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5038 data_size);
5039 ret = -EINVAL;
b481de9c
ZY
5040 goto err_release;
5041 }
250bdd21 5042 if (init_size > IWL39_MAX_INST_SIZE) {
90e759d1
TW
5043 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5044 init_size);
5045 ret = -EINVAL;
b481de9c
ZY
5046 goto err_release;
5047 }
250bdd21 5048 if (init_data_size > IWL39_MAX_DATA_SIZE) {
90e759d1
TW
5049 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5050 init_data_size);
5051 ret = -EINVAL;
b481de9c
ZY
5052 goto err_release;
5053 }
250bdd21 5054 if (boot_size > IWL39_MAX_BSM_SIZE) {
90e759d1
TW
5055 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5056 boot_size);
5057 ret = -EINVAL;
b481de9c
ZY
5058 goto err_release;
5059 }
5060
5061 /* Allocate ucode buffers for card's bus-master loading ... */
5062
5063 /* Runtime instructions and 2 copies of data:
5064 * 1) unmodified from disk
5065 * 2) backup cache for save/restore during power-downs */
5066 priv->ucode_code.len = inst_size;
98c92211 5067 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
5068
5069 priv->ucode_data.len = data_size;
98c92211 5070 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
5071
5072 priv->ucode_data_backup.len = data_size;
98c92211 5073 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5074
90e759d1
TW
5075 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5076 !priv->ucode_data_backup.v_addr)
5077 goto err_pci_alloc;
b481de9c
ZY
5078
5079 /* Initialization instructions and data */
90e759d1
TW
5080 if (init_size && init_data_size) {
5081 priv->ucode_init.len = init_size;
98c92211 5082 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
5083
5084 priv->ucode_init_data.len = init_data_size;
98c92211 5085 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
5086
5087 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5088 goto err_pci_alloc;
5089 }
b481de9c
ZY
5090
5091 /* Bootstrap (instructions only, no data) */
90e759d1
TW
5092 if (boot_size) {
5093 priv->ucode_boot.len = boot_size;
98c92211 5094 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5095
90e759d1
TW
5096 if (!priv->ucode_boot.v_addr)
5097 goto err_pci_alloc;
5098 }
b481de9c
ZY
5099
5100 /* Copy images into buffers for card's bus-master reads ... */
5101
5102 /* Runtime instructions (first block of data in file) */
5103 src = &ucode->data[0];
5104 len = priv->ucode_code.len;
90e759d1 5105 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY
5106 memcpy(priv->ucode_code.v_addr, src, len);
5107 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5108 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5109
5110 /* Runtime data (2nd block)
bb8c093b 5111 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
5112 src = &ucode->data[inst_size];
5113 len = priv->ucode_data.len;
90e759d1 5114 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
5115 memcpy(priv->ucode_data.v_addr, src, len);
5116 memcpy(priv->ucode_data_backup.v_addr, src, len);
5117
5118 /* Initialization instructions (3rd block) */
5119 if (init_size) {
5120 src = &ucode->data[inst_size + data_size];
5121 len = priv->ucode_init.len;
90e759d1
TW
5122 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5123 len);
b481de9c
ZY
5124 memcpy(priv->ucode_init.v_addr, src, len);
5125 }
5126
5127 /* Initialization data (4th block) */
5128 if (init_data_size) {
5129 src = &ucode->data[inst_size + data_size + init_size];
5130 len = priv->ucode_init_data.len;
5131 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5132 (int)len);
5133 memcpy(priv->ucode_init_data.v_addr, src, len);
5134 }
5135
5136 /* Bootstrap instructions (5th block) */
5137 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5138 len = priv->ucode_boot.len;
5139 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5140 (int)len);
5141 memcpy(priv->ucode_boot.v_addr, src, len);
5142
5143 /* We have our copies now, allow OS release its copies */
5144 release_firmware(ucode_raw);
5145 return 0;
5146
5147 err_pci_alloc:
15b1687c 5148 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 5149 ret = -ENOMEM;
bb8c093b 5150 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
5151
5152 err_release:
5153 release_firmware(ucode_raw);
5154
5155 error:
90e759d1 5156 return ret;
b481de9c
ZY
5157}
5158
5159
5160/**
bb8c093b 5161 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
5162 *
5163 * Tell initialization uCode where to find runtime uCode.
5164 *
5165 * BSM registers initially contain pointers to initialization uCode.
5166 * We need to replace them to load runtime uCode inst and data,
5167 * and to save runtime data when powering down.
5168 */
4a8a4322 5169static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
5170{
5171 dma_addr_t pinst;
5172 dma_addr_t pdata;
5173 int rc = 0;
5174 unsigned long flags;
5175
5176 /* bits 31:0 for 3945 */
5177 pinst = priv->ucode_code.p_addr;
5178 pdata = priv->ucode_data_backup.p_addr;
5179
5180 spin_lock_irqsave(&priv->lock, flags);
5d49f498 5181 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
5182 if (rc) {
5183 spin_unlock_irqrestore(&priv->lock, flags);
5184 return rc;
5185 }
5186
5187 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
5188 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5189 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5190 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
5191 priv->ucode_data.len);
5192
a96a27f9 5193 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 5194 * that all new ptr/size info is in place */
5d49f498 5195 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
5196 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5197
5d49f498 5198 iwl_release_nic_access(priv);
b481de9c
ZY
5199
5200 spin_unlock_irqrestore(&priv->lock, flags);
5201
5202 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5203
5204 return rc;
5205}
5206
5207/**
bb8c093b 5208 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
5209 *
5210 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5211 *
b481de9c 5212 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5213 */
4a8a4322 5214static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
5215{
5216 /* Check alive response for "valid" sign from uCode */
5217 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5218 /* We had an error bringing up the hardware, so take it
5219 * all the way back down so we can try again */
5220 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5221 goto restart;
5222 }
5223
5224 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5225 * This is a paranoid check, because we would not have gotten the
5226 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5227 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
5228 /* Runtime instruction load was bad;
5229 * take it all the way back down so we can try again */
5230 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5231 goto restart;
5232 }
5233
5234 /* Send pointers to protocol/runtime uCode image ... init code will
5235 * load and launch runtime uCode, which will send us another "Alive"
5236 * notification. */
5237 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5238 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
5239 /* Runtime instruction load won't happen;
5240 * take it all the way back down so we can try again */
5241 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5242 goto restart;
5243 }
5244 return;
5245
5246 restart:
5247 queue_work(priv->workqueue, &priv->restart);
5248}
5249
5250
9bdf5eca
MA
5251/* temporary */
5252static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
5253 struct sk_buff *skb);
5254
b481de9c 5255/**
bb8c093b 5256 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5257 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5258 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5259 */
4a8a4322 5260static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c
ZY
5261{
5262 int rc = 0;
5263 int thermal_spin = 0;
5264 u32 rfkill;
5265
5266 IWL_DEBUG_INFO("Runtime Alive received.\n");
5267
5268 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5269 /* We had an error bringing up the hardware, so take it
5270 * all the way back down so we can try again */
5271 IWL_DEBUG_INFO("Alive failed.\n");
5272 goto restart;
5273 }
5274
5275 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5276 * This is a paranoid check, because we would not have gotten the
5277 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5278 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
5279 /* Runtime instruction load was bad;
5280 * take it all the way back down so we can try again */
5281 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5282 goto restart;
5283 }
5284
bb8c093b 5285 iwl3945_clear_stations_table(priv);
b481de9c 5286
5d49f498 5287 rc = iwl_grab_nic_access(priv);
b481de9c 5288 if (rc) {
39aadf8c 5289 IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
b481de9c
ZY
5290 return;
5291 }
5292
5d49f498 5293 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5294 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
5d49f498 5295 iwl_release_nic_access(priv);
b481de9c
ZY
5296
5297 if (rfkill & 0x1) {
5298 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 5299 /* if RFKILL is not on, then wait for thermal
b481de9c 5300 * sensor in adapter to kick in */
bb8c093b 5301 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
5302 thermal_spin++;
5303 udelay(10);
5304 }
5305
5306 if (thermal_spin)
5307 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5308 thermal_spin * 10);
5309 } else
5310 set_bit(STATUS_RF_KILL_HW, &priv->status);
5311
9fbab516 5312 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
5313 set_bit(STATUS_ALIVE, &priv->status);
5314
5315 /* Clear out the uCode error bit if it is set */
5316 clear_bit(STATUS_FW_ERROR, &priv->status);
5317
775a6e27 5318 if (iwl_is_rfkill(priv))
b481de9c
ZY
5319 return;
5320
36d6825b 5321 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
5322
5323 priv->active_rate = priv->rates_mask;
5324 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5325
bb8c093b 5326 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5327
bb8c093b
CH
5328 if (iwl3945_is_associated(priv)) {
5329 struct iwl3945_rxon_cmd *active_rxon =
f2c7e521 5330 (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
b481de9c 5331
f2c7e521
AK
5332 memcpy(&priv->staging39_rxon, &priv->active39_rxon,
5333 sizeof(priv->staging39_rxon));
b481de9c
ZY
5334 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5335 } else {
5336 /* Initialize our rx_config data */
60294de3 5337 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
f2c7e521 5338 memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
b481de9c
ZY
5339 }
5340
9fbab516 5341 /* Configure Bluetooth device coexistence support */
bb8c093b 5342 iwl3945_send_bt_config(priv);
b481de9c
ZY
5343
5344 /* Configure the adapter for unassociated operation */
bb8c093b 5345 iwl3945_commit_rxon(priv);
b481de9c 5346
b481de9c
ZY
5347 iwl3945_reg_txpower_periodic(priv);
5348
fe00b5a5
RC
5349 iwl3945_led_register(priv);
5350
b481de9c 5351 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5352 set_bit(STATUS_READY, &priv->status);
5a66926a 5353 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
5354
5355 if (priv->error_recovering)
bb8c093b 5356 iwl3945_error_recovery(priv);
b481de9c 5357
9bdf5eca
MA
5358 /* reassociate for ADHOC mode */
5359 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
5360 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
5361 priv->vif);
5362 if (beacon)
5363 iwl3945_mac_beacon_update(priv->hw, beacon);
5364 }
5365
b481de9c
ZY
5366 return;
5367
5368 restart:
5369 queue_work(priv->workqueue, &priv->restart);
5370}
5371
4a8a4322 5372static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 5373
4a8a4322 5374static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
5375{
5376 unsigned long flags;
5377 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5378 struct ieee80211_conf *conf = NULL;
5379
5380 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5381
5382 conf = ieee80211_get_hw_conf(priv->hw);
5383
5384 if (!exit_pending)
5385 set_bit(STATUS_EXIT_PENDING, &priv->status);
5386
ab53d8af 5387 iwl3945_led_unregister(priv);
bb8c093b 5388 iwl3945_clear_stations_table(priv);
b481de9c
ZY
5389
5390 /* Unblock any waiting calls */
5391 wake_up_interruptible_all(&priv->wait_command_queue);
5392
b481de9c
ZY
5393 /* Wipe out the EXIT_PENDING status bit if we are not actually
5394 * exiting the module */
5395 if (!exit_pending)
5396 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5397
5398 /* stop and reset the on-board processor */
5d49f498 5399 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
5400
5401 /* tell the device to stop sending interrupts */
0359facc 5402 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5403 iwl3945_disable_interrupts(priv);
0359facc
MA
5404 spin_unlock_irqrestore(&priv->lock, flags);
5405 iwl_synchronize_irq(priv);
b481de9c
ZY
5406
5407 if (priv->mac80211_registered)
5408 ieee80211_stop_queues(priv->hw);
5409
bb8c093b 5410 /* If we have not previously called iwl3945_init() then
b481de9c 5411 * clear all bits but the RF Kill and SUSPEND bits and return */
775a6e27 5412 if (!iwl_is_init(priv)) {
b481de9c
ZY
5413 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5414 STATUS_RF_KILL_HW |
5415 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5416 STATUS_RF_KILL_SW |
9788864e
RC
5417 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5418 STATUS_GEO_CONFIGURED |
b481de9c 5419 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK
5420 STATUS_IN_SUSPEND |
5421 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5422 STATUS_EXIT_PENDING;
b481de9c
ZY
5423 goto exit;
5424 }
5425
5426 /* ...otherwise clear out all the status bits but the RF Kill and
5427 * SUSPEND bits and continue taking the NIC down. */
5428 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5429 STATUS_RF_KILL_HW |
5430 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5431 STATUS_RF_KILL_SW |
9788864e
RC
5432 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5433 STATUS_GEO_CONFIGURED |
b481de9c
ZY
5434 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5435 STATUS_IN_SUSPEND |
5436 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
5437 STATUS_FW_ERROR |
5438 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5439 STATUS_EXIT_PENDING;
b481de9c
ZY
5440
5441 spin_lock_irqsave(&priv->lock, flags);
5d49f498 5442 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
5443 spin_unlock_irqrestore(&priv->lock, flags);
5444
bb8c093b
CH
5445 iwl3945_hw_txq_ctx_stop(priv);
5446 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY
5447
5448 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK
5449 if (!iwl_grab_nic_access(priv)) {
5450 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5451 APMG_CLK_VAL_DMA_CLK_RQT);
5d49f498 5452 iwl_release_nic_access(priv);
b481de9c
ZY
5453 }
5454 spin_unlock_irqrestore(&priv->lock, flags);
5455
5456 udelay(5);
5457
01ec616d 5458 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 5459 exit:
3d24a9f7 5460 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
5461
5462 if (priv->ibss_beacon)
5463 dev_kfree_skb(priv->ibss_beacon);
5464 priv->ibss_beacon = NULL;
5465
5466 /* clear out any free frames */
bb8c093b 5467 iwl3945_clear_free_frames(priv);
b481de9c
ZY
5468}
5469
4a8a4322 5470static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
5471{
5472 mutex_lock(&priv->mutex);
bb8c093b 5473 __iwl3945_down(priv);
b481de9c 5474 mutex_unlock(&priv->mutex);
b24d22b1 5475
bb8c093b 5476 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
5477}
5478
5479#define MAX_HW_RESTARTS 5
5480
4a8a4322 5481static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
5482{
5483 int rc, i;
5484
5485 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 5486 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
5487 return -EIO;
5488 }
5489
5490 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
39aadf8c 5491 IWL_WARN(priv, "Radio disabled by SW RF kill (module "
b481de9c 5492 "parameter)\n");
e655b9f0
ZY
5493 return -ENODEV;
5494 }
5495
e903fbd4 5496 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 5497 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
5498 return -EIO;
5499 }
5500
e655b9f0 5501 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 5502 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
5503 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5504 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5505 else {
5506 set_bit(STATUS_RF_KILL_HW, &priv->status);
5507 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
39aadf8c 5508 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
e655b9f0
ZY
5509 return -ENODEV;
5510 }
b481de9c 5511 }
80fcc9e2 5512
5d49f498 5513 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5514
bb8c093b 5515 rc = iwl3945_hw_nic_init(priv);
b481de9c 5516 if (rc) {
15b1687c 5517 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
5518 return rc;
5519 }
5520
5521 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
5522 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5523 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
5524 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5525
5526 /* clear (again), then enable host interrupts */
5d49f498 5527 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
bb8c093b 5528 iwl3945_enable_interrupts(priv);
b481de9c
ZY
5529
5530 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
5531 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5532 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
5533
5534 /* Copy original ucode data image from disk into backup cache.
5535 * This will be used to initialize the on-board processor's
5536 * data SRAM for a clean start when the runtime program first loads. */
5537 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5538 priv->ucode_data.len);
b481de9c 5539
e655b9f0
ZY
5540 /* We return success when we resume from suspend and rf_kill is on. */
5541 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5542 return 0;
5543
b481de9c
ZY
5544 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5545
bb8c093b 5546 iwl3945_clear_stations_table(priv);
b481de9c
ZY
5547
5548 /* load bootstrap state machine,
5549 * load bootstrap program into processor's memory,
5550 * prepare to load the "initialize" uCode */
0164b9b4 5551 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
5552
5553 if (rc) {
15b1687c
WT
5554 IWL_ERR(priv,
5555 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
5556 continue;
5557 }
5558
5559 /* start card; "initialize" will load runtime ucode */
bb8c093b 5560 iwl3945_nic_start(priv);
b481de9c 5561
b481de9c
ZY
5562 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5563
5564 return 0;
5565 }
5566
5567 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5568 __iwl3945_down(priv);
ebef2008 5569 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
5570
5571 /* tried to restart and config the device for as long as our
5572 * patience could withstand */
15b1687c 5573 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
5574 return -EIO;
5575}
5576
5577
5578/*****************************************************************************
5579 *
5580 * Workqueue callbacks
5581 *
5582 *****************************************************************************/
5583
bb8c093b 5584static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5585{
4a8a4322
AK
5586 struct iwl_priv *priv =
5587 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
5588
5589 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5590 return;
5591
5592 mutex_lock(&priv->mutex);
bb8c093b 5593 iwl3945_init_alive_start(priv);
b481de9c
ZY
5594 mutex_unlock(&priv->mutex);
5595}
5596
bb8c093b 5597static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5598{
4a8a4322
AK
5599 struct iwl_priv *priv =
5600 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
5601
5602 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5603 return;
5604
5605 mutex_lock(&priv->mutex);
bb8c093b 5606 iwl3945_alive_start(priv);
b481de9c
ZY
5607 mutex_unlock(&priv->mutex);
5608}
5609
bb8c093b 5610static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5611{
4a8a4322 5612 struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
b481de9c
ZY
5613
5614 wake_up_interruptible(&priv->wait_command_queue);
5615
5616 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5617 return;
5618
5619 mutex_lock(&priv->mutex);
5620
775a6e27 5621 if (!iwl_is_rfkill(priv)) {
b481de9c
ZY
5622 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
5623 "HW and/or SW RF Kill no longer active, restarting "
5624 "device\n");
5625 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
5626 queue_work(priv->workqueue, &priv->restart);
5627 } else {
5628
5629 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
5630 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
5631 "disabled by SW switch\n");
5632 else
39aadf8c 5633 IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
b481de9c
ZY
5634 "Kill switch must be turned off for "
5635 "wireless networking to work.\n");
5636 }
ebef2008 5637
b481de9c 5638 mutex_unlock(&priv->mutex);
80fcc9e2 5639 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY
5640}
5641
5642#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
5643
bb8c093b 5644static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 5645{
4a8a4322
AK
5646 struct iwl_priv *priv =
5647 container_of(data, struct iwl_priv, scan_check.work);
b481de9c
ZY
5648
5649 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5650 return;
5651
5652 mutex_lock(&priv->mutex);
5653 if (test_bit(STATUS_SCANNING, &priv->status) ||
5654 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5655 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
5656 "Scan completion watchdog resetting adapter (%dms)\n",
5657 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 5658
b481de9c 5659 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 5660 iwl3945_send_scan_abort(priv);
b481de9c
ZY
5661 }
5662 mutex_unlock(&priv->mutex);
5663}
5664
bb8c093b 5665static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 5666{
4a8a4322
AK
5667 struct iwl_priv *priv =
5668 container_of(data, struct iwl_priv, request_scan);
c2d79b48 5669 struct iwl_host_cmd cmd = {
b481de9c 5670 .id = REPLY_SCAN_CMD,
bb8c093b 5671 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
5672 .meta.flags = CMD_SIZE_HUGE,
5673 };
5674 int rc = 0;
bb8c093b 5675 struct iwl3945_scan_cmd *scan;
b481de9c 5676 struct ieee80211_conf *conf = NULL;
f9340520 5677 u8 n_probes = 2;
8318d78a 5678 enum ieee80211_band band;
9387b7ca 5679 DECLARE_SSID_BUF(ssid);
b481de9c
ZY
5680
5681 conf = ieee80211_get_hw_conf(priv->hw);
5682
5683 mutex_lock(&priv->mutex);
5684
775a6e27 5685 if (!iwl_is_ready(priv)) {
39aadf8c 5686 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
5687 goto done;
5688 }
5689
a96a27f9 5690 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
5691 * was given the chance to run... */
5692 if (!test_bit(STATUS_SCANNING, &priv->status))
5693 goto done;
5694
5695 /* This should never be called or scheduled if there is currently
5696 * a scan active in the hardware. */
5697 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
5698 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
5699 "Ignoring second request.\n");
5700 rc = -EIO;
5701 goto done;
5702 }
5703
5704 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5705 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
5706 goto done;
5707 }
5708
5709 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5710 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
5711 goto done;
5712 }
5713
775a6e27 5714 if (iwl_is_rfkill(priv)) {
b481de9c
ZY
5715 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
5716 goto done;
5717 }
5718
5719 if (!test_bit(STATUS_READY, &priv->status)) {
5720 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
5721 goto done;
5722 }
5723
5724 if (!priv->scan_bands) {
5725 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
5726 goto done;
5727 }
5728
f2c7e521
AK
5729 if (!priv->scan39) {
5730 priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 5731 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
f2c7e521 5732 if (!priv->scan39) {
b481de9c
ZY
5733 rc = -ENOMEM;
5734 goto done;
5735 }
5736 }
f2c7e521 5737 scan = priv->scan39;
bb8c093b 5738 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
5739
5740 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
5741 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
5742
bb8c093b 5743 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
5744 u16 interval = 0;
5745 u32 extra;
5746 u32 suspend_time = 100;
5747 u32 scan_suspend_time = 100;
5748 unsigned long flags;
5749
5750 IWL_DEBUG_INFO("Scanning while associated...\n");
5751
5752 spin_lock_irqsave(&priv->lock, flags);
5753 interval = priv->beacon_int;
5754 spin_unlock_irqrestore(&priv->lock, flags);
5755
5756 scan->suspend_time = 0;
15e869d8 5757 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
5758 if (!interval)
5759 interval = suspend_time;
5760 /*
5761 * suspend time format:
5762 * 0-19: beacon interval in usec (time before exec.)
5763 * 20-23: 0
5764 * 24-31: number of beacons (suspend between channels)
5765 */
5766
5767 extra = (suspend_time / interval) << 24;
5768 scan_suspend_time = 0xFF0FFFFF &
5769 (extra | ((suspend_time % interval) * 1024));
5770
5771 scan->suspend_time = cpu_to_le32(scan_suspend_time);
5772 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
5773 scan_suspend_time, interval);
5774 }
5775
5776 /* We should add the ability for user to lock to PASSIVE ONLY */
5777 if (priv->one_direct_scan) {
5778 IWL_DEBUG_SCAN
5779 ("Kicking off one direct scan for '%s'\n",
9387b7ca
JL
5780 print_ssid(ssid, priv->direct_ssid,
5781 priv->direct_ssid_len));
b481de9c
ZY
5782 scan->direct_scan[0].id = WLAN_EID_SSID;
5783 scan->direct_scan[0].len = priv->direct_ssid_len;
5784 memcpy(scan->direct_scan[0].ssid,
5785 priv->direct_ssid, priv->direct_ssid_len);
f9340520 5786 n_probes++;
f9340520 5787 } else
786b4557 5788 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY
5789
5790 /* We don't build a direct scan probe request; the uCode will do
5791 * that based on the direct_mask added to each channel entry */
5792 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 5793 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
430cfe95 5794 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
b481de9c 5795 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 5796 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
5797 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
5798
5799 /* flags + rate selection */
5800
66b5004d 5801 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
5802 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
5803 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
5804 scan->good_CRC_th = 0;
8318d78a 5805 band = IEEE80211_BAND_2GHZ;
66b5004d 5806 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY
5807 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
5808 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 5809 band = IEEE80211_BAND_5GHZ;
66b5004d 5810 } else {
39aadf8c 5811 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
5812 goto done;
5813 }
5814
5815 /* select Rx antennas */
5816 scan->flags |= iwl3945_get_antenna_flags(priv);
5817
05c914fe 5818 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY
5819 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
5820
f9340520
AK
5821 scan->channel_count =
5822 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
5823 n_probes,
5824 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 5825
14b54336
RC
5826 if (scan->channel_count == 0) {
5827 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
5828 goto done;
5829 }
5830
b481de9c 5831 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 5832 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
5833 cmd.data = scan;
5834 scan->len = cpu_to_le16(cmd.len);
5835
5836 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 5837 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
5838 if (rc)
5839 goto done;
5840
5841 queue_delayed_work(priv->workqueue, &priv->scan_check,
5842 IWL_SCAN_CHECK_WATCHDOG);
5843
5844 mutex_unlock(&priv->mutex);
5845 return;
5846
5847 done:
2420ebc1
MA
5848 /* can not perform scan make sure we clear scanning
5849 * bits from status so next scan request can be performed.
5850 * if we dont clear scanning status bit here all next scan
5851 * will fail
5852 */
5853 clear_bit(STATUS_SCAN_HW, &priv->status);
5854 clear_bit(STATUS_SCANNING, &priv->status);
5855
01ebd063 5856 /* inform mac80211 scan aborted */
b481de9c
ZY
5857 queue_work(priv->workqueue, &priv->scan_completed);
5858 mutex_unlock(&priv->mutex);
5859}
5860
bb8c093b 5861static void iwl3945_bg_up(struct work_struct *data)
b481de9c 5862{
4a8a4322 5863 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
5864
5865 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5866 return;
5867
5868 mutex_lock(&priv->mutex);
bb8c093b 5869 __iwl3945_up(priv);
b481de9c 5870 mutex_unlock(&priv->mutex);
80fcc9e2 5871 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY
5872}
5873
bb8c093b 5874static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 5875{
4a8a4322 5876 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
5877
5878 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5879 return;
5880
bb8c093b 5881 iwl3945_down(priv);
b481de9c
ZY
5882 queue_work(priv->workqueue, &priv->up);
5883}
5884
bb8c093b 5885static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 5886{
4a8a4322
AK
5887 struct iwl_priv *priv =
5888 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
5889
5890 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5891 return;
5892
5893 mutex_lock(&priv->mutex);
bb8c093b 5894 iwl3945_rx_replenish(priv);
b481de9c
ZY
5895 mutex_unlock(&priv->mutex);
5896}
5897
7878a5a4
MA
5898#define IWL_DELAY_NEXT_SCAN (HZ*2)
5899
4a8a4322 5900static void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 5901{
b481de9c
ZY
5902 int rc = 0;
5903 struct ieee80211_conf *conf = NULL;
5904
05c914fe 5905 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 5906 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
5907 return;
5908 }
5909
5910
e174961c 5911 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
f2c7e521 5912 priv->assoc_id, priv->active39_rxon.bssid_addr);
b481de9c
ZY
5913
5914 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5915 return;
5916
322a9811 5917 if (!priv->vif || !priv->is_open)
6ef89d0a 5918 return;
322a9811 5919
bb8c093b 5920 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 5921
b481de9c
ZY
5922 conf = ieee80211_get_hw_conf(priv->hw);
5923
f2c7e521 5924 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 5925 iwl3945_commit_rxon(priv);
b481de9c 5926
28afaf91 5927 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH
5928 iwl3945_setup_rxon_timing(priv);
5929 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
5930 sizeof(priv->rxon_timing), &priv->rxon_timing);
5931 if (rc)
39aadf8c 5932 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
5933 "Attempting to continue.\n");
5934
f2c7e521 5935 priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 5936
f2c7e521 5937 priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c
ZY
5938
5939 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
5940 priv->assoc_id, priv->beacon_int);
5941
5942 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
f2c7e521 5943 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 5944 else
f2c7e521 5945 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 5946
f2c7e521 5947 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 5948 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 5949 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 5950 else
f2c7e521 5951 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 5952
05c914fe 5953 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 5954 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
5955
5956 }
5957
bb8c093b 5958 iwl3945_commit_rxon(priv);
b481de9c
ZY
5959
5960 switch (priv->iw_mode) {
05c914fe 5961 case NL80211_IFTYPE_STATION:
bb8c093b 5962 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
5963 break;
5964
05c914fe 5965 case NL80211_IFTYPE_ADHOC:
b481de9c 5966
ce546fd2 5967 priv->assoc_id = 1;
bb8c093b 5968 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 5969 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 5970 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
5971 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
5972 CMD_ASYNC);
bb8c093b
CH
5973 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
5974 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
5975
5976 break;
5977
5978 default:
15b1687c 5979 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 5980 __func__, priv->iw_mode);
b481de9c
ZY
5981 break;
5982 }
5983
bb8c093b 5984 iwl3945_activate_qos(priv, 0);
292ae174 5985
7878a5a4
MA
5986 /* we have just associated, don't start scan too early */
5987 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
5988}
5989
bb8c093b 5990static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 5991{
4a8a4322 5992 struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
b481de9c 5993
775a6e27 5994 if (!iwl_is_ready(priv))
b481de9c
ZY
5995 return;
5996
5997 mutex_lock(&priv->mutex);
5998
5999 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6000 iwl3945_send_scan_abort(priv);
b481de9c
ZY
6001
6002 mutex_unlock(&priv->mutex);
6003}
6004
e8975581 6005static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6006
bb8c093b 6007static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6008{
4a8a4322
AK
6009 struct iwl_priv *priv =
6010 container_of(work, struct iwl_priv, scan_completed);
b481de9c
ZY
6011
6012 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6013
6014 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6015 return;
6016
a0646470 6017 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6018 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6019
b481de9c
ZY
6020 ieee80211_scan_completed(priv->hw);
6021
6022 /* Since setting the TXPOWER may have been deferred while
6023 * performing the scan, fire one off */
6024 mutex_lock(&priv->mutex);
bb8c093b 6025 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
6026 mutex_unlock(&priv->mutex);
6027}
6028
6029/*****************************************************************************
6030 *
6031 * mac80211 entry point functions
6032 *
6033 *****************************************************************************/
6034
5a66926a
ZY
6035#define UCODE_READY_TIMEOUT (2 * HZ)
6036
bb8c093b 6037static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6038{
4a8a4322 6039 struct iwl_priv *priv = hw->priv;
5a66926a 6040 int ret;
b481de9c
ZY
6041
6042 IWL_DEBUG_MAC80211("enter\n");
6043
5a66926a 6044 if (pci_enable_device(priv->pci_dev)) {
15b1687c 6045 IWL_ERR(priv, "Fail to pci_enable_device\n");
5a66926a
ZY
6046 return -ENODEV;
6047 }
6048 pci_restore_state(priv->pci_dev);
6049 pci_enable_msi(priv->pci_dev);
6050
6051 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6052 DRV_NAME, priv);
6053 if (ret) {
15b1687c 6054 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
5a66926a
ZY
6055 goto out_disable_msi;
6056 }
6057
b481de9c
ZY
6058 /* we should be verifying the device is ready to be opened */
6059 mutex_lock(&priv->mutex);
6060
f2c7e521 6061 memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
5a66926a
ZY
6062 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6063 * ucode filename and max sizes are card-specific. */
6064
6065 if (!priv->ucode_code.len) {
6066 ret = iwl3945_read_ucode(priv);
6067 if (ret) {
15b1687c 6068 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
6069 mutex_unlock(&priv->mutex);
6070 goto out_release_irq;
6071 }
6072 }
b481de9c 6073
e655b9f0 6074 ret = __iwl3945_up(priv);
b481de9c
ZY
6075
6076 mutex_unlock(&priv->mutex);
5a66926a 6077
80fcc9e2
AG
6078 iwl3945_rfkill_set_hw_state(priv);
6079
e655b9f0
ZY
6080 if (ret)
6081 goto out_release_irq;
6082
6083 IWL_DEBUG_INFO("Start UP work.\n");
6084
6085 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6086 return 0;
6087
5a66926a
ZY
6088 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6089 * mac80211 will not be run successfully. */
6090 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6091 test_bit(STATUS_READY, &priv->status),
6092 UCODE_READY_TIMEOUT);
6093 if (!ret) {
6094 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
6095 IWL_ERR(priv,
6096 "Wait for START_ALIVE timeout after %dms.\n",
6097 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
6098 ret = -ETIMEDOUT;
6099 goto out_release_irq;
6100 }
6101 }
6102
e655b9f0 6103 priv->is_open = 1;
b481de9c
ZY
6104 IWL_DEBUG_MAC80211("leave\n");
6105 return 0;
5a66926a
ZY
6106
6107out_release_irq:
6108 free_irq(priv->pci_dev->irq, priv);
6109out_disable_msi:
6110 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY
6111 pci_disable_device(priv->pci_dev);
6112 priv->is_open = 0;
6113 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6114 return ret;
b481de9c
ZY
6115}
6116
bb8c093b 6117static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6118{
4a8a4322 6119 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6120
6121 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6122
e655b9f0
ZY
6123 if (!priv->is_open) {
6124 IWL_DEBUG_MAC80211("leave - skip\n");
6125 return;
6126 }
6127
b481de9c 6128 priv->is_open = 0;
5a66926a 6129
775a6e27 6130 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
6131 /* stop mac, cancel any scan request and clear
6132 * RXON_FILTER_ASSOC_MSK BIT
6133 */
5a66926a
ZY
6134 mutex_lock(&priv->mutex);
6135 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6136 mutex_unlock(&priv->mutex);
fde3571f
MA
6137 }
6138
5a66926a
ZY
6139 iwl3945_down(priv);
6140
6141 flush_workqueue(priv->workqueue);
6142 free_irq(priv->pci_dev->irq, priv);
6143 pci_disable_msi(priv->pci_dev);
6144 pci_save_state(priv->pci_dev);
6145 pci_disable_device(priv->pci_dev);
6ef89d0a 6146
b481de9c 6147 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6148}
6149
e039fa4a 6150static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6151{
4a8a4322 6152 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6153
6154 IWL_DEBUG_MAC80211("enter\n");
6155
b481de9c 6156 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6157 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6158
e039fa4a 6159 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
6160 dev_kfree_skb_any(skb);
6161
6162 IWL_DEBUG_MAC80211("leave\n");
637f8837 6163 return NETDEV_TX_OK;
b481de9c
ZY
6164}
6165
bb8c093b 6166static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6167 struct ieee80211_if_init_conf *conf)
6168{
4a8a4322 6169 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6170 unsigned long flags;
6171
32bfd35d 6172 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6173
32bfd35d
JB
6174 if (priv->vif) {
6175 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6176 return -EOPNOTSUPP;
b481de9c
ZY
6177 }
6178
6179 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6180 priv->vif = conf->vif;
60294de3 6181 priv->iw_mode = conf->type;
b481de9c
ZY
6182
6183 spin_unlock_irqrestore(&priv->lock, flags);
6184
6185 mutex_lock(&priv->mutex);
864792e3
TW
6186
6187 if (conf->mac_addr) {
e174961c 6188 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW
6189 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6190 }
6191
775a6e27 6192 if (iwl_is_ready(priv))
5a66926a 6193 iwl3945_set_mode(priv, conf->type);
b481de9c 6194
b481de9c
ZY
6195 mutex_unlock(&priv->mutex);
6196
5a66926a 6197 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6198 return 0;
6199}
6200
6201/**
bb8c093b 6202 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY
6203 *
6204 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6205 * be set inappropriately and the driver currently sets the hardware up to
6206 * use it whenever needed.
6207 */
e8975581 6208static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6209{
4a8a4322 6210 struct iwl_priv *priv = hw->priv;
d20b3c65 6211 const struct iwl_channel_info *ch_info;
e8975581 6212 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6213 unsigned long flags;
76bb77e0 6214 int ret = 0;
b481de9c
ZY
6215
6216 mutex_lock(&priv->mutex);
8318d78a 6217 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6218
775a6e27 6219 if (!iwl_is_ready(priv)) {
b481de9c 6220 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY
6221 ret = -EIO;
6222 goto out;
b481de9c
ZY
6223 }
6224
df878d8f 6225 if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
b481de9c 6226 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY
6227 IWL_DEBUG_MAC80211("leave - scanning\n");
6228 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6229 mutex_unlock(&priv->mutex);
a0646470 6230 return 0;
b481de9c
ZY
6231 }
6232
6233 spin_lock_irqsave(&priv->lock, flags);
6234
8318d78a
JB
6235 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6236 conf->channel->hw_value);
b481de9c 6237 if (!is_channel_valid(ch_info)) {
66b5004d 6238 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6239 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY
6240 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6241 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY
6242 ret = -EINVAL;
6243 goto out;
b481de9c
ZY
6244 }
6245
8318d78a 6246 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6247
8318d78a 6248 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY
6249
6250 /* The list of supported rates and rate mask can be different
6251 * for each phymode; since the phymode may have changed, reset
6252 * the rate mask to what mac80211 lists */
bb8c093b 6253 iwl3945_set_rate(priv);
b481de9c
ZY
6254
6255 spin_unlock_irqrestore(&priv->lock, flags);
6256
6257#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6258 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6259 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6260 goto out;
b481de9c
ZY
6261 }
6262#endif
6263
bb8c093b 6264 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY
6265
6266 if (!conf->radio_enabled) {
6267 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6268 goto out;
b481de9c
ZY
6269 }
6270
775a6e27 6271 if (iwl_is_rfkill(priv)) {
b481de9c 6272 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY
6273 ret = -EIO;
6274 goto out;
b481de9c
ZY
6275 }
6276
bb8c093b 6277 iwl3945_set_rate(priv);
b481de9c 6278
f2c7e521
AK
6279 if (memcmp(&priv->active39_rxon,
6280 &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
bb8c093b 6281 iwl3945_commit_rxon(priv);
b481de9c
ZY
6282 else
6283 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6284
6285 IWL_DEBUG_MAC80211("leave\n");
6286
76bb77e0 6287out:
a0646470 6288 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6289 mutex_unlock(&priv->mutex);
76bb77e0 6290 return ret;
b481de9c
ZY
6291}
6292
4a8a4322 6293static void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
6294{
6295 int rc = 0;
6296
d986bcd1 6297 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
6298 return;
6299
6300 /* The following should be done only at AP bring up */
5d1e2325 6301 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY
6302
6303 /* RXON - unassoc (to set timing command) */
f2c7e521 6304 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6305 iwl3945_commit_rxon(priv);
b481de9c
ZY
6306
6307 /* RXON Timing */
28afaf91 6308 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH
6309 iwl3945_setup_rxon_timing(priv);
6310 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6311 sizeof(priv->rxon_timing), &priv->rxon_timing);
6312 if (rc)
39aadf8c 6313 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
6314 "Attempting to continue.\n");
6315
6316 /* FIXME: what should be the assoc_id for AP? */
f2c7e521 6317 priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 6318 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
f2c7e521 6319 priv->staging39_rxon.flags |=
b481de9c
ZY
6320 RXON_FLG_SHORT_PREAMBLE_MSK;
6321 else
f2c7e521 6322 priv->staging39_rxon.flags &=
b481de9c
ZY
6323 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6324
f2c7e521 6325 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
6326 if (priv->assoc_capability &
6327 WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 6328 priv->staging39_rxon.flags |=
b481de9c
ZY
6329 RXON_FLG_SHORT_SLOT_MSK;
6330 else
f2c7e521 6331 priv->staging39_rxon.flags &=
b481de9c
ZY
6332 ~RXON_FLG_SHORT_SLOT_MSK;
6333
05c914fe 6334 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 6335 priv->staging39_rxon.flags &=
b481de9c
ZY
6336 ~RXON_FLG_SHORT_SLOT_MSK;
6337 }
6338 /* restore RXON assoc */
f2c7e521 6339 priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b 6340 iwl3945_commit_rxon(priv);
b5323d36 6341 iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
556f8db7 6342 }
bb8c093b 6343 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
6344
6345 /* FIXME - we need to add code here to detect a totally new
6346 * configuration, reset the AP, unassoc, rxon timing, assoc,
6347 * clear sta table, add BCAST sta... */
6348}
6349
32bfd35d
JB
6350static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6351 struct ieee80211_vif *vif,
4a8a4322 6352 struct ieee80211_if_conf *conf)
b481de9c 6353{
4a8a4322 6354 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6355 int rc;
6356
6357 if (conf == NULL)
6358 return -EIO;
6359
b716bb91
EG
6360 if (priv->vif != vif) {
6361 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG
6362 return 0;
6363 }
6364
9d139c81 6365 /* handle this temporarily here */
05c914fe 6366 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB
6367 conf->changed & IEEE80211_IFCC_BEACON) {
6368 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6369 if (!beacon)
6370 return -ENOMEM;
9bdf5eca 6371 mutex_lock(&priv->mutex);
9d139c81 6372 rc = iwl3945_mac_beacon_update(hw, beacon);
9bdf5eca 6373 mutex_unlock(&priv->mutex);
9d139c81
JB
6374 if (rc)
6375 return rc;
6376 }
6377
775a6e27 6378 if (!iwl_is_alive(priv))
5a66926a
ZY
6379 return -EAGAIN;
6380
b481de9c
ZY
6381 mutex_lock(&priv->mutex);
6382
b481de9c 6383 if (conf->bssid)
e174961c 6384 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6385
4150c572
JB
6386/*
6387 * very dubious code was here; the probe filtering flag is never set:
6388 *
b481de9c
ZY
6389 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6390 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6391 */
b481de9c 6392
05c914fe 6393 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY
6394 if (!conf->bssid) {
6395 conf->bssid = priv->mac_addr;
6396 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB
6397 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6398 conf->bssid);
b481de9c
ZY
6399 }
6400 if (priv->ibss_beacon)
6401 dev_kfree_skb(priv->ibss_beacon);
6402
9d139c81 6403 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY
6404 }
6405
775a6e27 6406 if (iwl_is_rfkill(priv))
fde3571f
MA
6407 goto done;
6408
b481de9c
ZY
6409 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6410 !is_multicast_ether_addr(conf->bssid)) {
6411 /* If there is currently a HW scan going on in the background
6412 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6413 if (iwl3945_scan_cancel_timeout(priv, 100)) {
39aadf8c 6414 IWL_WARN(priv, "Aborted scan still in progress "
b481de9c
ZY
6415 "after 100ms\n");
6416 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6417 mutex_unlock(&priv->mutex);
6418 return -EAGAIN;
6419 }
f2c7e521 6420 memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
b481de9c
ZY
6421
6422 /* TODO: Audit driver for usage of these members and see
6423 * if mac80211 deprecates them (priv->bssid looks like it
6424 * shouldn't be there, but I haven't scanned the IBSS code
6425 * to verify) - jpk */
6426 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6427
05c914fe 6428 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6429 iwl3945_config_ap(priv);
b481de9c 6430 else {
bb8c093b 6431 rc = iwl3945_commit_rxon(priv);
05c914fe 6432 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6433 iwl3945_add_station(priv,
f2c7e521 6434 priv->active39_rxon.bssid_addr, 1, 0);
b481de9c
ZY
6435 }
6436
6437 } else {
bb8c093b 6438 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6439 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6440 iwl3945_commit_rxon(priv);
b481de9c
ZY
6441 }
6442
fde3571f 6443 done:
b481de9c
ZY
6444 IWL_DEBUG_MAC80211("leave\n");
6445 mutex_unlock(&priv->mutex);
6446
6447 return 0;
6448}
6449
bb8c093b 6450static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB
6451 unsigned int changed_flags,
6452 unsigned int *total_flags,
6453 int mc_count, struct dev_addr_list *mc_list)
6454{
4a8a4322 6455 struct iwl_priv *priv = hw->priv;
f2c7e521 6456 __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
25b3f57c 6457
352bc8de
ZY
6458 IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
6459 changed_flags, *total_flags);
6460
6461 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
6462 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
6463 *filter_flags |= RXON_FILTER_PROMISC_MSK;
6464 else
6465 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
6466 }
6467 if (changed_flags & FIF_ALLMULTI) {
6468 if (*total_flags & FIF_ALLMULTI)
6469 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
6470 else
6471 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
6472 }
6473 if (changed_flags & FIF_CONTROL) {
6474 if (*total_flags & FIF_CONTROL)
6475 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
6476 else
6477 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
5ec03976 6478 }
352bc8de
ZY
6479 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
6480 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6481 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
6482 else
6483 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
6484 }
6485
6486 /* We avoid iwl_commit_rxon here to commit the new filter flags
6487 * since mac80211 will call ieee80211_hw_config immediately.
6488 * (mc_list is not supported at this time). Otherwise, we need to
6489 * queue a background iwl_commit_rxon work.
6490 */
6491
6492 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
25b3f57c 6493 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB
6494}
6495
bb8c093b 6496static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6497 struct ieee80211_if_init_conf *conf)
6498{
4a8a4322 6499 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6500
6501 IWL_DEBUG_MAC80211("enter\n");
6502
6503 mutex_lock(&priv->mutex);
6ef89d0a 6504
775a6e27 6505 if (iwl_is_ready_rf(priv)) {
fde3571f 6506 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6507 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
fde3571f
MA
6508 iwl3945_commit_rxon(priv);
6509 }
32bfd35d
JB
6510 if (priv->vif == conf->vif) {
6511 priv->vif = NULL;
b481de9c 6512 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY
6513 }
6514 mutex_unlock(&priv->mutex);
6515
6516 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6517}
6518
cd56d331
AK
6519#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6520
6521static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6522 struct ieee80211_vif *vif,
6523 struct ieee80211_bss_conf *bss_conf,
6524 u32 changes)
6525{
4a8a4322 6526 struct iwl_priv *priv = hw->priv;
cd56d331
AK
6527
6528 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6529
6530 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6531 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6532 bss_conf->use_short_preamble);
6533 if (bss_conf->use_short_preamble)
f2c7e521 6534 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
cd56d331 6535 else
f2c7e521 6536 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
cd56d331
AK
6537 }
6538
6539 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6540 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6541 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
f2c7e521 6542 priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
cd56d331 6543 else
f2c7e521 6544 priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
cd56d331
AK
6545 }
6546
6547 if (changes & BSS_CHANGED_ASSOC) {
6548 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6549 /* This should never happen as this function should
6550 * never be called from interrupt context. */
6551 if (WARN_ON_ONCE(in_interrupt()))
6552 return;
6553 if (bss_conf->assoc) {
6554 priv->assoc_id = bss_conf->aid;
6555 priv->beacon_int = bss_conf->beacon_int;
28afaf91 6556 priv->timestamp = bss_conf->timestamp;
cd56d331
AK
6557 priv->assoc_capability = bss_conf->assoc_capability;
6558 priv->next_scan_jiffies = jiffies +
6559 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6560 mutex_lock(&priv->mutex);
6561 iwl3945_post_associate(priv);
6562 mutex_unlock(&priv->mutex);
6563 } else {
6564 priv->assoc_id = 0;
6565 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6566 }
6567 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6568 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6569 iwl3945_send_rxon_assoc(priv);
6570 }
6571
6572}
6573
bb8c093b 6574static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY
6575{
6576 int rc = 0;
6577 unsigned long flags;
4a8a4322 6578 struct iwl_priv *priv = hw->priv;
9387b7ca 6579 DECLARE_SSID_BUF(ssid_buf);
b481de9c
ZY
6580
6581 IWL_DEBUG_MAC80211("enter\n");
6582
15e869d8 6583 mutex_lock(&priv->mutex);
b481de9c
ZY
6584 spin_lock_irqsave(&priv->lock, flags);
6585
775a6e27 6586 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
6587 rc = -EIO;
6588 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6589 goto out_unlock;
6590 }
6591
7878a5a4
MA
6592 /* we don't schedule scan within next_scan_jiffies period */
6593 if (priv->next_scan_jiffies &&
6594 time_after(priv->next_scan_jiffies, jiffies)) {
6595 rc = -EAGAIN;
6596 goto out_unlock;
6597 }
15dbf1b7
BM
6598 /* if we just finished scan ask for delay for a broadcast scan */
6599 if ((len == 0) && priv->last_scan_jiffies &&
6600 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6601 jiffies)) {
b481de9c
ZY
6602 rc = -EAGAIN;
6603 goto out_unlock;
6604 }
6605 if (len) {
7878a5a4 6606 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
9387b7ca 6607 print_ssid(ssid_buf, ssid, len), (int)len);
b481de9c
ZY
6608
6609 priv->one_direct_scan = 1;
6610 priv->direct_ssid_len = (u8)
6611 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6612 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA
6613 } else
6614 priv->one_direct_scan = 0;
b481de9c 6615
bb8c093b 6616 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY
6617
6618 IWL_DEBUG_MAC80211("leave\n");
6619
6620out_unlock:
6621 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 6622 mutex_unlock(&priv->mutex);
b481de9c
ZY
6623
6624 return rc;
6625}
6626
bb8c093b 6627static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY
6628 const u8 *local_addr, const u8 *addr,
6629 struct ieee80211_key_conf *key)
6630{
4a8a4322 6631 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6632 int rc = 0;
6633 u8 sta_id;
6634
6635 IWL_DEBUG_MAC80211("enter\n");
6636
df878d8f 6637 if (iwl3945_mod_params.sw_crypto) {
b481de9c
ZY
6638 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
6639 return -EOPNOTSUPP;
6640 }
6641
6642 if (is_zero_ether_addr(addr))
6643 /* only support pairwise keys */
6644 return -EOPNOTSUPP;
6645
bb8c093b 6646 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 6647 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB
6648 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
6649 addr);
b481de9c
ZY
6650 return -EINVAL;
6651 }
6652
6653 mutex_lock(&priv->mutex);
6654
bb8c093b 6655 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 6656
b481de9c
ZY
6657 switch (cmd) {
6658 case SET_KEY:
bb8c093b 6659 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 6660 if (!rc) {
bb8c093b
CH
6661 iwl3945_set_rxon_hwcrypto(priv, 1);
6662 iwl3945_commit_rxon(priv);
b481de9c
ZY
6663 key->hw_key_idx = sta_id;
6664 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
6665 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6666 }
6667 break;
6668 case DISABLE_KEY:
bb8c093b 6669 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 6670 if (!rc) {
bb8c093b
CH
6671 iwl3945_set_rxon_hwcrypto(priv, 0);
6672 iwl3945_commit_rxon(priv);
b481de9c
ZY
6673 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
6674 }
6675 break;
6676 default:
6677 rc = -EINVAL;
6678 }
6679
6680 IWL_DEBUG_MAC80211("leave\n");
6681 mutex_unlock(&priv->mutex);
6682
6683 return rc;
6684}
6685
e100bb64 6686static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY
6687 const struct ieee80211_tx_queue_params *params)
6688{
4a8a4322 6689 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6690 unsigned long flags;
6691 int q;
b481de9c
ZY
6692
6693 IWL_DEBUG_MAC80211("enter\n");
6694
775a6e27 6695 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
6696 IWL_DEBUG_MAC80211("leave - RF not ready\n");
6697 return -EIO;
6698 }
6699
6700 if (queue >= AC_NUM) {
6701 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
6702 return 0;
6703 }
6704
b481de9c
ZY
6705 q = AC_NUM - 1 - queue;
6706
6707 spin_lock_irqsave(&priv->lock, flags);
6708
6709 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
6710 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
6711 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
6712 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 6713 cpu_to_le16((params->txop * 32));
b481de9c
ZY
6714
6715 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
6716 priv->qos_data.qos_active = 1;
6717
6718 spin_unlock_irqrestore(&priv->lock, flags);
6719
6720 mutex_lock(&priv->mutex);
05c914fe 6721 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH
6722 iwl3945_activate_qos(priv, 1);
6723 else if (priv->assoc_id && iwl3945_is_associated(priv))
6724 iwl3945_activate_qos(priv, 0);
b481de9c
ZY
6725
6726 mutex_unlock(&priv->mutex);
6727
b481de9c
ZY
6728 IWL_DEBUG_MAC80211("leave\n");
6729 return 0;
6730}
6731
bb8c093b 6732static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
6733 struct ieee80211_tx_queue_stats *stats)
6734{
4a8a4322 6735 struct iwl_priv *priv = hw->priv;
b481de9c 6736 int i, avail;
188cf6c7 6737 struct iwl_tx_queue *txq;
d20b3c65 6738 struct iwl_queue *q;
b481de9c
ZY
6739 unsigned long flags;
6740
6741 IWL_DEBUG_MAC80211("enter\n");
6742
775a6e27 6743 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
6744 IWL_DEBUG_MAC80211("leave - RF not ready\n");
6745 return -EIO;
6746 }
6747
6748 spin_lock_irqsave(&priv->lock, flags);
6749
6750 for (i = 0; i < AC_NUM; i++) {
188cf6c7 6751 txq = &priv->txq[i];
b481de9c 6752 q = &txq->q;
d20b3c65 6753 avail = iwl_queue_space(q);
b481de9c 6754
57ffc589
JB
6755 stats[i].len = q->n_window - avail;
6756 stats[i].limit = q->n_window - q->high_mark;
6757 stats[i].count = q->n_window;
b481de9c
ZY
6758
6759 }
6760 spin_unlock_irqrestore(&priv->lock, flags);
6761
6762 IWL_DEBUG_MAC80211("leave\n");
6763
6764 return 0;
6765}
6766
bb8c093b 6767static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 6768{
4a8a4322 6769 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6770 unsigned long flags;
6771
6772 mutex_lock(&priv->mutex);
6773 IWL_DEBUG_MAC80211("enter\n");
6774
775a6e27 6775 iwl_reset_qos(priv);
292ae174 6776
b481de9c
ZY
6777 spin_lock_irqsave(&priv->lock, flags);
6778 priv->assoc_id = 0;
6779 priv->assoc_capability = 0;
6780 priv->call_post_assoc_from_beacon = 0;
6781
6782 /* new association get rid of ibss beacon skb */
6783 if (priv->ibss_beacon)
6784 dev_kfree_skb(priv->ibss_beacon);
6785
6786 priv->ibss_beacon = NULL;
6787
6788 priv->beacon_int = priv->hw->conf.beacon_int;
28afaf91 6789 priv->timestamp = 0;
05c914fe 6790 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY
6791 priv->beacon_int = 0;
6792
6793 spin_unlock_irqrestore(&priv->lock, flags);
6794
775a6e27 6795 if (!iwl_is_ready_rf(priv)) {
fde3571f
MA
6796 IWL_DEBUG_MAC80211("leave - not ready\n");
6797 mutex_unlock(&priv->mutex);
6798 return;
6799 }
6800
15e869d8
MA
6801 /* we are restarting association process
6802 * clear RXON_FILTER_ASSOC_MSK bit
6803 */
05c914fe 6804 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 6805 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6806 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6807 iwl3945_commit_rxon(priv);
15e869d8
MA
6808 }
6809
b481de9c 6810 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 6811 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 6812
b481de9c
ZY
6813 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
6814 mutex_unlock(&priv->mutex);
6815 return;
b481de9c
ZY
6816 }
6817
bb8c093b 6818 iwl3945_set_rate(priv);
b481de9c
ZY
6819
6820 mutex_unlock(&priv->mutex);
6821
6822 IWL_DEBUG_MAC80211("leave\n");
6823
6824}
6825
e039fa4a 6826static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6827{
4a8a4322 6828 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6829 unsigned long flags;
6830
b481de9c
ZY
6831 IWL_DEBUG_MAC80211("enter\n");
6832
775a6e27 6833 if (!iwl_is_ready_rf(priv)) {
b481de9c 6834 IWL_DEBUG_MAC80211("leave - RF not ready\n");
b481de9c
ZY
6835 return -EIO;
6836 }
6837
05c914fe 6838 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c 6839 IWL_DEBUG_MAC80211("leave - not IBSS\n");
b481de9c
ZY
6840 return -EIO;
6841 }
6842
6843 spin_lock_irqsave(&priv->lock, flags);
6844
6845 if (priv->ibss_beacon)
6846 dev_kfree_skb(priv->ibss_beacon);
6847
6848 priv->ibss_beacon = skb;
6849
6850 priv->assoc_id = 0;
6851
6852 IWL_DEBUG_MAC80211("leave\n");
6853 spin_unlock_irqrestore(&priv->lock, flags);
6854
775a6e27 6855 iwl_reset_qos(priv);
b481de9c 6856
dc4b1e7d 6857 iwl3945_post_associate(priv);
b481de9c 6858
b481de9c
ZY
6859
6860 return 0;
6861}
6862
6863/*****************************************************************************
6864 *
6865 * sysfs attributes
6866 *
6867 *****************************************************************************/
6868
c8b0e6e1 6869#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
6870
6871/*
6872 * The following adds a new attribute to the sysfs representation
6873 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
6874 * used for controlling the debug level.
6875 *
6876 * See the level definitions in iwl for details.
6877 */
40b8ec0b
SO
6878static ssize_t show_debug_level(struct device *d,
6879 struct device_attribute *attr, char *buf)
b481de9c 6880{
4a8a4322 6881 struct iwl_priv *priv = d->driver_data;
40b8ec0b
SO
6882
6883 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 6884}
40b8ec0b
SO
6885static ssize_t store_debug_level(struct device *d,
6886 struct device_attribute *attr,
b481de9c
ZY
6887 const char *buf, size_t count)
6888{
4a8a4322 6889 struct iwl_priv *priv = d->driver_data;
40b8ec0b
SO
6890 unsigned long val;
6891 int ret;
b481de9c 6892
40b8ec0b
SO
6893 ret = strict_strtoul(buf, 0, &val);
6894 if (ret)
978785a3 6895 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 6896 else
40b8ec0b 6897 priv->debug_level = val;
b481de9c
ZY
6898
6899 return strnlen(buf, count);
6900}
6901
40b8ec0b
SO
6902static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
6903 show_debug_level, store_debug_level);
b481de9c 6904
c8b0e6e1 6905#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 6906
b481de9c
ZY
6907static ssize_t show_temperature(struct device *d,
6908 struct device_attribute *attr, char *buf)
6909{
4a8a4322 6910 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 6911
775a6e27 6912 if (!iwl_is_alive(priv))
b481de9c
ZY
6913 return -EAGAIN;
6914
bb8c093b 6915 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
6916}
6917
6918static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
6919
b481de9c
ZY
6920static ssize_t show_tx_power(struct device *d,
6921 struct device_attribute *attr, char *buf)
6922{
4a8a4322 6923 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6924 return sprintf(buf, "%d\n", priv->user_txpower_limit);
6925}
6926
6927static ssize_t store_tx_power(struct device *d,
6928 struct device_attribute *attr,
6929 const char *buf, size_t count)
6930{
4a8a4322 6931 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6932 char *p = (char *)buf;
6933 u32 val;
6934
6935 val = simple_strtoul(p, &p, 10);
6936 if (p == buf)
978785a3 6937 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 6938 else
bb8c093b 6939 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
6940
6941 return count;
6942}
6943
6944static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
6945
6946static ssize_t show_flags(struct device *d,
6947 struct device_attribute *attr, char *buf)
6948{
4a8a4322 6949 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 6950
f2c7e521 6951 return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
b481de9c
ZY
6952}
6953
6954static ssize_t store_flags(struct device *d,
6955 struct device_attribute *attr,
6956 const char *buf, size_t count)
6957{
4a8a4322 6958 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6959 u32 flags = simple_strtoul(buf, NULL, 0);
6960
6961 mutex_lock(&priv->mutex);
f2c7e521 6962 if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
b481de9c 6963 /* Cancel any currently running scans... */
bb8c093b 6964 if (iwl3945_scan_cancel_timeout(priv, 100))
39aadf8c 6965 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c
ZY
6966 else {
6967 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
6968 flags);
f2c7e521 6969 priv->staging39_rxon.flags = cpu_to_le32(flags);
bb8c093b 6970 iwl3945_commit_rxon(priv);
b481de9c
ZY
6971 }
6972 }
6973 mutex_unlock(&priv->mutex);
6974
6975 return count;
6976}
6977
6978static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
6979
6980static ssize_t show_filter_flags(struct device *d,
6981 struct device_attribute *attr, char *buf)
6982{
4a8a4322 6983 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6984
6985 return sprintf(buf, "0x%04X\n",
f2c7e521 6986 le32_to_cpu(priv->active39_rxon.filter_flags));
b481de9c
ZY
6987}
6988
6989static ssize_t store_filter_flags(struct device *d,
6990 struct device_attribute *attr,
6991 const char *buf, size_t count)
6992{
4a8a4322 6993 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6994 u32 filter_flags = simple_strtoul(buf, NULL, 0);
6995
6996 mutex_lock(&priv->mutex);
f2c7e521 6997 if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
b481de9c 6998 /* Cancel any currently running scans... */
bb8c093b 6999 if (iwl3945_scan_cancel_timeout(priv, 100))
39aadf8c 7000 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c
ZY
7001 else {
7002 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7003 "0x%04X\n", filter_flags);
f2c7e521 7004 priv->staging39_rxon.filter_flags =
b481de9c 7005 cpu_to_le32(filter_flags);
bb8c093b 7006 iwl3945_commit_rxon(priv);
b481de9c
ZY
7007 }
7008 }
7009 mutex_unlock(&priv->mutex);
7010
7011 return count;
7012}
7013
7014static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7015 store_filter_flags);
7016
c8b0e6e1 7017#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7018
7019static ssize_t show_measurement(struct device *d,
7020 struct device_attribute *attr, char *buf)
7021{
4a8a4322 7022 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 7023 struct iwl_spectrum_notification measure_report;
b481de9c 7024 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7025 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
7026 unsigned long flags;
7027
7028 spin_lock_irqsave(&priv->lock, flags);
7029 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7030 spin_unlock_irqrestore(&priv->lock, flags);
7031 return 0;
7032 }
7033 memcpy(&measure_report, &priv->measure_report, size);
7034 priv->measurement_status = 0;
7035 spin_unlock_irqrestore(&priv->lock, flags);
7036
7037 while (size && (PAGE_SIZE - len)) {
7038 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7039 PAGE_SIZE - len, 1);
7040 len = strlen(buf);
7041 if (PAGE_SIZE - len)
7042 buf[len++] = '\n';
7043
7044 ofs += 16;
7045 size -= min(size, 16U);
7046 }
7047
7048 return len;
7049}
7050
7051static ssize_t store_measurement(struct device *d,
7052 struct device_attribute *attr,
7053 const char *buf, size_t count)
7054{
4a8a4322 7055 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 7056 struct ieee80211_measurement_params params = {
f2c7e521 7057 .channel = le16_to_cpu(priv->active39_rxon.channel),
b481de9c
ZY
7058 .start_time = cpu_to_le64(priv->last_tsf),
7059 .duration = cpu_to_le16(1),
7060 };
7061 u8 type = IWL_MEASURE_BASIC;
7062 u8 buffer[32];
7063 u8 channel;
7064
7065 if (count) {
7066 char *p = buffer;
7067 strncpy(buffer, buf, min(sizeof(buffer), count));
7068 channel = simple_strtoul(p, NULL, 0);
7069 if (channel)
7070 params.channel = channel;
7071
7072 p = buffer;
7073 while (*p && *p != ' ')
7074 p++;
7075 if (*p)
7076 type = simple_strtoul(p + 1, NULL, 0);
7077 }
7078
7079 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7080 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7081 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
7082
7083 return count;
7084}
7085
7086static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7087 show_measurement, store_measurement);
c8b0e6e1 7088#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7089
b481de9c
ZY
7090static ssize_t store_retry_rate(struct device *d,
7091 struct device_attribute *attr,
7092 const char *buf, size_t count)
7093{
4a8a4322 7094 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7095
7096 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7097 if (priv->retry_rate <= 0)
7098 priv->retry_rate = 1;
7099
7100 return count;
7101}
7102
7103static ssize_t show_retry_rate(struct device *d,
7104 struct device_attribute *attr, char *buf)
7105{
4a8a4322 7106 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7107 return sprintf(buf, "%d", priv->retry_rate);
7108}
7109
7110static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7111 store_retry_rate);
7112
7113static ssize_t store_power_level(struct device *d,
7114 struct device_attribute *attr,
7115 const char *buf, size_t count)
7116{
4a8a4322 7117 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7118 int rc;
7119 int mode;
7120
7121 mode = simple_strtoul(buf, NULL, 0);
7122 mutex_lock(&priv->mutex);
7123
775a6e27 7124 if (!iwl_is_ready(priv)) {
b481de9c
ZY
7125 rc = -EAGAIN;
7126 goto out;
7127 }
7128
1125eff3
SO
7129 if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
7130 (mode == IWL39_POWER_AC))
7131 mode = IWL39_POWER_AC;
b481de9c
ZY
7132 else
7133 mode |= IWL_POWER_ENABLED;
7134
7135 if (mode != priv->power_mode) {
bb8c093b 7136 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY
7137 if (rc) {
7138 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7139 goto out;
7140 }
7141 priv->power_mode = mode;
7142 }
7143
7144 rc = count;
7145
7146 out:
7147 mutex_unlock(&priv->mutex);
7148 return rc;
7149}
7150
7151#define MAX_WX_STRING 80
7152
7153/* Values are in microsecond */
7154static const s32 timeout_duration[] = {
7155 350000,
7156 250000,
7157 75000,
7158 37000,
7159 25000,
7160};
7161static const s32 period_duration[] = {
7162 400000,
7163 700000,
7164 1000000,
7165 1000000,
7166 1000000
7167};
7168
7169static ssize_t show_power_level(struct device *d,
7170 struct device_attribute *attr, char *buf)
7171{
4a8a4322 7172 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7173 int level = IWL_POWER_LEVEL(priv->power_mode);
7174 char *p = buf;
7175
7176 p += sprintf(p, "%d ", level);
7177 switch (level) {
7178 case IWL_POWER_MODE_CAM:
1125eff3 7179 case IWL39_POWER_AC:
b481de9c
ZY
7180 p += sprintf(p, "(AC)");
7181 break;
1125eff3 7182 case IWL39_POWER_BATTERY:
b481de9c
ZY
7183 p += sprintf(p, "(BATTERY)");
7184 break;
7185 default:
7186 p += sprintf(p,
7187 "(Timeout %dms, Period %dms)",
7188 timeout_duration[level - 1] / 1000,
7189 period_duration[level - 1] / 1000);
7190 }
7191
7192 if (!(priv->power_mode & IWL_POWER_ENABLED))
7193 p += sprintf(p, " OFF\n");
7194 else
7195 p += sprintf(p, " \n");
7196
3ac7f146 7197 return p - buf + 1;
b481de9c
ZY
7198
7199}
7200
7201static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7202 store_power_level);
7203
7204static ssize_t show_channels(struct device *d,
7205 struct device_attribute *attr, char *buf)
7206{
8318d78a
JB
7207 /* all this shit doesn't belong into sysfs anyway */
7208 return 0;
b481de9c
ZY
7209}
7210
7211static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7212
7213static ssize_t show_statistics(struct device *d,
7214 struct device_attribute *attr, char *buf)
7215{
4a8a4322 7216 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 7217 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7218 u32 len = 0, ofs = 0;
f2c7e521 7219 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
7220 int rc = 0;
7221
775a6e27 7222 if (!iwl_is_alive(priv))
b481de9c
ZY
7223 return -EAGAIN;
7224
7225 mutex_lock(&priv->mutex);
bb8c093b 7226 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY
7227 mutex_unlock(&priv->mutex);
7228
7229 if (rc) {
7230 len = sprintf(buf,
7231 "Error sending statistics request: 0x%08X\n", rc);
7232 return len;
7233 }
7234
7235 while (size && (PAGE_SIZE - len)) {
7236 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7237 PAGE_SIZE - len, 1);
7238 len = strlen(buf);
7239 if (PAGE_SIZE - len)
7240 buf[len++] = '\n';
7241
7242 ofs += 16;
7243 size -= min(size, 16U);
7244 }
7245
7246 return len;
7247}
7248
7249static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7250
7251static ssize_t show_antenna(struct device *d,
7252 struct device_attribute *attr, char *buf)
7253{
4a8a4322 7254 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 7255
775a6e27 7256 if (!iwl_is_alive(priv))
b481de9c
ZY
7257 return -EAGAIN;
7258
7259 return sprintf(buf, "%d\n", priv->antenna);
7260}
7261
7262static ssize_t store_antenna(struct device *d,
7263 struct device_attribute *attr,
7264 const char *buf, size_t count)
7265{
7266 int ant;
4a8a4322 7267 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7268
7269 if (count == 0)
7270 return 0;
7271
7272 if (sscanf(buf, "%1i", &ant) != 1) {
7273 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7274 return count;
7275 }
7276
7277 if ((ant >= 0) && (ant <= 2)) {
7278 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7279 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY
7280 } else
7281 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7282
7283
7284 return count;
7285}
7286
7287static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7288
7289static ssize_t show_status(struct device *d,
7290 struct device_attribute *attr, char *buf)
7291{
4a8a4322 7292 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
775a6e27 7293 if (!iwl_is_alive(priv))
b481de9c
ZY
7294 return -EAGAIN;
7295 return sprintf(buf, "0x%08x\n", (int)priv->status);
7296}
7297
7298static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7299
7300static ssize_t dump_error_log(struct device *d,
7301 struct device_attribute *attr,
7302 const char *buf, size_t count)
7303{
7304 char *p = (char *)buf;
7305
7306 if (p[0] == '1')
4a8a4322 7307 iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY
7308
7309 return strnlen(buf, count);
7310}
7311
7312static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7313
7314static ssize_t dump_event_log(struct device *d,
7315 struct device_attribute *attr,
7316 const char *buf, size_t count)
7317{
7318 char *p = (char *)buf;
7319
7320 if (p[0] == '1')
4a8a4322 7321 iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY
7322
7323 return strnlen(buf, count);
7324}
7325
7326static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7327
7328/*****************************************************************************
7329 *
a96a27f9 7330 * driver setup and tear down
b481de9c
ZY
7331 *
7332 *****************************************************************************/
7333
4a8a4322 7334static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY
7335{
7336 priv->workqueue = create_workqueue(DRV_NAME);
7337
7338 init_waitqueue_head(&priv->wait_command_queue);
7339
bb8c093b
CH
7340 INIT_WORK(&priv->up, iwl3945_bg_up);
7341 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7342 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7343 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7344 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7345 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7346 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7347 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
7348 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7349 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7350 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7351
7352 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
7353
7354 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7355 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
7356}
7357
4a8a4322 7358static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 7359{
bb8c093b 7360 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7361
e47eb6ad 7362 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
7363 cancel_delayed_work(&priv->scan_check);
7364 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
7365 cancel_work_sync(&priv->beacon_update);
7366}
7367
bb8c093b 7368static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
7369 &dev_attr_antenna.attr,
7370 &dev_attr_channels.attr,
7371 &dev_attr_dump_errors.attr,
7372 &dev_attr_dump_events.attr,
7373 &dev_attr_flags.attr,
7374 &dev_attr_filter_flags.attr,
c8b0e6e1 7375#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7376 &dev_attr_measurement.attr,
7377#endif
7378 &dev_attr_power_level.attr,
b481de9c 7379 &dev_attr_retry_rate.attr,
b481de9c
ZY
7380 &dev_attr_statistics.attr,
7381 &dev_attr_status.attr,
7382 &dev_attr_temperature.attr,
b481de9c 7383 &dev_attr_tx_power.attr,
40b8ec0b
SO
7384#ifdef CONFIG_IWL3945_DEBUG
7385 &dev_attr_debug_level.attr,
7386#endif
b481de9c
ZY
7387 NULL
7388};
7389
bb8c093b 7390static struct attribute_group iwl3945_attribute_group = {
b481de9c 7391 .name = NULL, /* put in device directory */
bb8c093b 7392 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
7393};
7394
bb8c093b
CH
7395static struct ieee80211_ops iwl3945_hw_ops = {
7396 .tx = iwl3945_mac_tx,
7397 .start = iwl3945_mac_start,
7398 .stop = iwl3945_mac_stop,
7399 .add_interface = iwl3945_mac_add_interface,
7400 .remove_interface = iwl3945_mac_remove_interface,
7401 .config = iwl3945_mac_config,
7402 .config_interface = iwl3945_mac_config_interface,
7403 .configure_filter = iwl3945_configure_filter,
7404 .set_key = iwl3945_mac_set_key,
bb8c093b
CH
7405 .get_tx_stats = iwl3945_mac_get_tx_stats,
7406 .conf_tx = iwl3945_mac_conf_tx,
bb8c093b 7407 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7408 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7409 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY
7410};
7411
e52119c5 7412static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
7413{
7414 int ret;
7415
7416 priv->retry_rate = 1;
7417 priv->ibss_beacon = NULL;
7418
7419 spin_lock_init(&priv->lock);
7420 spin_lock_init(&priv->power_data.lock);
7421 spin_lock_init(&priv->sta_lock);
7422 spin_lock_init(&priv->hcmd_lock);
7423
7424 INIT_LIST_HEAD(&priv->free_frames);
7425
7426 mutex_init(&priv->mutex);
7427
7428 /* Clear the driver's (not device's) station table */
7429 iwl3945_clear_stations_table(priv);
7430
7431 priv->data_retry_limit = -1;
7432 priv->ieee_channels = NULL;
7433 priv->ieee_rates = NULL;
7434 priv->band = IEEE80211_BAND_2GHZ;
7435
7436 priv->iw_mode = NL80211_IFTYPE_STATION;
7437
7438 iwl_reset_qos(priv);
7439
7440 priv->qos_data.qos_active = 0;
7441 priv->qos_data.qos_cap.val = 0;
7442
7443 priv->rates_mask = IWL_RATES_MASK;
7444 /* If power management is turned on, default to AC mode */
7445 priv->power_mode = IWL_POWER_AC;
7446 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7447
7448 ret = iwl3945_init_channel_map(priv);
7449 if (ret) {
7450 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
7451 goto err;
7452 }
7453
7454 ret = iwl3945_init_geos(priv);
7455 if (ret) {
7456 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
7457 goto err_free_channel_map;
7458 }
7459
7460 return 0;
7461
7462err_free_channel_map:
7463 iwl3945_free_channel_map(priv);
7464err:
7465 return ret;
7466}
7467
bb8c093b 7468static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
7469{
7470 int err = 0;
4a8a4322 7471 struct iwl_priv *priv;
b481de9c 7472 struct ieee80211_hw *hw;
c0f20d91 7473 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 7474 unsigned long flags;
b481de9c 7475
cee53ddb
KA
7476 /***********************
7477 * 1. Allocating HW data
7478 * ********************/
7479
b481de9c
ZY
7480 /* mac80211 allocates memory for this device instance, including
7481 * space for this driver's private structure */
90a30a02 7482 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 7483 if (hw == NULL) {
a3139c59 7484 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
7485 err = -ENOMEM;
7486 goto out;
7487 }
b481de9c 7488 priv = hw->priv;
90a30a02 7489 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 7490
df878d8f
KA
7491 if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
7492 (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT
7493 IWL_ERR(priv,
7494 "invalid queues_num, should be between %d and %d\n",
7495 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
a3139c59
SO
7496 err = -EINVAL;
7497 goto out;
7498 }
7499
90a30a02
KA
7500 /*
7501 * Disabling hardware scan means that mac80211 will perform scans
7502 * "the hard way", rather than using device's scan.
7503 */
df878d8f 7504 if (iwl3945_mod_params.disable_hw_scan) {
40b8ec0b
SO
7505 IWL_DEBUG_INFO("Disabling hw_scan\n");
7506 iwl3945_hw_ops.hw_scan = NULL;
7507 }
7508
90a30a02 7509
cee53ddb 7510 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
90a30a02
KA
7511 priv->cfg = cfg;
7512 priv->pci_dev = pdev;
cee53ddb 7513
c8b0e6e1 7514#ifdef CONFIG_IWL3945_DEBUG
df878d8f 7515 priv->debug_level = iwl3945_mod_params.debug;
b481de9c
ZY
7516 atomic_set(&priv->restrict_refcnt, 0);
7517#endif
90a30a02
KA
7518 hw->rate_control_algorithm = "iwl-3945-rs";
7519 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
7520
7521 /* Select antenna (may be helpful if only one antenna is connected) */
7522 priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
b481de9c 7523
566bfe5a 7524 /* Tell mac80211 our characteristics */
605a0bd6 7525 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7526 IEEE80211_HW_NOISE_DBM;
b481de9c 7527
f59ac048 7528 hw->wiphy->interface_modes =
f59ac048
LR
7529 BIT(NL80211_IFTYPE_STATION) |
7530 BIT(NL80211_IFTYPE_ADHOC);
7531
ea4a82dc
LR
7532 hw->wiphy->fw_handles_regulatory = true;
7533
6440adb5 7534 /* 4 EDCA QOS priorities */
b481de9c
ZY
7535 hw->queues = 4;
7536
cee53ddb
KA
7537 /***************************
7538 * 2. Initializing PCI bus
7539 * *************************/
b481de9c
ZY
7540 if (pci_enable_device(pdev)) {
7541 err = -ENODEV;
7542 goto out_ieee80211_free_hw;
7543 }
7544
7545 pci_set_master(pdev);
7546
b481de9c
ZY
7547 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7548 if (!err)
7549 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7550 if (err) {
978785a3 7551 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
7552 goto out_pci_disable_device;
7553 }
7554
7555 pci_set_drvdata(pdev, priv);
7556 err = pci_request_regions(pdev, DRV_NAME);
7557 if (err)
7558 goto out_pci_disable_device;
6440adb5 7559
cee53ddb
KA
7560 /***********************
7561 * 3. Read REV Register
7562 * ********************/
b481de9c
ZY
7563 priv->hw_base = pci_iomap(pdev, 0, 0);
7564 if (!priv->hw_base) {
7565 err = -ENODEV;
7566 goto out_pci_release_regions;
7567 }
7568
7569 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7570 (unsigned long long) pci_resource_len(pdev, 0));
7571 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7572
cee53ddb
KA
7573 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7574 * PCI Tx retries from interfering with C3 CPU state */
7575 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 7576
90a30a02
KA
7577 /* amp init */
7578 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 7579 if (err < 0) {
90a30a02
KA
7580 IWL_DEBUG_INFO("Failed to init APMG\n");
7581 goto out_iounmap;
cee53ddb 7582 }
b481de9c 7583
cee53ddb
KA
7584 /***********************
7585 * 4. Read EEPROM
7586 * ********************/
90a30a02 7587
cee53ddb
KA
7588 /* Read the EEPROM */
7589 err = iwl3945_eeprom_init(priv);
7590 if (err) {
15b1687c 7591 IWL_ERR(priv, "Unable to init EEPROM\n");
cee53ddb
KA
7592 goto out_remove_sysfs;
7593 }
7594 /* MAC Address location in EEPROM same for 3945/4965 */
7595 get_eeprom_mac(priv, priv->mac_addr);
7596 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
7597 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7598
cee53ddb
KA
7599 /***********************
7600 * 5. Setup HW Constants
7601 * ********************/
b481de9c 7602 /* Device-specific setup */
3832ec9d 7603 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 7604 IWL_ERR(priv, "failed to set hw settings\n");
b481de9c
ZY
7605 goto out_iounmap;
7606 }
7607
cee53ddb
KA
7608 /***********************
7609 * 6. Setup priv
7610 * ********************/
cee53ddb 7611
90a30a02 7612 err = iwl3945_init_drv(priv);
b481de9c 7613 if (err) {
90a30a02
KA
7614 IWL_ERR(priv, "initializing driver failed\n");
7615 goto out_free_geos;
b481de9c
ZY
7616 }
7617
978785a3
TW
7618 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
7619 priv->cfg->name);
cee53ddb
KA
7620
7621 /***********************************
7622 * 7. Initialize Module Parameters
7623 * **********************************/
7624
7625 /* Initialize module parameter values here */
7626 /* Disable radio (SW RF KILL) via parameter when loading driver */
df878d8f 7627 if (iwl3945_mod_params.disable) {
cee53ddb
KA
7628 set_bit(STATUS_RF_KILL_SW, &priv->status);
7629 IWL_DEBUG_INFO("Radio disabled.\n");
849e0dce
RC
7630 }
7631
cee53ddb
KA
7632
7633 /***********************
7634 * 8. Setup Services
7635 * ********************/
7636
7637 spin_lock_irqsave(&priv->lock, flags);
7638 iwl3945_disable_interrupts(priv);
7639 spin_unlock_irqrestore(&priv->lock, flags);
7640
7641 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 7642 if (err) {
15b1687c 7643 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 7644 goto out_release_irq;
849e0dce 7645 }
849e0dce 7646
cee53ddb
KA
7647 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
7648 iwl3945_setup_deferred_work(priv);
7649 iwl3945_setup_rx_handlers(priv);
7650
7651 /***********************
7652 * 9. Conclude
7653 * ********************/
7654 pci_save_state(pdev);
7655 pci_disable_device(pdev);
7656
7657 /*********************************
7658 * 10. Setup and Register mac80211
7659 * *******************************/
7660
5a66926a
ZY
7661 err = ieee80211_register_hw(priv->hw);
7662 if (err) {
15b1687c 7663 IWL_ERR(priv, "Failed to register network device: %d\n", err);
cee53ddb 7664 goto out_remove_sysfs;
5a66926a 7665 }
b481de9c 7666
5a66926a
ZY
7667 priv->hw->conf.beacon_int = 100;
7668 priv->mac80211_registered = 1;
cee53ddb 7669
ebef2008
AK
7670 err = iwl3945_rfkill_init(priv);
7671 if (err)
15b1687c 7672 IWL_ERR(priv, "Unable to initialize RFKILL system. "
ebef2008
AK
7673 "Ignoring error: %d\n", err);
7674
b481de9c
ZY
7675 return 0;
7676
cee53ddb
KA
7677 out_remove_sysfs:
7678 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce
RC
7679 out_free_geos:
7680 iwl3945_free_geos(priv);
b481de9c
ZY
7681
7682 out_release_irq:
b481de9c
ZY
7683 destroy_workqueue(priv->workqueue);
7684 priv->workqueue = NULL;
3832ec9d 7685 iwl3945_unset_hw_params(priv);
b481de9c
ZY
7686
7687 out_iounmap:
7688 pci_iounmap(pdev, priv->hw_base);
7689 out_pci_release_regions:
7690 pci_release_regions(pdev);
7691 out_pci_disable_device:
7692 pci_disable_device(pdev);
7693 pci_set_drvdata(pdev, NULL);
7694 out_ieee80211_free_hw:
7695 ieee80211_free_hw(priv->hw);
7696 out:
7697 return err;
7698}
7699
c83dbf68 7700static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 7701{
4a8a4322 7702 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 7703 unsigned long flags;
b481de9c
ZY
7704
7705 if (!priv)
7706 return;
7707
7708 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
7709
b481de9c 7710 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 7711
d552bfb6
KA
7712 if (priv->mac80211_registered) {
7713 ieee80211_unregister_hw(priv->hw);
7714 priv->mac80211_registered = 0;
7715 } else {
7716 iwl3945_down(priv);
7717 }
b481de9c 7718
0359facc
MA
7719 /* make sure we flush any pending irq or
7720 * tasklet for the driver
7721 */
7722 spin_lock_irqsave(&priv->lock, flags);
7723 iwl3945_disable_interrupts(priv);
7724 spin_unlock_irqrestore(&priv->lock, flags);
7725
7726 iwl_synchronize_irq(priv);
7727
bb8c093b 7728 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 7729
ebef2008 7730 iwl3945_rfkill_unregister(priv);
bb8c093b 7731 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
7732
7733 if (priv->rxq.bd)
bb8c093b
CH
7734 iwl3945_rx_queue_free(priv, &priv->rxq);
7735 iwl3945_hw_txq_ctx_free(priv);
b481de9c 7736
3832ec9d 7737 iwl3945_unset_hw_params(priv);
bb8c093b 7738 iwl3945_clear_stations_table(priv);
b481de9c 7739
6ef89d0a
MA
7740 /*netif_stop_queue(dev); */
7741 flush_workqueue(priv->workqueue);
7742
bb8c093b 7743 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
7744 * priv->workqueue... so we can't take down the workqueue
7745 * until now... */
7746 destroy_workqueue(priv->workqueue);
7747 priv->workqueue = NULL;
7748
b481de9c
ZY
7749 pci_iounmap(pdev, priv->hw_base);
7750 pci_release_regions(pdev);
7751 pci_disable_device(pdev);
7752 pci_set_drvdata(pdev, NULL);
7753
849e0dce
RC
7754 iwl3945_free_channel_map(priv);
7755 iwl3945_free_geos(priv);
f2c7e521 7756 kfree(priv->scan39);
b481de9c
ZY
7757 if (priv->ibss_beacon)
7758 dev_kfree_skb(priv->ibss_beacon);
7759
7760 ieee80211_free_hw(priv->hw);
7761}
7762
7763#ifdef CONFIG_PM
7764
bb8c093b 7765static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 7766{
4a8a4322 7767 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 7768
e655b9f0
ZY
7769 if (priv->is_open) {
7770 set_bit(STATUS_IN_SUSPEND, &priv->status);
7771 iwl3945_mac_stop(priv->hw);
7772 priv->is_open = 1;
7773 }
b481de9c 7774
b481de9c
ZY
7775 pci_set_power_state(pdev, PCI_D3hot);
7776
b481de9c
ZY
7777 return 0;
7778}
7779
bb8c093b 7780static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 7781{
4a8a4322 7782 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 7783
b481de9c 7784 pci_set_power_state(pdev, PCI_D0);
b481de9c 7785
e655b9f0
ZY
7786 if (priv->is_open)
7787 iwl3945_mac_start(priv->hw);
b481de9c 7788
e655b9f0 7789 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY
7790 return 0;
7791}
7792
7793#endif /* CONFIG_PM */
7794
ebef2008 7795/*************** RFKILL FUNCTIONS **********/
80fcc9e2 7796#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK
7797/* software rf-kill from user */
7798static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
7799{
4a8a4322 7800 struct iwl_priv *priv = data;
ebef2008
AK
7801 int err = 0;
7802
80fcc9e2 7803 if (!priv->rfkill)
ebef2008
AK
7804 return 0;
7805
7806 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7807 return 0;
7808
a96a27f9 7809 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
ebef2008
AK
7810 mutex_lock(&priv->mutex);
7811
7812 switch (state) {
acdfe9b4 7813 case RFKILL_STATE_UNBLOCKED:
775a6e27 7814 if (iwl_is_rfkill_hw(priv)) {
ebef2008 7815 err = -EBUSY;
80fcc9e2
AG
7816 goto out_unlock;
7817 }
7818 iwl3945_radio_kill_sw(priv, 0);
ebef2008 7819 break;
acdfe9b4 7820 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 7821 iwl3945_radio_kill_sw(priv, 1);
ebef2008 7822 break;
acdfe9b4 7823 default:
39aadf8c 7824 IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
acdfe9b4 7825 break;
ebef2008 7826 }
80fcc9e2 7827out_unlock:
ebef2008
AK
7828 mutex_unlock(&priv->mutex);
7829
7830 return err;
7831}
7832
4a8a4322 7833int iwl3945_rfkill_init(struct iwl_priv *priv)
ebef2008
AK
7834{
7835 struct device *device = wiphy_dev(priv->hw->wiphy);
7836 int ret = 0;
7837
7838 BUG_ON(device == NULL);
7839
7840 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG
7841 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
7842 if (!priv->rfkill) {
15b1687c 7843 IWL_ERR(priv, "Unable to allocate rfkill device.\n");
ebef2008
AK
7844 ret = -ENOMEM;
7845 goto error;
7846 }
7847
80fcc9e2
AG
7848 priv->rfkill->name = priv->cfg->name;
7849 priv->rfkill->data = priv;
7850 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
7851 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
7852 priv->rfkill->user_claim_unsupported = 1;
ebef2008 7853
80fcc9e2
AG
7854 priv->rfkill->dev.class->suspend = NULL;
7855 priv->rfkill->dev.class->resume = NULL;
ebef2008 7856
80fcc9e2 7857 ret = rfkill_register(priv->rfkill);
ebef2008 7858 if (ret) {
15b1687c 7859 IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
80fcc9e2 7860 goto freed_rfkill;
ebef2008
AK
7861 }
7862
7863 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
7864 return ret;
7865
ebef2008 7866freed_rfkill:
80fcc9e2
AG
7867 if (priv->rfkill != NULL)
7868 rfkill_free(priv->rfkill);
7869 priv->rfkill = NULL;
ebef2008
AK
7870
7871error:
7872 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
7873 return ret;
7874}
7875
4a8a4322 7876void iwl3945_rfkill_unregister(struct iwl_priv *priv)
ebef2008 7877{
80fcc9e2
AG
7878 if (priv->rfkill)
7879 rfkill_unregister(priv->rfkill);
ebef2008 7880
80fcc9e2 7881 priv->rfkill = NULL;
ebef2008
AK
7882}
7883
7884/* set rf-kill to the right state. */
4a8a4322 7885void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
ebef2008
AK
7886{
7887
80fcc9e2
AG
7888 if (!priv->rfkill)
7889 return;
7890
775a6e27 7891 if (iwl_is_rfkill_hw(priv)) {
80fcc9e2 7892 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 7893 return;
80fcc9e2 7894 }
ebef2008 7895
775a6e27 7896 if (!iwl_is_rfkill_sw(priv))
80fcc9e2 7897 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 7898 else
80fcc9e2 7899 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK
7900}
7901#endif
7902
b481de9c
ZY
7903/*****************************************************************************
7904 *
7905 * driver and module entry point
7906 *
7907 *****************************************************************************/
7908
bb8c093b 7909static struct pci_driver iwl3945_driver = {
b481de9c 7910 .name = DRV_NAME,
bb8c093b
CH
7911 .id_table = iwl3945_hw_card_ids,
7912 .probe = iwl3945_pci_probe,
7913 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 7914#ifdef CONFIG_PM
bb8c093b
CH
7915 .suspend = iwl3945_pci_suspend,
7916 .resume = iwl3945_pci_resume,
b481de9c
ZY
7917#endif
7918};
7919
bb8c093b 7920static int __init iwl3945_init(void)
b481de9c
ZY
7921{
7922
7923 int ret;
7924 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
7925 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
7926
7927 ret = iwl3945_rate_control_register();
7928 if (ret) {
a3139c59
SO
7929 printk(KERN_ERR DRV_NAME
7930 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
7931 return ret;
7932 }
7933
bb8c093b 7934 ret = pci_register_driver(&iwl3945_driver);
b481de9c 7935 if (ret) {
a3139c59 7936 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 7937 goto error_register;
b481de9c 7938 }
b481de9c
ZY
7939
7940 return ret;
897e1cf2 7941
897e1cf2
RC
7942error_register:
7943 iwl3945_rate_control_unregister();
7944 return ret;
b481de9c
ZY
7945}
7946
bb8c093b 7947static void __exit iwl3945_exit(void)
b481de9c 7948{
bb8c093b 7949 pci_unregister_driver(&iwl3945_driver);
897e1cf2 7950 iwl3945_rate_control_unregister();
b481de9c
ZY
7951}
7952
a0987a8d 7953MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 7954
df878d8f 7955module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 7956MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
df878d8f 7957module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
b481de9c 7958MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
df878d8f 7959module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
b481de9c
ZY
7960MODULE_PARM_DESC(hwcrypto,
7961 "using hardware crypto engine (default 0 [software])\n");
df878d8f 7962module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
b481de9c 7963MODULE_PARM_DESC(debug, "debug output mask");
df878d8f 7964module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c
ZY
7965MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
7966
df878d8f 7967module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
b481de9c
ZY
7968MODULE_PARM_DESC(queues_num, "number of hw queues.");
7969
bb8c093b
CH
7970module_exit(iwl3945_exit);
7971module_init(iwl3945_init);