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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/version.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
b481de9c ZY |
44 | #include <net/mac80211.h> |
45 | ||
46 | #include <asm/div64.h> | |
47 | ||
6bc913bd | 48 | #include "iwl-eeprom.h" |
b481de9c | 49 | #include "iwl-4965.h" |
fee1247a | 50 | #include "iwl-core.h" |
3395f6e9 | 51 | #include "iwl-io.h" |
b481de9c ZY |
52 | #include "iwl-helpers.h" |
53 | ||
c79dd5b5 | 54 | static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 55 | struct iwl4965_tx_queue *txq); |
416e1438 | 56 | |
b481de9c ZY |
57 | /****************************************************************************** |
58 | * | |
59 | * module boiler plate | |
60 | * | |
61 | ******************************************************************************/ | |
62 | ||
b481de9c ZY |
63 | /* |
64 | * module name, copyright, version, etc. | |
65 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | |
66 | */ | |
67 | ||
68 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux" | |
69 | ||
0a6857e7 | 70 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
71 | #define VD "d" |
72 | #else | |
73 | #define VD | |
74 | #endif | |
75 | ||
c8b0e6e1 | 76 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
77 | #define VS "s" |
78 | #else | |
79 | #define VS | |
80 | #endif | |
81 | ||
df48c323 | 82 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 83 | |
b481de9c ZY |
84 | |
85 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
86 | MODULE_VERSION(DRV_VERSION); | |
87 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
88 | MODULE_LICENSE("GPL"); | |
89 | ||
90 | __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr) | |
91 | { | |
92 | u16 fc = le16_to_cpu(hdr->frame_control); | |
93 | int hdr_len = ieee80211_get_hdrlen(fc); | |
94 | ||
95 | if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA)) | |
96 | return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN); | |
97 | return NULL; | |
98 | } | |
99 | ||
8318d78a | 100 | static const struct ieee80211_supported_band *iwl4965_get_hw_mode( |
c79dd5b5 | 101 | struct iwl_priv *priv, enum ieee80211_band band) |
b481de9c | 102 | { |
8318d78a | 103 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
104 | } |
105 | ||
bb8c093b | 106 | static int iwl4965_is_empty_essid(const char *essid, int essid_len) |
b481de9c ZY |
107 | { |
108 | /* Single white space is for Linksys APs */ | |
109 | if (essid_len == 1 && essid[0] == ' ') | |
110 | return 1; | |
111 | ||
112 | /* Otherwise, if the entire essid is 0, we assume it is hidden */ | |
113 | while (essid_len) { | |
114 | essid_len--; | |
115 | if (essid[essid_len] != '\0') | |
116 | return 0; | |
117 | } | |
118 | ||
119 | return 1; | |
120 | } | |
121 | ||
bb8c093b | 122 | static const char *iwl4965_escape_essid(const char *essid, u8 essid_len) |
b481de9c ZY |
123 | { |
124 | static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; | |
125 | const char *s = essid; | |
126 | char *d = escaped; | |
127 | ||
bb8c093b | 128 | if (iwl4965_is_empty_essid(essid, essid_len)) { |
b481de9c ZY |
129 | memcpy(escaped, "<hidden>", sizeof("<hidden>")); |
130 | return escaped; | |
131 | } | |
132 | ||
133 | essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE); | |
134 | while (essid_len--) { | |
135 | if (*s == '\0') { | |
136 | *d++ = '\\'; | |
137 | *d++ = '0'; | |
138 | s++; | |
139 | } else | |
140 | *d++ = *s++; | |
141 | } | |
142 | *d = '\0'; | |
143 | return escaped; | |
144 | } | |
145 | ||
b481de9c ZY |
146 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
147 | * DMA services | |
148 | * | |
149 | * Theory of operation | |
150 | * | |
6440adb5 BC |
151 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
152 | * of buffer descriptors, each of which points to one or more data buffers for | |
153 | * the device to read from or fill. Driver and device exchange status of each | |
154 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
155 | * entries in each circular buffer, to protect against confusing empty and full | |
156 | * queue states. | |
157 | * | |
158 | * The device reads or writes the data in the queues via the device's several | |
159 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
160 | * |
161 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
162 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
163 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
164 | * Tx queue resumed. | |
165 | * | |
6440adb5 BC |
166 | * The 4965 operates with up to 17 queues: One receive queue, one transmit |
167 | * queue (#4) for sending commands to the device firmware, and 15 other | |
168 | * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels. | |
e3851447 BC |
169 | * |
170 | * See more detailed info in iwl-4965-hw.h. | |
b481de9c ZY |
171 | ***************************************************/ |
172 | ||
fe01b477 | 173 | int iwl4965_queue_space(const struct iwl4965_queue *q) |
b481de9c | 174 | { |
fc4b6853 | 175 | int s = q->read_ptr - q->write_ptr; |
b481de9c | 176 | |
fc4b6853 | 177 | if (q->read_ptr > q->write_ptr) |
b481de9c ZY |
178 | s -= q->n_bd; |
179 | ||
180 | if (s <= 0) | |
181 | s += q->n_window; | |
182 | /* keep some reserve to not confuse empty and full situations */ | |
183 | s -= 2; | |
184 | if (s < 0) | |
185 | s = 0; | |
186 | return s; | |
187 | } | |
188 | ||
b481de9c | 189 | |
bb8c093b | 190 | static inline int x2_queue_used(const struct iwl4965_queue *q, int i) |
b481de9c | 191 | { |
fc4b6853 TW |
192 | return q->write_ptr > q->read_ptr ? |
193 | (i >= q->read_ptr && i < q->write_ptr) : | |
194 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
195 | } |
196 | ||
bb8c093b | 197 | static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge) |
b481de9c | 198 | { |
6440adb5 | 199 | /* This is for scan command, the big buffer at end of command array */ |
b481de9c | 200 | if (is_huge) |
6440adb5 | 201 | return q->n_window; /* must be power of 2 */ |
b481de9c | 202 | |
6440adb5 | 203 | /* Otherwise, use normal size buffers */ |
b481de9c ZY |
204 | return index & (q->n_window - 1); |
205 | } | |
206 | ||
6440adb5 BC |
207 | /** |
208 | * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes | |
209 | */ | |
c79dd5b5 | 210 | static int iwl4965_queue_init(struct iwl_priv *priv, struct iwl4965_queue *q, |
b481de9c ZY |
211 | int count, int slots_num, u32 id) |
212 | { | |
213 | q->n_bd = count; | |
214 | q->n_window = slots_num; | |
215 | q->id = id; | |
216 | ||
c54b679d TW |
217 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
218 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
219 | BUG_ON(!is_power_of_2(count)); |
220 | ||
221 | /* slots_num must be power-of-two size, otherwise | |
222 | * get_cmd_index is broken. */ | |
223 | BUG_ON(!is_power_of_2(slots_num)); | |
224 | ||
225 | q->low_mark = q->n_window / 4; | |
226 | if (q->low_mark < 4) | |
227 | q->low_mark = 4; | |
228 | ||
229 | q->high_mark = q->n_window / 8; | |
230 | if (q->high_mark < 2) | |
231 | q->high_mark = 2; | |
232 | ||
fc4b6853 | 233 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
234 | |
235 | return 0; | |
236 | } | |
237 | ||
6440adb5 BC |
238 | /** |
239 | * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
240 | */ | |
c79dd5b5 | 241 | static int iwl4965_tx_queue_alloc(struct iwl_priv *priv, |
bb8c093b | 242 | struct iwl4965_tx_queue *txq, u32 id) |
b481de9c ZY |
243 | { |
244 | struct pci_dev *dev = priv->pci_dev; | |
245 | ||
6440adb5 BC |
246 | /* Driver private data, only for Tx (not command) queues, |
247 | * not shared with device. */ | |
b481de9c ZY |
248 | if (id != IWL_CMD_QUEUE_NUM) { |
249 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
250 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
251 | if (!txq->txb) { | |
01ebd063 | 252 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
253 | "structures failed\n"); |
254 | goto error; | |
255 | } | |
256 | } else | |
257 | txq->txb = NULL; | |
258 | ||
6440adb5 BC |
259 | /* Circular buffer of transmit frame descriptors (TFDs), |
260 | * shared with device */ | |
b481de9c ZY |
261 | txq->bd = pci_alloc_consistent(dev, |
262 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
263 | &txq->q.dma_addr); | |
264 | ||
265 | if (!txq->bd) { | |
266 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
267 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
268 | goto error; | |
269 | } | |
270 | txq->q.id = id; | |
271 | ||
272 | return 0; | |
273 | ||
274 | error: | |
275 | if (txq->txb) { | |
276 | kfree(txq->txb); | |
277 | txq->txb = NULL; | |
278 | } | |
279 | ||
280 | return -ENOMEM; | |
281 | } | |
282 | ||
8b6eaea8 BC |
283 | /** |
284 | * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue | |
285 | */ | |
c79dd5b5 | 286 | int iwl4965_tx_queue_init(struct iwl_priv *priv, |
bb8c093b | 287 | struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id) |
b481de9c ZY |
288 | { |
289 | struct pci_dev *dev = priv->pci_dev; | |
290 | int len; | |
291 | int rc = 0; | |
292 | ||
8b6eaea8 BC |
293 | /* |
294 | * Alloc buffer array for commands (Tx or other types of commands). | |
295 | * For the command queue (#4), allocate command space + one big | |
296 | * command for scan, since scan command is very huge; the system will | |
297 | * not have two scans at the same time, so only one is needed. | |
bb54244b | 298 | * For normal Tx queues (all other queues), no super-size command |
8b6eaea8 BC |
299 | * space is needed. |
300 | */ | |
857485c0 | 301 | len = sizeof(struct iwl_cmd) * slots_num; |
b481de9c ZY |
302 | if (txq_id == IWL_CMD_QUEUE_NUM) |
303 | len += IWL_MAX_SCAN_SIZE; | |
304 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
305 | if (!txq->cmd) | |
306 | return -ENOMEM; | |
307 | ||
8b6eaea8 | 308 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 309 | rc = iwl4965_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
310 | if (rc) { |
311 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
312 | ||
313 | return -ENOMEM; | |
314 | } | |
315 | txq->need_update = 0; | |
316 | ||
317 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 318 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 319 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
8b6eaea8 BC |
320 | |
321 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
bb8c093b | 322 | iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 323 | |
8b6eaea8 | 324 | /* Tell device where to find queue */ |
bb8c093b | 325 | iwl4965_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
330 | /** | |
bb8c093b | 331 | * iwl4965_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
332 | * @txq: Transmit queue to deallocate. |
333 | * | |
334 | * Empty queue by removing and destroying all BD's. | |
6440adb5 BC |
335 | * Free all buffers. |
336 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 337 | */ |
c79dd5b5 | 338 | void iwl4965_tx_queue_free(struct iwl_priv *priv, struct iwl4965_tx_queue *txq) |
b481de9c | 339 | { |
bb8c093b | 340 | struct iwl4965_queue *q = &txq->q; |
b481de9c ZY |
341 | struct pci_dev *dev = priv->pci_dev; |
342 | int len; | |
343 | ||
344 | if (q->n_bd == 0) | |
345 | return; | |
346 | ||
347 | /* first, empty all BD's */ | |
fc4b6853 | 348 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 349 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 350 | iwl4965_hw_txq_free_tfd(priv, txq); |
b481de9c | 351 | |
857485c0 | 352 | len = sizeof(struct iwl_cmd) * q->n_window; |
b481de9c ZY |
353 | if (q->id == IWL_CMD_QUEUE_NUM) |
354 | len += IWL_MAX_SCAN_SIZE; | |
355 | ||
6440adb5 | 356 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
357 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
358 | ||
6440adb5 | 359 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 360 | if (txq->q.n_bd) |
bb8c093b | 361 | pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) * |
b481de9c ZY |
362 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
363 | ||
6440adb5 | 364 | /* De-alloc array of per-TFD driver data */ |
b481de9c ZY |
365 | if (txq->txb) { |
366 | kfree(txq->txb); | |
367 | txq->txb = NULL; | |
368 | } | |
369 | ||
6440adb5 | 370 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
371 | memset(txq, 0, sizeof(*txq)); |
372 | } | |
373 | ||
bb8c093b | 374 | const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
b481de9c ZY |
375 | |
376 | /*************** STATION TABLE MANAGEMENT **** | |
9fbab516 | 377 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
378 | * the functionality provided here |
379 | */ | |
380 | ||
381 | /**************************************************************/ | |
382 | ||
01ebd063 | 383 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 BC |
384 | /** |
385 | * iwl4965_remove_station - Remove driver's knowledge of station. | |
386 | * | |
387 | * NOTE: This does not remove station from device's station table. | |
388 | */ | |
c79dd5b5 | 389 | static u8 iwl4965_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
390 | { |
391 | int index = IWL_INVALID_STATION; | |
392 | int i; | |
393 | unsigned long flags; | |
394 | ||
395 | spin_lock_irqsave(&priv->sta_lock, flags); | |
396 | ||
397 | if (is_ap) | |
398 | index = IWL_AP_ID; | |
399 | else if (is_broadcast_ether_addr(addr)) | |
400 | index = priv->hw_setting.bcast_sta_id; | |
401 | else | |
402 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) | |
403 | if (priv->stations[i].used && | |
404 | !compare_ether_addr(priv->stations[i].sta.sta.addr, | |
405 | addr)) { | |
406 | index = i; | |
407 | break; | |
408 | } | |
409 | ||
410 | if (unlikely(index == IWL_INVALID_STATION)) | |
411 | goto out; | |
412 | ||
413 | if (priv->stations[index].used) { | |
414 | priv->stations[index].used = 0; | |
415 | priv->num_stations--; | |
416 | } | |
417 | ||
418 | BUG_ON(priv->num_stations < 0); | |
419 | ||
420 | out: | |
421 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
422 | return 0; | |
423 | } | |
556f8db7 | 424 | #endif |
b481de9c | 425 | |
6440adb5 BC |
426 | /** |
427 | * iwl4965_add_station_flags - Add station to tables in driver and device | |
428 | */ | |
c79dd5b5 | 429 | u8 iwl4965_add_station_flags(struct iwl_priv *priv, const u8 *addr, |
67d62035 | 430 | int is_ap, u8 flags, void *ht_data) |
b481de9c ZY |
431 | { |
432 | int i; | |
433 | int index = IWL_INVALID_STATION; | |
bb8c093b | 434 | struct iwl4965_station_entry *station; |
b481de9c | 435 | unsigned long flags_spin; |
0795af57 | 436 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
437 | |
438 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
439 | if (is_ap) | |
440 | index = IWL_AP_ID; | |
441 | else if (is_broadcast_ether_addr(addr)) | |
442 | index = priv->hw_setting.bcast_sta_id; | |
443 | else | |
444 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) { | |
445 | if (!compare_ether_addr(priv->stations[i].sta.sta.addr, | |
446 | addr)) { | |
447 | index = i; | |
448 | break; | |
449 | } | |
450 | ||
451 | if (!priv->stations[i].used && | |
452 | index == IWL_INVALID_STATION) | |
453 | index = i; | |
454 | } | |
455 | ||
456 | ||
9fbab516 BC |
457 | /* These two conditions have the same outcome, but keep them separate |
458 | since they have different meanings */ | |
b481de9c ZY |
459 | if (unlikely(index == IWL_INVALID_STATION)) { |
460 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
461 | return index; | |
462 | } | |
463 | ||
464 | if (priv->stations[index].used && | |
465 | !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) { | |
466 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
467 | return index; | |
468 | } | |
469 | ||
470 | ||
0795af57 | 471 | IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr)); |
b481de9c ZY |
472 | station = &priv->stations[index]; |
473 | station->used = 1; | |
474 | priv->num_stations++; | |
475 | ||
6440adb5 | 476 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 477 | memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd)); |
b481de9c ZY |
478 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
479 | station->sta.mode = 0; | |
480 | station->sta.sta.sta_id = index; | |
481 | station->sta.station_flags = 0; | |
482 | ||
c8b0e6e1 | 483 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
484 | /* BCAST station and IBSS stations do not work in HT mode */ |
485 | if (index != priv->hw_setting.bcast_sta_id && | |
486 | priv->iw_mode != IEEE80211_IF_TYPE_IBSS) | |
67d62035 RR |
487 | iwl4965_set_ht_add_station(priv, index, |
488 | (struct ieee80211_ht_info *) ht_data); | |
c8b0e6e1 | 489 | #endif /*CONFIG_IWL4965_HT*/ |
b481de9c ZY |
490 | |
491 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
6440adb5 BC |
492 | |
493 | /* Add station to device's station table */ | |
bb8c093b | 494 | iwl4965_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
495 | return index; |
496 | ||
497 | } | |
498 | ||
b481de9c | 499 | |
b481de9c ZY |
500 | |
501 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
502 | ||
b481de9c | 503 | /** |
bb8c093b | 504 | * iwl4965_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
505 | * @priv: device private data point |
506 | * @cmd: a point to the ucode command structure | |
507 | * | |
508 | * The function returns < 0 values to indicate the operation is | |
509 | * failed. On success, it turns the index (> 0) of command in the | |
510 | * command queue. | |
511 | */ | |
857485c0 | 512 | int iwl4965_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
b481de9c | 513 | { |
bb8c093b CH |
514 | struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
515 | struct iwl4965_queue *q = &txq->q; | |
516 | struct iwl4965_tfd_frame *tfd; | |
b481de9c | 517 | u32 *control_flags; |
857485c0 | 518 | struct iwl_cmd *out_cmd; |
b481de9c ZY |
519 | u32 idx; |
520 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
521 | dma_addr_t phys_addr; | |
522 | int ret; | |
523 | unsigned long flags; | |
524 | ||
525 | /* If any of the command structures end up being larger than | |
526 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
527 | * we will need to increase the size of the TFD entries */ | |
528 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
529 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
530 | ||
fee1247a | 531 | if (iwl_is_rfkill(priv)) { |
c342a1b9 GG |
532 | IWL_DEBUG_INFO("Not sending command - RF KILL"); |
533 | return -EIO; | |
534 | } | |
535 | ||
bb8c093b | 536 | if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
537 | IWL_ERROR("No space for Tx\n"); |
538 | return -ENOSPC; | |
539 | } | |
540 | ||
541 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
542 | ||
fc4b6853 | 543 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
544 | memset(tfd, 0, sizeof(*tfd)); |
545 | ||
546 | control_flags = (u32 *) tfd; | |
547 | ||
fc4b6853 | 548 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
549 | out_cmd = &txq->cmd[idx]; |
550 | ||
551 | out_cmd->hdr.cmd = cmd->id; | |
552 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
553 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
554 | ||
555 | /* At this point, the out_cmd now has all of the incoming cmd | |
556 | * information */ | |
557 | ||
558 | out_cmd->hdr.flags = 0; | |
559 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 560 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c ZY |
561 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
562 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
563 | ||
564 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
857485c0 | 565 | offsetof(struct iwl_cmd, hdr); |
bb8c093b | 566 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
b481de9c ZY |
567 | |
568 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
569 | "%d bytes at %d[%d]:%d\n", | |
570 | get_cmd_string(out_cmd->hdr.cmd), | |
571 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 572 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
573 | |
574 | txq->need_update = 1; | |
6440adb5 BC |
575 | |
576 | /* Set up entry in queue's byte count circular buffer */ | |
b481de9c | 577 | ret = iwl4965_tx_queue_update_wr_ptr(priv, txq, 0); |
6440adb5 BC |
578 | |
579 | /* Increment and update queue's write index */ | |
c54b679d | 580 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 581 | iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
582 | |
583 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
584 | return ret ? ret : idx; | |
585 | } | |
586 | ||
deb09c43 EG |
587 | static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
588 | { | |
589 | struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; | |
590 | ||
591 | if (hw_decrypt) | |
592 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
593 | else | |
594 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
595 | ||
596 | } | |
597 | ||
c79dd5b5 | 598 | int iwl4965_send_statistics_request(struct iwl_priv *priv) |
b481de9c | 599 | { |
857485c0 TW |
600 | u32 flags = 0; |
601 | return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, | |
602 | sizeof(flags), &flags); | |
b481de9c ZY |
603 | } |
604 | ||
605 | /** | |
bb8c093b | 606 | * iwl4965_rxon_add_station - add station into station table. |
b481de9c ZY |
607 | * |
608 | * there is only one AP station with id= IWL_AP_ID | |
9fbab516 BC |
609 | * NOTE: mutex must be held before calling this fnction |
610 | */ | |
c79dd5b5 | 611 | static int iwl4965_rxon_add_station(struct iwl_priv *priv, |
b481de9c ZY |
612 | const u8 *addr, int is_ap) |
613 | { | |
556f8db7 | 614 | u8 sta_id; |
b481de9c | 615 | |
6440adb5 | 616 | /* Add station to device's station table */ |
67d62035 RR |
617 | #ifdef CONFIG_IWL4965_HT |
618 | struct ieee80211_conf *conf = &priv->hw->conf; | |
619 | struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf; | |
620 | ||
621 | if ((is_ap) && | |
622 | (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) && | |
623 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) | |
624 | sta_id = iwl4965_add_station_flags(priv, addr, is_ap, | |
625 | 0, cur_ht_config); | |
626 | else | |
627 | #endif /* CONFIG_IWL4965_HT */ | |
628 | sta_id = iwl4965_add_station_flags(priv, addr, is_ap, | |
629 | 0, NULL); | |
6440adb5 BC |
630 | |
631 | /* Set up default rate scaling table in device's station table */ | |
b481de9c ZY |
632 | iwl4965_add_station(priv, addr, is_ap); |
633 | ||
556f8db7 | 634 | return sta_id; |
b481de9c ZY |
635 | } |
636 | ||
b481de9c | 637 | /** |
bb8c093b | 638 | * iwl4965_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
639 | * |
640 | * NOTE: This is really only useful during development and can eventually | |
641 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
642 | * making changes | |
643 | */ | |
bb8c093b | 644 | static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon) |
b481de9c ZY |
645 | { |
646 | int error = 0; | |
647 | int counter = 1; | |
648 | ||
649 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
650 | error |= le32_to_cpu(rxon->flags & | |
651 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
652 | RXON_FLG_RADAR_DETECT_MSK)); | |
653 | if (error) | |
654 | IWL_WARNING("check 24G fields %d | %d\n", | |
655 | counter++, error); | |
656 | } else { | |
657 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
658 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
659 | if (error) | |
660 | IWL_WARNING("check 52 fields %d | %d\n", | |
661 | counter++, error); | |
662 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
663 | if (error) | |
664 | IWL_WARNING("check 52 CCK %d | %d\n", | |
665 | counter++, error); | |
666 | } | |
667 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
668 | if (error) | |
669 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
670 | ||
671 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
672 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
673 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
674 | if (error) | |
675 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
676 | ||
677 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
678 | if (error) | |
679 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
680 | ||
681 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
682 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
683 | if (error) | |
684 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
685 | counter++, error); | |
686 | ||
687 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
688 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
689 | if (error) | |
690 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
691 | counter++, error); | |
692 | ||
693 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
694 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
695 | if (error) | |
696 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
697 | counter++, error); | |
698 | ||
699 | if (error) | |
700 | IWL_WARNING("Tuning to channel %d\n", | |
701 | le16_to_cpu(rxon->channel)); | |
702 | ||
703 | if (error) { | |
bb8c093b | 704 | IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
705 | return -1; |
706 | } | |
707 | return 0; | |
708 | } | |
709 | ||
710 | /** | |
9fbab516 | 711 | * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 712 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 713 | * |
9fbab516 BC |
714 | * If the RXON structure is changing enough to require a new tune, |
715 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
716 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 717 | */ |
c79dd5b5 | 718 | static int iwl4965_full_rxon_required(struct iwl_priv *priv) |
b481de9c ZY |
719 | { |
720 | ||
721 | /* These items are only settable from the full RXON command */ | |
722 | if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || | |
723 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
724 | priv->active_rxon.bssid_addr) || | |
725 | compare_ether_addr(priv->staging_rxon.node_addr, | |
726 | priv->active_rxon.node_addr) || | |
727 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
728 | priv->active_rxon.wlap_bssid_addr) || | |
729 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
730 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
731 | (priv->staging_rxon.air_propagation != | |
732 | priv->active_rxon.air_propagation) || | |
733 | (priv->staging_rxon.ofdm_ht_single_stream_basic_rates != | |
734 | priv->active_rxon.ofdm_ht_single_stream_basic_rates) || | |
735 | (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates != | |
736 | priv->active_rxon.ofdm_ht_dual_stream_basic_rates) || | |
737 | (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) || | |
738 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) | |
739 | return 1; | |
740 | ||
741 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
742 | * be updated with the RXON_ASSOC command -- however only some | |
743 | * flag transitions are allowed using RXON_ASSOC */ | |
744 | ||
745 | /* Check if we are not switching bands */ | |
746 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
747 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
748 | return 1; | |
749 | ||
750 | /* Check if we are switching association toggle */ | |
751 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
752 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
753 | return 1; | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
c79dd5b5 | 758 | static int iwl4965_send_rxon_assoc(struct iwl_priv *priv) |
b481de9c ZY |
759 | { |
760 | int rc = 0; | |
bb8c093b CH |
761 | struct iwl4965_rx_packet *res = NULL; |
762 | struct iwl4965_rxon_assoc_cmd rxon_assoc; | |
857485c0 | 763 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
764 | .id = REPLY_RXON_ASSOC, |
765 | .len = sizeof(rxon_assoc), | |
766 | .meta.flags = CMD_WANT_SKB, | |
767 | .data = &rxon_assoc, | |
768 | }; | |
bb8c093b CH |
769 | const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon; |
770 | const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon; | |
b481de9c ZY |
771 | |
772 | if ((rxon1->flags == rxon2->flags) && | |
773 | (rxon1->filter_flags == rxon2->filter_flags) && | |
774 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
775 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
776 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
777 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
778 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
779 | (rxon1->rx_chain == rxon2->rx_chain) && | |
780 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
781 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
782 | return 0; | |
783 | } | |
784 | ||
785 | rxon_assoc.flags = priv->staging_rxon.flags; | |
786 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
787 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
788 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
789 | rxon_assoc.reserved = 0; | |
790 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
791 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
792 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
793 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
794 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
795 | ||
857485c0 | 796 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
797 | if (rc) |
798 | return rc; | |
799 | ||
bb8c093b | 800 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
801 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
802 | IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n"); | |
803 | rc = -EIO; | |
804 | } | |
805 | ||
806 | priv->alloc_rxb_skb--; | |
807 | dev_kfree_skb_any(cmd.meta.u.skb); | |
808 | ||
809 | return rc; | |
810 | } | |
811 | ||
812 | /** | |
bb8c093b | 813 | * iwl4965_commit_rxon - commit staging_rxon to hardware |
b481de9c | 814 | * |
01ebd063 | 815 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
816 | * the active_rxon structure is updated with the new data. This |
817 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
818 | * a HW tune is required based on the RXON structure changes. | |
819 | */ | |
c79dd5b5 | 820 | static int iwl4965_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
821 | { |
822 | /* cast away the const for active_rxon in this function */ | |
bb8c093b | 823 | struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
0795af57 | 824 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
825 | int rc = 0; |
826 | ||
fee1247a | 827 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
828 | return -1; |
829 | ||
830 | /* always get timestamp with Rx frame */ | |
831 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
832 | ||
bb8c093b | 833 | rc = iwl4965_check_rxon_cmd(&priv->staging_rxon); |
b481de9c ZY |
834 | if (rc) { |
835 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 840 | * iwl4965_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 841 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
842 | if (!iwl4965_full_rxon_required(priv)) { |
843 | rc = iwl4965_send_rxon_assoc(priv); | |
b481de9c ZY |
844 | if (rc) { |
845 | IWL_ERROR("Error setting RXON_ASSOC " | |
846 | "configuration (%d).\n", rc); | |
847 | return rc; | |
848 | } | |
849 | ||
850 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | /* station table will be cleared */ | |
856 | priv->assoc_station_added = 0; | |
857 | ||
c8b0e6e1 | 858 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
859 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; |
860 | if (!priv->error_recovering) | |
861 | priv->start_calib = 0; | |
862 | ||
863 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 1); | |
c8b0e6e1 | 864 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
865 | |
866 | /* If we are currently associated and the new config requires | |
867 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
868 | * we must clear the associated from the active configuration | |
869 | * before we apply the new config */ | |
3109ece1 | 870 | if (iwl_is_associated(priv) && |
b481de9c ZY |
871 | (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
872 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); | |
873 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
874 | ||
857485c0 | 875 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON, |
bb8c093b | 876 | sizeof(struct iwl4965_rxon_cmd), |
b481de9c ZY |
877 | &priv->active_rxon); |
878 | ||
879 | /* If the mask clearing failed then we set | |
880 | * active_rxon back to what it was previously */ | |
881 | if (rc) { | |
882 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
883 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
884 | "configuration (%d).\n", rc); | |
885 | return rc; | |
886 | } | |
b481de9c ZY |
887 | } |
888 | ||
889 | IWL_DEBUG_INFO("Sending RXON\n" | |
890 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
891 | "* channel = %d\n" | |
0795af57 | 892 | "* bssid = %s\n", |
b481de9c ZY |
893 | ((priv->staging_rxon.filter_flags & |
894 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), | |
895 | le16_to_cpu(priv->staging_rxon.channel), | |
0795af57 | 896 | print_mac(mac, priv->staging_rxon.bssid_addr)); |
b481de9c | 897 | |
deb09c43 | 898 | iwl4965_set_rxon_hwcrypto(priv, priv->cfg->mod_params->hw_crypto); |
b481de9c | 899 | /* Apply the new configuration */ |
857485c0 | 900 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON, |
bb8c093b | 901 | sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon); |
b481de9c ZY |
902 | if (rc) { |
903 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
904 | return rc; | |
905 | } | |
906 | ||
bf85ea4f | 907 | iwlcore_clear_stations_table(priv); |
556f8db7 | 908 | |
c8b0e6e1 | 909 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
910 | if (!priv->error_recovering) |
911 | priv->start_calib = 0; | |
912 | ||
913 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; | |
914 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 1); | |
c8b0e6e1 | 915 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
916 | |
917 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
918 | ||
919 | /* If we issue a new RXON command which required a tune then we must | |
920 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 921 | rc = iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
922 | if (rc) { |
923 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
924 | return rc; | |
925 | } | |
926 | ||
927 | /* Add the broadcast address so we can send broadcast frames */ | |
bb8c093b | 928 | if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) == |
b481de9c ZY |
929 | IWL_INVALID_STATION) { |
930 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
931 | return -EIO; | |
932 | } | |
933 | ||
934 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
935 | * add the IWL_AP_ID to the station rate table */ | |
3109ece1 | 936 | if (iwl_is_associated(priv) && |
b481de9c | 937 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) { |
bb8c093b | 938 | if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1) |
b481de9c ZY |
939 | == IWL_INVALID_STATION) { |
940 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
941 | return -EIO; | |
942 | } | |
943 | priv->assoc_station_added = 1; | |
944 | } | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
c79dd5b5 | 949 | static int iwl4965_send_bt_config(struct iwl_priv *priv) |
b481de9c | 950 | { |
bb8c093b | 951 | struct iwl4965_bt_cmd bt_cmd = { |
b481de9c ZY |
952 | .flags = 3, |
953 | .lead_time = 0xAA, | |
954 | .max_kill = 1, | |
955 | .kill_ack_mask = 0, | |
956 | .kill_cts_mask = 0, | |
957 | }; | |
958 | ||
857485c0 | 959 | return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
bb8c093b | 960 | sizeof(struct iwl4965_bt_cmd), &bt_cmd); |
b481de9c ZY |
961 | } |
962 | ||
c79dd5b5 | 963 | static int iwl4965_send_scan_abort(struct iwl_priv *priv) |
b481de9c ZY |
964 | { |
965 | int rc = 0; | |
bb8c093b | 966 | struct iwl4965_rx_packet *res; |
857485c0 | 967 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
968 | .id = REPLY_SCAN_ABORT_CMD, |
969 | .meta.flags = CMD_WANT_SKB, | |
970 | }; | |
971 | ||
972 | /* If there isn't a scan actively going on in the hardware | |
973 | * then we are in between scan bands and not actually | |
974 | * actively scanning, so don't send the abort command */ | |
975 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
976 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
977 | return 0; | |
978 | } | |
979 | ||
857485c0 | 980 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
981 | if (rc) { |
982 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
983 | return rc; | |
984 | } | |
985 | ||
bb8c093b | 986 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
987 | if (res->u.status != CAN_ABORT_STATUS) { |
988 | /* The scan abort will return 1 for success or | |
989 | * 2 for "failure". A failure condition can be | |
990 | * due to simply not being in an active scan which | |
991 | * can occur if we send the scan abort before we | |
992 | * the microcode has notified us that a scan is | |
993 | * completed. */ | |
994 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
995 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
996 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
997 | } | |
998 | ||
999 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1000 | ||
1001 | return rc; | |
1002 | } | |
1003 | ||
c79dd5b5 | 1004 | static int iwl4965_card_state_sync_callback(struct iwl_priv *priv, |
857485c0 | 1005 | struct iwl_cmd *cmd, |
b481de9c ZY |
1006 | struct sk_buff *skb) |
1007 | { | |
1008 | return 1; | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * CARD_STATE_CMD | |
1013 | * | |
9fbab516 | 1014 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
1015 | * |
1016 | * When in the 'enable' state the card operates as normal. | |
1017 | * When in the 'disable' state, the card enters into a low power mode. | |
1018 | * When in the 'halt' state, the card is shut down and must be fully | |
1019 | * restarted to come back on. | |
1020 | */ | |
c79dd5b5 | 1021 | static int iwl4965_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1022 | { |
857485c0 | 1023 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
1024 | .id = REPLY_CARD_STATE_CMD, |
1025 | .len = sizeof(u32), | |
1026 | .data = &flags, | |
1027 | .meta.flags = meta_flag, | |
1028 | }; | |
1029 | ||
1030 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1031 | cmd.meta.u.callback = iwl4965_card_state_sync_callback; |
b481de9c | 1032 | |
857485c0 | 1033 | return iwl_send_cmd(priv, &cmd); |
b481de9c ZY |
1034 | } |
1035 | ||
c79dd5b5 | 1036 | static int iwl4965_add_sta_sync_callback(struct iwl_priv *priv, |
857485c0 | 1037 | struct iwl_cmd *cmd, struct sk_buff *skb) |
b481de9c | 1038 | { |
bb8c093b | 1039 | struct iwl4965_rx_packet *res = NULL; |
b481de9c ZY |
1040 | |
1041 | if (!skb) { | |
1042 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1043 | return 1; | |
1044 | } | |
1045 | ||
bb8c093b | 1046 | res = (struct iwl4965_rx_packet *)skb->data; |
b481de9c ZY |
1047 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1048 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1049 | res->hdr.flags); | |
1050 | return 1; | |
1051 | } | |
1052 | ||
1053 | switch (res->u.add_sta.status) { | |
1054 | case ADD_STA_SUCCESS_MSK: | |
1055 | break; | |
1056 | default: | |
1057 | break; | |
1058 | } | |
1059 | ||
1060 | /* We didn't cache the SKB; let the caller free it */ | |
1061 | return 1; | |
1062 | } | |
1063 | ||
c79dd5b5 | 1064 | int iwl4965_send_add_station(struct iwl_priv *priv, |
bb8c093b | 1065 | struct iwl4965_addsta_cmd *sta, u8 flags) |
b481de9c | 1066 | { |
bb8c093b | 1067 | struct iwl4965_rx_packet *res = NULL; |
b481de9c | 1068 | int rc = 0; |
857485c0 | 1069 | struct iwl_host_cmd cmd = { |
b481de9c | 1070 | .id = REPLY_ADD_STA, |
bb8c093b | 1071 | .len = sizeof(struct iwl4965_addsta_cmd), |
b481de9c ZY |
1072 | .meta.flags = flags, |
1073 | .data = sta, | |
1074 | }; | |
1075 | ||
1076 | if (flags & CMD_ASYNC) | |
bb8c093b | 1077 | cmd.meta.u.callback = iwl4965_add_sta_sync_callback; |
b481de9c ZY |
1078 | else |
1079 | cmd.meta.flags |= CMD_WANT_SKB; | |
1080 | ||
857485c0 | 1081 | rc = iwl_send_cmd(priv, &cmd); |
b481de9c ZY |
1082 | |
1083 | if (rc || (flags & CMD_ASYNC)) | |
1084 | return rc; | |
1085 | ||
bb8c093b | 1086 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1087 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1088 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1089 | res->hdr.flags); | |
1090 | rc = -EIO; | |
1091 | } | |
1092 | ||
1093 | if (rc == 0) { | |
1094 | switch (res->u.add_sta.status) { | |
1095 | case ADD_STA_SUCCESS_MSK: | |
1096 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1097 | break; | |
1098 | default: | |
1099 | rc = -EIO; | |
1100 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1101 | break; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | priv->alloc_rxb_skb--; | |
1106 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1107 | ||
1108 | return rc; | |
1109 | } | |
1110 | ||
deb09c43 | 1111 | static int iwl4965_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
1112 | struct ieee80211_key_conf *keyconf, |
1113 | u8 sta_id) | |
1114 | { | |
1115 | unsigned long flags; | |
1116 | __le16 key_flags = 0; | |
1117 | ||
deb09c43 EG |
1118 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); |
1119 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
1120 | ||
1121 | if (sta_id == priv->hw_setting.bcast_sta_id) | |
1122 | key_flags |= STA_KEY_MULTICAST_MSK; | |
1123 | ||
1124 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1125 | keyconf->hw_key_idx = keyconf->keyidx; | |
1126 | ||
1127 | key_flags &= ~STA_KEY_FLG_INVALID; | |
1128 | ||
b481de9c ZY |
1129 | spin_lock_irqsave(&priv->sta_lock, flags); |
1130 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; | |
1131 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
deb09c43 | 1132 | |
b481de9c ZY |
1133 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, |
1134 | keyconf->keylen); | |
1135 | ||
1136 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, | |
1137 | keyconf->keylen); | |
deb09c43 EG |
1138 | |
1139 | priv->stations[sta_id].sta.key.key_offset | |
1140 | = (sta_id % STA_KEY_MAX_NUM);/*FIXME*/ | |
b481de9c ZY |
1141 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
1142 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1143 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1144 | ||
1145 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1146 | ||
1147 | IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); | |
deb09c43 EG |
1148 | return iwl4965_send_add_station(priv, |
1149 | &priv->stations[sta_id].sta, CMD_ASYNC); | |
1150 | } | |
1151 | ||
1152 | static int iwl4965_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
1153 | struct ieee80211_key_conf *keyconf, | |
1154 | u8 sta_id) | |
1155 | { | |
2bc75089 EG |
1156 | unsigned long flags; |
1157 | int ret = 0; | |
1158 | ||
1159 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1160 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
1161 | keyconf->hw_key_idx = keyconf->keyidx; | |
1162 | ||
1163 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1164 | ||
1165 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; | |
1166 | priv->stations[sta_id].keyinfo.conf = keyconf; | |
1167 | priv->stations[sta_id].keyinfo.keylen = 16; | |
1168 | ||
1169 | /* This copy is acutally not needed: we get the key with each TX */ | |
1170 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16); | |
1171 | ||
1172 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, 16); | |
1173 | ||
1174 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1175 | ||
1176 | return ret; | |
b481de9c ZY |
1177 | } |
1178 | ||
c79dd5b5 | 1179 | static int iwl4965_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
1180 | { |
1181 | unsigned long flags; | |
1182 | ||
1183 | spin_lock_irqsave(&priv->sta_lock, flags); | |
bb8c093b CH |
1184 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl4965_hw_key)); |
1185 | memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl4965_keyinfo)); | |
b481de9c ZY |
1186 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
1187 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1188 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1189 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1190 | ||
1191 | IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); | |
bb8c093b | 1192 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1193 | return 0; |
1194 | } | |
1195 | ||
deb09c43 EG |
1196 | static int iwl4965_set_dynamic_key(struct iwl_priv *priv, |
1197 | struct ieee80211_key_conf *key, u8 sta_id) | |
1198 | { | |
1199 | int ret; | |
1200 | ||
1201 | switch (key->alg) { | |
1202 | case ALG_CCMP: | |
1203 | ret = iwl4965_set_ccmp_dynamic_key_info(priv, key, sta_id); | |
1204 | break; | |
1205 | case ALG_TKIP: | |
1206 | ret = iwl4965_set_tkip_dynamic_key_info(priv, key, sta_id); | |
1207 | break; | |
1208 | case ALG_WEP: | |
1209 | ret = -EOPNOTSUPP; | |
1210 | break; | |
1211 | default: | |
1212 | IWL_ERROR("Unknown alg: %s alg = %d\n", __func__, key->alg); | |
1213 | ret = -EINVAL; | |
1214 | } | |
1215 | ||
1216 | return ret; | |
1217 | } | |
1218 | ||
1219 | static int iwl4965_remove_static_key(struct iwl_priv *priv) | |
1220 | { | |
1221 | int ret = -EOPNOTSUPP; | |
1222 | ||
1223 | return ret; | |
1224 | } | |
1225 | ||
1226 | static int iwl4965_set_static_key(struct iwl_priv *priv, | |
1227 | struct ieee80211_key_conf *key) | |
1228 | { | |
1229 | if (key->alg == ALG_WEP) | |
1230 | return -EOPNOTSUPP; | |
1231 | ||
1232 | IWL_ERROR("Static key invalid: alg %d\n", key->alg); | |
1233 | return -EINVAL; | |
1234 | } | |
1235 | ||
c79dd5b5 | 1236 | static void iwl4965_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
1237 | { |
1238 | struct list_head *element; | |
1239 | ||
1240 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1241 | priv->frames_count); | |
1242 | ||
1243 | while (!list_empty(&priv->free_frames)) { | |
1244 | element = priv->free_frames.next; | |
1245 | list_del(element); | |
bb8c093b | 1246 | kfree(list_entry(element, struct iwl4965_frame, list)); |
b481de9c ZY |
1247 | priv->frames_count--; |
1248 | } | |
1249 | ||
1250 | if (priv->frames_count) { | |
1251 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1252 | priv->frames_count); | |
1253 | priv->frames_count = 0; | |
1254 | } | |
1255 | } | |
1256 | ||
c79dd5b5 | 1257 | static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl_priv *priv) |
b481de9c | 1258 | { |
bb8c093b | 1259 | struct iwl4965_frame *frame; |
b481de9c ZY |
1260 | struct list_head *element; |
1261 | if (list_empty(&priv->free_frames)) { | |
1262 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1263 | if (!frame) { | |
1264 | IWL_ERROR("Could not allocate frame!\n"); | |
1265 | return NULL; | |
1266 | } | |
1267 | ||
1268 | priv->frames_count++; | |
1269 | return frame; | |
1270 | } | |
1271 | ||
1272 | element = priv->free_frames.next; | |
1273 | list_del(element); | |
bb8c093b | 1274 | return list_entry(element, struct iwl4965_frame, list); |
b481de9c ZY |
1275 | } |
1276 | ||
c79dd5b5 | 1277 | static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl4965_frame *frame) |
b481de9c ZY |
1278 | { |
1279 | memset(frame, 0, sizeof(*frame)); | |
1280 | list_add(&frame->list, &priv->free_frames); | |
1281 | } | |
1282 | ||
c79dd5b5 | 1283 | unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c ZY |
1284 | struct ieee80211_hdr *hdr, |
1285 | const u8 *dest, int left) | |
1286 | { | |
1287 | ||
3109ece1 | 1288 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
b481de9c ZY |
1289 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && |
1290 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) | |
1291 | return 0; | |
1292 | ||
1293 | if (priv->ibss_beacon->len > left) | |
1294 | return 0; | |
1295 | ||
1296 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1297 | ||
1298 | return priv->ibss_beacon->len; | |
1299 | } | |
1300 | ||
bb8c093b | 1301 | static u8 iwl4965_rate_get_lowest_plcp(int rate_mask) |
b481de9c ZY |
1302 | { |
1303 | u8 i; | |
1304 | ||
1305 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1306 | i = iwl4965_rates[i].next_ieee) { |
b481de9c | 1307 | if (rate_mask & (1 << i)) |
bb8c093b | 1308 | return iwl4965_rates[i].plcp; |
b481de9c ZY |
1309 | } |
1310 | ||
1311 | return IWL_RATE_INVALID; | |
1312 | } | |
1313 | ||
c79dd5b5 | 1314 | static int iwl4965_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 1315 | { |
bb8c093b | 1316 | struct iwl4965_frame *frame; |
b481de9c ZY |
1317 | unsigned int frame_size; |
1318 | int rc; | |
1319 | u8 rate; | |
1320 | ||
bb8c093b | 1321 | frame = iwl4965_get_free_frame(priv); |
b481de9c ZY |
1322 | |
1323 | if (!frame) { | |
1324 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1325 | "command.\n"); | |
1326 | return -ENOMEM; | |
1327 | } | |
1328 | ||
1329 | if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { | |
bb8c093b | 1330 | rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & |
b481de9c ZY |
1331 | 0xFF0); |
1332 | if (rate == IWL_INVALID_RATE) | |
1333 | rate = IWL_RATE_6M_PLCP; | |
1334 | } else { | |
bb8c093b | 1335 | rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF); |
b481de9c ZY |
1336 | if (rate == IWL_INVALID_RATE) |
1337 | rate = IWL_RATE_1M_PLCP; | |
1338 | } | |
1339 | ||
bb8c093b | 1340 | frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1341 | |
857485c0 | 1342 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1343 | &frame->u.cmd[0]); |
1344 | ||
bb8c093b | 1345 | iwl4965_free_frame(priv, frame); |
b481de9c ZY |
1346 | |
1347 | return rc; | |
1348 | } | |
1349 | ||
b481de9c ZY |
1350 | /****************************************************************************** |
1351 | * | |
1352 | * Misc. internal state and helper functions | |
1353 | * | |
1354 | ******************************************************************************/ | |
b481de9c | 1355 | |
c79dd5b5 | 1356 | static void iwl4965_unset_hw_setting(struct iwl_priv *priv) |
b481de9c ZY |
1357 | { |
1358 | if (priv->hw_setting.shared_virt) | |
1359 | pci_free_consistent(priv->pci_dev, | |
bb8c093b | 1360 | sizeof(struct iwl4965_shared), |
b481de9c ZY |
1361 | priv->hw_setting.shared_virt, |
1362 | priv->hw_setting.shared_phys); | |
1363 | } | |
1364 | ||
1365 | /** | |
bb8c093b | 1366 | * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1367 | * |
1368 | * return : set the bit for each supported rate insert in ie | |
1369 | */ | |
bb8c093b | 1370 | static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1371 | u16 basic_rate, int *left) |
b481de9c ZY |
1372 | { |
1373 | u16 ret_rates = 0, bit; | |
1374 | int i; | |
c7c46676 TW |
1375 | u8 *cnt = ie; |
1376 | u8 *rates = ie + 1; | |
b481de9c ZY |
1377 | |
1378 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1379 | if (bit & supported_rate) { | |
1380 | ret_rates |= bit; | |
bb8c093b | 1381 | rates[*cnt] = iwl4965_rates[i].ieee | |
c7c46676 TW |
1382 | ((bit & basic_rate) ? 0x80 : 0x00); |
1383 | (*cnt)++; | |
1384 | (*left)--; | |
1385 | if ((*left <= 0) || | |
1386 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1387 | break; |
1388 | } | |
1389 | } | |
1390 | ||
1391 | return ret_rates; | |
1392 | } | |
1393 | ||
b481de9c | 1394 | /** |
bb8c093b | 1395 | * iwl4965_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1396 | */ |
c79dd5b5 | 1397 | static u16 iwl4965_fill_probe_req(struct iwl_priv *priv, |
78330fdd TW |
1398 | enum ieee80211_band band, |
1399 | struct ieee80211_mgmt *frame, | |
1400 | int left, int is_direct) | |
b481de9c ZY |
1401 | { |
1402 | int len = 0; | |
1403 | u8 *pos = NULL; | |
bee488db | 1404 | u16 active_rates, ret_rates, cck_rates, active_rate_basic; |
8fb88032 | 1405 | #ifdef CONFIG_IWL4965_HT |
78330fdd TW |
1406 | const struct ieee80211_supported_band *sband = |
1407 | iwl4965_get_hw_mode(priv, band); | |
8fb88032 | 1408 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
1409 | |
1410 | /* Make sure there is enough space for the probe request, | |
1411 | * two mandatory IEs and the data */ | |
1412 | left -= 24; | |
1413 | if (left < 0) | |
1414 | return 0; | |
1415 | len += 24; | |
1416 | ||
1417 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
bb8c093b | 1418 | memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN); |
b481de9c | 1419 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
bb8c093b | 1420 | memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN); |
b481de9c ZY |
1421 | frame->seq_ctrl = 0; |
1422 | ||
1423 | /* fill in our indirect SSID IE */ | |
1424 | /* ...next IE... */ | |
1425 | ||
1426 | left -= 2; | |
1427 | if (left < 0) | |
1428 | return 0; | |
1429 | len += 2; | |
1430 | pos = &(frame->u.probe_req.variable[0]); | |
1431 | *pos++ = WLAN_EID_SSID; | |
1432 | *pos++ = 0; | |
1433 | ||
1434 | /* fill in our direct SSID IE... */ | |
1435 | if (is_direct) { | |
1436 | /* ...next IE... */ | |
1437 | left -= 2 + priv->essid_len; | |
1438 | if (left < 0) | |
1439 | return 0; | |
1440 | /* ... fill it in... */ | |
1441 | *pos++ = WLAN_EID_SSID; | |
1442 | *pos++ = priv->essid_len; | |
1443 | memcpy(pos, priv->essid, priv->essid_len); | |
1444 | pos += priv->essid_len; | |
1445 | len += 2 + priv->essid_len; | |
1446 | } | |
1447 | ||
1448 | /* fill in supported rate */ | |
1449 | /* ...next IE... */ | |
1450 | left -= 2; | |
1451 | if (left < 0) | |
1452 | return 0; | |
c7c46676 | 1453 | |
b481de9c ZY |
1454 | /* ... fill it in... */ |
1455 | *pos++ = WLAN_EID_SUPP_RATES; | |
1456 | *pos = 0; | |
c7c46676 | 1457 | |
bee488db | 1458 | /* exclude 60M rate */ |
1459 | active_rates = priv->rates_mask; | |
1460 | active_rates &= ~IWL_RATE_60M_MASK; | |
1461 | ||
1462 | active_rate_basic = active_rates & IWL_BASIC_RATES_MASK; | |
b481de9c | 1463 | |
c7c46676 | 1464 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1465 | ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates, |
bee488db | 1466 | active_rate_basic, &left); |
c7c46676 TW |
1467 | active_rates &= ~ret_rates; |
1468 | ||
bb8c093b | 1469 | ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates, |
bee488db | 1470 | active_rate_basic, &left); |
c7c46676 TW |
1471 | active_rates &= ~ret_rates; |
1472 | ||
b481de9c ZY |
1473 | len += 2 + *pos; |
1474 | pos += (*pos) + 1; | |
c7c46676 | 1475 | if (active_rates == 0) |
b481de9c ZY |
1476 | goto fill_end; |
1477 | ||
1478 | /* fill in supported extended rate */ | |
1479 | /* ...next IE... */ | |
1480 | left -= 2; | |
1481 | if (left < 0) | |
1482 | return 0; | |
1483 | /* ... fill it in... */ | |
1484 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1485 | *pos = 0; | |
bb8c093b | 1486 | iwl4965_supported_rate_to_ie(pos, active_rates, |
bee488db | 1487 | active_rate_basic, &left); |
b481de9c ZY |
1488 | if (*pos > 0) |
1489 | len += 2 + *pos; | |
1490 | ||
c8b0e6e1 | 1491 | #ifdef CONFIG_IWL4965_HT |
78330fdd TW |
1492 | if (sband && sband->ht_info.ht_supported) { |
1493 | struct ieee80211_ht_cap *ht_cap; | |
b481de9c ZY |
1494 | pos += (*pos) + 1; |
1495 | *pos++ = WLAN_EID_HT_CAPABILITY; | |
8fb88032 | 1496 | *pos++ = sizeof(struct ieee80211_ht_cap); |
78330fdd TW |
1497 | ht_cap = (struct ieee80211_ht_cap *)pos; |
1498 | ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap); | |
1499 | memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16); | |
1500 | ht_cap->ampdu_params_info =(sband->ht_info.ampdu_factor & | |
1501 | IEEE80211_HT_CAP_AMPDU_FACTOR) | | |
1502 | ((sband->ht_info.ampdu_density << 2) & | |
1503 | IEEE80211_HT_CAP_AMPDU_DENSITY); | |
8fb88032 | 1504 | len += 2 + sizeof(struct ieee80211_ht_cap); |
b481de9c | 1505 | } |
c8b0e6e1 | 1506 | #endif /*CONFIG_IWL4965_HT */ |
b481de9c ZY |
1507 | |
1508 | fill_end: | |
1509 | return (u16)len; | |
1510 | } | |
1511 | ||
1512 | /* | |
1513 | * QoS support | |
1514 | */ | |
c79dd5b5 | 1515 | static int iwl4965_send_qos_params_command(struct iwl_priv *priv, |
bb8c093b | 1516 | struct iwl4965_qosparam_cmd *qos) |
b481de9c ZY |
1517 | { |
1518 | ||
857485c0 | 1519 | return iwl_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
bb8c093b | 1520 | sizeof(struct iwl4965_qosparam_cmd), qos); |
b481de9c ZY |
1521 | } |
1522 | ||
c79dd5b5 | 1523 | static void iwl4965_activate_qos(struct iwl_priv *priv, u8 force) |
b481de9c ZY |
1524 | { |
1525 | unsigned long flags; | |
1526 | ||
b481de9c ZY |
1527 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1528 | return; | |
1529 | ||
1530 | if (!priv->qos_data.qos_enable) | |
1531 | return; | |
1532 | ||
1533 | spin_lock_irqsave(&priv->lock, flags); | |
1534 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1535 | ||
1536 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1537 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1538 | priv->qos_data.def_qos_parm.qos_flags |= | |
1539 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
b481de9c ZY |
1540 | if (priv->qos_data.qos_active) |
1541 | priv->qos_data.def_qos_parm.qos_flags |= | |
1542 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1543 | ||
c8b0e6e1 | 1544 | #ifdef CONFIG_IWL4965_HT |
fd105e79 | 1545 | if (priv->current_ht_config.is_ht) |
f1f1f5c7 | 1546 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; |
c8b0e6e1 | 1547 | #endif /* CONFIG_IWL4965_HT */ |
f1f1f5c7 | 1548 | |
b481de9c ZY |
1549 | spin_unlock_irqrestore(&priv->lock, flags); |
1550 | ||
3109ece1 | 1551 | if (force || iwl_is_associated(priv)) { |
f1f1f5c7 TW |
1552 | IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
1553 | priv->qos_data.qos_active, | |
1554 | priv->qos_data.def_qos_parm.qos_flags); | |
b481de9c | 1555 | |
bb8c093b | 1556 | iwl4965_send_qos_params_command(priv, |
b481de9c ZY |
1557 | &(priv->qos_data.def_qos_parm)); |
1558 | } | |
1559 | } | |
1560 | ||
b481de9c ZY |
1561 | /* |
1562 | * Power management (not Tx power!) functions | |
1563 | */ | |
1564 | #define MSEC_TO_USEC 1024 | |
1565 | ||
1566 | #define NOSLP __constant_cpu_to_le16(0), 0, 0 | |
1567 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
1568 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) | |
1569 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1570 | __constant_cpu_to_le32(X1), \ | |
1571 | __constant_cpu_to_le32(X2), \ | |
1572 | __constant_cpu_to_le32(X3), \ | |
1573 | __constant_cpu_to_le32(X4)} | |
1574 | ||
1575 | ||
1576 | /* default power management (not Tx power) table values */ | |
1577 | /* for tim 0-10 */ | |
bb8c093b | 1578 | static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = { |
b481de9c ZY |
1579 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1580 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1581 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1582 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1583 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1584 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1585 | }; | |
1586 | ||
1587 | /* for tim > 10 */ | |
bb8c093b | 1588 | static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = { |
b481de9c ZY |
1589 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1590 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1591 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1592 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1593 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1594 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1595 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1596 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1597 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1598 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1599 | }; | |
1600 | ||
c79dd5b5 | 1601 | int iwl4965_power_init_handle(struct iwl_priv *priv) |
b481de9c ZY |
1602 | { |
1603 | int rc = 0, i; | |
bb8c093b CH |
1604 | struct iwl4965_power_mgr *pow_data; |
1605 | int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC; | |
b481de9c ZY |
1606 | u16 pci_pm; |
1607 | ||
1608 | IWL_DEBUG_POWER("Initialize power \n"); | |
1609 | ||
1610 | pow_data = &(priv->power_data); | |
1611 | ||
1612 | memset(pow_data, 0, sizeof(*pow_data)); | |
1613 | ||
1614 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1615 | pow_data->dtim_val = 0xffff; | |
1616 | ||
1617 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1618 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1619 | ||
1620 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1621 | if (rc != 0) | |
1622 | return 0; | |
1623 | else { | |
bb8c093b | 1624 | struct iwl4965_powertable_cmd *cmd; |
b481de9c ZY |
1625 | |
1626 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1627 | ||
1628 | for (i = 0; i < IWL_POWER_AC; i++) { | |
1629 | cmd = &pow_data->pwr_range_0[i].cmd; | |
1630 | ||
1631 | if (pci_pm & 0x1) | |
1632 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1633 | else | |
1634 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1635 | } | |
1636 | } | |
1637 | return rc; | |
1638 | } | |
1639 | ||
c79dd5b5 | 1640 | static int iwl4965_update_power_cmd(struct iwl_priv *priv, |
bb8c093b | 1641 | struct iwl4965_powertable_cmd *cmd, u32 mode) |
b481de9c ZY |
1642 | { |
1643 | int rc = 0, i; | |
1644 | u8 skip; | |
1645 | u32 max_sleep = 0; | |
bb8c093b | 1646 | struct iwl4965_power_vec_entry *range; |
b481de9c | 1647 | u8 period = 0; |
bb8c093b | 1648 | struct iwl4965_power_mgr *pow_data; |
b481de9c ZY |
1649 | |
1650 | if (mode > IWL_POWER_INDEX_5) { | |
1651 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1652 | return -1; | |
1653 | } | |
1654 | pow_data = &(priv->power_data); | |
1655 | ||
1656 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1657 | range = &pow_data->pwr_range_0[0]; | |
1658 | else | |
1659 | range = &pow_data->pwr_range_1[1]; | |
1660 | ||
bb8c093b | 1661 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd)); |
b481de9c ZY |
1662 | |
1663 | #ifdef IWL_MAC80211_DISABLE | |
1664 | if (priv->assoc_network != NULL) { | |
1665 | unsigned long flags; | |
1666 | ||
1667 | period = priv->assoc_network->tim.tim_period; | |
1668 | } | |
1669 | #endif /*IWL_MAC80211_DISABLE */ | |
1670 | skip = range[mode].no_dtim; | |
1671 | ||
1672 | if (period == 0) { | |
1673 | period = 1; | |
1674 | skip = 0; | |
1675 | } | |
1676 | ||
1677 | if (skip == 0) { | |
1678 | max_sleep = period; | |
1679 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1680 | } else { | |
1681 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1682 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1683 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1684 | } | |
1685 | ||
1686 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1687 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1688 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1689 | } | |
1690 | ||
1691 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1692 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1693 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1694 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1695 | le32_to_cpu(cmd->sleep_interval[0]), | |
1696 | le32_to_cpu(cmd->sleep_interval[1]), | |
1697 | le32_to_cpu(cmd->sleep_interval[2]), | |
1698 | le32_to_cpu(cmd->sleep_interval[3]), | |
1699 | le32_to_cpu(cmd->sleep_interval[4])); | |
1700 | ||
1701 | return rc; | |
1702 | } | |
1703 | ||
c79dd5b5 | 1704 | static int iwl4965_send_power_mode(struct iwl_priv *priv, u32 mode) |
b481de9c | 1705 | { |
9a62f73b | 1706 | u32 uninitialized_var(final_mode); |
b481de9c | 1707 | int rc; |
bb8c093b | 1708 | struct iwl4965_powertable_cmd cmd; |
b481de9c ZY |
1709 | |
1710 | /* If on battery, set to 3, | |
01ebd063 | 1711 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
1712 | * else user level */ |
1713 | switch (mode) { | |
1714 | case IWL_POWER_BATTERY: | |
1715 | final_mode = IWL_POWER_INDEX_3; | |
1716 | break; | |
1717 | case IWL_POWER_AC: | |
1718 | final_mode = IWL_POWER_MODE_CAM; | |
1719 | break; | |
1720 | default: | |
1721 | final_mode = mode; | |
1722 | break; | |
1723 | } | |
1724 | ||
1725 | cmd.keep_alive_beacons = 0; | |
1726 | ||
bb8c093b | 1727 | iwl4965_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 1728 | |
857485c0 | 1729 | rc = iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
1730 | |
1731 | if (final_mode == IWL_POWER_MODE_CAM) | |
1732 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
1733 | else | |
1734 | set_bit(STATUS_POWER_PMI, &priv->status); | |
1735 | ||
1736 | return rc; | |
1737 | } | |
1738 | ||
c79dd5b5 | 1739 | int iwl4965_is_network_packet(struct iwl_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
1740 | { |
1741 | /* Filter incoming packets to determine if they are targeted toward | |
1742 | * this network, discarding packets coming from ourselves */ | |
1743 | switch (priv->iw_mode) { | |
1744 | case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */ | |
1745 | /* packets from our adapter are dropped (echo) */ | |
1746 | if (!compare_ether_addr(header->addr2, priv->mac_addr)) | |
1747 | return 0; | |
1748 | /* {broad,multi}cast packets to our IBSS go through */ | |
1749 | if (is_multicast_ether_addr(header->addr1)) | |
1750 | return !compare_ether_addr(header->addr3, priv->bssid); | |
1751 | /* packets to our adapter go through */ | |
1752 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
1753 | case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */ | |
1754 | /* packets from our adapter are dropped (echo) */ | |
1755 | if (!compare_ether_addr(header->addr3, priv->mac_addr)) | |
1756 | return 0; | |
1757 | /* {broad,multi}cast packets to our BSS go through */ | |
1758 | if (is_multicast_ether_addr(header->addr1)) | |
1759 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1760 | /* packets to our adapter go through */ | |
1761 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
69dc5d9d TW |
1762 | default: |
1763 | break; | |
b481de9c ZY |
1764 | } |
1765 | ||
1766 | return 1; | |
1767 | } | |
1768 | ||
1769 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
1770 | ||
bb8c093b | 1771 | static const char *iwl4965_get_tx_fail_reason(u32 status) |
b481de9c ZY |
1772 | { |
1773 | switch (status & TX_STATUS_MSK) { | |
1774 | case TX_STATUS_SUCCESS: | |
1775 | return "SUCCESS"; | |
1776 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1777 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1778 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1779 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1780 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1781 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1782 | TX_STATUS_ENTRY(DEST_PS); | |
1783 | TX_STATUS_ENTRY(ABORTED); | |
1784 | TX_STATUS_ENTRY(BT_RETRY); | |
1785 | TX_STATUS_ENTRY(STA_INVALID); | |
1786 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1787 | TX_STATUS_ENTRY(TID_DISABLE); | |
1788 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1789 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1790 | TX_STATUS_ENTRY(TX_LOCKED); | |
1791 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1792 | } | |
1793 | ||
1794 | return "UNKNOWN"; | |
1795 | } | |
1796 | ||
1797 | /** | |
bb8c093b | 1798 | * iwl4965_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
1799 | * |
1800 | * NOTE: priv->mutex is not required before calling this function | |
1801 | */ | |
c79dd5b5 | 1802 | static int iwl4965_scan_cancel(struct iwl_priv *priv) |
b481de9c ZY |
1803 | { |
1804 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1805 | clear_bit(STATUS_SCANNING, &priv->status); | |
1806 | return 0; | |
1807 | } | |
1808 | ||
1809 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1810 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1811 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
1812 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1813 | queue_work(priv->workqueue, &priv->abort_scan); | |
1814 | ||
1815 | } else | |
1816 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
1817 | ||
1818 | return test_bit(STATUS_SCANNING, &priv->status); | |
1819 | } | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
1824 | /** | |
bb8c093b | 1825 | * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
1826 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
1827 | * | |
1828 | * NOTE: priv->mutex must be held before calling this function | |
1829 | */ | |
c79dd5b5 | 1830 | static int iwl4965_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms) |
b481de9c ZY |
1831 | { |
1832 | unsigned long now = jiffies; | |
1833 | int ret; | |
1834 | ||
bb8c093b | 1835 | ret = iwl4965_scan_cancel(priv); |
b481de9c ZY |
1836 | if (ret && ms) { |
1837 | mutex_unlock(&priv->mutex); | |
1838 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
1839 | test_bit(STATUS_SCANNING, &priv->status)) | |
1840 | msleep(1); | |
1841 | mutex_lock(&priv->mutex); | |
1842 | ||
1843 | return test_bit(STATUS_SCANNING, &priv->status); | |
1844 | } | |
1845 | ||
1846 | return ret; | |
1847 | } | |
1848 | ||
c79dd5b5 | 1849 | static void iwl4965_sequence_reset(struct iwl_priv *priv) |
b481de9c ZY |
1850 | { |
1851 | /* Reset ieee stats */ | |
1852 | ||
1853 | /* We don't reset the net_device_stats (ieee->stats) on | |
1854 | * re-association */ | |
1855 | ||
1856 | priv->last_seq_num = -1; | |
1857 | priv->last_frag_num = -1; | |
1858 | priv->last_packet_time = 0; | |
1859 | ||
bb8c093b | 1860 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
1861 | } |
1862 | ||
1863 | #define MAX_UCODE_BEACON_INTERVAL 4096 | |
1864 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
1865 | ||
bb8c093b | 1866 | static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
1867 | { |
1868 | u16 new_val = 0; | |
1869 | u16 beacon_factor = 0; | |
1870 | ||
1871 | beacon_factor = | |
1872 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
1873 | / MAX_UCODE_BEACON_INTERVAL; | |
1874 | new_val = beacon_val / beacon_factor; | |
1875 | ||
1876 | return cpu_to_le16(new_val); | |
1877 | } | |
1878 | ||
c79dd5b5 | 1879 | static void iwl4965_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
1880 | { |
1881 | u64 interval_tm_unit; | |
1882 | u64 tsf, result; | |
1883 | unsigned long flags; | |
1884 | struct ieee80211_conf *conf = NULL; | |
1885 | u16 beacon_int = 0; | |
1886 | ||
1887 | conf = ieee80211_get_hw_conf(priv->hw); | |
1888 | ||
1889 | spin_lock_irqsave(&priv->lock, flags); | |
3109ece1 TW |
1890 | priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp >> 32); |
1891 | priv->rxon_timing.timestamp.dw[0] = | |
1892 | cpu_to_le32(priv->timestamp & 0xFFFFFFFF); | |
b481de9c ZY |
1893 | |
1894 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | |
1895 | ||
3109ece1 | 1896 | tsf = priv->timestamp; |
b481de9c ZY |
1897 | |
1898 | beacon_int = priv->beacon_int; | |
1899 | spin_unlock_irqrestore(&priv->lock, flags); | |
1900 | ||
1901 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) { | |
1902 | if (beacon_int == 0) { | |
1903 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
1904 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
1905 | } else { | |
1906 | priv->rxon_timing.beacon_interval = | |
1907 | cpu_to_le16(beacon_int); | |
1908 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1909 | iwl4965_adjust_beacon_interval( |
b481de9c ZY |
1910 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
1911 | } | |
1912 | ||
1913 | priv->rxon_timing.atim_window = 0; | |
1914 | } else { | |
1915 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1916 | iwl4965_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
1917 | /* TODO: we need to get atim_window from upper stack |
1918 | * for now we set to 0 */ | |
1919 | priv->rxon_timing.atim_window = 0; | |
1920 | } | |
1921 | ||
1922 | interval_tm_unit = | |
1923 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
1924 | result = do_div(tsf, interval_tm_unit); | |
1925 | priv->rxon_timing.beacon_init_val = | |
1926 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
1927 | ||
1928 | IWL_DEBUG_ASSOC | |
1929 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
1930 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
1931 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
1932 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
1933 | } | |
1934 | ||
c79dd5b5 | 1935 | static int iwl4965_scan_initiate(struct iwl_priv *priv) |
b481de9c ZY |
1936 | { |
1937 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
1938 | IWL_ERROR("APs don't scan.\n"); | |
1939 | return 0; | |
1940 | } | |
1941 | ||
fee1247a | 1942 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
1943 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
1944 | return -EIO; | |
1945 | } | |
1946 | ||
1947 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1948 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
1949 | return -EAGAIN; | |
1950 | } | |
1951 | ||
1952 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1953 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
1954 | "Queuing.\n"); | |
1955 | return -EAGAIN; | |
1956 | } | |
1957 | ||
1958 | IWL_DEBUG_INFO("Starting scan...\n"); | |
1959 | priv->scan_bands = 2; | |
1960 | set_bit(STATUS_SCANNING, &priv->status); | |
1961 | priv->scan_start = jiffies; | |
1962 | priv->scan_pass_start = priv->scan_start; | |
1963 | ||
1964 | queue_work(priv->workqueue, &priv->request_scan); | |
1965 | ||
1966 | return 0; | |
1967 | } | |
1968 | ||
b481de9c | 1969 | |
c79dd5b5 | 1970 | static void iwl4965_set_flags_for_phymode(struct iwl_priv *priv, |
8318d78a | 1971 | enum ieee80211_band band) |
b481de9c | 1972 | { |
8318d78a | 1973 | if (band == IEEE80211_BAND_5GHZ) { |
b481de9c ZY |
1974 | priv->staging_rxon.flags &= |
1975 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
1976 | | RXON_FLG_CCK_MSK); | |
1977 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1978 | } else { | |
bb8c093b | 1979 | /* Copied from iwl4965_bg_post_associate() */ |
b481de9c ZY |
1980 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
1981 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1982 | else | |
1983 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1984 | ||
1985 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
1986 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1987 | ||
1988 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1989 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
1990 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
1991 | } | |
1992 | } | |
1993 | ||
1994 | /* | |
01ebd063 | 1995 | * initialize rxon structure with default values from eeprom |
b481de9c | 1996 | */ |
c79dd5b5 | 1997 | static void iwl4965_connection_init_rx_config(struct iwl_priv *priv) |
b481de9c | 1998 | { |
bf85ea4f | 1999 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
2000 | |
2001 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
2002 | ||
2003 | switch (priv->iw_mode) { | |
2004 | case IEEE80211_IF_TYPE_AP: | |
2005 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
2006 | break; | |
2007 | ||
2008 | case IEEE80211_IF_TYPE_STA: | |
2009 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
2010 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
2011 | break; | |
2012 | ||
2013 | case IEEE80211_IF_TYPE_IBSS: | |
2014 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
2015 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
2016 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
2017 | RXON_FILTER_ACCEPT_GRP_MSK; | |
2018 | break; | |
2019 | ||
2020 | case IEEE80211_IF_TYPE_MNTR: | |
2021 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; | |
2022 | priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
2023 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
2024 | break; | |
69dc5d9d TW |
2025 | default: |
2026 | IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode); | |
2027 | break; | |
b481de9c ZY |
2028 | } |
2029 | ||
2030 | #if 0 | |
2031 | /* TODO: Figure out when short_preamble would be set and cache from | |
2032 | * that */ | |
2033 | if (!hw_to_local(priv->hw)->short_preamble) | |
2034 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2035 | else | |
2036 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2037 | #endif | |
2038 | ||
8622e705 | 2039 | ch_info = iwl_get_channel_info(priv, priv->band, |
b481de9c ZY |
2040 | le16_to_cpu(priv->staging_rxon.channel)); |
2041 | ||
2042 | if (!ch_info) | |
2043 | ch_info = &priv->channel_info[0]; | |
2044 | ||
2045 | /* | |
2046 | * in some case A channels are all non IBSS | |
2047 | * in this case force B/G channel | |
2048 | */ | |
2049 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | |
2050 | !(is_channel_ibss(ch_info))) | |
2051 | ch_info = &priv->channel_info[0]; | |
2052 | ||
2053 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
8318d78a | 2054 | priv->band = ch_info->band; |
b481de9c | 2055 | |
8318d78a | 2056 | iwl4965_set_flags_for_phymode(priv, priv->band); |
b481de9c ZY |
2057 | |
2058 | priv->staging_rxon.ofdm_basic_rates = | |
2059 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2060 | priv->staging_rxon.cck_basic_rates = | |
2061 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2062 | ||
2063 | priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | | |
2064 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); | |
2065 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); | |
2066 | memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); | |
2067 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; | |
2068 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; | |
2069 | iwl4965_set_rxon_chain(priv); | |
2070 | } | |
2071 | ||
c79dd5b5 | 2072 | static int iwl4965_set_mode(struct iwl_priv *priv, int mode) |
b481de9c | 2073 | { |
b481de9c | 2074 | if (mode == IEEE80211_IF_TYPE_IBSS) { |
bf85ea4f | 2075 | const struct iwl_channel_info *ch_info; |
b481de9c | 2076 | |
8622e705 | 2077 | ch_info = iwl_get_channel_info(priv, |
8318d78a | 2078 | priv->band, |
b481de9c ZY |
2079 | le16_to_cpu(priv->staging_rxon.channel)); |
2080 | ||
2081 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2082 | IWL_ERROR("channel %d not IBSS channel\n", | |
2083 | le16_to_cpu(priv->staging_rxon.channel)); | |
2084 | return -EINVAL; | |
2085 | } | |
2086 | } | |
2087 | ||
b481de9c ZY |
2088 | priv->iw_mode = mode; |
2089 | ||
bb8c093b | 2090 | iwl4965_connection_init_rx_config(priv); |
b481de9c ZY |
2091 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2092 | ||
bf85ea4f | 2093 | iwlcore_clear_stations_table(priv); |
b481de9c | 2094 | |
fde3571f | 2095 | /* dont commit rxon if rf-kill is on*/ |
fee1247a | 2096 | if (!iwl_is_ready_rf(priv)) |
fde3571f MA |
2097 | return -EAGAIN; |
2098 | ||
2099 | cancel_delayed_work(&priv->scan_check); | |
2100 | if (iwl4965_scan_cancel_timeout(priv, 100)) { | |
2101 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
2102 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
2103 | return -EAGAIN; | |
2104 | } | |
2105 | ||
bb8c093b | 2106 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
2107 | |
2108 | return 0; | |
2109 | } | |
2110 | ||
c79dd5b5 | 2111 | static void iwl4965_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
b481de9c | 2112 | struct ieee80211_tx_control *ctl, |
857485c0 | 2113 | struct iwl_cmd *cmd, |
b481de9c | 2114 | struct sk_buff *skb_frag, |
deb09c43 | 2115 | int sta_id) |
b481de9c | 2116 | { |
deb09c43 | 2117 | struct iwl4965_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
b481de9c ZY |
2118 | |
2119 | switch (keyinfo->alg) { | |
2120 | case ALG_CCMP: | |
2121 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
2122 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
8236e183 MS |
2123 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
2124 | cmd->cmd.tx.tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
b481de9c ZY |
2125 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); |
2126 | break; | |
2127 | ||
2128 | case ALG_TKIP: | |
b481de9c | 2129 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; |
2bc75089 EG |
2130 | ieee80211_get_tkip_key(keyinfo->conf, skb_frag, |
2131 | IEEE80211_TKIP_P2_KEY, cmd->cmd.tx.key); | |
2132 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); | |
b481de9c ZY |
2133 | break; |
2134 | ||
2135 | case ALG_WEP: | |
2136 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP | | |
2137 | (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; | |
2138 | ||
2139 | if (keyinfo->keylen == 13) | |
2140 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2141 | ||
2142 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen); | |
2143 | ||
2144 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
2145 | "with key %d\n", ctl->key_idx); | |
2146 | break; | |
2147 | ||
b481de9c ZY |
2148 | default: |
2149 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2150 | break; | |
2151 | } | |
2152 | } | |
2153 | ||
2154 | /* | |
2155 | * handle build REPLY_TX command notification. | |
2156 | */ | |
c79dd5b5 | 2157 | static void iwl4965_build_tx_cmd_basic(struct iwl_priv *priv, |
857485c0 | 2158 | struct iwl_cmd *cmd, |
b481de9c ZY |
2159 | struct ieee80211_tx_control *ctrl, |
2160 | struct ieee80211_hdr *hdr, | |
2161 | int is_unicast, u8 std_id) | |
2162 | { | |
2163 | __le16 *qc; | |
2164 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2165 | __le32 tx_flags = cmd->cmd.tx.tx_flags; | |
2166 | ||
2167 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
2168 | if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { | |
2169 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
2170 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
2171 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2172 | if (ieee80211_is_probe_response(fc) && | |
2173 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
2174 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2175 | } else { | |
2176 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2177 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2178 | } | |
2179 | ||
87e4f7df TW |
2180 | if (ieee80211_is_back_request(fc)) |
2181 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
2182 | ||
2183 | ||
b481de9c ZY |
2184 | cmd->cmd.tx.sta_id = std_id; |
2185 | if (ieee80211_get_morefrag(hdr)) | |
2186 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
2187 | ||
2188 | qc = ieee80211_get_qos_ctrl(hdr); | |
2189 | if (qc) { | |
2190 | cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf); | |
2191 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
2192 | } else | |
2193 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2194 | ||
2195 | if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { | |
2196 | tx_flags |= TX_CMD_FLG_RTS_MSK; | |
2197 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
2198 | } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { | |
2199 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
2200 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2201 | } | |
2202 | ||
2203 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2204 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2205 | ||
2206 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
2207 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { | |
2208 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || | |
2209 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) | |
bc434dd2 | 2210 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2211 | else |
bc434dd2 | 2212 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2213 | } else { |
b481de9c | 2214 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; |
ab53d8af | 2215 | } |
b481de9c ZY |
2216 | |
2217 | cmd->cmd.tx.driver_txop = 0; | |
2218 | cmd->cmd.tx.tx_flags = tx_flags; | |
2219 | cmd->cmd.tx.next_frame_len = 0; | |
2220 | } | |
19758bef TW |
2221 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) |
2222 | { | |
2223 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
2224 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
2225 | priv->tx_stats[idx].cnt++; | |
2226 | priv->tx_stats[idx].bytes += len; | |
2227 | } | |
6440adb5 BC |
2228 | /** |
2229 | * iwl4965_get_sta_id - Find station's index within station table | |
2230 | * | |
2231 | * If new IBSS station, create new entry in station table | |
2232 | */ | |
c79dd5b5 | 2233 | static int iwl4965_get_sta_id(struct iwl_priv *priv, |
9fbab516 | 2234 | struct ieee80211_hdr *hdr) |
b481de9c ZY |
2235 | { |
2236 | int sta_id; | |
2237 | u16 fc = le16_to_cpu(hdr->frame_control); | |
0795af57 | 2238 | DECLARE_MAC_BUF(mac); |
b481de9c | 2239 | |
6440adb5 | 2240 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2241 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2242 | is_multicast_ether_addr(hdr->addr1)) | |
2243 | return priv->hw_setting.bcast_sta_id; | |
2244 | ||
2245 | switch (priv->iw_mode) { | |
2246 | ||
6440adb5 BC |
2247 | /* If we are a client station in a BSS network, use the special |
2248 | * AP station entry (that's the only station we communicate with) */ | |
b481de9c ZY |
2249 | case IEEE80211_IF_TYPE_STA: |
2250 | return IWL_AP_ID; | |
2251 | ||
2252 | /* If we are an AP, then find the station, or use BCAST */ | |
2253 | case IEEE80211_IF_TYPE_AP: | |
bb8c093b | 2254 | sta_id = iwl4965_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2255 | if (sta_id != IWL_INVALID_STATION) |
2256 | return sta_id; | |
2257 | return priv->hw_setting.bcast_sta_id; | |
2258 | ||
6440adb5 BC |
2259 | /* If this frame is going out to an IBSS network, find the station, |
2260 | * or create a new station table entry */ | |
b481de9c | 2261 | case IEEE80211_IF_TYPE_IBSS: |
bb8c093b | 2262 | sta_id = iwl4965_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2263 | if (sta_id != IWL_INVALID_STATION) |
2264 | return sta_id; | |
2265 | ||
6440adb5 | 2266 | /* Create new station table entry */ |
67d62035 RR |
2267 | sta_id = iwl4965_add_station_flags(priv, hdr->addr1, |
2268 | 0, CMD_ASYNC, NULL); | |
b481de9c ZY |
2269 | |
2270 | if (sta_id != IWL_INVALID_STATION) | |
2271 | return sta_id; | |
2272 | ||
0795af57 | 2273 | IWL_DEBUG_DROP("Station %s not in station map. " |
b481de9c | 2274 | "Defaulting to broadcast...\n", |
0795af57 | 2275 | print_mac(mac, hdr->addr1)); |
0a6857e7 | 2276 | iwl_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
b481de9c ZY |
2277 | return priv->hw_setting.bcast_sta_id; |
2278 | ||
2279 | default: | |
01ebd063 | 2280 | IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); |
b481de9c ZY |
2281 | return priv->hw_setting.bcast_sta_id; |
2282 | } | |
2283 | } | |
2284 | ||
2285 | /* | |
2286 | * start REPLY_TX command process | |
2287 | */ | |
c79dd5b5 | 2288 | static int iwl4965_tx_skb(struct iwl_priv *priv, |
b481de9c ZY |
2289 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) |
2290 | { | |
2291 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
bb8c093b | 2292 | struct iwl4965_tfd_frame *tfd; |
b481de9c ZY |
2293 | u32 *control_flags; |
2294 | int txq_id = ctl->queue; | |
bb8c093b CH |
2295 | struct iwl4965_tx_queue *txq = NULL; |
2296 | struct iwl4965_queue *q = NULL; | |
b481de9c ZY |
2297 | dma_addr_t phys_addr; |
2298 | dma_addr_t txcmd_phys; | |
87e4f7df | 2299 | dma_addr_t scratch_phys; |
857485c0 | 2300 | struct iwl_cmd *out_cmd = NULL; |
b481de9c ZY |
2301 | u16 len, idx, len_org; |
2302 | u8 id, hdr_len, unicast; | |
2303 | u8 sta_id; | |
2304 | u16 seq_number = 0; | |
2305 | u16 fc; | |
2306 | __le16 *qc; | |
2307 | u8 wait_write_ptr = 0; | |
2308 | unsigned long flags; | |
2309 | int rc; | |
2310 | ||
2311 | spin_lock_irqsave(&priv->lock, flags); | |
fee1247a | 2312 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
2313 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2314 | goto drop_unlock; | |
2315 | } | |
2316 | ||
32bfd35d JB |
2317 | if (!priv->vif) { |
2318 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
b481de9c ZY |
2319 | goto drop_unlock; |
2320 | } | |
2321 | ||
8318d78a | 2322 | if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2323 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2324 | goto drop_unlock; | |
2325 | } | |
2326 | ||
2327 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2328 | id = 0; | |
2329 | ||
2330 | fc = le16_to_cpu(hdr->frame_control); | |
2331 | ||
0a6857e7 | 2332 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2333 | if (ieee80211_is_auth(fc)) |
2334 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
2335 | else if (ieee80211_is_assoc_request(fc)) | |
2336 | IWL_DEBUG_TX("Sending ASSOC frame\n"); | |
2337 | else if (ieee80211_is_reassoc_request(fc)) | |
2338 | IWL_DEBUG_TX("Sending REASSOC frame\n"); | |
2339 | #endif | |
2340 | ||
7878a5a4 | 2341 | /* drop all data frame if we are not associated */ |
76f3915b | 2342 | if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) && |
3109ece1 | 2343 | (!iwl_is_associated(priv) || |
a6477249 | 2344 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) || |
76f3915b | 2345 | !priv->assoc_station_added)) { |
3109ece1 | 2346 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
2347 | goto drop_unlock; |
2348 | } | |
2349 | ||
2350 | spin_unlock_irqrestore(&priv->lock, flags); | |
2351 | ||
2352 | hdr_len = ieee80211_get_hdrlen(fc); | |
6440adb5 BC |
2353 | |
2354 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2355 | sta_id = iwl4965_get_sta_id(priv, hdr); |
b481de9c | 2356 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
2357 | DECLARE_MAC_BUF(mac); |
2358 | ||
2359 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
2360 | print_mac(mac, hdr->addr1)); | |
b481de9c ZY |
2361 | goto drop; |
2362 | } | |
2363 | ||
2364 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2365 | ||
2366 | qc = ieee80211_get_qos_ctrl(hdr); | |
2367 | if (qc) { | |
2368 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2369 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
2370 | IEEE80211_SCTL_SEQ; | |
2371 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2372 | (hdr->seq_ctrl & | |
2373 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2374 | seq_number += 0x10; | |
c8b0e6e1 | 2375 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 2376 | /* aggregation is on for this <sta,tid> */ |
fe01b477 | 2377 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
b481de9c | 2378 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
fe01b477 | 2379 | priv->stations[sta_id].tid[tid].tfds_in_queue++; |
c8b0e6e1 | 2380 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 2381 | } |
6440adb5 BC |
2382 | |
2383 | /* Descriptor for chosen Tx queue */ | |
b481de9c ZY |
2384 | txq = &priv->txq[txq_id]; |
2385 | q = &txq->q; | |
2386 | ||
2387 | spin_lock_irqsave(&priv->lock, flags); | |
2388 | ||
6440adb5 | 2389 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2390 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2391 | memset(tfd, 0, sizeof(*tfd)); |
2392 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2393 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2394 | |
6440adb5 | 2395 | /* Set up driver data for this TFD */ |
bb8c093b | 2396 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info)); |
fc4b6853 TW |
2397 | txq->txb[q->write_ptr].skb[0] = skb; |
2398 | memcpy(&(txq->txb[q->write_ptr].status.control), | |
b481de9c | 2399 | ctl, sizeof(struct ieee80211_tx_control)); |
6440adb5 BC |
2400 | |
2401 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2402 | out_cmd = &txq->cmd[idx]; |
2403 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2404 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 BC |
2405 | |
2406 | /* | |
2407 | * Set up the Tx-command (not MAC!) header. | |
2408 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2409 | * after Tx, uCode's Tx response will return this value so driver can | |
2410 | * locate the frame within the tx queue and do post-tx processing. | |
2411 | */ | |
b481de9c ZY |
2412 | out_cmd->hdr.cmd = REPLY_TX; |
2413 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2414 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
2415 | |
2416 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2417 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2418 | ||
6440adb5 BC |
2419 | /* |
2420 | * Use the first empty entry in this queue's command buffer array | |
2421 | * to contain the Tx command and MAC header concatenated together | |
2422 | * (payload data will be in another buffer). | |
2423 | * Size of this varies, due to varying MAC header length. | |
2424 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2425 | * of the MAC header (device reads on dword boundaries). | |
2426 | * We'll tell device about this padding later. | |
2427 | */ | |
b481de9c | 2428 | len = priv->hw_setting.tx_cmd_len + |
857485c0 | 2429 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
2430 | |
2431 | len_org = len; | |
2432 | len = (len + 3) & ~3; | |
2433 | ||
2434 | if (len_org != len) | |
2435 | len_org = 1; | |
2436 | else | |
2437 | len_org = 0; | |
2438 | ||
6440adb5 BC |
2439 | /* Physical address of this Tx command's header (not MAC header!), |
2440 | * within command buffer array. */ | |
857485c0 TW |
2441 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + |
2442 | offsetof(struct iwl_cmd, hdr); | |
b481de9c | 2443 | |
6440adb5 BC |
2444 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2445 | * first entry */ | |
bb8c093b | 2446 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c ZY |
2447 | |
2448 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) | |
deb09c43 | 2449 | iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, sta_id); |
b481de9c | 2450 | |
6440adb5 BC |
2451 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2452 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2453 | len = skb->len - hdr_len; |
2454 | if (len) { | |
2455 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2456 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2457 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2458 | } |
2459 | ||
6440adb5 | 2460 | /* Tell 4965 about any 2-byte padding after MAC header */ |
b481de9c ZY |
2461 | if (len_org) |
2462 | out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
2463 | ||
6440adb5 | 2464 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2465 | len = (u16)skb->len; |
2466 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2467 | ||
2468 | /* TODO need this for burst mode later on */ | |
bb8c093b | 2469 | iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id); |
b481de9c ZY |
2470 | |
2471 | /* set is_hcca to 0; it probably will never be implemented */ | |
bb8c093b | 2472 | iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0); |
b481de9c | 2473 | |
19758bef TW |
2474 | iwl_update_tx_stats(priv, fc, len); |
2475 | ||
857485c0 | 2476 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
87e4f7df TW |
2477 | offsetof(struct iwl4965_tx_cmd, scratch); |
2478 | out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
2479 | out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); | |
2480 | ||
b481de9c ZY |
2481 | if (!ieee80211_get_morefrag(hdr)) { |
2482 | txq->need_update = 1; | |
2483 | if (qc) { | |
2484 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2485 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
2486 | } | |
2487 | } else { | |
2488 | wait_write_ptr = 1; | |
2489 | txq->need_update = 0; | |
2490 | } | |
2491 | ||
0a6857e7 | 2492 | iwl_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2493 | sizeof(out_cmd->cmd.tx)); |
2494 | ||
0a6857e7 | 2495 | iwl_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
b481de9c ZY |
2496 | ieee80211_get_hdrlen(fc)); |
2497 | ||
6440adb5 | 2498 | /* Set up entry for this TFD in Tx byte-count array */ |
b481de9c ZY |
2499 | iwl4965_tx_queue_update_wr_ptr(priv, txq, len); |
2500 | ||
6440adb5 | 2501 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2502 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 2503 | rc = iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2504 | spin_unlock_irqrestore(&priv->lock, flags); |
2505 | ||
2506 | if (rc) | |
2507 | return rc; | |
2508 | ||
bb8c093b | 2509 | if ((iwl4965_queue_space(q) < q->high_mark) |
b481de9c ZY |
2510 | && priv->mac80211_registered) { |
2511 | if (wait_write_ptr) { | |
2512 | spin_lock_irqsave(&priv->lock, flags); | |
2513 | txq->need_update = 1; | |
bb8c093b | 2514 | iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2515 | spin_unlock_irqrestore(&priv->lock, flags); |
2516 | } | |
2517 | ||
2518 | ieee80211_stop_queue(priv->hw, ctl->queue); | |
2519 | } | |
2520 | ||
2521 | return 0; | |
2522 | ||
2523 | drop_unlock: | |
2524 | spin_unlock_irqrestore(&priv->lock, flags); | |
2525 | drop: | |
2526 | return -1; | |
2527 | } | |
2528 | ||
c79dd5b5 | 2529 | static void iwl4965_set_rate(struct iwl_priv *priv) |
b481de9c | 2530 | { |
8318d78a | 2531 | const struct ieee80211_supported_band *hw = NULL; |
b481de9c ZY |
2532 | struct ieee80211_rate *rate; |
2533 | int i; | |
2534 | ||
8318d78a | 2535 | hw = iwl4965_get_hw_mode(priv, priv->band); |
c4ba9621 SA |
2536 | if (!hw) { |
2537 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); | |
2538 | return; | |
2539 | } | |
b481de9c ZY |
2540 | |
2541 | priv->active_rate = 0; | |
2542 | priv->active_rate_basic = 0; | |
2543 | ||
8318d78a JB |
2544 | for (i = 0; i < hw->n_bitrates; i++) { |
2545 | rate = &(hw->bitrates[i]); | |
2546 | if (rate->hw_value < IWL_RATE_COUNT) | |
2547 | priv->active_rate |= (1 << rate->hw_value); | |
b481de9c ZY |
2548 | } |
2549 | ||
2550 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2551 | priv->active_rate, priv->active_rate_basic); | |
2552 | ||
2553 | /* | |
2554 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2555 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2556 | * OFDM | |
2557 | */ | |
2558 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
2559 | priv->staging_rxon.cck_basic_rates = | |
2560 | ((priv->active_rate_basic & | |
2561 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2562 | else | |
2563 | priv->staging_rxon.cck_basic_rates = | |
2564 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2565 | ||
2566 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
2567 | priv->staging_rxon.ofdm_basic_rates = | |
2568 | ((priv->active_rate_basic & | |
2569 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2570 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2571 | else | |
2572 | priv->staging_rxon.ofdm_basic_rates = | |
2573 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2574 | } | |
2575 | ||
ad97edd2 | 2576 | void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio) |
b481de9c ZY |
2577 | { |
2578 | unsigned long flags; | |
2579 | ||
2580 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2581 | return; | |
2582 | ||
2583 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2584 | disable_radio ? "OFF" : "ON"); | |
2585 | ||
2586 | if (disable_radio) { | |
bb8c093b | 2587 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
2588 | /* FIXME: This is a workaround for AP */ |
2589 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
2590 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 2591 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2592 | CSR_UCODE_SW_BIT_RFKILL); |
2593 | spin_unlock_irqrestore(&priv->lock, flags); | |
ad97edd2 MA |
2594 | /* call the host command only if no hw rf-kill set */ |
2595 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2596 | iwl4965_send_card_state(priv, | |
2597 | CARD_STATE_CMD_DISABLE, | |
2598 | 0); | |
b481de9c | 2599 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
ad97edd2 MA |
2600 | |
2601 | /* make sure mac80211 stop sending Tx frame */ | |
2602 | if (priv->mac80211_registered) | |
2603 | ieee80211_stop_queues(priv->hw); | |
b481de9c ZY |
2604 | } |
2605 | return; | |
2606 | } | |
2607 | ||
2608 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 2609 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2610 | |
2611 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2612 | spin_unlock_irqrestore(&priv->lock, flags); | |
2613 | ||
2614 | /* wake up ucode */ | |
2615 | msleep(10); | |
2616 | ||
2617 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
2618 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
2619 | if (!iwl_grab_nic_access(priv)) | |
2620 | iwl_release_nic_access(priv); | |
b481de9c ZY |
2621 | spin_unlock_irqrestore(&priv->lock, flags); |
2622 | ||
2623 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2624 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2625 | "disabled by HW switch\n"); | |
2626 | return; | |
2627 | } | |
2628 | ||
2629 | queue_work(priv->workqueue, &priv->restart); | |
2630 | return; | |
2631 | } | |
2632 | ||
c79dd5b5 | 2633 | void iwl4965_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2634 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2635 | { | |
2636 | u16 fc = | |
2637 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2638 | ||
2639 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
2640 | return; | |
2641 | ||
2642 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2643 | return; | |
2644 | ||
2645 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2646 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2647 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
17e476b8 EG |
2648 | /* The uCode has got a bad phase 1 Key, pushes the packet. |
2649 | * Decryption will be done in SW. */ | |
2650 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2651 | RX_RES_STATUS_BAD_KEY_TTAK) | |
2652 | break; | |
2653 | ||
b481de9c ZY |
2654 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == |
2655 | RX_RES_STATUS_BAD_ICV_MIC) | |
2656 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2657 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2658 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2659 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2660 | RX_RES_STATUS_DECRYPT_OK) { | |
2661 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2662 | stats->flag |= RX_FLAG_DECRYPTED; | |
2663 | } | |
2664 | break; | |
2665 | ||
2666 | default: | |
2667 | break; | |
2668 | } | |
2669 | } | |
2670 | ||
b481de9c ZY |
2671 | |
2672 | #define IWL_PACKET_RETRY_TIME HZ | |
2673 | ||
c79dd5b5 | 2674 | int iwl4965_is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2675 | { |
2676 | u16 sc = le16_to_cpu(header->seq_ctrl); | |
2677 | u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4; | |
2678 | u16 frag = sc & IEEE80211_SCTL_FRAG; | |
2679 | u16 *last_seq, *last_frag; | |
2680 | unsigned long *last_time; | |
2681 | ||
2682 | switch (priv->iw_mode) { | |
2683 | case IEEE80211_IF_TYPE_IBSS:{ | |
2684 | struct list_head *p; | |
bb8c093b | 2685 | struct iwl4965_ibss_seq *entry = NULL; |
b481de9c ZY |
2686 | u8 *mac = header->addr2; |
2687 | int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1); | |
2688 | ||
2689 | __list_for_each(p, &priv->ibss_mac_hash[index]) { | |
bb8c093b | 2690 | entry = list_entry(p, struct iwl4965_ibss_seq, list); |
b481de9c ZY |
2691 | if (!compare_ether_addr(entry->mac, mac)) |
2692 | break; | |
2693 | } | |
2694 | if (p == &priv->ibss_mac_hash[index]) { | |
2695 | entry = kzalloc(sizeof(*entry), GFP_ATOMIC); | |
2696 | if (!entry) { | |
bc434dd2 | 2697 | IWL_ERROR("Cannot malloc new mac entry\n"); |
b481de9c ZY |
2698 | return 0; |
2699 | } | |
2700 | memcpy(entry->mac, mac, ETH_ALEN); | |
2701 | entry->seq_num = seq; | |
2702 | entry->frag_num = frag; | |
2703 | entry->packet_time = jiffies; | |
bc434dd2 | 2704 | list_add(&entry->list, &priv->ibss_mac_hash[index]); |
b481de9c ZY |
2705 | return 0; |
2706 | } | |
2707 | last_seq = &entry->seq_num; | |
2708 | last_frag = &entry->frag_num; | |
2709 | last_time = &entry->packet_time; | |
2710 | break; | |
2711 | } | |
2712 | case IEEE80211_IF_TYPE_STA: | |
2713 | last_seq = &priv->last_seq_num; | |
2714 | last_frag = &priv->last_frag_num; | |
2715 | last_time = &priv->last_packet_time; | |
2716 | break; | |
2717 | default: | |
2718 | return 0; | |
2719 | } | |
2720 | if ((*last_seq == seq) && | |
2721 | time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) { | |
2722 | if (*last_frag == frag) | |
2723 | goto drop; | |
2724 | if (*last_frag + 1 != frag) | |
2725 | /* out-of-order fragment */ | |
2726 | goto drop; | |
2727 | } else | |
2728 | *last_seq = seq; | |
2729 | ||
2730 | *last_frag = frag; | |
2731 | *last_time = jiffies; | |
2732 | return 0; | |
2733 | ||
2734 | drop: | |
2735 | return 1; | |
2736 | } | |
2737 | ||
c8b0e6e1 | 2738 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2739 | |
2740 | #include "iwl-spectrum.h" | |
2741 | ||
2742 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2743 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2744 | #define TIME_UNIT 1024 | |
2745 | ||
2746 | /* | |
2747 | * extended beacon time format | |
2748 | * time in usec will be changed into a 32-bit value in 8:24 format | |
2749 | * the high 1 byte is the beacon counts | |
2750 | * the lower 3 bytes is the time in usec within one beacon interval | |
2751 | */ | |
2752 | ||
bb8c093b | 2753 | static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
2754 | { |
2755 | u32 quot; | |
2756 | u32 rem; | |
2757 | u32 interval = beacon_interval * 1024; | |
2758 | ||
2759 | if (!interval || !usec) | |
2760 | return 0; | |
2761 | ||
2762 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
2763 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
2764 | ||
2765 | return (quot << 24) + rem; | |
2766 | } | |
2767 | ||
2768 | /* base is usually what we get from ucode with each received frame, | |
2769 | * the same as HW timer counter counting down | |
2770 | */ | |
2771 | ||
bb8c093b | 2772 | static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
2773 | { |
2774 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
2775 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
2776 | u32 interval = beacon_interval * TIME_UNIT; | |
2777 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
2778 | (addon & BEACON_TIME_MASK_HIGH); | |
2779 | ||
2780 | if (base_low > addon_low) | |
2781 | res += base_low - addon_low; | |
2782 | else if (base_low < addon_low) { | |
2783 | res += interval + base_low - addon_low; | |
2784 | res += (1 << 24); | |
2785 | } else | |
2786 | res += (1 << 24); | |
2787 | ||
2788 | return cpu_to_le32(res); | |
2789 | } | |
2790 | ||
c79dd5b5 | 2791 | static int iwl4965_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
2792 | struct ieee80211_measurement_params *params, |
2793 | u8 type) | |
2794 | { | |
bb8c093b CH |
2795 | struct iwl4965_spectrum_cmd spectrum; |
2796 | struct iwl4965_rx_packet *res; | |
857485c0 | 2797 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
2798 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
2799 | .data = (void *)&spectrum, | |
2800 | .meta.flags = CMD_WANT_SKB, | |
2801 | }; | |
2802 | u32 add_time = le64_to_cpu(params->start_time); | |
2803 | int rc; | |
2804 | int spectrum_resp_status; | |
2805 | int duration = le16_to_cpu(params->duration); | |
2806 | ||
3109ece1 | 2807 | if (iwl_is_associated(priv)) |
b481de9c | 2808 | add_time = |
bb8c093b | 2809 | iwl4965_usecs_to_beacons( |
b481de9c ZY |
2810 | le64_to_cpu(params->start_time) - priv->last_tsf, |
2811 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2812 | ||
2813 | memset(&spectrum, 0, sizeof(spectrum)); | |
2814 | ||
2815 | spectrum.channel_count = cpu_to_le16(1); | |
2816 | spectrum.flags = | |
2817 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
2818 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
2819 | cmd.len = sizeof(spectrum); | |
2820 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
2821 | ||
3109ece1 | 2822 | if (iwl_is_associated(priv)) |
b481de9c | 2823 | spectrum.start_time = |
bb8c093b | 2824 | iwl4965_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
2825 | add_time, |
2826 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2827 | else | |
2828 | spectrum.start_time = 0; | |
2829 | ||
2830 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
2831 | spectrum.channels[0].channel = params->channel; | |
2832 | spectrum.channels[0].type = type; | |
2833 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
2834 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
2835 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
2836 | ||
857485c0 | 2837 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2838 | if (rc) |
2839 | return rc; | |
2840 | ||
bb8c093b | 2841 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
2842 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
2843 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
2844 | rc = -EIO; | |
2845 | } | |
2846 | ||
2847 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
2848 | switch (spectrum_resp_status) { | |
2849 | case 0: /* Command will be handled */ | |
2850 | if (res->u.spectrum.id != 0xff) { | |
2851 | IWL_DEBUG_INFO | |
2852 | ("Replaced existing measurement: %d\n", | |
2853 | res->u.spectrum.id); | |
2854 | priv->measurement_status &= ~MEASUREMENT_READY; | |
2855 | } | |
2856 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
2857 | rc = 0; | |
2858 | break; | |
2859 | ||
2860 | case 1: /* Command will not be handled */ | |
2861 | rc = -EAGAIN; | |
2862 | break; | |
2863 | } | |
2864 | ||
2865 | dev_kfree_skb_any(cmd.meta.u.skb); | |
2866 | ||
2867 | return rc; | |
2868 | } | |
2869 | #endif | |
2870 | ||
c79dd5b5 | 2871 | static void iwl4965_txstatus_to_ieee(struct iwl_priv *priv, |
bb8c093b | 2872 | struct iwl4965_tx_info *tx_sta) |
b481de9c ZY |
2873 | { |
2874 | ||
2875 | tx_sta->status.ack_signal = 0; | |
2876 | tx_sta->status.excessive_retries = 0; | |
2877 | tx_sta->status.queue_length = 0; | |
2878 | tx_sta->status.queue_number = 0; | |
2879 | ||
2880 | if (in_interrupt()) | |
2881 | ieee80211_tx_status_irqsafe(priv->hw, | |
2882 | tx_sta->skb[0], &(tx_sta->status)); | |
2883 | else | |
2884 | ieee80211_tx_status(priv->hw, | |
2885 | tx_sta->skb[0], &(tx_sta->status)); | |
2886 | ||
2887 | tx_sta->skb[0] = NULL; | |
2888 | } | |
2889 | ||
2890 | /** | |
6440adb5 | 2891 | * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd |
b481de9c | 2892 | * |
6440adb5 BC |
2893 | * When FW advances 'R' index, all entries between old and new 'R' index |
2894 | * need to be reclaimed. As result, some free space forms. If there is | |
2895 | * enough free space (> low mark), wake the stack that feeds us. | |
b481de9c | 2896 | */ |
c79dd5b5 | 2897 | int iwl4965_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
b481de9c | 2898 | { |
bb8c093b CH |
2899 | struct iwl4965_tx_queue *txq = &priv->txq[txq_id]; |
2900 | struct iwl4965_queue *q = &txq->q; | |
b481de9c ZY |
2901 | int nfreed = 0; |
2902 | ||
2903 | if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) { | |
2904 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
2905 | "is out of range [0-%d] %d %d.\n", txq_id, | |
fc4b6853 | 2906 | index, q->n_bd, q->write_ptr, q->read_ptr); |
b481de9c ZY |
2907 | return 0; |
2908 | } | |
2909 | ||
c54b679d | 2910 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
fc4b6853 | 2911 | q->read_ptr != index; |
c54b679d | 2912 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
b481de9c | 2913 | if (txq_id != IWL_CMD_QUEUE_NUM) { |
bb8c093b | 2914 | iwl4965_txstatus_to_ieee(priv, |
fc4b6853 | 2915 | &(txq->txb[txq->q.read_ptr])); |
bb8c093b | 2916 | iwl4965_hw_txq_free_tfd(priv, txq); |
b481de9c ZY |
2917 | } else if (nfreed > 1) { |
2918 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
fc4b6853 | 2919 | q->write_ptr, q->read_ptr); |
b481de9c ZY |
2920 | queue_work(priv->workqueue, &priv->restart); |
2921 | } | |
2922 | nfreed++; | |
2923 | } | |
2924 | ||
fe01b477 | 2925 | /* if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) && |
b481de9c ZY |
2926 | (txq_id != IWL_CMD_QUEUE_NUM) && |
2927 | priv->mac80211_registered) | |
fe01b477 | 2928 | ieee80211_wake_queue(priv->hw, txq_id); */ |
b481de9c ZY |
2929 | |
2930 | ||
2931 | return nfreed; | |
2932 | } | |
2933 | ||
bb8c093b | 2934 | static int iwl4965_is_tx_success(u32 status) |
b481de9c ZY |
2935 | { |
2936 | status &= TX_STATUS_MSK; | |
2937 | return (status == TX_STATUS_SUCCESS) | |
2938 | || (status == TX_STATUS_DIRECT_DONE); | |
2939 | } | |
2940 | ||
2941 | /****************************************************************************** | |
2942 | * | |
2943 | * Generic RX handler implementations | |
2944 | * | |
2945 | ******************************************************************************/ | |
c8b0e6e1 | 2946 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 2947 | |
c79dd5b5 | 2948 | static inline int iwl4965_get_ra_sta_id(struct iwl_priv *priv, |
b481de9c ZY |
2949 | struct ieee80211_hdr *hdr) |
2950 | { | |
2951 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) | |
2952 | return IWL_AP_ID; | |
2953 | else { | |
2954 | u8 *da = ieee80211_get_DA(hdr); | |
bb8c093b | 2955 | return iwl4965_hw_find_station(priv, da); |
b481de9c ZY |
2956 | } |
2957 | } | |
2958 | ||
bb8c093b | 2959 | static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr( |
c79dd5b5 | 2960 | struct iwl_priv *priv, int txq_id, int idx) |
b481de9c ZY |
2961 | { |
2962 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
2963 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
2964 | txb[idx].skb[0]->data; | |
2965 | return NULL; | |
2966 | } | |
2967 | ||
bb8c093b | 2968 | static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp) |
b481de9c ZY |
2969 | { |
2970 | __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status + | |
2971 | tx_resp->frame_count); | |
2972 | return le32_to_cpu(*scd_ssn) & MAX_SN; | |
2973 | ||
2974 | } | |
6440adb5 BC |
2975 | |
2976 | /** | |
2977 | * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue | |
2978 | */ | |
c79dd5b5 | 2979 | static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv, |
bb8c093b | 2980 | struct iwl4965_ht_agg *agg, |
fe01b477 | 2981 | struct iwl4965_tx_resp_agg *tx_resp, |
b481de9c ZY |
2982 | u16 start_idx) |
2983 | { | |
fe01b477 RR |
2984 | u16 status; |
2985 | struct agg_tx_status *frame_status = &tx_resp->status; | |
b481de9c ZY |
2986 | struct ieee80211_tx_status *tx_status = NULL; |
2987 | struct ieee80211_hdr *hdr = NULL; | |
2988 | int i, sh; | |
2989 | int txq_id, idx; | |
2990 | u16 seq; | |
2991 | ||
2992 | if (agg->wait_for_ba) | |
6440adb5 | 2993 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); |
b481de9c ZY |
2994 | |
2995 | agg->frame_count = tx_resp->frame_count; | |
2996 | agg->start_idx = start_idx; | |
2997 | agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
fe01b477 | 2998 | agg->bitmap = 0; |
b481de9c | 2999 | |
6440adb5 | 3000 | /* # frames attempted by Tx command */ |
b481de9c | 3001 | if (agg->frame_count == 1) { |
6440adb5 | 3002 | /* Only one frame was attempted; no block-ack will arrive */ |
fe01b477 RR |
3003 | status = le16_to_cpu(frame_status[0].status); |
3004 | seq = le16_to_cpu(frame_status[0].sequence); | |
3005 | idx = SEQ_TO_INDEX(seq); | |
3006 | txq_id = SEQ_TO_QUEUE(seq); | |
b481de9c | 3007 | |
b481de9c | 3008 | /* FIXME: code repetition */ |
fe01b477 RR |
3009 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", |
3010 | agg->frame_count, agg->start_idx, idx); | |
b481de9c | 3011 | |
fe01b477 | 3012 | tx_status = &(priv->txq[txq_id].txb[idx].status); |
b481de9c ZY |
3013 | tx_status->retry_count = tx_resp->failure_frame; |
3014 | tx_status->queue_number = status & 0xff; | |
fe01b477 RR |
3015 | tx_status->queue_length = tx_resp->failure_rts; |
3016 | tx_status->control.flags &= ~IEEE80211_TXCTL_AMPDU; | |
bb8c093b | 3017 | tx_status->flags = iwl4965_is_tx_success(status)? |
b481de9c | 3018 | IEEE80211_TX_STATUS_ACK : 0; |
4c424e4c RR |
3019 | iwl4965_hwrate_to_tx_control(priv, |
3020 | le32_to_cpu(tx_resp->rate_n_flags), | |
3021 | &tx_status->control); | |
b481de9c ZY |
3022 | /* FIXME: code repetition end */ |
3023 | ||
3024 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
3025 | status & 0xff, tx_resp->failure_frame); | |
3026 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", | |
bb8c093b | 3027 | iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags)); |
b481de9c ZY |
3028 | |
3029 | agg->wait_for_ba = 0; | |
3030 | } else { | |
6440adb5 | 3031 | /* Two or more frames were attempted; expect block-ack */ |
b481de9c ZY |
3032 | u64 bitmap = 0; |
3033 | int start = agg->start_idx; | |
3034 | ||
6440adb5 | 3035 | /* Construct bit-map of pending frames within Tx window */ |
b481de9c ZY |
3036 | for (i = 0; i < agg->frame_count; i++) { |
3037 | u16 sc; | |
fe01b477 RR |
3038 | status = le16_to_cpu(frame_status[i].status); |
3039 | seq = le16_to_cpu(frame_status[i].sequence); | |
b481de9c ZY |
3040 | idx = SEQ_TO_INDEX(seq); |
3041 | txq_id = SEQ_TO_QUEUE(seq); | |
3042 | ||
3043 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
3044 | AGG_TX_STATE_ABORT_MSK)) | |
3045 | continue; | |
3046 | ||
3047 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
3048 | agg->frame_count, txq_id, idx); | |
3049 | ||
bb8c093b | 3050 | hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx); |
b481de9c ZY |
3051 | |
3052 | sc = le16_to_cpu(hdr->seq_ctrl); | |
3053 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
3054 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
3055 | " idx=%d, seq_idx=%d, seq=%d\n", | |
3056 | idx, SEQ_TO_SN(sc), | |
3057 | hdr->seq_ctrl); | |
3058 | return -1; | |
3059 | } | |
3060 | ||
3061 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
3062 | i, idx, SEQ_TO_SN(sc)); | |
3063 | ||
3064 | sh = idx - start; | |
3065 | if (sh > 64) { | |
3066 | sh = (start - idx) + 0xff; | |
3067 | bitmap = bitmap << sh; | |
3068 | sh = 0; | |
3069 | start = idx; | |
3070 | } else if (sh < -64) | |
3071 | sh = 0xff - (start - idx); | |
3072 | else if (sh < 0) { | |
3073 | sh = start - idx; | |
3074 | start = idx; | |
3075 | bitmap = bitmap << sh; | |
3076 | sh = 0; | |
3077 | } | |
3078 | bitmap |= (1 << sh); | |
3079 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n", | |
3080 | start, (u32)(bitmap & 0xFFFFFFFF)); | |
3081 | } | |
3082 | ||
fe01b477 | 3083 | agg->bitmap = bitmap; |
b481de9c ZY |
3084 | agg->start_idx = start; |
3085 | agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
fe01b477 | 3086 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
b481de9c | 3087 | agg->frame_count, agg->start_idx, |
06501d29 | 3088 | (unsigned long long)agg->bitmap); |
b481de9c ZY |
3089 | |
3090 | if (bitmap) | |
3091 | agg->wait_for_ba = 1; | |
3092 | } | |
3093 | return 0; | |
3094 | } | |
3095 | #endif | |
b481de9c | 3096 | |
6440adb5 BC |
3097 | /** |
3098 | * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response | |
3099 | */ | |
c79dd5b5 | 3100 | static void iwl4965_rx_reply_tx(struct iwl_priv *priv, |
bb8c093b | 3101 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3102 | { |
bb8c093b | 3103 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3104 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3105 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3106 | int index = SEQ_TO_INDEX(sequence); | |
bb8c093b | 3107 | struct iwl4965_tx_queue *txq = &priv->txq[txq_id]; |
b481de9c | 3108 | struct ieee80211_tx_status *tx_status; |
bb8c093b | 3109 | struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
b481de9c | 3110 | u32 status = le32_to_cpu(tx_resp->status); |
c8b0e6e1 | 3111 | #ifdef CONFIG_IWL4965_HT |
fe01b477 RR |
3112 | int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; |
3113 | struct ieee80211_hdr *hdr; | |
3114 | __le16 *qc; | |
b481de9c ZY |
3115 | #endif |
3116 | ||
3117 | if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) { | |
3118 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
3119 | "is out of range [0-%d] %d %d\n", txq_id, | |
fc4b6853 TW |
3120 | index, txq->q.n_bd, txq->q.write_ptr, |
3121 | txq->q.read_ptr); | |
b481de9c ZY |
3122 | return; |
3123 | } | |
3124 | ||
c8b0e6e1 | 3125 | #ifdef CONFIG_IWL4965_HT |
fe01b477 RR |
3126 | hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, index); |
3127 | qc = ieee80211_get_qos_ctrl(hdr); | |
3128 | ||
3129 | if (qc) | |
3130 | tid = le16_to_cpu(*qc) & 0xf; | |
3131 | ||
3132 | sta_id = iwl4965_get_ra_sta_id(priv, hdr); | |
3133 | if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { | |
3134 | IWL_ERROR("Station not known\n"); | |
3135 | return; | |
3136 | } | |
3137 | ||
b481de9c | 3138 | if (txq->sched_retry) { |
bb8c093b | 3139 | const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp); |
bb8c093b | 3140 | struct iwl4965_ht_agg *agg = NULL; |
b481de9c | 3141 | |
fe01b477 | 3142 | if (!qc) |
b481de9c | 3143 | return; |
b481de9c ZY |
3144 | |
3145 | agg = &priv->stations[sta_id].tid[tid].agg; | |
3146 | ||
fe01b477 RR |
3147 | iwl4965_tx_status_reply_tx(priv, agg, |
3148 | (struct iwl4965_tx_resp_agg *)tx_resp, index); | |
b481de9c ZY |
3149 | |
3150 | if ((tx_resp->frame_count == 1) && | |
bb8c093b | 3151 | !iwl4965_is_tx_success(status)) { |
b481de9c ZY |
3152 | /* TODO: send BAR */ |
3153 | } | |
3154 | ||
fe01b477 RR |
3155 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { |
3156 | int freed; | |
c54b679d | 3157 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
b481de9c ZY |
3158 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " |
3159 | "%d index %d\n", scd_ssn , index); | |
fe01b477 RR |
3160 | freed = iwl4965_tx_queue_reclaim(priv, txq_id, index); |
3161 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
3162 | ||
3163 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
3164 | txq_id >= 0 && priv->mac80211_registered && | |
3165 | agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) | |
3166 | ieee80211_wake_queue(priv->hw, txq_id); | |
3167 | ||
3168 | iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id); | |
b481de9c ZY |
3169 | } |
3170 | } else { | |
c8b0e6e1 | 3171 | #endif /* CONFIG_IWL4965_HT */ |
fc4b6853 | 3172 | tx_status = &(txq->txb[txq->q.read_ptr].status); |
b481de9c ZY |
3173 | |
3174 | tx_status->retry_count = tx_resp->failure_frame; | |
3175 | tx_status->queue_number = status; | |
3176 | tx_status->queue_length = tx_resp->bt_kill_count; | |
3177 | tx_status->queue_length |= tx_resp->failure_rts; | |
b481de9c | 3178 | tx_status->flags = |
bb8c093b | 3179 | iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0; |
4c424e4c RR |
3180 | iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags), |
3181 | &tx_status->control); | |
b481de9c | 3182 | |
b481de9c | 3183 | IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x " |
bb8c093b | 3184 | "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status), |
b481de9c ZY |
3185 | status, le32_to_cpu(tx_resp->rate_n_flags), |
3186 | tx_resp->failure_frame); | |
3187 | ||
3188 | IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); | |
fe01b477 RR |
3189 | if (index != -1) { |
3190 | int freed = iwl4965_tx_queue_reclaim(priv, txq_id, index); | |
3191 | #ifdef CONFIG_IWL4965_HT | |
3192 | if (tid != MAX_TID_COUNT) | |
3193 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
3194 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
3195 | (txq_id >= 0) && | |
3196 | priv->mac80211_registered) | |
3197 | ieee80211_wake_queue(priv->hw, txq_id); | |
3198 | if (tid != MAX_TID_COUNT) | |
3199 | iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id); | |
3200 | #endif | |
3201 | } | |
c8b0e6e1 | 3202 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 3203 | } |
c8b0e6e1 | 3204 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
3205 | |
3206 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) | |
3207 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
3208 | } | |
3209 | ||
3210 | ||
c79dd5b5 | 3211 | static void iwl4965_rx_reply_alive(struct iwl_priv *priv, |
bb8c093b | 3212 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3213 | { |
bb8c093b CH |
3214 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3215 | struct iwl4965_alive_resp *palive; | |
b481de9c ZY |
3216 | struct delayed_work *pwork; |
3217 | ||
3218 | palive = &pkt->u.alive_frame; | |
3219 | ||
3220 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
3221 | "0x%01X 0x%01X\n", | |
3222 | palive->is_valid, palive->ver_type, | |
3223 | palive->ver_subtype); | |
3224 | ||
3225 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
3226 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3227 | memcpy(&priv->card_alive_init, | |
3228 | &pkt->u.alive_frame, | |
bb8c093b | 3229 | sizeof(struct iwl4965_init_alive_resp)); |
b481de9c ZY |
3230 | pwork = &priv->init_alive_start; |
3231 | } else { | |
3232 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
3233 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
bb8c093b | 3234 | sizeof(struct iwl4965_alive_resp)); |
b481de9c ZY |
3235 | pwork = &priv->alive_start; |
3236 | } | |
3237 | ||
3238 | /* We delay the ALIVE response by 5ms to | |
3239 | * give the HW RF Kill time to activate... */ | |
3240 | if (palive->is_valid == UCODE_VALID_OK) | |
3241 | queue_delayed_work(priv->workqueue, pwork, | |
3242 | msecs_to_jiffies(5)); | |
3243 | else | |
3244 | IWL_WARNING("uCode did not respond OK.\n"); | |
3245 | } | |
3246 | ||
c79dd5b5 | 3247 | static void iwl4965_rx_reply_add_sta(struct iwl_priv *priv, |
bb8c093b | 3248 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3249 | { |
bb8c093b | 3250 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3251 | |
3252 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
3253 | return; | |
3254 | } | |
3255 | ||
c79dd5b5 | 3256 | static void iwl4965_rx_reply_error(struct iwl_priv *priv, |
bb8c093b | 3257 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3258 | { |
bb8c093b | 3259 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3260 | |
3261 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
3262 | "seq 0x%04X ser 0x%08X\n", | |
3263 | le32_to_cpu(pkt->u.err_resp.error_type), | |
3264 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
3265 | pkt->u.err_resp.cmd_id, | |
3266 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
3267 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
3268 | } | |
3269 | ||
3270 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
3271 | ||
c79dd5b5 | 3272 | static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3273 | { |
bb8c093b CH |
3274 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3275 | struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
3276 | struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif); | |
b481de9c ZY |
3277 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
3278 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
3279 | rxon->channel = csa->channel; | |
3280 | priv->staging_rxon.channel = csa->channel; | |
3281 | } | |
3282 | ||
c79dd5b5 | 3283 | static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv, |
bb8c093b | 3284 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3285 | { |
c8b0e6e1 | 3286 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
bb8c093b CH |
3287 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3288 | struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
b481de9c ZY |
3289 | |
3290 | if (!report->state) { | |
3291 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
3292 | "Spectrum Measure Notification: Start\n"); | |
3293 | return; | |
3294 | } | |
3295 | ||
3296 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
3297 | priv->measurement_status |= MEASUREMENT_READY; | |
3298 | #endif | |
3299 | } | |
3300 | ||
c79dd5b5 | 3301 | static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv, |
bb8c093b | 3302 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3303 | { |
0a6857e7 | 3304 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3305 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3306 | struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
b481de9c ZY |
3307 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
3308 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
3309 | #endif | |
3310 | } | |
3311 | ||
c79dd5b5 | 3312 | static void iwl4965_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
bb8c093b | 3313 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3314 | { |
bb8c093b | 3315 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3316 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
3317 | "notification for %s:\n", | |
3318 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
0a6857e7 | 3319 | iwl_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
3320 | } |
3321 | ||
bb8c093b | 3322 | static void iwl4965_bg_beacon_update(struct work_struct *work) |
b481de9c | 3323 | { |
c79dd5b5 TW |
3324 | struct iwl_priv *priv = |
3325 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
3326 | struct sk_buff *beacon; |
3327 | ||
3328 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
32bfd35d | 3329 | beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); |
b481de9c ZY |
3330 | |
3331 | if (!beacon) { | |
3332 | IWL_ERROR("update beacon failed\n"); | |
3333 | return; | |
3334 | } | |
3335 | ||
3336 | mutex_lock(&priv->mutex); | |
3337 | /* new beacon skb is allocated every time; dispose previous.*/ | |
3338 | if (priv->ibss_beacon) | |
3339 | dev_kfree_skb(priv->ibss_beacon); | |
3340 | ||
3341 | priv->ibss_beacon = beacon; | |
3342 | mutex_unlock(&priv->mutex); | |
3343 | ||
bb8c093b | 3344 | iwl4965_send_beacon_cmd(priv); |
b481de9c ZY |
3345 | } |
3346 | ||
c79dd5b5 | 3347 | static void iwl4965_rx_beacon_notif(struct iwl_priv *priv, |
bb8c093b | 3348 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3349 | { |
0a6857e7 | 3350 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3351 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3352 | struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status); | |
3353 | u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); | |
b481de9c ZY |
3354 | |
3355 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3356 | "tsf %d %d rate %d\n", | |
3357 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3358 | beacon->beacon_notify_hdr.failure_frame, | |
3359 | le32_to_cpu(beacon->ibss_mgr_status), | |
3360 | le32_to_cpu(beacon->high_tsf), | |
3361 | le32_to_cpu(beacon->low_tsf), rate); | |
3362 | #endif | |
3363 | ||
3364 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && | |
3365 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) | |
3366 | queue_work(priv->workqueue, &priv->beacon_update); | |
3367 | } | |
3368 | ||
3369 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
c79dd5b5 | 3370 | static void iwl4965_rx_reply_scan(struct iwl_priv *priv, |
bb8c093b | 3371 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3372 | { |
0a6857e7 | 3373 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3374 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3375 | struct iwl4965_scanreq_notification *notif = | |
3376 | (struct iwl4965_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3377 | |
3378 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3379 | #endif | |
3380 | } | |
3381 | ||
3382 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
c79dd5b5 | 3383 | static void iwl4965_rx_scan_start_notif(struct iwl_priv *priv, |
bb8c093b | 3384 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3385 | { |
bb8c093b CH |
3386 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3387 | struct iwl4965_scanstart_notification *notif = | |
3388 | (struct iwl4965_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3389 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3390 | IWL_DEBUG_SCAN("Scan start: " | |
3391 | "%d [802.11%s] " | |
3392 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3393 | notif->channel, | |
3394 | notif->band ? "bg" : "a", | |
3395 | notif->tsf_high, | |
3396 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3397 | } | |
3398 | ||
3399 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
c79dd5b5 | 3400 | static void iwl4965_rx_scan_results_notif(struct iwl_priv *priv, |
bb8c093b | 3401 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3402 | { |
bb8c093b CH |
3403 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3404 | struct iwl4965_scanresults_notification *notif = | |
3405 | (struct iwl4965_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3406 | |
3407 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3408 | "%d [802.11%s] " | |
3409 | "(TSF: 0x%08X:%08X) - %d " | |
3410 | "elapsed=%lu usec (%dms since last)\n", | |
3411 | notif->channel, | |
3412 | notif->band ? "bg" : "a", | |
3413 | le32_to_cpu(notif->tsf_high), | |
3414 | le32_to_cpu(notif->tsf_low), | |
3415 | le32_to_cpu(notif->statistics[0]), | |
3416 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3417 | jiffies_to_msecs(elapsed_jiffies | |
3418 | (priv->last_scan_jiffies, jiffies))); | |
3419 | ||
3420 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3421 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3422 | } |
3423 | ||
3424 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
c79dd5b5 | 3425 | static void iwl4965_rx_scan_complete_notif(struct iwl_priv *priv, |
bb8c093b | 3426 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3427 | { |
bb8c093b CH |
3428 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3429 | struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
b481de9c ZY |
3430 | |
3431 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3432 | scan_notif->scanned_channels, | |
3433 | scan_notif->tsf_low, | |
3434 | scan_notif->tsf_high, scan_notif->status); | |
3435 | ||
3436 | /* The HW is no longer scanning */ | |
3437 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3438 | ||
3439 | /* The scan completion notification came in, so kill that timer... */ | |
3440 | cancel_delayed_work(&priv->scan_check); | |
3441 | ||
3442 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
3443 | (priv->scan_bands == 2) ? "2.4" : "5.2", | |
3444 | jiffies_to_msecs(elapsed_jiffies | |
3445 | (priv->scan_pass_start, jiffies))); | |
3446 | ||
3447 | /* Remove this scanned band from the list | |
3448 | * of pending bands to scan */ | |
3449 | priv->scan_bands--; | |
3450 | ||
3451 | /* If a request to abort was given, or the scan did not succeed | |
3452 | * then we reset the scan state machine and terminate, | |
3453 | * re-queuing another scan if one has been requested */ | |
3454 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3455 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3456 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3457 | } else { | |
3458 | /* If there are more bands on this scan pass reschedule */ | |
3459 | if (priv->scan_bands > 0) | |
3460 | goto reschedule; | |
3461 | } | |
3462 | ||
3463 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3464 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3465 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3466 | ||
3467 | clear_bit(STATUS_SCANNING, &priv->status); | |
3468 | ||
3469 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3470 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3471 | ||
3472 | queue_work(priv->workqueue, &priv->scan_completed); | |
3473 | ||
3474 | return; | |
3475 | ||
3476 | reschedule: | |
3477 | priv->scan_pass_start = jiffies; | |
3478 | queue_work(priv->workqueue, &priv->request_scan); | |
3479 | } | |
3480 | ||
3481 | /* Handle notification from uCode that card's power state is changing | |
3482 | * due to software, hardware, or critical temperature RFKILL */ | |
c79dd5b5 | 3483 | static void iwl4965_rx_card_state_notif(struct iwl_priv *priv, |
bb8c093b | 3484 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3485 | { |
bb8c093b | 3486 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3487 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3488 | unsigned long status = priv->status; | |
3489 | ||
3490 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3491 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3492 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3493 | ||
3494 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3495 | RF_CARD_DISABLED)) { | |
3496 | ||
3395f6e9 | 3497 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3498 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3499 | ||
3395f6e9 TW |
3500 | if (!iwl_grab_nic_access(priv)) { |
3501 | iwl_write_direct32( | |
b481de9c ZY |
3502 | priv, HBUS_TARG_MBX_C, |
3503 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
3504 | ||
3395f6e9 | 3505 | iwl_release_nic_access(priv); |
b481de9c ZY |
3506 | } |
3507 | ||
3508 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 3509 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 3510 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3395f6e9 TW |
3511 | if (!iwl_grab_nic_access(priv)) { |
3512 | iwl_write_direct32( | |
b481de9c ZY |
3513 | priv, HBUS_TARG_MBX_C, |
3514 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
3515 | ||
3395f6e9 | 3516 | iwl_release_nic_access(priv); |
b481de9c ZY |
3517 | } |
3518 | } | |
3519 | ||
3520 | if (flags & RF_CARD_DISABLED) { | |
3395f6e9 | 3521 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c | 3522 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
3395f6e9 TW |
3523 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
3524 | if (!iwl_grab_nic_access(priv)) | |
3525 | iwl_release_nic_access(priv); | |
b481de9c ZY |
3526 | } |
3527 | } | |
3528 | ||
3529 | if (flags & HW_CARD_DISABLED) | |
3530 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3531 | else | |
3532 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3533 | ||
3534 | ||
3535 | if (flags & SW_CARD_DISABLED) | |
3536 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3537 | else | |
3538 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3539 | ||
3540 | if (!(flags & RXON_CARD_DISABLED)) | |
bb8c093b | 3541 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
3542 | |
3543 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3544 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3545 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3546 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3547 | queue_work(priv->workqueue, &priv->rf_kill); | |
3548 | else | |
3549 | wake_up_interruptible(&priv->wait_command_queue); | |
3550 | } | |
3551 | ||
3552 | /** | |
bb8c093b | 3553 | * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3554 | * |
3555 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3556 | * to the host. | |
3557 | * | |
3558 | * This function chains into the hardware specific files for them to setup | |
3559 | * any hardware specific handlers as well. | |
3560 | */ | |
c79dd5b5 | 3561 | static void iwl4965_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 3562 | { |
bb8c093b CH |
3563 | priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive; |
3564 | priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta; | |
3565 | priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error; | |
3566 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa; | |
b481de9c | 3567 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3568 | iwl4965_rx_spectrum_measure_notif; |
3569 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif; | |
b481de9c | 3570 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3571 | iwl4965_rx_pm_debug_statistics_notif; |
3572 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif; | |
b481de9c | 3573 | |
9fbab516 BC |
3574 | /* |
3575 | * The same handler is used for both the REPLY to a discrete | |
3576 | * statistics request from the host as well as for the periodic | |
3577 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3578 | */ |
bb8c093b CH |
3579 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics; |
3580 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics; | |
b481de9c | 3581 | |
bb8c093b CH |
3582 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan; |
3583 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif; | |
b481de9c | 3584 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3585 | iwl4965_rx_scan_results_notif; |
b481de9c | 3586 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3587 | iwl4965_rx_scan_complete_notif; |
3588 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif; | |
3589 | priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx; | |
b481de9c | 3590 | |
9fbab516 | 3591 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3592 | iwl4965_hw_rx_handler_setup(priv); |
b481de9c ZY |
3593 | } |
3594 | ||
3595 | /** | |
bb8c093b | 3596 | * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3597 | * @rxb: Rx buffer to reclaim |
3598 | * | |
3599 | * If an Rx buffer has an async callback associated with it the callback | |
3600 | * will be executed. The attached skb (if present) will only be freed | |
3601 | * if the callback returns 1 | |
3602 | */ | |
c79dd5b5 | 3603 | static void iwl4965_tx_cmd_complete(struct iwl_priv *priv, |
bb8c093b | 3604 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3605 | { |
bb8c093b | 3606 | struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3607 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3608 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3609 | int index = SEQ_TO_INDEX(sequence); | |
3610 | int huge = sequence & SEQ_HUGE_FRAME; | |
3611 | int cmd_index; | |
857485c0 | 3612 | struct iwl_cmd *cmd; |
b481de9c ZY |
3613 | |
3614 | /* If a Tx command is being handled and it isn't in the actual | |
3615 | * command queue then there a command routing bug has been introduced | |
3616 | * in the queue management code. */ | |
3617 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
3618 | IWL_ERROR("Error wrong command queue %d command id 0x%X\n", | |
3619 | txq_id, pkt->hdr.cmd); | |
3620 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); | |
3621 | ||
3622 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
3623 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
3624 | ||
3625 | /* Input error checking is done when commands are added to queue. */ | |
3626 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3627 | cmd->meta.source->u.skb = rxb->skb; | |
3628 | rxb->skb = NULL; | |
3629 | } else if (cmd->meta.u.callback && | |
3630 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3631 | rxb->skb = NULL; | |
3632 | ||
bb8c093b | 3633 | iwl4965_tx_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3634 | |
3635 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3636 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3637 | wake_up_interruptible(&priv->wait_command_queue); | |
3638 | } | |
3639 | } | |
3640 | ||
3641 | /************************** RX-FUNCTIONS ****************************/ | |
3642 | /* | |
3643 | * Rx theory of operation | |
3644 | * | |
9fbab516 BC |
3645 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), |
3646 | * each of which point to Receive Buffers to be filled by 4965. These get | |
3647 | * used not only for Rx frames, but for any command response or notification | |
3648 | * from the 4965. The driver and 4965 manage the Rx buffers by means | |
3649 | * of indexes into the circular buffer. | |
b481de9c ZY |
3650 | * |
3651 | * Rx Queue Indexes | |
3652 | * The host/firmware share two index registers for managing the Rx buffers. | |
3653 | * | |
3654 | * The READ index maps to the first position that the firmware may be writing | |
3655 | * to -- the driver can read up to (but not including) this position and get | |
3656 | * good data. | |
3657 | * The READ index is managed by the firmware once the card is enabled. | |
3658 | * | |
3659 | * The WRITE index maps to the last position the driver has read from -- the | |
3660 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3661 | * | |
3662 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3663 | * WRITE = READ. | |
3664 | * | |
9fbab516 | 3665 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3666 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3667 | * | |
9fbab516 | 3668 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3669 | * and fire the RX interrupt. The driver can then query the READ index and |
3670 | * process as many packets as possible, moving the WRITE index forward as it | |
3671 | * resets the Rx queue buffers with new memory. | |
3672 | * | |
3673 | * The management in the driver is as follows: | |
3674 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3675 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3676 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3677 | * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3678 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3679 | * 'processed' and 'read' driver indexes as well) | |
3680 | * + A received packet is processed and handed to the kernel network stack, | |
3681 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3682 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3683 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3684 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3685 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3686 | * | |
3687 | * | |
3688 | * Driver sequence: | |
3689 | * | |
9fbab516 BC |
3690 | * iwl4965_rx_queue_alloc() Allocates rx_free |
3691 | * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3692 | * iwl4965_rx_queue_restock |
9fbab516 | 3693 | * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3694 | * queue, updates firmware pointers, and updates |
3695 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3696 | * are available, schedules iwl4965_rx_replenish |
b481de9c ZY |
3697 | * |
3698 | * -- enable interrupts -- | |
9fbab516 | 3699 | * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the |
b481de9c ZY |
3700 | * READ INDEX, detaching the SKB from the pool. |
3701 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3702 | * Calls iwl4965_rx_queue_restock to refill any empty |
b481de9c ZY |
3703 | * slots. |
3704 | * ... | |
3705 | * | |
3706 | */ | |
3707 | ||
3708 | /** | |
bb8c093b | 3709 | * iwl4965_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3710 | */ |
bb8c093b | 3711 | static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q) |
b481de9c ZY |
3712 | { |
3713 | int s = q->read - q->write; | |
3714 | if (s <= 0) | |
3715 | s += RX_QUEUE_SIZE; | |
3716 | /* keep some buffer to not confuse full and empty queue */ | |
3717 | s -= 2; | |
3718 | if (s < 0) | |
3719 | s = 0; | |
3720 | return s; | |
3721 | } | |
3722 | ||
3723 | /** | |
bb8c093b | 3724 | * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3725 | */ |
c79dd5b5 | 3726 | int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl4965_rx_queue *q) |
b481de9c ZY |
3727 | { |
3728 | u32 reg = 0; | |
3729 | int rc = 0; | |
3730 | unsigned long flags; | |
3731 | ||
3732 | spin_lock_irqsave(&q->lock, flags); | |
3733 | ||
3734 | if (q->need_update == 0) | |
3735 | goto exit_unlock; | |
3736 | ||
6440adb5 | 3737 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3738 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
3395f6e9 | 3739 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3740 | |
3741 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
3395f6e9 | 3742 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3743 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3744 | goto exit_unlock; | |
3745 | } | |
3746 | ||
3395f6e9 | 3747 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
3748 | if (rc) |
3749 | goto exit_unlock; | |
3750 | ||
6440adb5 | 3751 | /* Device expects a multiple of 8 */ |
3395f6e9 | 3752 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, |
b481de9c | 3753 | q->write & ~0x7); |
3395f6e9 | 3754 | iwl_release_nic_access(priv); |
6440adb5 BC |
3755 | |
3756 | /* Else device is assumed to be awake */ | |
b481de9c | 3757 | } else |
6440adb5 | 3758 | /* Device expects a multiple of 8 */ |
3395f6e9 | 3759 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3760 | |
3761 | ||
3762 | q->need_update = 0; | |
3763 | ||
3764 | exit_unlock: | |
3765 | spin_unlock_irqrestore(&q->lock, flags); | |
3766 | return rc; | |
3767 | } | |
3768 | ||
3769 | /** | |
9fbab516 | 3770 | * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3771 | */ |
c79dd5b5 | 3772 | static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
3773 | dma_addr_t dma_addr) |
3774 | { | |
3775 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
3776 | } | |
3777 | ||
3778 | ||
3779 | /** | |
bb8c093b | 3780 | * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3781 | * |
9fbab516 | 3782 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3783 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3784 | * as we can, pulling from rx_free. |
b481de9c ZY |
3785 | * |
3786 | * This moves the 'write' index forward to catch up with 'processed', and | |
3787 | * also updates the memory address in the firmware to reference the new | |
3788 | * target buffer. | |
3789 | */ | |
c79dd5b5 | 3790 | static int iwl4965_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 3791 | { |
bb8c093b | 3792 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c | 3793 | struct list_head *element; |
bb8c093b | 3794 | struct iwl4965_rx_mem_buffer *rxb; |
b481de9c ZY |
3795 | unsigned long flags; |
3796 | int write, rc; | |
3797 | ||
3798 | spin_lock_irqsave(&rxq->lock, flags); | |
3799 | write = rxq->write & ~0x7; | |
bb8c093b | 3800 | while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3801 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3802 | element = rxq->rx_free.next; |
bb8c093b | 3803 | rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list); |
b481de9c | 3804 | list_del(element); |
6440adb5 BC |
3805 | |
3806 | /* Point to Rx buffer via next RBD in circular buffer */ | |
bb8c093b | 3807 | rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr); |
b481de9c ZY |
3808 | rxq->queue[rxq->write] = rxb; |
3809 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3810 | rxq->free_count--; | |
3811 | } | |
3812 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3813 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3814 | * refill it */ | |
3815 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3816 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3817 | ||
3818 | ||
6440adb5 BC |
3819 | /* If we've added more space for the firmware to place data, tell it. |
3820 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3821 | if ((write != (rxq->write & ~0x7)) |
3822 | || (abs(rxq->write - rxq->read) > 7)) { | |
3823 | spin_lock_irqsave(&rxq->lock, flags); | |
3824 | rxq->need_update = 1; | |
3825 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3826 | rc = iwl4965_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3827 | if (rc) |
3828 | return rc; | |
3829 | } | |
3830 | ||
3831 | return 0; | |
3832 | } | |
3833 | ||
3834 | /** | |
bb8c093b | 3835 | * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3836 | * |
3837 | * When moving to rx_free an SKB is allocated for the slot. | |
3838 | * | |
bb8c093b | 3839 | * Also restock the Rx queue via iwl4965_rx_queue_restock. |
01ebd063 | 3840 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3841 | */ |
c79dd5b5 | 3842 | static void iwl4965_rx_allocate(struct iwl_priv *priv) |
b481de9c | 3843 | { |
bb8c093b | 3844 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c | 3845 | struct list_head *element; |
bb8c093b | 3846 | struct iwl4965_rx_mem_buffer *rxb; |
b481de9c ZY |
3847 | unsigned long flags; |
3848 | spin_lock_irqsave(&rxq->lock, flags); | |
3849 | while (!list_empty(&rxq->rx_used)) { | |
3850 | element = rxq->rx_used.next; | |
bb8c093b | 3851 | rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list); |
6440adb5 BC |
3852 | |
3853 | /* Alloc a new receive buffer */ | |
b481de9c | 3854 | rxb->skb = |
9ee1ba47 RR |
3855 | alloc_skb(priv->hw_setting.rx_buf_size, |
3856 | __GFP_NOWARN | GFP_ATOMIC); | |
b481de9c ZY |
3857 | if (!rxb->skb) { |
3858 | if (net_ratelimit()) | |
3859 | printk(KERN_CRIT DRV_NAME | |
3860 | ": Can not allocate SKB buffers\n"); | |
3861 | /* We don't reschedule replenish work here -- we will | |
3862 | * call the restock method and if it still needs | |
3863 | * more buffers it will schedule replenish */ | |
3864 | break; | |
3865 | } | |
3866 | priv->alloc_rxb_skb++; | |
3867 | list_del(element); | |
6440adb5 BC |
3868 | |
3869 | /* Get physical address of RB/SKB */ | |
b481de9c ZY |
3870 | rxb->dma_addr = |
3871 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
9ee1ba47 | 3872 | priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE); |
b481de9c ZY |
3873 | list_add_tail(&rxb->list, &rxq->rx_free); |
3874 | rxq->free_count++; | |
3875 | } | |
3876 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3877 | } |
3878 | ||
3879 | /* | |
3880 | * this should be called while priv->lock is locked | |
3881 | */ | |
4fd1f841 | 3882 | static void __iwl4965_rx_replenish(void *data) |
5c0eef96 | 3883 | { |
c79dd5b5 | 3884 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3885 | |
3886 | iwl4965_rx_allocate(priv); | |
3887 | iwl4965_rx_queue_restock(priv); | |
3888 | } | |
3889 | ||
3890 | ||
3891 | void iwl4965_rx_replenish(void *data) | |
3892 | { | |
c79dd5b5 | 3893 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3894 | unsigned long flags; |
3895 | ||
3896 | iwl4965_rx_allocate(priv); | |
b481de9c ZY |
3897 | |
3898 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3899 | iwl4965_rx_queue_restock(priv); |
b481de9c ZY |
3900 | spin_unlock_irqrestore(&priv->lock, flags); |
3901 | } | |
3902 | ||
3903 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3904 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3905 | * This free routine walks the list of POOL entries and if SKB is set to |
3906 | * non NULL it is unmapped and freed | |
3907 | */ | |
c79dd5b5 | 3908 | static void iwl4965_rx_queue_free(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
3909 | { |
3910 | int i; | |
3911 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3912 | if (rxq->pool[i].skb != NULL) { | |
3913 | pci_unmap_single(priv->pci_dev, | |
3914 | rxq->pool[i].dma_addr, | |
9ee1ba47 RR |
3915 | priv->hw_setting.rx_buf_size, |
3916 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3917 | dev_kfree_skb(rxq->pool[i].skb); |
3918 | } | |
3919 | } | |
3920 | ||
3921 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3922 | rxq->dma_addr); | |
3923 | rxq->bd = NULL; | |
3924 | } | |
3925 | ||
c79dd5b5 | 3926 | int iwl4965_rx_queue_alloc(struct iwl_priv *priv) |
b481de9c | 3927 | { |
bb8c093b | 3928 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3929 | struct pci_dev *dev = priv->pci_dev; |
3930 | int i; | |
3931 | ||
3932 | spin_lock_init(&rxq->lock); | |
3933 | INIT_LIST_HEAD(&rxq->rx_free); | |
3934 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 BC |
3935 | |
3936 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3937 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3938 | if (!rxq->bd) | |
3939 | return -ENOMEM; | |
6440adb5 | 3940 | |
b481de9c ZY |
3941 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3942 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3943 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3944 | |
b481de9c ZY |
3945 | /* Set us so that we have processed and used all buffers, but have |
3946 | * not restocked the Rx queue with fresh buffers */ | |
3947 | rxq->read = rxq->write = 0; | |
3948 | rxq->free_count = 0; | |
3949 | rxq->need_update = 0; | |
3950 | return 0; | |
3951 | } | |
3952 | ||
c79dd5b5 | 3953 | void iwl4965_rx_queue_reset(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
3954 | { |
3955 | unsigned long flags; | |
3956 | int i; | |
3957 | spin_lock_irqsave(&rxq->lock, flags); | |
3958 | INIT_LIST_HEAD(&rxq->rx_free); | |
3959 | INIT_LIST_HEAD(&rxq->rx_used); | |
3960 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
3961 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
3962 | /* In the reset function, these buffers may have been allocated | |
3963 | * to an SKB, so we need to unmap and free potential storage */ | |
3964 | if (rxq->pool[i].skb != NULL) { | |
3965 | pci_unmap_single(priv->pci_dev, | |
3966 | rxq->pool[i].dma_addr, | |
9ee1ba47 RR |
3967 | priv->hw_setting.rx_buf_size, |
3968 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3969 | priv->alloc_rxb_skb--; |
3970 | dev_kfree_skb(rxq->pool[i].skb); | |
3971 | rxq->pool[i].skb = NULL; | |
3972 | } | |
3973 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
3974 | } | |
3975 | ||
3976 | /* Set us so that we have processed and used all buffers, but have | |
3977 | * not restocked the Rx queue with fresh buffers */ | |
3978 | rxq->read = rxq->write = 0; | |
3979 | rxq->free_count = 0; | |
3980 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3981 | } | |
3982 | ||
3983 | /* Convert linear signal-to-noise ratio into dB */ | |
3984 | static u8 ratio2dB[100] = { | |
3985 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3986 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3987 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3988 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3989 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3990 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3991 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3992 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3993 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3994 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3995 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3996 | }; | |
3997 | ||
3998 | /* Calculates a relative dB value from a ratio of linear | |
3999 | * (i.e. not dB) signal levels. | |
4000 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 4001 | int iwl4965_calc_db_from_ratio(int sig_ratio) |
b481de9c | 4002 | { |
c899a575 AB |
4003 | /* 1000:1 or higher just report as 60 dB */ |
4004 | if (sig_ratio >= 1000) | |
b481de9c ZY |
4005 | return 60; |
4006 | ||
c899a575 | 4007 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 4008 | * add 20 dB to make up for divide by 10 */ |
c899a575 | 4009 | if (sig_ratio >= 100) |
b481de9c ZY |
4010 | return (20 + (int)ratio2dB[sig_ratio/10]); |
4011 | ||
4012 | /* We shouldn't see this */ | |
4013 | if (sig_ratio < 1) | |
4014 | return 0; | |
4015 | ||
4016 | /* Use table for ratios 1:1 - 99:1 */ | |
4017 | return (int)ratio2dB[sig_ratio]; | |
4018 | } | |
4019 | ||
4020 | #define PERFECT_RSSI (-20) /* dBm */ | |
4021 | #define WORST_RSSI (-95) /* dBm */ | |
4022 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
4023 | ||
4024 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
4025 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
4026 | * about formulas used below. */ | |
bb8c093b | 4027 | int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
4028 | { |
4029 | int sig_qual; | |
4030 | int degradation = PERFECT_RSSI - rssi_dbm; | |
4031 | ||
4032 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
4033 | * as indicator; formula is (signal dbm - noise dbm). | |
4034 | * SNR at or above 40 is a great signal (100%). | |
4035 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
4036 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
4037 | if (noise_dbm) { | |
4038 | if (rssi_dbm - noise_dbm >= 40) | |
4039 | return 100; | |
4040 | else if (rssi_dbm < noise_dbm) | |
4041 | return 0; | |
4042 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
4043 | ||
4044 | /* Else use just the signal level. | |
4045 | * This formula is a least squares fit of data points collected and | |
4046 | * compared with a reference system that had a percentage (%) display | |
4047 | * for signal quality. */ | |
4048 | } else | |
4049 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
4050 | (15 * RSSI_RANGE + 62 * degradation)) / | |
4051 | (RSSI_RANGE * RSSI_RANGE); | |
4052 | ||
4053 | if (sig_qual > 100) | |
4054 | sig_qual = 100; | |
4055 | else if (sig_qual < 1) | |
4056 | sig_qual = 0; | |
4057 | ||
4058 | return sig_qual; | |
4059 | } | |
4060 | ||
4061 | /** | |
9fbab516 | 4062 | * iwl4965_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
4063 | * |
4064 | * Uses the priv->rx_handlers callback function array to invoke | |
4065 | * the appropriate handlers, including command responses, | |
4066 | * frame-received notifications, and other notifications. | |
4067 | */ | |
c79dd5b5 | 4068 | static void iwl4965_rx_handle(struct iwl_priv *priv) |
b481de9c | 4069 | { |
bb8c093b CH |
4070 | struct iwl4965_rx_mem_buffer *rxb; |
4071 | struct iwl4965_rx_packet *pkt; | |
4072 | struct iwl4965_rx_queue *rxq = &priv->rxq; | |
b481de9c ZY |
4073 | u32 r, i; |
4074 | int reclaim; | |
4075 | unsigned long flags; | |
5c0eef96 | 4076 | u8 fill_rx = 0; |
d68ab680 | 4077 | u32 count = 8; |
b481de9c | 4078 | |
6440adb5 BC |
4079 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
4080 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 4081 | r = iwl4965_hw_get_rx_read(priv); |
b481de9c ZY |
4082 | i = rxq->read; |
4083 | ||
4084 | /* Rx interrupt, but nothing sent from uCode */ | |
4085 | if (i == r) | |
4086 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
4087 | ||
5c0eef96 MA |
4088 | if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
4089 | fill_rx = 1; | |
4090 | ||
b481de9c ZY |
4091 | while (i != r) { |
4092 | rxb = rxq->queue[i]; | |
4093 | ||
9fbab516 | 4094 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
4095 | * then a bug has been introduced in the queue refilling |
4096 | * routines -- catch it here */ | |
4097 | BUG_ON(rxb == NULL); | |
4098 | ||
4099 | rxq->queue[i] = NULL; | |
4100 | ||
4101 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, | |
9ee1ba47 | 4102 | priv->hw_setting.rx_buf_size, |
b481de9c | 4103 | PCI_DMA_FROMDEVICE); |
bb8c093b | 4104 | pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
4105 | |
4106 | /* Reclaim a command buffer only if this packet is a response | |
4107 | * to a (driver-originated) command. | |
4108 | * If the packet (e.g. Rx frame) originated from uCode, | |
4109 | * there is no command buffer to reclaim. | |
4110 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
4111 | * but apparently a few don't get set; catch them here. */ | |
4112 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
4113 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 4114 | (pkt->hdr.cmd != REPLY_RX) && |
cfe01709 | 4115 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
4116 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
4117 | (pkt->hdr.cmd != REPLY_TX); | |
4118 | ||
4119 | /* Based on type of command response or notification, | |
4120 | * handle those that need handling via function in | |
bb8c093b | 4121 | * rx_handlers table. See iwl4965_setup_rx_handlers() */ |
b481de9c ZY |
4122 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
4123 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4124 | "r = %d, i = %d, %s, 0x%02x\n", r, i, | |
4125 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
4126 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
4127 | } else { | |
4128 | /* No handling needed */ | |
4129 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4130 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
4131 | r, i, get_cmd_string(pkt->hdr.cmd), | |
4132 | pkt->hdr.cmd); | |
4133 | } | |
4134 | ||
4135 | if (reclaim) { | |
9fbab516 | 4136 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 4137 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
4138 | * as we reclaim the driver command queue */ |
4139 | if (rxb && rxb->skb) | |
bb8c093b | 4140 | iwl4965_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
4141 | else |
4142 | IWL_WARNING("Claim null rxb?\n"); | |
4143 | } | |
4144 | ||
4145 | /* For now we just don't re-use anything. We can tweak this | |
4146 | * later to try and re-use notification packets and SKBs that | |
4147 | * fail to Rx correctly */ | |
4148 | if (rxb->skb != NULL) { | |
4149 | priv->alloc_rxb_skb--; | |
4150 | dev_kfree_skb_any(rxb->skb); | |
4151 | rxb->skb = NULL; | |
4152 | } | |
4153 | ||
4154 | pci_unmap_single(priv->pci_dev, rxb->dma_addr, | |
9ee1ba47 RR |
4155 | priv->hw_setting.rx_buf_size, |
4156 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
4157 | spin_lock_irqsave(&rxq->lock, flags); |
4158 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
4159 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4160 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
4161 | /* If there are a lot of unused frames, |
4162 | * restock the Rx queue so ucode wont assert. */ | |
4163 | if (fill_rx) { | |
4164 | count++; | |
4165 | if (count >= 8) { | |
4166 | priv->rxq.read = i; | |
4167 | __iwl4965_rx_replenish(priv); | |
4168 | count = 0; | |
4169 | } | |
4170 | } | |
b481de9c ZY |
4171 | } |
4172 | ||
4173 | /* Backtrack one entry */ | |
4174 | priv->rxq.read = i; | |
bb8c093b | 4175 | iwl4965_rx_queue_restock(priv); |
b481de9c ZY |
4176 | } |
4177 | ||
6440adb5 BC |
4178 | /** |
4179 | * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware | |
4180 | */ | |
c79dd5b5 | 4181 | static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 4182 | struct iwl4965_tx_queue *txq) |
b481de9c ZY |
4183 | { |
4184 | u32 reg = 0; | |
4185 | int rc = 0; | |
4186 | int txq_id = txq->q.id; | |
4187 | ||
4188 | if (txq->need_update == 0) | |
4189 | return rc; | |
4190 | ||
4191 | /* if we're trying to save power */ | |
4192 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
4193 | /* wake up nic if it's powered down ... | |
4194 | * uCode will wake up, and interrupt us again, so next | |
4195 | * time we'll skip this part. */ | |
3395f6e9 | 4196 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
4197 | |
4198 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
4199 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
3395f6e9 | 4200 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
4201 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4202 | return rc; | |
4203 | } | |
4204 | ||
4205 | /* restore this queue's parameters in nic hardware. */ | |
3395f6e9 | 4206 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4207 | if (rc) |
4208 | return rc; | |
3395f6e9 | 4209 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4210 | txq->q.write_ptr | (txq_id << 8)); |
3395f6e9 | 4211 | iwl_release_nic_access(priv); |
b481de9c ZY |
4212 | |
4213 | /* else not in power-save mode, uCode will never sleep when we're | |
4214 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
4215 | } else | |
3395f6e9 | 4216 | iwl_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4217 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
4218 | |
4219 | txq->need_update = 0; | |
4220 | ||
4221 | return rc; | |
4222 | } | |
4223 | ||
0a6857e7 | 4224 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 4225 | static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon) |
b481de9c | 4226 | { |
0795af57 JP |
4227 | DECLARE_MAC_BUF(mac); |
4228 | ||
b481de9c | 4229 | IWL_DEBUG_RADIO("RX CONFIG:\n"); |
0a6857e7 | 4230 | iwl_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
4231 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
4232 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
4233 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
4234 | le32_to_cpu(rxon->filter_flags)); | |
4235 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
4236 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
4237 | rxon->ofdm_basic_rates); | |
4238 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
0795af57 JP |
4239 | IWL_DEBUG_RADIO("u8[6] node_addr: %s\n", |
4240 | print_mac(mac, rxon->node_addr)); | |
4241 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n", | |
4242 | print_mac(mac, rxon->bssid_addr)); | |
b481de9c ZY |
4243 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
4244 | } | |
4245 | #endif | |
4246 | ||
c79dd5b5 | 4247 | static void iwl4965_enable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
4248 | { |
4249 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
4250 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
3395f6e9 | 4251 | iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
4252 | } |
4253 | ||
0359facc MA |
4254 | /* call this function to flush any scheduled tasklet */ |
4255 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
4256 | { | |
4257 | /* wait to make sure we flush pedding tasklet*/ | |
4258 | synchronize_irq(priv->pci_dev->irq); | |
4259 | tasklet_kill(&priv->irq_tasklet); | |
4260 | } | |
4261 | ||
c79dd5b5 | 4262 | static inline void iwl4965_disable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
4263 | { |
4264 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
4265 | ||
4266 | /* disable interrupts from uCode/NIC to host */ | |
3395f6e9 | 4267 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
4268 | |
4269 | /* acknowledge/clear/reset any interrupts still pending | |
4270 | * from uCode or flow handler (Rx/Tx DMA) */ | |
3395f6e9 TW |
4271 | iwl_write32(priv, CSR_INT, 0xffffffff); |
4272 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
4273 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
4274 | } | |
4275 | ||
4276 | static const char *desc_lookup(int i) | |
4277 | { | |
4278 | switch (i) { | |
4279 | case 1: | |
4280 | return "FAIL"; | |
4281 | case 2: | |
4282 | return "BAD_PARAM"; | |
4283 | case 3: | |
4284 | return "BAD_CHECKSUM"; | |
4285 | case 4: | |
4286 | return "NMI_INTERRUPT"; | |
4287 | case 5: | |
4288 | return "SYSASSERT"; | |
4289 | case 6: | |
4290 | return "FATAL_ERROR"; | |
4291 | } | |
4292 | ||
4293 | return "UNKNOWN"; | |
4294 | } | |
4295 | ||
4296 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
4297 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
4298 | ||
c79dd5b5 | 4299 | static void iwl4965_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
4300 | { |
4301 | u32 data2, line; | |
4302 | u32 desc, time, count, base, data1; | |
4303 | u32 blink1, blink2, ilink1, ilink2; | |
4304 | int rc; | |
4305 | ||
4306 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
4307 | ||
bb8c093b | 4308 | if (!iwl4965_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4309 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
4310 | return; | |
4311 | } | |
4312 | ||
3395f6e9 | 4313 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4314 | if (rc) { |
4315 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4316 | return; | |
4317 | } | |
4318 | ||
3395f6e9 | 4319 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
4320 | |
4321 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
4322 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 4323 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
4324 | } |
4325 | ||
3395f6e9 TW |
4326 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); |
4327 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
4328 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
4329 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
4330 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
4331 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
4332 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
4333 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
4334 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
b481de9c ZY |
4335 | |
4336 | IWL_ERROR("Desc Time " | |
4337 | "data1 data2 line\n"); | |
4338 | IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n", | |
4339 | desc_lookup(desc), desc, time, data1, data2, line); | |
4340 | IWL_ERROR("blink1 blink2 ilink1 ilink2\n"); | |
4341 | IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
4342 | ilink1, ilink2); | |
4343 | ||
3395f6e9 | 4344 | iwl_release_nic_access(priv); |
b481de9c ZY |
4345 | } |
4346 | ||
4347 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
4348 | ||
4349 | /** | |
bb8c093b | 4350 | * iwl4965_print_event_log - Dump error event log to syslog |
b481de9c | 4351 | * |
3395f6e9 | 4352 | * NOTE: Must be called with iwl_grab_nic_access() already obtained! |
b481de9c | 4353 | */ |
c79dd5b5 | 4354 | static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
4355 | u32 num_events, u32 mode) |
4356 | { | |
4357 | u32 i; | |
4358 | u32 base; /* SRAM byte address of event log header */ | |
4359 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4360 | u32 ptr; /* SRAM byte address of log data */ | |
4361 | u32 ev, time, data; /* event log data */ | |
4362 | ||
4363 | if (num_events == 0) | |
4364 | return; | |
4365 | ||
4366 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4367 | ||
4368 | if (mode == 0) | |
4369 | event_size = 2 * sizeof(u32); | |
4370 | else | |
4371 | event_size = 3 * sizeof(u32); | |
4372 | ||
4373 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4374 | ||
4375 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4376 | * place event id # at far right for easier visual parsing. */ | |
4377 | for (i = 0; i < num_events; i++) { | |
3395f6e9 | 4378 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 4379 | ptr += sizeof(u32); |
3395f6e9 | 4380 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4381 | ptr += sizeof(u32); |
4382 | if (mode == 0) | |
4383 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4384 | else { | |
3395f6e9 | 4385 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4386 | ptr += sizeof(u32); |
4387 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4388 | } | |
4389 | } | |
4390 | } | |
4391 | ||
c79dd5b5 | 4392 | static void iwl4965_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c ZY |
4393 | { |
4394 | int rc; | |
4395 | u32 base; /* SRAM byte address of event log header */ | |
4396 | u32 capacity; /* event log capacity in # entries */ | |
4397 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4398 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4399 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4400 | u32 size; /* # entries that we'll print */ | |
4401 | ||
4402 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 4403 | if (!iwl4965_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4404 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4405 | return; | |
4406 | } | |
4407 | ||
3395f6e9 | 4408 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4409 | if (rc) { |
4410 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4411 | return; | |
4412 | } | |
4413 | ||
4414 | /* event log header */ | |
3395f6e9 TW |
4415 | capacity = iwl_read_targ_mem(priv, base); |
4416 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4417 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4418 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4419 | |
4420 | size = num_wraps ? capacity : next_entry; | |
4421 | ||
4422 | /* bail out if nothing in log */ | |
4423 | if (size == 0) { | |
583fab37 | 4424 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
3395f6e9 | 4425 | iwl_release_nic_access(priv); |
b481de9c ZY |
4426 | return; |
4427 | } | |
4428 | ||
583fab37 | 4429 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4430 | size, num_wraps); |
4431 | ||
4432 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4433 | * i.e the next one that uCode would fill. */ | |
4434 | if (num_wraps) | |
bb8c093b | 4435 | iwl4965_print_event_log(priv, next_entry, |
b481de9c ZY |
4436 | capacity - next_entry, mode); |
4437 | ||
4438 | /* (then/else) start at top of log */ | |
bb8c093b | 4439 | iwl4965_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4440 | |
3395f6e9 | 4441 | iwl_release_nic_access(priv); |
b481de9c ZY |
4442 | } |
4443 | ||
4444 | /** | |
bb8c093b | 4445 | * iwl4965_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4446 | */ |
c79dd5b5 | 4447 | static void iwl4965_irq_handle_error(struct iwl_priv *priv) |
b481de9c | 4448 | { |
bb8c093b | 4449 | /* Set the FW error flag -- cleared on iwl4965_down */ |
b481de9c ZY |
4450 | set_bit(STATUS_FW_ERROR, &priv->status); |
4451 | ||
4452 | /* Cancel currently queued command. */ | |
4453 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4454 | ||
0a6857e7 TW |
4455 | #ifdef CONFIG_IWLWIFI_DEBUG |
4456 | if (iwl_debug_level & IWL_DL_FW_ERRORS) { | |
bb8c093b CH |
4457 | iwl4965_dump_nic_error_log(priv); |
4458 | iwl4965_dump_nic_event_log(priv); | |
4459 | iwl4965_print_rx_config_cmd(&priv->staging_rxon); | |
b481de9c ZY |
4460 | } |
4461 | #endif | |
4462 | ||
4463 | wake_up_interruptible(&priv->wait_command_queue); | |
4464 | ||
4465 | /* Keep the restart process from trying to send host | |
4466 | * commands by clearing the INIT status bit */ | |
4467 | clear_bit(STATUS_READY, &priv->status); | |
4468 | ||
4469 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4470 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4471 | "Restarting adapter due to uCode error.\n"); | |
4472 | ||
3109ece1 | 4473 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4474 | memcpy(&priv->recovery_rxon, &priv->active_rxon, |
4475 | sizeof(priv->recovery_rxon)); | |
4476 | priv->error_recovering = 1; | |
4477 | } | |
4478 | queue_work(priv->workqueue, &priv->restart); | |
4479 | } | |
4480 | } | |
4481 | ||
c79dd5b5 | 4482 | static void iwl4965_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
4483 | { |
4484 | unsigned long flags; | |
4485 | ||
4486 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
4487 | sizeof(priv->staging_rxon)); | |
4488 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4489 | iwl4965_commit_rxon(priv); |
b481de9c | 4490 | |
bb8c093b | 4491 | iwl4965_rxon_add_station(priv, priv->bssid, 1); |
b481de9c ZY |
4492 | |
4493 | spin_lock_irqsave(&priv->lock, flags); | |
4494 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
4495 | priv->error_recovering = 0; | |
4496 | spin_unlock_irqrestore(&priv->lock, flags); | |
4497 | } | |
4498 | ||
c79dd5b5 | 4499 | static void iwl4965_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
4500 | { |
4501 | u32 inta, handled = 0; | |
4502 | u32 inta_fh; | |
4503 | unsigned long flags; | |
0a6857e7 | 4504 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
4505 | u32 inta_mask; |
4506 | #endif | |
4507 | ||
4508 | spin_lock_irqsave(&priv->lock, flags); | |
4509 | ||
4510 | /* Ack/clear/reset pending uCode interrupts. | |
4511 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4512 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
4513 | inta = iwl_read32(priv, CSR_INT); |
4514 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4515 | |
4516 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4517 | * Any new interrupts that happen after this, either while we're | |
4518 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
4519 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
4520 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4521 | |
0a6857e7 TW |
4522 | #ifdef CONFIG_IWLWIFI_DEBUG |
4523 | if (iwl_debug_level & IWL_DL_ISR) { | |
9fbab516 | 4524 | /* just for debug */ |
3395f6e9 | 4525 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
b481de9c ZY |
4526 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4527 | inta, inta_mask, inta_fh); | |
4528 | } | |
4529 | #endif | |
4530 | ||
4531 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4532 | * atomic, make sure that inta covers all the interrupts that | |
4533 | * we've discovered, even if FH interrupt came in just after | |
4534 | * reading CSR_INT. */ | |
6f83eaa1 | 4535 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 4536 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4537 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
4538 | inta |= CSR_INT_BIT_FH_TX; |
4539 | ||
4540 | /* Now service all interrupt bits discovered above. */ | |
4541 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4542 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4543 | ||
4544 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4545 | iwl4965_disable_interrupts(priv); |
b481de9c | 4546 | |
bb8c093b | 4547 | iwl4965_irq_handle_error(priv); |
b481de9c ZY |
4548 | |
4549 | handled |= CSR_INT_BIT_HW_ERR; | |
4550 | ||
4551 | spin_unlock_irqrestore(&priv->lock, flags); | |
4552 | ||
4553 | return; | |
4554 | } | |
4555 | ||
0a6857e7 TW |
4556 | #ifdef CONFIG_IWLWIFI_DEBUG |
4557 | if (iwl_debug_level & (IWL_DL_ISR)) { | |
b481de9c | 4558 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4559 | if (inta & CSR_INT_BIT_SCD) |
4560 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4561 | "the frame/frames.\n"); | |
b481de9c ZY |
4562 | |
4563 | /* Alive notification via Rx interrupt will do the real work */ | |
4564 | if (inta & CSR_INT_BIT_ALIVE) | |
4565 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4566 | } | |
4567 | #endif | |
4568 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4569 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 4570 | |
9fbab516 | 4571 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
4572 | if (inta & CSR_INT_BIT_RF_KILL) { |
4573 | int hw_rf_kill = 0; | |
3395f6e9 | 4574 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
4575 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
4576 | hw_rf_kill = 1; | |
4577 | ||
4578 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, | |
4579 | "RF_KILL bit toggled to %s.\n", | |
4580 | hw_rf_kill ? "disable radio":"enable radio"); | |
4581 | ||
4582 | /* Queue restart only if RF_KILL switch was set to "kill" | |
4583 | * when we loaded driver, and is now set to "enable". | |
4584 | * After we're Alive, RF_KILL gets handled by | |
3230455d | 4585 | * iwl4965_rx_card_state_notif() */ |
53e49093 ZY |
4586 | if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { |
4587 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
b481de9c | 4588 | queue_work(priv->workqueue, &priv->restart); |
53e49093 | 4589 | } |
b481de9c ZY |
4590 | |
4591 | handled |= CSR_INT_BIT_RF_KILL; | |
4592 | } | |
4593 | ||
9fbab516 | 4594 | /* Chip got too hot and stopped itself */ |
b481de9c ZY |
4595 | if (inta & CSR_INT_BIT_CT_KILL) { |
4596 | IWL_ERROR("Microcode CT kill error detected.\n"); | |
4597 | handled |= CSR_INT_BIT_CT_KILL; | |
4598 | } | |
4599 | ||
4600 | /* Error detected by uCode */ | |
4601 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4602 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4603 | inta); | |
bb8c093b | 4604 | iwl4965_irq_handle_error(priv); |
b481de9c ZY |
4605 | handled |= CSR_INT_BIT_SW_ERR; |
4606 | } | |
4607 | ||
4608 | /* uCode wakes up after power-down sleep */ | |
4609 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4610 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b CH |
4611 | iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq); |
4612 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]); | |
4613 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]); | |
4614 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]); | |
4615 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]); | |
4616 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]); | |
4617 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
4618 | |
4619 | handled |= CSR_INT_BIT_WAKEUP; | |
4620 | } | |
4621 | ||
4622 | /* All uCode command responses, including Tx command responses, | |
4623 | * Rx "responses" (frame-received notification), and other | |
4624 | * notifications from uCode come through here*/ | |
4625 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4626 | iwl4965_rx_handle(priv); |
b481de9c ZY |
4627 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4628 | } | |
4629 | ||
4630 | if (inta & CSR_INT_BIT_FH_TX) { | |
4631 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4632 | handled |= CSR_INT_BIT_FH_TX; | |
4633 | } | |
4634 | ||
4635 | if (inta & ~handled) | |
4636 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4637 | ||
4638 | if (inta & ~CSR_INI_SET_MASK) { | |
4639 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4640 | inta & ~CSR_INI_SET_MASK); | |
4641 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4642 | } | |
4643 | ||
4644 | /* Re-enable all interrupts */ | |
0359facc MA |
4645 | /* only Re-enable if diabled by irq */ |
4646 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4647 | iwl4965_enable_interrupts(priv); | |
b481de9c | 4648 | |
0a6857e7 TW |
4649 | #ifdef CONFIG_IWLWIFI_DEBUG |
4650 | if (iwl_debug_level & (IWL_DL_ISR)) { | |
3395f6e9 TW |
4651 | inta = iwl_read32(priv, CSR_INT); |
4652 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
4653 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4654 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4655 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4656 | } | |
4657 | #endif | |
4658 | spin_unlock_irqrestore(&priv->lock, flags); | |
4659 | } | |
4660 | ||
bb8c093b | 4661 | static irqreturn_t iwl4965_isr(int irq, void *data) |
b481de9c | 4662 | { |
c79dd5b5 | 4663 | struct iwl_priv *priv = data; |
b481de9c ZY |
4664 | u32 inta, inta_mask; |
4665 | u32 inta_fh; | |
4666 | if (!priv) | |
4667 | return IRQ_NONE; | |
4668 | ||
4669 | spin_lock(&priv->lock); | |
4670 | ||
4671 | /* Disable (but don't clear!) interrupts here to avoid | |
4672 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4673 | * If we have something to service, the tasklet will re-enable ints. | |
4674 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
3395f6e9 TW |
4675 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
4676 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4677 | |
4678 | /* Discover which interrupts are active/pending */ | |
3395f6e9 TW |
4679 | inta = iwl_read32(priv, CSR_INT); |
4680 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4681 | |
4682 | /* Ignore interrupt if there's nothing in NIC to service. | |
4683 | * This may be due to IRQ shared with another device, | |
4684 | * or due to sporadic interrupts thrown from our NIC. */ | |
4685 | if (!inta && !inta_fh) { | |
4686 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4687 | goto none; | |
4688 | } | |
4689 | ||
4690 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
66fbb541 ON |
4691 | /* Hardware disappeared. It might have already raised |
4692 | * an interrupt */ | |
b481de9c | 4693 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta); |
66fbb541 | 4694 | goto unplugged; |
b481de9c ZY |
4695 | } |
4696 | ||
4697 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4698 | inta, inta_mask, inta_fh); | |
4699 | ||
25c03d8e JP |
4700 | inta &= ~CSR_INT_BIT_SCD; |
4701 | ||
bb8c093b | 4702 | /* iwl4965_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4703 | if (likely(inta || inta_fh)) |
4704 | tasklet_schedule(&priv->irq_tasklet); | |
b481de9c | 4705 | |
66fbb541 ON |
4706 | unplugged: |
4707 | spin_unlock(&priv->lock); | |
b481de9c ZY |
4708 | return IRQ_HANDLED; |
4709 | ||
4710 | none: | |
4711 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
4712 | /* only Re-enable if diabled by irq */ |
4713 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4714 | iwl4965_enable_interrupts(priv); | |
b481de9c ZY |
4715 | spin_unlock(&priv->lock); |
4716 | return IRQ_NONE; | |
4717 | } | |
4718 | ||
b481de9c ZY |
4719 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4720 | * sending probe req. This should be set long enough to hear probe responses | |
4721 | * from more than one AP. */ | |
4722 | #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4723 | #define IWL_ACTIVE_DWELL_TIME_52 (10) | |
4724 | ||
4725 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4726 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4727 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4728 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4729 | * no other traffic). | |
4730 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4731 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
4732 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */ | |
4733 | ||
4734 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4735 | * Must be set longer than active dwell time. | |
4736 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4737 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4738 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4739 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4740 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4741 | ||
c79dd5b5 | 4742 | static inline u16 iwl4965_get_active_dwell_time(struct iwl_priv *priv, |
8318d78a | 4743 | enum ieee80211_band band) |
b481de9c | 4744 | { |
8318d78a | 4745 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4746 | return IWL_ACTIVE_DWELL_TIME_52; |
4747 | else | |
4748 | return IWL_ACTIVE_DWELL_TIME_24; | |
4749 | } | |
4750 | ||
c79dd5b5 | 4751 | static u16 iwl4965_get_passive_dwell_time(struct iwl_priv *priv, |
8318d78a | 4752 | enum ieee80211_band band) |
b481de9c | 4753 | { |
8318d78a JB |
4754 | u16 active = iwl4965_get_active_dwell_time(priv, band); |
4755 | u16 passive = (band != IEEE80211_BAND_5GHZ) ? | |
b481de9c ZY |
4756 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4757 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4758 | ||
3109ece1 | 4759 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4760 | /* If we're associated, we clamp the maximum passive |
4761 | * dwell time to be 98% of the beacon interval (minus | |
4762 | * 2 * channel tune time) */ | |
4763 | passive = priv->beacon_int; | |
4764 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4765 | passive = IWL_PASSIVE_DWELL_BASE; | |
4766 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4767 | } | |
4768 | ||
4769 | if (passive <= active) | |
4770 | passive = active + 1; | |
4771 | ||
4772 | return passive; | |
4773 | } | |
4774 | ||
c79dd5b5 | 4775 | static int iwl4965_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 4776 | enum ieee80211_band band, |
b481de9c | 4777 | u8 is_active, u8 direct_mask, |
bb8c093b | 4778 | struct iwl4965_scan_channel *scan_ch) |
b481de9c ZY |
4779 | { |
4780 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4781 | const struct ieee80211_supported_band *sband; |
bf85ea4f | 4782 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
4783 | u16 passive_dwell = 0; |
4784 | u16 active_dwell = 0; | |
4785 | int added, i; | |
4786 | ||
8318d78a JB |
4787 | sband = iwl4965_get_hw_mode(priv, band); |
4788 | if (!sband) | |
b481de9c ZY |
4789 | return 0; |
4790 | ||
8318d78a | 4791 | channels = sband->channels; |
b481de9c | 4792 | |
8318d78a JB |
4793 | active_dwell = iwl4965_get_active_dwell_time(priv, band); |
4794 | passive_dwell = iwl4965_get_passive_dwell_time(priv, band); | |
b481de9c | 4795 | |
8318d78a | 4796 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4797 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4798 | continue; | |
4799 | ||
8318d78a | 4800 | if (ieee80211_frequency_to_channel(channels[i].center_freq) == |
b481de9c | 4801 | le16_to_cpu(priv->active_rxon.channel)) { |
3109ece1 | 4802 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4803 | IWL_DEBUG_SCAN |
4804 | ("Skipping current channel %d\n", | |
4805 | le16_to_cpu(priv->active_rxon.channel)); | |
4806 | continue; | |
4807 | } | |
4808 | } else if (priv->only_active_channel) | |
4809 | continue; | |
4810 | ||
8318d78a | 4811 | scan_ch->channel = ieee80211_frequency_to_channel(channels[i].center_freq); |
b481de9c | 4812 | |
8622e705 | 4813 | ch_info = iwl_get_channel_info(priv, band, |
9fbab516 | 4814 | scan_ch->channel); |
b481de9c ZY |
4815 | if (!is_channel_valid(ch_info)) { |
4816 | IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n", | |
4817 | scan_ch->channel); | |
4818 | continue; | |
4819 | } | |
4820 | ||
4821 | if (!is_active || is_channel_passive(ch_info) || | |
8318d78a | 4822 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) |
b481de9c ZY |
4823 | scan_ch->type = 0; /* passive */ |
4824 | else | |
4825 | scan_ch->type = 1; /* active */ | |
4826 | ||
4827 | if (scan_ch->type & 1) | |
4828 | scan_ch->type |= (direct_mask << 1); | |
4829 | ||
4830 | if (is_channel_narrow(ch_info)) | |
4831 | scan_ch->type |= (1 << 7); | |
4832 | ||
4833 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
4834 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
4835 | ||
9fbab516 | 4836 | /* Set txpower levels to defaults */ |
b481de9c ZY |
4837 | scan_ch->tpc.dsp_atten = 110; |
4838 | /* scan_pwr_info->tpc.dsp_atten; */ | |
4839 | ||
4840 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 4841 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4842 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
4843 | else { | |
4844 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
4845 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 4846 | * power level: |
8a1b0245 | 4847 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
4848 | */ |
4849 | } | |
4850 | ||
4851 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
4852 | scan_ch->channel, | |
4853 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
4854 | (scan_ch->type & 1) ? | |
4855 | active_dwell : passive_dwell); | |
4856 | ||
4857 | scan_ch++; | |
4858 | added++; | |
4859 | } | |
4860 | ||
4861 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
4862 | return added; | |
4863 | } | |
4864 | ||
c79dd5b5 | 4865 | static void iwl4965_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
4866 | struct ieee80211_rate *rates) |
4867 | { | |
4868 | int i; | |
4869 | ||
4870 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
4871 | rates[i].bitrate = iwl4965_rates[i].ieee * 5; |
4872 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4873 | rates[i].hw_value_short = i; | |
4874 | rates[i].flags = 0; | |
4875 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
b481de9c | 4876 | /* |
8318d78a | 4877 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 4878 | */ |
35cdeaf4 TW |
4879 | rates[i].flags |= |
4880 | (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
4881 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
b481de9c | 4882 | } |
b481de9c | 4883 | } |
b481de9c ZY |
4884 | } |
4885 | ||
4886 | /** | |
bb8c093b | 4887 | * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 4888 | */ |
bf85ea4f | 4889 | int iwl4965_init_geos(struct iwl_priv *priv) |
b481de9c | 4890 | { |
bf85ea4f | 4891 | struct iwl_channel_info *ch; |
8211ef78 | 4892 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
4893 | struct ieee80211_channel *channels; |
4894 | struct ieee80211_channel *geo_ch; | |
4895 | struct ieee80211_rate *rates; | |
4896 | int i = 0; | |
b481de9c | 4897 | |
8318d78a JB |
4898 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
4899 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
4900 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
4901 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4902 | return 0; | |
4903 | } | |
4904 | ||
b481de9c ZY |
4905 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
4906 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 4907 | if (!channels) |
b481de9c | 4908 | return -ENOMEM; |
b481de9c | 4909 | |
8211ef78 | 4910 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
4911 | GFP_KERNEL); |
4912 | if (!rates) { | |
b481de9c ZY |
4913 | kfree(channels); |
4914 | return -ENOMEM; | |
4915 | } | |
4916 | ||
b481de9c | 4917 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 | 4918 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
bf85ea4f | 4919 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; |
8211ef78 TW |
4920 | /* just OFDM */ |
4921 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
4922 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
8318d78a | 4923 | |
1ea87396 | 4924 | iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ); |
78330fdd | 4925 | |
8211ef78 TW |
4926 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
4927 | sband->channels = channels; | |
4928 | /* OFDM & CCK */ | |
4929 | sband->bitrates = rates; | |
4930 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c | 4931 | |
1ea87396 | 4932 | iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ); |
78330fdd | 4933 | |
b481de9c ZY |
4934 | priv->ieee_channels = channels; |
4935 | priv->ieee_rates = rates; | |
4936 | ||
bb8c093b | 4937 | iwl4965_init_hw_rates(priv, rates); |
b481de9c | 4938 | |
8211ef78 | 4939 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
4940 | ch = &priv->channel_info[i]; |
4941 | ||
8211ef78 TW |
4942 | /* FIXME: might be removed if scan is OK */ |
4943 | if (!is_channel_valid(ch)) | |
b481de9c | 4944 | continue; |
b481de9c | 4945 | |
8211ef78 TW |
4946 | if (is_channel_a_band(ch)) |
4947 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
4948 | else | |
4949 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
b481de9c | 4950 | |
8211ef78 TW |
4951 | geo_ch = &sband->channels[sband->n_channels++]; |
4952 | ||
4953 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
4954 | geo_ch->max_power = ch->max_power_avg; |
4955 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 4956 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
4957 | |
4958 | if (is_channel_valid(ch)) { | |
8318d78a JB |
4959 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
4960 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 4961 | |
8318d78a JB |
4962 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
4963 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
4964 | |
4965 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 4966 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
4967 | |
4968 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
4969 | priv->max_channel_txpower_limit = | |
4970 | ch->max_power_avg; | |
8211ef78 | 4971 | } else { |
8318d78a | 4972 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
4973 | } |
4974 | ||
4975 | /* Save flags for reg domain usage */ | |
4976 | geo_ch->orig_flags = geo_ch->flags; | |
4977 | ||
4978 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
4979 | ch->channel, geo_ch->center_freq, | |
4980 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
4981 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
4982 | "restricted" : "valid", | |
4983 | geo_ch->flags); | |
b481de9c ZY |
4984 | } |
4985 | ||
82b9a121 TW |
4986 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
4987 | priv->cfg->sku & IWL_SKU_A) { | |
b481de9c ZY |
4988 | printk(KERN_INFO DRV_NAME |
4989 | ": Incorrectly detected BG card as ABG. Please send " | |
4990 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
4991 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 4992 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
4993 | } |
4994 | ||
4995 | printk(KERN_INFO DRV_NAME | |
4996 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
4997 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
4998 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 4999 | |
e0e0a67e JL |
5000 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
5001 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
5002 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
5003 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
5004 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
5005 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 5006 | |
b481de9c ZY |
5007 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
5008 | ||
5009 | return 0; | |
5010 | } | |
5011 | ||
849e0dce RC |
5012 | /* |
5013 | * iwl4965_free_geos - undo allocations in iwl4965_init_geos | |
5014 | */ | |
bf85ea4f | 5015 | void iwl4965_free_geos(struct iwl_priv *priv) |
849e0dce | 5016 | { |
849e0dce RC |
5017 | kfree(priv->ieee_channels); |
5018 | kfree(priv->ieee_rates); | |
5019 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
5020 | } | |
5021 | ||
b481de9c ZY |
5022 | /****************************************************************************** |
5023 | * | |
5024 | * uCode download functions | |
5025 | * | |
5026 | ******************************************************************************/ | |
5027 | ||
c79dd5b5 | 5028 | static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 5029 | { |
98c92211 TW |
5030 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
5031 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
5032 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
5033 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
5034 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
5035 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
5036 | } |
5037 | ||
5038 | /** | |
bb8c093b | 5039 | * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5040 | * looking at all data. |
5041 | */ | |
c79dd5b5 | 5042 | static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image, |
9fbab516 | 5043 | u32 len) |
b481de9c ZY |
5044 | { |
5045 | u32 val; | |
5046 | u32 save_len = len; | |
5047 | int rc = 0; | |
5048 | u32 errcnt; | |
5049 | ||
5050 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5051 | ||
3395f6e9 | 5052 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5053 | if (rc) |
5054 | return rc; | |
5055 | ||
3395f6e9 | 5056 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
b481de9c ZY |
5057 | |
5058 | errcnt = 0; | |
5059 | for (; len > 0; len -= sizeof(u32), image++) { | |
5060 | /* read data comes through single port, auto-incr addr */ | |
5061 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5062 | * if IWL_DL_IO is set */ | |
3395f6e9 | 5063 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5064 | if (val != le32_to_cpu(*image)) { |
5065 | IWL_ERROR("uCode INST section is invalid at " | |
5066 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5067 | save_len - len, val, le32_to_cpu(*image)); | |
5068 | rc = -EIO; | |
5069 | errcnt++; | |
5070 | if (errcnt >= 20) | |
5071 | break; | |
5072 | } | |
5073 | } | |
5074 | ||
3395f6e9 | 5075 | iwl_release_nic_access(priv); |
b481de9c ZY |
5076 | |
5077 | if (!errcnt) | |
5078 | IWL_DEBUG_INFO | |
5079 | ("ucode image in INSTRUCTION memory is good\n"); | |
5080 | ||
5081 | return rc; | |
5082 | } | |
5083 | ||
5084 | ||
5085 | /** | |
bb8c093b | 5086 | * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5087 | * using sample data 100 bytes apart. If these sample points are good, |
5088 | * it's a pretty good bet that everything between them is good, too. | |
5089 | */ | |
c79dd5b5 | 5090 | static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
5091 | { |
5092 | u32 val; | |
5093 | int rc = 0; | |
5094 | u32 errcnt = 0; | |
5095 | u32 i; | |
5096 | ||
5097 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5098 | ||
3395f6e9 | 5099 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5100 | if (rc) |
5101 | return rc; | |
5102 | ||
5103 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
5104 | /* read data comes through single port, auto-incr addr */ | |
5105 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5106 | * if IWL_DL_IO is set */ | |
3395f6e9 | 5107 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
b481de9c | 5108 | i + RTC_INST_LOWER_BOUND); |
3395f6e9 | 5109 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5110 | if (val != le32_to_cpu(*image)) { |
5111 | #if 0 /* Enable this if you want to see details */ | |
5112 | IWL_ERROR("uCode INST section is invalid at " | |
5113 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5114 | i, val, *image); | |
5115 | #endif | |
5116 | rc = -EIO; | |
5117 | errcnt++; | |
5118 | if (errcnt >= 3) | |
5119 | break; | |
5120 | } | |
5121 | } | |
5122 | ||
3395f6e9 | 5123 | iwl_release_nic_access(priv); |
b481de9c ZY |
5124 | |
5125 | return rc; | |
5126 | } | |
5127 | ||
5128 | ||
5129 | /** | |
bb8c093b | 5130 | * iwl4965_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5131 | * and verify its contents |
5132 | */ | |
c79dd5b5 | 5133 | static int iwl4965_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
5134 | { |
5135 | __le32 *image; | |
5136 | u32 len; | |
5137 | int rc = 0; | |
5138 | ||
5139 | /* Try bootstrap */ | |
5140 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5141 | len = priv->ucode_boot.len; | |
bb8c093b | 5142 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5143 | if (rc == 0) { |
5144 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5145 | return 0; | |
5146 | } | |
5147 | ||
5148 | /* Try initialize */ | |
5149 | image = (__le32 *)priv->ucode_init.v_addr; | |
5150 | len = priv->ucode_init.len; | |
bb8c093b | 5151 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5152 | if (rc == 0) { |
5153 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5154 | return 0; | |
5155 | } | |
5156 | ||
5157 | /* Try runtime/protocol */ | |
5158 | image = (__le32 *)priv->ucode_code.v_addr; | |
5159 | len = priv->ucode_code.len; | |
bb8c093b | 5160 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5161 | if (rc == 0) { |
5162 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5163 | return 0; | |
5164 | } | |
5165 | ||
5166 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5167 | ||
9fbab516 BC |
5168 | /* Since nothing seems to match, show first several data entries in |
5169 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5170 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5171 | image = (__le32 *)priv->ucode_boot.v_addr; |
5172 | len = priv->ucode_boot.len; | |
bb8c093b | 5173 | rc = iwl4965_verify_inst_full(priv, image, len); |
b481de9c ZY |
5174 | |
5175 | return rc; | |
5176 | } | |
5177 | ||
5178 | ||
5179 | /* check contents of special bootstrap uCode SRAM */ | |
c79dd5b5 | 5180 | static int iwl4965_verify_bsm(struct iwl_priv *priv) |
b481de9c ZY |
5181 | { |
5182 | __le32 *image = priv->ucode_boot.v_addr; | |
5183 | u32 len = priv->ucode_boot.len; | |
5184 | u32 reg; | |
5185 | u32 val; | |
5186 | ||
5187 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
5188 | ||
5189 | /* verify BSM SRAM contents */ | |
3395f6e9 | 5190 | val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG); |
b481de9c ZY |
5191 | for (reg = BSM_SRAM_LOWER_BOUND; |
5192 | reg < BSM_SRAM_LOWER_BOUND + len; | |
5193 | reg += sizeof(u32), image ++) { | |
3395f6e9 | 5194 | val = iwl_read_prph(priv, reg); |
b481de9c ZY |
5195 | if (val != le32_to_cpu(*image)) { |
5196 | IWL_ERROR("BSM uCode verification failed at " | |
5197 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
5198 | BSM_SRAM_LOWER_BOUND, | |
5199 | reg - BSM_SRAM_LOWER_BOUND, len, | |
5200 | val, le32_to_cpu(*image)); | |
5201 | return -EIO; | |
5202 | } | |
5203 | } | |
5204 | ||
5205 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
5206 | ||
5207 | return 0; | |
5208 | } | |
5209 | ||
5210 | /** | |
bb8c093b | 5211 | * iwl4965_load_bsm - Load bootstrap instructions |
b481de9c ZY |
5212 | * |
5213 | * BSM operation: | |
5214 | * | |
5215 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
5216 | * in special SRAM that does not power down during RFKILL. When powering back | |
5217 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
5218 | * the bootstrap program into the on-board processor, and starts it. | |
5219 | * | |
5220 | * The bootstrap program loads (via DMA) instructions and data for a new | |
5221 | * program from host DRAM locations indicated by the host driver in the | |
5222 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
5223 | * automatically. | |
5224 | * | |
5225 | * When initializing the NIC, the host driver points the BSM to the | |
5226 | * "initialize" uCode image. This uCode sets up some internal data, then | |
5227 | * notifies host via "initialize alive" that it is complete. | |
5228 | * | |
5229 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
5230 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
5231 | * (filled initially with starting data values for the on-board processor), | |
5232 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
5233 | * which begins normal operation. | |
5234 | * | |
5235 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
5236 | * the backup data cache in DRAM before SRAM is powered down. | |
5237 | * | |
5238 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
5239 | * the runtime uCode instructions and the backup data cache into SRAM, | |
5240 | * and re-launches the runtime uCode from where it left off. | |
5241 | */ | |
c79dd5b5 | 5242 | static int iwl4965_load_bsm(struct iwl_priv *priv) |
b481de9c ZY |
5243 | { |
5244 | __le32 *image = priv->ucode_boot.v_addr; | |
5245 | u32 len = priv->ucode_boot.len; | |
5246 | dma_addr_t pinst; | |
5247 | dma_addr_t pdata; | |
5248 | u32 inst_len; | |
5249 | u32 data_len; | |
5250 | int rc; | |
5251 | int i; | |
5252 | u32 done; | |
5253 | u32 reg_offset; | |
5254 | ||
5255 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
5256 | ||
5257 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
5258 | if (len > IWL_MAX_BSM_SIZE) | |
5259 | return -EINVAL; | |
5260 | ||
5261 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
9fbab516 | 5262 | * in host DRAM ... host DRAM physical address bits 35:4 for 4965. |
bb8c093b | 5263 | * NOTE: iwl4965_initialize_alive_start() will replace these values, |
b481de9c ZY |
5264 | * after the "initialize" uCode has run, to point to |
5265 | * runtime/protocol instructions and backup data cache. */ | |
5266 | pinst = priv->ucode_init.p_addr >> 4; | |
5267 | pdata = priv->ucode_init_data.p_addr >> 4; | |
5268 | inst_len = priv->ucode_init.len; | |
5269 | data_len = priv->ucode_init_data.len; | |
5270 | ||
3395f6e9 | 5271 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5272 | if (rc) |
5273 | return rc; | |
5274 | ||
3395f6e9 TW |
5275 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5276 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5277 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
5278 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
b481de9c ZY |
5279 | |
5280 | /* Fill BSM memory with bootstrap instructions */ | |
5281 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
5282 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
5283 | reg_offset += sizeof(u32), image++) | |
3395f6e9 | 5284 | _iwl_write_prph(priv, reg_offset, |
b481de9c ZY |
5285 | le32_to_cpu(*image)); |
5286 | ||
bb8c093b | 5287 | rc = iwl4965_verify_bsm(priv); |
b481de9c | 5288 | if (rc) { |
3395f6e9 | 5289 | iwl_release_nic_access(priv); |
b481de9c ZY |
5290 | return rc; |
5291 | } | |
5292 | ||
5293 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
3395f6e9 TW |
5294 | iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); |
5295 | iwl_write_prph(priv, BSM_WR_MEM_DST_REG, | |
b481de9c | 5296 | RTC_INST_LOWER_BOUND); |
3395f6e9 | 5297 | iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
b481de9c ZY |
5298 | |
5299 | /* Load bootstrap code into instruction SRAM now, | |
5300 | * to prepare to load "initialize" uCode */ | |
3395f6e9 | 5301 | iwl_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5302 | BSM_WR_CTRL_REG_BIT_START); |
5303 | ||
5304 | /* Wait for load of bootstrap uCode to finish */ | |
5305 | for (i = 0; i < 100; i++) { | |
3395f6e9 | 5306 | done = iwl_read_prph(priv, BSM_WR_CTRL_REG); |
b481de9c ZY |
5307 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
5308 | break; | |
5309 | udelay(10); | |
5310 | } | |
5311 | if (i < 100) | |
5312 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
5313 | else { | |
5314 | IWL_ERROR("BSM write did not complete!\n"); | |
5315 | return -EIO; | |
5316 | } | |
5317 | ||
5318 | /* Enable future boot loads whenever power management unit triggers it | |
5319 | * (e.g. when powering back up after power-save shutdown) */ | |
3395f6e9 | 5320 | iwl_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5321 | BSM_WR_CTRL_REG_BIT_START_EN); |
5322 | ||
3395f6e9 | 5323 | iwl_release_nic_access(priv); |
b481de9c ZY |
5324 | |
5325 | return 0; | |
5326 | } | |
5327 | ||
c79dd5b5 | 5328 | static void iwl4965_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
5329 | { |
5330 | /* Remove all resets to allow NIC to operate */ | |
3395f6e9 | 5331 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5332 | } |
5333 | ||
90e759d1 | 5334 | |
b481de9c | 5335 | /** |
bb8c093b | 5336 | * iwl4965_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5337 | * |
5338 | * Copy into buffers for card to fetch via bus-mastering | |
5339 | */ | |
c79dd5b5 | 5340 | static int iwl4965_read_ucode(struct iwl_priv *priv) |
b481de9c | 5341 | { |
bb8c093b | 5342 | struct iwl4965_ucode *ucode; |
90e759d1 | 5343 | int ret; |
b481de9c | 5344 | const struct firmware *ucode_raw; |
4bf775cd | 5345 | const char *name = priv->cfg->fw_name; |
b481de9c ZY |
5346 | u8 *src; |
5347 | size_t len; | |
5348 | u32 ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
5349 | ||
5350 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5351 | * request_firmware() is synchronous, file is in memory on return. */ | |
90e759d1 TW |
5352 | ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev); |
5353 | if (ret < 0) { | |
5354 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5355 | name, ret); | |
b481de9c ZY |
5356 | goto error; |
5357 | } | |
5358 | ||
5359 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5360 | name, ucode_raw->size); | |
5361 | ||
5362 | /* Make sure that we got at least our header! */ | |
5363 | if (ucode_raw->size < sizeof(*ucode)) { | |
5364 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5365 | ret = -EINVAL; |
b481de9c ZY |
5366 | goto err_release; |
5367 | } | |
5368 | ||
5369 | /* Data from ucode file: header followed by uCode images */ | |
5370 | ucode = (void *)ucode_raw->data; | |
5371 | ||
5372 | ver = le32_to_cpu(ucode->ver); | |
5373 | inst_size = le32_to_cpu(ucode->inst_size); | |
5374 | data_size = le32_to_cpu(ucode->data_size); | |
5375 | init_size = le32_to_cpu(ucode->init_size); | |
5376 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5377 | boot_size = le32_to_cpu(ucode->boot_size); | |
5378 | ||
5379 | IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver); | |
5380 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", | |
5381 | inst_size); | |
5382 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", | |
5383 | data_size); | |
5384 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", | |
5385 | init_size); | |
5386 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", | |
5387 | init_data_size); | |
5388 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", | |
5389 | boot_size); | |
5390 | ||
5391 | /* Verify size of file vs. image size info in file's header */ | |
5392 | if (ucode_raw->size < sizeof(*ucode) + | |
5393 | inst_size + data_size + init_size + | |
5394 | init_data_size + boot_size) { | |
5395 | ||
5396 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5397 | (int)ucode_raw->size); | |
90e759d1 | 5398 | ret = -EINVAL; |
b481de9c ZY |
5399 | goto err_release; |
5400 | } | |
5401 | ||
5402 | /* Verify that uCode images will fit in card's SRAM */ | |
5403 | if (inst_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5404 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5405 | inst_size); | |
5406 | ret = -EINVAL; | |
b481de9c ZY |
5407 | goto err_release; |
5408 | } | |
5409 | ||
5410 | if (data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5411 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5412 | data_size); | |
5413 | ret = -EINVAL; | |
b481de9c ZY |
5414 | goto err_release; |
5415 | } | |
5416 | if (init_size > IWL_MAX_INST_SIZE) { | |
5417 | IWL_DEBUG_INFO | |
90e759d1 TW |
5418 | ("uCode init instr len %d too large to fit in\n", |
5419 | init_size); | |
5420 | ret = -EINVAL; | |
b481de9c ZY |
5421 | goto err_release; |
5422 | } | |
5423 | if (init_data_size > IWL_MAX_DATA_SIZE) { | |
5424 | IWL_DEBUG_INFO | |
90e759d1 TW |
5425 | ("uCode init data len %d too large to fit in\n", |
5426 | init_data_size); | |
5427 | ret = -EINVAL; | |
b481de9c ZY |
5428 | goto err_release; |
5429 | } | |
5430 | if (boot_size > IWL_MAX_BSM_SIZE) { | |
5431 | IWL_DEBUG_INFO | |
90e759d1 TW |
5432 | ("uCode boot instr len %d too large to fit in\n", |
5433 | boot_size); | |
5434 | ret = -EINVAL; | |
b481de9c ZY |
5435 | goto err_release; |
5436 | } | |
5437 | ||
5438 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5439 | ||
5440 | /* Runtime instructions and 2 copies of data: | |
5441 | * 1) unmodified from disk | |
5442 | * 2) backup cache for save/restore during power-downs */ | |
5443 | priv->ucode_code.len = inst_size; | |
98c92211 | 5444 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5445 | |
5446 | priv->ucode_data.len = data_size; | |
98c92211 | 5447 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5448 | |
5449 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5450 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c ZY |
5451 | |
5452 | /* Initialization instructions and data */ | |
90e759d1 TW |
5453 | if (init_size && init_data_size) { |
5454 | priv->ucode_init.len = init_size; | |
98c92211 | 5455 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5456 | |
5457 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5458 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5459 | |
5460 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5461 | goto err_pci_alloc; | |
5462 | } | |
b481de9c ZY |
5463 | |
5464 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5465 | if (boot_size) { |
5466 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5467 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5468 | |
90e759d1 TW |
5469 | if (!priv->ucode_boot.v_addr) |
5470 | goto err_pci_alloc; | |
5471 | } | |
b481de9c ZY |
5472 | |
5473 | /* Copy images into buffers for card's bus-master reads ... */ | |
5474 | ||
5475 | /* Runtime instructions (first block of data in file) */ | |
5476 | src = &ucode->data[0]; | |
5477 | len = priv->ucode_code.len; | |
90e759d1 | 5478 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5479 | memcpy(priv->ucode_code.v_addr, src, len); |
5480 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5481 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5482 | ||
5483 | /* Runtime data (2nd block) | |
bb8c093b | 5484 | * NOTE: Copy into backup buffer will be done in iwl4965_up() */ |
b481de9c ZY |
5485 | src = &ucode->data[inst_size]; |
5486 | len = priv->ucode_data.len; | |
90e759d1 | 5487 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5488 | memcpy(priv->ucode_data.v_addr, src, len); |
5489 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5490 | ||
5491 | /* Initialization instructions (3rd block) */ | |
5492 | if (init_size) { | |
5493 | src = &ucode->data[inst_size + data_size]; | |
5494 | len = priv->ucode_init.len; | |
90e759d1 TW |
5495 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5496 | len); | |
b481de9c ZY |
5497 | memcpy(priv->ucode_init.v_addr, src, len); |
5498 | } | |
5499 | ||
5500 | /* Initialization data (4th block) */ | |
5501 | if (init_data_size) { | |
5502 | src = &ucode->data[inst_size + data_size + init_size]; | |
5503 | len = priv->ucode_init_data.len; | |
90e759d1 TW |
5504 | IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n", |
5505 | len); | |
b481de9c ZY |
5506 | memcpy(priv->ucode_init_data.v_addr, src, len); |
5507 | } | |
5508 | ||
5509 | /* Bootstrap instructions (5th block) */ | |
5510 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5511 | len = priv->ucode_boot.len; | |
90e759d1 | 5512 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
5513 | memcpy(priv->ucode_boot.v_addr, src, len); |
5514 | ||
5515 | /* We have our copies now, allow OS release its copies */ | |
5516 | release_firmware(ucode_raw); | |
5517 | return 0; | |
5518 | ||
5519 | err_pci_alloc: | |
5520 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5521 | ret = -ENOMEM; |
bb8c093b | 5522 | iwl4965_dealloc_ucode_pci(priv); |
b481de9c ZY |
5523 | |
5524 | err_release: | |
5525 | release_firmware(ucode_raw); | |
5526 | ||
5527 | error: | |
90e759d1 | 5528 | return ret; |
b481de9c ZY |
5529 | } |
5530 | ||
5531 | ||
5532 | /** | |
bb8c093b | 5533 | * iwl4965_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5534 | * |
5535 | * Tell initialization uCode where to find runtime uCode. | |
5536 | * | |
5537 | * BSM registers initially contain pointers to initialization uCode. | |
5538 | * We need to replace them to load runtime uCode inst and data, | |
5539 | * and to save runtime data when powering down. | |
5540 | */ | |
c79dd5b5 | 5541 | static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
5542 | { |
5543 | dma_addr_t pinst; | |
5544 | dma_addr_t pdata; | |
5545 | int rc = 0; | |
5546 | unsigned long flags; | |
5547 | ||
5548 | /* bits 35:4 for 4965 */ | |
5549 | pinst = priv->ucode_code.p_addr >> 4; | |
5550 | pdata = priv->ucode_data_backup.p_addr >> 4; | |
5551 | ||
5552 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 5553 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5554 | if (rc) { |
5555 | spin_unlock_irqrestore(&priv->lock, flags); | |
5556 | return rc; | |
5557 | } | |
5558 | ||
5559 | /* Tell bootstrap uCode where to find image to load */ | |
3395f6e9 TW |
5560 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5561 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5562 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5563 | priv->ucode_data.len); |
5564 | ||
5565 | /* Inst bytecount must be last to set up, bit 31 signals uCode | |
5566 | * that all new ptr/size info is in place */ | |
3395f6e9 | 5567 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5568 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5569 | ||
3395f6e9 | 5570 | iwl_release_nic_access(priv); |
b481de9c ZY |
5571 | |
5572 | spin_unlock_irqrestore(&priv->lock, flags); | |
5573 | ||
5574 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5575 | ||
5576 | return rc; | |
5577 | } | |
5578 | ||
5579 | /** | |
bb8c093b | 5580 | * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5581 | * |
5582 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5583 | * | |
5584 | * The 4965 "initialize" ALIVE reply contains calibration data for: | |
5585 | * Voltage, temperature, and MIMO tx gain correction, now stored in priv | |
5586 | * (3945 does not contain this data). | |
5587 | * | |
5588 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
5589 | */ | |
c79dd5b5 | 5590 | static void iwl4965_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5591 | { |
5592 | /* Check alive response for "valid" sign from uCode */ | |
5593 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5594 | /* We had an error bringing up the hardware, so take it | |
5595 | * all the way back down so we can try again */ | |
5596 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5597 | goto restart; | |
5598 | } | |
5599 | ||
5600 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5601 | * This is a paranoid check, because we would not have gotten the | |
5602 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5603 | if (iwl4965_verify_ucode(priv)) { |
b481de9c ZY |
5604 | /* Runtime instruction load was bad; |
5605 | * take it all the way back down so we can try again */ | |
5606 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5607 | goto restart; | |
5608 | } | |
5609 | ||
5610 | /* Calculate temperature */ | |
5611 | priv->temperature = iwl4965_get_temperature(priv); | |
5612 | ||
5613 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5614 | * load and launch runtime uCode, which will send us another "Alive" | |
5615 | * notification. */ | |
5616 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5617 | if (iwl4965_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5618 | /* Runtime instruction load won't happen; |
5619 | * take it all the way back down so we can try again */ | |
5620 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5621 | goto restart; | |
5622 | } | |
5623 | return; | |
5624 | ||
5625 | restart: | |
5626 | queue_work(priv->workqueue, &priv->restart); | |
5627 | } | |
5628 | ||
5629 | ||
5630 | /** | |
bb8c093b | 5631 | * iwl4965_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5632 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5633 | * Alive gets handled by iwl4965_init_alive_start()). |
b481de9c | 5634 | */ |
c79dd5b5 | 5635 | static void iwl4965_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5636 | { |
5637 | int rc = 0; | |
5638 | ||
5639 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5640 | ||
5641 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5642 | /* We had an error bringing up the hardware, so take it | |
5643 | * all the way back down so we can try again */ | |
5644 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5645 | goto restart; | |
5646 | } | |
5647 | ||
5648 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5649 | * This is a paranoid check, because we would not have gotten the | |
5650 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5651 | if (iwl4965_verify_ucode(priv)) { |
b481de9c ZY |
5652 | /* Runtime instruction load was bad; |
5653 | * take it all the way back down so we can try again */ | |
5654 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5655 | goto restart; | |
5656 | } | |
5657 | ||
bf85ea4f | 5658 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5659 | |
5660 | rc = iwl4965_alive_notify(priv); | |
5661 | if (rc) { | |
5662 | IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n", | |
5663 | rc); | |
5664 | goto restart; | |
5665 | } | |
5666 | ||
9fbab516 | 5667 | /* After the ALIVE response, we can send host commands to 4965 uCode */ |
b481de9c ZY |
5668 | set_bit(STATUS_ALIVE, &priv->status); |
5669 | ||
5670 | /* Clear out the uCode error bit if it is set */ | |
5671 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5672 | ||
fee1247a | 5673 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
5674 | return; |
5675 | ||
5a66926a | 5676 | ieee80211_start_queues(priv->hw); |
b481de9c ZY |
5677 | |
5678 | priv->active_rate = priv->rates_mask; | |
5679 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5680 | ||
bb8c093b | 5681 | iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5682 | |
3109ece1 | 5683 | if (iwl_is_associated(priv)) { |
bb8c093b CH |
5684 | struct iwl4965_rxon_cmd *active_rxon = |
5685 | (struct iwl4965_rxon_cmd *)(&priv->active_rxon); | |
b481de9c ZY |
5686 | |
5687 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
5688 | sizeof(priv->staging_rxon)); | |
5689 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5690 | } else { | |
5691 | /* Initialize our rx_config data */ | |
bb8c093b | 5692 | iwl4965_connection_init_rx_config(priv); |
b481de9c ZY |
5693 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
5694 | } | |
5695 | ||
9fbab516 | 5696 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5697 | iwl4965_send_bt_config(priv); |
b481de9c ZY |
5698 | |
5699 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5700 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
5701 | |
5702 | /* At this point, the NIC is initialized and operational */ | |
5703 | priv->notif_missed_beacons = 0; | |
b481de9c ZY |
5704 | |
5705 | iwl4965_rf_kill_ct_config(priv); | |
5a66926a | 5706 | |
fe00b5a5 RC |
5707 | iwl_leds_register(priv); |
5708 | ||
b481de9c | 5709 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5710 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5711 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5712 | |
5713 | if (priv->error_recovering) | |
bb8c093b | 5714 | iwl4965_error_recovery(priv); |
b481de9c | 5715 | |
c8381fdc | 5716 | iwlcore_low_level_notify(priv, IWLCORE_START_EVT); |
84363e6e | 5717 | ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); |
b481de9c ZY |
5718 | return; |
5719 | ||
5720 | restart: | |
5721 | queue_work(priv->workqueue, &priv->restart); | |
5722 | } | |
5723 | ||
c79dd5b5 | 5724 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 5725 | |
c79dd5b5 | 5726 | static void __iwl4965_down(struct iwl_priv *priv) |
b481de9c ZY |
5727 | { |
5728 | unsigned long flags; | |
5729 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5730 | struct ieee80211_conf *conf = NULL; | |
5731 | ||
5732 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5733 | ||
5734 | conf = ieee80211_get_hw_conf(priv->hw); | |
5735 | ||
5736 | if (!exit_pending) | |
5737 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5738 | ||
ab53d8af MA |
5739 | iwl_leds_unregister(priv); |
5740 | ||
c8381fdc MA |
5741 | iwlcore_low_level_notify(priv, IWLCORE_STOP_EVT); |
5742 | ||
bf85ea4f | 5743 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5744 | |
5745 | /* Unblock any waiting calls */ | |
5746 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5747 | ||
b481de9c ZY |
5748 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5749 | * exiting the module */ | |
5750 | if (!exit_pending) | |
5751 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5752 | ||
5753 | /* stop and reset the on-board processor */ | |
3395f6e9 | 5754 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5755 | |
5756 | /* tell the device to stop sending interrupts */ | |
0359facc | 5757 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5758 | iwl4965_disable_interrupts(priv); |
0359facc MA |
5759 | spin_unlock_irqrestore(&priv->lock, flags); |
5760 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5761 | |
5762 | if (priv->mac80211_registered) | |
5763 | ieee80211_stop_queues(priv->hw); | |
5764 | ||
bb8c093b | 5765 | /* If we have not previously called iwl4965_init() then |
b481de9c | 5766 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
fee1247a | 5767 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
5768 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5769 | STATUS_RF_KILL_HW | | |
5770 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5771 | STATUS_RF_KILL_SW | | |
9788864e RC |
5772 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5773 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5774 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5775 | STATUS_IN_SUSPEND; | |
5776 | goto exit; | |
5777 | } | |
5778 | ||
5779 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5780 | * SUSPEND bits and continue taking the NIC down. */ | |
5781 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5782 | STATUS_RF_KILL_HW | | |
5783 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5784 | STATUS_RF_KILL_SW | | |
9788864e RC |
5785 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5786 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5787 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5788 | STATUS_IN_SUSPEND | | |
5789 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
5790 | STATUS_FW_ERROR; | |
5791 | ||
5792 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 5793 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 5794 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5795 | spin_unlock_irqrestore(&priv->lock, flags); |
5796 | ||
bb8c093b CH |
5797 | iwl4965_hw_txq_ctx_stop(priv); |
5798 | iwl4965_hw_rxq_stop(priv); | |
b481de9c ZY |
5799 | |
5800 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
5801 | if (!iwl_grab_nic_access(priv)) { |
5802 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5803 | APMG_CLK_VAL_DMA_CLK_RQT); |
3395f6e9 | 5804 | iwl_release_nic_access(priv); |
b481de9c ZY |
5805 | } |
5806 | spin_unlock_irqrestore(&priv->lock, flags); | |
5807 | ||
5808 | udelay(5); | |
5809 | ||
bb8c093b | 5810 | iwl4965_hw_nic_stop_master(priv); |
3395f6e9 | 5811 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
bb8c093b | 5812 | iwl4965_hw_nic_reset(priv); |
b481de9c ZY |
5813 | |
5814 | exit: | |
bb8c093b | 5815 | memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp)); |
b481de9c ZY |
5816 | |
5817 | if (priv->ibss_beacon) | |
5818 | dev_kfree_skb(priv->ibss_beacon); | |
5819 | priv->ibss_beacon = NULL; | |
5820 | ||
5821 | /* clear out any free frames */ | |
bb8c093b | 5822 | iwl4965_clear_free_frames(priv); |
b481de9c ZY |
5823 | } |
5824 | ||
c79dd5b5 | 5825 | static void iwl4965_down(struct iwl_priv *priv) |
b481de9c ZY |
5826 | { |
5827 | mutex_lock(&priv->mutex); | |
bb8c093b | 5828 | __iwl4965_down(priv); |
b481de9c | 5829 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5830 | |
bb8c093b | 5831 | iwl4965_cancel_deferred_work(priv); |
b481de9c ZY |
5832 | } |
5833 | ||
5834 | #define MAX_HW_RESTARTS 5 | |
5835 | ||
c79dd5b5 | 5836 | static int __iwl4965_up(struct iwl_priv *priv) |
b481de9c ZY |
5837 | { |
5838 | int rc, i; | |
b481de9c ZY |
5839 | |
5840 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5841 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
5842 | return -EIO; | |
5843 | } | |
5844 | ||
5845 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
5846 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
5847 | "parameter)\n"); | |
ad97edd2 | 5848 | iwl_rfkill_set_hw_state(priv); |
e655b9f0 ZY |
5849 | return -ENODEV; |
5850 | } | |
5851 | ||
e903fbd4 RC |
5852 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
5853 | IWL_ERROR("ucode not available for device bringup\n"); | |
5854 | return -EIO; | |
5855 | } | |
5856 | ||
e655b9f0 | 5857 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3395f6e9 | 5858 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
5859 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
5860 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5861 | else { | |
5862 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5863 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
ad97edd2 | 5864 | iwl_rfkill_set_hw_state(priv); |
e655b9f0 ZY |
5865 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); |
5866 | return -ENODEV; | |
5867 | } | |
b481de9c ZY |
5868 | } |
5869 | ||
ad97edd2 | 5870 | iwl_rfkill_set_hw_state(priv); |
3395f6e9 | 5871 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 5872 | |
bb8c093b | 5873 | rc = iwl4965_hw_nic_init(priv); |
b481de9c ZY |
5874 | if (rc) { |
5875 | IWL_ERROR("Unable to int nic\n"); | |
5876 | return rc; | |
5877 | } | |
5878 | ||
5879 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
5880 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5881 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
5882 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
5883 | ||
5884 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 5885 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
bb8c093b | 5886 | iwl4965_enable_interrupts(priv); |
b481de9c ZY |
5887 | |
5888 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
5889 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5890 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
5891 | |
5892 | /* Copy original ucode data image from disk into backup cache. | |
5893 | * This will be used to initialize the on-board processor's | |
5894 | * data SRAM for a clean start when the runtime program first loads. */ | |
5895 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 5896 | priv->ucode_data.len); |
b481de9c | 5897 | |
e655b9f0 ZY |
5898 | /* We return success when we resume from suspend and rf_kill is on. */ |
5899 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
b481de9c | 5900 | return 0; |
b481de9c ZY |
5901 | |
5902 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | |
5903 | ||
bf85ea4f | 5904 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5905 | |
5906 | /* load bootstrap state machine, | |
5907 | * load bootstrap program into processor's memory, | |
5908 | * prepare to load the "initialize" uCode */ | |
bb8c093b | 5909 | rc = iwl4965_load_bsm(priv); |
b481de9c ZY |
5910 | |
5911 | if (rc) { | |
5912 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc); | |
5913 | continue; | |
5914 | } | |
5915 | ||
5916 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 5917 | iwl4965_nic_start(priv); |
b481de9c | 5918 | |
b481de9c ZY |
5919 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
5920 | ||
5921 | return 0; | |
5922 | } | |
5923 | ||
5924 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 5925 | __iwl4965_down(priv); |
b481de9c ZY |
5926 | |
5927 | /* tried to restart and config the device for as long as our | |
5928 | * patience could withstand */ | |
5929 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
5930 | return -EIO; | |
5931 | } | |
5932 | ||
5933 | ||
5934 | /***************************************************************************** | |
5935 | * | |
5936 | * Workqueue callbacks | |
5937 | * | |
5938 | *****************************************************************************/ | |
5939 | ||
bb8c093b | 5940 | static void iwl4965_bg_init_alive_start(struct work_struct *data) |
b481de9c | 5941 | { |
c79dd5b5 TW |
5942 | struct iwl_priv *priv = |
5943 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
5944 | |
5945 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5946 | return; | |
5947 | ||
5948 | mutex_lock(&priv->mutex); | |
bb8c093b | 5949 | iwl4965_init_alive_start(priv); |
b481de9c ZY |
5950 | mutex_unlock(&priv->mutex); |
5951 | } | |
5952 | ||
bb8c093b | 5953 | static void iwl4965_bg_alive_start(struct work_struct *data) |
b481de9c | 5954 | { |
c79dd5b5 TW |
5955 | struct iwl_priv *priv = |
5956 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
5957 | |
5958 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5959 | return; | |
5960 | ||
5961 | mutex_lock(&priv->mutex); | |
bb8c093b | 5962 | iwl4965_alive_start(priv); |
b481de9c ZY |
5963 | mutex_unlock(&priv->mutex); |
5964 | } | |
5965 | ||
bb8c093b | 5966 | static void iwl4965_bg_rf_kill(struct work_struct *work) |
b481de9c | 5967 | { |
c79dd5b5 | 5968 | struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill); |
b481de9c ZY |
5969 | |
5970 | wake_up_interruptible(&priv->wait_command_queue); | |
5971 | ||
5972 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5973 | return; | |
5974 | ||
5975 | mutex_lock(&priv->mutex); | |
5976 | ||
fee1247a | 5977 | if (!iwl_is_rfkill(priv)) { |
b481de9c ZY |
5978 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
5979 | "HW and/or SW RF Kill no longer active, restarting " | |
5980 | "device\n"); | |
5981 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5982 | queue_work(priv->workqueue, &priv->restart); | |
5983 | } else { | |
ad97edd2 MA |
5984 | /* make sure mac80211 stop sending Tx frame */ |
5985 | if (priv->mac80211_registered) | |
5986 | ieee80211_stop_queues(priv->hw); | |
b481de9c ZY |
5987 | |
5988 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5989 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
5990 | "disabled by SW switch\n"); | |
5991 | else | |
5992 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
5993 | "Kill switch must be turned off for " | |
5994 | "wireless networking to work.\n"); | |
5995 | } | |
ad97edd2 MA |
5996 | iwl_rfkill_set_hw_state(priv); |
5997 | ||
b481de9c ZY |
5998 | mutex_unlock(&priv->mutex); |
5999 | } | |
6000 | ||
6001 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) | |
6002 | ||
bb8c093b | 6003 | static void iwl4965_bg_scan_check(struct work_struct *data) |
b481de9c | 6004 | { |
c79dd5b5 TW |
6005 | struct iwl_priv *priv = |
6006 | container_of(data, struct iwl_priv, scan_check.work); | |
b481de9c ZY |
6007 | |
6008 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6009 | return; | |
6010 | ||
6011 | mutex_lock(&priv->mutex); | |
6012 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
6013 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6014 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
6015 | "Scan completion watchdog resetting adapter (%dms)\n", | |
6016 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
052c4b9f | 6017 | |
b481de9c | 6018 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 6019 | iwl4965_send_scan_abort(priv); |
b481de9c ZY |
6020 | } |
6021 | mutex_unlock(&priv->mutex); | |
6022 | } | |
6023 | ||
bb8c093b | 6024 | static void iwl4965_bg_request_scan(struct work_struct *data) |
b481de9c | 6025 | { |
c79dd5b5 TW |
6026 | struct iwl_priv *priv = |
6027 | container_of(data, struct iwl_priv, request_scan); | |
857485c0 | 6028 | struct iwl_host_cmd cmd = { |
b481de9c | 6029 | .id = REPLY_SCAN_CMD, |
bb8c093b | 6030 | .len = sizeof(struct iwl4965_scan_cmd), |
b481de9c ZY |
6031 | .meta.flags = CMD_SIZE_HUGE, |
6032 | }; | |
bb8c093b | 6033 | struct iwl4965_scan_cmd *scan; |
b481de9c | 6034 | struct ieee80211_conf *conf = NULL; |
78330fdd | 6035 | u16 cmd_len; |
8318d78a | 6036 | enum ieee80211_band band; |
78330fdd | 6037 | u8 direct_mask; |
857485c0 | 6038 | int ret = 0; |
b481de9c ZY |
6039 | |
6040 | conf = ieee80211_get_hw_conf(priv->hw); | |
6041 | ||
6042 | mutex_lock(&priv->mutex); | |
6043 | ||
fee1247a | 6044 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
6045 | IWL_WARNING("request scan called when driver not ready.\n"); |
6046 | goto done; | |
6047 | } | |
6048 | ||
6049 | /* Make sure the scan wasn't cancelled before this queued work | |
6050 | * was given the chance to run... */ | |
6051 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
6052 | goto done; | |
6053 | ||
6054 | /* This should never be called or scheduled if there is currently | |
6055 | * a scan active in the hardware. */ | |
6056 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
6057 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
6058 | "Ignoring second request.\n"); | |
857485c0 | 6059 | ret = -EIO; |
b481de9c ZY |
6060 | goto done; |
6061 | } | |
6062 | ||
6063 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6064 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
6065 | goto done; | |
6066 | } | |
6067 | ||
6068 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6069 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
6070 | goto done; | |
6071 | } | |
6072 | ||
fee1247a | 6073 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
6074 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
6075 | goto done; | |
6076 | } | |
6077 | ||
6078 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6079 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
6080 | goto done; | |
6081 | } | |
6082 | ||
6083 | if (!priv->scan_bands) { | |
6084 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
6085 | goto done; | |
6086 | } | |
6087 | ||
6088 | if (!priv->scan) { | |
bb8c093b | 6089 | priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) + |
b481de9c ZY |
6090 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
6091 | if (!priv->scan) { | |
857485c0 | 6092 | ret = -ENOMEM; |
b481de9c ZY |
6093 | goto done; |
6094 | } | |
6095 | } | |
6096 | scan = priv->scan; | |
bb8c093b | 6097 | memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
6098 | |
6099 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
6100 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
6101 | ||
3109ece1 | 6102 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
6103 | u16 interval = 0; |
6104 | u32 extra; | |
6105 | u32 suspend_time = 100; | |
6106 | u32 scan_suspend_time = 100; | |
6107 | unsigned long flags; | |
6108 | ||
6109 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
6110 | ||
6111 | spin_lock_irqsave(&priv->lock, flags); | |
6112 | interval = priv->beacon_int; | |
6113 | spin_unlock_irqrestore(&priv->lock, flags); | |
6114 | ||
6115 | scan->suspend_time = 0; | |
052c4b9f | 6116 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
6117 | if (!interval) |
6118 | interval = suspend_time; | |
6119 | ||
6120 | extra = (suspend_time / interval) << 22; | |
6121 | scan_suspend_time = (extra | | |
6122 | ((suspend_time % interval) * 1024)); | |
6123 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
6124 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
6125 | scan_suspend_time, interval); | |
6126 | } | |
6127 | ||
6128 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
6129 | if (priv->one_direct_scan) { | |
6130 | IWL_DEBUG_SCAN | |
6131 | ("Kicking off one direct scan for '%s'\n", | |
bb8c093b | 6132 | iwl4965_escape_essid(priv->direct_ssid, |
b481de9c ZY |
6133 | priv->direct_ssid_len)); |
6134 | scan->direct_scan[0].id = WLAN_EID_SSID; | |
6135 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
6136 | memcpy(scan->direct_scan[0].ssid, | |
6137 | priv->direct_ssid, priv->direct_ssid_len); | |
6138 | direct_mask = 1; | |
3109ece1 | 6139 | } else if (!iwl_is_associated(priv) && priv->essid_len) { |
b481de9c ZY |
6140 | scan->direct_scan[0].id = WLAN_EID_SSID; |
6141 | scan->direct_scan[0].len = priv->essid_len; | |
6142 | memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len); | |
6143 | direct_mask = 1; | |
857485c0 | 6144 | } else { |
b481de9c | 6145 | direct_mask = 0; |
857485c0 | 6146 | } |
b481de9c | 6147 | |
b481de9c ZY |
6148 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
6149 | scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id; | |
6150 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
6151 | ||
b481de9c ZY |
6152 | |
6153 | switch (priv->scan_bands) { | |
6154 | case 2: | |
6155 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
6156 | scan->tx_cmd.rate_n_flags = | |
bb8c093b | 6157 | iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP, |
b481de9c ZY |
6158 | RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK); |
6159 | ||
6160 | scan->good_CRC_th = 0; | |
8318d78a | 6161 | band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
6162 | break; |
6163 | ||
6164 | case 1: | |
6165 | scan->tx_cmd.rate_n_flags = | |
bb8c093b | 6166 | iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP, |
b481de9c ZY |
6167 | RATE_MCS_ANT_B_MSK); |
6168 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 6169 | band = IEEE80211_BAND_5GHZ; |
b481de9c ZY |
6170 | break; |
6171 | ||
6172 | default: | |
6173 | IWL_WARNING("Invalid scan band count\n"); | |
6174 | goto done; | |
6175 | } | |
6176 | ||
78330fdd TW |
6177 | /* We don't build a direct scan probe request; the uCode will do |
6178 | * that based on the direct_mask added to each channel entry */ | |
6179 | cmd_len = iwl4965_fill_probe_req(priv, band, | |
6180 | (struct ieee80211_mgmt *)scan->data, | |
6181 | IWL_MAX_SCAN_SIZE - sizeof(*scan), 0); | |
6182 | ||
6183 | scan->tx_cmd.len = cpu_to_le16(cmd_len); | |
b481de9c ZY |
6184 | /* select Rx chains */ |
6185 | ||
6186 | /* Force use of chains B and C (0x6) for scan Rx. | |
6187 | * Avoid A (0x1) because of its off-channel reception on A-band. | |
6188 | * MIMO is not used here, but value is required to make uCode happy. */ | |
6189 | scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK | | |
6190 | cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) | | |
6191 | (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) | | |
6192 | (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS)); | |
6193 | ||
6194 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) | |
6195 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; | |
6196 | ||
26c0f03f | 6197 | if (direct_mask) { |
b481de9c ZY |
6198 | IWL_DEBUG_SCAN |
6199 | ("Initiating direct scan for %s.\n", | |
bb8c093b | 6200 | iwl4965_escape_essid(priv->essid, priv->essid_len)); |
26c0f03f RC |
6201 | scan->channel_count = |
6202 | iwl4965_get_channels_for_scan( | |
6203 | priv, band, 1, /* active */ | |
6204 | direct_mask, | |
6205 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
6206 | } else { | |
b481de9c | 6207 | IWL_DEBUG_SCAN("Initiating indirect scan.\n"); |
26c0f03f RC |
6208 | scan->channel_count = |
6209 | iwl4965_get_channels_for_scan( | |
6210 | priv, band, 0, /* passive */ | |
6211 | direct_mask, | |
6212 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
6213 | } | |
b481de9c ZY |
6214 | |
6215 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + | |
bb8c093b | 6216 | scan->channel_count * sizeof(struct iwl4965_scan_channel); |
b481de9c ZY |
6217 | cmd.data = scan; |
6218 | scan->len = cpu_to_le16(cmd.len); | |
6219 | ||
6220 | set_bit(STATUS_SCAN_HW, &priv->status); | |
857485c0 TW |
6221 | ret = iwl_send_cmd_sync(priv, &cmd); |
6222 | if (ret) | |
b481de9c ZY |
6223 | goto done; |
6224 | ||
6225 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
6226 | IWL_SCAN_CHECK_WATCHDOG); | |
6227 | ||
6228 | mutex_unlock(&priv->mutex); | |
6229 | return; | |
6230 | ||
6231 | done: | |
01ebd063 | 6232 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
6233 | queue_work(priv->workqueue, &priv->scan_completed); |
6234 | mutex_unlock(&priv->mutex); | |
6235 | } | |
6236 | ||
bb8c093b | 6237 | static void iwl4965_bg_up(struct work_struct *data) |
b481de9c | 6238 | { |
c79dd5b5 | 6239 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
6240 | |
6241 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6242 | return; | |
6243 | ||
6244 | mutex_lock(&priv->mutex); | |
bb8c093b | 6245 | __iwl4965_up(priv); |
b481de9c ZY |
6246 | mutex_unlock(&priv->mutex); |
6247 | } | |
6248 | ||
bb8c093b | 6249 | static void iwl4965_bg_restart(struct work_struct *data) |
b481de9c | 6250 | { |
c79dd5b5 | 6251 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
6252 | |
6253 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6254 | return; | |
6255 | ||
bb8c093b | 6256 | iwl4965_down(priv); |
b481de9c ZY |
6257 | queue_work(priv->workqueue, &priv->up); |
6258 | } | |
6259 | ||
bb8c093b | 6260 | static void iwl4965_bg_rx_replenish(struct work_struct *data) |
b481de9c | 6261 | { |
c79dd5b5 TW |
6262 | struct iwl_priv *priv = |
6263 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
6264 | |
6265 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6266 | return; | |
6267 | ||
6268 | mutex_lock(&priv->mutex); | |
bb8c093b | 6269 | iwl4965_rx_replenish(priv); |
b481de9c ZY |
6270 | mutex_unlock(&priv->mutex); |
6271 | } | |
6272 | ||
7878a5a4 MA |
6273 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
6274 | ||
bb8c093b | 6275 | static void iwl4965_bg_post_associate(struct work_struct *data) |
b481de9c | 6276 | { |
c79dd5b5 | 6277 | struct iwl_priv *priv = container_of(data, struct iwl_priv, |
b481de9c | 6278 | post_associate.work); |
b481de9c | 6279 | struct ieee80211_conf *conf = NULL; |
857485c0 | 6280 | int ret = 0; |
0795af57 | 6281 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6282 | |
6283 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6284 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | |
6285 | return; | |
6286 | } | |
6287 | ||
0795af57 JP |
6288 | IWL_DEBUG_ASSOC("Associated as %d to: %s\n", |
6289 | priv->assoc_id, | |
6290 | print_mac(mac, priv->active_rxon.bssid_addr)); | |
b481de9c ZY |
6291 | |
6292 | ||
6293 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6294 | return; | |
6295 | ||
6296 | mutex_lock(&priv->mutex); | |
6297 | ||
32bfd35d | 6298 | if (!priv->vif || !priv->is_open) { |
948c171c MA |
6299 | mutex_unlock(&priv->mutex); |
6300 | return; | |
6301 | } | |
bb8c093b | 6302 | iwl4965_scan_cancel_timeout(priv, 200); |
052c4b9f | 6303 | |
b481de9c ZY |
6304 | conf = ieee80211_get_hw_conf(priv->hw); |
6305 | ||
6306 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6307 | iwl4965_commit_rxon(priv); |
b481de9c | 6308 | |
bb8c093b CH |
6309 | memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd)); |
6310 | iwl4965_setup_rxon_timing(priv); | |
857485c0 | 6311 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 6312 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 6313 | if (ret) |
b481de9c ZY |
6314 | IWL_WARNING("REPLY_RXON_TIMING failed - " |
6315 | "Attempting to continue.\n"); | |
6316 | ||
6317 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
6318 | ||
c8b0e6e1 | 6319 | #ifdef CONFIG_IWL4965_HT |
fd105e79 RR |
6320 | if (priv->current_ht_config.is_ht) |
6321 | iwl4965_set_rxon_ht(priv, &priv->current_ht_config); | |
c8b0e6e1 | 6322 | #endif /* CONFIG_IWL4965_HT*/ |
b481de9c ZY |
6323 | iwl4965_set_rxon_chain(priv); |
6324 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6325 | ||
6326 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6327 | priv->assoc_id, priv->beacon_int); | |
6328 | ||
6329 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6330 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6331 | else | |
6332 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6333 | ||
6334 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6335 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6336 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
6337 | else | |
6338 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6339 | ||
6340 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6341 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6342 | ||
6343 | } | |
6344 | ||
bb8c093b | 6345 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6346 | |
6347 | switch (priv->iw_mode) { | |
6348 | case IEEE80211_IF_TYPE_STA: | |
bb8c093b | 6349 | iwl4965_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6350 | break; |
6351 | ||
6352 | case IEEE80211_IF_TYPE_IBSS: | |
6353 | ||
6354 | /* clear out the station table */ | |
bf85ea4f | 6355 | iwlcore_clear_stations_table(priv); |
b481de9c | 6356 | |
bb8c093b CH |
6357 | iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); |
6358 | iwl4965_rxon_add_station(priv, priv->bssid, 0); | |
6359 | iwl4965_rate_scale_init(priv->hw, IWL_STA_ID); | |
6360 | iwl4965_send_beacon_cmd(priv); | |
b481de9c ZY |
6361 | |
6362 | break; | |
6363 | ||
6364 | default: | |
6365 | IWL_ERROR("%s Should not be called in %d mode\n", | |
6366 | __FUNCTION__, priv->iw_mode); | |
6367 | break; | |
6368 | } | |
6369 | ||
bb8c093b | 6370 | iwl4965_sequence_reset(priv); |
b481de9c | 6371 | |
c8b0e6e1 | 6372 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
6373 | /* Enable Rx differential gain and sensitivity calibrations */ |
6374 | iwl4965_chain_noise_reset(priv); | |
6375 | priv->start_calib = 1; | |
c8b0e6e1 | 6376 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
6377 | |
6378 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6379 | priv->assoc_station_added = 1; | |
6380 | ||
bb8c093b | 6381 | iwl4965_activate_qos(priv, 0); |
292ae174 | 6382 | |
7878a5a4 MA |
6383 | /* we have just associated, don't start scan too early */ |
6384 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
b481de9c ZY |
6385 | mutex_unlock(&priv->mutex); |
6386 | } | |
6387 | ||
bb8c093b | 6388 | static void iwl4965_bg_abort_scan(struct work_struct *work) |
b481de9c | 6389 | { |
c79dd5b5 | 6390 | struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan); |
b481de9c | 6391 | |
fee1247a | 6392 | if (!iwl_is_ready(priv)) |
b481de9c ZY |
6393 | return; |
6394 | ||
6395 | mutex_lock(&priv->mutex); | |
6396 | ||
6397 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6398 | iwl4965_send_scan_abort(priv); |
b481de9c ZY |
6399 | |
6400 | mutex_unlock(&priv->mutex); | |
6401 | } | |
6402 | ||
76bb77e0 ZY |
6403 | static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); |
6404 | ||
bb8c093b | 6405 | static void iwl4965_bg_scan_completed(struct work_struct *work) |
b481de9c | 6406 | { |
c79dd5b5 TW |
6407 | struct iwl_priv *priv = |
6408 | container_of(work, struct iwl_priv, scan_completed); | |
b481de9c ZY |
6409 | |
6410 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6411 | ||
6412 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6413 | return; | |
6414 | ||
a0646470 ZY |
6415 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
6416 | iwl4965_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw)); | |
76bb77e0 | 6417 | |
b481de9c ZY |
6418 | ieee80211_scan_completed(priv->hw); |
6419 | ||
6420 | /* Since setting the TXPOWER may have been deferred while | |
6421 | * performing the scan, fire one off */ | |
6422 | mutex_lock(&priv->mutex); | |
bb8c093b | 6423 | iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
6424 | mutex_unlock(&priv->mutex); |
6425 | } | |
6426 | ||
6427 | /***************************************************************************** | |
6428 | * | |
6429 | * mac80211 entry point functions | |
6430 | * | |
6431 | *****************************************************************************/ | |
6432 | ||
5a66926a ZY |
6433 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6434 | ||
bb8c093b | 6435 | static int iwl4965_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6436 | { |
c79dd5b5 | 6437 | struct iwl_priv *priv = hw->priv; |
5a66926a | 6438 | int ret; |
b481de9c ZY |
6439 | |
6440 | IWL_DEBUG_MAC80211("enter\n"); | |
6441 | ||
5a66926a ZY |
6442 | if (pci_enable_device(priv->pci_dev)) { |
6443 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6444 | return -ENODEV; | |
6445 | } | |
6446 | pci_restore_state(priv->pci_dev); | |
6447 | pci_enable_msi(priv->pci_dev); | |
6448 | ||
6449 | ret = request_irq(priv->pci_dev->irq, iwl4965_isr, IRQF_SHARED, | |
6450 | DRV_NAME, priv); | |
6451 | if (ret) { | |
6452 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6453 | goto out_disable_msi; | |
6454 | } | |
6455 | ||
b481de9c ZY |
6456 | /* we should be verifying the device is ready to be opened */ |
6457 | mutex_lock(&priv->mutex); | |
6458 | ||
5a66926a ZY |
6459 | memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd)); |
6460 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
6461 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 6462 | |
5a66926a ZY |
6463 | if (!priv->ucode_code.len) { |
6464 | ret = iwl4965_read_ucode(priv); | |
6465 | if (ret) { | |
6466 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6467 | mutex_unlock(&priv->mutex); | |
6468 | goto out_release_irq; | |
6469 | } | |
6470 | } | |
b481de9c | 6471 | |
e655b9f0 | 6472 | ret = __iwl4965_up(priv); |
5a66926a | 6473 | |
b481de9c | 6474 | mutex_unlock(&priv->mutex); |
5a66926a | 6475 | |
e655b9f0 ZY |
6476 | if (ret) |
6477 | goto out_release_irq; | |
6478 | ||
6479 | IWL_DEBUG_INFO("Start UP work done.\n"); | |
6480 | ||
6481 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6482 | return 0; | |
6483 | ||
5a66926a ZY |
6484 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6485 | * mac80211 will not be run successfully. */ | |
6486 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6487 | test_bit(STATUS_READY, &priv->status), | |
6488 | UCODE_READY_TIMEOUT); | |
6489 | if (!ret) { | |
6490 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6491 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6492 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6493 | ret = -ETIMEDOUT; | |
6494 | goto out_release_irq; | |
6495 | } | |
6496 | } | |
6497 | ||
e655b9f0 | 6498 | priv->is_open = 1; |
b481de9c ZY |
6499 | IWL_DEBUG_MAC80211("leave\n"); |
6500 | return 0; | |
5a66926a ZY |
6501 | |
6502 | out_release_irq: | |
6503 | free_irq(priv->pci_dev->irq, priv); | |
6504 | out_disable_msi: | |
6505 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6506 | pci_disable_device(priv->pci_dev); |
6507 | priv->is_open = 0; | |
6508 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6509 | return ret; |
b481de9c ZY |
6510 | } |
6511 | ||
bb8c093b | 6512 | static void iwl4965_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6513 | { |
c79dd5b5 | 6514 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6515 | |
6516 | IWL_DEBUG_MAC80211("enter\n"); | |
948c171c | 6517 | |
e655b9f0 ZY |
6518 | if (!priv->is_open) { |
6519 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6520 | return; | |
6521 | } | |
6522 | ||
b481de9c | 6523 | priv->is_open = 0; |
5a66926a | 6524 | |
fee1247a | 6525 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
6526 | /* stop mac, cancel any scan request and clear |
6527 | * RXON_FILTER_ASSOC_MSK BIT | |
6528 | */ | |
5a66926a ZY |
6529 | mutex_lock(&priv->mutex); |
6530 | iwl4965_scan_cancel_timeout(priv, 100); | |
6531 | cancel_delayed_work(&priv->post_associate); | |
fde3571f | 6532 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6533 | } |
6534 | ||
5a66926a ZY |
6535 | iwl4965_down(priv); |
6536 | ||
6537 | flush_workqueue(priv->workqueue); | |
6538 | free_irq(priv->pci_dev->irq, priv); | |
6539 | pci_disable_msi(priv->pci_dev); | |
6540 | pci_save_state(priv->pci_dev); | |
6541 | pci_disable_device(priv->pci_dev); | |
948c171c | 6542 | |
b481de9c | 6543 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6544 | } |
6545 | ||
bb8c093b | 6546 | static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
6547 | struct ieee80211_tx_control *ctl) |
6548 | { | |
c79dd5b5 | 6549 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6550 | |
6551 | IWL_DEBUG_MAC80211("enter\n"); | |
6552 | ||
6553 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | |
6554 | IWL_DEBUG_MAC80211("leave - monitor\n"); | |
6555 | return -1; | |
6556 | } | |
6557 | ||
6558 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | |
8318d78a | 6559 | ctl->tx_rate->bitrate); |
b481de9c | 6560 | |
bb8c093b | 6561 | if (iwl4965_tx_skb(priv, skb, ctl)) |
b481de9c ZY |
6562 | dev_kfree_skb_any(skb); |
6563 | ||
6564 | IWL_DEBUG_MAC80211("leave\n"); | |
6565 | return 0; | |
6566 | } | |
6567 | ||
bb8c093b | 6568 | static int iwl4965_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6569 | struct ieee80211_if_init_conf *conf) |
6570 | { | |
c79dd5b5 | 6571 | struct iwl_priv *priv = hw->priv; |
b481de9c | 6572 | unsigned long flags; |
0795af57 | 6573 | DECLARE_MAC_BUF(mac); |
b481de9c | 6574 | |
32bfd35d | 6575 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6576 | |
32bfd35d JB |
6577 | if (priv->vif) { |
6578 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
75849d28 | 6579 | return -EOPNOTSUPP; |
b481de9c ZY |
6580 | } |
6581 | ||
6582 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6583 | priv->vif = conf->vif; |
b481de9c ZY |
6584 | |
6585 | spin_unlock_irqrestore(&priv->lock, flags); | |
6586 | ||
6587 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6588 | |
6589 | if (conf->mac_addr) { | |
6590 | IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr)); | |
6591 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
6592 | } | |
b481de9c | 6593 | |
fee1247a | 6594 | if (iwl_is_ready(priv)) |
5a66926a ZY |
6595 | iwl4965_set_mode(priv, conf->type); |
6596 | ||
b481de9c ZY |
6597 | mutex_unlock(&priv->mutex); |
6598 | ||
5a66926a | 6599 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6600 | return 0; |
6601 | } | |
6602 | ||
6603 | /** | |
bb8c093b | 6604 | * iwl4965_mac_config - mac80211 config callback |
b481de9c ZY |
6605 | * |
6606 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6607 | * be set inappropriately and the driver currently sets the hardware up to | |
6608 | * use it whenever needed. | |
6609 | */ | |
bb8c093b | 6610 | static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
b481de9c | 6611 | { |
c79dd5b5 | 6612 | struct iwl_priv *priv = hw->priv; |
bf85ea4f | 6613 | const struct iwl_channel_info *ch_info; |
b481de9c | 6614 | unsigned long flags; |
76bb77e0 | 6615 | int ret = 0; |
b481de9c ZY |
6616 | |
6617 | mutex_lock(&priv->mutex); | |
8318d78a | 6618 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6619 | |
12342c47 ZY |
6620 | priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP); |
6621 | ||
fee1247a | 6622 | if (!iwl_is_ready(priv)) { |
b481de9c | 6623 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6624 | ret = -EIO; |
6625 | goto out; | |
b481de9c ZY |
6626 | } |
6627 | ||
1ea87396 | 6628 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && |
b481de9c | 6629 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6630 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6631 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6632 | mutex_unlock(&priv->mutex); |
a0646470 | 6633 | return 0; |
b481de9c ZY |
6634 | } |
6635 | ||
6636 | spin_lock_irqsave(&priv->lock, flags); | |
6637 | ||
8622e705 | 6638 | ch_info = iwl_get_channel_info(priv, conf->channel->band, |
8318d78a | 6639 | ieee80211_frequency_to_channel(conf->channel->center_freq)); |
b481de9c | 6640 | if (!is_channel_valid(ch_info)) { |
b481de9c ZY |
6641 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6642 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6643 | ret = -EINVAL; |
6644 | goto out; | |
b481de9c ZY |
6645 | } |
6646 | ||
c8b0e6e1 | 6647 | #ifdef CONFIG_IWL4965_HT |
78330fdd | 6648 | /* if we are switching from ht to 2.4 clear flags |
b481de9c ZY |
6649 | * from any ht related info since 2.4 does not |
6650 | * support ht */ | |
78330fdd | 6651 | if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel->hw_value) |
b481de9c ZY |
6652 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH |
6653 | && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) | |
6654 | #endif | |
6655 | ) | |
6656 | priv->staging_rxon.flags = 0; | |
c8b0e6e1 | 6657 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 6658 | |
bf85ea4f | 6659 | iwlcore_set_rxon_channel(priv, conf->channel->band, |
8318d78a | 6660 | ieee80211_frequency_to_channel(conf->channel->center_freq)); |
b481de9c | 6661 | |
8318d78a | 6662 | iwl4965_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6663 | |
6664 | /* The list of supported rates and rate mask can be different | |
8318d78a | 6665 | * for each band; since the band may have changed, reset |
b481de9c | 6666 | * the rate mask to what mac80211 lists */ |
bb8c093b | 6667 | iwl4965_set_rate(priv); |
b481de9c ZY |
6668 | |
6669 | spin_unlock_irqrestore(&priv->lock, flags); | |
6670 | ||
6671 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6672 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6673 | iwl4965_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6674 | goto out; |
b481de9c ZY |
6675 | } |
6676 | #endif | |
6677 | ||
ad97edd2 MA |
6678 | if (priv->cfg->ops->lib->radio_kill_sw) |
6679 | priv->cfg->ops->lib->radio_kill_sw(priv, !conf->radio_enabled); | |
b481de9c ZY |
6680 | |
6681 | if (!conf->radio_enabled) { | |
6682 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6683 | goto out; |
b481de9c ZY |
6684 | } |
6685 | ||
fee1247a | 6686 | if (iwl_is_rfkill(priv)) { |
b481de9c | 6687 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6688 | ret = -EIO; |
6689 | goto out; | |
b481de9c ZY |
6690 | } |
6691 | ||
bb8c093b | 6692 | iwl4965_set_rate(priv); |
b481de9c ZY |
6693 | |
6694 | if (memcmp(&priv->active_rxon, | |
6695 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
bb8c093b | 6696 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6697 | else |
6698 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6699 | ||
6700 | IWL_DEBUG_MAC80211("leave\n"); | |
6701 | ||
a0646470 ZY |
6702 | out: |
6703 | clear_bit(STATUS_CONF_PENDING, &priv->status); | |
5a66926a | 6704 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6705 | return ret; |
b481de9c ZY |
6706 | } |
6707 | ||
c79dd5b5 | 6708 | static void iwl4965_config_ap(struct iwl_priv *priv) |
b481de9c | 6709 | { |
857485c0 | 6710 | int ret = 0; |
b481de9c | 6711 | |
d986bcd1 | 6712 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6713 | return; |
6714 | ||
6715 | /* The following should be done only at AP bring up */ | |
6716 | if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { | |
6717 | ||
6718 | /* RXON - unassoc (to set timing command) */ | |
6719 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6720 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6721 | |
6722 | /* RXON Timing */ | |
bb8c093b CH |
6723 | memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd)); |
6724 | iwl4965_setup_rxon_timing(priv); | |
857485c0 | 6725 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 6726 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 6727 | if (ret) |
b481de9c ZY |
6728 | IWL_WARNING("REPLY_RXON_TIMING failed - " |
6729 | "Attempting to continue.\n"); | |
6730 | ||
6731 | iwl4965_set_rxon_chain(priv); | |
6732 | ||
6733 | /* FIXME: what should be the assoc_id for AP? */ | |
6734 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6735 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6736 | priv->staging_rxon.flags |= | |
6737 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
6738 | else | |
6739 | priv->staging_rxon.flags &= | |
6740 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6741 | ||
6742 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6743 | if (priv->assoc_capability & | |
6744 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6745 | priv->staging_rxon.flags |= | |
6746 | RXON_FLG_SHORT_SLOT_MSK; | |
6747 | else | |
6748 | priv->staging_rxon.flags &= | |
6749 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6750 | ||
6751 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6752 | priv->staging_rxon.flags &= | |
6753 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6754 | } | |
6755 | /* restore RXON assoc */ | |
6756 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6757 | iwl4965_commit_rxon(priv); |
bb8c093b | 6758 | iwl4965_activate_qos(priv, 1); |
bb8c093b | 6759 | iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); |
e1493deb | 6760 | } |
bb8c093b | 6761 | iwl4965_send_beacon_cmd(priv); |
b481de9c ZY |
6762 | |
6763 | /* FIXME - we need to add code here to detect a totally new | |
6764 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6765 | * clear sta table, add BCAST sta... */ | |
6766 | } | |
6767 | ||
32bfd35d JB |
6768 | static int iwl4965_mac_config_interface(struct ieee80211_hw *hw, |
6769 | struct ieee80211_vif *vif, | |
b481de9c ZY |
6770 | struct ieee80211_if_conf *conf) |
6771 | { | |
c79dd5b5 | 6772 | struct iwl_priv *priv = hw->priv; |
0795af57 | 6773 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6774 | unsigned long flags; |
6775 | int rc; | |
6776 | ||
6777 | if (conf == NULL) | |
6778 | return -EIO; | |
6779 | ||
b716bb91 EG |
6780 | if (priv->vif != vif) { |
6781 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
6782 | mutex_unlock(&priv->mutex); | |
6783 | return 0; | |
6784 | } | |
6785 | ||
b481de9c ZY |
6786 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && |
6787 | (!conf->beacon || !conf->ssid_len)) { | |
6788 | IWL_DEBUG_MAC80211 | |
6789 | ("Leaving in AP mode because HostAPD is not ready.\n"); | |
6790 | return 0; | |
6791 | } | |
6792 | ||
fee1247a | 6793 | if (!iwl_is_alive(priv)) |
5a66926a ZY |
6794 | return -EAGAIN; |
6795 | ||
b481de9c ZY |
6796 | mutex_lock(&priv->mutex); |
6797 | ||
b481de9c | 6798 | if (conf->bssid) |
0795af57 JP |
6799 | IWL_DEBUG_MAC80211("bssid: %s\n", |
6800 | print_mac(mac, conf->bssid)); | |
b481de9c | 6801 | |
4150c572 JB |
6802 | /* |
6803 | * very dubious code was here; the probe filtering flag is never set: | |
6804 | * | |
b481de9c ZY |
6805 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6806 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6807 | */ |
b481de9c ZY |
6808 | |
6809 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6810 | if (!conf->bssid) { | |
6811 | conf->bssid = priv->mac_addr; | |
6812 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
0795af57 JP |
6813 | IWL_DEBUG_MAC80211("bssid was set to: %s\n", |
6814 | print_mac(mac, conf->bssid)); | |
b481de9c ZY |
6815 | } |
6816 | if (priv->ibss_beacon) | |
6817 | dev_kfree_skb(priv->ibss_beacon); | |
6818 | ||
6819 | priv->ibss_beacon = conf->beacon; | |
6820 | } | |
6821 | ||
fee1247a | 6822 | if (iwl_is_rfkill(priv)) |
fde3571f MA |
6823 | goto done; |
6824 | ||
b481de9c ZY |
6825 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6826 | !is_multicast_ether_addr(conf->bssid)) { | |
6827 | /* If there is currently a HW scan going on in the background | |
6828 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 6829 | if (iwl4965_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
6830 | IWL_WARNING("Aborted scan still in progress " |
6831 | "after 100ms\n"); | |
6832 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6833 | mutex_unlock(&priv->mutex); | |
6834 | return -EAGAIN; | |
6835 | } | |
6836 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
6837 | ||
6838 | /* TODO: Audit driver for usage of these members and see | |
6839 | * if mac80211 deprecates them (priv->bssid looks like it | |
6840 | * shouldn't be there, but I haven't scanned the IBSS code | |
6841 | * to verify) - jpk */ | |
6842 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6843 | ||
6844 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 6845 | iwl4965_config_ap(priv); |
b481de9c | 6846 | else { |
bb8c093b | 6847 | rc = iwl4965_commit_rxon(priv); |
b481de9c | 6848 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc) |
bb8c093b | 6849 | iwl4965_rxon_add_station( |
b481de9c ZY |
6850 | priv, priv->active_rxon.bssid_addr, 1); |
6851 | } | |
6852 | ||
6853 | } else { | |
bb8c093b | 6854 | iwl4965_scan_cancel_timeout(priv, 100); |
b481de9c | 6855 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6856 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6857 | } |
6858 | ||
fde3571f | 6859 | done: |
b481de9c ZY |
6860 | spin_lock_irqsave(&priv->lock, flags); |
6861 | if (!conf->ssid_len) | |
6862 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6863 | else | |
6864 | memcpy(priv->essid, conf->ssid, conf->ssid_len); | |
6865 | ||
6866 | priv->essid_len = conf->ssid_len; | |
6867 | spin_unlock_irqrestore(&priv->lock, flags); | |
6868 | ||
6869 | IWL_DEBUG_MAC80211("leave\n"); | |
6870 | mutex_unlock(&priv->mutex); | |
6871 | ||
6872 | return 0; | |
6873 | } | |
6874 | ||
bb8c093b | 6875 | static void iwl4965_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
6876 | unsigned int changed_flags, |
6877 | unsigned int *total_flags, | |
6878 | int mc_count, struct dev_addr_list *mc_list) | |
6879 | { | |
6880 | /* | |
6881 | * XXX: dummy | |
bb8c093b | 6882 | * see also iwl4965_connection_init_rx_config |
4150c572 JB |
6883 | */ |
6884 | *total_flags = 0; | |
6885 | } | |
6886 | ||
bb8c093b | 6887 | static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6888 | struct ieee80211_if_init_conf *conf) |
6889 | { | |
c79dd5b5 | 6890 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6891 | |
6892 | IWL_DEBUG_MAC80211("enter\n"); | |
6893 | ||
6894 | mutex_lock(&priv->mutex); | |
948c171c | 6895 | |
fee1247a | 6896 | if (iwl_is_ready_rf(priv)) { |
fde3571f MA |
6897 | iwl4965_scan_cancel_timeout(priv, 100); |
6898 | cancel_delayed_work(&priv->post_associate); | |
6899 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
6900 | iwl4965_commit_rxon(priv); | |
6901 | } | |
32bfd35d JB |
6902 | if (priv->vif == conf->vif) { |
6903 | priv->vif = NULL; | |
b481de9c ZY |
6904 | memset(priv->bssid, 0, ETH_ALEN); |
6905 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6906 | priv->essid_len = 0; | |
6907 | } | |
6908 | mutex_unlock(&priv->mutex); | |
6909 | ||
6910 | IWL_DEBUG_MAC80211("leave\n"); | |
6911 | ||
6912 | } | |
471b3efd | 6913 | |
98952d5d TW |
6914 | |
6915 | #ifdef CONFIG_IWL4965_HT | |
6916 | static void iwl4965_ht_conf(struct iwl_priv *priv, | |
6917 | struct ieee80211_bss_conf *bss_conf) | |
6918 | { | |
6919 | struct ieee80211_ht_info *ht_conf = bss_conf->ht_conf; | |
6920 | struct ieee80211_ht_bss_info *ht_bss_conf = bss_conf->ht_bss_conf; | |
6921 | struct iwl_ht_info *iwl_conf = &priv->current_ht_config; | |
6922 | ||
6923 | IWL_DEBUG_MAC80211("enter: \n"); | |
6924 | ||
6925 | iwl_conf->is_ht = bss_conf->assoc_ht; | |
6926 | ||
6927 | if (!iwl_conf->is_ht) | |
6928 | return; | |
6929 | ||
6930 | priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2); | |
6931 | ||
6932 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20) | |
6933 | iwl_conf->sgf |= 0x1; | |
6934 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40) | |
6935 | iwl_conf->sgf |= 0x2; | |
6936 | ||
6937 | iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD); | |
6938 | iwl_conf->max_amsdu_size = | |
6939 | !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU); | |
6940 | ||
6941 | iwl_conf->supported_chan_width = | |
6942 | !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH); | |
6943 | iwl_conf->extension_chan_offset = | |
6944 | ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET; | |
6945 | /* If no above or below channel supplied disable FAT channel */ | |
6946 | if (iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_ABOVE && | |
6947 | iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_BELOW) | |
6948 | iwl_conf->supported_chan_width = 0; | |
6949 | ||
6950 | iwl_conf->tx_mimo_ps_mode = | |
6951 | (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2); | |
6952 | memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16); | |
6953 | ||
6954 | iwl_conf->control_channel = ht_bss_conf->primary_channel; | |
6955 | iwl_conf->tx_chan_width = | |
6956 | !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH); | |
6957 | iwl_conf->ht_protection = | |
6958 | ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION; | |
6959 | iwl_conf->non_GF_STA_present = | |
6960 | !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT); | |
6961 | ||
6962 | IWL_DEBUG_MAC80211("control channel %d\n", iwl_conf->control_channel); | |
6963 | IWL_DEBUG_MAC80211("leave\n"); | |
6964 | } | |
6965 | #else | |
6966 | static inline void iwl4965_ht_conf(struct iwl_priv *priv, | |
6967 | struct ieee80211_bss_conf *bss_conf) | |
6968 | { | |
6969 | } | |
6970 | #endif | |
6971 | ||
3109ece1 | 6972 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
471b3efd JB |
6973 | static void iwl4965_bss_info_changed(struct ieee80211_hw *hw, |
6974 | struct ieee80211_vif *vif, | |
6975 | struct ieee80211_bss_conf *bss_conf, | |
6976 | u32 changes) | |
220173b0 | 6977 | { |
c79dd5b5 | 6978 | struct iwl_priv *priv = hw->priv; |
220173b0 | 6979 | |
3109ece1 TW |
6980 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); |
6981 | ||
471b3efd | 6982 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
3109ece1 TW |
6983 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", |
6984 | bss_conf->use_short_preamble); | |
471b3efd | 6985 | if (bss_conf->use_short_preamble) |
220173b0 TW |
6986 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
6987 | else | |
6988 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6989 | } | |
6990 | ||
471b3efd | 6991 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { |
3109ece1 | 6992 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); |
8318d78a | 6993 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) |
220173b0 TW |
6994 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
6995 | else | |
6996 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
6997 | } | |
6998 | ||
98952d5d | 6999 | if (changes & BSS_CHANGED_HT) { |
3109ece1 | 7000 | IWL_DEBUG_MAC80211("HT %d\n", bss_conf->assoc_ht); |
98952d5d TW |
7001 | iwl4965_ht_conf(priv, bss_conf); |
7002 | iwl4965_set_rxon_chain(priv); | |
7003 | } | |
7004 | ||
471b3efd | 7005 | if (changes & BSS_CHANGED_ASSOC) { |
3109ece1 TW |
7006 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); |
7007 | if (bss_conf->assoc) { | |
7008 | priv->assoc_id = bss_conf->aid; | |
7009 | priv->beacon_int = bss_conf->beacon_int; | |
7010 | priv->timestamp = bss_conf->timestamp; | |
7011 | priv->assoc_capability = bss_conf->assoc_capability; | |
7012 | priv->next_scan_jiffies = jiffies + | |
7013 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
7014 | queue_work(priv->workqueue, &priv->post_associate.work); | |
7015 | } else { | |
7016 | priv->assoc_id = 0; | |
7017 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
7018 | } | |
7019 | } else if (changes && iwl_is_associated(priv) && priv->assoc_id) { | |
7020 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
7021 | iwl4965_send_rxon_assoc(priv); | |
471b3efd JB |
7022 | } |
7023 | ||
220173b0 | 7024 | } |
b481de9c | 7025 | |
bb8c093b | 7026 | static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
7027 | { |
7028 | int rc = 0; | |
7029 | unsigned long flags; | |
c79dd5b5 | 7030 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7031 | |
7032 | IWL_DEBUG_MAC80211("enter\n"); | |
7033 | ||
052c4b9f | 7034 | mutex_lock(&priv->mutex); |
b481de9c ZY |
7035 | spin_lock_irqsave(&priv->lock, flags); |
7036 | ||
fee1247a | 7037 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7038 | rc = -EIO; |
7039 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
7040 | goto out_unlock; | |
7041 | } | |
7042 | ||
7043 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */ | |
7044 | rc = -EIO; | |
7045 | IWL_ERROR("ERROR: APs don't scan\n"); | |
7046 | goto out_unlock; | |
7047 | } | |
7048 | ||
7878a5a4 MA |
7049 | /* we don't schedule scan within next_scan_jiffies period */ |
7050 | if (priv->next_scan_jiffies && | |
7051 | time_after(priv->next_scan_jiffies, jiffies)) { | |
7052 | rc = -EAGAIN; | |
7053 | goto out_unlock; | |
7054 | } | |
b481de9c | 7055 | /* if we just finished scan ask for delay */ |
7878a5a4 MA |
7056 | if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies + |
7057 | IWL_DELAY_NEXT_SCAN, jiffies)) { | |
b481de9c ZY |
7058 | rc = -EAGAIN; |
7059 | goto out_unlock; | |
7060 | } | |
7061 | if (len) { | |
7878a5a4 | 7062 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
bb8c093b | 7063 | iwl4965_escape_essid(ssid, len), (int)len); |
b481de9c ZY |
7064 | |
7065 | priv->one_direct_scan = 1; | |
7066 | priv->direct_ssid_len = (u8) | |
7067 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
7068 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
948c171c MA |
7069 | } else |
7070 | priv->one_direct_scan = 0; | |
b481de9c | 7071 | |
bb8c093b | 7072 | rc = iwl4965_scan_initiate(priv); |
b481de9c ZY |
7073 | |
7074 | IWL_DEBUG_MAC80211("leave\n"); | |
7075 | ||
7076 | out_unlock: | |
7077 | spin_unlock_irqrestore(&priv->lock, flags); | |
052c4b9f | 7078 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
7079 | |
7080 | return rc; | |
7081 | } | |
7082 | ||
ab885f8c EG |
7083 | static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw, |
7084 | struct ieee80211_key_conf *keyconf, const u8 *addr, | |
7085 | u32 iv32, u16 *phase1key) | |
7086 | { | |
7087 | struct iwl_priv *priv = hw->priv; | |
7088 | u8 sta_id = IWL_INVALID_STATION; | |
7089 | unsigned long flags; | |
7090 | __le16 key_flags = 0; | |
7091 | int i; | |
7092 | DECLARE_MAC_BUF(mac); | |
7093 | ||
7094 | IWL_DEBUG_MAC80211("enter\n"); | |
7095 | ||
7096 | sta_id = iwl4965_hw_find_station(priv, addr); | |
7097 | if (sta_id == IWL_INVALID_STATION) { | |
7098 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
7099 | print_mac(mac, addr)); | |
7100 | return; | |
7101 | } | |
7102 | ||
7103 | iwl4965_scan_cancel_timeout(priv, 100); | |
7104 | ||
7105 | key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); | |
7106 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
7107 | key_flags &= ~STA_KEY_FLG_INVALID; | |
7108 | ||
7109 | if (sta_id == priv->hw_setting.bcast_sta_id) | |
7110 | key_flags |= STA_KEY_MULTICAST_MSK; | |
7111 | ||
7112 | spin_lock_irqsave(&priv->sta_lock, flags); | |
7113 | ||
7114 | priv->stations[sta_id].sta.key.key_offset = | |
7115 | (sta_id % STA_KEY_MAX_NUM);/* FIXME */ | |
7116 | priv->stations[sta_id].sta.key.key_flags = key_flags; | |
7117 | priv->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; | |
7118 | ||
7119 | for (i = 0; i < 5; i++) | |
7120 | priv->stations[sta_id].sta.key.tkip_rx_ttak[i] = | |
7121 | cpu_to_le16(phase1key[i]); | |
7122 | ||
7123 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
7124 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
7125 | ||
7126 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); | |
7127 | ||
7128 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
7129 | ||
7130 | IWL_DEBUG_MAC80211("leave\n"); | |
7131 | } | |
7132 | ||
bb8c093b | 7133 | static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
7134 | const u8 *local_addr, const u8 *addr, |
7135 | struct ieee80211_key_conf *key) | |
7136 | { | |
c79dd5b5 | 7137 | struct iwl_priv *priv = hw->priv; |
0795af57 | 7138 | DECLARE_MAC_BUF(mac); |
deb09c43 EG |
7139 | int ret = 0; |
7140 | u8 sta_id = IWL_INVALID_STATION; | |
7141 | u8 static_key; | |
b481de9c ZY |
7142 | |
7143 | IWL_DEBUG_MAC80211("enter\n"); | |
7144 | ||
1ea87396 | 7145 | if (!priv->cfg->mod_params->hw_crypto) { |
b481de9c ZY |
7146 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
7147 | return -EOPNOTSUPP; | |
7148 | } | |
7149 | ||
7150 | if (is_zero_ether_addr(addr)) | |
7151 | /* only support pairwise keys */ | |
7152 | return -EOPNOTSUPP; | |
7153 | ||
deb09c43 EG |
7154 | /* FIXME: need to differenciate between static and dynamic key |
7155 | * in the level of mac80211 */ | |
3109ece1 | 7156 | static_key = !iwl_is_associated(priv); |
b481de9c | 7157 | |
deb09c43 EG |
7158 | if (!static_key) { |
7159 | sta_id = iwl4965_hw_find_station(priv, addr); | |
7160 | if (sta_id == IWL_INVALID_STATION) { | |
7161 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
7162 | print_mac(mac, addr)); | |
7163 | return -EINVAL; | |
7164 | } | |
7165 | } | |
b481de9c | 7166 | |
bb8c093b | 7167 | iwl4965_scan_cancel_timeout(priv, 100); |
052c4b9f | 7168 | |
b481de9c | 7169 | switch (cmd) { |
deb09c43 EG |
7170 | case SET_KEY: |
7171 | if (static_key) | |
7172 | ret = iwl4965_set_static_key(priv, key); | |
7173 | else | |
7174 | ret = iwl4965_set_dynamic_key(priv, key, sta_id); | |
7175 | ||
7176 | IWL_DEBUG_MAC80211("enable hwcrypto key\n"); | |
b481de9c ZY |
7177 | break; |
7178 | case DISABLE_KEY: | |
deb09c43 EG |
7179 | if (static_key) |
7180 | ret = iwl4965_remove_static_key(priv); | |
7181 | else | |
7182 | ret = iwl4965_clear_sta_key_info(priv, sta_id); | |
7183 | ||
7184 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); | |
b481de9c ZY |
7185 | break; |
7186 | default: | |
deb09c43 | 7187 | ret = -EINVAL; |
b481de9c ZY |
7188 | } |
7189 | ||
7190 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c | 7191 | |
deb09c43 | 7192 | return ret; |
b481de9c ZY |
7193 | } |
7194 | ||
bb8c093b | 7195 | static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue, |
b481de9c ZY |
7196 | const struct ieee80211_tx_queue_params *params) |
7197 | { | |
c79dd5b5 | 7198 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7199 | unsigned long flags; |
7200 | int q; | |
b481de9c ZY |
7201 | |
7202 | IWL_DEBUG_MAC80211("enter\n"); | |
7203 | ||
fee1247a | 7204 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7205 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7206 | return -EIO; | |
7207 | } | |
7208 | ||
7209 | if (queue >= AC_NUM) { | |
7210 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
7211 | return 0; | |
7212 | } | |
7213 | ||
b481de9c ZY |
7214 | if (!priv->qos_data.qos_enable) { |
7215 | priv->qos_data.qos_active = 0; | |
7216 | IWL_DEBUG_MAC80211("leave - qos not enabled\n"); | |
7217 | return 0; | |
7218 | } | |
7219 | q = AC_NUM - 1 - queue; | |
7220 | ||
7221 | spin_lock_irqsave(&priv->lock, flags); | |
7222 | ||
7223 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
7224 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
7225 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
7226 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 7227 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
7228 | |
7229 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
7230 | priv->qos_data.qos_active = 1; | |
7231 | ||
7232 | spin_unlock_irqrestore(&priv->lock, flags); | |
7233 | ||
7234 | mutex_lock(&priv->mutex); | |
7235 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 7236 | iwl4965_activate_qos(priv, 1); |
3109ece1 | 7237 | else if (priv->assoc_id && iwl_is_associated(priv)) |
bb8c093b | 7238 | iwl4965_activate_qos(priv, 0); |
b481de9c ZY |
7239 | |
7240 | mutex_unlock(&priv->mutex); | |
7241 | ||
b481de9c ZY |
7242 | IWL_DEBUG_MAC80211("leave\n"); |
7243 | return 0; | |
7244 | } | |
7245 | ||
bb8c093b | 7246 | static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7247 | struct ieee80211_tx_queue_stats *stats) |
7248 | { | |
c79dd5b5 | 7249 | struct iwl_priv *priv = hw->priv; |
b481de9c | 7250 | int i, avail; |
bb8c093b CH |
7251 | struct iwl4965_tx_queue *txq; |
7252 | struct iwl4965_queue *q; | |
b481de9c ZY |
7253 | unsigned long flags; |
7254 | ||
7255 | IWL_DEBUG_MAC80211("enter\n"); | |
7256 | ||
fee1247a | 7257 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7258 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7259 | return -EIO; | |
7260 | } | |
7261 | ||
7262 | spin_lock_irqsave(&priv->lock, flags); | |
7263 | ||
7264 | for (i = 0; i < AC_NUM; i++) { | |
7265 | txq = &priv->txq[i]; | |
7266 | q = &txq->q; | |
bb8c093b | 7267 | avail = iwl4965_queue_space(q); |
b481de9c ZY |
7268 | |
7269 | stats->data[i].len = q->n_window - avail; | |
7270 | stats->data[i].limit = q->n_window - q->high_mark; | |
7271 | stats->data[i].count = q->n_window; | |
7272 | ||
7273 | } | |
7274 | spin_unlock_irqrestore(&priv->lock, flags); | |
7275 | ||
7276 | IWL_DEBUG_MAC80211("leave\n"); | |
7277 | ||
7278 | return 0; | |
7279 | } | |
7280 | ||
bb8c093b | 7281 | static int iwl4965_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7282 | struct ieee80211_low_level_stats *stats) |
7283 | { | |
7284 | IWL_DEBUG_MAC80211("enter\n"); | |
7285 | IWL_DEBUG_MAC80211("leave\n"); | |
7286 | ||
7287 | return 0; | |
7288 | } | |
7289 | ||
bb8c093b | 7290 | static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw) |
b481de9c ZY |
7291 | { |
7292 | IWL_DEBUG_MAC80211("enter\n"); | |
7293 | IWL_DEBUG_MAC80211("leave\n"); | |
7294 | ||
7295 | return 0; | |
7296 | } | |
7297 | ||
bb8c093b | 7298 | static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7299 | { |
c79dd5b5 | 7300 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7301 | unsigned long flags; |
7302 | ||
7303 | mutex_lock(&priv->mutex); | |
7304 | IWL_DEBUG_MAC80211("enter\n"); | |
7305 | ||
7306 | priv->lq_mngr.lq_ready = 0; | |
c8b0e6e1 | 7307 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 7308 | spin_lock_irqsave(&priv->lock, flags); |
fd105e79 | 7309 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); |
b481de9c | 7310 | spin_unlock_irqrestore(&priv->lock, flags); |
c8b0e6e1 | 7311 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 7312 | |
bf85ea4f | 7313 | iwlcore_reset_qos(priv); |
b481de9c ZY |
7314 | |
7315 | cancel_delayed_work(&priv->post_associate); | |
7316 | ||
7317 | spin_lock_irqsave(&priv->lock, flags); | |
7318 | priv->assoc_id = 0; | |
7319 | priv->assoc_capability = 0; | |
b481de9c ZY |
7320 | priv->assoc_station_added = 0; |
7321 | ||
7322 | /* new association get rid of ibss beacon skb */ | |
7323 | if (priv->ibss_beacon) | |
7324 | dev_kfree_skb(priv->ibss_beacon); | |
7325 | ||
7326 | priv->ibss_beacon = NULL; | |
7327 | ||
7328 | priv->beacon_int = priv->hw->conf.beacon_int; | |
3109ece1 | 7329 | priv->timestamp = 0; |
b481de9c ZY |
7330 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA)) |
7331 | priv->beacon_int = 0; | |
7332 | ||
7333 | spin_unlock_irqrestore(&priv->lock, flags); | |
7334 | ||
fee1247a | 7335 | if (!iwl_is_ready_rf(priv)) { |
fde3571f MA |
7336 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
7337 | mutex_unlock(&priv->mutex); | |
7338 | return; | |
7339 | } | |
7340 | ||
052c4b9f | 7341 | /* we are restarting association process |
7342 | * clear RXON_FILTER_ASSOC_MSK bit | |
7343 | */ | |
7344 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
bb8c093b | 7345 | iwl4965_scan_cancel_timeout(priv, 100); |
052c4b9f | 7346 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7347 | iwl4965_commit_rxon(priv); |
052c4b9f | 7348 | } |
7349 | ||
b481de9c ZY |
7350 | /* Per mac80211.h: This is only used in IBSS mode... */ |
7351 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
052c4b9f | 7352 | |
b481de9c ZY |
7353 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7354 | mutex_unlock(&priv->mutex); | |
7355 | return; | |
7356 | } | |
7357 | ||
b481de9c ZY |
7358 | priv->only_active_channel = 0; |
7359 | ||
bb8c093b | 7360 | iwl4965_set_rate(priv); |
b481de9c ZY |
7361 | |
7362 | mutex_unlock(&priv->mutex); | |
7363 | ||
7364 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
7365 | } |
7366 | ||
bb8c093b | 7367 | static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
7368 | struct ieee80211_tx_control *control) |
7369 | { | |
c79dd5b5 | 7370 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7371 | unsigned long flags; |
7372 | ||
7373 | mutex_lock(&priv->mutex); | |
7374 | IWL_DEBUG_MAC80211("enter\n"); | |
7375 | ||
fee1247a | 7376 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7377 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7378 | mutex_unlock(&priv->mutex); | |
7379 | return -EIO; | |
7380 | } | |
7381 | ||
7382 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
7383 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); | |
7384 | mutex_unlock(&priv->mutex); | |
7385 | return -EIO; | |
7386 | } | |
7387 | ||
7388 | spin_lock_irqsave(&priv->lock, flags); | |
7389 | ||
7390 | if (priv->ibss_beacon) | |
7391 | dev_kfree_skb(priv->ibss_beacon); | |
7392 | ||
7393 | priv->ibss_beacon = skb; | |
7394 | ||
7395 | priv->assoc_id = 0; | |
7396 | ||
7397 | IWL_DEBUG_MAC80211("leave\n"); | |
7398 | spin_unlock_irqrestore(&priv->lock, flags); | |
7399 | ||
bf85ea4f | 7400 | iwlcore_reset_qos(priv); |
b481de9c ZY |
7401 | |
7402 | queue_work(priv->workqueue, &priv->post_associate.work); | |
7403 | ||
7404 | mutex_unlock(&priv->mutex); | |
7405 | ||
7406 | return 0; | |
7407 | } | |
7408 | ||
b481de9c ZY |
7409 | /***************************************************************************** |
7410 | * | |
7411 | * sysfs attributes | |
7412 | * | |
7413 | *****************************************************************************/ | |
7414 | ||
0a6857e7 | 7415 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
7416 | |
7417 | /* | |
7418 | * The following adds a new attribute to the sysfs representation | |
7419 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7420 | * used for controlling the debug level. | |
7421 | * | |
7422 | * See the level definitions in iwl for details. | |
7423 | */ | |
7424 | ||
7425 | static ssize_t show_debug_level(struct device_driver *d, char *buf) | |
7426 | { | |
0a6857e7 | 7427 | return sprintf(buf, "0x%08X\n", iwl_debug_level); |
b481de9c ZY |
7428 | } |
7429 | static ssize_t store_debug_level(struct device_driver *d, | |
7430 | const char *buf, size_t count) | |
7431 | { | |
7432 | char *p = (char *)buf; | |
7433 | u32 val; | |
7434 | ||
7435 | val = simple_strtoul(p, &p, 0); | |
7436 | if (p == buf) | |
7437 | printk(KERN_INFO DRV_NAME | |
7438 | ": %s is not in hex or decimal form.\n", buf); | |
7439 | else | |
0a6857e7 | 7440 | iwl_debug_level = val; |
b481de9c ZY |
7441 | |
7442 | return strnlen(buf, count); | |
7443 | } | |
7444 | ||
7445 | static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
7446 | show_debug_level, store_debug_level); | |
7447 | ||
0a6857e7 | 7448 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 7449 | |
b481de9c ZY |
7450 | |
7451 | static ssize_t show_temperature(struct device *d, | |
7452 | struct device_attribute *attr, char *buf) | |
7453 | { | |
c79dd5b5 | 7454 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 7455 | |
fee1247a | 7456 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7457 | return -EAGAIN; |
7458 | ||
bb8c093b | 7459 | return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv)); |
b481de9c ZY |
7460 | } |
7461 | ||
7462 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7463 | ||
7464 | static ssize_t show_rs_window(struct device *d, | |
7465 | struct device_attribute *attr, | |
7466 | char *buf) | |
7467 | { | |
c79dd5b5 | 7468 | struct iwl_priv *priv = d->driver_data; |
bb8c093b | 7469 | return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID); |
b481de9c ZY |
7470 | } |
7471 | static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL); | |
7472 | ||
7473 | static ssize_t show_tx_power(struct device *d, | |
7474 | struct device_attribute *attr, char *buf) | |
7475 | { | |
c79dd5b5 | 7476 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7477 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7478 | } | |
7479 | ||
7480 | static ssize_t store_tx_power(struct device *d, | |
7481 | struct device_attribute *attr, | |
7482 | const char *buf, size_t count) | |
7483 | { | |
c79dd5b5 | 7484 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7485 | char *p = (char *)buf; |
7486 | u32 val; | |
7487 | ||
7488 | val = simple_strtoul(p, &p, 10); | |
7489 | if (p == buf) | |
7490 | printk(KERN_INFO DRV_NAME | |
7491 | ": %s is not in decimal form.\n", buf); | |
7492 | else | |
bb8c093b | 7493 | iwl4965_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7494 | |
7495 | return count; | |
7496 | } | |
7497 | ||
7498 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7499 | ||
7500 | static ssize_t show_flags(struct device *d, | |
7501 | struct device_attribute *attr, char *buf) | |
7502 | { | |
c79dd5b5 | 7503 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7504 | |
7505 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
7506 | } | |
7507 | ||
7508 | static ssize_t store_flags(struct device *d, | |
7509 | struct device_attribute *attr, | |
7510 | const char *buf, size_t count) | |
7511 | { | |
c79dd5b5 | 7512 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7513 | u32 flags = simple_strtoul(buf, NULL, 0); |
7514 | ||
7515 | mutex_lock(&priv->mutex); | |
7516 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
7517 | /* Cancel any currently running scans... */ | |
bb8c093b | 7518 | if (iwl4965_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7519 | IWL_WARNING("Could not cancel scan.\n"); |
7520 | else { | |
7521 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7522 | flags); | |
7523 | priv->staging_rxon.flags = cpu_to_le32(flags); | |
bb8c093b | 7524 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
7525 | } |
7526 | } | |
7527 | mutex_unlock(&priv->mutex); | |
7528 | ||
7529 | return count; | |
7530 | } | |
7531 | ||
7532 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7533 | ||
7534 | static ssize_t show_filter_flags(struct device *d, | |
7535 | struct device_attribute *attr, char *buf) | |
7536 | { | |
c79dd5b5 | 7537 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7538 | |
7539 | return sprintf(buf, "0x%04X\n", | |
7540 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
7541 | } | |
7542 | ||
7543 | static ssize_t store_filter_flags(struct device *d, | |
7544 | struct device_attribute *attr, | |
7545 | const char *buf, size_t count) | |
7546 | { | |
c79dd5b5 | 7547 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7548 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7549 | ||
7550 | mutex_lock(&priv->mutex); | |
7551 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
7552 | /* Cancel any currently running scans... */ | |
bb8c093b | 7553 | if (iwl4965_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7554 | IWL_WARNING("Could not cancel scan.\n"); |
7555 | else { | |
7556 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7557 | "0x%04X\n", filter_flags); | |
7558 | priv->staging_rxon.filter_flags = | |
7559 | cpu_to_le32(filter_flags); | |
bb8c093b | 7560 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
7561 | } |
7562 | } | |
7563 | mutex_unlock(&priv->mutex); | |
7564 | ||
7565 | return count; | |
7566 | } | |
7567 | ||
7568 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7569 | store_filter_flags); | |
7570 | ||
c8b0e6e1 | 7571 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7572 | |
7573 | static ssize_t show_measurement(struct device *d, | |
7574 | struct device_attribute *attr, char *buf) | |
7575 | { | |
c79dd5b5 | 7576 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7577 | struct iwl4965_spectrum_notification measure_report; |
b481de9c ZY |
7578 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
7579 | u8 *data = (u8 *) & measure_report; | |
7580 | unsigned long flags; | |
7581 | ||
7582 | spin_lock_irqsave(&priv->lock, flags); | |
7583 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7584 | spin_unlock_irqrestore(&priv->lock, flags); | |
7585 | return 0; | |
7586 | } | |
7587 | memcpy(&measure_report, &priv->measure_report, size); | |
7588 | priv->measurement_status = 0; | |
7589 | spin_unlock_irqrestore(&priv->lock, flags); | |
7590 | ||
7591 | while (size && (PAGE_SIZE - len)) { | |
7592 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7593 | PAGE_SIZE - len, 1); | |
7594 | len = strlen(buf); | |
7595 | if (PAGE_SIZE - len) | |
7596 | buf[len++] = '\n'; | |
7597 | ||
7598 | ofs += 16; | |
7599 | size -= min(size, 16U); | |
7600 | } | |
7601 | ||
7602 | return len; | |
7603 | } | |
7604 | ||
7605 | static ssize_t store_measurement(struct device *d, | |
7606 | struct device_attribute *attr, | |
7607 | const char *buf, size_t count) | |
7608 | { | |
c79dd5b5 | 7609 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7610 | struct ieee80211_measurement_params params = { |
7611 | .channel = le16_to_cpu(priv->active_rxon.channel), | |
7612 | .start_time = cpu_to_le64(priv->last_tsf), | |
7613 | .duration = cpu_to_le16(1), | |
7614 | }; | |
7615 | u8 type = IWL_MEASURE_BASIC; | |
7616 | u8 buffer[32]; | |
7617 | u8 channel; | |
7618 | ||
7619 | if (count) { | |
7620 | char *p = buffer; | |
7621 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7622 | channel = simple_strtoul(p, NULL, 0); | |
7623 | if (channel) | |
7624 | params.channel = channel; | |
7625 | ||
7626 | p = buffer; | |
7627 | while (*p && *p != ' ') | |
7628 | p++; | |
7629 | if (*p) | |
7630 | type = simple_strtoul(p + 1, NULL, 0); | |
7631 | } | |
7632 | ||
7633 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7634 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7635 | iwl4965_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7636 | |
7637 | return count; | |
7638 | } | |
7639 | ||
7640 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7641 | show_measurement, store_measurement); | |
c8b0e6e1 | 7642 | #endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */ |
b481de9c ZY |
7643 | |
7644 | static ssize_t store_retry_rate(struct device *d, | |
7645 | struct device_attribute *attr, | |
7646 | const char *buf, size_t count) | |
7647 | { | |
c79dd5b5 | 7648 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7649 | |
7650 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7651 | if (priv->retry_rate <= 0) | |
7652 | priv->retry_rate = 1; | |
7653 | ||
7654 | return count; | |
7655 | } | |
7656 | ||
7657 | static ssize_t show_retry_rate(struct device *d, | |
7658 | struct device_attribute *attr, char *buf) | |
7659 | { | |
c79dd5b5 | 7660 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7661 | return sprintf(buf, "%d", priv->retry_rate); |
7662 | } | |
7663 | ||
7664 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7665 | store_retry_rate); | |
7666 | ||
7667 | static ssize_t store_power_level(struct device *d, | |
7668 | struct device_attribute *attr, | |
7669 | const char *buf, size_t count) | |
7670 | { | |
c79dd5b5 | 7671 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7672 | int rc; |
7673 | int mode; | |
7674 | ||
7675 | mode = simple_strtoul(buf, NULL, 0); | |
7676 | mutex_lock(&priv->mutex); | |
7677 | ||
fee1247a | 7678 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
7679 | rc = -EAGAIN; |
7680 | goto out; | |
7681 | } | |
7682 | ||
7683 | if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) | |
7684 | mode = IWL_POWER_AC; | |
7685 | else | |
7686 | mode |= IWL_POWER_ENABLED; | |
7687 | ||
7688 | if (mode != priv->power_mode) { | |
bb8c093b | 7689 | rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7690 | if (rc) { |
7691 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7692 | goto out; | |
7693 | } | |
7694 | priv->power_mode = mode; | |
7695 | } | |
7696 | ||
7697 | rc = count; | |
7698 | ||
7699 | out: | |
7700 | mutex_unlock(&priv->mutex); | |
7701 | return rc; | |
7702 | } | |
7703 | ||
7704 | #define MAX_WX_STRING 80 | |
7705 | ||
7706 | /* Values are in microsecond */ | |
7707 | static const s32 timeout_duration[] = { | |
7708 | 350000, | |
7709 | 250000, | |
7710 | 75000, | |
7711 | 37000, | |
7712 | 25000, | |
7713 | }; | |
7714 | static const s32 period_duration[] = { | |
7715 | 400000, | |
7716 | 700000, | |
7717 | 1000000, | |
7718 | 1000000, | |
7719 | 1000000 | |
7720 | }; | |
7721 | ||
7722 | static ssize_t show_power_level(struct device *d, | |
7723 | struct device_attribute *attr, char *buf) | |
7724 | { | |
c79dd5b5 | 7725 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7726 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7727 | char *p = buf; | |
7728 | ||
7729 | p += sprintf(p, "%d ", level); | |
7730 | switch (level) { | |
7731 | case IWL_POWER_MODE_CAM: | |
7732 | case IWL_POWER_AC: | |
7733 | p += sprintf(p, "(AC)"); | |
7734 | break; | |
7735 | case IWL_POWER_BATTERY: | |
7736 | p += sprintf(p, "(BATTERY)"); | |
7737 | break; | |
7738 | default: | |
7739 | p += sprintf(p, | |
7740 | "(Timeout %dms, Period %dms)", | |
7741 | timeout_duration[level - 1] / 1000, | |
7742 | period_duration[level - 1] / 1000); | |
7743 | } | |
7744 | ||
7745 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7746 | p += sprintf(p, " OFF\n"); | |
7747 | else | |
7748 | p += sprintf(p, " \n"); | |
7749 | ||
7750 | return (p - buf + 1); | |
7751 | ||
7752 | } | |
7753 | ||
7754 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7755 | store_power_level); | |
7756 | ||
7757 | static ssize_t show_channels(struct device *d, | |
7758 | struct device_attribute *attr, char *buf) | |
7759 | { | |
8318d78a JB |
7760 | /* all this shit doesn't belong into sysfs anyway */ |
7761 | return 0; | |
b481de9c ZY |
7762 | } |
7763 | ||
7764 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7765 | ||
7766 | static ssize_t show_statistics(struct device *d, | |
7767 | struct device_attribute *attr, char *buf) | |
7768 | { | |
c79dd5b5 | 7769 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7770 | u32 size = sizeof(struct iwl4965_notif_statistics); |
b481de9c ZY |
7771 | u32 len = 0, ofs = 0; |
7772 | u8 *data = (u8 *) & priv->statistics; | |
7773 | int rc = 0; | |
7774 | ||
fee1247a | 7775 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7776 | return -EAGAIN; |
7777 | ||
7778 | mutex_lock(&priv->mutex); | |
bb8c093b | 7779 | rc = iwl4965_send_statistics_request(priv); |
b481de9c ZY |
7780 | mutex_unlock(&priv->mutex); |
7781 | ||
7782 | if (rc) { | |
7783 | len = sprintf(buf, | |
7784 | "Error sending statistics request: 0x%08X\n", rc); | |
7785 | return len; | |
7786 | } | |
7787 | ||
7788 | while (size && (PAGE_SIZE - len)) { | |
7789 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7790 | PAGE_SIZE - len, 1); | |
7791 | len = strlen(buf); | |
7792 | if (PAGE_SIZE - len) | |
7793 | buf[len++] = '\n'; | |
7794 | ||
7795 | ofs += 16; | |
7796 | size -= min(size, 16U); | |
7797 | } | |
7798 | ||
7799 | return len; | |
7800 | } | |
7801 | ||
7802 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7803 | ||
7804 | static ssize_t show_antenna(struct device *d, | |
7805 | struct device_attribute *attr, char *buf) | |
7806 | { | |
c79dd5b5 | 7807 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 7808 | |
fee1247a | 7809 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7810 | return -EAGAIN; |
7811 | ||
7812 | return sprintf(buf, "%d\n", priv->antenna); | |
7813 | } | |
7814 | ||
7815 | static ssize_t store_antenna(struct device *d, | |
7816 | struct device_attribute *attr, | |
7817 | const char *buf, size_t count) | |
7818 | { | |
7819 | int ant; | |
c79dd5b5 | 7820 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7821 | |
7822 | if (count == 0) | |
7823 | return 0; | |
7824 | ||
7825 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7826 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7827 | return count; | |
7828 | } | |
7829 | ||
7830 | if ((ant >= 0) && (ant <= 2)) { | |
7831 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7832 | priv->antenna = (enum iwl4965_antenna)ant; |
b481de9c ZY |
7833 | } else |
7834 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7835 | ||
7836 | ||
7837 | return count; | |
7838 | } | |
7839 | ||
7840 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7841 | ||
7842 | static ssize_t show_status(struct device *d, | |
7843 | struct device_attribute *attr, char *buf) | |
7844 | { | |
c79dd5b5 | 7845 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
fee1247a | 7846 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7847 | return -EAGAIN; |
7848 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7849 | } | |
7850 | ||
7851 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7852 | ||
7853 | static ssize_t dump_error_log(struct device *d, | |
7854 | struct device_attribute *attr, | |
7855 | const char *buf, size_t count) | |
7856 | { | |
7857 | char *p = (char *)buf; | |
7858 | ||
7859 | if (p[0] == '1') | |
c79dd5b5 | 7860 | iwl4965_dump_nic_error_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7861 | |
7862 | return strnlen(buf, count); | |
7863 | } | |
7864 | ||
7865 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7866 | ||
7867 | static ssize_t dump_event_log(struct device *d, | |
7868 | struct device_attribute *attr, | |
7869 | const char *buf, size_t count) | |
7870 | { | |
7871 | char *p = (char *)buf; | |
7872 | ||
7873 | if (p[0] == '1') | |
c79dd5b5 | 7874 | iwl4965_dump_nic_event_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7875 | |
7876 | return strnlen(buf, count); | |
7877 | } | |
7878 | ||
7879 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7880 | ||
7881 | /***************************************************************************** | |
7882 | * | |
7883 | * driver setup and teardown | |
7884 | * | |
7885 | *****************************************************************************/ | |
7886 | ||
c79dd5b5 | 7887 | static void iwl4965_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
7888 | { |
7889 | priv->workqueue = create_workqueue(DRV_NAME); | |
7890 | ||
7891 | init_waitqueue_head(&priv->wait_command_queue); | |
7892 | ||
bb8c093b CH |
7893 | INIT_WORK(&priv->up, iwl4965_bg_up); |
7894 | INIT_WORK(&priv->restart, iwl4965_bg_restart); | |
7895 | INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish); | |
7896 | INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed); | |
7897 | INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan); | |
7898 | INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan); | |
7899 | INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill); | |
7900 | INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update); | |
7901 | INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate); | |
7902 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start); | |
7903 | INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start); | |
7904 | INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check); | |
7905 | ||
7906 | iwl4965_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7907 | |
7908 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7909 | iwl4965_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7910 | } |
7911 | ||
c79dd5b5 | 7912 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 7913 | { |
bb8c093b | 7914 | iwl4965_hw_cancel_deferred_work(priv); |
b481de9c | 7915 | |
3ae6a054 | 7916 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7917 | cancel_delayed_work(&priv->scan_check); |
7918 | cancel_delayed_work(&priv->alive_start); | |
7919 | cancel_delayed_work(&priv->post_associate); | |
7920 | cancel_work_sync(&priv->beacon_update); | |
7921 | } | |
7922 | ||
bb8c093b | 7923 | static struct attribute *iwl4965_sysfs_entries[] = { |
b481de9c ZY |
7924 | &dev_attr_antenna.attr, |
7925 | &dev_attr_channels.attr, | |
7926 | &dev_attr_dump_errors.attr, | |
7927 | &dev_attr_dump_events.attr, | |
7928 | &dev_attr_flags.attr, | |
7929 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7930 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7931 | &dev_attr_measurement.attr, |
7932 | #endif | |
7933 | &dev_attr_power_level.attr, | |
7934 | &dev_attr_retry_rate.attr, | |
b481de9c ZY |
7935 | &dev_attr_rs_window.attr, |
7936 | &dev_attr_statistics.attr, | |
7937 | &dev_attr_status.attr, | |
7938 | &dev_attr_temperature.attr, | |
b481de9c ZY |
7939 | &dev_attr_tx_power.attr, |
7940 | ||
7941 | NULL | |
7942 | }; | |
7943 | ||
bb8c093b | 7944 | static struct attribute_group iwl4965_attribute_group = { |
b481de9c | 7945 | .name = NULL, /* put in device directory */ |
bb8c093b | 7946 | .attrs = iwl4965_sysfs_entries, |
b481de9c ZY |
7947 | }; |
7948 | ||
bb8c093b CH |
7949 | static struct ieee80211_ops iwl4965_hw_ops = { |
7950 | .tx = iwl4965_mac_tx, | |
7951 | .start = iwl4965_mac_start, | |
7952 | .stop = iwl4965_mac_stop, | |
7953 | .add_interface = iwl4965_mac_add_interface, | |
7954 | .remove_interface = iwl4965_mac_remove_interface, | |
7955 | .config = iwl4965_mac_config, | |
7956 | .config_interface = iwl4965_mac_config_interface, | |
7957 | .configure_filter = iwl4965_configure_filter, | |
7958 | .set_key = iwl4965_mac_set_key, | |
ab885f8c | 7959 | .update_tkip_key = iwl4965_mac_update_tkip_key, |
bb8c093b CH |
7960 | .get_stats = iwl4965_mac_get_stats, |
7961 | .get_tx_stats = iwl4965_mac_get_tx_stats, | |
7962 | .conf_tx = iwl4965_mac_conf_tx, | |
7963 | .get_tsf = iwl4965_mac_get_tsf, | |
7964 | .reset_tsf = iwl4965_mac_reset_tsf, | |
7965 | .beacon_update = iwl4965_mac_beacon_update, | |
471b3efd | 7966 | .bss_info_changed = iwl4965_bss_info_changed, |
c8b0e6e1 | 7967 | #ifdef CONFIG_IWL4965_HT |
9ab46173 | 7968 | .ampdu_action = iwl4965_mac_ampdu_action, |
c8b0e6e1 | 7969 | #endif /* CONFIG_IWL4965_HT */ |
bb8c093b | 7970 | .hw_scan = iwl4965_mac_hw_scan |
b481de9c ZY |
7971 | }; |
7972 | ||
bb8c093b | 7973 | static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7974 | { |
7975 | int err = 0; | |
c79dd5b5 | 7976 | struct iwl_priv *priv; |
b481de9c | 7977 | struct ieee80211_hw *hw; |
82b9a121 | 7978 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 7979 | unsigned long flags; |
5a66926a | 7980 | DECLARE_MAC_BUF(mac); |
b481de9c | 7981 | |
316c30d9 AK |
7982 | /************************ |
7983 | * 1. Allocating HW data | |
7984 | ************************/ | |
7985 | ||
6440adb5 BC |
7986 | /* Disabling hardware scan means that mac80211 will perform scans |
7987 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 7988 | if (cfg->mod_params->disable_hw_scan) { |
b481de9c | 7989 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
bb8c093b | 7990 | iwl4965_hw_ops.hw_scan = NULL; |
b481de9c ZY |
7991 | } |
7992 | ||
1d0a082d AK |
7993 | hw = iwl_alloc_all(cfg, &iwl4965_hw_ops); |
7994 | if (!hw) { | |
b481de9c ZY |
7995 | err = -ENOMEM; |
7996 | goto out; | |
7997 | } | |
1d0a082d AK |
7998 | priv = hw->priv; |
7999 | /* At this point both hw and priv are allocated. */ | |
8000 | ||
b481de9c ZY |
8001 | SET_IEEE80211_DEV(hw, &pdev->dev); |
8002 | ||
8003 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); | |
82b9a121 | 8004 | priv->cfg = cfg; |
b481de9c | 8005 | priv->pci_dev = pdev; |
316c30d9 | 8006 | |
0a6857e7 | 8007 | #ifdef CONFIG_IWLWIFI_DEBUG |
1ea87396 | 8008 | iwl_debug_level = priv->cfg->mod_params->debug; |
b481de9c ZY |
8009 | atomic_set(&priv->restrict_refcnt, 0); |
8010 | #endif | |
b481de9c | 8011 | |
316c30d9 AK |
8012 | /************************** |
8013 | * 2. Initializing PCI bus | |
8014 | **************************/ | |
8015 | if (pci_enable_device(pdev)) { | |
8016 | err = -ENODEV; | |
8017 | goto out_ieee80211_free_hw; | |
8018 | } | |
8019 | ||
8020 | pci_set_master(pdev); | |
8021 | ||
8022 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
8023 | if (!err) | |
8024 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
8025 | if (err) { | |
8026 | printk(KERN_WARNING DRV_NAME | |
8027 | ": No suitable DMA available.\n"); | |
8028 | goto out_pci_disable_device; | |
8029 | } | |
8030 | ||
8031 | err = pci_request_regions(pdev, DRV_NAME); | |
8032 | if (err) | |
8033 | goto out_pci_disable_device; | |
8034 | ||
8035 | pci_set_drvdata(pdev, priv); | |
8036 | ||
8037 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
8038 | * PCI Tx retries from interfering with C3 CPU state */ | |
8039 | pci_write_config_byte(pdev, 0x41, 0x00); | |
8040 | ||
8041 | /*********************** | |
8042 | * 3. Read REV register | |
8043 | ***********************/ | |
8044 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
8045 | if (!priv->hw_base) { | |
8046 | err = -ENODEV; | |
8047 | goto out_pci_release_regions; | |
8048 | } | |
8049 | ||
8050 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
8051 | (unsigned long long) pci_resource_len(pdev, 0)); | |
8052 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
8053 | ||
8054 | printk(KERN_INFO DRV_NAME | |
8055 | ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); | |
8056 | ||
8057 | /***************** | |
8058 | * 4. Read EEPROM | |
8059 | *****************/ | |
8060 | /* nic init */ | |
3395f6e9 | 8061 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
316c30d9 AK |
8062 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
8063 | ||
3395f6e9 TW |
8064 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
8065 | err = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
316c30d9 AK |
8066 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
8067 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
8068 | if (err < 0) { | |
8069 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
8070 | goto out_iounmap; | |
8071 | } | |
8072 | /* Read the EEPROM */ | |
8073 | err = iwl_eeprom_init(priv); | |
8074 | if (err) { | |
8075 | IWL_ERROR("Unable to init EEPROM\n"); | |
8076 | goto out_iounmap; | |
8077 | } | |
8078 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
8079 | iwl_eeprom_get_mac(priv, priv->mac_addr); | |
8080 | IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); | |
8081 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
8082 | ||
8083 | /************************ | |
8084 | * 5. Setup HW constants | |
8085 | ************************/ | |
8086 | /* Device-specific setup */ | |
8087 | if (iwl4965_hw_set_hw_setting(priv)) { | |
8088 | IWL_ERROR("failed to set hw settings\n"); | |
8089 | goto out_iounmap; | |
8090 | } | |
8091 | ||
8092 | /******************* | |
8093 | * 6. Setup hw/priv | |
8094 | *******************/ | |
b481de9c | 8095 | |
bf85ea4f AK |
8096 | err = iwl_setup(priv); |
8097 | if (err) | |
316c30d9 | 8098 | goto out_unset_hw_settings; |
bf85ea4f | 8099 | /* At this point both hw and priv are initialized. */ |
316c30d9 AK |
8100 | |
8101 | /********************************** | |
8102 | * 7. Initialize module parameters | |
8103 | **********************************/ | |
8104 | ||
8105 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
1ea87396 | 8106 | if (priv->cfg->mod_params->disable) { |
316c30d9 AK |
8107 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
8108 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
8109 | } | |
8110 | ||
1ea87396 | 8111 | if (priv->cfg->mod_params->enable_qos) |
316c30d9 AK |
8112 | priv->qos_data.qos_enable = 1; |
8113 | ||
8114 | /******************** | |
8115 | * 8. Setup services | |
8116 | ********************/ | |
0359facc | 8117 | spin_lock_irqsave(&priv->lock, flags); |
316c30d9 | 8118 | iwl4965_disable_interrupts(priv); |
0359facc | 8119 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 AK |
8120 | |
8121 | err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group); | |
8122 | if (err) { | |
8123 | IWL_ERROR("failed to create sysfs device attributes\n"); | |
bf85ea4f | 8124 | goto out_unset_hw_settings; |
316c30d9 AK |
8125 | } |
8126 | ||
8127 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
8128 | if (err) { | |
8129 | IWL_ERROR("failed to create debugfs files\n"); | |
8130 | goto out_remove_sysfs; | |
8131 | } | |
8132 | ||
8133 | iwl4965_setup_deferred_work(priv); | |
8134 | iwl4965_setup_rx_handlers(priv); | |
8135 | ||
8136 | /******************** | |
8137 | * 9. Conclude | |
8138 | ********************/ | |
5a66926a ZY |
8139 | pci_save_state(pdev); |
8140 | pci_disable_device(pdev); | |
b481de9c | 8141 | |
c8381fdc MA |
8142 | /* notify iwlcore to init */ |
8143 | iwlcore_low_level_notify(priv, IWLCORE_INIT_EVT); | |
b481de9c ZY |
8144 | return 0; |
8145 | ||
316c30d9 AK |
8146 | out_remove_sysfs: |
8147 | sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); | |
316c30d9 | 8148 | out_unset_hw_settings: |
bb8c093b | 8149 | iwl4965_unset_hw_setting(priv); |
b481de9c ZY |
8150 | out_iounmap: |
8151 | pci_iounmap(pdev, priv->hw_base); | |
8152 | out_pci_release_regions: | |
8153 | pci_release_regions(pdev); | |
316c30d9 | 8154 | pci_set_drvdata(pdev, NULL); |
b481de9c ZY |
8155 | out_pci_disable_device: |
8156 | pci_disable_device(pdev); | |
b481de9c ZY |
8157 | out_ieee80211_free_hw: |
8158 | ieee80211_free_hw(priv->hw); | |
8159 | out: | |
8160 | return err; | |
8161 | } | |
8162 | ||
c83dbf68 | 8163 | static void __devexit iwl4965_pci_remove(struct pci_dev *pdev) |
b481de9c | 8164 | { |
c79dd5b5 | 8165 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c ZY |
8166 | struct list_head *p, *q; |
8167 | int i; | |
0359facc | 8168 | unsigned long flags; |
b481de9c ZY |
8169 | |
8170 | if (!priv) | |
8171 | return; | |
8172 | ||
8173 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
8174 | ||
c4f55232 RR |
8175 | if (priv->mac80211_registered) { |
8176 | ieee80211_unregister_hw(priv->hw); | |
8177 | priv->mac80211_registered = 0; | |
8178 | } | |
8179 | ||
b481de9c | 8180 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 8181 | |
bb8c093b | 8182 | iwl4965_down(priv); |
b481de9c | 8183 | |
0359facc MA |
8184 | /* make sure we flush any pending irq or |
8185 | * tasklet for the driver | |
8186 | */ | |
8187 | spin_lock_irqsave(&priv->lock, flags); | |
8188 | iwl4965_disable_interrupts(priv); | |
8189 | spin_unlock_irqrestore(&priv->lock, flags); | |
8190 | ||
8191 | iwl_synchronize_irq(priv); | |
8192 | ||
b481de9c ZY |
8193 | /* Free MAC hash list for ADHOC */ |
8194 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) { | |
8195 | list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) { | |
8196 | list_del(p); | |
bb8c093b | 8197 | kfree(list_entry(p, struct iwl4965_ibss_seq, list)); |
b481de9c ZY |
8198 | } |
8199 | } | |
8200 | ||
c8381fdc | 8201 | iwlcore_low_level_notify(priv, IWLCORE_REMOVE_EVT); |
712b6cf5 | 8202 | iwl_dbgfs_unregister(priv); |
bb8c093b | 8203 | sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); |
b481de9c | 8204 | |
bb8c093b | 8205 | iwl4965_dealloc_ucode_pci(priv); |
b481de9c ZY |
8206 | |
8207 | if (priv->rxq.bd) | |
bb8c093b CH |
8208 | iwl4965_rx_queue_free(priv, &priv->rxq); |
8209 | iwl4965_hw_txq_ctx_free(priv); | |
b481de9c | 8210 | |
bb8c093b | 8211 | iwl4965_unset_hw_setting(priv); |
bf85ea4f | 8212 | iwlcore_clear_stations_table(priv); |
b481de9c | 8213 | |
b481de9c | 8214 | |
948c171c MA |
8215 | /*netif_stop_queue(dev); */ |
8216 | flush_workqueue(priv->workqueue); | |
8217 | ||
bb8c093b | 8218 | /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes |
b481de9c ZY |
8219 | * priv->workqueue... so we can't take down the workqueue |
8220 | * until now... */ | |
8221 | destroy_workqueue(priv->workqueue); | |
8222 | priv->workqueue = NULL; | |
8223 | ||
b481de9c ZY |
8224 | pci_iounmap(pdev, priv->hw_base); |
8225 | pci_release_regions(pdev); | |
8226 | pci_disable_device(pdev); | |
8227 | pci_set_drvdata(pdev, NULL); | |
8228 | ||
bf85ea4f | 8229 | iwl_free_channel_map(priv); |
849e0dce | 8230 | iwl4965_free_geos(priv); |
b481de9c ZY |
8231 | |
8232 | if (priv->ibss_beacon) | |
8233 | dev_kfree_skb(priv->ibss_beacon); | |
8234 | ||
8235 | ieee80211_free_hw(priv->hw); | |
8236 | } | |
8237 | ||
8238 | #ifdef CONFIG_PM | |
8239 | ||
bb8c093b | 8240 | static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 8241 | { |
c79dd5b5 | 8242 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8243 | |
e655b9f0 ZY |
8244 | if (priv->is_open) { |
8245 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
8246 | iwl4965_mac_stop(priv->hw); | |
8247 | priv->is_open = 1; | |
8248 | } | |
b481de9c | 8249 | |
b481de9c ZY |
8250 | pci_set_power_state(pdev, PCI_D3hot); |
8251 | ||
b481de9c ZY |
8252 | return 0; |
8253 | } | |
8254 | ||
bb8c093b | 8255 | static int iwl4965_pci_resume(struct pci_dev *pdev) |
b481de9c | 8256 | { |
c79dd5b5 | 8257 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8258 | |
b481de9c | 8259 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8260 | |
e655b9f0 ZY |
8261 | if (priv->is_open) |
8262 | iwl4965_mac_start(priv->hw); | |
b481de9c | 8263 | |
e655b9f0 | 8264 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8265 | return 0; |
8266 | } | |
8267 | ||
8268 | #endif /* CONFIG_PM */ | |
8269 | ||
8270 | /***************************************************************************** | |
8271 | * | |
8272 | * driver and module entry point | |
8273 | * | |
8274 | *****************************************************************************/ | |
8275 | ||
bb8c093b | 8276 | static struct pci_driver iwl4965_driver = { |
b481de9c | 8277 | .name = DRV_NAME, |
bb8c093b CH |
8278 | .id_table = iwl4965_hw_card_ids, |
8279 | .probe = iwl4965_pci_probe, | |
8280 | .remove = __devexit_p(iwl4965_pci_remove), | |
b481de9c | 8281 | #ifdef CONFIG_PM |
bb8c093b CH |
8282 | .suspend = iwl4965_pci_suspend, |
8283 | .resume = iwl4965_pci_resume, | |
b481de9c ZY |
8284 | #endif |
8285 | }; | |
8286 | ||
bb8c093b | 8287 | static int __init iwl4965_init(void) |
b481de9c ZY |
8288 | { |
8289 | ||
8290 | int ret; | |
8291 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8292 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
8293 | |
8294 | ret = iwl4965_rate_control_register(); | |
8295 | if (ret) { | |
8296 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); | |
8297 | return ret; | |
8298 | } | |
8299 | ||
bb8c093b | 8300 | ret = pci_register_driver(&iwl4965_driver); |
b481de9c ZY |
8301 | if (ret) { |
8302 | IWL_ERROR("Unable to initialize PCI module\n"); | |
897e1cf2 | 8303 | goto error_register; |
b481de9c | 8304 | } |
0a6857e7 | 8305 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 8306 | ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level); |
b481de9c ZY |
8307 | if (ret) { |
8308 | IWL_ERROR("Unable to create driver sysfs file\n"); | |
897e1cf2 | 8309 | goto error_debug; |
b481de9c ZY |
8310 | } |
8311 | #endif | |
8312 | ||
8313 | return ret; | |
897e1cf2 RC |
8314 | |
8315 | #ifdef CONFIG_IWLWIFI_DEBUG | |
8316 | error_debug: | |
8317 | pci_unregister_driver(&iwl4965_driver); | |
8318 | #endif | |
8319 | error_register: | |
8320 | iwl4965_rate_control_unregister(); | |
8321 | return ret; | |
b481de9c ZY |
8322 | } |
8323 | ||
bb8c093b | 8324 | static void __exit iwl4965_exit(void) |
b481de9c | 8325 | { |
0a6857e7 | 8326 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 8327 | driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level); |
b481de9c | 8328 | #endif |
bb8c093b | 8329 | pci_unregister_driver(&iwl4965_driver); |
897e1cf2 | 8330 | iwl4965_rate_control_unregister(); |
b481de9c ZY |
8331 | } |
8332 | ||
bb8c093b CH |
8333 | module_exit(iwl4965_exit); |
8334 | module_init(iwl4965_init); |