]>
Commit | Line | Data |
---|---|---|
b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/version.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
b481de9c ZY |
44 | #include <net/mac80211.h> |
45 | ||
46 | #include <asm/div64.h> | |
47 | ||
6bc913bd | 48 | #include "iwl-eeprom.h" |
b481de9c | 49 | #include "iwl-4965.h" |
fee1247a | 50 | #include "iwl-core.h" |
3395f6e9 | 51 | #include "iwl-io.h" |
b481de9c | 52 | #include "iwl-helpers.h" |
6974e363 | 53 | #include "iwl-sta.h" |
b481de9c | 54 | |
c79dd5b5 | 55 | static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 56 | struct iwl4965_tx_queue *txq); |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
66 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | |
67 | */ | |
68 | ||
69 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux" | |
70 | ||
0a6857e7 | 71 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
72 | #define VD "d" |
73 | #else | |
74 | #define VD | |
75 | #endif | |
76 | ||
c8b0e6e1 | 77 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
78 | #define VS "s" |
79 | #else | |
80 | #define VS | |
81 | #endif | |
82 | ||
df48c323 | 83 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 84 | |
b481de9c ZY |
85 | |
86 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
87 | MODULE_VERSION(DRV_VERSION); | |
88 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
89 | MODULE_LICENSE("GPL"); | |
90 | ||
91 | __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr) | |
92 | { | |
93 | u16 fc = le16_to_cpu(hdr->frame_control); | |
94 | int hdr_len = ieee80211_get_hdrlen(fc); | |
95 | ||
96 | if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA)) | |
97 | return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN); | |
98 | return NULL; | |
99 | } | |
100 | ||
8318d78a | 101 | static const struct ieee80211_supported_band *iwl4965_get_hw_mode( |
c79dd5b5 | 102 | struct iwl_priv *priv, enum ieee80211_band band) |
b481de9c | 103 | { |
8318d78a | 104 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
105 | } |
106 | ||
bb8c093b | 107 | static int iwl4965_is_empty_essid(const char *essid, int essid_len) |
b481de9c ZY |
108 | { |
109 | /* Single white space is for Linksys APs */ | |
110 | if (essid_len == 1 && essid[0] == ' ') | |
111 | return 1; | |
112 | ||
113 | /* Otherwise, if the entire essid is 0, we assume it is hidden */ | |
114 | while (essid_len) { | |
115 | essid_len--; | |
116 | if (essid[essid_len] != '\0') | |
117 | return 0; | |
118 | } | |
119 | ||
120 | return 1; | |
121 | } | |
122 | ||
bb8c093b | 123 | static const char *iwl4965_escape_essid(const char *essid, u8 essid_len) |
b481de9c ZY |
124 | { |
125 | static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; | |
126 | const char *s = essid; | |
127 | char *d = escaped; | |
128 | ||
bb8c093b | 129 | if (iwl4965_is_empty_essid(essid, essid_len)) { |
b481de9c ZY |
130 | memcpy(escaped, "<hidden>", sizeof("<hidden>")); |
131 | return escaped; | |
132 | } | |
133 | ||
134 | essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE); | |
135 | while (essid_len--) { | |
136 | if (*s == '\0') { | |
137 | *d++ = '\\'; | |
138 | *d++ = '0'; | |
139 | s++; | |
140 | } else | |
141 | *d++ = *s++; | |
142 | } | |
143 | *d = '\0'; | |
144 | return escaped; | |
145 | } | |
146 | ||
b481de9c ZY |
147 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
148 | * DMA services | |
149 | * | |
150 | * Theory of operation | |
151 | * | |
6440adb5 BC |
152 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
153 | * of buffer descriptors, each of which points to one or more data buffers for | |
154 | * the device to read from or fill. Driver and device exchange status of each | |
155 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
156 | * entries in each circular buffer, to protect against confusing empty and full | |
157 | * queue states. | |
158 | * | |
159 | * The device reads or writes the data in the queues via the device's several | |
160 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
161 | * |
162 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
163 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
164 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
165 | * Tx queue resumed. | |
166 | * | |
6440adb5 BC |
167 | * The 4965 operates with up to 17 queues: One receive queue, one transmit |
168 | * queue (#4) for sending commands to the device firmware, and 15 other | |
169 | * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels. | |
e3851447 BC |
170 | * |
171 | * See more detailed info in iwl-4965-hw.h. | |
b481de9c ZY |
172 | ***************************************************/ |
173 | ||
fe01b477 | 174 | int iwl4965_queue_space(const struct iwl4965_queue *q) |
b481de9c | 175 | { |
fc4b6853 | 176 | int s = q->read_ptr - q->write_ptr; |
b481de9c | 177 | |
fc4b6853 | 178 | if (q->read_ptr > q->write_ptr) |
b481de9c ZY |
179 | s -= q->n_bd; |
180 | ||
181 | if (s <= 0) | |
182 | s += q->n_window; | |
183 | /* keep some reserve to not confuse empty and full situations */ | |
184 | s -= 2; | |
185 | if (s < 0) | |
186 | s = 0; | |
187 | return s; | |
188 | } | |
189 | ||
b481de9c | 190 | |
bb8c093b | 191 | static inline int x2_queue_used(const struct iwl4965_queue *q, int i) |
b481de9c | 192 | { |
fc4b6853 TW |
193 | return q->write_ptr > q->read_ptr ? |
194 | (i >= q->read_ptr && i < q->write_ptr) : | |
195 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
196 | } |
197 | ||
bb8c093b | 198 | static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge) |
b481de9c | 199 | { |
6440adb5 | 200 | /* This is for scan command, the big buffer at end of command array */ |
b481de9c | 201 | if (is_huge) |
6440adb5 | 202 | return q->n_window; /* must be power of 2 */ |
b481de9c | 203 | |
6440adb5 | 204 | /* Otherwise, use normal size buffers */ |
b481de9c ZY |
205 | return index & (q->n_window - 1); |
206 | } | |
207 | ||
6440adb5 BC |
208 | /** |
209 | * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes | |
210 | */ | |
c79dd5b5 | 211 | static int iwl4965_queue_init(struct iwl_priv *priv, struct iwl4965_queue *q, |
b481de9c ZY |
212 | int count, int slots_num, u32 id) |
213 | { | |
214 | q->n_bd = count; | |
215 | q->n_window = slots_num; | |
216 | q->id = id; | |
217 | ||
c54b679d TW |
218 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
219 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
220 | BUG_ON(!is_power_of_2(count)); |
221 | ||
222 | /* slots_num must be power-of-two size, otherwise | |
223 | * get_cmd_index is broken. */ | |
224 | BUG_ON(!is_power_of_2(slots_num)); | |
225 | ||
226 | q->low_mark = q->n_window / 4; | |
227 | if (q->low_mark < 4) | |
228 | q->low_mark = 4; | |
229 | ||
230 | q->high_mark = q->n_window / 8; | |
231 | if (q->high_mark < 2) | |
232 | q->high_mark = 2; | |
233 | ||
fc4b6853 | 234 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
235 | |
236 | return 0; | |
237 | } | |
238 | ||
6440adb5 BC |
239 | /** |
240 | * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
241 | */ | |
c79dd5b5 | 242 | static int iwl4965_tx_queue_alloc(struct iwl_priv *priv, |
bb8c093b | 243 | struct iwl4965_tx_queue *txq, u32 id) |
b481de9c ZY |
244 | { |
245 | struct pci_dev *dev = priv->pci_dev; | |
246 | ||
6440adb5 BC |
247 | /* Driver private data, only for Tx (not command) queues, |
248 | * not shared with device. */ | |
b481de9c ZY |
249 | if (id != IWL_CMD_QUEUE_NUM) { |
250 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
251 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
252 | if (!txq->txb) { | |
01ebd063 | 253 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
254 | "structures failed\n"); |
255 | goto error; | |
256 | } | |
257 | } else | |
258 | txq->txb = NULL; | |
259 | ||
6440adb5 BC |
260 | /* Circular buffer of transmit frame descriptors (TFDs), |
261 | * shared with device */ | |
b481de9c ZY |
262 | txq->bd = pci_alloc_consistent(dev, |
263 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
264 | &txq->q.dma_addr); | |
265 | ||
266 | if (!txq->bd) { | |
267 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
268 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
269 | goto error; | |
270 | } | |
271 | txq->q.id = id; | |
272 | ||
273 | return 0; | |
274 | ||
275 | error: | |
276 | if (txq->txb) { | |
277 | kfree(txq->txb); | |
278 | txq->txb = NULL; | |
279 | } | |
280 | ||
281 | return -ENOMEM; | |
282 | } | |
283 | ||
8b6eaea8 BC |
284 | /** |
285 | * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue | |
286 | */ | |
c79dd5b5 | 287 | int iwl4965_tx_queue_init(struct iwl_priv *priv, |
bb8c093b | 288 | struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id) |
b481de9c ZY |
289 | { |
290 | struct pci_dev *dev = priv->pci_dev; | |
291 | int len; | |
292 | int rc = 0; | |
293 | ||
8b6eaea8 BC |
294 | /* |
295 | * Alloc buffer array for commands (Tx or other types of commands). | |
296 | * For the command queue (#4), allocate command space + one big | |
297 | * command for scan, since scan command is very huge; the system will | |
298 | * not have two scans at the same time, so only one is needed. | |
bb54244b | 299 | * For normal Tx queues (all other queues), no super-size command |
8b6eaea8 BC |
300 | * space is needed. |
301 | */ | |
857485c0 | 302 | len = sizeof(struct iwl_cmd) * slots_num; |
b481de9c ZY |
303 | if (txq_id == IWL_CMD_QUEUE_NUM) |
304 | len += IWL_MAX_SCAN_SIZE; | |
305 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
306 | if (!txq->cmd) | |
307 | return -ENOMEM; | |
308 | ||
8b6eaea8 | 309 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 310 | rc = iwl4965_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
311 | if (rc) { |
312 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
313 | ||
314 | return -ENOMEM; | |
315 | } | |
316 | txq->need_update = 0; | |
317 | ||
318 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 319 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 320 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
8b6eaea8 BC |
321 | |
322 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
bb8c093b | 323 | iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 324 | |
8b6eaea8 | 325 | /* Tell device where to find queue */ |
bb8c093b | 326 | iwl4965_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | /** | |
bb8c093b | 332 | * iwl4965_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
333 | * @txq: Transmit queue to deallocate. |
334 | * | |
335 | * Empty queue by removing and destroying all BD's. | |
6440adb5 BC |
336 | * Free all buffers. |
337 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 338 | */ |
c79dd5b5 | 339 | void iwl4965_tx_queue_free(struct iwl_priv *priv, struct iwl4965_tx_queue *txq) |
b481de9c | 340 | { |
bb8c093b | 341 | struct iwl4965_queue *q = &txq->q; |
b481de9c ZY |
342 | struct pci_dev *dev = priv->pci_dev; |
343 | int len; | |
344 | ||
345 | if (q->n_bd == 0) | |
346 | return; | |
347 | ||
348 | /* first, empty all BD's */ | |
fc4b6853 | 349 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 350 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 351 | iwl4965_hw_txq_free_tfd(priv, txq); |
b481de9c | 352 | |
857485c0 | 353 | len = sizeof(struct iwl_cmd) * q->n_window; |
b481de9c ZY |
354 | if (q->id == IWL_CMD_QUEUE_NUM) |
355 | len += IWL_MAX_SCAN_SIZE; | |
356 | ||
6440adb5 | 357 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
358 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
359 | ||
6440adb5 | 360 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 361 | if (txq->q.n_bd) |
bb8c093b | 362 | pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) * |
b481de9c ZY |
363 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
364 | ||
6440adb5 | 365 | /* De-alloc array of per-TFD driver data */ |
b481de9c ZY |
366 | if (txq->txb) { |
367 | kfree(txq->txb); | |
368 | txq->txb = NULL; | |
369 | } | |
370 | ||
6440adb5 | 371 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
372 | memset(txq, 0, sizeof(*txq)); |
373 | } | |
374 | ||
bb8c093b | 375 | const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
b481de9c ZY |
376 | |
377 | /*************** STATION TABLE MANAGEMENT **** | |
9fbab516 | 378 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
379 | * the functionality provided here |
380 | */ | |
381 | ||
382 | /**************************************************************/ | |
383 | ||
01ebd063 | 384 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 BC |
385 | /** |
386 | * iwl4965_remove_station - Remove driver's knowledge of station. | |
387 | * | |
388 | * NOTE: This does not remove station from device's station table. | |
389 | */ | |
c79dd5b5 | 390 | static u8 iwl4965_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
391 | { |
392 | int index = IWL_INVALID_STATION; | |
393 | int i; | |
394 | unsigned long flags; | |
395 | ||
396 | spin_lock_irqsave(&priv->sta_lock, flags); | |
397 | ||
398 | if (is_ap) | |
399 | index = IWL_AP_ID; | |
400 | else if (is_broadcast_ether_addr(addr)) | |
401 | index = priv->hw_setting.bcast_sta_id; | |
402 | else | |
403 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) | |
404 | if (priv->stations[i].used && | |
405 | !compare_ether_addr(priv->stations[i].sta.sta.addr, | |
406 | addr)) { | |
407 | index = i; | |
408 | break; | |
409 | } | |
410 | ||
411 | if (unlikely(index == IWL_INVALID_STATION)) | |
412 | goto out; | |
413 | ||
414 | if (priv->stations[index].used) { | |
415 | priv->stations[index].used = 0; | |
416 | priv->num_stations--; | |
417 | } | |
418 | ||
419 | BUG_ON(priv->num_stations < 0); | |
420 | ||
421 | out: | |
422 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
423 | return 0; | |
424 | } | |
556f8db7 | 425 | #endif |
b481de9c | 426 | |
6440adb5 BC |
427 | /** |
428 | * iwl4965_add_station_flags - Add station to tables in driver and device | |
429 | */ | |
c79dd5b5 | 430 | u8 iwl4965_add_station_flags(struct iwl_priv *priv, const u8 *addr, |
67d62035 | 431 | int is_ap, u8 flags, void *ht_data) |
b481de9c ZY |
432 | { |
433 | int i; | |
434 | int index = IWL_INVALID_STATION; | |
bb8c093b | 435 | struct iwl4965_station_entry *station; |
b481de9c | 436 | unsigned long flags_spin; |
0795af57 | 437 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
438 | |
439 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
440 | if (is_ap) | |
441 | index = IWL_AP_ID; | |
442 | else if (is_broadcast_ether_addr(addr)) | |
443 | index = priv->hw_setting.bcast_sta_id; | |
444 | else | |
445 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) { | |
446 | if (!compare_ether_addr(priv->stations[i].sta.sta.addr, | |
447 | addr)) { | |
448 | index = i; | |
449 | break; | |
450 | } | |
451 | ||
452 | if (!priv->stations[i].used && | |
453 | index == IWL_INVALID_STATION) | |
454 | index = i; | |
455 | } | |
456 | ||
457 | ||
9fbab516 BC |
458 | /* These two conditions have the same outcome, but keep them separate |
459 | since they have different meanings */ | |
b481de9c ZY |
460 | if (unlikely(index == IWL_INVALID_STATION)) { |
461 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
462 | return index; | |
463 | } | |
464 | ||
465 | if (priv->stations[index].used && | |
466 | !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) { | |
467 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
468 | return index; | |
469 | } | |
470 | ||
471 | ||
0795af57 | 472 | IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr)); |
b481de9c ZY |
473 | station = &priv->stations[index]; |
474 | station->used = 1; | |
475 | priv->num_stations++; | |
476 | ||
6440adb5 | 477 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 478 | memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd)); |
b481de9c ZY |
479 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
480 | station->sta.mode = 0; | |
481 | station->sta.sta.sta_id = index; | |
482 | station->sta.station_flags = 0; | |
483 | ||
c8b0e6e1 | 484 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
485 | /* BCAST station and IBSS stations do not work in HT mode */ |
486 | if (index != priv->hw_setting.bcast_sta_id && | |
487 | priv->iw_mode != IEEE80211_IF_TYPE_IBSS) | |
67d62035 RR |
488 | iwl4965_set_ht_add_station(priv, index, |
489 | (struct ieee80211_ht_info *) ht_data); | |
c8b0e6e1 | 490 | #endif /*CONFIG_IWL4965_HT*/ |
b481de9c ZY |
491 | |
492 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
6440adb5 BC |
493 | |
494 | /* Add station to device's station table */ | |
bb8c093b | 495 | iwl4965_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
496 | return index; |
497 | ||
498 | } | |
499 | ||
b481de9c | 500 | |
b481de9c ZY |
501 | |
502 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
503 | ||
b481de9c | 504 | /** |
bb8c093b | 505 | * iwl4965_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
506 | * @priv: device private data point |
507 | * @cmd: a point to the ucode command structure | |
508 | * | |
509 | * The function returns < 0 values to indicate the operation is | |
510 | * failed. On success, it turns the index (> 0) of command in the | |
511 | * command queue. | |
512 | */ | |
857485c0 | 513 | int iwl4965_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
b481de9c | 514 | { |
bb8c093b CH |
515 | struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
516 | struct iwl4965_queue *q = &txq->q; | |
517 | struct iwl4965_tfd_frame *tfd; | |
b481de9c | 518 | u32 *control_flags; |
857485c0 | 519 | struct iwl_cmd *out_cmd; |
b481de9c ZY |
520 | u32 idx; |
521 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
522 | dma_addr_t phys_addr; | |
523 | int ret; | |
524 | unsigned long flags; | |
525 | ||
526 | /* If any of the command structures end up being larger than | |
527 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
528 | * we will need to increase the size of the TFD entries */ | |
529 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
530 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
531 | ||
fee1247a | 532 | if (iwl_is_rfkill(priv)) { |
c342a1b9 GG |
533 | IWL_DEBUG_INFO("Not sending command - RF KILL"); |
534 | return -EIO; | |
535 | } | |
536 | ||
bb8c093b | 537 | if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
538 | IWL_ERROR("No space for Tx\n"); |
539 | return -ENOSPC; | |
540 | } | |
541 | ||
542 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
543 | ||
fc4b6853 | 544 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
545 | memset(tfd, 0, sizeof(*tfd)); |
546 | ||
547 | control_flags = (u32 *) tfd; | |
548 | ||
fc4b6853 | 549 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
550 | out_cmd = &txq->cmd[idx]; |
551 | ||
552 | out_cmd->hdr.cmd = cmd->id; | |
553 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
554 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
555 | ||
556 | /* At this point, the out_cmd now has all of the incoming cmd | |
557 | * information */ | |
558 | ||
559 | out_cmd->hdr.flags = 0; | |
560 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 561 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c ZY |
562 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
563 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
564 | ||
565 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
857485c0 | 566 | offsetof(struct iwl_cmd, hdr); |
bb8c093b | 567 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
b481de9c ZY |
568 | |
569 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
570 | "%d bytes at %d[%d]:%d\n", | |
571 | get_cmd_string(out_cmd->hdr.cmd), | |
572 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 573 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
574 | |
575 | txq->need_update = 1; | |
6440adb5 BC |
576 | |
577 | /* Set up entry in queue's byte count circular buffer */ | |
e2a722eb | 578 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); |
6440adb5 BC |
579 | |
580 | /* Increment and update queue's write index */ | |
c54b679d | 581 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
e2a722eb | 582 | ret = iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
583 | |
584 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
585 | return ret ? ret : idx; | |
586 | } | |
587 | ||
deb09c43 EG |
588 | static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
589 | { | |
590 | struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; | |
591 | ||
592 | if (hw_decrypt) | |
593 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
594 | else | |
595 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
596 | ||
597 | } | |
598 | ||
c79dd5b5 | 599 | int iwl4965_send_statistics_request(struct iwl_priv *priv) |
b481de9c | 600 | { |
857485c0 TW |
601 | u32 flags = 0; |
602 | return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, | |
603 | sizeof(flags), &flags); | |
b481de9c ZY |
604 | } |
605 | ||
606 | /** | |
bb8c093b | 607 | * iwl4965_rxon_add_station - add station into station table. |
b481de9c ZY |
608 | * |
609 | * there is only one AP station with id= IWL_AP_ID | |
9fbab516 BC |
610 | * NOTE: mutex must be held before calling this fnction |
611 | */ | |
c79dd5b5 | 612 | static int iwl4965_rxon_add_station(struct iwl_priv *priv, |
b481de9c ZY |
613 | const u8 *addr, int is_ap) |
614 | { | |
556f8db7 | 615 | u8 sta_id; |
b481de9c | 616 | |
6440adb5 | 617 | /* Add station to device's station table */ |
67d62035 RR |
618 | #ifdef CONFIG_IWL4965_HT |
619 | struct ieee80211_conf *conf = &priv->hw->conf; | |
620 | struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf; | |
621 | ||
622 | if ((is_ap) && | |
623 | (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) && | |
624 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) | |
625 | sta_id = iwl4965_add_station_flags(priv, addr, is_ap, | |
626 | 0, cur_ht_config); | |
627 | else | |
628 | #endif /* CONFIG_IWL4965_HT */ | |
629 | sta_id = iwl4965_add_station_flags(priv, addr, is_ap, | |
630 | 0, NULL); | |
6440adb5 BC |
631 | |
632 | /* Set up default rate scaling table in device's station table */ | |
b481de9c ZY |
633 | iwl4965_add_station(priv, addr, is_ap); |
634 | ||
556f8db7 | 635 | return sta_id; |
b481de9c ZY |
636 | } |
637 | ||
b481de9c | 638 | /** |
bb8c093b | 639 | * iwl4965_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
640 | * |
641 | * NOTE: This is really only useful during development and can eventually | |
642 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
643 | * making changes | |
644 | */ | |
bb8c093b | 645 | static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon) |
b481de9c ZY |
646 | { |
647 | int error = 0; | |
648 | int counter = 1; | |
649 | ||
650 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
651 | error |= le32_to_cpu(rxon->flags & | |
652 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
653 | RXON_FLG_RADAR_DETECT_MSK)); | |
654 | if (error) | |
655 | IWL_WARNING("check 24G fields %d | %d\n", | |
656 | counter++, error); | |
657 | } else { | |
658 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
659 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
660 | if (error) | |
661 | IWL_WARNING("check 52 fields %d | %d\n", | |
662 | counter++, error); | |
663 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
664 | if (error) | |
665 | IWL_WARNING("check 52 CCK %d | %d\n", | |
666 | counter++, error); | |
667 | } | |
668 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
669 | if (error) | |
670 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
671 | ||
672 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
673 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
674 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
675 | if (error) | |
676 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
677 | ||
678 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
679 | if (error) | |
680 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
681 | ||
682 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
683 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
684 | if (error) | |
685 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
686 | counter++, error); | |
687 | ||
688 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
689 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
690 | if (error) | |
691 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
692 | counter++, error); | |
693 | ||
694 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
695 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
696 | if (error) | |
697 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
698 | counter++, error); | |
699 | ||
700 | if (error) | |
701 | IWL_WARNING("Tuning to channel %d\n", | |
702 | le16_to_cpu(rxon->channel)); | |
703 | ||
704 | if (error) { | |
bb8c093b | 705 | IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
706 | return -1; |
707 | } | |
708 | return 0; | |
709 | } | |
710 | ||
711 | /** | |
9fbab516 | 712 | * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 713 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 714 | * |
9fbab516 BC |
715 | * If the RXON structure is changing enough to require a new tune, |
716 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
717 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 718 | */ |
c79dd5b5 | 719 | static int iwl4965_full_rxon_required(struct iwl_priv *priv) |
b481de9c ZY |
720 | { |
721 | ||
722 | /* These items are only settable from the full RXON command */ | |
723 | if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || | |
724 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
725 | priv->active_rxon.bssid_addr) || | |
726 | compare_ether_addr(priv->staging_rxon.node_addr, | |
727 | priv->active_rxon.node_addr) || | |
728 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
729 | priv->active_rxon.wlap_bssid_addr) || | |
730 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
731 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
732 | (priv->staging_rxon.air_propagation != | |
733 | priv->active_rxon.air_propagation) || | |
734 | (priv->staging_rxon.ofdm_ht_single_stream_basic_rates != | |
735 | priv->active_rxon.ofdm_ht_single_stream_basic_rates) || | |
736 | (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates != | |
737 | priv->active_rxon.ofdm_ht_dual_stream_basic_rates) || | |
738 | (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) || | |
739 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) | |
740 | return 1; | |
741 | ||
742 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
743 | * be updated with the RXON_ASSOC command -- however only some | |
744 | * flag transitions are allowed using RXON_ASSOC */ | |
745 | ||
746 | /* Check if we are not switching bands */ | |
747 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
748 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
749 | return 1; | |
750 | ||
751 | /* Check if we are switching association toggle */ | |
752 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
753 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
754 | return 1; | |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
c79dd5b5 | 759 | static int iwl4965_send_rxon_assoc(struct iwl_priv *priv) |
b481de9c | 760 | { |
51dbfd1d | 761 | int ret = 0; |
bb8c093b | 762 | struct iwl4965_rxon_assoc_cmd rxon_assoc; |
bb8c093b CH |
763 | const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon; |
764 | const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon; | |
b481de9c ZY |
765 | |
766 | if ((rxon1->flags == rxon2->flags) && | |
767 | (rxon1->filter_flags == rxon2->filter_flags) && | |
768 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
769 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
770 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
771 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
772 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
773 | (rxon1->rx_chain == rxon2->rx_chain) && | |
774 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
775 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
776 | return 0; | |
777 | } | |
778 | ||
779 | rxon_assoc.flags = priv->staging_rxon.flags; | |
780 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
781 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
782 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
783 | rxon_assoc.reserved = 0; | |
784 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
785 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
786 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
787 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
788 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
789 | ||
51dbfd1d RC |
790 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, |
791 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
792 | if (ret) | |
793 | return ret; | |
b481de9c | 794 | |
51dbfd1d | 795 | return ret; |
b481de9c ZY |
796 | } |
797 | ||
798 | /** | |
bb8c093b | 799 | * iwl4965_commit_rxon - commit staging_rxon to hardware |
b481de9c | 800 | * |
01ebd063 | 801 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
802 | * the active_rxon structure is updated with the new data. This |
803 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
804 | * a HW tune is required based on the RXON structure changes. | |
805 | */ | |
c79dd5b5 | 806 | static int iwl4965_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
807 | { |
808 | /* cast away the const for active_rxon in this function */ | |
bb8c093b | 809 | struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
0795af57 | 810 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
811 | int rc = 0; |
812 | ||
fee1247a | 813 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
814 | return -1; |
815 | ||
816 | /* always get timestamp with Rx frame */ | |
817 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
818 | ||
bb8c093b | 819 | rc = iwl4965_check_rxon_cmd(&priv->staging_rxon); |
b481de9c ZY |
820 | if (rc) { |
821 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
822 | return -EINVAL; | |
823 | } | |
824 | ||
825 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 826 | * iwl4965_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 827 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
828 | if (!iwl4965_full_rxon_required(priv)) { |
829 | rc = iwl4965_send_rxon_assoc(priv); | |
b481de9c ZY |
830 | if (rc) { |
831 | IWL_ERROR("Error setting RXON_ASSOC " | |
832 | "configuration (%d).\n", rc); | |
833 | return rc; | |
834 | } | |
835 | ||
836 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | /* station table will be cleared */ | |
842 | priv->assoc_station_added = 0; | |
843 | ||
c8b0e6e1 | 844 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
845 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; |
846 | if (!priv->error_recovering) | |
847 | priv->start_calib = 0; | |
848 | ||
849 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 1); | |
c8b0e6e1 | 850 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
851 | |
852 | /* If we are currently associated and the new config requires | |
853 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
854 | * we must clear the associated from the active configuration | |
855 | * before we apply the new config */ | |
3109ece1 | 856 | if (iwl_is_associated(priv) && |
b481de9c ZY |
857 | (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
858 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); | |
859 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
860 | ||
857485c0 | 861 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON, |
bb8c093b | 862 | sizeof(struct iwl4965_rxon_cmd), |
b481de9c ZY |
863 | &priv->active_rxon); |
864 | ||
865 | /* If the mask clearing failed then we set | |
866 | * active_rxon back to what it was previously */ | |
867 | if (rc) { | |
868 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
869 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
870 | "configuration (%d).\n", rc); | |
871 | return rc; | |
872 | } | |
b481de9c ZY |
873 | } |
874 | ||
875 | IWL_DEBUG_INFO("Sending RXON\n" | |
876 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
877 | "* channel = %d\n" | |
0795af57 | 878 | "* bssid = %s\n", |
b481de9c ZY |
879 | ((priv->staging_rxon.filter_flags & |
880 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), | |
881 | le16_to_cpu(priv->staging_rxon.channel), | |
0795af57 | 882 | print_mac(mac, priv->staging_rxon.bssid_addr)); |
b481de9c | 883 | |
deb09c43 | 884 | iwl4965_set_rxon_hwcrypto(priv, priv->cfg->mod_params->hw_crypto); |
b481de9c | 885 | /* Apply the new configuration */ |
857485c0 | 886 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON, |
bb8c093b | 887 | sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon); |
b481de9c ZY |
888 | if (rc) { |
889 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
890 | return rc; | |
891 | } | |
892 | ||
bf85ea4f | 893 | iwlcore_clear_stations_table(priv); |
556f8db7 | 894 | |
c8b0e6e1 | 895 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
896 | if (!priv->error_recovering) |
897 | priv->start_calib = 0; | |
898 | ||
899 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; | |
900 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 1); | |
c8b0e6e1 | 901 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
902 | |
903 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
904 | ||
905 | /* If we issue a new RXON command which required a tune then we must | |
906 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 907 | rc = iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
908 | if (rc) { |
909 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
910 | return rc; | |
911 | } | |
912 | ||
913 | /* Add the broadcast address so we can send broadcast frames */ | |
bb8c093b | 914 | if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) == |
b481de9c ZY |
915 | IWL_INVALID_STATION) { |
916 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
917 | return -EIO; | |
918 | } | |
919 | ||
920 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
921 | * add the IWL_AP_ID to the station rate table */ | |
3109ece1 | 922 | if (iwl_is_associated(priv) && |
b481de9c | 923 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) { |
bb8c093b | 924 | if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1) |
b481de9c ZY |
925 | == IWL_INVALID_STATION) { |
926 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
927 | return -EIO; | |
928 | } | |
929 | priv->assoc_station_added = 1; | |
6974e363 EG |
930 | if (priv->default_wep_key && |
931 | iwl_send_static_wepkey_cmd(priv, 0)) | |
932 | IWL_ERROR("Could not send WEP static key.\n"); | |
b481de9c ZY |
933 | } |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
c79dd5b5 | 938 | static int iwl4965_send_bt_config(struct iwl_priv *priv) |
b481de9c | 939 | { |
bb8c093b | 940 | struct iwl4965_bt_cmd bt_cmd = { |
b481de9c ZY |
941 | .flags = 3, |
942 | .lead_time = 0xAA, | |
943 | .max_kill = 1, | |
944 | .kill_ack_mask = 0, | |
945 | .kill_cts_mask = 0, | |
946 | }; | |
947 | ||
857485c0 | 948 | return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
bb8c093b | 949 | sizeof(struct iwl4965_bt_cmd), &bt_cmd); |
b481de9c ZY |
950 | } |
951 | ||
c79dd5b5 | 952 | static int iwl4965_send_scan_abort(struct iwl_priv *priv) |
b481de9c ZY |
953 | { |
954 | int rc = 0; | |
bb8c093b | 955 | struct iwl4965_rx_packet *res; |
857485c0 | 956 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
957 | .id = REPLY_SCAN_ABORT_CMD, |
958 | .meta.flags = CMD_WANT_SKB, | |
959 | }; | |
960 | ||
961 | /* If there isn't a scan actively going on in the hardware | |
962 | * then we are in between scan bands and not actually | |
963 | * actively scanning, so don't send the abort command */ | |
964 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
965 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
966 | return 0; | |
967 | } | |
968 | ||
857485c0 | 969 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
970 | if (rc) { |
971 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
972 | return rc; | |
973 | } | |
974 | ||
bb8c093b | 975 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
976 | if (res->u.status != CAN_ABORT_STATUS) { |
977 | /* The scan abort will return 1 for success or | |
978 | * 2 for "failure". A failure condition can be | |
979 | * due to simply not being in an active scan which | |
980 | * can occur if we send the scan abort before we | |
981 | * the microcode has notified us that a scan is | |
982 | * completed. */ | |
983 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
984 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
985 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
986 | } | |
987 | ||
988 | dev_kfree_skb_any(cmd.meta.u.skb); | |
989 | ||
990 | return rc; | |
991 | } | |
992 | ||
c79dd5b5 | 993 | static int iwl4965_card_state_sync_callback(struct iwl_priv *priv, |
857485c0 | 994 | struct iwl_cmd *cmd, |
b481de9c ZY |
995 | struct sk_buff *skb) |
996 | { | |
997 | return 1; | |
998 | } | |
999 | ||
1000 | /* | |
1001 | * CARD_STATE_CMD | |
1002 | * | |
9fbab516 | 1003 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
1004 | * |
1005 | * When in the 'enable' state the card operates as normal. | |
1006 | * When in the 'disable' state, the card enters into a low power mode. | |
1007 | * When in the 'halt' state, the card is shut down and must be fully | |
1008 | * restarted to come back on. | |
1009 | */ | |
c79dd5b5 | 1010 | static int iwl4965_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1011 | { |
857485c0 | 1012 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
1013 | .id = REPLY_CARD_STATE_CMD, |
1014 | .len = sizeof(u32), | |
1015 | .data = &flags, | |
1016 | .meta.flags = meta_flag, | |
1017 | }; | |
1018 | ||
1019 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1020 | cmd.meta.u.callback = iwl4965_card_state_sync_callback; |
b481de9c | 1021 | |
857485c0 | 1022 | return iwl_send_cmd(priv, &cmd); |
b481de9c ZY |
1023 | } |
1024 | ||
c79dd5b5 | 1025 | static int iwl4965_add_sta_sync_callback(struct iwl_priv *priv, |
857485c0 | 1026 | struct iwl_cmd *cmd, struct sk_buff *skb) |
b481de9c | 1027 | { |
bb8c093b | 1028 | struct iwl4965_rx_packet *res = NULL; |
b481de9c ZY |
1029 | |
1030 | if (!skb) { | |
1031 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1032 | return 1; | |
1033 | } | |
1034 | ||
bb8c093b | 1035 | res = (struct iwl4965_rx_packet *)skb->data; |
b481de9c ZY |
1036 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1037 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1038 | res->hdr.flags); | |
1039 | return 1; | |
1040 | } | |
1041 | ||
1042 | switch (res->u.add_sta.status) { | |
1043 | case ADD_STA_SUCCESS_MSK: | |
1044 | break; | |
1045 | default: | |
1046 | break; | |
1047 | } | |
1048 | ||
1049 | /* We didn't cache the SKB; let the caller free it */ | |
1050 | return 1; | |
1051 | } | |
1052 | ||
c79dd5b5 | 1053 | int iwl4965_send_add_station(struct iwl_priv *priv, |
bb8c093b | 1054 | struct iwl4965_addsta_cmd *sta, u8 flags) |
b481de9c | 1055 | { |
bb8c093b | 1056 | struct iwl4965_rx_packet *res = NULL; |
b481de9c | 1057 | int rc = 0; |
857485c0 | 1058 | struct iwl_host_cmd cmd = { |
b481de9c | 1059 | .id = REPLY_ADD_STA, |
bb8c093b | 1060 | .len = sizeof(struct iwl4965_addsta_cmd), |
b481de9c ZY |
1061 | .meta.flags = flags, |
1062 | .data = sta, | |
1063 | }; | |
1064 | ||
1065 | if (flags & CMD_ASYNC) | |
bb8c093b | 1066 | cmd.meta.u.callback = iwl4965_add_sta_sync_callback; |
b481de9c ZY |
1067 | else |
1068 | cmd.meta.flags |= CMD_WANT_SKB; | |
1069 | ||
857485c0 | 1070 | rc = iwl_send_cmd(priv, &cmd); |
b481de9c ZY |
1071 | |
1072 | if (rc || (flags & CMD_ASYNC)) | |
1073 | return rc; | |
1074 | ||
bb8c093b | 1075 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1076 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1077 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1078 | res->hdr.flags); | |
1079 | rc = -EIO; | |
1080 | } | |
1081 | ||
1082 | if (rc == 0) { | |
1083 | switch (res->u.add_sta.status) { | |
1084 | case ADD_STA_SUCCESS_MSK: | |
1085 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1086 | break; | |
1087 | default: | |
1088 | rc = -EIO; | |
1089 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1090 | break; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | priv->alloc_rxb_skb--; | |
1095 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1096 | ||
1097 | return rc; | |
1098 | } | |
1099 | ||
c79dd5b5 | 1100 | static void iwl4965_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
1101 | { |
1102 | struct list_head *element; | |
1103 | ||
1104 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1105 | priv->frames_count); | |
1106 | ||
1107 | while (!list_empty(&priv->free_frames)) { | |
1108 | element = priv->free_frames.next; | |
1109 | list_del(element); | |
bb8c093b | 1110 | kfree(list_entry(element, struct iwl4965_frame, list)); |
b481de9c ZY |
1111 | priv->frames_count--; |
1112 | } | |
1113 | ||
1114 | if (priv->frames_count) { | |
1115 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1116 | priv->frames_count); | |
1117 | priv->frames_count = 0; | |
1118 | } | |
1119 | } | |
1120 | ||
c79dd5b5 | 1121 | static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl_priv *priv) |
b481de9c | 1122 | { |
bb8c093b | 1123 | struct iwl4965_frame *frame; |
b481de9c ZY |
1124 | struct list_head *element; |
1125 | if (list_empty(&priv->free_frames)) { | |
1126 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1127 | if (!frame) { | |
1128 | IWL_ERROR("Could not allocate frame!\n"); | |
1129 | return NULL; | |
1130 | } | |
1131 | ||
1132 | priv->frames_count++; | |
1133 | return frame; | |
1134 | } | |
1135 | ||
1136 | element = priv->free_frames.next; | |
1137 | list_del(element); | |
bb8c093b | 1138 | return list_entry(element, struct iwl4965_frame, list); |
b481de9c ZY |
1139 | } |
1140 | ||
c79dd5b5 | 1141 | static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl4965_frame *frame) |
b481de9c ZY |
1142 | { |
1143 | memset(frame, 0, sizeof(*frame)); | |
1144 | list_add(&frame->list, &priv->free_frames); | |
1145 | } | |
1146 | ||
c79dd5b5 | 1147 | unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c ZY |
1148 | struct ieee80211_hdr *hdr, |
1149 | const u8 *dest, int left) | |
1150 | { | |
1151 | ||
3109ece1 | 1152 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
b481de9c ZY |
1153 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && |
1154 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) | |
1155 | return 0; | |
1156 | ||
1157 | if (priv->ibss_beacon->len > left) | |
1158 | return 0; | |
1159 | ||
1160 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1161 | ||
1162 | return priv->ibss_beacon->len; | |
1163 | } | |
1164 | ||
bb8c093b | 1165 | static u8 iwl4965_rate_get_lowest_plcp(int rate_mask) |
b481de9c ZY |
1166 | { |
1167 | u8 i; | |
1168 | ||
1169 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1170 | i = iwl4965_rates[i].next_ieee) { |
b481de9c | 1171 | if (rate_mask & (1 << i)) |
bb8c093b | 1172 | return iwl4965_rates[i].plcp; |
b481de9c ZY |
1173 | } |
1174 | ||
1175 | return IWL_RATE_INVALID; | |
1176 | } | |
1177 | ||
c79dd5b5 | 1178 | static int iwl4965_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 1179 | { |
bb8c093b | 1180 | struct iwl4965_frame *frame; |
b481de9c ZY |
1181 | unsigned int frame_size; |
1182 | int rc; | |
1183 | u8 rate; | |
1184 | ||
bb8c093b | 1185 | frame = iwl4965_get_free_frame(priv); |
b481de9c ZY |
1186 | |
1187 | if (!frame) { | |
1188 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1189 | "command.\n"); | |
1190 | return -ENOMEM; | |
1191 | } | |
1192 | ||
1193 | if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { | |
bb8c093b | 1194 | rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & |
b481de9c ZY |
1195 | 0xFF0); |
1196 | if (rate == IWL_INVALID_RATE) | |
1197 | rate = IWL_RATE_6M_PLCP; | |
1198 | } else { | |
bb8c093b | 1199 | rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF); |
b481de9c ZY |
1200 | if (rate == IWL_INVALID_RATE) |
1201 | rate = IWL_RATE_1M_PLCP; | |
1202 | } | |
1203 | ||
bb8c093b | 1204 | frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1205 | |
857485c0 | 1206 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1207 | &frame->u.cmd[0]); |
1208 | ||
bb8c093b | 1209 | iwl4965_free_frame(priv, frame); |
b481de9c ZY |
1210 | |
1211 | return rc; | |
1212 | } | |
1213 | ||
b481de9c ZY |
1214 | /****************************************************************************** |
1215 | * | |
1216 | * Misc. internal state and helper functions | |
1217 | * | |
1218 | ******************************************************************************/ | |
b481de9c | 1219 | |
c79dd5b5 | 1220 | static void iwl4965_unset_hw_setting(struct iwl_priv *priv) |
b481de9c | 1221 | { |
059ff826 | 1222 | if (priv->shared_virt) |
b481de9c | 1223 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 1224 | sizeof(struct iwl4965_shared), |
059ff826 TW |
1225 | priv->shared_virt, |
1226 | priv->shared_phys); | |
b481de9c ZY |
1227 | } |
1228 | ||
1229 | /** | |
bb8c093b | 1230 | * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1231 | * |
1232 | * return : set the bit for each supported rate insert in ie | |
1233 | */ | |
bb8c093b | 1234 | static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1235 | u16 basic_rate, int *left) |
b481de9c ZY |
1236 | { |
1237 | u16 ret_rates = 0, bit; | |
1238 | int i; | |
c7c46676 TW |
1239 | u8 *cnt = ie; |
1240 | u8 *rates = ie + 1; | |
b481de9c ZY |
1241 | |
1242 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1243 | if (bit & supported_rate) { | |
1244 | ret_rates |= bit; | |
bb8c093b | 1245 | rates[*cnt] = iwl4965_rates[i].ieee | |
c7c46676 TW |
1246 | ((bit & basic_rate) ? 0x80 : 0x00); |
1247 | (*cnt)++; | |
1248 | (*left)--; | |
1249 | if ((*left <= 0) || | |
1250 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1251 | break; |
1252 | } | |
1253 | } | |
1254 | ||
1255 | return ret_rates; | |
1256 | } | |
1257 | ||
b481de9c | 1258 | /** |
bb8c093b | 1259 | * iwl4965_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1260 | */ |
c79dd5b5 | 1261 | static u16 iwl4965_fill_probe_req(struct iwl_priv *priv, |
78330fdd TW |
1262 | enum ieee80211_band band, |
1263 | struct ieee80211_mgmt *frame, | |
1264 | int left, int is_direct) | |
b481de9c ZY |
1265 | { |
1266 | int len = 0; | |
1267 | u8 *pos = NULL; | |
bee488db | 1268 | u16 active_rates, ret_rates, cck_rates, active_rate_basic; |
8fb88032 | 1269 | #ifdef CONFIG_IWL4965_HT |
78330fdd TW |
1270 | const struct ieee80211_supported_band *sband = |
1271 | iwl4965_get_hw_mode(priv, band); | |
8fb88032 | 1272 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
1273 | |
1274 | /* Make sure there is enough space for the probe request, | |
1275 | * two mandatory IEs and the data */ | |
1276 | left -= 24; | |
1277 | if (left < 0) | |
1278 | return 0; | |
1279 | len += 24; | |
1280 | ||
1281 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
bb8c093b | 1282 | memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN); |
b481de9c | 1283 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
bb8c093b | 1284 | memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN); |
b481de9c ZY |
1285 | frame->seq_ctrl = 0; |
1286 | ||
1287 | /* fill in our indirect SSID IE */ | |
1288 | /* ...next IE... */ | |
1289 | ||
1290 | left -= 2; | |
1291 | if (left < 0) | |
1292 | return 0; | |
1293 | len += 2; | |
1294 | pos = &(frame->u.probe_req.variable[0]); | |
1295 | *pos++ = WLAN_EID_SSID; | |
1296 | *pos++ = 0; | |
1297 | ||
1298 | /* fill in our direct SSID IE... */ | |
1299 | if (is_direct) { | |
1300 | /* ...next IE... */ | |
1301 | left -= 2 + priv->essid_len; | |
1302 | if (left < 0) | |
1303 | return 0; | |
1304 | /* ... fill it in... */ | |
1305 | *pos++ = WLAN_EID_SSID; | |
1306 | *pos++ = priv->essid_len; | |
1307 | memcpy(pos, priv->essid, priv->essid_len); | |
1308 | pos += priv->essid_len; | |
1309 | len += 2 + priv->essid_len; | |
1310 | } | |
1311 | ||
1312 | /* fill in supported rate */ | |
1313 | /* ...next IE... */ | |
1314 | left -= 2; | |
1315 | if (left < 0) | |
1316 | return 0; | |
c7c46676 | 1317 | |
b481de9c ZY |
1318 | /* ... fill it in... */ |
1319 | *pos++ = WLAN_EID_SUPP_RATES; | |
1320 | *pos = 0; | |
c7c46676 | 1321 | |
bee488db | 1322 | /* exclude 60M rate */ |
1323 | active_rates = priv->rates_mask; | |
1324 | active_rates &= ~IWL_RATE_60M_MASK; | |
1325 | ||
1326 | active_rate_basic = active_rates & IWL_BASIC_RATES_MASK; | |
b481de9c | 1327 | |
c7c46676 | 1328 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1329 | ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates, |
bee488db | 1330 | active_rate_basic, &left); |
c7c46676 TW |
1331 | active_rates &= ~ret_rates; |
1332 | ||
bb8c093b | 1333 | ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates, |
bee488db | 1334 | active_rate_basic, &left); |
c7c46676 TW |
1335 | active_rates &= ~ret_rates; |
1336 | ||
b481de9c ZY |
1337 | len += 2 + *pos; |
1338 | pos += (*pos) + 1; | |
c7c46676 | 1339 | if (active_rates == 0) |
b481de9c ZY |
1340 | goto fill_end; |
1341 | ||
1342 | /* fill in supported extended rate */ | |
1343 | /* ...next IE... */ | |
1344 | left -= 2; | |
1345 | if (left < 0) | |
1346 | return 0; | |
1347 | /* ... fill it in... */ | |
1348 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1349 | *pos = 0; | |
bb8c093b | 1350 | iwl4965_supported_rate_to_ie(pos, active_rates, |
bee488db | 1351 | active_rate_basic, &left); |
b481de9c ZY |
1352 | if (*pos > 0) |
1353 | len += 2 + *pos; | |
1354 | ||
c8b0e6e1 | 1355 | #ifdef CONFIG_IWL4965_HT |
78330fdd TW |
1356 | if (sband && sband->ht_info.ht_supported) { |
1357 | struct ieee80211_ht_cap *ht_cap; | |
b481de9c ZY |
1358 | pos += (*pos) + 1; |
1359 | *pos++ = WLAN_EID_HT_CAPABILITY; | |
8fb88032 | 1360 | *pos++ = sizeof(struct ieee80211_ht_cap); |
78330fdd TW |
1361 | ht_cap = (struct ieee80211_ht_cap *)pos; |
1362 | ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap); | |
1363 | memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16); | |
1364 | ht_cap->ampdu_params_info =(sband->ht_info.ampdu_factor & | |
1365 | IEEE80211_HT_CAP_AMPDU_FACTOR) | | |
1366 | ((sband->ht_info.ampdu_density << 2) & | |
1367 | IEEE80211_HT_CAP_AMPDU_DENSITY); | |
8fb88032 | 1368 | len += 2 + sizeof(struct ieee80211_ht_cap); |
b481de9c | 1369 | } |
c8b0e6e1 | 1370 | #endif /*CONFIG_IWL4965_HT */ |
b481de9c ZY |
1371 | |
1372 | fill_end: | |
1373 | return (u16)len; | |
1374 | } | |
1375 | ||
1376 | /* | |
1377 | * QoS support | |
1378 | */ | |
c79dd5b5 | 1379 | static int iwl4965_send_qos_params_command(struct iwl_priv *priv, |
bb8c093b | 1380 | struct iwl4965_qosparam_cmd *qos) |
b481de9c ZY |
1381 | { |
1382 | ||
857485c0 | 1383 | return iwl_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
bb8c093b | 1384 | sizeof(struct iwl4965_qosparam_cmd), qos); |
b481de9c ZY |
1385 | } |
1386 | ||
c79dd5b5 | 1387 | static void iwl4965_activate_qos(struct iwl_priv *priv, u8 force) |
b481de9c ZY |
1388 | { |
1389 | unsigned long flags; | |
1390 | ||
b481de9c ZY |
1391 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1392 | return; | |
1393 | ||
1394 | if (!priv->qos_data.qos_enable) | |
1395 | return; | |
1396 | ||
1397 | spin_lock_irqsave(&priv->lock, flags); | |
1398 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1399 | ||
1400 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1401 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1402 | priv->qos_data.def_qos_parm.qos_flags |= | |
1403 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
b481de9c ZY |
1404 | if (priv->qos_data.qos_active) |
1405 | priv->qos_data.def_qos_parm.qos_flags |= | |
1406 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1407 | ||
c8b0e6e1 | 1408 | #ifdef CONFIG_IWL4965_HT |
fd105e79 | 1409 | if (priv->current_ht_config.is_ht) |
f1f1f5c7 | 1410 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; |
c8b0e6e1 | 1411 | #endif /* CONFIG_IWL4965_HT */ |
f1f1f5c7 | 1412 | |
b481de9c ZY |
1413 | spin_unlock_irqrestore(&priv->lock, flags); |
1414 | ||
3109ece1 | 1415 | if (force || iwl_is_associated(priv)) { |
f1f1f5c7 TW |
1416 | IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
1417 | priv->qos_data.qos_active, | |
1418 | priv->qos_data.def_qos_parm.qos_flags); | |
b481de9c | 1419 | |
bb8c093b | 1420 | iwl4965_send_qos_params_command(priv, |
b481de9c ZY |
1421 | &(priv->qos_data.def_qos_parm)); |
1422 | } | |
1423 | } | |
1424 | ||
b481de9c ZY |
1425 | /* |
1426 | * Power management (not Tx power!) functions | |
1427 | */ | |
1428 | #define MSEC_TO_USEC 1024 | |
1429 | ||
1430 | #define NOSLP __constant_cpu_to_le16(0), 0, 0 | |
1431 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
1432 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) | |
1433 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1434 | __constant_cpu_to_le32(X1), \ | |
1435 | __constant_cpu_to_le32(X2), \ | |
1436 | __constant_cpu_to_le32(X3), \ | |
1437 | __constant_cpu_to_le32(X4)} | |
1438 | ||
1439 | ||
1440 | /* default power management (not Tx power) table values */ | |
1441 | /* for tim 0-10 */ | |
bb8c093b | 1442 | static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = { |
b481de9c ZY |
1443 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1444 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1445 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1446 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1447 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1448 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1449 | }; | |
1450 | ||
1451 | /* for tim > 10 */ | |
bb8c093b | 1452 | static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = { |
b481de9c ZY |
1453 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1454 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1455 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1456 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1457 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1458 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1459 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1460 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1461 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1462 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1463 | }; | |
1464 | ||
c79dd5b5 | 1465 | int iwl4965_power_init_handle(struct iwl_priv *priv) |
b481de9c ZY |
1466 | { |
1467 | int rc = 0, i; | |
bb8c093b CH |
1468 | struct iwl4965_power_mgr *pow_data; |
1469 | int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC; | |
b481de9c ZY |
1470 | u16 pci_pm; |
1471 | ||
1472 | IWL_DEBUG_POWER("Initialize power \n"); | |
1473 | ||
1474 | pow_data = &(priv->power_data); | |
1475 | ||
1476 | memset(pow_data, 0, sizeof(*pow_data)); | |
1477 | ||
1478 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1479 | pow_data->dtim_val = 0xffff; | |
1480 | ||
1481 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1482 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1483 | ||
1484 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1485 | if (rc != 0) | |
1486 | return 0; | |
1487 | else { | |
bb8c093b | 1488 | struct iwl4965_powertable_cmd *cmd; |
b481de9c ZY |
1489 | |
1490 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1491 | ||
1492 | for (i = 0; i < IWL_POWER_AC; i++) { | |
1493 | cmd = &pow_data->pwr_range_0[i].cmd; | |
1494 | ||
1495 | if (pci_pm & 0x1) | |
1496 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1497 | else | |
1498 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1499 | } | |
1500 | } | |
1501 | return rc; | |
1502 | } | |
1503 | ||
c79dd5b5 | 1504 | static int iwl4965_update_power_cmd(struct iwl_priv *priv, |
bb8c093b | 1505 | struct iwl4965_powertable_cmd *cmd, u32 mode) |
b481de9c ZY |
1506 | { |
1507 | int rc = 0, i; | |
1508 | u8 skip; | |
1509 | u32 max_sleep = 0; | |
bb8c093b | 1510 | struct iwl4965_power_vec_entry *range; |
b481de9c | 1511 | u8 period = 0; |
bb8c093b | 1512 | struct iwl4965_power_mgr *pow_data; |
b481de9c ZY |
1513 | |
1514 | if (mode > IWL_POWER_INDEX_5) { | |
1515 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1516 | return -1; | |
1517 | } | |
1518 | pow_data = &(priv->power_data); | |
1519 | ||
1520 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1521 | range = &pow_data->pwr_range_0[0]; | |
1522 | else | |
1523 | range = &pow_data->pwr_range_1[1]; | |
1524 | ||
bb8c093b | 1525 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd)); |
b481de9c ZY |
1526 | |
1527 | #ifdef IWL_MAC80211_DISABLE | |
1528 | if (priv->assoc_network != NULL) { | |
1529 | unsigned long flags; | |
1530 | ||
1531 | period = priv->assoc_network->tim.tim_period; | |
1532 | } | |
1533 | #endif /*IWL_MAC80211_DISABLE */ | |
1534 | skip = range[mode].no_dtim; | |
1535 | ||
1536 | if (period == 0) { | |
1537 | period = 1; | |
1538 | skip = 0; | |
1539 | } | |
1540 | ||
1541 | if (skip == 0) { | |
1542 | max_sleep = period; | |
1543 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1544 | } else { | |
1545 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1546 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1547 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1548 | } | |
1549 | ||
1550 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1551 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1552 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1553 | } | |
1554 | ||
1555 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1556 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1557 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1558 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1559 | le32_to_cpu(cmd->sleep_interval[0]), | |
1560 | le32_to_cpu(cmd->sleep_interval[1]), | |
1561 | le32_to_cpu(cmd->sleep_interval[2]), | |
1562 | le32_to_cpu(cmd->sleep_interval[3]), | |
1563 | le32_to_cpu(cmd->sleep_interval[4])); | |
1564 | ||
1565 | return rc; | |
1566 | } | |
1567 | ||
c79dd5b5 | 1568 | static int iwl4965_send_power_mode(struct iwl_priv *priv, u32 mode) |
b481de9c | 1569 | { |
9a62f73b | 1570 | u32 uninitialized_var(final_mode); |
b481de9c | 1571 | int rc; |
bb8c093b | 1572 | struct iwl4965_powertable_cmd cmd; |
b481de9c ZY |
1573 | |
1574 | /* If on battery, set to 3, | |
01ebd063 | 1575 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
1576 | * else user level */ |
1577 | switch (mode) { | |
1578 | case IWL_POWER_BATTERY: | |
1579 | final_mode = IWL_POWER_INDEX_3; | |
1580 | break; | |
1581 | case IWL_POWER_AC: | |
1582 | final_mode = IWL_POWER_MODE_CAM; | |
1583 | break; | |
1584 | default: | |
1585 | final_mode = mode; | |
1586 | break; | |
1587 | } | |
1588 | ||
1589 | cmd.keep_alive_beacons = 0; | |
1590 | ||
bb8c093b | 1591 | iwl4965_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 1592 | |
857485c0 | 1593 | rc = iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
1594 | |
1595 | if (final_mode == IWL_POWER_MODE_CAM) | |
1596 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
1597 | else | |
1598 | set_bit(STATUS_POWER_PMI, &priv->status); | |
1599 | ||
1600 | return rc; | |
1601 | } | |
1602 | ||
c79dd5b5 | 1603 | int iwl4965_is_network_packet(struct iwl_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
1604 | { |
1605 | /* Filter incoming packets to determine if they are targeted toward | |
1606 | * this network, discarding packets coming from ourselves */ | |
1607 | switch (priv->iw_mode) { | |
1608 | case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */ | |
1609 | /* packets from our adapter are dropped (echo) */ | |
1610 | if (!compare_ether_addr(header->addr2, priv->mac_addr)) | |
1611 | return 0; | |
1612 | /* {broad,multi}cast packets to our IBSS go through */ | |
1613 | if (is_multicast_ether_addr(header->addr1)) | |
1614 | return !compare_ether_addr(header->addr3, priv->bssid); | |
1615 | /* packets to our adapter go through */ | |
1616 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
1617 | case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */ | |
1618 | /* packets from our adapter are dropped (echo) */ | |
1619 | if (!compare_ether_addr(header->addr3, priv->mac_addr)) | |
1620 | return 0; | |
1621 | /* {broad,multi}cast packets to our BSS go through */ | |
1622 | if (is_multicast_ether_addr(header->addr1)) | |
1623 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1624 | /* packets to our adapter go through */ | |
1625 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
69dc5d9d TW |
1626 | default: |
1627 | break; | |
b481de9c ZY |
1628 | } |
1629 | ||
1630 | return 1; | |
1631 | } | |
1632 | ||
1633 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
1634 | ||
bb8c093b | 1635 | static const char *iwl4965_get_tx_fail_reason(u32 status) |
b481de9c ZY |
1636 | { |
1637 | switch (status & TX_STATUS_MSK) { | |
1638 | case TX_STATUS_SUCCESS: | |
1639 | return "SUCCESS"; | |
1640 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1641 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1642 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1643 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1644 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1645 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1646 | TX_STATUS_ENTRY(DEST_PS); | |
1647 | TX_STATUS_ENTRY(ABORTED); | |
1648 | TX_STATUS_ENTRY(BT_RETRY); | |
1649 | TX_STATUS_ENTRY(STA_INVALID); | |
1650 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1651 | TX_STATUS_ENTRY(TID_DISABLE); | |
1652 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1653 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1654 | TX_STATUS_ENTRY(TX_LOCKED); | |
1655 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1656 | } | |
1657 | ||
1658 | return "UNKNOWN"; | |
1659 | } | |
1660 | ||
1661 | /** | |
bb8c093b | 1662 | * iwl4965_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
1663 | * |
1664 | * NOTE: priv->mutex is not required before calling this function | |
1665 | */ | |
c79dd5b5 | 1666 | static int iwl4965_scan_cancel(struct iwl_priv *priv) |
b481de9c ZY |
1667 | { |
1668 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1669 | clear_bit(STATUS_SCANNING, &priv->status); | |
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1674 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1675 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
1676 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1677 | queue_work(priv->workqueue, &priv->abort_scan); | |
1678 | ||
1679 | } else | |
1680 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
1681 | ||
1682 | return test_bit(STATUS_SCANNING, &priv->status); | |
1683 | } | |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | /** | |
bb8c093b | 1689 | * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
1690 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
1691 | * | |
1692 | * NOTE: priv->mutex must be held before calling this function | |
1693 | */ | |
c79dd5b5 | 1694 | static int iwl4965_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms) |
b481de9c ZY |
1695 | { |
1696 | unsigned long now = jiffies; | |
1697 | int ret; | |
1698 | ||
bb8c093b | 1699 | ret = iwl4965_scan_cancel(priv); |
b481de9c ZY |
1700 | if (ret && ms) { |
1701 | mutex_unlock(&priv->mutex); | |
1702 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
1703 | test_bit(STATUS_SCANNING, &priv->status)) | |
1704 | msleep(1); | |
1705 | mutex_lock(&priv->mutex); | |
1706 | ||
1707 | return test_bit(STATUS_SCANNING, &priv->status); | |
1708 | } | |
1709 | ||
1710 | return ret; | |
1711 | } | |
1712 | ||
c79dd5b5 | 1713 | static void iwl4965_sequence_reset(struct iwl_priv *priv) |
b481de9c ZY |
1714 | { |
1715 | /* Reset ieee stats */ | |
1716 | ||
1717 | /* We don't reset the net_device_stats (ieee->stats) on | |
1718 | * re-association */ | |
1719 | ||
1720 | priv->last_seq_num = -1; | |
1721 | priv->last_frag_num = -1; | |
1722 | priv->last_packet_time = 0; | |
1723 | ||
bb8c093b | 1724 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
1725 | } |
1726 | ||
1727 | #define MAX_UCODE_BEACON_INTERVAL 4096 | |
1728 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
1729 | ||
bb8c093b | 1730 | static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
1731 | { |
1732 | u16 new_val = 0; | |
1733 | u16 beacon_factor = 0; | |
1734 | ||
1735 | beacon_factor = | |
1736 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
1737 | / MAX_UCODE_BEACON_INTERVAL; | |
1738 | new_val = beacon_val / beacon_factor; | |
1739 | ||
1740 | return cpu_to_le16(new_val); | |
1741 | } | |
1742 | ||
c79dd5b5 | 1743 | static void iwl4965_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
1744 | { |
1745 | u64 interval_tm_unit; | |
1746 | u64 tsf, result; | |
1747 | unsigned long flags; | |
1748 | struct ieee80211_conf *conf = NULL; | |
1749 | u16 beacon_int = 0; | |
1750 | ||
1751 | conf = ieee80211_get_hw_conf(priv->hw); | |
1752 | ||
1753 | spin_lock_irqsave(&priv->lock, flags); | |
3109ece1 TW |
1754 | priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp >> 32); |
1755 | priv->rxon_timing.timestamp.dw[0] = | |
1756 | cpu_to_le32(priv->timestamp & 0xFFFFFFFF); | |
b481de9c ZY |
1757 | |
1758 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | |
1759 | ||
3109ece1 | 1760 | tsf = priv->timestamp; |
b481de9c ZY |
1761 | |
1762 | beacon_int = priv->beacon_int; | |
1763 | spin_unlock_irqrestore(&priv->lock, flags); | |
1764 | ||
1765 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) { | |
1766 | if (beacon_int == 0) { | |
1767 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
1768 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
1769 | } else { | |
1770 | priv->rxon_timing.beacon_interval = | |
1771 | cpu_to_le16(beacon_int); | |
1772 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1773 | iwl4965_adjust_beacon_interval( |
b481de9c ZY |
1774 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
1775 | } | |
1776 | ||
1777 | priv->rxon_timing.atim_window = 0; | |
1778 | } else { | |
1779 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1780 | iwl4965_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
1781 | /* TODO: we need to get atim_window from upper stack |
1782 | * for now we set to 0 */ | |
1783 | priv->rxon_timing.atim_window = 0; | |
1784 | } | |
1785 | ||
1786 | interval_tm_unit = | |
1787 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
1788 | result = do_div(tsf, interval_tm_unit); | |
1789 | priv->rxon_timing.beacon_init_val = | |
1790 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
1791 | ||
1792 | IWL_DEBUG_ASSOC | |
1793 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
1794 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
1795 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
1796 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
1797 | } | |
1798 | ||
c79dd5b5 | 1799 | static int iwl4965_scan_initiate(struct iwl_priv *priv) |
b481de9c ZY |
1800 | { |
1801 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
1802 | IWL_ERROR("APs don't scan.\n"); | |
1803 | return 0; | |
1804 | } | |
1805 | ||
fee1247a | 1806 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
1807 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
1808 | return -EIO; | |
1809 | } | |
1810 | ||
1811 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1812 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
1813 | return -EAGAIN; | |
1814 | } | |
1815 | ||
1816 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1817 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
1818 | "Queuing.\n"); | |
1819 | return -EAGAIN; | |
1820 | } | |
1821 | ||
1822 | IWL_DEBUG_INFO("Starting scan...\n"); | |
1823 | priv->scan_bands = 2; | |
1824 | set_bit(STATUS_SCANNING, &priv->status); | |
1825 | priv->scan_start = jiffies; | |
1826 | priv->scan_pass_start = priv->scan_start; | |
1827 | ||
1828 | queue_work(priv->workqueue, &priv->request_scan); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
1832 | ||
b481de9c | 1833 | |
c79dd5b5 | 1834 | static void iwl4965_set_flags_for_phymode(struct iwl_priv *priv, |
8318d78a | 1835 | enum ieee80211_band band) |
b481de9c | 1836 | { |
8318d78a | 1837 | if (band == IEEE80211_BAND_5GHZ) { |
b481de9c ZY |
1838 | priv->staging_rxon.flags &= |
1839 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
1840 | | RXON_FLG_CCK_MSK); | |
1841 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1842 | } else { | |
508e32e1 | 1843 | /* Copied from iwl4965_post_associate() */ |
b481de9c ZY |
1844 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
1845 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1846 | else | |
1847 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1848 | ||
1849 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
1850 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1851 | ||
1852 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1853 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
1854 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
1855 | } | |
1856 | } | |
1857 | ||
1858 | /* | |
01ebd063 | 1859 | * initialize rxon structure with default values from eeprom |
b481de9c | 1860 | */ |
c79dd5b5 | 1861 | static void iwl4965_connection_init_rx_config(struct iwl_priv *priv) |
b481de9c | 1862 | { |
bf85ea4f | 1863 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1864 | |
1865 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
1866 | ||
1867 | switch (priv->iw_mode) { | |
1868 | case IEEE80211_IF_TYPE_AP: | |
1869 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
1870 | break; | |
1871 | ||
1872 | case IEEE80211_IF_TYPE_STA: | |
1873 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
1874 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
1875 | break; | |
1876 | ||
1877 | case IEEE80211_IF_TYPE_IBSS: | |
1878 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
1879 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
1880 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
1881 | RXON_FILTER_ACCEPT_GRP_MSK; | |
1882 | break; | |
1883 | ||
1884 | case IEEE80211_IF_TYPE_MNTR: | |
1885 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; | |
1886 | priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
1887 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
1888 | break; | |
69dc5d9d TW |
1889 | default: |
1890 | IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode); | |
1891 | break; | |
b481de9c ZY |
1892 | } |
1893 | ||
1894 | #if 0 | |
1895 | /* TODO: Figure out when short_preamble would be set and cache from | |
1896 | * that */ | |
1897 | if (!hw_to_local(priv->hw)->short_preamble) | |
1898 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
1899 | else | |
1900 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
1901 | #endif | |
1902 | ||
8622e705 | 1903 | ch_info = iwl_get_channel_info(priv, priv->band, |
b481de9c ZY |
1904 | le16_to_cpu(priv->staging_rxon.channel)); |
1905 | ||
1906 | if (!ch_info) | |
1907 | ch_info = &priv->channel_info[0]; | |
1908 | ||
1909 | /* | |
1910 | * in some case A channels are all non IBSS | |
1911 | * in this case force B/G channel | |
1912 | */ | |
1913 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | |
1914 | !(is_channel_ibss(ch_info))) | |
1915 | ch_info = &priv->channel_info[0]; | |
1916 | ||
1917 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
8318d78a | 1918 | priv->band = ch_info->band; |
b481de9c | 1919 | |
8318d78a | 1920 | iwl4965_set_flags_for_phymode(priv, priv->band); |
b481de9c ZY |
1921 | |
1922 | priv->staging_rxon.ofdm_basic_rates = | |
1923 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
1924 | priv->staging_rxon.cck_basic_rates = | |
1925 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
1926 | ||
1927 | priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | | |
1928 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); | |
1929 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); | |
1930 | memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); | |
1931 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; | |
1932 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; | |
1933 | iwl4965_set_rxon_chain(priv); | |
1934 | } | |
1935 | ||
c79dd5b5 | 1936 | static int iwl4965_set_mode(struct iwl_priv *priv, int mode) |
b481de9c | 1937 | { |
b481de9c | 1938 | if (mode == IEEE80211_IF_TYPE_IBSS) { |
bf85ea4f | 1939 | const struct iwl_channel_info *ch_info; |
b481de9c | 1940 | |
8622e705 | 1941 | ch_info = iwl_get_channel_info(priv, |
8318d78a | 1942 | priv->band, |
b481de9c ZY |
1943 | le16_to_cpu(priv->staging_rxon.channel)); |
1944 | ||
1945 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
1946 | IWL_ERROR("channel %d not IBSS channel\n", | |
1947 | le16_to_cpu(priv->staging_rxon.channel)); | |
1948 | return -EINVAL; | |
1949 | } | |
1950 | } | |
1951 | ||
b481de9c ZY |
1952 | priv->iw_mode = mode; |
1953 | ||
bb8c093b | 1954 | iwl4965_connection_init_rx_config(priv); |
b481de9c ZY |
1955 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1956 | ||
bf85ea4f | 1957 | iwlcore_clear_stations_table(priv); |
b481de9c | 1958 | |
fde3571f | 1959 | /* dont commit rxon if rf-kill is on*/ |
fee1247a | 1960 | if (!iwl_is_ready_rf(priv)) |
fde3571f MA |
1961 | return -EAGAIN; |
1962 | ||
1963 | cancel_delayed_work(&priv->scan_check); | |
1964 | if (iwl4965_scan_cancel_timeout(priv, 100)) { | |
1965 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
1966 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
1967 | return -EAGAIN; | |
1968 | } | |
1969 | ||
bb8c093b | 1970 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
1971 | |
1972 | return 0; | |
1973 | } | |
1974 | ||
c79dd5b5 | 1975 | static void iwl4965_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
b481de9c | 1976 | struct ieee80211_tx_control *ctl, |
857485c0 | 1977 | struct iwl_cmd *cmd, |
b481de9c | 1978 | struct sk_buff *skb_frag, |
deb09c43 | 1979 | int sta_id) |
b481de9c | 1980 | { |
deb09c43 | 1981 | struct iwl4965_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
6974e363 EG |
1982 | struct iwl_wep_key *wepkey; |
1983 | int keyidx = 0; | |
1984 | ||
1985 | BUG_ON(ctl->key_idx > 3); | |
b481de9c ZY |
1986 | |
1987 | switch (keyinfo->alg) { | |
1988 | case ALG_CCMP: | |
1989 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
1990 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
8236e183 MS |
1991 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
1992 | cmd->cmd.tx.tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
b481de9c ZY |
1993 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); |
1994 | break; | |
1995 | ||
1996 | case ALG_TKIP: | |
b481de9c | 1997 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; |
2bc75089 EG |
1998 | ieee80211_get_tkip_key(keyinfo->conf, skb_frag, |
1999 | IEEE80211_TKIP_P2_KEY, cmd->cmd.tx.key); | |
2000 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); | |
b481de9c ZY |
2001 | break; |
2002 | ||
2003 | case ALG_WEP: | |
6974e363 EG |
2004 | wepkey = &priv->wep_keys[ctl->key_idx]; |
2005 | cmd->cmd.tx.sec_ctl = 0; | |
2006 | if (priv->default_wep_key) { | |
2007 | /* the WEP key was sent as static */ | |
2008 | keyidx = ctl->key_idx; | |
2009 | memcpy(&cmd->cmd.tx.key[3], wepkey->key, | |
2010 | wepkey->key_size); | |
2011 | if (wepkey->key_size == WEP_KEY_LEN_128) | |
2012 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2013 | } else { | |
0211ddda EG |
2014 | /* the WEP key was sent as dynamic */ |
2015 | keyidx = keyinfo->keyidx; | |
2016 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, | |
2017 | keyinfo->keylen); | |
2018 | if (keyinfo->keylen == WEP_KEY_LEN_128) | |
2019 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
6974e363 | 2020 | } |
b481de9c | 2021 | |
6974e363 EG |
2022 | cmd->cmd.tx.sec_ctl |= (TX_CMD_SEC_WEP | |
2023 | (keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); | |
b481de9c ZY |
2024 | |
2025 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
6974e363 | 2026 | "with key %d\n", keyidx); |
b481de9c ZY |
2027 | break; |
2028 | ||
b481de9c ZY |
2029 | default: |
2030 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2031 | break; | |
2032 | } | |
2033 | } | |
2034 | ||
2035 | /* | |
2036 | * handle build REPLY_TX command notification. | |
2037 | */ | |
c79dd5b5 | 2038 | static void iwl4965_build_tx_cmd_basic(struct iwl_priv *priv, |
857485c0 | 2039 | struct iwl_cmd *cmd, |
b481de9c ZY |
2040 | struct ieee80211_tx_control *ctrl, |
2041 | struct ieee80211_hdr *hdr, | |
2042 | int is_unicast, u8 std_id) | |
2043 | { | |
2044 | __le16 *qc; | |
2045 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2046 | __le32 tx_flags = cmd->cmd.tx.tx_flags; | |
2047 | ||
2048 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
2049 | if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { | |
2050 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
2051 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
2052 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2053 | if (ieee80211_is_probe_response(fc) && | |
2054 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
2055 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2056 | } else { | |
2057 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2058 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2059 | } | |
2060 | ||
87e4f7df TW |
2061 | if (ieee80211_is_back_request(fc)) |
2062 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
2063 | ||
2064 | ||
b481de9c ZY |
2065 | cmd->cmd.tx.sta_id = std_id; |
2066 | if (ieee80211_get_morefrag(hdr)) | |
2067 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
2068 | ||
2069 | qc = ieee80211_get_qos_ctrl(hdr); | |
2070 | if (qc) { | |
2071 | cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf); | |
2072 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
2073 | } else | |
2074 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2075 | ||
2076 | if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { | |
2077 | tx_flags |= TX_CMD_FLG_RTS_MSK; | |
2078 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
2079 | } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { | |
2080 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
2081 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2082 | } | |
2083 | ||
2084 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2085 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2086 | ||
2087 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
2088 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { | |
2089 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || | |
2090 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) | |
bc434dd2 | 2091 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2092 | else |
bc434dd2 | 2093 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2094 | } else { |
b481de9c | 2095 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; |
ab53d8af | 2096 | } |
b481de9c ZY |
2097 | |
2098 | cmd->cmd.tx.driver_txop = 0; | |
2099 | cmd->cmd.tx.tx_flags = tx_flags; | |
2100 | cmd->cmd.tx.next_frame_len = 0; | |
2101 | } | |
19758bef TW |
2102 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) |
2103 | { | |
2104 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
2105 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
2106 | priv->tx_stats[idx].cnt++; | |
2107 | priv->tx_stats[idx].bytes += len; | |
2108 | } | |
6440adb5 BC |
2109 | /** |
2110 | * iwl4965_get_sta_id - Find station's index within station table | |
2111 | * | |
2112 | * If new IBSS station, create new entry in station table | |
2113 | */ | |
c79dd5b5 | 2114 | static int iwl4965_get_sta_id(struct iwl_priv *priv, |
9fbab516 | 2115 | struct ieee80211_hdr *hdr) |
b481de9c ZY |
2116 | { |
2117 | int sta_id; | |
2118 | u16 fc = le16_to_cpu(hdr->frame_control); | |
0795af57 | 2119 | DECLARE_MAC_BUF(mac); |
b481de9c | 2120 | |
6440adb5 | 2121 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2122 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2123 | is_multicast_ether_addr(hdr->addr1)) | |
2124 | return priv->hw_setting.bcast_sta_id; | |
2125 | ||
2126 | switch (priv->iw_mode) { | |
2127 | ||
6440adb5 BC |
2128 | /* If we are a client station in a BSS network, use the special |
2129 | * AP station entry (that's the only station we communicate with) */ | |
b481de9c ZY |
2130 | case IEEE80211_IF_TYPE_STA: |
2131 | return IWL_AP_ID; | |
2132 | ||
2133 | /* If we are an AP, then find the station, or use BCAST */ | |
2134 | case IEEE80211_IF_TYPE_AP: | |
bb8c093b | 2135 | sta_id = iwl4965_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2136 | if (sta_id != IWL_INVALID_STATION) |
2137 | return sta_id; | |
2138 | return priv->hw_setting.bcast_sta_id; | |
2139 | ||
6440adb5 BC |
2140 | /* If this frame is going out to an IBSS network, find the station, |
2141 | * or create a new station table entry */ | |
b481de9c | 2142 | case IEEE80211_IF_TYPE_IBSS: |
bb8c093b | 2143 | sta_id = iwl4965_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2144 | if (sta_id != IWL_INVALID_STATION) |
2145 | return sta_id; | |
2146 | ||
6440adb5 | 2147 | /* Create new station table entry */ |
67d62035 RR |
2148 | sta_id = iwl4965_add_station_flags(priv, hdr->addr1, |
2149 | 0, CMD_ASYNC, NULL); | |
b481de9c ZY |
2150 | |
2151 | if (sta_id != IWL_INVALID_STATION) | |
2152 | return sta_id; | |
2153 | ||
0795af57 | 2154 | IWL_DEBUG_DROP("Station %s not in station map. " |
b481de9c | 2155 | "Defaulting to broadcast...\n", |
0795af57 | 2156 | print_mac(mac, hdr->addr1)); |
0a6857e7 | 2157 | iwl_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
b481de9c ZY |
2158 | return priv->hw_setting.bcast_sta_id; |
2159 | ||
2160 | default: | |
01ebd063 | 2161 | IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); |
b481de9c ZY |
2162 | return priv->hw_setting.bcast_sta_id; |
2163 | } | |
2164 | } | |
2165 | ||
2166 | /* | |
2167 | * start REPLY_TX command process | |
2168 | */ | |
c79dd5b5 | 2169 | static int iwl4965_tx_skb(struct iwl_priv *priv, |
b481de9c ZY |
2170 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) |
2171 | { | |
2172 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
bb8c093b | 2173 | struct iwl4965_tfd_frame *tfd; |
b481de9c ZY |
2174 | u32 *control_flags; |
2175 | int txq_id = ctl->queue; | |
bb8c093b CH |
2176 | struct iwl4965_tx_queue *txq = NULL; |
2177 | struct iwl4965_queue *q = NULL; | |
b481de9c ZY |
2178 | dma_addr_t phys_addr; |
2179 | dma_addr_t txcmd_phys; | |
87e4f7df | 2180 | dma_addr_t scratch_phys; |
857485c0 | 2181 | struct iwl_cmd *out_cmd = NULL; |
b481de9c ZY |
2182 | u16 len, idx, len_org; |
2183 | u8 id, hdr_len, unicast; | |
2184 | u8 sta_id; | |
2185 | u16 seq_number = 0; | |
2186 | u16 fc; | |
2187 | __le16 *qc; | |
2188 | u8 wait_write_ptr = 0; | |
2189 | unsigned long flags; | |
2190 | int rc; | |
2191 | ||
2192 | spin_lock_irqsave(&priv->lock, flags); | |
fee1247a | 2193 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
2194 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2195 | goto drop_unlock; | |
2196 | } | |
2197 | ||
32bfd35d JB |
2198 | if (!priv->vif) { |
2199 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
b481de9c ZY |
2200 | goto drop_unlock; |
2201 | } | |
2202 | ||
8318d78a | 2203 | if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2204 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2205 | goto drop_unlock; | |
2206 | } | |
2207 | ||
2208 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2209 | id = 0; | |
2210 | ||
2211 | fc = le16_to_cpu(hdr->frame_control); | |
2212 | ||
0a6857e7 | 2213 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2214 | if (ieee80211_is_auth(fc)) |
2215 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
2216 | else if (ieee80211_is_assoc_request(fc)) | |
2217 | IWL_DEBUG_TX("Sending ASSOC frame\n"); | |
2218 | else if (ieee80211_is_reassoc_request(fc)) | |
2219 | IWL_DEBUG_TX("Sending REASSOC frame\n"); | |
2220 | #endif | |
2221 | ||
7878a5a4 | 2222 | /* drop all data frame if we are not associated */ |
76f3915b | 2223 | if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) && |
3109ece1 | 2224 | (!iwl_is_associated(priv) || |
a6477249 | 2225 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) || |
76f3915b | 2226 | !priv->assoc_station_added)) { |
3109ece1 | 2227 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
2228 | goto drop_unlock; |
2229 | } | |
2230 | ||
2231 | spin_unlock_irqrestore(&priv->lock, flags); | |
2232 | ||
2233 | hdr_len = ieee80211_get_hdrlen(fc); | |
6440adb5 BC |
2234 | |
2235 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2236 | sta_id = iwl4965_get_sta_id(priv, hdr); |
b481de9c | 2237 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
2238 | DECLARE_MAC_BUF(mac); |
2239 | ||
2240 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
2241 | print_mac(mac, hdr->addr1)); | |
b481de9c ZY |
2242 | goto drop; |
2243 | } | |
2244 | ||
2245 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2246 | ||
2247 | qc = ieee80211_get_qos_ctrl(hdr); | |
2248 | if (qc) { | |
2249 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2250 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
2251 | IEEE80211_SCTL_SEQ; | |
2252 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2253 | (hdr->seq_ctrl & | |
2254 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2255 | seq_number += 0x10; | |
c8b0e6e1 | 2256 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 2257 | /* aggregation is on for this <sta,tid> */ |
fe01b477 | 2258 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
b481de9c | 2259 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
fe01b477 | 2260 | priv->stations[sta_id].tid[tid].tfds_in_queue++; |
c8b0e6e1 | 2261 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 2262 | } |
6440adb5 BC |
2263 | |
2264 | /* Descriptor for chosen Tx queue */ | |
b481de9c ZY |
2265 | txq = &priv->txq[txq_id]; |
2266 | q = &txq->q; | |
2267 | ||
2268 | spin_lock_irqsave(&priv->lock, flags); | |
2269 | ||
6440adb5 | 2270 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2271 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2272 | memset(tfd, 0, sizeof(*tfd)); |
2273 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2274 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2275 | |
6440adb5 | 2276 | /* Set up driver data for this TFD */ |
bb8c093b | 2277 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info)); |
fc4b6853 TW |
2278 | txq->txb[q->write_ptr].skb[0] = skb; |
2279 | memcpy(&(txq->txb[q->write_ptr].status.control), | |
b481de9c | 2280 | ctl, sizeof(struct ieee80211_tx_control)); |
6440adb5 BC |
2281 | |
2282 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2283 | out_cmd = &txq->cmd[idx]; |
2284 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2285 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 BC |
2286 | |
2287 | /* | |
2288 | * Set up the Tx-command (not MAC!) header. | |
2289 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2290 | * after Tx, uCode's Tx response will return this value so driver can | |
2291 | * locate the frame within the tx queue and do post-tx processing. | |
2292 | */ | |
b481de9c ZY |
2293 | out_cmd->hdr.cmd = REPLY_TX; |
2294 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2295 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
2296 | |
2297 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2298 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2299 | ||
6440adb5 BC |
2300 | /* |
2301 | * Use the first empty entry in this queue's command buffer array | |
2302 | * to contain the Tx command and MAC header concatenated together | |
2303 | * (payload data will be in another buffer). | |
2304 | * Size of this varies, due to varying MAC header length. | |
2305 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2306 | * of the MAC header (device reads on dword boundaries). | |
2307 | * We'll tell device about this padding later. | |
2308 | */ | |
b481de9c | 2309 | len = priv->hw_setting.tx_cmd_len + |
857485c0 | 2310 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
2311 | |
2312 | len_org = len; | |
2313 | len = (len + 3) & ~3; | |
2314 | ||
2315 | if (len_org != len) | |
2316 | len_org = 1; | |
2317 | else | |
2318 | len_org = 0; | |
2319 | ||
6440adb5 BC |
2320 | /* Physical address of this Tx command's header (not MAC header!), |
2321 | * within command buffer array. */ | |
857485c0 TW |
2322 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + |
2323 | offsetof(struct iwl_cmd, hdr); | |
b481de9c | 2324 | |
6440adb5 BC |
2325 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2326 | * first entry */ | |
bb8c093b | 2327 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c ZY |
2328 | |
2329 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) | |
deb09c43 | 2330 | iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, sta_id); |
b481de9c | 2331 | |
6440adb5 BC |
2332 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2333 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2334 | len = skb->len - hdr_len; |
2335 | if (len) { | |
2336 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2337 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2338 | iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2339 | } |
2340 | ||
6440adb5 | 2341 | /* Tell 4965 about any 2-byte padding after MAC header */ |
b481de9c ZY |
2342 | if (len_org) |
2343 | out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
2344 | ||
6440adb5 | 2345 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2346 | len = (u16)skb->len; |
2347 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2348 | ||
2349 | /* TODO need this for burst mode later on */ | |
bb8c093b | 2350 | iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id); |
b481de9c ZY |
2351 | |
2352 | /* set is_hcca to 0; it probably will never be implemented */ | |
bb8c093b | 2353 | iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0); |
b481de9c | 2354 | |
19758bef TW |
2355 | iwl_update_tx_stats(priv, fc, len); |
2356 | ||
857485c0 | 2357 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
87e4f7df TW |
2358 | offsetof(struct iwl4965_tx_cmd, scratch); |
2359 | out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
2360 | out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); | |
2361 | ||
b481de9c ZY |
2362 | if (!ieee80211_get_morefrag(hdr)) { |
2363 | txq->need_update = 1; | |
2364 | if (qc) { | |
2365 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2366 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
2367 | } | |
2368 | } else { | |
2369 | wait_write_ptr = 1; | |
2370 | txq->need_update = 0; | |
2371 | } | |
2372 | ||
0a6857e7 | 2373 | iwl_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2374 | sizeof(out_cmd->cmd.tx)); |
2375 | ||
0a6857e7 | 2376 | iwl_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
b481de9c ZY |
2377 | ieee80211_get_hdrlen(fc)); |
2378 | ||
6440adb5 | 2379 | /* Set up entry for this TFD in Tx byte-count array */ |
e2a722eb | 2380 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); |
b481de9c | 2381 | |
6440adb5 | 2382 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2383 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 2384 | rc = iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2385 | spin_unlock_irqrestore(&priv->lock, flags); |
2386 | ||
2387 | if (rc) | |
2388 | return rc; | |
2389 | ||
bb8c093b | 2390 | if ((iwl4965_queue_space(q) < q->high_mark) |
b481de9c ZY |
2391 | && priv->mac80211_registered) { |
2392 | if (wait_write_ptr) { | |
2393 | spin_lock_irqsave(&priv->lock, flags); | |
2394 | txq->need_update = 1; | |
bb8c093b | 2395 | iwl4965_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2396 | spin_unlock_irqrestore(&priv->lock, flags); |
2397 | } | |
2398 | ||
2399 | ieee80211_stop_queue(priv->hw, ctl->queue); | |
2400 | } | |
2401 | ||
2402 | return 0; | |
2403 | ||
2404 | drop_unlock: | |
2405 | spin_unlock_irqrestore(&priv->lock, flags); | |
2406 | drop: | |
2407 | return -1; | |
2408 | } | |
2409 | ||
c79dd5b5 | 2410 | static void iwl4965_set_rate(struct iwl_priv *priv) |
b481de9c | 2411 | { |
8318d78a | 2412 | const struct ieee80211_supported_band *hw = NULL; |
b481de9c ZY |
2413 | struct ieee80211_rate *rate; |
2414 | int i; | |
2415 | ||
8318d78a | 2416 | hw = iwl4965_get_hw_mode(priv, priv->band); |
c4ba9621 SA |
2417 | if (!hw) { |
2418 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); | |
2419 | return; | |
2420 | } | |
b481de9c ZY |
2421 | |
2422 | priv->active_rate = 0; | |
2423 | priv->active_rate_basic = 0; | |
2424 | ||
8318d78a JB |
2425 | for (i = 0; i < hw->n_bitrates; i++) { |
2426 | rate = &(hw->bitrates[i]); | |
2427 | if (rate->hw_value < IWL_RATE_COUNT) | |
2428 | priv->active_rate |= (1 << rate->hw_value); | |
b481de9c ZY |
2429 | } |
2430 | ||
2431 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2432 | priv->active_rate, priv->active_rate_basic); | |
2433 | ||
2434 | /* | |
2435 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2436 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2437 | * OFDM | |
2438 | */ | |
2439 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
2440 | priv->staging_rxon.cck_basic_rates = | |
2441 | ((priv->active_rate_basic & | |
2442 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2443 | else | |
2444 | priv->staging_rxon.cck_basic_rates = | |
2445 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2446 | ||
2447 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
2448 | priv->staging_rxon.ofdm_basic_rates = | |
2449 | ((priv->active_rate_basic & | |
2450 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2451 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2452 | else | |
2453 | priv->staging_rxon.ofdm_basic_rates = | |
2454 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2455 | } | |
2456 | ||
ad97edd2 | 2457 | void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio) |
b481de9c ZY |
2458 | { |
2459 | unsigned long flags; | |
2460 | ||
2461 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2462 | return; | |
2463 | ||
2464 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2465 | disable_radio ? "OFF" : "ON"); | |
2466 | ||
2467 | if (disable_radio) { | |
bb8c093b | 2468 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
2469 | /* FIXME: This is a workaround for AP */ |
2470 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
2471 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 2472 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2473 | CSR_UCODE_SW_BIT_RFKILL); |
2474 | spin_unlock_irqrestore(&priv->lock, flags); | |
ad97edd2 MA |
2475 | /* call the host command only if no hw rf-kill set */ |
2476 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2477 | iwl4965_send_card_state(priv, | |
2478 | CARD_STATE_CMD_DISABLE, | |
2479 | 0); | |
b481de9c | 2480 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
ad97edd2 MA |
2481 | |
2482 | /* make sure mac80211 stop sending Tx frame */ | |
2483 | if (priv->mac80211_registered) | |
2484 | ieee80211_stop_queues(priv->hw); | |
b481de9c ZY |
2485 | } |
2486 | return; | |
2487 | } | |
2488 | ||
2489 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 2490 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2491 | |
2492 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2493 | spin_unlock_irqrestore(&priv->lock, flags); | |
2494 | ||
2495 | /* wake up ucode */ | |
2496 | msleep(10); | |
2497 | ||
2498 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
2499 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
2500 | if (!iwl_grab_nic_access(priv)) | |
2501 | iwl_release_nic_access(priv); | |
b481de9c ZY |
2502 | spin_unlock_irqrestore(&priv->lock, flags); |
2503 | ||
2504 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2505 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2506 | "disabled by HW switch\n"); | |
2507 | return; | |
2508 | } | |
2509 | ||
2510 | queue_work(priv->workqueue, &priv->restart); | |
2511 | return; | |
2512 | } | |
2513 | ||
c79dd5b5 | 2514 | void iwl4965_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2515 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2516 | { | |
2517 | u16 fc = | |
2518 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2519 | ||
2520 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
2521 | return; | |
2522 | ||
2523 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2524 | return; | |
2525 | ||
2526 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2527 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2528 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
17e476b8 EG |
2529 | /* The uCode has got a bad phase 1 Key, pushes the packet. |
2530 | * Decryption will be done in SW. */ | |
2531 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2532 | RX_RES_STATUS_BAD_KEY_TTAK) | |
2533 | break; | |
2534 | ||
b481de9c ZY |
2535 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == |
2536 | RX_RES_STATUS_BAD_ICV_MIC) | |
2537 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2538 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2539 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2540 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2541 | RX_RES_STATUS_DECRYPT_OK) { | |
2542 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2543 | stats->flag |= RX_FLAG_DECRYPTED; | |
2544 | } | |
2545 | break; | |
2546 | ||
2547 | default: | |
2548 | break; | |
2549 | } | |
2550 | } | |
2551 | ||
b481de9c ZY |
2552 | |
2553 | #define IWL_PACKET_RETRY_TIME HZ | |
2554 | ||
c79dd5b5 | 2555 | int iwl4965_is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2556 | { |
2557 | u16 sc = le16_to_cpu(header->seq_ctrl); | |
2558 | u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4; | |
2559 | u16 frag = sc & IEEE80211_SCTL_FRAG; | |
2560 | u16 *last_seq, *last_frag; | |
2561 | unsigned long *last_time; | |
2562 | ||
2563 | switch (priv->iw_mode) { | |
2564 | case IEEE80211_IF_TYPE_IBSS:{ | |
2565 | struct list_head *p; | |
bb8c093b | 2566 | struct iwl4965_ibss_seq *entry = NULL; |
b481de9c ZY |
2567 | u8 *mac = header->addr2; |
2568 | int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1); | |
2569 | ||
2570 | __list_for_each(p, &priv->ibss_mac_hash[index]) { | |
bb8c093b | 2571 | entry = list_entry(p, struct iwl4965_ibss_seq, list); |
b481de9c ZY |
2572 | if (!compare_ether_addr(entry->mac, mac)) |
2573 | break; | |
2574 | } | |
2575 | if (p == &priv->ibss_mac_hash[index]) { | |
2576 | entry = kzalloc(sizeof(*entry), GFP_ATOMIC); | |
2577 | if (!entry) { | |
bc434dd2 | 2578 | IWL_ERROR("Cannot malloc new mac entry\n"); |
b481de9c ZY |
2579 | return 0; |
2580 | } | |
2581 | memcpy(entry->mac, mac, ETH_ALEN); | |
2582 | entry->seq_num = seq; | |
2583 | entry->frag_num = frag; | |
2584 | entry->packet_time = jiffies; | |
bc434dd2 | 2585 | list_add(&entry->list, &priv->ibss_mac_hash[index]); |
b481de9c ZY |
2586 | return 0; |
2587 | } | |
2588 | last_seq = &entry->seq_num; | |
2589 | last_frag = &entry->frag_num; | |
2590 | last_time = &entry->packet_time; | |
2591 | break; | |
2592 | } | |
2593 | case IEEE80211_IF_TYPE_STA: | |
2594 | last_seq = &priv->last_seq_num; | |
2595 | last_frag = &priv->last_frag_num; | |
2596 | last_time = &priv->last_packet_time; | |
2597 | break; | |
2598 | default: | |
2599 | return 0; | |
2600 | } | |
2601 | if ((*last_seq == seq) && | |
2602 | time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) { | |
2603 | if (*last_frag == frag) | |
2604 | goto drop; | |
2605 | if (*last_frag + 1 != frag) | |
2606 | /* out-of-order fragment */ | |
2607 | goto drop; | |
2608 | } else | |
2609 | *last_seq = seq; | |
2610 | ||
2611 | *last_frag = frag; | |
2612 | *last_time = jiffies; | |
2613 | return 0; | |
2614 | ||
2615 | drop: | |
2616 | return 1; | |
2617 | } | |
2618 | ||
c8b0e6e1 | 2619 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2620 | |
2621 | #include "iwl-spectrum.h" | |
2622 | ||
2623 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2624 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2625 | #define TIME_UNIT 1024 | |
2626 | ||
2627 | /* | |
2628 | * extended beacon time format | |
2629 | * time in usec will be changed into a 32-bit value in 8:24 format | |
2630 | * the high 1 byte is the beacon counts | |
2631 | * the lower 3 bytes is the time in usec within one beacon interval | |
2632 | */ | |
2633 | ||
bb8c093b | 2634 | static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
2635 | { |
2636 | u32 quot; | |
2637 | u32 rem; | |
2638 | u32 interval = beacon_interval * 1024; | |
2639 | ||
2640 | if (!interval || !usec) | |
2641 | return 0; | |
2642 | ||
2643 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
2644 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
2645 | ||
2646 | return (quot << 24) + rem; | |
2647 | } | |
2648 | ||
2649 | /* base is usually what we get from ucode with each received frame, | |
2650 | * the same as HW timer counter counting down | |
2651 | */ | |
2652 | ||
bb8c093b | 2653 | static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
2654 | { |
2655 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
2656 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
2657 | u32 interval = beacon_interval * TIME_UNIT; | |
2658 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
2659 | (addon & BEACON_TIME_MASK_HIGH); | |
2660 | ||
2661 | if (base_low > addon_low) | |
2662 | res += base_low - addon_low; | |
2663 | else if (base_low < addon_low) { | |
2664 | res += interval + base_low - addon_low; | |
2665 | res += (1 << 24); | |
2666 | } else | |
2667 | res += (1 << 24); | |
2668 | ||
2669 | return cpu_to_le32(res); | |
2670 | } | |
2671 | ||
c79dd5b5 | 2672 | static int iwl4965_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
2673 | struct ieee80211_measurement_params *params, |
2674 | u8 type) | |
2675 | { | |
bb8c093b CH |
2676 | struct iwl4965_spectrum_cmd spectrum; |
2677 | struct iwl4965_rx_packet *res; | |
857485c0 | 2678 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
2679 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
2680 | .data = (void *)&spectrum, | |
2681 | .meta.flags = CMD_WANT_SKB, | |
2682 | }; | |
2683 | u32 add_time = le64_to_cpu(params->start_time); | |
2684 | int rc; | |
2685 | int spectrum_resp_status; | |
2686 | int duration = le16_to_cpu(params->duration); | |
2687 | ||
3109ece1 | 2688 | if (iwl_is_associated(priv)) |
b481de9c | 2689 | add_time = |
bb8c093b | 2690 | iwl4965_usecs_to_beacons( |
b481de9c ZY |
2691 | le64_to_cpu(params->start_time) - priv->last_tsf, |
2692 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2693 | ||
2694 | memset(&spectrum, 0, sizeof(spectrum)); | |
2695 | ||
2696 | spectrum.channel_count = cpu_to_le16(1); | |
2697 | spectrum.flags = | |
2698 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
2699 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
2700 | cmd.len = sizeof(spectrum); | |
2701 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
2702 | ||
3109ece1 | 2703 | if (iwl_is_associated(priv)) |
b481de9c | 2704 | spectrum.start_time = |
bb8c093b | 2705 | iwl4965_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
2706 | add_time, |
2707 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2708 | else | |
2709 | spectrum.start_time = 0; | |
2710 | ||
2711 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
2712 | spectrum.channels[0].channel = params->channel; | |
2713 | spectrum.channels[0].type = type; | |
2714 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
2715 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
2716 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
2717 | ||
857485c0 | 2718 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2719 | if (rc) |
2720 | return rc; | |
2721 | ||
bb8c093b | 2722 | res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
2723 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
2724 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
2725 | rc = -EIO; | |
2726 | } | |
2727 | ||
2728 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
2729 | switch (spectrum_resp_status) { | |
2730 | case 0: /* Command will be handled */ | |
2731 | if (res->u.spectrum.id != 0xff) { | |
2732 | IWL_DEBUG_INFO | |
2733 | ("Replaced existing measurement: %d\n", | |
2734 | res->u.spectrum.id); | |
2735 | priv->measurement_status &= ~MEASUREMENT_READY; | |
2736 | } | |
2737 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
2738 | rc = 0; | |
2739 | break; | |
2740 | ||
2741 | case 1: /* Command will not be handled */ | |
2742 | rc = -EAGAIN; | |
2743 | break; | |
2744 | } | |
2745 | ||
2746 | dev_kfree_skb_any(cmd.meta.u.skb); | |
2747 | ||
2748 | return rc; | |
2749 | } | |
2750 | #endif | |
2751 | ||
c79dd5b5 | 2752 | static void iwl4965_txstatus_to_ieee(struct iwl_priv *priv, |
bb8c093b | 2753 | struct iwl4965_tx_info *tx_sta) |
b481de9c ZY |
2754 | { |
2755 | ||
2756 | tx_sta->status.ack_signal = 0; | |
2757 | tx_sta->status.excessive_retries = 0; | |
2758 | tx_sta->status.queue_length = 0; | |
2759 | tx_sta->status.queue_number = 0; | |
2760 | ||
2761 | if (in_interrupt()) | |
2762 | ieee80211_tx_status_irqsafe(priv->hw, | |
2763 | tx_sta->skb[0], &(tx_sta->status)); | |
2764 | else | |
2765 | ieee80211_tx_status(priv->hw, | |
2766 | tx_sta->skb[0], &(tx_sta->status)); | |
2767 | ||
2768 | tx_sta->skb[0] = NULL; | |
2769 | } | |
2770 | ||
2771 | /** | |
6440adb5 | 2772 | * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd |
b481de9c | 2773 | * |
6440adb5 BC |
2774 | * When FW advances 'R' index, all entries between old and new 'R' index |
2775 | * need to be reclaimed. As result, some free space forms. If there is | |
2776 | * enough free space (> low mark), wake the stack that feeds us. | |
b481de9c | 2777 | */ |
c79dd5b5 | 2778 | int iwl4965_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
b481de9c | 2779 | { |
bb8c093b CH |
2780 | struct iwl4965_tx_queue *txq = &priv->txq[txq_id]; |
2781 | struct iwl4965_queue *q = &txq->q; | |
b481de9c ZY |
2782 | int nfreed = 0; |
2783 | ||
2784 | if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) { | |
2785 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
2786 | "is out of range [0-%d] %d %d.\n", txq_id, | |
fc4b6853 | 2787 | index, q->n_bd, q->write_ptr, q->read_ptr); |
b481de9c ZY |
2788 | return 0; |
2789 | } | |
2790 | ||
c54b679d | 2791 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
fc4b6853 | 2792 | q->read_ptr != index; |
c54b679d | 2793 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
b481de9c | 2794 | if (txq_id != IWL_CMD_QUEUE_NUM) { |
bb8c093b | 2795 | iwl4965_txstatus_to_ieee(priv, |
fc4b6853 | 2796 | &(txq->txb[txq->q.read_ptr])); |
bb8c093b | 2797 | iwl4965_hw_txq_free_tfd(priv, txq); |
b481de9c ZY |
2798 | } else if (nfreed > 1) { |
2799 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
fc4b6853 | 2800 | q->write_ptr, q->read_ptr); |
b481de9c ZY |
2801 | queue_work(priv->workqueue, &priv->restart); |
2802 | } | |
2803 | nfreed++; | |
2804 | } | |
2805 | ||
fe01b477 | 2806 | /* if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) && |
b481de9c ZY |
2807 | (txq_id != IWL_CMD_QUEUE_NUM) && |
2808 | priv->mac80211_registered) | |
fe01b477 | 2809 | ieee80211_wake_queue(priv->hw, txq_id); */ |
b481de9c ZY |
2810 | |
2811 | ||
2812 | return nfreed; | |
2813 | } | |
2814 | ||
bb8c093b | 2815 | static int iwl4965_is_tx_success(u32 status) |
b481de9c ZY |
2816 | { |
2817 | status &= TX_STATUS_MSK; | |
2818 | return (status == TX_STATUS_SUCCESS) | |
2819 | || (status == TX_STATUS_DIRECT_DONE); | |
2820 | } | |
2821 | ||
2822 | /****************************************************************************** | |
2823 | * | |
2824 | * Generic RX handler implementations | |
2825 | * | |
2826 | ******************************************************************************/ | |
c8b0e6e1 | 2827 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 2828 | |
c79dd5b5 | 2829 | static inline int iwl4965_get_ra_sta_id(struct iwl_priv *priv, |
b481de9c ZY |
2830 | struct ieee80211_hdr *hdr) |
2831 | { | |
2832 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) | |
2833 | return IWL_AP_ID; | |
2834 | else { | |
2835 | u8 *da = ieee80211_get_DA(hdr); | |
bb8c093b | 2836 | return iwl4965_hw_find_station(priv, da); |
b481de9c ZY |
2837 | } |
2838 | } | |
2839 | ||
bb8c093b | 2840 | static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr( |
c79dd5b5 | 2841 | struct iwl_priv *priv, int txq_id, int idx) |
b481de9c ZY |
2842 | { |
2843 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
2844 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
2845 | txb[idx].skb[0]->data; | |
2846 | return NULL; | |
2847 | } | |
2848 | ||
bb8c093b | 2849 | static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp) |
b481de9c ZY |
2850 | { |
2851 | __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status + | |
2852 | tx_resp->frame_count); | |
2853 | return le32_to_cpu(*scd_ssn) & MAX_SN; | |
2854 | ||
2855 | } | |
6440adb5 BC |
2856 | |
2857 | /** | |
2858 | * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue | |
2859 | */ | |
c79dd5b5 | 2860 | static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv, |
bb8c093b | 2861 | struct iwl4965_ht_agg *agg, |
fe01b477 | 2862 | struct iwl4965_tx_resp_agg *tx_resp, |
b481de9c ZY |
2863 | u16 start_idx) |
2864 | { | |
fe01b477 RR |
2865 | u16 status; |
2866 | struct agg_tx_status *frame_status = &tx_resp->status; | |
b481de9c ZY |
2867 | struct ieee80211_tx_status *tx_status = NULL; |
2868 | struct ieee80211_hdr *hdr = NULL; | |
2869 | int i, sh; | |
2870 | int txq_id, idx; | |
2871 | u16 seq; | |
2872 | ||
2873 | if (agg->wait_for_ba) | |
6440adb5 | 2874 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); |
b481de9c ZY |
2875 | |
2876 | agg->frame_count = tx_resp->frame_count; | |
2877 | agg->start_idx = start_idx; | |
2878 | agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
fe01b477 | 2879 | agg->bitmap = 0; |
b481de9c | 2880 | |
6440adb5 | 2881 | /* # frames attempted by Tx command */ |
b481de9c | 2882 | if (agg->frame_count == 1) { |
6440adb5 | 2883 | /* Only one frame was attempted; no block-ack will arrive */ |
fe01b477 RR |
2884 | status = le16_to_cpu(frame_status[0].status); |
2885 | seq = le16_to_cpu(frame_status[0].sequence); | |
2886 | idx = SEQ_TO_INDEX(seq); | |
2887 | txq_id = SEQ_TO_QUEUE(seq); | |
b481de9c | 2888 | |
b481de9c | 2889 | /* FIXME: code repetition */ |
fe01b477 RR |
2890 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", |
2891 | agg->frame_count, agg->start_idx, idx); | |
b481de9c | 2892 | |
fe01b477 | 2893 | tx_status = &(priv->txq[txq_id].txb[idx].status); |
b481de9c ZY |
2894 | tx_status->retry_count = tx_resp->failure_frame; |
2895 | tx_status->queue_number = status & 0xff; | |
fe01b477 RR |
2896 | tx_status->queue_length = tx_resp->failure_rts; |
2897 | tx_status->control.flags &= ~IEEE80211_TXCTL_AMPDU; | |
bb8c093b | 2898 | tx_status->flags = iwl4965_is_tx_success(status)? |
b481de9c | 2899 | IEEE80211_TX_STATUS_ACK : 0; |
4c424e4c RR |
2900 | iwl4965_hwrate_to_tx_control(priv, |
2901 | le32_to_cpu(tx_resp->rate_n_flags), | |
2902 | &tx_status->control); | |
b481de9c ZY |
2903 | /* FIXME: code repetition end */ |
2904 | ||
2905 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
2906 | status & 0xff, tx_resp->failure_frame); | |
2907 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", | |
bb8c093b | 2908 | iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags)); |
b481de9c ZY |
2909 | |
2910 | agg->wait_for_ba = 0; | |
2911 | } else { | |
6440adb5 | 2912 | /* Two or more frames were attempted; expect block-ack */ |
b481de9c ZY |
2913 | u64 bitmap = 0; |
2914 | int start = agg->start_idx; | |
2915 | ||
6440adb5 | 2916 | /* Construct bit-map of pending frames within Tx window */ |
b481de9c ZY |
2917 | for (i = 0; i < agg->frame_count; i++) { |
2918 | u16 sc; | |
fe01b477 RR |
2919 | status = le16_to_cpu(frame_status[i].status); |
2920 | seq = le16_to_cpu(frame_status[i].sequence); | |
b481de9c ZY |
2921 | idx = SEQ_TO_INDEX(seq); |
2922 | txq_id = SEQ_TO_QUEUE(seq); | |
2923 | ||
2924 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
2925 | AGG_TX_STATE_ABORT_MSK)) | |
2926 | continue; | |
2927 | ||
2928 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
2929 | agg->frame_count, txq_id, idx); | |
2930 | ||
bb8c093b | 2931 | hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx); |
b481de9c ZY |
2932 | |
2933 | sc = le16_to_cpu(hdr->seq_ctrl); | |
2934 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
2935 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
2936 | " idx=%d, seq_idx=%d, seq=%d\n", | |
2937 | idx, SEQ_TO_SN(sc), | |
2938 | hdr->seq_ctrl); | |
2939 | return -1; | |
2940 | } | |
2941 | ||
2942 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
2943 | i, idx, SEQ_TO_SN(sc)); | |
2944 | ||
2945 | sh = idx - start; | |
2946 | if (sh > 64) { | |
2947 | sh = (start - idx) + 0xff; | |
2948 | bitmap = bitmap << sh; | |
2949 | sh = 0; | |
2950 | start = idx; | |
2951 | } else if (sh < -64) | |
2952 | sh = 0xff - (start - idx); | |
2953 | else if (sh < 0) { | |
2954 | sh = start - idx; | |
2955 | start = idx; | |
2956 | bitmap = bitmap << sh; | |
2957 | sh = 0; | |
2958 | } | |
2959 | bitmap |= (1 << sh); | |
2960 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n", | |
2961 | start, (u32)(bitmap & 0xFFFFFFFF)); | |
2962 | } | |
2963 | ||
fe01b477 | 2964 | agg->bitmap = bitmap; |
b481de9c ZY |
2965 | agg->start_idx = start; |
2966 | agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
fe01b477 | 2967 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
b481de9c | 2968 | agg->frame_count, agg->start_idx, |
06501d29 | 2969 | (unsigned long long)agg->bitmap); |
b481de9c ZY |
2970 | |
2971 | if (bitmap) | |
2972 | agg->wait_for_ba = 1; | |
2973 | } | |
2974 | return 0; | |
2975 | } | |
2976 | #endif | |
b481de9c | 2977 | |
6440adb5 BC |
2978 | /** |
2979 | * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response | |
2980 | */ | |
c79dd5b5 | 2981 | static void iwl4965_rx_reply_tx(struct iwl_priv *priv, |
bb8c093b | 2982 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 2983 | { |
bb8c093b | 2984 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2985 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
2986 | int txq_id = SEQ_TO_QUEUE(sequence); | |
2987 | int index = SEQ_TO_INDEX(sequence); | |
bb8c093b | 2988 | struct iwl4965_tx_queue *txq = &priv->txq[txq_id]; |
b481de9c | 2989 | struct ieee80211_tx_status *tx_status; |
bb8c093b | 2990 | struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
b481de9c | 2991 | u32 status = le32_to_cpu(tx_resp->status); |
c8b0e6e1 | 2992 | #ifdef CONFIG_IWL4965_HT |
fe01b477 RR |
2993 | int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; |
2994 | struct ieee80211_hdr *hdr; | |
2995 | __le16 *qc; | |
b481de9c ZY |
2996 | #endif |
2997 | ||
2998 | if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) { | |
2999 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
3000 | "is out of range [0-%d] %d %d\n", txq_id, | |
fc4b6853 TW |
3001 | index, txq->q.n_bd, txq->q.write_ptr, |
3002 | txq->q.read_ptr); | |
b481de9c ZY |
3003 | return; |
3004 | } | |
3005 | ||
c8b0e6e1 | 3006 | #ifdef CONFIG_IWL4965_HT |
fe01b477 RR |
3007 | hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, index); |
3008 | qc = ieee80211_get_qos_ctrl(hdr); | |
3009 | ||
3010 | if (qc) | |
3011 | tid = le16_to_cpu(*qc) & 0xf; | |
3012 | ||
3013 | sta_id = iwl4965_get_ra_sta_id(priv, hdr); | |
3014 | if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { | |
3015 | IWL_ERROR("Station not known\n"); | |
3016 | return; | |
3017 | } | |
3018 | ||
b481de9c | 3019 | if (txq->sched_retry) { |
bb8c093b | 3020 | const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp); |
bb8c093b | 3021 | struct iwl4965_ht_agg *agg = NULL; |
b481de9c | 3022 | |
fe01b477 | 3023 | if (!qc) |
b481de9c | 3024 | return; |
b481de9c ZY |
3025 | |
3026 | agg = &priv->stations[sta_id].tid[tid].agg; | |
3027 | ||
fe01b477 RR |
3028 | iwl4965_tx_status_reply_tx(priv, agg, |
3029 | (struct iwl4965_tx_resp_agg *)tx_resp, index); | |
b481de9c ZY |
3030 | |
3031 | if ((tx_resp->frame_count == 1) && | |
bb8c093b | 3032 | !iwl4965_is_tx_success(status)) { |
b481de9c ZY |
3033 | /* TODO: send BAR */ |
3034 | } | |
3035 | ||
fe01b477 RR |
3036 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { |
3037 | int freed; | |
c54b679d | 3038 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
b481de9c ZY |
3039 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " |
3040 | "%d index %d\n", scd_ssn , index); | |
fe01b477 RR |
3041 | freed = iwl4965_tx_queue_reclaim(priv, txq_id, index); |
3042 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
3043 | ||
3044 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
3045 | txq_id >= 0 && priv->mac80211_registered && | |
3046 | agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) | |
3047 | ieee80211_wake_queue(priv->hw, txq_id); | |
3048 | ||
3049 | iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id); | |
b481de9c ZY |
3050 | } |
3051 | } else { | |
c8b0e6e1 | 3052 | #endif /* CONFIG_IWL4965_HT */ |
fc4b6853 | 3053 | tx_status = &(txq->txb[txq->q.read_ptr].status); |
b481de9c ZY |
3054 | |
3055 | tx_status->retry_count = tx_resp->failure_frame; | |
3056 | tx_status->queue_number = status; | |
3057 | tx_status->queue_length = tx_resp->bt_kill_count; | |
3058 | tx_status->queue_length |= tx_resp->failure_rts; | |
b481de9c | 3059 | tx_status->flags = |
bb8c093b | 3060 | iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0; |
4c424e4c RR |
3061 | iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags), |
3062 | &tx_status->control); | |
b481de9c | 3063 | |
b481de9c | 3064 | IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x " |
bb8c093b | 3065 | "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status), |
b481de9c ZY |
3066 | status, le32_to_cpu(tx_resp->rate_n_flags), |
3067 | tx_resp->failure_frame); | |
3068 | ||
3069 | IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); | |
fe01b477 RR |
3070 | if (index != -1) { |
3071 | int freed = iwl4965_tx_queue_reclaim(priv, txq_id, index); | |
3072 | #ifdef CONFIG_IWL4965_HT | |
3073 | if (tid != MAX_TID_COUNT) | |
3074 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
3075 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
3076 | (txq_id >= 0) && | |
3077 | priv->mac80211_registered) | |
3078 | ieee80211_wake_queue(priv->hw, txq_id); | |
3079 | if (tid != MAX_TID_COUNT) | |
3080 | iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id); | |
3081 | #endif | |
3082 | } | |
c8b0e6e1 | 3083 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 3084 | } |
c8b0e6e1 | 3085 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
3086 | |
3087 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) | |
3088 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
3089 | } | |
3090 | ||
3091 | ||
c79dd5b5 | 3092 | static void iwl4965_rx_reply_alive(struct iwl_priv *priv, |
bb8c093b | 3093 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3094 | { |
bb8c093b CH |
3095 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3096 | struct iwl4965_alive_resp *palive; | |
b481de9c ZY |
3097 | struct delayed_work *pwork; |
3098 | ||
3099 | palive = &pkt->u.alive_frame; | |
3100 | ||
3101 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
3102 | "0x%01X 0x%01X\n", | |
3103 | palive->is_valid, palive->ver_type, | |
3104 | palive->ver_subtype); | |
3105 | ||
3106 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
3107 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3108 | memcpy(&priv->card_alive_init, | |
3109 | &pkt->u.alive_frame, | |
bb8c093b | 3110 | sizeof(struct iwl4965_init_alive_resp)); |
b481de9c ZY |
3111 | pwork = &priv->init_alive_start; |
3112 | } else { | |
3113 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
3114 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
bb8c093b | 3115 | sizeof(struct iwl4965_alive_resp)); |
b481de9c ZY |
3116 | pwork = &priv->alive_start; |
3117 | } | |
3118 | ||
3119 | /* We delay the ALIVE response by 5ms to | |
3120 | * give the HW RF Kill time to activate... */ | |
3121 | if (palive->is_valid == UCODE_VALID_OK) | |
3122 | queue_delayed_work(priv->workqueue, pwork, | |
3123 | msecs_to_jiffies(5)); | |
3124 | else | |
3125 | IWL_WARNING("uCode did not respond OK.\n"); | |
3126 | } | |
3127 | ||
c79dd5b5 | 3128 | static void iwl4965_rx_reply_add_sta(struct iwl_priv *priv, |
bb8c093b | 3129 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3130 | { |
bb8c093b | 3131 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3132 | |
3133 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
3134 | return; | |
3135 | } | |
3136 | ||
c79dd5b5 | 3137 | static void iwl4965_rx_reply_error(struct iwl_priv *priv, |
bb8c093b | 3138 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3139 | { |
bb8c093b | 3140 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3141 | |
3142 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
3143 | "seq 0x%04X ser 0x%08X\n", | |
3144 | le32_to_cpu(pkt->u.err_resp.error_type), | |
3145 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
3146 | pkt->u.err_resp.cmd_id, | |
3147 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
3148 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
3149 | } | |
3150 | ||
3151 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
3152 | ||
c79dd5b5 | 3153 | static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3154 | { |
bb8c093b CH |
3155 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3156 | struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
3157 | struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif); | |
b481de9c ZY |
3158 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
3159 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
3160 | rxon->channel = csa->channel; | |
3161 | priv->staging_rxon.channel = csa->channel; | |
3162 | } | |
3163 | ||
c79dd5b5 | 3164 | static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv, |
bb8c093b | 3165 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3166 | { |
c8b0e6e1 | 3167 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
bb8c093b CH |
3168 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3169 | struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
b481de9c ZY |
3170 | |
3171 | if (!report->state) { | |
3172 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
3173 | "Spectrum Measure Notification: Start\n"); | |
3174 | return; | |
3175 | } | |
3176 | ||
3177 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
3178 | priv->measurement_status |= MEASUREMENT_READY; | |
3179 | #endif | |
3180 | } | |
3181 | ||
c79dd5b5 | 3182 | static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv, |
bb8c093b | 3183 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3184 | { |
0a6857e7 | 3185 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3186 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3187 | struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
b481de9c ZY |
3188 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
3189 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
3190 | #endif | |
3191 | } | |
3192 | ||
c79dd5b5 | 3193 | static void iwl4965_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
bb8c093b | 3194 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3195 | { |
bb8c093b | 3196 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3197 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
3198 | "notification for %s:\n", | |
3199 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
0a6857e7 | 3200 | iwl_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
3201 | } |
3202 | ||
bb8c093b | 3203 | static void iwl4965_bg_beacon_update(struct work_struct *work) |
b481de9c | 3204 | { |
c79dd5b5 TW |
3205 | struct iwl_priv *priv = |
3206 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
3207 | struct sk_buff *beacon; |
3208 | ||
3209 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
32bfd35d | 3210 | beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); |
b481de9c ZY |
3211 | |
3212 | if (!beacon) { | |
3213 | IWL_ERROR("update beacon failed\n"); | |
3214 | return; | |
3215 | } | |
3216 | ||
3217 | mutex_lock(&priv->mutex); | |
3218 | /* new beacon skb is allocated every time; dispose previous.*/ | |
3219 | if (priv->ibss_beacon) | |
3220 | dev_kfree_skb(priv->ibss_beacon); | |
3221 | ||
3222 | priv->ibss_beacon = beacon; | |
3223 | mutex_unlock(&priv->mutex); | |
3224 | ||
bb8c093b | 3225 | iwl4965_send_beacon_cmd(priv); |
b481de9c ZY |
3226 | } |
3227 | ||
c79dd5b5 | 3228 | static void iwl4965_rx_beacon_notif(struct iwl_priv *priv, |
bb8c093b | 3229 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3230 | { |
0a6857e7 | 3231 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3232 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3233 | struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status); | |
3234 | u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); | |
b481de9c ZY |
3235 | |
3236 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3237 | "tsf %d %d rate %d\n", | |
3238 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3239 | beacon->beacon_notify_hdr.failure_frame, | |
3240 | le32_to_cpu(beacon->ibss_mgr_status), | |
3241 | le32_to_cpu(beacon->high_tsf), | |
3242 | le32_to_cpu(beacon->low_tsf), rate); | |
3243 | #endif | |
3244 | ||
3245 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && | |
3246 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) | |
3247 | queue_work(priv->workqueue, &priv->beacon_update); | |
3248 | } | |
3249 | ||
3250 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
c79dd5b5 | 3251 | static void iwl4965_rx_reply_scan(struct iwl_priv *priv, |
bb8c093b | 3252 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3253 | { |
0a6857e7 | 3254 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b CH |
3255 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3256 | struct iwl4965_scanreq_notification *notif = | |
3257 | (struct iwl4965_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3258 | |
3259 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3260 | #endif | |
3261 | } | |
3262 | ||
3263 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
c79dd5b5 | 3264 | static void iwl4965_rx_scan_start_notif(struct iwl_priv *priv, |
bb8c093b | 3265 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3266 | { |
bb8c093b CH |
3267 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3268 | struct iwl4965_scanstart_notification *notif = | |
3269 | (struct iwl4965_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3270 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3271 | IWL_DEBUG_SCAN("Scan start: " | |
3272 | "%d [802.11%s] " | |
3273 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3274 | notif->channel, | |
3275 | notif->band ? "bg" : "a", | |
3276 | notif->tsf_high, | |
3277 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3278 | } | |
3279 | ||
3280 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
c79dd5b5 | 3281 | static void iwl4965_rx_scan_results_notif(struct iwl_priv *priv, |
bb8c093b | 3282 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3283 | { |
bb8c093b CH |
3284 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3285 | struct iwl4965_scanresults_notification *notif = | |
3286 | (struct iwl4965_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3287 | |
3288 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3289 | "%d [802.11%s] " | |
3290 | "(TSF: 0x%08X:%08X) - %d " | |
3291 | "elapsed=%lu usec (%dms since last)\n", | |
3292 | notif->channel, | |
3293 | notif->band ? "bg" : "a", | |
3294 | le32_to_cpu(notif->tsf_high), | |
3295 | le32_to_cpu(notif->tsf_low), | |
3296 | le32_to_cpu(notif->statistics[0]), | |
3297 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3298 | jiffies_to_msecs(elapsed_jiffies | |
3299 | (priv->last_scan_jiffies, jiffies))); | |
3300 | ||
3301 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3302 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3303 | } |
3304 | ||
3305 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
c79dd5b5 | 3306 | static void iwl4965_rx_scan_complete_notif(struct iwl_priv *priv, |
bb8c093b | 3307 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3308 | { |
bb8c093b CH |
3309 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3310 | struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
b481de9c ZY |
3311 | |
3312 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3313 | scan_notif->scanned_channels, | |
3314 | scan_notif->tsf_low, | |
3315 | scan_notif->tsf_high, scan_notif->status); | |
3316 | ||
3317 | /* The HW is no longer scanning */ | |
3318 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3319 | ||
3320 | /* The scan completion notification came in, so kill that timer... */ | |
3321 | cancel_delayed_work(&priv->scan_check); | |
3322 | ||
3323 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
3324 | (priv->scan_bands == 2) ? "2.4" : "5.2", | |
3325 | jiffies_to_msecs(elapsed_jiffies | |
3326 | (priv->scan_pass_start, jiffies))); | |
3327 | ||
3328 | /* Remove this scanned band from the list | |
3329 | * of pending bands to scan */ | |
3330 | priv->scan_bands--; | |
3331 | ||
3332 | /* If a request to abort was given, or the scan did not succeed | |
3333 | * then we reset the scan state machine and terminate, | |
3334 | * re-queuing another scan if one has been requested */ | |
3335 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3336 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3337 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3338 | } else { | |
3339 | /* If there are more bands on this scan pass reschedule */ | |
3340 | if (priv->scan_bands > 0) | |
3341 | goto reschedule; | |
3342 | } | |
3343 | ||
3344 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3345 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3346 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3347 | ||
3348 | clear_bit(STATUS_SCANNING, &priv->status); | |
3349 | ||
3350 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3351 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3352 | ||
3353 | queue_work(priv->workqueue, &priv->scan_completed); | |
3354 | ||
3355 | return; | |
3356 | ||
3357 | reschedule: | |
3358 | priv->scan_pass_start = jiffies; | |
3359 | queue_work(priv->workqueue, &priv->request_scan); | |
3360 | } | |
3361 | ||
3362 | /* Handle notification from uCode that card's power state is changing | |
3363 | * due to software, hardware, or critical temperature RFKILL */ | |
c79dd5b5 | 3364 | static void iwl4965_rx_card_state_notif(struct iwl_priv *priv, |
bb8c093b | 3365 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3366 | { |
bb8c093b | 3367 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3368 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3369 | unsigned long status = priv->status; | |
3370 | ||
3371 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3372 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3373 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3374 | ||
3375 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3376 | RF_CARD_DISABLED)) { | |
3377 | ||
3395f6e9 | 3378 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3379 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3380 | ||
3395f6e9 TW |
3381 | if (!iwl_grab_nic_access(priv)) { |
3382 | iwl_write_direct32( | |
b481de9c ZY |
3383 | priv, HBUS_TARG_MBX_C, |
3384 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
3385 | ||
3395f6e9 | 3386 | iwl_release_nic_access(priv); |
b481de9c ZY |
3387 | } |
3388 | ||
3389 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 3390 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 3391 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3395f6e9 TW |
3392 | if (!iwl_grab_nic_access(priv)) { |
3393 | iwl_write_direct32( | |
b481de9c ZY |
3394 | priv, HBUS_TARG_MBX_C, |
3395 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
3396 | ||
3395f6e9 | 3397 | iwl_release_nic_access(priv); |
b481de9c ZY |
3398 | } |
3399 | } | |
3400 | ||
3401 | if (flags & RF_CARD_DISABLED) { | |
3395f6e9 | 3402 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c | 3403 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
3395f6e9 TW |
3404 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
3405 | if (!iwl_grab_nic_access(priv)) | |
3406 | iwl_release_nic_access(priv); | |
b481de9c ZY |
3407 | } |
3408 | } | |
3409 | ||
3410 | if (flags & HW_CARD_DISABLED) | |
3411 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3412 | else | |
3413 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3414 | ||
3415 | ||
3416 | if (flags & SW_CARD_DISABLED) | |
3417 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3418 | else | |
3419 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3420 | ||
3421 | if (!(flags & RXON_CARD_DISABLED)) | |
bb8c093b | 3422 | iwl4965_scan_cancel(priv); |
b481de9c ZY |
3423 | |
3424 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3425 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3426 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3427 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3428 | queue_work(priv->workqueue, &priv->rf_kill); | |
3429 | else | |
3430 | wake_up_interruptible(&priv->wait_command_queue); | |
3431 | } | |
3432 | ||
3433 | /** | |
bb8c093b | 3434 | * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3435 | * |
3436 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3437 | * to the host. | |
3438 | * | |
3439 | * This function chains into the hardware specific files for them to setup | |
3440 | * any hardware specific handlers as well. | |
3441 | */ | |
c79dd5b5 | 3442 | static void iwl4965_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 3443 | { |
bb8c093b CH |
3444 | priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive; |
3445 | priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta; | |
3446 | priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error; | |
3447 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa; | |
b481de9c | 3448 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3449 | iwl4965_rx_spectrum_measure_notif; |
3450 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif; | |
b481de9c | 3451 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3452 | iwl4965_rx_pm_debug_statistics_notif; |
3453 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif; | |
b481de9c | 3454 | |
9fbab516 BC |
3455 | /* |
3456 | * The same handler is used for both the REPLY to a discrete | |
3457 | * statistics request from the host as well as for the periodic | |
3458 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3459 | */ |
bb8c093b CH |
3460 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics; |
3461 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics; | |
b481de9c | 3462 | |
bb8c093b CH |
3463 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan; |
3464 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif; | |
b481de9c | 3465 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3466 | iwl4965_rx_scan_results_notif; |
b481de9c | 3467 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3468 | iwl4965_rx_scan_complete_notif; |
3469 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif; | |
3470 | priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx; | |
b481de9c | 3471 | |
9fbab516 | 3472 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3473 | iwl4965_hw_rx_handler_setup(priv); |
b481de9c ZY |
3474 | } |
3475 | ||
3476 | /** | |
bb8c093b | 3477 | * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3478 | * @rxb: Rx buffer to reclaim |
3479 | * | |
3480 | * If an Rx buffer has an async callback associated with it the callback | |
3481 | * will be executed. The attached skb (if present) will only be freed | |
3482 | * if the callback returns 1 | |
3483 | */ | |
c79dd5b5 | 3484 | static void iwl4965_tx_cmd_complete(struct iwl_priv *priv, |
bb8c093b | 3485 | struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3486 | { |
bb8c093b | 3487 | struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3488 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3489 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3490 | int index = SEQ_TO_INDEX(sequence); | |
3491 | int huge = sequence & SEQ_HUGE_FRAME; | |
3492 | int cmd_index; | |
857485c0 | 3493 | struct iwl_cmd *cmd; |
b481de9c ZY |
3494 | |
3495 | /* If a Tx command is being handled and it isn't in the actual | |
3496 | * command queue then there a command routing bug has been introduced | |
3497 | * in the queue management code. */ | |
3498 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
3499 | IWL_ERROR("Error wrong command queue %d command id 0x%X\n", | |
3500 | txq_id, pkt->hdr.cmd); | |
3501 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); | |
3502 | ||
3503 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
3504 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
3505 | ||
3506 | /* Input error checking is done when commands are added to queue. */ | |
3507 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3508 | cmd->meta.source->u.skb = rxb->skb; | |
3509 | rxb->skb = NULL; | |
3510 | } else if (cmd->meta.u.callback && | |
3511 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3512 | rxb->skb = NULL; | |
3513 | ||
bb8c093b | 3514 | iwl4965_tx_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3515 | |
3516 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3517 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3518 | wake_up_interruptible(&priv->wait_command_queue); | |
3519 | } | |
3520 | } | |
3521 | ||
3522 | /************************** RX-FUNCTIONS ****************************/ | |
3523 | /* | |
3524 | * Rx theory of operation | |
3525 | * | |
9fbab516 BC |
3526 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), |
3527 | * each of which point to Receive Buffers to be filled by 4965. These get | |
3528 | * used not only for Rx frames, but for any command response or notification | |
3529 | * from the 4965. The driver and 4965 manage the Rx buffers by means | |
3530 | * of indexes into the circular buffer. | |
b481de9c ZY |
3531 | * |
3532 | * Rx Queue Indexes | |
3533 | * The host/firmware share two index registers for managing the Rx buffers. | |
3534 | * | |
3535 | * The READ index maps to the first position that the firmware may be writing | |
3536 | * to -- the driver can read up to (but not including) this position and get | |
3537 | * good data. | |
3538 | * The READ index is managed by the firmware once the card is enabled. | |
3539 | * | |
3540 | * The WRITE index maps to the last position the driver has read from -- the | |
3541 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3542 | * | |
3543 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3544 | * WRITE = READ. | |
3545 | * | |
9fbab516 | 3546 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3547 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3548 | * | |
9fbab516 | 3549 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3550 | * and fire the RX interrupt. The driver can then query the READ index and |
3551 | * process as many packets as possible, moving the WRITE index forward as it | |
3552 | * resets the Rx queue buffers with new memory. | |
3553 | * | |
3554 | * The management in the driver is as follows: | |
3555 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3556 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3557 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3558 | * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3559 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3560 | * 'processed' and 'read' driver indexes as well) | |
3561 | * + A received packet is processed and handed to the kernel network stack, | |
3562 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3563 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3564 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3565 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3566 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3567 | * | |
3568 | * | |
3569 | * Driver sequence: | |
3570 | * | |
9fbab516 BC |
3571 | * iwl4965_rx_queue_alloc() Allocates rx_free |
3572 | * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3573 | * iwl4965_rx_queue_restock |
9fbab516 | 3574 | * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3575 | * queue, updates firmware pointers, and updates |
3576 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3577 | * are available, schedules iwl4965_rx_replenish |
b481de9c ZY |
3578 | * |
3579 | * -- enable interrupts -- | |
9fbab516 | 3580 | * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the |
b481de9c ZY |
3581 | * READ INDEX, detaching the SKB from the pool. |
3582 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3583 | * Calls iwl4965_rx_queue_restock to refill any empty |
b481de9c ZY |
3584 | * slots. |
3585 | * ... | |
3586 | * | |
3587 | */ | |
3588 | ||
3589 | /** | |
bb8c093b | 3590 | * iwl4965_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3591 | */ |
bb8c093b | 3592 | static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q) |
b481de9c ZY |
3593 | { |
3594 | int s = q->read - q->write; | |
3595 | if (s <= 0) | |
3596 | s += RX_QUEUE_SIZE; | |
3597 | /* keep some buffer to not confuse full and empty queue */ | |
3598 | s -= 2; | |
3599 | if (s < 0) | |
3600 | s = 0; | |
3601 | return s; | |
3602 | } | |
3603 | ||
3604 | /** | |
bb8c093b | 3605 | * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3606 | */ |
c79dd5b5 | 3607 | int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl4965_rx_queue *q) |
b481de9c ZY |
3608 | { |
3609 | u32 reg = 0; | |
3610 | int rc = 0; | |
3611 | unsigned long flags; | |
3612 | ||
3613 | spin_lock_irqsave(&q->lock, flags); | |
3614 | ||
3615 | if (q->need_update == 0) | |
3616 | goto exit_unlock; | |
3617 | ||
6440adb5 | 3618 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3619 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
3395f6e9 | 3620 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3621 | |
3622 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
3395f6e9 | 3623 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3624 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3625 | goto exit_unlock; | |
3626 | } | |
3627 | ||
3395f6e9 | 3628 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
3629 | if (rc) |
3630 | goto exit_unlock; | |
3631 | ||
6440adb5 | 3632 | /* Device expects a multiple of 8 */ |
3395f6e9 | 3633 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, |
b481de9c | 3634 | q->write & ~0x7); |
3395f6e9 | 3635 | iwl_release_nic_access(priv); |
6440adb5 BC |
3636 | |
3637 | /* Else device is assumed to be awake */ | |
b481de9c | 3638 | } else |
6440adb5 | 3639 | /* Device expects a multiple of 8 */ |
3395f6e9 | 3640 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3641 | |
3642 | ||
3643 | q->need_update = 0; | |
3644 | ||
3645 | exit_unlock: | |
3646 | spin_unlock_irqrestore(&q->lock, flags); | |
3647 | return rc; | |
3648 | } | |
3649 | ||
3650 | /** | |
9fbab516 | 3651 | * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3652 | */ |
c79dd5b5 | 3653 | static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
3654 | dma_addr_t dma_addr) |
3655 | { | |
3656 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
3657 | } | |
3658 | ||
3659 | ||
3660 | /** | |
bb8c093b | 3661 | * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3662 | * |
9fbab516 | 3663 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3664 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3665 | * as we can, pulling from rx_free. |
b481de9c ZY |
3666 | * |
3667 | * This moves the 'write' index forward to catch up with 'processed', and | |
3668 | * also updates the memory address in the firmware to reference the new | |
3669 | * target buffer. | |
3670 | */ | |
c79dd5b5 | 3671 | static int iwl4965_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 3672 | { |
bb8c093b | 3673 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c | 3674 | struct list_head *element; |
bb8c093b | 3675 | struct iwl4965_rx_mem_buffer *rxb; |
b481de9c ZY |
3676 | unsigned long flags; |
3677 | int write, rc; | |
3678 | ||
3679 | spin_lock_irqsave(&rxq->lock, flags); | |
3680 | write = rxq->write & ~0x7; | |
bb8c093b | 3681 | while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3682 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3683 | element = rxq->rx_free.next; |
bb8c093b | 3684 | rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list); |
b481de9c | 3685 | list_del(element); |
6440adb5 BC |
3686 | |
3687 | /* Point to Rx buffer via next RBD in circular buffer */ | |
bb8c093b | 3688 | rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr); |
b481de9c ZY |
3689 | rxq->queue[rxq->write] = rxb; |
3690 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3691 | rxq->free_count--; | |
3692 | } | |
3693 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3694 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3695 | * refill it */ | |
3696 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3697 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3698 | ||
3699 | ||
6440adb5 BC |
3700 | /* If we've added more space for the firmware to place data, tell it. |
3701 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3702 | if ((write != (rxq->write & ~0x7)) |
3703 | || (abs(rxq->write - rxq->read) > 7)) { | |
3704 | spin_lock_irqsave(&rxq->lock, flags); | |
3705 | rxq->need_update = 1; | |
3706 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3707 | rc = iwl4965_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3708 | if (rc) |
3709 | return rc; | |
3710 | } | |
3711 | ||
3712 | return 0; | |
3713 | } | |
3714 | ||
3715 | /** | |
bb8c093b | 3716 | * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3717 | * |
3718 | * When moving to rx_free an SKB is allocated for the slot. | |
3719 | * | |
bb8c093b | 3720 | * Also restock the Rx queue via iwl4965_rx_queue_restock. |
01ebd063 | 3721 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3722 | */ |
c79dd5b5 | 3723 | static void iwl4965_rx_allocate(struct iwl_priv *priv) |
b481de9c | 3724 | { |
bb8c093b | 3725 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c | 3726 | struct list_head *element; |
bb8c093b | 3727 | struct iwl4965_rx_mem_buffer *rxb; |
b481de9c ZY |
3728 | unsigned long flags; |
3729 | spin_lock_irqsave(&rxq->lock, flags); | |
3730 | while (!list_empty(&rxq->rx_used)) { | |
3731 | element = rxq->rx_used.next; | |
bb8c093b | 3732 | rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list); |
6440adb5 BC |
3733 | |
3734 | /* Alloc a new receive buffer */ | |
b481de9c | 3735 | rxb->skb = |
9ee1ba47 RR |
3736 | alloc_skb(priv->hw_setting.rx_buf_size, |
3737 | __GFP_NOWARN | GFP_ATOMIC); | |
b481de9c ZY |
3738 | if (!rxb->skb) { |
3739 | if (net_ratelimit()) | |
3740 | printk(KERN_CRIT DRV_NAME | |
3741 | ": Can not allocate SKB buffers\n"); | |
3742 | /* We don't reschedule replenish work here -- we will | |
3743 | * call the restock method and if it still needs | |
3744 | * more buffers it will schedule replenish */ | |
3745 | break; | |
3746 | } | |
3747 | priv->alloc_rxb_skb++; | |
3748 | list_del(element); | |
6440adb5 BC |
3749 | |
3750 | /* Get physical address of RB/SKB */ | |
b481de9c ZY |
3751 | rxb->dma_addr = |
3752 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
9ee1ba47 | 3753 | priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE); |
b481de9c ZY |
3754 | list_add_tail(&rxb->list, &rxq->rx_free); |
3755 | rxq->free_count++; | |
3756 | } | |
3757 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3758 | } |
3759 | ||
3760 | /* | |
3761 | * this should be called while priv->lock is locked | |
3762 | */ | |
4fd1f841 | 3763 | static void __iwl4965_rx_replenish(void *data) |
5c0eef96 | 3764 | { |
c79dd5b5 | 3765 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3766 | |
3767 | iwl4965_rx_allocate(priv); | |
3768 | iwl4965_rx_queue_restock(priv); | |
3769 | } | |
3770 | ||
3771 | ||
3772 | void iwl4965_rx_replenish(void *data) | |
3773 | { | |
c79dd5b5 | 3774 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3775 | unsigned long flags; |
3776 | ||
3777 | iwl4965_rx_allocate(priv); | |
b481de9c ZY |
3778 | |
3779 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3780 | iwl4965_rx_queue_restock(priv); |
b481de9c ZY |
3781 | spin_unlock_irqrestore(&priv->lock, flags); |
3782 | } | |
3783 | ||
3784 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3785 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3786 | * This free routine walks the list of POOL entries and if SKB is set to |
3787 | * non NULL it is unmapped and freed | |
3788 | */ | |
c79dd5b5 | 3789 | static void iwl4965_rx_queue_free(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
3790 | { |
3791 | int i; | |
3792 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3793 | if (rxq->pool[i].skb != NULL) { | |
3794 | pci_unmap_single(priv->pci_dev, | |
3795 | rxq->pool[i].dma_addr, | |
9ee1ba47 RR |
3796 | priv->hw_setting.rx_buf_size, |
3797 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3798 | dev_kfree_skb(rxq->pool[i].skb); |
3799 | } | |
3800 | } | |
3801 | ||
3802 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3803 | rxq->dma_addr); | |
3804 | rxq->bd = NULL; | |
3805 | } | |
3806 | ||
c79dd5b5 | 3807 | int iwl4965_rx_queue_alloc(struct iwl_priv *priv) |
b481de9c | 3808 | { |
bb8c093b | 3809 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3810 | struct pci_dev *dev = priv->pci_dev; |
3811 | int i; | |
3812 | ||
3813 | spin_lock_init(&rxq->lock); | |
3814 | INIT_LIST_HEAD(&rxq->rx_free); | |
3815 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 BC |
3816 | |
3817 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3818 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3819 | if (!rxq->bd) | |
3820 | return -ENOMEM; | |
6440adb5 | 3821 | |
b481de9c ZY |
3822 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3823 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3824 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3825 | |
b481de9c ZY |
3826 | /* Set us so that we have processed and used all buffers, but have |
3827 | * not restocked the Rx queue with fresh buffers */ | |
3828 | rxq->read = rxq->write = 0; | |
3829 | rxq->free_count = 0; | |
3830 | rxq->need_update = 0; | |
3831 | return 0; | |
3832 | } | |
3833 | ||
c79dd5b5 | 3834 | void iwl4965_rx_queue_reset(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
3835 | { |
3836 | unsigned long flags; | |
3837 | int i; | |
3838 | spin_lock_irqsave(&rxq->lock, flags); | |
3839 | INIT_LIST_HEAD(&rxq->rx_free); | |
3840 | INIT_LIST_HEAD(&rxq->rx_used); | |
3841 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
3842 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
3843 | /* In the reset function, these buffers may have been allocated | |
3844 | * to an SKB, so we need to unmap and free potential storage */ | |
3845 | if (rxq->pool[i].skb != NULL) { | |
3846 | pci_unmap_single(priv->pci_dev, | |
3847 | rxq->pool[i].dma_addr, | |
9ee1ba47 RR |
3848 | priv->hw_setting.rx_buf_size, |
3849 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3850 | priv->alloc_rxb_skb--; |
3851 | dev_kfree_skb(rxq->pool[i].skb); | |
3852 | rxq->pool[i].skb = NULL; | |
3853 | } | |
3854 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
3855 | } | |
3856 | ||
3857 | /* Set us so that we have processed and used all buffers, but have | |
3858 | * not restocked the Rx queue with fresh buffers */ | |
3859 | rxq->read = rxq->write = 0; | |
3860 | rxq->free_count = 0; | |
3861 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3862 | } | |
3863 | ||
3864 | /* Convert linear signal-to-noise ratio into dB */ | |
3865 | static u8 ratio2dB[100] = { | |
3866 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3867 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3868 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3869 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3870 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3871 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3872 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3873 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3874 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3875 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3876 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3877 | }; | |
3878 | ||
3879 | /* Calculates a relative dB value from a ratio of linear | |
3880 | * (i.e. not dB) signal levels. | |
3881 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 3882 | int iwl4965_calc_db_from_ratio(int sig_ratio) |
b481de9c | 3883 | { |
c899a575 AB |
3884 | /* 1000:1 or higher just report as 60 dB */ |
3885 | if (sig_ratio >= 1000) | |
b481de9c ZY |
3886 | return 60; |
3887 | ||
c899a575 | 3888 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 3889 | * add 20 dB to make up for divide by 10 */ |
c899a575 | 3890 | if (sig_ratio >= 100) |
b481de9c ZY |
3891 | return (20 + (int)ratio2dB[sig_ratio/10]); |
3892 | ||
3893 | /* We shouldn't see this */ | |
3894 | if (sig_ratio < 1) | |
3895 | return 0; | |
3896 | ||
3897 | /* Use table for ratios 1:1 - 99:1 */ | |
3898 | return (int)ratio2dB[sig_ratio]; | |
3899 | } | |
3900 | ||
3901 | #define PERFECT_RSSI (-20) /* dBm */ | |
3902 | #define WORST_RSSI (-95) /* dBm */ | |
3903 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
3904 | ||
3905 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
3906 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
3907 | * about formulas used below. */ | |
bb8c093b | 3908 | int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
3909 | { |
3910 | int sig_qual; | |
3911 | int degradation = PERFECT_RSSI - rssi_dbm; | |
3912 | ||
3913 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
3914 | * as indicator; formula is (signal dbm - noise dbm). | |
3915 | * SNR at or above 40 is a great signal (100%). | |
3916 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
3917 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
3918 | if (noise_dbm) { | |
3919 | if (rssi_dbm - noise_dbm >= 40) | |
3920 | return 100; | |
3921 | else if (rssi_dbm < noise_dbm) | |
3922 | return 0; | |
3923 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
3924 | ||
3925 | /* Else use just the signal level. | |
3926 | * This formula is a least squares fit of data points collected and | |
3927 | * compared with a reference system that had a percentage (%) display | |
3928 | * for signal quality. */ | |
3929 | } else | |
3930 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
3931 | (15 * RSSI_RANGE + 62 * degradation)) / | |
3932 | (RSSI_RANGE * RSSI_RANGE); | |
3933 | ||
3934 | if (sig_qual > 100) | |
3935 | sig_qual = 100; | |
3936 | else if (sig_qual < 1) | |
3937 | sig_qual = 0; | |
3938 | ||
3939 | return sig_qual; | |
3940 | } | |
3941 | ||
3942 | /** | |
9fbab516 | 3943 | * iwl4965_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
3944 | * |
3945 | * Uses the priv->rx_handlers callback function array to invoke | |
3946 | * the appropriate handlers, including command responses, | |
3947 | * frame-received notifications, and other notifications. | |
3948 | */ | |
c79dd5b5 | 3949 | static void iwl4965_rx_handle(struct iwl_priv *priv) |
b481de9c | 3950 | { |
bb8c093b CH |
3951 | struct iwl4965_rx_mem_buffer *rxb; |
3952 | struct iwl4965_rx_packet *pkt; | |
3953 | struct iwl4965_rx_queue *rxq = &priv->rxq; | |
b481de9c ZY |
3954 | u32 r, i; |
3955 | int reclaim; | |
3956 | unsigned long flags; | |
5c0eef96 | 3957 | u8 fill_rx = 0; |
d68ab680 | 3958 | u32 count = 8; |
b481de9c | 3959 | |
6440adb5 BC |
3960 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
3961 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 3962 | r = iwl4965_hw_get_rx_read(priv); |
b481de9c ZY |
3963 | i = rxq->read; |
3964 | ||
3965 | /* Rx interrupt, but nothing sent from uCode */ | |
3966 | if (i == r) | |
3967 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
3968 | ||
5c0eef96 MA |
3969 | if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
3970 | fill_rx = 1; | |
3971 | ||
b481de9c ZY |
3972 | while (i != r) { |
3973 | rxb = rxq->queue[i]; | |
3974 | ||
9fbab516 | 3975 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
3976 | * then a bug has been introduced in the queue refilling |
3977 | * routines -- catch it here */ | |
3978 | BUG_ON(rxb == NULL); | |
3979 | ||
3980 | rxq->queue[i] = NULL; | |
3981 | ||
3982 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, | |
9ee1ba47 | 3983 | priv->hw_setting.rx_buf_size, |
b481de9c | 3984 | PCI_DMA_FROMDEVICE); |
bb8c093b | 3985 | pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3986 | |
3987 | /* Reclaim a command buffer only if this packet is a response | |
3988 | * to a (driver-originated) command. | |
3989 | * If the packet (e.g. Rx frame) originated from uCode, | |
3990 | * there is no command buffer to reclaim. | |
3991 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
3992 | * but apparently a few don't get set; catch them here. */ | |
3993 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
3994 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 3995 | (pkt->hdr.cmd != REPLY_RX) && |
cfe01709 | 3996 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
3997 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
3998 | (pkt->hdr.cmd != REPLY_TX); | |
3999 | ||
4000 | /* Based on type of command response or notification, | |
4001 | * handle those that need handling via function in | |
bb8c093b | 4002 | * rx_handlers table. See iwl4965_setup_rx_handlers() */ |
b481de9c ZY |
4003 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
4004 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4005 | "r = %d, i = %d, %s, 0x%02x\n", r, i, | |
4006 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
4007 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
4008 | } else { | |
4009 | /* No handling needed */ | |
4010 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4011 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
4012 | r, i, get_cmd_string(pkt->hdr.cmd), | |
4013 | pkt->hdr.cmd); | |
4014 | } | |
4015 | ||
4016 | if (reclaim) { | |
9fbab516 | 4017 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 4018 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
4019 | * as we reclaim the driver command queue */ |
4020 | if (rxb && rxb->skb) | |
bb8c093b | 4021 | iwl4965_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
4022 | else |
4023 | IWL_WARNING("Claim null rxb?\n"); | |
4024 | } | |
4025 | ||
4026 | /* For now we just don't re-use anything. We can tweak this | |
4027 | * later to try and re-use notification packets and SKBs that | |
4028 | * fail to Rx correctly */ | |
4029 | if (rxb->skb != NULL) { | |
4030 | priv->alloc_rxb_skb--; | |
4031 | dev_kfree_skb_any(rxb->skb); | |
4032 | rxb->skb = NULL; | |
4033 | } | |
4034 | ||
4035 | pci_unmap_single(priv->pci_dev, rxb->dma_addr, | |
9ee1ba47 RR |
4036 | priv->hw_setting.rx_buf_size, |
4037 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
4038 | spin_lock_irqsave(&rxq->lock, flags); |
4039 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
4040 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4041 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
4042 | /* If there are a lot of unused frames, |
4043 | * restock the Rx queue so ucode wont assert. */ | |
4044 | if (fill_rx) { | |
4045 | count++; | |
4046 | if (count >= 8) { | |
4047 | priv->rxq.read = i; | |
4048 | __iwl4965_rx_replenish(priv); | |
4049 | count = 0; | |
4050 | } | |
4051 | } | |
b481de9c ZY |
4052 | } |
4053 | ||
4054 | /* Backtrack one entry */ | |
4055 | priv->rxq.read = i; | |
bb8c093b | 4056 | iwl4965_rx_queue_restock(priv); |
b481de9c ZY |
4057 | } |
4058 | ||
6440adb5 BC |
4059 | /** |
4060 | * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware | |
4061 | */ | |
c79dd5b5 | 4062 | static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv, |
bb8c093b | 4063 | struct iwl4965_tx_queue *txq) |
b481de9c ZY |
4064 | { |
4065 | u32 reg = 0; | |
4066 | int rc = 0; | |
4067 | int txq_id = txq->q.id; | |
4068 | ||
4069 | if (txq->need_update == 0) | |
4070 | return rc; | |
4071 | ||
4072 | /* if we're trying to save power */ | |
4073 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
4074 | /* wake up nic if it's powered down ... | |
4075 | * uCode will wake up, and interrupt us again, so next | |
4076 | * time we'll skip this part. */ | |
3395f6e9 | 4077 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
4078 | |
4079 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
4080 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
3395f6e9 | 4081 | iwl_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
4082 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4083 | return rc; | |
4084 | } | |
4085 | ||
4086 | /* restore this queue's parameters in nic hardware. */ | |
3395f6e9 | 4087 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4088 | if (rc) |
4089 | return rc; | |
3395f6e9 | 4090 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4091 | txq->q.write_ptr | (txq_id << 8)); |
3395f6e9 | 4092 | iwl_release_nic_access(priv); |
b481de9c ZY |
4093 | |
4094 | /* else not in power-save mode, uCode will never sleep when we're | |
4095 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
4096 | } else | |
3395f6e9 | 4097 | iwl_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4098 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
4099 | |
4100 | txq->need_update = 0; | |
4101 | ||
4102 | return rc; | |
4103 | } | |
4104 | ||
0a6857e7 | 4105 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 4106 | static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon) |
b481de9c | 4107 | { |
0795af57 JP |
4108 | DECLARE_MAC_BUF(mac); |
4109 | ||
b481de9c | 4110 | IWL_DEBUG_RADIO("RX CONFIG:\n"); |
0a6857e7 | 4111 | iwl_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
4112 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
4113 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
4114 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
4115 | le32_to_cpu(rxon->filter_flags)); | |
4116 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
4117 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
4118 | rxon->ofdm_basic_rates); | |
4119 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
0795af57 JP |
4120 | IWL_DEBUG_RADIO("u8[6] node_addr: %s\n", |
4121 | print_mac(mac, rxon->node_addr)); | |
4122 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n", | |
4123 | print_mac(mac, rxon->bssid_addr)); | |
b481de9c ZY |
4124 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
4125 | } | |
4126 | #endif | |
4127 | ||
c79dd5b5 | 4128 | static void iwl4965_enable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
4129 | { |
4130 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
4131 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
3395f6e9 | 4132 | iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
4133 | } |
4134 | ||
0359facc MA |
4135 | /* call this function to flush any scheduled tasklet */ |
4136 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
4137 | { | |
4138 | /* wait to make sure we flush pedding tasklet*/ | |
4139 | synchronize_irq(priv->pci_dev->irq); | |
4140 | tasklet_kill(&priv->irq_tasklet); | |
4141 | } | |
4142 | ||
c79dd5b5 | 4143 | static inline void iwl4965_disable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
4144 | { |
4145 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
4146 | ||
4147 | /* disable interrupts from uCode/NIC to host */ | |
3395f6e9 | 4148 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
4149 | |
4150 | /* acknowledge/clear/reset any interrupts still pending | |
4151 | * from uCode or flow handler (Rx/Tx DMA) */ | |
3395f6e9 TW |
4152 | iwl_write32(priv, CSR_INT, 0xffffffff); |
4153 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
4154 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
4155 | } | |
4156 | ||
4157 | static const char *desc_lookup(int i) | |
4158 | { | |
4159 | switch (i) { | |
4160 | case 1: | |
4161 | return "FAIL"; | |
4162 | case 2: | |
4163 | return "BAD_PARAM"; | |
4164 | case 3: | |
4165 | return "BAD_CHECKSUM"; | |
4166 | case 4: | |
4167 | return "NMI_INTERRUPT"; | |
4168 | case 5: | |
4169 | return "SYSASSERT"; | |
4170 | case 6: | |
4171 | return "FATAL_ERROR"; | |
4172 | } | |
4173 | ||
4174 | return "UNKNOWN"; | |
4175 | } | |
4176 | ||
4177 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
4178 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
4179 | ||
c79dd5b5 | 4180 | static void iwl4965_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
4181 | { |
4182 | u32 data2, line; | |
4183 | u32 desc, time, count, base, data1; | |
4184 | u32 blink1, blink2, ilink1, ilink2; | |
4185 | int rc; | |
4186 | ||
4187 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
4188 | ||
57aab75a | 4189 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4190 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
4191 | return; | |
4192 | } | |
4193 | ||
3395f6e9 | 4194 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4195 | if (rc) { |
4196 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4197 | return; | |
4198 | } | |
4199 | ||
3395f6e9 | 4200 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
4201 | |
4202 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
4203 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 4204 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
4205 | } |
4206 | ||
3395f6e9 TW |
4207 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); |
4208 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
4209 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
4210 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
4211 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
4212 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
4213 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
4214 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
4215 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
b481de9c ZY |
4216 | |
4217 | IWL_ERROR("Desc Time " | |
4218 | "data1 data2 line\n"); | |
4219 | IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n", | |
4220 | desc_lookup(desc), desc, time, data1, data2, line); | |
4221 | IWL_ERROR("blink1 blink2 ilink1 ilink2\n"); | |
4222 | IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
4223 | ilink1, ilink2); | |
4224 | ||
3395f6e9 | 4225 | iwl_release_nic_access(priv); |
b481de9c ZY |
4226 | } |
4227 | ||
4228 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
4229 | ||
4230 | /** | |
bb8c093b | 4231 | * iwl4965_print_event_log - Dump error event log to syslog |
b481de9c | 4232 | * |
3395f6e9 | 4233 | * NOTE: Must be called with iwl_grab_nic_access() already obtained! |
b481de9c | 4234 | */ |
c79dd5b5 | 4235 | static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
4236 | u32 num_events, u32 mode) |
4237 | { | |
4238 | u32 i; | |
4239 | u32 base; /* SRAM byte address of event log header */ | |
4240 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4241 | u32 ptr; /* SRAM byte address of log data */ | |
4242 | u32 ev, time, data; /* event log data */ | |
4243 | ||
4244 | if (num_events == 0) | |
4245 | return; | |
4246 | ||
4247 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4248 | ||
4249 | if (mode == 0) | |
4250 | event_size = 2 * sizeof(u32); | |
4251 | else | |
4252 | event_size = 3 * sizeof(u32); | |
4253 | ||
4254 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4255 | ||
4256 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4257 | * place event id # at far right for easier visual parsing. */ | |
4258 | for (i = 0; i < num_events; i++) { | |
3395f6e9 | 4259 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 4260 | ptr += sizeof(u32); |
3395f6e9 | 4261 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4262 | ptr += sizeof(u32); |
4263 | if (mode == 0) | |
4264 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4265 | else { | |
3395f6e9 | 4266 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c ZY |
4267 | ptr += sizeof(u32); |
4268 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4269 | } | |
4270 | } | |
4271 | } | |
4272 | ||
c79dd5b5 | 4273 | static void iwl4965_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c ZY |
4274 | { |
4275 | int rc; | |
4276 | u32 base; /* SRAM byte address of event log header */ | |
4277 | u32 capacity; /* event log capacity in # entries */ | |
4278 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4279 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4280 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4281 | u32 size; /* # entries that we'll print */ | |
4282 | ||
4283 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
57aab75a | 4284 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4285 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4286 | return; | |
4287 | } | |
4288 | ||
3395f6e9 | 4289 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4290 | if (rc) { |
4291 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4292 | return; | |
4293 | } | |
4294 | ||
4295 | /* event log header */ | |
3395f6e9 TW |
4296 | capacity = iwl_read_targ_mem(priv, base); |
4297 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4298 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4299 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4300 | |
4301 | size = num_wraps ? capacity : next_entry; | |
4302 | ||
4303 | /* bail out if nothing in log */ | |
4304 | if (size == 0) { | |
583fab37 | 4305 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
3395f6e9 | 4306 | iwl_release_nic_access(priv); |
b481de9c ZY |
4307 | return; |
4308 | } | |
4309 | ||
583fab37 | 4310 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4311 | size, num_wraps); |
4312 | ||
4313 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4314 | * i.e the next one that uCode would fill. */ | |
4315 | if (num_wraps) | |
bb8c093b | 4316 | iwl4965_print_event_log(priv, next_entry, |
b481de9c ZY |
4317 | capacity - next_entry, mode); |
4318 | ||
4319 | /* (then/else) start at top of log */ | |
bb8c093b | 4320 | iwl4965_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4321 | |
3395f6e9 | 4322 | iwl_release_nic_access(priv); |
b481de9c ZY |
4323 | } |
4324 | ||
4325 | /** | |
bb8c093b | 4326 | * iwl4965_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4327 | */ |
c79dd5b5 | 4328 | static void iwl4965_irq_handle_error(struct iwl_priv *priv) |
b481de9c | 4329 | { |
bb8c093b | 4330 | /* Set the FW error flag -- cleared on iwl4965_down */ |
b481de9c ZY |
4331 | set_bit(STATUS_FW_ERROR, &priv->status); |
4332 | ||
4333 | /* Cancel currently queued command. */ | |
4334 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4335 | ||
0a6857e7 TW |
4336 | #ifdef CONFIG_IWLWIFI_DEBUG |
4337 | if (iwl_debug_level & IWL_DL_FW_ERRORS) { | |
bb8c093b CH |
4338 | iwl4965_dump_nic_error_log(priv); |
4339 | iwl4965_dump_nic_event_log(priv); | |
4340 | iwl4965_print_rx_config_cmd(&priv->staging_rxon); | |
b481de9c ZY |
4341 | } |
4342 | #endif | |
4343 | ||
4344 | wake_up_interruptible(&priv->wait_command_queue); | |
4345 | ||
4346 | /* Keep the restart process from trying to send host | |
4347 | * commands by clearing the INIT status bit */ | |
4348 | clear_bit(STATUS_READY, &priv->status); | |
4349 | ||
4350 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4351 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4352 | "Restarting adapter due to uCode error.\n"); | |
4353 | ||
3109ece1 | 4354 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4355 | memcpy(&priv->recovery_rxon, &priv->active_rxon, |
4356 | sizeof(priv->recovery_rxon)); | |
4357 | priv->error_recovering = 1; | |
4358 | } | |
4359 | queue_work(priv->workqueue, &priv->restart); | |
4360 | } | |
4361 | } | |
4362 | ||
c79dd5b5 | 4363 | static void iwl4965_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
4364 | { |
4365 | unsigned long flags; | |
4366 | ||
4367 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
4368 | sizeof(priv->staging_rxon)); | |
4369 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4370 | iwl4965_commit_rxon(priv); |
b481de9c | 4371 | |
bb8c093b | 4372 | iwl4965_rxon_add_station(priv, priv->bssid, 1); |
b481de9c ZY |
4373 | |
4374 | spin_lock_irqsave(&priv->lock, flags); | |
4375 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
4376 | priv->error_recovering = 0; | |
4377 | spin_unlock_irqrestore(&priv->lock, flags); | |
4378 | } | |
4379 | ||
c79dd5b5 | 4380 | static void iwl4965_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
4381 | { |
4382 | u32 inta, handled = 0; | |
4383 | u32 inta_fh; | |
4384 | unsigned long flags; | |
0a6857e7 | 4385 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
4386 | u32 inta_mask; |
4387 | #endif | |
4388 | ||
4389 | spin_lock_irqsave(&priv->lock, flags); | |
4390 | ||
4391 | /* Ack/clear/reset pending uCode interrupts. | |
4392 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4393 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
4394 | inta = iwl_read32(priv, CSR_INT); |
4395 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4396 | |
4397 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4398 | * Any new interrupts that happen after this, either while we're | |
4399 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
4400 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
4401 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4402 | |
0a6857e7 TW |
4403 | #ifdef CONFIG_IWLWIFI_DEBUG |
4404 | if (iwl_debug_level & IWL_DL_ISR) { | |
9fbab516 | 4405 | /* just for debug */ |
3395f6e9 | 4406 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
b481de9c ZY |
4407 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4408 | inta, inta_mask, inta_fh); | |
4409 | } | |
4410 | #endif | |
4411 | ||
4412 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4413 | * atomic, make sure that inta covers all the interrupts that | |
4414 | * we've discovered, even if FH interrupt came in just after | |
4415 | * reading CSR_INT. */ | |
6f83eaa1 | 4416 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 4417 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4418 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
4419 | inta |= CSR_INT_BIT_FH_TX; |
4420 | ||
4421 | /* Now service all interrupt bits discovered above. */ | |
4422 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4423 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4424 | ||
4425 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4426 | iwl4965_disable_interrupts(priv); |
b481de9c | 4427 | |
bb8c093b | 4428 | iwl4965_irq_handle_error(priv); |
b481de9c ZY |
4429 | |
4430 | handled |= CSR_INT_BIT_HW_ERR; | |
4431 | ||
4432 | spin_unlock_irqrestore(&priv->lock, flags); | |
4433 | ||
4434 | return; | |
4435 | } | |
4436 | ||
0a6857e7 TW |
4437 | #ifdef CONFIG_IWLWIFI_DEBUG |
4438 | if (iwl_debug_level & (IWL_DL_ISR)) { | |
b481de9c | 4439 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4440 | if (inta & CSR_INT_BIT_SCD) |
4441 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4442 | "the frame/frames.\n"); | |
b481de9c ZY |
4443 | |
4444 | /* Alive notification via Rx interrupt will do the real work */ | |
4445 | if (inta & CSR_INT_BIT_ALIVE) | |
4446 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4447 | } | |
4448 | #endif | |
4449 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4450 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 4451 | |
9fbab516 | 4452 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
4453 | if (inta & CSR_INT_BIT_RF_KILL) { |
4454 | int hw_rf_kill = 0; | |
3395f6e9 | 4455 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
4456 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
4457 | hw_rf_kill = 1; | |
4458 | ||
4459 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, | |
4460 | "RF_KILL bit toggled to %s.\n", | |
4461 | hw_rf_kill ? "disable radio":"enable radio"); | |
4462 | ||
4463 | /* Queue restart only if RF_KILL switch was set to "kill" | |
4464 | * when we loaded driver, and is now set to "enable". | |
4465 | * After we're Alive, RF_KILL gets handled by | |
3230455d | 4466 | * iwl4965_rx_card_state_notif() */ |
53e49093 ZY |
4467 | if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { |
4468 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
b481de9c | 4469 | queue_work(priv->workqueue, &priv->restart); |
53e49093 | 4470 | } |
b481de9c ZY |
4471 | |
4472 | handled |= CSR_INT_BIT_RF_KILL; | |
4473 | } | |
4474 | ||
9fbab516 | 4475 | /* Chip got too hot and stopped itself */ |
b481de9c ZY |
4476 | if (inta & CSR_INT_BIT_CT_KILL) { |
4477 | IWL_ERROR("Microcode CT kill error detected.\n"); | |
4478 | handled |= CSR_INT_BIT_CT_KILL; | |
4479 | } | |
4480 | ||
4481 | /* Error detected by uCode */ | |
4482 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4483 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4484 | inta); | |
bb8c093b | 4485 | iwl4965_irq_handle_error(priv); |
b481de9c ZY |
4486 | handled |= CSR_INT_BIT_SW_ERR; |
4487 | } | |
4488 | ||
4489 | /* uCode wakes up after power-down sleep */ | |
4490 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4491 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b CH |
4492 | iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq); |
4493 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]); | |
4494 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]); | |
4495 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]); | |
4496 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]); | |
4497 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]); | |
4498 | iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
4499 | |
4500 | handled |= CSR_INT_BIT_WAKEUP; | |
4501 | } | |
4502 | ||
4503 | /* All uCode command responses, including Tx command responses, | |
4504 | * Rx "responses" (frame-received notification), and other | |
4505 | * notifications from uCode come through here*/ | |
4506 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4507 | iwl4965_rx_handle(priv); |
b481de9c ZY |
4508 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4509 | } | |
4510 | ||
4511 | if (inta & CSR_INT_BIT_FH_TX) { | |
4512 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4513 | handled |= CSR_INT_BIT_FH_TX; | |
4514 | } | |
4515 | ||
4516 | if (inta & ~handled) | |
4517 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4518 | ||
4519 | if (inta & ~CSR_INI_SET_MASK) { | |
4520 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4521 | inta & ~CSR_INI_SET_MASK); | |
4522 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4523 | } | |
4524 | ||
4525 | /* Re-enable all interrupts */ | |
0359facc MA |
4526 | /* only Re-enable if diabled by irq */ |
4527 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4528 | iwl4965_enable_interrupts(priv); | |
b481de9c | 4529 | |
0a6857e7 TW |
4530 | #ifdef CONFIG_IWLWIFI_DEBUG |
4531 | if (iwl_debug_level & (IWL_DL_ISR)) { | |
3395f6e9 TW |
4532 | inta = iwl_read32(priv, CSR_INT); |
4533 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
4534 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4535 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4536 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4537 | } | |
4538 | #endif | |
4539 | spin_unlock_irqrestore(&priv->lock, flags); | |
4540 | } | |
4541 | ||
bb8c093b | 4542 | static irqreturn_t iwl4965_isr(int irq, void *data) |
b481de9c | 4543 | { |
c79dd5b5 | 4544 | struct iwl_priv *priv = data; |
b481de9c ZY |
4545 | u32 inta, inta_mask; |
4546 | u32 inta_fh; | |
4547 | if (!priv) | |
4548 | return IRQ_NONE; | |
4549 | ||
4550 | spin_lock(&priv->lock); | |
4551 | ||
4552 | /* Disable (but don't clear!) interrupts here to avoid | |
4553 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4554 | * If we have something to service, the tasklet will re-enable ints. | |
4555 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
3395f6e9 TW |
4556 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
4557 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4558 | |
4559 | /* Discover which interrupts are active/pending */ | |
3395f6e9 TW |
4560 | inta = iwl_read32(priv, CSR_INT); |
4561 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4562 | |
4563 | /* Ignore interrupt if there's nothing in NIC to service. | |
4564 | * This may be due to IRQ shared with another device, | |
4565 | * or due to sporadic interrupts thrown from our NIC. */ | |
4566 | if (!inta && !inta_fh) { | |
4567 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4568 | goto none; | |
4569 | } | |
4570 | ||
4571 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
66fbb541 ON |
4572 | /* Hardware disappeared. It might have already raised |
4573 | * an interrupt */ | |
b481de9c | 4574 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta); |
66fbb541 | 4575 | goto unplugged; |
b481de9c ZY |
4576 | } |
4577 | ||
4578 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4579 | inta, inta_mask, inta_fh); | |
4580 | ||
25c03d8e JP |
4581 | inta &= ~CSR_INT_BIT_SCD; |
4582 | ||
bb8c093b | 4583 | /* iwl4965_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4584 | if (likely(inta || inta_fh)) |
4585 | tasklet_schedule(&priv->irq_tasklet); | |
b481de9c | 4586 | |
66fbb541 ON |
4587 | unplugged: |
4588 | spin_unlock(&priv->lock); | |
b481de9c ZY |
4589 | return IRQ_HANDLED; |
4590 | ||
4591 | none: | |
4592 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
4593 | /* only Re-enable if diabled by irq */ |
4594 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4595 | iwl4965_enable_interrupts(priv); | |
b481de9c ZY |
4596 | spin_unlock(&priv->lock); |
4597 | return IRQ_NONE; | |
4598 | } | |
4599 | ||
b481de9c ZY |
4600 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4601 | * sending probe req. This should be set long enough to hear probe responses | |
4602 | * from more than one AP. */ | |
4603 | #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4604 | #define IWL_ACTIVE_DWELL_TIME_52 (10) | |
4605 | ||
4606 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4607 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4608 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4609 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4610 | * no other traffic). | |
4611 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4612 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
4613 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */ | |
4614 | ||
4615 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4616 | * Must be set longer than active dwell time. | |
4617 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4618 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4619 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4620 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4621 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4622 | ||
c79dd5b5 | 4623 | static inline u16 iwl4965_get_active_dwell_time(struct iwl_priv *priv, |
8318d78a | 4624 | enum ieee80211_band band) |
b481de9c | 4625 | { |
8318d78a | 4626 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4627 | return IWL_ACTIVE_DWELL_TIME_52; |
4628 | else | |
4629 | return IWL_ACTIVE_DWELL_TIME_24; | |
4630 | } | |
4631 | ||
c79dd5b5 | 4632 | static u16 iwl4965_get_passive_dwell_time(struct iwl_priv *priv, |
8318d78a | 4633 | enum ieee80211_band band) |
b481de9c | 4634 | { |
8318d78a JB |
4635 | u16 active = iwl4965_get_active_dwell_time(priv, band); |
4636 | u16 passive = (band != IEEE80211_BAND_5GHZ) ? | |
b481de9c ZY |
4637 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4638 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4639 | ||
3109ece1 | 4640 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4641 | /* If we're associated, we clamp the maximum passive |
4642 | * dwell time to be 98% of the beacon interval (minus | |
4643 | * 2 * channel tune time) */ | |
4644 | passive = priv->beacon_int; | |
4645 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4646 | passive = IWL_PASSIVE_DWELL_BASE; | |
4647 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4648 | } | |
4649 | ||
4650 | if (passive <= active) | |
4651 | passive = active + 1; | |
4652 | ||
4653 | return passive; | |
4654 | } | |
4655 | ||
c79dd5b5 | 4656 | static int iwl4965_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 4657 | enum ieee80211_band band, |
b481de9c | 4658 | u8 is_active, u8 direct_mask, |
bb8c093b | 4659 | struct iwl4965_scan_channel *scan_ch) |
b481de9c ZY |
4660 | { |
4661 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4662 | const struct ieee80211_supported_band *sband; |
bf85ea4f | 4663 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
4664 | u16 passive_dwell = 0; |
4665 | u16 active_dwell = 0; | |
4666 | int added, i; | |
4667 | ||
8318d78a JB |
4668 | sband = iwl4965_get_hw_mode(priv, band); |
4669 | if (!sband) | |
b481de9c ZY |
4670 | return 0; |
4671 | ||
8318d78a | 4672 | channels = sband->channels; |
b481de9c | 4673 | |
8318d78a JB |
4674 | active_dwell = iwl4965_get_active_dwell_time(priv, band); |
4675 | passive_dwell = iwl4965_get_passive_dwell_time(priv, band); | |
b481de9c | 4676 | |
8318d78a | 4677 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4678 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4679 | continue; | |
4680 | ||
8318d78a | 4681 | if (ieee80211_frequency_to_channel(channels[i].center_freq) == |
b481de9c | 4682 | le16_to_cpu(priv->active_rxon.channel)) { |
3109ece1 | 4683 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
4684 | IWL_DEBUG_SCAN |
4685 | ("Skipping current channel %d\n", | |
4686 | le16_to_cpu(priv->active_rxon.channel)); | |
4687 | continue; | |
4688 | } | |
4689 | } else if (priv->only_active_channel) | |
4690 | continue; | |
4691 | ||
8318d78a | 4692 | scan_ch->channel = ieee80211_frequency_to_channel(channels[i].center_freq); |
b481de9c | 4693 | |
8622e705 | 4694 | ch_info = iwl_get_channel_info(priv, band, |
9fbab516 | 4695 | scan_ch->channel); |
b481de9c ZY |
4696 | if (!is_channel_valid(ch_info)) { |
4697 | IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n", | |
4698 | scan_ch->channel); | |
4699 | continue; | |
4700 | } | |
4701 | ||
4702 | if (!is_active || is_channel_passive(ch_info) || | |
8318d78a | 4703 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) |
b481de9c ZY |
4704 | scan_ch->type = 0; /* passive */ |
4705 | else | |
4706 | scan_ch->type = 1; /* active */ | |
4707 | ||
4708 | if (scan_ch->type & 1) | |
4709 | scan_ch->type |= (direct_mask << 1); | |
4710 | ||
4711 | if (is_channel_narrow(ch_info)) | |
4712 | scan_ch->type |= (1 << 7); | |
4713 | ||
4714 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
4715 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
4716 | ||
9fbab516 | 4717 | /* Set txpower levels to defaults */ |
b481de9c ZY |
4718 | scan_ch->tpc.dsp_atten = 110; |
4719 | /* scan_pwr_info->tpc.dsp_atten; */ | |
4720 | ||
4721 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 4722 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4723 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
4724 | else { | |
4725 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
4726 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 4727 | * power level: |
8a1b0245 | 4728 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
4729 | */ |
4730 | } | |
4731 | ||
4732 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
4733 | scan_ch->channel, | |
4734 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
4735 | (scan_ch->type & 1) ? | |
4736 | active_dwell : passive_dwell); | |
4737 | ||
4738 | scan_ch++; | |
4739 | added++; | |
4740 | } | |
4741 | ||
4742 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
4743 | return added; | |
4744 | } | |
4745 | ||
c79dd5b5 | 4746 | static void iwl4965_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
4747 | struct ieee80211_rate *rates) |
4748 | { | |
4749 | int i; | |
4750 | ||
4751 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
4752 | rates[i].bitrate = iwl4965_rates[i].ieee * 5; |
4753 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4754 | rates[i].hw_value_short = i; | |
4755 | rates[i].flags = 0; | |
4756 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
b481de9c | 4757 | /* |
8318d78a | 4758 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 4759 | */ |
35cdeaf4 TW |
4760 | rates[i].flags |= |
4761 | (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
4762 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
b481de9c | 4763 | } |
b481de9c | 4764 | } |
b481de9c ZY |
4765 | } |
4766 | ||
4767 | /** | |
bb8c093b | 4768 | * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 4769 | */ |
bf85ea4f | 4770 | int iwl4965_init_geos(struct iwl_priv *priv) |
b481de9c | 4771 | { |
bf85ea4f | 4772 | struct iwl_channel_info *ch; |
8211ef78 | 4773 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
4774 | struct ieee80211_channel *channels; |
4775 | struct ieee80211_channel *geo_ch; | |
4776 | struct ieee80211_rate *rates; | |
4777 | int i = 0; | |
b481de9c | 4778 | |
8318d78a JB |
4779 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
4780 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
4781 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
4782 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4783 | return 0; | |
4784 | } | |
4785 | ||
b481de9c ZY |
4786 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
4787 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 4788 | if (!channels) |
b481de9c | 4789 | return -ENOMEM; |
b481de9c | 4790 | |
8211ef78 | 4791 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
4792 | GFP_KERNEL); |
4793 | if (!rates) { | |
b481de9c ZY |
4794 | kfree(channels); |
4795 | return -ENOMEM; | |
4796 | } | |
4797 | ||
b481de9c | 4798 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 | 4799 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
bf85ea4f | 4800 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; |
8211ef78 TW |
4801 | /* just OFDM */ |
4802 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
4803 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
8318d78a | 4804 | |
1ea87396 | 4805 | iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ); |
78330fdd | 4806 | |
8211ef78 TW |
4807 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
4808 | sband->channels = channels; | |
4809 | /* OFDM & CCK */ | |
4810 | sband->bitrates = rates; | |
4811 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c | 4812 | |
1ea87396 | 4813 | iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ); |
78330fdd | 4814 | |
b481de9c ZY |
4815 | priv->ieee_channels = channels; |
4816 | priv->ieee_rates = rates; | |
4817 | ||
bb8c093b | 4818 | iwl4965_init_hw_rates(priv, rates); |
b481de9c | 4819 | |
8211ef78 | 4820 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
4821 | ch = &priv->channel_info[i]; |
4822 | ||
8211ef78 TW |
4823 | /* FIXME: might be removed if scan is OK */ |
4824 | if (!is_channel_valid(ch)) | |
b481de9c | 4825 | continue; |
b481de9c | 4826 | |
8211ef78 TW |
4827 | if (is_channel_a_band(ch)) |
4828 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
4829 | else | |
4830 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
b481de9c | 4831 | |
8211ef78 TW |
4832 | geo_ch = &sband->channels[sband->n_channels++]; |
4833 | ||
4834 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
4835 | geo_ch->max_power = ch->max_power_avg; |
4836 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 4837 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
4838 | |
4839 | if (is_channel_valid(ch)) { | |
8318d78a JB |
4840 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
4841 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 4842 | |
8318d78a JB |
4843 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
4844 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
4845 | |
4846 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 4847 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
4848 | |
4849 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
4850 | priv->max_channel_txpower_limit = | |
4851 | ch->max_power_avg; | |
8211ef78 | 4852 | } else { |
8318d78a | 4853 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
4854 | } |
4855 | ||
4856 | /* Save flags for reg domain usage */ | |
4857 | geo_ch->orig_flags = geo_ch->flags; | |
4858 | ||
4859 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
4860 | ch->channel, geo_ch->center_freq, | |
4861 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
4862 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
4863 | "restricted" : "valid", | |
4864 | geo_ch->flags); | |
b481de9c ZY |
4865 | } |
4866 | ||
82b9a121 TW |
4867 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
4868 | priv->cfg->sku & IWL_SKU_A) { | |
b481de9c ZY |
4869 | printk(KERN_INFO DRV_NAME |
4870 | ": Incorrectly detected BG card as ABG. Please send " | |
4871 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
4872 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 4873 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
4874 | } |
4875 | ||
4876 | printk(KERN_INFO DRV_NAME | |
4877 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
4878 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
4879 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 4880 | |
e0e0a67e JL |
4881 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
4882 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
4883 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
4884 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
4885 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
4886 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 4887 | |
b481de9c ZY |
4888 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
4889 | ||
4890 | return 0; | |
4891 | } | |
4892 | ||
849e0dce RC |
4893 | /* |
4894 | * iwl4965_free_geos - undo allocations in iwl4965_init_geos | |
4895 | */ | |
bf85ea4f | 4896 | void iwl4965_free_geos(struct iwl_priv *priv) |
849e0dce | 4897 | { |
849e0dce RC |
4898 | kfree(priv->ieee_channels); |
4899 | kfree(priv->ieee_rates); | |
4900 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4901 | } | |
4902 | ||
b481de9c ZY |
4903 | /****************************************************************************** |
4904 | * | |
4905 | * uCode download functions | |
4906 | * | |
4907 | ******************************************************************************/ | |
4908 | ||
c79dd5b5 | 4909 | static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 4910 | { |
98c92211 TW |
4911 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
4912 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
4913 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
4914 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
4915 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
4916 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
4917 | } |
4918 | ||
4919 | /** | |
bb8c093b | 4920 | * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4921 | * looking at all data. |
4922 | */ | |
c79dd5b5 | 4923 | static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image, |
9fbab516 | 4924 | u32 len) |
b481de9c ZY |
4925 | { |
4926 | u32 val; | |
4927 | u32 save_len = len; | |
4928 | int rc = 0; | |
4929 | u32 errcnt; | |
4930 | ||
4931 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4932 | ||
3395f6e9 | 4933 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4934 | if (rc) |
4935 | return rc; | |
4936 | ||
3395f6e9 | 4937 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
b481de9c ZY |
4938 | |
4939 | errcnt = 0; | |
4940 | for (; len > 0; len -= sizeof(u32), image++) { | |
4941 | /* read data comes through single port, auto-incr addr */ | |
4942 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4943 | * if IWL_DL_IO is set */ | |
3395f6e9 | 4944 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4945 | if (val != le32_to_cpu(*image)) { |
4946 | IWL_ERROR("uCode INST section is invalid at " | |
4947 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
4948 | save_len - len, val, le32_to_cpu(*image)); | |
4949 | rc = -EIO; | |
4950 | errcnt++; | |
4951 | if (errcnt >= 20) | |
4952 | break; | |
4953 | } | |
4954 | } | |
4955 | ||
3395f6e9 | 4956 | iwl_release_nic_access(priv); |
b481de9c ZY |
4957 | |
4958 | if (!errcnt) | |
4959 | IWL_DEBUG_INFO | |
4960 | ("ucode image in INSTRUCTION memory is good\n"); | |
4961 | ||
4962 | return rc; | |
4963 | } | |
4964 | ||
4965 | ||
4966 | /** | |
bb8c093b | 4967 | * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4968 | * using sample data 100 bytes apart. If these sample points are good, |
4969 | * it's a pretty good bet that everything between them is good, too. | |
4970 | */ | |
c79dd5b5 | 4971 | static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
4972 | { |
4973 | u32 val; | |
4974 | int rc = 0; | |
4975 | u32 errcnt = 0; | |
4976 | u32 i; | |
4977 | ||
4978 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4979 | ||
3395f6e9 | 4980 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4981 | if (rc) |
4982 | return rc; | |
4983 | ||
4984 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
4985 | /* read data comes through single port, auto-incr addr */ | |
4986 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4987 | * if IWL_DL_IO is set */ | |
3395f6e9 | 4988 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
b481de9c | 4989 | i + RTC_INST_LOWER_BOUND); |
3395f6e9 | 4990 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4991 | if (val != le32_to_cpu(*image)) { |
4992 | #if 0 /* Enable this if you want to see details */ | |
4993 | IWL_ERROR("uCode INST section is invalid at " | |
4994 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
4995 | i, val, *image); | |
4996 | #endif | |
4997 | rc = -EIO; | |
4998 | errcnt++; | |
4999 | if (errcnt >= 3) | |
5000 | break; | |
5001 | } | |
5002 | } | |
5003 | ||
3395f6e9 | 5004 | iwl_release_nic_access(priv); |
b481de9c ZY |
5005 | |
5006 | return rc; | |
5007 | } | |
5008 | ||
5009 | ||
5010 | /** | |
bb8c093b | 5011 | * iwl4965_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5012 | * and verify its contents |
5013 | */ | |
c79dd5b5 | 5014 | static int iwl4965_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
5015 | { |
5016 | __le32 *image; | |
5017 | u32 len; | |
5018 | int rc = 0; | |
5019 | ||
5020 | /* Try bootstrap */ | |
5021 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5022 | len = priv->ucode_boot.len; | |
bb8c093b | 5023 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5024 | if (rc == 0) { |
5025 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5026 | return 0; | |
5027 | } | |
5028 | ||
5029 | /* Try initialize */ | |
5030 | image = (__le32 *)priv->ucode_init.v_addr; | |
5031 | len = priv->ucode_init.len; | |
bb8c093b | 5032 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5033 | if (rc == 0) { |
5034 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5035 | return 0; | |
5036 | } | |
5037 | ||
5038 | /* Try runtime/protocol */ | |
5039 | image = (__le32 *)priv->ucode_code.v_addr; | |
5040 | len = priv->ucode_code.len; | |
bb8c093b | 5041 | rc = iwl4965_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5042 | if (rc == 0) { |
5043 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5044 | return 0; | |
5045 | } | |
5046 | ||
5047 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5048 | ||
9fbab516 BC |
5049 | /* Since nothing seems to match, show first several data entries in |
5050 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5051 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5052 | image = (__le32 *)priv->ucode_boot.v_addr; |
5053 | len = priv->ucode_boot.len; | |
bb8c093b | 5054 | rc = iwl4965_verify_inst_full(priv, image, len); |
b481de9c ZY |
5055 | |
5056 | return rc; | |
5057 | } | |
5058 | ||
c79dd5b5 | 5059 | static void iwl4965_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
5060 | { |
5061 | /* Remove all resets to allow NIC to operate */ | |
3395f6e9 | 5062 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5063 | } |
5064 | ||
90e759d1 | 5065 | |
b481de9c | 5066 | /** |
bb8c093b | 5067 | * iwl4965_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5068 | * |
5069 | * Copy into buffers for card to fetch via bus-mastering | |
5070 | */ | |
c79dd5b5 | 5071 | static int iwl4965_read_ucode(struct iwl_priv *priv) |
b481de9c | 5072 | { |
bb8c093b | 5073 | struct iwl4965_ucode *ucode; |
90e759d1 | 5074 | int ret; |
b481de9c | 5075 | const struct firmware *ucode_raw; |
4bf775cd | 5076 | const char *name = priv->cfg->fw_name; |
b481de9c ZY |
5077 | u8 *src; |
5078 | size_t len; | |
5079 | u32 ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
5080 | ||
5081 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5082 | * request_firmware() is synchronous, file is in memory on return. */ | |
90e759d1 TW |
5083 | ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev); |
5084 | if (ret < 0) { | |
5085 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5086 | name, ret); | |
b481de9c ZY |
5087 | goto error; |
5088 | } | |
5089 | ||
5090 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5091 | name, ucode_raw->size); | |
5092 | ||
5093 | /* Make sure that we got at least our header! */ | |
5094 | if (ucode_raw->size < sizeof(*ucode)) { | |
5095 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5096 | ret = -EINVAL; |
b481de9c ZY |
5097 | goto err_release; |
5098 | } | |
5099 | ||
5100 | /* Data from ucode file: header followed by uCode images */ | |
5101 | ucode = (void *)ucode_raw->data; | |
5102 | ||
5103 | ver = le32_to_cpu(ucode->ver); | |
5104 | inst_size = le32_to_cpu(ucode->inst_size); | |
5105 | data_size = le32_to_cpu(ucode->data_size); | |
5106 | init_size = le32_to_cpu(ucode->init_size); | |
5107 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5108 | boot_size = le32_to_cpu(ucode->boot_size); | |
5109 | ||
5110 | IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver); | |
5111 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", | |
5112 | inst_size); | |
5113 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", | |
5114 | data_size); | |
5115 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", | |
5116 | init_size); | |
5117 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", | |
5118 | init_data_size); | |
5119 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", | |
5120 | boot_size); | |
5121 | ||
5122 | /* Verify size of file vs. image size info in file's header */ | |
5123 | if (ucode_raw->size < sizeof(*ucode) + | |
5124 | inst_size + data_size + init_size + | |
5125 | init_data_size + boot_size) { | |
5126 | ||
5127 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5128 | (int)ucode_raw->size); | |
90e759d1 | 5129 | ret = -EINVAL; |
b481de9c ZY |
5130 | goto err_release; |
5131 | } | |
5132 | ||
5133 | /* Verify that uCode images will fit in card's SRAM */ | |
5134 | if (inst_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5135 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5136 | inst_size); | |
5137 | ret = -EINVAL; | |
b481de9c ZY |
5138 | goto err_release; |
5139 | } | |
5140 | ||
5141 | if (data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5142 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5143 | data_size); | |
5144 | ret = -EINVAL; | |
b481de9c ZY |
5145 | goto err_release; |
5146 | } | |
5147 | if (init_size > IWL_MAX_INST_SIZE) { | |
5148 | IWL_DEBUG_INFO | |
90e759d1 TW |
5149 | ("uCode init instr len %d too large to fit in\n", |
5150 | init_size); | |
5151 | ret = -EINVAL; | |
b481de9c ZY |
5152 | goto err_release; |
5153 | } | |
5154 | if (init_data_size > IWL_MAX_DATA_SIZE) { | |
5155 | IWL_DEBUG_INFO | |
90e759d1 TW |
5156 | ("uCode init data len %d too large to fit in\n", |
5157 | init_data_size); | |
5158 | ret = -EINVAL; | |
b481de9c ZY |
5159 | goto err_release; |
5160 | } | |
5161 | if (boot_size > IWL_MAX_BSM_SIZE) { | |
5162 | IWL_DEBUG_INFO | |
90e759d1 TW |
5163 | ("uCode boot instr len %d too large to fit in\n", |
5164 | boot_size); | |
5165 | ret = -EINVAL; | |
b481de9c ZY |
5166 | goto err_release; |
5167 | } | |
5168 | ||
5169 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5170 | ||
5171 | /* Runtime instructions and 2 copies of data: | |
5172 | * 1) unmodified from disk | |
5173 | * 2) backup cache for save/restore during power-downs */ | |
5174 | priv->ucode_code.len = inst_size; | |
98c92211 | 5175 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5176 | |
5177 | priv->ucode_data.len = data_size; | |
98c92211 | 5178 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5179 | |
5180 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5181 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c ZY |
5182 | |
5183 | /* Initialization instructions and data */ | |
90e759d1 TW |
5184 | if (init_size && init_data_size) { |
5185 | priv->ucode_init.len = init_size; | |
98c92211 | 5186 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5187 | |
5188 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5189 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5190 | |
5191 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5192 | goto err_pci_alloc; | |
5193 | } | |
b481de9c ZY |
5194 | |
5195 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5196 | if (boot_size) { |
5197 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5198 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5199 | |
90e759d1 TW |
5200 | if (!priv->ucode_boot.v_addr) |
5201 | goto err_pci_alloc; | |
5202 | } | |
b481de9c ZY |
5203 | |
5204 | /* Copy images into buffers for card's bus-master reads ... */ | |
5205 | ||
5206 | /* Runtime instructions (first block of data in file) */ | |
5207 | src = &ucode->data[0]; | |
5208 | len = priv->ucode_code.len; | |
90e759d1 | 5209 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5210 | memcpy(priv->ucode_code.v_addr, src, len); |
5211 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5212 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5213 | ||
5214 | /* Runtime data (2nd block) | |
bb8c093b | 5215 | * NOTE: Copy into backup buffer will be done in iwl4965_up() */ |
b481de9c ZY |
5216 | src = &ucode->data[inst_size]; |
5217 | len = priv->ucode_data.len; | |
90e759d1 | 5218 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5219 | memcpy(priv->ucode_data.v_addr, src, len); |
5220 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5221 | ||
5222 | /* Initialization instructions (3rd block) */ | |
5223 | if (init_size) { | |
5224 | src = &ucode->data[inst_size + data_size]; | |
5225 | len = priv->ucode_init.len; | |
90e759d1 TW |
5226 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5227 | len); | |
b481de9c ZY |
5228 | memcpy(priv->ucode_init.v_addr, src, len); |
5229 | } | |
5230 | ||
5231 | /* Initialization data (4th block) */ | |
5232 | if (init_data_size) { | |
5233 | src = &ucode->data[inst_size + data_size + init_size]; | |
5234 | len = priv->ucode_init_data.len; | |
90e759d1 TW |
5235 | IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n", |
5236 | len); | |
b481de9c ZY |
5237 | memcpy(priv->ucode_init_data.v_addr, src, len); |
5238 | } | |
5239 | ||
5240 | /* Bootstrap instructions (5th block) */ | |
5241 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5242 | len = priv->ucode_boot.len; | |
90e759d1 | 5243 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
5244 | memcpy(priv->ucode_boot.v_addr, src, len); |
5245 | ||
5246 | /* We have our copies now, allow OS release its copies */ | |
5247 | release_firmware(ucode_raw); | |
5248 | return 0; | |
5249 | ||
5250 | err_pci_alloc: | |
5251 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5252 | ret = -ENOMEM; |
bb8c093b | 5253 | iwl4965_dealloc_ucode_pci(priv); |
b481de9c ZY |
5254 | |
5255 | err_release: | |
5256 | release_firmware(ucode_raw); | |
5257 | ||
5258 | error: | |
90e759d1 | 5259 | return ret; |
b481de9c ZY |
5260 | } |
5261 | ||
5262 | ||
5263 | /** | |
bb8c093b | 5264 | * iwl4965_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5265 | * |
5266 | * Tell initialization uCode where to find runtime uCode. | |
5267 | * | |
5268 | * BSM registers initially contain pointers to initialization uCode. | |
5269 | * We need to replace them to load runtime uCode inst and data, | |
5270 | * and to save runtime data when powering down. | |
5271 | */ | |
c79dd5b5 | 5272 | static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
5273 | { |
5274 | dma_addr_t pinst; | |
5275 | dma_addr_t pdata; | |
5276 | int rc = 0; | |
5277 | unsigned long flags; | |
5278 | ||
5279 | /* bits 35:4 for 4965 */ | |
5280 | pinst = priv->ucode_code.p_addr >> 4; | |
5281 | pdata = priv->ucode_data_backup.p_addr >> 4; | |
5282 | ||
5283 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 5284 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
5285 | if (rc) { |
5286 | spin_unlock_irqrestore(&priv->lock, flags); | |
5287 | return rc; | |
5288 | } | |
5289 | ||
5290 | /* Tell bootstrap uCode where to find image to load */ | |
3395f6e9 TW |
5291 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5292 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5293 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5294 | priv->ucode_data.len); |
5295 | ||
5296 | /* Inst bytecount must be last to set up, bit 31 signals uCode | |
5297 | * that all new ptr/size info is in place */ | |
3395f6e9 | 5298 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5299 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5300 | ||
3395f6e9 | 5301 | iwl_release_nic_access(priv); |
b481de9c ZY |
5302 | |
5303 | spin_unlock_irqrestore(&priv->lock, flags); | |
5304 | ||
5305 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5306 | ||
5307 | return rc; | |
5308 | } | |
5309 | ||
5310 | /** | |
bb8c093b | 5311 | * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5312 | * |
5313 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5314 | * | |
5315 | * The 4965 "initialize" ALIVE reply contains calibration data for: | |
5316 | * Voltage, temperature, and MIMO tx gain correction, now stored in priv | |
5317 | * (3945 does not contain this data). | |
5318 | * | |
5319 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
5320 | */ | |
c79dd5b5 | 5321 | static void iwl4965_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5322 | { |
5323 | /* Check alive response for "valid" sign from uCode */ | |
5324 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5325 | /* We had an error bringing up the hardware, so take it | |
5326 | * all the way back down so we can try again */ | |
5327 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5328 | goto restart; | |
5329 | } | |
5330 | ||
5331 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5332 | * This is a paranoid check, because we would not have gotten the | |
5333 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5334 | if (iwl4965_verify_ucode(priv)) { |
b481de9c ZY |
5335 | /* Runtime instruction load was bad; |
5336 | * take it all the way back down so we can try again */ | |
5337 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5338 | goto restart; | |
5339 | } | |
5340 | ||
5341 | /* Calculate temperature */ | |
5342 | priv->temperature = iwl4965_get_temperature(priv); | |
5343 | ||
5344 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5345 | * load and launch runtime uCode, which will send us another "Alive" | |
5346 | * notification. */ | |
5347 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5348 | if (iwl4965_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5349 | /* Runtime instruction load won't happen; |
5350 | * take it all the way back down so we can try again */ | |
5351 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5352 | goto restart; | |
5353 | } | |
5354 | return; | |
5355 | ||
5356 | restart: | |
5357 | queue_work(priv->workqueue, &priv->restart); | |
5358 | } | |
5359 | ||
5360 | ||
5361 | /** | |
bb8c093b | 5362 | * iwl4965_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5363 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5364 | * Alive gets handled by iwl4965_init_alive_start()). |
b481de9c | 5365 | */ |
c79dd5b5 | 5366 | static void iwl4965_alive_start(struct iwl_priv *priv) |
b481de9c | 5367 | { |
57aab75a | 5368 | int ret = 0; |
b481de9c ZY |
5369 | |
5370 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5371 | ||
5372 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5373 | /* We had an error bringing up the hardware, so take it | |
5374 | * all the way back down so we can try again */ | |
5375 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5376 | goto restart; | |
5377 | } | |
5378 | ||
5379 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5380 | * This is a paranoid check, because we would not have gotten the | |
5381 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5382 | if (iwl4965_verify_ucode(priv)) { |
b481de9c ZY |
5383 | /* Runtime instruction load was bad; |
5384 | * take it all the way back down so we can try again */ | |
5385 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5386 | goto restart; | |
5387 | } | |
5388 | ||
bf85ea4f | 5389 | iwlcore_clear_stations_table(priv); |
b481de9c | 5390 | |
57aab75a TW |
5391 | ret = priv->cfg->ops->lib->alive_notify(priv); |
5392 | if (ret) { | |
b481de9c | 5393 | IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n", |
57aab75a | 5394 | ret); |
b481de9c ZY |
5395 | goto restart; |
5396 | } | |
5397 | ||
9fbab516 | 5398 | /* After the ALIVE response, we can send host commands to 4965 uCode */ |
b481de9c ZY |
5399 | set_bit(STATUS_ALIVE, &priv->status); |
5400 | ||
5401 | /* Clear out the uCode error bit if it is set */ | |
5402 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5403 | ||
fee1247a | 5404 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
5405 | return; |
5406 | ||
5a66926a | 5407 | ieee80211_start_queues(priv->hw); |
b481de9c ZY |
5408 | |
5409 | priv->active_rate = priv->rates_mask; | |
5410 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5411 | ||
bb8c093b | 5412 | iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5413 | |
3109ece1 | 5414 | if (iwl_is_associated(priv)) { |
bb8c093b CH |
5415 | struct iwl4965_rxon_cmd *active_rxon = |
5416 | (struct iwl4965_rxon_cmd *)(&priv->active_rxon); | |
b481de9c ZY |
5417 | |
5418 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
5419 | sizeof(priv->staging_rxon)); | |
5420 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5421 | } else { | |
5422 | /* Initialize our rx_config data */ | |
bb8c093b | 5423 | iwl4965_connection_init_rx_config(priv); |
b481de9c ZY |
5424 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
5425 | } | |
5426 | ||
9fbab516 | 5427 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5428 | iwl4965_send_bt_config(priv); |
b481de9c ZY |
5429 | |
5430 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5431 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
5432 | |
5433 | /* At this point, the NIC is initialized and operational */ | |
5434 | priv->notif_missed_beacons = 0; | |
b481de9c ZY |
5435 | |
5436 | iwl4965_rf_kill_ct_config(priv); | |
5a66926a | 5437 | |
fe00b5a5 RC |
5438 | iwl_leds_register(priv); |
5439 | ||
b481de9c | 5440 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5441 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5442 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5443 | |
5444 | if (priv->error_recovering) | |
bb8c093b | 5445 | iwl4965_error_recovery(priv); |
b481de9c | 5446 | |
c8381fdc | 5447 | iwlcore_low_level_notify(priv, IWLCORE_START_EVT); |
84363e6e | 5448 | ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); |
b481de9c ZY |
5449 | return; |
5450 | ||
5451 | restart: | |
5452 | queue_work(priv->workqueue, &priv->restart); | |
5453 | } | |
5454 | ||
c79dd5b5 | 5455 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 5456 | |
c79dd5b5 | 5457 | static void __iwl4965_down(struct iwl_priv *priv) |
b481de9c ZY |
5458 | { |
5459 | unsigned long flags; | |
5460 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5461 | struct ieee80211_conf *conf = NULL; | |
5462 | ||
5463 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5464 | ||
5465 | conf = ieee80211_get_hw_conf(priv->hw); | |
5466 | ||
5467 | if (!exit_pending) | |
5468 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5469 | ||
ab53d8af MA |
5470 | iwl_leds_unregister(priv); |
5471 | ||
c8381fdc MA |
5472 | iwlcore_low_level_notify(priv, IWLCORE_STOP_EVT); |
5473 | ||
bf85ea4f | 5474 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5475 | |
5476 | /* Unblock any waiting calls */ | |
5477 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5478 | ||
b481de9c ZY |
5479 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5480 | * exiting the module */ | |
5481 | if (!exit_pending) | |
5482 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5483 | ||
5484 | /* stop and reset the on-board processor */ | |
3395f6e9 | 5485 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5486 | |
5487 | /* tell the device to stop sending interrupts */ | |
0359facc | 5488 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5489 | iwl4965_disable_interrupts(priv); |
0359facc MA |
5490 | spin_unlock_irqrestore(&priv->lock, flags); |
5491 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5492 | |
5493 | if (priv->mac80211_registered) | |
5494 | ieee80211_stop_queues(priv->hw); | |
5495 | ||
bb8c093b | 5496 | /* If we have not previously called iwl4965_init() then |
b481de9c | 5497 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
fee1247a | 5498 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
5499 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5500 | STATUS_RF_KILL_HW | | |
5501 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5502 | STATUS_RF_KILL_SW | | |
9788864e RC |
5503 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5504 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5505 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5506 | STATUS_IN_SUSPEND; | |
5507 | goto exit; | |
5508 | } | |
5509 | ||
5510 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5511 | * SUSPEND bits and continue taking the NIC down. */ | |
5512 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5513 | STATUS_RF_KILL_HW | | |
5514 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5515 | STATUS_RF_KILL_SW | | |
9788864e RC |
5516 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5517 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5518 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5519 | STATUS_IN_SUSPEND | | |
5520 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
5521 | STATUS_FW_ERROR; | |
5522 | ||
5523 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 5524 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 5525 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5526 | spin_unlock_irqrestore(&priv->lock, flags); |
5527 | ||
bb8c093b CH |
5528 | iwl4965_hw_txq_ctx_stop(priv); |
5529 | iwl4965_hw_rxq_stop(priv); | |
b481de9c ZY |
5530 | |
5531 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
5532 | if (!iwl_grab_nic_access(priv)) { |
5533 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5534 | APMG_CLK_VAL_DMA_CLK_RQT); |
3395f6e9 | 5535 | iwl_release_nic_access(priv); |
b481de9c ZY |
5536 | } |
5537 | spin_unlock_irqrestore(&priv->lock, flags); | |
5538 | ||
5539 | udelay(5); | |
5540 | ||
bb8c093b | 5541 | iwl4965_hw_nic_stop_master(priv); |
3395f6e9 | 5542 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
bb8c093b | 5543 | iwl4965_hw_nic_reset(priv); |
b481de9c ZY |
5544 | |
5545 | exit: | |
bb8c093b | 5546 | memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp)); |
b481de9c ZY |
5547 | |
5548 | if (priv->ibss_beacon) | |
5549 | dev_kfree_skb(priv->ibss_beacon); | |
5550 | priv->ibss_beacon = NULL; | |
5551 | ||
5552 | /* clear out any free frames */ | |
bb8c093b | 5553 | iwl4965_clear_free_frames(priv); |
b481de9c ZY |
5554 | } |
5555 | ||
c79dd5b5 | 5556 | static void iwl4965_down(struct iwl_priv *priv) |
b481de9c ZY |
5557 | { |
5558 | mutex_lock(&priv->mutex); | |
bb8c093b | 5559 | __iwl4965_down(priv); |
b481de9c | 5560 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5561 | |
bb8c093b | 5562 | iwl4965_cancel_deferred_work(priv); |
b481de9c ZY |
5563 | } |
5564 | ||
5565 | #define MAX_HW_RESTARTS 5 | |
5566 | ||
c79dd5b5 | 5567 | static int __iwl4965_up(struct iwl_priv *priv) |
b481de9c | 5568 | { |
57aab75a TW |
5569 | int i; |
5570 | int ret; | |
b481de9c ZY |
5571 | |
5572 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5573 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
5574 | return -EIO; | |
5575 | } | |
5576 | ||
5577 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
5578 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
5579 | "parameter)\n"); | |
ad97edd2 | 5580 | iwl_rfkill_set_hw_state(priv); |
e655b9f0 ZY |
5581 | return -ENODEV; |
5582 | } | |
5583 | ||
e903fbd4 RC |
5584 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
5585 | IWL_ERROR("ucode not available for device bringup\n"); | |
5586 | return -EIO; | |
5587 | } | |
5588 | ||
e655b9f0 | 5589 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3395f6e9 | 5590 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
5591 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
5592 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5593 | else { | |
5594 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5595 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
ad97edd2 | 5596 | iwl_rfkill_set_hw_state(priv); |
e655b9f0 ZY |
5597 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); |
5598 | return -ENODEV; | |
5599 | } | |
b481de9c ZY |
5600 | } |
5601 | ||
ad97edd2 | 5602 | iwl_rfkill_set_hw_state(priv); |
3395f6e9 | 5603 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 5604 | |
57aab75a TW |
5605 | ret = priv->cfg->ops->lib->hw_nic_init(priv); |
5606 | if (ret) { | |
5607 | IWL_ERROR("Unable to init nic\n"); | |
5608 | return ret; | |
b481de9c ZY |
5609 | } |
5610 | ||
5611 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
5612 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5613 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
5614 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
5615 | ||
5616 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 5617 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
bb8c093b | 5618 | iwl4965_enable_interrupts(priv); |
b481de9c ZY |
5619 | |
5620 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
5621 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5622 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
5623 | |
5624 | /* Copy original ucode data image from disk into backup cache. | |
5625 | * This will be used to initialize the on-board processor's | |
5626 | * data SRAM for a clean start when the runtime program first loads. */ | |
5627 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 5628 | priv->ucode_data.len); |
b481de9c | 5629 | |
e655b9f0 ZY |
5630 | /* We return success when we resume from suspend and rf_kill is on. */ |
5631 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
b481de9c | 5632 | return 0; |
b481de9c ZY |
5633 | |
5634 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | |
5635 | ||
bf85ea4f | 5636 | iwlcore_clear_stations_table(priv); |
b481de9c ZY |
5637 | |
5638 | /* load bootstrap state machine, | |
5639 | * load bootstrap program into processor's memory, | |
5640 | * prepare to load the "initialize" uCode */ | |
57aab75a | 5641 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 5642 | |
57aab75a TW |
5643 | if (ret) { |
5644 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", ret); | |
b481de9c ZY |
5645 | continue; |
5646 | } | |
5647 | ||
5648 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 5649 | iwl4965_nic_start(priv); |
b481de9c | 5650 | |
b481de9c ZY |
5651 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
5652 | ||
5653 | return 0; | |
5654 | } | |
5655 | ||
5656 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 5657 | __iwl4965_down(priv); |
b481de9c ZY |
5658 | |
5659 | /* tried to restart and config the device for as long as our | |
5660 | * patience could withstand */ | |
5661 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
5662 | return -EIO; | |
5663 | } | |
5664 | ||
5665 | ||
5666 | /***************************************************************************** | |
5667 | * | |
5668 | * Workqueue callbacks | |
5669 | * | |
5670 | *****************************************************************************/ | |
5671 | ||
bb8c093b | 5672 | static void iwl4965_bg_init_alive_start(struct work_struct *data) |
b481de9c | 5673 | { |
c79dd5b5 TW |
5674 | struct iwl_priv *priv = |
5675 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
5676 | |
5677 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5678 | return; | |
5679 | ||
5680 | mutex_lock(&priv->mutex); | |
bb8c093b | 5681 | iwl4965_init_alive_start(priv); |
b481de9c ZY |
5682 | mutex_unlock(&priv->mutex); |
5683 | } | |
5684 | ||
bb8c093b | 5685 | static void iwl4965_bg_alive_start(struct work_struct *data) |
b481de9c | 5686 | { |
c79dd5b5 TW |
5687 | struct iwl_priv *priv = |
5688 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
5689 | |
5690 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5691 | return; | |
5692 | ||
5693 | mutex_lock(&priv->mutex); | |
bb8c093b | 5694 | iwl4965_alive_start(priv); |
b481de9c ZY |
5695 | mutex_unlock(&priv->mutex); |
5696 | } | |
5697 | ||
bb8c093b | 5698 | static void iwl4965_bg_rf_kill(struct work_struct *work) |
b481de9c | 5699 | { |
c79dd5b5 | 5700 | struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill); |
b481de9c ZY |
5701 | |
5702 | wake_up_interruptible(&priv->wait_command_queue); | |
5703 | ||
5704 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5705 | return; | |
5706 | ||
5707 | mutex_lock(&priv->mutex); | |
5708 | ||
fee1247a | 5709 | if (!iwl_is_rfkill(priv)) { |
b481de9c ZY |
5710 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
5711 | "HW and/or SW RF Kill no longer active, restarting " | |
5712 | "device\n"); | |
5713 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5714 | queue_work(priv->workqueue, &priv->restart); | |
5715 | } else { | |
ad97edd2 MA |
5716 | /* make sure mac80211 stop sending Tx frame */ |
5717 | if (priv->mac80211_registered) | |
5718 | ieee80211_stop_queues(priv->hw); | |
b481de9c ZY |
5719 | |
5720 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5721 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
5722 | "disabled by SW switch\n"); | |
5723 | else | |
5724 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
5725 | "Kill switch must be turned off for " | |
5726 | "wireless networking to work.\n"); | |
5727 | } | |
ad97edd2 MA |
5728 | iwl_rfkill_set_hw_state(priv); |
5729 | ||
b481de9c ZY |
5730 | mutex_unlock(&priv->mutex); |
5731 | } | |
5732 | ||
5733 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) | |
5734 | ||
bb8c093b | 5735 | static void iwl4965_bg_scan_check(struct work_struct *data) |
b481de9c | 5736 | { |
c79dd5b5 TW |
5737 | struct iwl_priv *priv = |
5738 | container_of(data, struct iwl_priv, scan_check.work); | |
b481de9c ZY |
5739 | |
5740 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5741 | return; | |
5742 | ||
5743 | mutex_lock(&priv->mutex); | |
5744 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
5745 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5746 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
5747 | "Scan completion watchdog resetting adapter (%dms)\n", | |
5748 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
052c4b9f | 5749 | |
b481de9c | 5750 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 5751 | iwl4965_send_scan_abort(priv); |
b481de9c ZY |
5752 | } |
5753 | mutex_unlock(&priv->mutex); | |
5754 | } | |
5755 | ||
bb8c093b | 5756 | static void iwl4965_bg_request_scan(struct work_struct *data) |
b481de9c | 5757 | { |
c79dd5b5 TW |
5758 | struct iwl_priv *priv = |
5759 | container_of(data, struct iwl_priv, request_scan); | |
857485c0 | 5760 | struct iwl_host_cmd cmd = { |
b481de9c | 5761 | .id = REPLY_SCAN_CMD, |
bb8c093b | 5762 | .len = sizeof(struct iwl4965_scan_cmd), |
b481de9c ZY |
5763 | .meta.flags = CMD_SIZE_HUGE, |
5764 | }; | |
bb8c093b | 5765 | struct iwl4965_scan_cmd *scan; |
b481de9c | 5766 | struct ieee80211_conf *conf = NULL; |
78330fdd | 5767 | u16 cmd_len; |
8318d78a | 5768 | enum ieee80211_band band; |
78330fdd | 5769 | u8 direct_mask; |
857485c0 | 5770 | int ret = 0; |
b481de9c ZY |
5771 | |
5772 | conf = ieee80211_get_hw_conf(priv->hw); | |
5773 | ||
5774 | mutex_lock(&priv->mutex); | |
5775 | ||
fee1247a | 5776 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
5777 | IWL_WARNING("request scan called when driver not ready.\n"); |
5778 | goto done; | |
5779 | } | |
5780 | ||
5781 | /* Make sure the scan wasn't cancelled before this queued work | |
5782 | * was given the chance to run... */ | |
5783 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
5784 | goto done; | |
5785 | ||
5786 | /* This should never be called or scheduled if there is currently | |
5787 | * a scan active in the hardware. */ | |
5788 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
5789 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
5790 | "Ignoring second request.\n"); | |
857485c0 | 5791 | ret = -EIO; |
b481de9c ZY |
5792 | goto done; |
5793 | } | |
5794 | ||
5795 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5796 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
5797 | goto done; | |
5798 | } | |
5799 | ||
5800 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5801 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
5802 | goto done; | |
5803 | } | |
5804 | ||
fee1247a | 5805 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
5806 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
5807 | goto done; | |
5808 | } | |
5809 | ||
5810 | if (!test_bit(STATUS_READY, &priv->status)) { | |
5811 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
5812 | goto done; | |
5813 | } | |
5814 | ||
5815 | if (!priv->scan_bands) { | |
5816 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
5817 | goto done; | |
5818 | } | |
5819 | ||
5820 | if (!priv->scan) { | |
bb8c093b | 5821 | priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) + |
b481de9c ZY |
5822 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
5823 | if (!priv->scan) { | |
857485c0 | 5824 | ret = -ENOMEM; |
b481de9c ZY |
5825 | goto done; |
5826 | } | |
5827 | } | |
5828 | scan = priv->scan; | |
bb8c093b | 5829 | memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
5830 | |
5831 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
5832 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
5833 | ||
3109ece1 | 5834 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
5835 | u16 interval = 0; |
5836 | u32 extra; | |
5837 | u32 suspend_time = 100; | |
5838 | u32 scan_suspend_time = 100; | |
5839 | unsigned long flags; | |
5840 | ||
5841 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
5842 | ||
5843 | spin_lock_irqsave(&priv->lock, flags); | |
5844 | interval = priv->beacon_int; | |
5845 | spin_unlock_irqrestore(&priv->lock, flags); | |
5846 | ||
5847 | scan->suspend_time = 0; | |
052c4b9f | 5848 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
5849 | if (!interval) |
5850 | interval = suspend_time; | |
5851 | ||
5852 | extra = (suspend_time / interval) << 22; | |
5853 | scan_suspend_time = (extra | | |
5854 | ((suspend_time % interval) * 1024)); | |
5855 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
5856 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
5857 | scan_suspend_time, interval); | |
5858 | } | |
5859 | ||
5860 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
5861 | if (priv->one_direct_scan) { | |
5862 | IWL_DEBUG_SCAN | |
5863 | ("Kicking off one direct scan for '%s'\n", | |
bb8c093b | 5864 | iwl4965_escape_essid(priv->direct_ssid, |
b481de9c ZY |
5865 | priv->direct_ssid_len)); |
5866 | scan->direct_scan[0].id = WLAN_EID_SSID; | |
5867 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
5868 | memcpy(scan->direct_scan[0].ssid, | |
5869 | priv->direct_ssid, priv->direct_ssid_len); | |
5870 | direct_mask = 1; | |
3109ece1 | 5871 | } else if (!iwl_is_associated(priv) && priv->essid_len) { |
b481de9c ZY |
5872 | scan->direct_scan[0].id = WLAN_EID_SSID; |
5873 | scan->direct_scan[0].len = priv->essid_len; | |
5874 | memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len); | |
5875 | direct_mask = 1; | |
857485c0 | 5876 | } else { |
b481de9c | 5877 | direct_mask = 0; |
857485c0 | 5878 | } |
b481de9c | 5879 | |
b481de9c ZY |
5880 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
5881 | scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id; | |
5882 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
5883 | ||
b481de9c ZY |
5884 | |
5885 | switch (priv->scan_bands) { | |
5886 | case 2: | |
5887 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
5888 | scan->tx_cmd.rate_n_flags = | |
bb8c093b | 5889 | iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP, |
b481de9c ZY |
5890 | RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK); |
5891 | ||
5892 | scan->good_CRC_th = 0; | |
8318d78a | 5893 | band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
5894 | break; |
5895 | ||
5896 | case 1: | |
5897 | scan->tx_cmd.rate_n_flags = | |
bb8c093b | 5898 | iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP, |
b481de9c ZY |
5899 | RATE_MCS_ANT_B_MSK); |
5900 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 5901 | band = IEEE80211_BAND_5GHZ; |
b481de9c ZY |
5902 | break; |
5903 | ||
5904 | default: | |
5905 | IWL_WARNING("Invalid scan band count\n"); | |
5906 | goto done; | |
5907 | } | |
5908 | ||
78330fdd TW |
5909 | /* We don't build a direct scan probe request; the uCode will do |
5910 | * that based on the direct_mask added to each channel entry */ | |
5911 | cmd_len = iwl4965_fill_probe_req(priv, band, | |
5912 | (struct ieee80211_mgmt *)scan->data, | |
5913 | IWL_MAX_SCAN_SIZE - sizeof(*scan), 0); | |
5914 | ||
5915 | scan->tx_cmd.len = cpu_to_le16(cmd_len); | |
b481de9c ZY |
5916 | /* select Rx chains */ |
5917 | ||
5918 | /* Force use of chains B and C (0x6) for scan Rx. | |
5919 | * Avoid A (0x1) because of its off-channel reception on A-band. | |
5920 | * MIMO is not used here, but value is required to make uCode happy. */ | |
5921 | scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK | | |
5922 | cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) | | |
5923 | (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) | | |
5924 | (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS)); | |
5925 | ||
5926 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) | |
5927 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; | |
5928 | ||
26c0f03f | 5929 | if (direct_mask) { |
b481de9c ZY |
5930 | IWL_DEBUG_SCAN |
5931 | ("Initiating direct scan for %s.\n", | |
bb8c093b | 5932 | iwl4965_escape_essid(priv->essid, priv->essid_len)); |
26c0f03f RC |
5933 | scan->channel_count = |
5934 | iwl4965_get_channels_for_scan( | |
5935 | priv, band, 1, /* active */ | |
5936 | direct_mask, | |
5937 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
5938 | } else { | |
b481de9c | 5939 | IWL_DEBUG_SCAN("Initiating indirect scan.\n"); |
26c0f03f RC |
5940 | scan->channel_count = |
5941 | iwl4965_get_channels_for_scan( | |
5942 | priv, band, 0, /* passive */ | |
5943 | direct_mask, | |
5944 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
5945 | } | |
b481de9c ZY |
5946 | |
5947 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + | |
bb8c093b | 5948 | scan->channel_count * sizeof(struct iwl4965_scan_channel); |
b481de9c ZY |
5949 | cmd.data = scan; |
5950 | scan->len = cpu_to_le16(cmd.len); | |
5951 | ||
5952 | set_bit(STATUS_SCAN_HW, &priv->status); | |
857485c0 TW |
5953 | ret = iwl_send_cmd_sync(priv, &cmd); |
5954 | if (ret) | |
b481de9c ZY |
5955 | goto done; |
5956 | ||
5957 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
5958 | IWL_SCAN_CHECK_WATCHDOG); | |
5959 | ||
5960 | mutex_unlock(&priv->mutex); | |
5961 | return; | |
5962 | ||
5963 | done: | |
01ebd063 | 5964 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
5965 | queue_work(priv->workqueue, &priv->scan_completed); |
5966 | mutex_unlock(&priv->mutex); | |
5967 | } | |
5968 | ||
bb8c093b | 5969 | static void iwl4965_bg_up(struct work_struct *data) |
b481de9c | 5970 | { |
c79dd5b5 | 5971 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
5972 | |
5973 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5974 | return; | |
5975 | ||
5976 | mutex_lock(&priv->mutex); | |
bb8c093b | 5977 | __iwl4965_up(priv); |
b481de9c ZY |
5978 | mutex_unlock(&priv->mutex); |
5979 | } | |
5980 | ||
bb8c093b | 5981 | static void iwl4965_bg_restart(struct work_struct *data) |
b481de9c | 5982 | { |
c79dd5b5 | 5983 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
5984 | |
5985 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5986 | return; | |
5987 | ||
bb8c093b | 5988 | iwl4965_down(priv); |
b481de9c ZY |
5989 | queue_work(priv->workqueue, &priv->up); |
5990 | } | |
5991 | ||
bb8c093b | 5992 | static void iwl4965_bg_rx_replenish(struct work_struct *data) |
b481de9c | 5993 | { |
c79dd5b5 TW |
5994 | struct iwl_priv *priv = |
5995 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
5996 | |
5997 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5998 | return; | |
5999 | ||
6000 | mutex_lock(&priv->mutex); | |
bb8c093b | 6001 | iwl4965_rx_replenish(priv); |
b481de9c ZY |
6002 | mutex_unlock(&priv->mutex); |
6003 | } | |
6004 | ||
7878a5a4 MA |
6005 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
6006 | ||
508e32e1 | 6007 | static void iwl4965_post_associate(struct iwl_priv *priv) |
b481de9c | 6008 | { |
b481de9c | 6009 | struct ieee80211_conf *conf = NULL; |
857485c0 | 6010 | int ret = 0; |
0795af57 | 6011 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6012 | |
6013 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6014 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | |
6015 | return; | |
6016 | } | |
6017 | ||
0795af57 JP |
6018 | IWL_DEBUG_ASSOC("Associated as %d to: %s\n", |
6019 | priv->assoc_id, | |
6020 | print_mac(mac, priv->active_rxon.bssid_addr)); | |
b481de9c ZY |
6021 | |
6022 | ||
6023 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6024 | return; | |
6025 | ||
b481de9c | 6026 | |
508e32e1 | 6027 | if (!priv->vif || !priv->is_open) |
948c171c | 6028 | return; |
508e32e1 | 6029 | |
bb8c093b | 6030 | iwl4965_scan_cancel_timeout(priv, 200); |
052c4b9f | 6031 | |
b481de9c ZY |
6032 | conf = ieee80211_get_hw_conf(priv->hw); |
6033 | ||
6034 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6035 | iwl4965_commit_rxon(priv); |
b481de9c | 6036 | |
bb8c093b CH |
6037 | memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd)); |
6038 | iwl4965_setup_rxon_timing(priv); | |
857485c0 | 6039 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 6040 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 6041 | if (ret) |
b481de9c ZY |
6042 | IWL_WARNING("REPLY_RXON_TIMING failed - " |
6043 | "Attempting to continue.\n"); | |
6044 | ||
6045 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
6046 | ||
c8b0e6e1 | 6047 | #ifdef CONFIG_IWL4965_HT |
fd105e79 RR |
6048 | if (priv->current_ht_config.is_ht) |
6049 | iwl4965_set_rxon_ht(priv, &priv->current_ht_config); | |
c8b0e6e1 | 6050 | #endif /* CONFIG_IWL4965_HT*/ |
b481de9c ZY |
6051 | iwl4965_set_rxon_chain(priv); |
6052 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6053 | ||
6054 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6055 | priv->assoc_id, priv->beacon_int); | |
6056 | ||
6057 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6058 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6059 | else | |
6060 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6061 | ||
6062 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6063 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6064 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
6065 | else | |
6066 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6067 | ||
6068 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6069 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6070 | ||
6071 | } | |
6072 | ||
bb8c093b | 6073 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6074 | |
6075 | switch (priv->iw_mode) { | |
6076 | case IEEE80211_IF_TYPE_STA: | |
bb8c093b | 6077 | iwl4965_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6078 | break; |
6079 | ||
6080 | case IEEE80211_IF_TYPE_IBSS: | |
6081 | ||
6082 | /* clear out the station table */ | |
bf85ea4f | 6083 | iwlcore_clear_stations_table(priv); |
b481de9c | 6084 | |
bb8c093b CH |
6085 | iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); |
6086 | iwl4965_rxon_add_station(priv, priv->bssid, 0); | |
6087 | iwl4965_rate_scale_init(priv->hw, IWL_STA_ID); | |
6088 | iwl4965_send_beacon_cmd(priv); | |
b481de9c ZY |
6089 | |
6090 | break; | |
6091 | ||
6092 | default: | |
6093 | IWL_ERROR("%s Should not be called in %d mode\n", | |
6094 | __FUNCTION__, priv->iw_mode); | |
6095 | break; | |
6096 | } | |
6097 | ||
bb8c093b | 6098 | iwl4965_sequence_reset(priv); |
b481de9c | 6099 | |
c8b0e6e1 | 6100 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
6101 | /* Enable Rx differential gain and sensitivity calibrations */ |
6102 | iwl4965_chain_noise_reset(priv); | |
6103 | priv->start_calib = 1; | |
c8b0e6e1 | 6104 | #endif /* CONFIG_IWL4965_SENSITIVITY */ |
b481de9c ZY |
6105 | |
6106 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6107 | priv->assoc_station_added = 1; | |
6108 | ||
bb8c093b | 6109 | iwl4965_activate_qos(priv, 0); |
292ae174 | 6110 | |
7878a5a4 MA |
6111 | /* we have just associated, don't start scan too early */ |
6112 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
508e32e1 RC |
6113 | } |
6114 | ||
6115 | ||
6116 | static void iwl4965_bg_post_associate(struct work_struct *data) | |
6117 | { | |
6118 | struct iwl_priv *priv = container_of(data, struct iwl_priv, | |
6119 | post_associate.work); | |
6120 | ||
6121 | mutex_lock(&priv->mutex); | |
6122 | iwl4965_post_associate(priv); | |
b481de9c | 6123 | mutex_unlock(&priv->mutex); |
508e32e1 | 6124 | |
b481de9c ZY |
6125 | } |
6126 | ||
bb8c093b | 6127 | static void iwl4965_bg_abort_scan(struct work_struct *work) |
b481de9c | 6128 | { |
c79dd5b5 | 6129 | struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan); |
b481de9c | 6130 | |
fee1247a | 6131 | if (!iwl_is_ready(priv)) |
b481de9c ZY |
6132 | return; |
6133 | ||
6134 | mutex_lock(&priv->mutex); | |
6135 | ||
6136 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6137 | iwl4965_send_scan_abort(priv); |
b481de9c ZY |
6138 | |
6139 | mutex_unlock(&priv->mutex); | |
6140 | } | |
6141 | ||
76bb77e0 ZY |
6142 | static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); |
6143 | ||
bb8c093b | 6144 | static void iwl4965_bg_scan_completed(struct work_struct *work) |
b481de9c | 6145 | { |
c79dd5b5 TW |
6146 | struct iwl_priv *priv = |
6147 | container_of(work, struct iwl_priv, scan_completed); | |
b481de9c ZY |
6148 | |
6149 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6150 | ||
6151 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6152 | return; | |
6153 | ||
a0646470 ZY |
6154 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
6155 | iwl4965_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw)); | |
76bb77e0 | 6156 | |
b481de9c ZY |
6157 | ieee80211_scan_completed(priv->hw); |
6158 | ||
6159 | /* Since setting the TXPOWER may have been deferred while | |
6160 | * performing the scan, fire one off */ | |
6161 | mutex_lock(&priv->mutex); | |
bb8c093b | 6162 | iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
6163 | mutex_unlock(&priv->mutex); |
6164 | } | |
6165 | ||
6166 | /***************************************************************************** | |
6167 | * | |
6168 | * mac80211 entry point functions | |
6169 | * | |
6170 | *****************************************************************************/ | |
6171 | ||
5a66926a ZY |
6172 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6173 | ||
bb8c093b | 6174 | static int iwl4965_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6175 | { |
c79dd5b5 | 6176 | struct iwl_priv *priv = hw->priv; |
5a66926a | 6177 | int ret; |
b481de9c ZY |
6178 | |
6179 | IWL_DEBUG_MAC80211("enter\n"); | |
6180 | ||
5a66926a ZY |
6181 | if (pci_enable_device(priv->pci_dev)) { |
6182 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6183 | return -ENODEV; | |
6184 | } | |
6185 | pci_restore_state(priv->pci_dev); | |
6186 | pci_enable_msi(priv->pci_dev); | |
6187 | ||
6188 | ret = request_irq(priv->pci_dev->irq, iwl4965_isr, IRQF_SHARED, | |
6189 | DRV_NAME, priv); | |
6190 | if (ret) { | |
6191 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6192 | goto out_disable_msi; | |
6193 | } | |
6194 | ||
b481de9c ZY |
6195 | /* we should be verifying the device is ready to be opened */ |
6196 | mutex_lock(&priv->mutex); | |
6197 | ||
5a66926a ZY |
6198 | memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd)); |
6199 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
6200 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 6201 | |
5a66926a ZY |
6202 | if (!priv->ucode_code.len) { |
6203 | ret = iwl4965_read_ucode(priv); | |
6204 | if (ret) { | |
6205 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6206 | mutex_unlock(&priv->mutex); | |
6207 | goto out_release_irq; | |
6208 | } | |
6209 | } | |
b481de9c | 6210 | |
e655b9f0 | 6211 | ret = __iwl4965_up(priv); |
5a66926a | 6212 | |
b481de9c | 6213 | mutex_unlock(&priv->mutex); |
5a66926a | 6214 | |
e655b9f0 ZY |
6215 | if (ret) |
6216 | goto out_release_irq; | |
6217 | ||
6218 | IWL_DEBUG_INFO("Start UP work done.\n"); | |
6219 | ||
6220 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6221 | return 0; | |
6222 | ||
5a66926a ZY |
6223 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6224 | * mac80211 will not be run successfully. */ | |
6225 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6226 | test_bit(STATUS_READY, &priv->status), | |
6227 | UCODE_READY_TIMEOUT); | |
6228 | if (!ret) { | |
6229 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6230 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6231 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6232 | ret = -ETIMEDOUT; | |
6233 | goto out_release_irq; | |
6234 | } | |
6235 | } | |
6236 | ||
e655b9f0 | 6237 | priv->is_open = 1; |
b481de9c ZY |
6238 | IWL_DEBUG_MAC80211("leave\n"); |
6239 | return 0; | |
5a66926a ZY |
6240 | |
6241 | out_release_irq: | |
6242 | free_irq(priv->pci_dev->irq, priv); | |
6243 | out_disable_msi: | |
6244 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6245 | pci_disable_device(priv->pci_dev); |
6246 | priv->is_open = 0; | |
6247 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6248 | return ret; |
b481de9c ZY |
6249 | } |
6250 | ||
bb8c093b | 6251 | static void iwl4965_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6252 | { |
c79dd5b5 | 6253 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6254 | |
6255 | IWL_DEBUG_MAC80211("enter\n"); | |
948c171c | 6256 | |
e655b9f0 ZY |
6257 | if (!priv->is_open) { |
6258 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6259 | return; | |
6260 | } | |
6261 | ||
b481de9c | 6262 | priv->is_open = 0; |
5a66926a | 6263 | |
fee1247a | 6264 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
6265 | /* stop mac, cancel any scan request and clear |
6266 | * RXON_FILTER_ASSOC_MSK BIT | |
6267 | */ | |
5a66926a ZY |
6268 | mutex_lock(&priv->mutex); |
6269 | iwl4965_scan_cancel_timeout(priv, 100); | |
6270 | cancel_delayed_work(&priv->post_associate); | |
fde3571f | 6271 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6272 | } |
6273 | ||
5a66926a ZY |
6274 | iwl4965_down(priv); |
6275 | ||
6276 | flush_workqueue(priv->workqueue); | |
6277 | free_irq(priv->pci_dev->irq, priv); | |
6278 | pci_disable_msi(priv->pci_dev); | |
6279 | pci_save_state(priv->pci_dev); | |
6280 | pci_disable_device(priv->pci_dev); | |
948c171c | 6281 | |
b481de9c | 6282 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6283 | } |
6284 | ||
bb8c093b | 6285 | static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
6286 | struct ieee80211_tx_control *ctl) |
6287 | { | |
c79dd5b5 | 6288 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6289 | |
6290 | IWL_DEBUG_MAC80211("enter\n"); | |
6291 | ||
6292 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | |
6293 | IWL_DEBUG_MAC80211("leave - monitor\n"); | |
6294 | return -1; | |
6295 | } | |
6296 | ||
6297 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | |
8318d78a | 6298 | ctl->tx_rate->bitrate); |
b481de9c | 6299 | |
bb8c093b | 6300 | if (iwl4965_tx_skb(priv, skb, ctl)) |
b481de9c ZY |
6301 | dev_kfree_skb_any(skb); |
6302 | ||
6303 | IWL_DEBUG_MAC80211("leave\n"); | |
6304 | return 0; | |
6305 | } | |
6306 | ||
bb8c093b | 6307 | static int iwl4965_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6308 | struct ieee80211_if_init_conf *conf) |
6309 | { | |
c79dd5b5 | 6310 | struct iwl_priv *priv = hw->priv; |
b481de9c | 6311 | unsigned long flags; |
0795af57 | 6312 | DECLARE_MAC_BUF(mac); |
b481de9c | 6313 | |
32bfd35d | 6314 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6315 | |
32bfd35d JB |
6316 | if (priv->vif) { |
6317 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
75849d28 | 6318 | return -EOPNOTSUPP; |
b481de9c ZY |
6319 | } |
6320 | ||
6321 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6322 | priv->vif = conf->vif; |
b481de9c ZY |
6323 | |
6324 | spin_unlock_irqrestore(&priv->lock, flags); | |
6325 | ||
6326 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6327 | |
6328 | if (conf->mac_addr) { | |
6329 | IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr)); | |
6330 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
6331 | } | |
b481de9c | 6332 | |
fee1247a | 6333 | if (iwl_is_ready(priv)) |
5a66926a ZY |
6334 | iwl4965_set_mode(priv, conf->type); |
6335 | ||
b481de9c ZY |
6336 | mutex_unlock(&priv->mutex); |
6337 | ||
5a66926a | 6338 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6339 | return 0; |
6340 | } | |
6341 | ||
6342 | /** | |
bb8c093b | 6343 | * iwl4965_mac_config - mac80211 config callback |
b481de9c ZY |
6344 | * |
6345 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6346 | * be set inappropriately and the driver currently sets the hardware up to | |
6347 | * use it whenever needed. | |
6348 | */ | |
bb8c093b | 6349 | static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
b481de9c | 6350 | { |
c79dd5b5 | 6351 | struct iwl_priv *priv = hw->priv; |
bf85ea4f | 6352 | const struct iwl_channel_info *ch_info; |
b481de9c | 6353 | unsigned long flags; |
76bb77e0 | 6354 | int ret = 0; |
b481de9c ZY |
6355 | |
6356 | mutex_lock(&priv->mutex); | |
8318d78a | 6357 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6358 | |
12342c47 ZY |
6359 | priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP); |
6360 | ||
fee1247a | 6361 | if (!iwl_is_ready(priv)) { |
b481de9c | 6362 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6363 | ret = -EIO; |
6364 | goto out; | |
b481de9c ZY |
6365 | } |
6366 | ||
1ea87396 | 6367 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && |
b481de9c | 6368 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6369 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6370 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6371 | mutex_unlock(&priv->mutex); |
a0646470 | 6372 | return 0; |
b481de9c ZY |
6373 | } |
6374 | ||
6375 | spin_lock_irqsave(&priv->lock, flags); | |
6376 | ||
8622e705 | 6377 | ch_info = iwl_get_channel_info(priv, conf->channel->band, |
8318d78a | 6378 | ieee80211_frequency_to_channel(conf->channel->center_freq)); |
b481de9c | 6379 | if (!is_channel_valid(ch_info)) { |
b481de9c ZY |
6380 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6381 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6382 | ret = -EINVAL; |
6383 | goto out; | |
b481de9c ZY |
6384 | } |
6385 | ||
c8b0e6e1 | 6386 | #ifdef CONFIG_IWL4965_HT |
78330fdd | 6387 | /* if we are switching from ht to 2.4 clear flags |
b481de9c ZY |
6388 | * from any ht related info since 2.4 does not |
6389 | * support ht */ | |
78330fdd | 6390 | if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel->hw_value) |
b481de9c ZY |
6391 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH |
6392 | && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) | |
6393 | #endif | |
6394 | ) | |
6395 | priv->staging_rxon.flags = 0; | |
c8b0e6e1 | 6396 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 6397 | |
bf85ea4f | 6398 | iwlcore_set_rxon_channel(priv, conf->channel->band, |
8318d78a | 6399 | ieee80211_frequency_to_channel(conf->channel->center_freq)); |
b481de9c | 6400 | |
8318d78a | 6401 | iwl4965_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6402 | |
6403 | /* The list of supported rates and rate mask can be different | |
8318d78a | 6404 | * for each band; since the band may have changed, reset |
b481de9c | 6405 | * the rate mask to what mac80211 lists */ |
bb8c093b | 6406 | iwl4965_set_rate(priv); |
b481de9c ZY |
6407 | |
6408 | spin_unlock_irqrestore(&priv->lock, flags); | |
6409 | ||
6410 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6411 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6412 | iwl4965_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6413 | goto out; |
b481de9c ZY |
6414 | } |
6415 | #endif | |
6416 | ||
ad97edd2 MA |
6417 | if (priv->cfg->ops->lib->radio_kill_sw) |
6418 | priv->cfg->ops->lib->radio_kill_sw(priv, !conf->radio_enabled); | |
b481de9c ZY |
6419 | |
6420 | if (!conf->radio_enabled) { | |
6421 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6422 | goto out; |
b481de9c ZY |
6423 | } |
6424 | ||
fee1247a | 6425 | if (iwl_is_rfkill(priv)) { |
b481de9c | 6426 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6427 | ret = -EIO; |
6428 | goto out; | |
b481de9c ZY |
6429 | } |
6430 | ||
bb8c093b | 6431 | iwl4965_set_rate(priv); |
b481de9c ZY |
6432 | |
6433 | if (memcmp(&priv->active_rxon, | |
6434 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
bb8c093b | 6435 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6436 | else |
6437 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6438 | ||
6439 | IWL_DEBUG_MAC80211("leave\n"); | |
6440 | ||
a0646470 ZY |
6441 | out: |
6442 | clear_bit(STATUS_CONF_PENDING, &priv->status); | |
5a66926a | 6443 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6444 | return ret; |
b481de9c ZY |
6445 | } |
6446 | ||
c79dd5b5 | 6447 | static void iwl4965_config_ap(struct iwl_priv *priv) |
b481de9c | 6448 | { |
857485c0 | 6449 | int ret = 0; |
b481de9c | 6450 | |
d986bcd1 | 6451 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6452 | return; |
6453 | ||
6454 | /* The following should be done only at AP bring up */ | |
6455 | if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { | |
6456 | ||
6457 | /* RXON - unassoc (to set timing command) */ | |
6458 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6459 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6460 | |
6461 | /* RXON Timing */ | |
bb8c093b CH |
6462 | memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd)); |
6463 | iwl4965_setup_rxon_timing(priv); | |
857485c0 | 6464 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 6465 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 6466 | if (ret) |
b481de9c ZY |
6467 | IWL_WARNING("REPLY_RXON_TIMING failed - " |
6468 | "Attempting to continue.\n"); | |
6469 | ||
6470 | iwl4965_set_rxon_chain(priv); | |
6471 | ||
6472 | /* FIXME: what should be the assoc_id for AP? */ | |
6473 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6474 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6475 | priv->staging_rxon.flags |= | |
6476 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
6477 | else | |
6478 | priv->staging_rxon.flags &= | |
6479 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6480 | ||
6481 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6482 | if (priv->assoc_capability & | |
6483 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6484 | priv->staging_rxon.flags |= | |
6485 | RXON_FLG_SHORT_SLOT_MSK; | |
6486 | else | |
6487 | priv->staging_rxon.flags &= | |
6488 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6489 | ||
6490 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6491 | priv->staging_rxon.flags &= | |
6492 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6493 | } | |
6494 | /* restore RXON assoc */ | |
6495 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6496 | iwl4965_commit_rxon(priv); |
bb8c093b | 6497 | iwl4965_activate_qos(priv, 1); |
bb8c093b | 6498 | iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0); |
e1493deb | 6499 | } |
bb8c093b | 6500 | iwl4965_send_beacon_cmd(priv); |
b481de9c ZY |
6501 | |
6502 | /* FIXME - we need to add code here to detect a totally new | |
6503 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6504 | * clear sta table, add BCAST sta... */ | |
6505 | } | |
6506 | ||
32bfd35d JB |
6507 | static int iwl4965_mac_config_interface(struct ieee80211_hw *hw, |
6508 | struct ieee80211_vif *vif, | |
b481de9c ZY |
6509 | struct ieee80211_if_conf *conf) |
6510 | { | |
c79dd5b5 | 6511 | struct iwl_priv *priv = hw->priv; |
0795af57 | 6512 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6513 | unsigned long flags; |
6514 | int rc; | |
6515 | ||
6516 | if (conf == NULL) | |
6517 | return -EIO; | |
6518 | ||
b716bb91 EG |
6519 | if (priv->vif != vif) { |
6520 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
6521 | mutex_unlock(&priv->mutex); | |
6522 | return 0; | |
6523 | } | |
6524 | ||
b481de9c ZY |
6525 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && |
6526 | (!conf->beacon || !conf->ssid_len)) { | |
6527 | IWL_DEBUG_MAC80211 | |
6528 | ("Leaving in AP mode because HostAPD is not ready.\n"); | |
6529 | return 0; | |
6530 | } | |
6531 | ||
fee1247a | 6532 | if (!iwl_is_alive(priv)) |
5a66926a ZY |
6533 | return -EAGAIN; |
6534 | ||
b481de9c ZY |
6535 | mutex_lock(&priv->mutex); |
6536 | ||
b481de9c | 6537 | if (conf->bssid) |
0795af57 JP |
6538 | IWL_DEBUG_MAC80211("bssid: %s\n", |
6539 | print_mac(mac, conf->bssid)); | |
b481de9c | 6540 | |
4150c572 JB |
6541 | /* |
6542 | * very dubious code was here; the probe filtering flag is never set: | |
6543 | * | |
b481de9c ZY |
6544 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6545 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6546 | */ |
b481de9c ZY |
6547 | |
6548 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6549 | if (!conf->bssid) { | |
6550 | conf->bssid = priv->mac_addr; | |
6551 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
0795af57 JP |
6552 | IWL_DEBUG_MAC80211("bssid was set to: %s\n", |
6553 | print_mac(mac, conf->bssid)); | |
b481de9c ZY |
6554 | } |
6555 | if (priv->ibss_beacon) | |
6556 | dev_kfree_skb(priv->ibss_beacon); | |
6557 | ||
6558 | priv->ibss_beacon = conf->beacon; | |
6559 | } | |
6560 | ||
fee1247a | 6561 | if (iwl_is_rfkill(priv)) |
fde3571f MA |
6562 | goto done; |
6563 | ||
b481de9c ZY |
6564 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6565 | !is_multicast_ether_addr(conf->bssid)) { | |
6566 | /* If there is currently a HW scan going on in the background | |
6567 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 6568 | if (iwl4965_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
6569 | IWL_WARNING("Aborted scan still in progress " |
6570 | "after 100ms\n"); | |
6571 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6572 | mutex_unlock(&priv->mutex); | |
6573 | return -EAGAIN; | |
6574 | } | |
6575 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
6576 | ||
6577 | /* TODO: Audit driver for usage of these members and see | |
6578 | * if mac80211 deprecates them (priv->bssid looks like it | |
6579 | * shouldn't be there, but I haven't scanned the IBSS code | |
6580 | * to verify) - jpk */ | |
6581 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6582 | ||
6583 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 6584 | iwl4965_config_ap(priv); |
b481de9c | 6585 | else { |
bb8c093b | 6586 | rc = iwl4965_commit_rxon(priv); |
b481de9c | 6587 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc) |
bb8c093b | 6588 | iwl4965_rxon_add_station( |
b481de9c ZY |
6589 | priv, priv->active_rxon.bssid_addr, 1); |
6590 | } | |
6591 | ||
6592 | } else { | |
bb8c093b | 6593 | iwl4965_scan_cancel_timeout(priv, 100); |
b481de9c | 6594 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6595 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
6596 | } |
6597 | ||
fde3571f | 6598 | done: |
b481de9c ZY |
6599 | spin_lock_irqsave(&priv->lock, flags); |
6600 | if (!conf->ssid_len) | |
6601 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6602 | else | |
6603 | memcpy(priv->essid, conf->ssid, conf->ssid_len); | |
6604 | ||
6605 | priv->essid_len = conf->ssid_len; | |
6606 | spin_unlock_irqrestore(&priv->lock, flags); | |
6607 | ||
6608 | IWL_DEBUG_MAC80211("leave\n"); | |
6609 | mutex_unlock(&priv->mutex); | |
6610 | ||
6611 | return 0; | |
6612 | } | |
6613 | ||
bb8c093b | 6614 | static void iwl4965_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
6615 | unsigned int changed_flags, |
6616 | unsigned int *total_flags, | |
6617 | int mc_count, struct dev_addr_list *mc_list) | |
6618 | { | |
6619 | /* | |
6620 | * XXX: dummy | |
bb8c093b | 6621 | * see also iwl4965_connection_init_rx_config |
4150c572 JB |
6622 | */ |
6623 | *total_flags = 0; | |
6624 | } | |
6625 | ||
bb8c093b | 6626 | static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6627 | struct ieee80211_if_init_conf *conf) |
6628 | { | |
c79dd5b5 | 6629 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6630 | |
6631 | IWL_DEBUG_MAC80211("enter\n"); | |
6632 | ||
6633 | mutex_lock(&priv->mutex); | |
948c171c | 6634 | |
fee1247a | 6635 | if (iwl_is_ready_rf(priv)) { |
fde3571f MA |
6636 | iwl4965_scan_cancel_timeout(priv, 100); |
6637 | cancel_delayed_work(&priv->post_associate); | |
6638 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
6639 | iwl4965_commit_rxon(priv); | |
6640 | } | |
32bfd35d JB |
6641 | if (priv->vif == conf->vif) { |
6642 | priv->vif = NULL; | |
b481de9c ZY |
6643 | memset(priv->bssid, 0, ETH_ALEN); |
6644 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6645 | priv->essid_len = 0; | |
6646 | } | |
6647 | mutex_unlock(&priv->mutex); | |
6648 | ||
6649 | IWL_DEBUG_MAC80211("leave\n"); | |
6650 | ||
6651 | } | |
471b3efd | 6652 | |
98952d5d TW |
6653 | |
6654 | #ifdef CONFIG_IWL4965_HT | |
6655 | static void iwl4965_ht_conf(struct iwl_priv *priv, | |
6656 | struct ieee80211_bss_conf *bss_conf) | |
6657 | { | |
6658 | struct ieee80211_ht_info *ht_conf = bss_conf->ht_conf; | |
6659 | struct ieee80211_ht_bss_info *ht_bss_conf = bss_conf->ht_bss_conf; | |
6660 | struct iwl_ht_info *iwl_conf = &priv->current_ht_config; | |
6661 | ||
6662 | IWL_DEBUG_MAC80211("enter: \n"); | |
6663 | ||
6664 | iwl_conf->is_ht = bss_conf->assoc_ht; | |
6665 | ||
6666 | if (!iwl_conf->is_ht) | |
6667 | return; | |
6668 | ||
6669 | priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2); | |
6670 | ||
6671 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20) | |
6672 | iwl_conf->sgf |= 0x1; | |
6673 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40) | |
6674 | iwl_conf->sgf |= 0x2; | |
6675 | ||
6676 | iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD); | |
6677 | iwl_conf->max_amsdu_size = | |
6678 | !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU); | |
6679 | ||
6680 | iwl_conf->supported_chan_width = | |
6681 | !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH); | |
6682 | iwl_conf->extension_chan_offset = | |
6683 | ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET; | |
6684 | /* If no above or below channel supplied disable FAT channel */ | |
6685 | if (iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_ABOVE && | |
6686 | iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_BELOW) | |
6687 | iwl_conf->supported_chan_width = 0; | |
6688 | ||
6689 | iwl_conf->tx_mimo_ps_mode = | |
6690 | (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2); | |
6691 | memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16); | |
6692 | ||
6693 | iwl_conf->control_channel = ht_bss_conf->primary_channel; | |
6694 | iwl_conf->tx_chan_width = | |
6695 | !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH); | |
6696 | iwl_conf->ht_protection = | |
6697 | ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION; | |
6698 | iwl_conf->non_GF_STA_present = | |
6699 | !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT); | |
6700 | ||
6701 | IWL_DEBUG_MAC80211("control channel %d\n", iwl_conf->control_channel); | |
6702 | IWL_DEBUG_MAC80211("leave\n"); | |
6703 | } | |
6704 | #else | |
6705 | static inline void iwl4965_ht_conf(struct iwl_priv *priv, | |
6706 | struct ieee80211_bss_conf *bss_conf) | |
6707 | { | |
6708 | } | |
6709 | #endif | |
6710 | ||
3109ece1 | 6711 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
471b3efd JB |
6712 | static void iwl4965_bss_info_changed(struct ieee80211_hw *hw, |
6713 | struct ieee80211_vif *vif, | |
6714 | struct ieee80211_bss_conf *bss_conf, | |
6715 | u32 changes) | |
220173b0 | 6716 | { |
c79dd5b5 | 6717 | struct iwl_priv *priv = hw->priv; |
220173b0 | 6718 | |
3109ece1 TW |
6719 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); |
6720 | ||
471b3efd | 6721 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
3109ece1 TW |
6722 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", |
6723 | bss_conf->use_short_preamble); | |
471b3efd | 6724 | if (bss_conf->use_short_preamble) |
220173b0 TW |
6725 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
6726 | else | |
6727 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6728 | } | |
6729 | ||
471b3efd | 6730 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { |
3109ece1 | 6731 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); |
8318d78a | 6732 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) |
220173b0 TW |
6733 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
6734 | else | |
6735 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
6736 | } | |
6737 | ||
98952d5d | 6738 | if (changes & BSS_CHANGED_HT) { |
3109ece1 | 6739 | IWL_DEBUG_MAC80211("HT %d\n", bss_conf->assoc_ht); |
98952d5d TW |
6740 | iwl4965_ht_conf(priv, bss_conf); |
6741 | iwl4965_set_rxon_chain(priv); | |
6742 | } | |
6743 | ||
471b3efd | 6744 | if (changes & BSS_CHANGED_ASSOC) { |
3109ece1 | 6745 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); |
508e32e1 RC |
6746 | /* This should never happen as this function should |
6747 | * never be called from interrupt context. */ | |
6748 | if (WARN_ON_ONCE(in_interrupt())) | |
6749 | return; | |
3109ece1 TW |
6750 | if (bss_conf->assoc) { |
6751 | priv->assoc_id = bss_conf->aid; | |
6752 | priv->beacon_int = bss_conf->beacon_int; | |
6753 | priv->timestamp = bss_conf->timestamp; | |
6754 | priv->assoc_capability = bss_conf->assoc_capability; | |
6755 | priv->next_scan_jiffies = jiffies + | |
6756 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
508e32e1 RC |
6757 | mutex_lock(&priv->mutex); |
6758 | iwl4965_post_associate(priv); | |
6759 | mutex_unlock(&priv->mutex); | |
3109ece1 TW |
6760 | } else { |
6761 | priv->assoc_id = 0; | |
6762 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
6763 | } | |
6764 | } else if (changes && iwl_is_associated(priv) && priv->assoc_id) { | |
6765 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
6766 | iwl4965_send_rxon_assoc(priv); | |
471b3efd JB |
6767 | } |
6768 | ||
220173b0 | 6769 | } |
b481de9c | 6770 | |
bb8c093b | 6771 | static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
6772 | { |
6773 | int rc = 0; | |
6774 | unsigned long flags; | |
c79dd5b5 | 6775 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6776 | |
6777 | IWL_DEBUG_MAC80211("enter\n"); | |
6778 | ||
052c4b9f | 6779 | mutex_lock(&priv->mutex); |
b481de9c ZY |
6780 | spin_lock_irqsave(&priv->lock, flags); |
6781 | ||
fee1247a | 6782 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6783 | rc = -EIO; |
6784 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
6785 | goto out_unlock; | |
6786 | } | |
6787 | ||
6788 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */ | |
6789 | rc = -EIO; | |
6790 | IWL_ERROR("ERROR: APs don't scan\n"); | |
6791 | goto out_unlock; | |
6792 | } | |
6793 | ||
7878a5a4 MA |
6794 | /* we don't schedule scan within next_scan_jiffies period */ |
6795 | if (priv->next_scan_jiffies && | |
6796 | time_after(priv->next_scan_jiffies, jiffies)) { | |
6797 | rc = -EAGAIN; | |
6798 | goto out_unlock; | |
6799 | } | |
b481de9c | 6800 | /* if we just finished scan ask for delay */ |
7878a5a4 MA |
6801 | if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies + |
6802 | IWL_DELAY_NEXT_SCAN, jiffies)) { | |
b481de9c ZY |
6803 | rc = -EAGAIN; |
6804 | goto out_unlock; | |
6805 | } | |
6806 | if (len) { | |
7878a5a4 | 6807 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
bb8c093b | 6808 | iwl4965_escape_essid(ssid, len), (int)len); |
b481de9c ZY |
6809 | |
6810 | priv->one_direct_scan = 1; | |
6811 | priv->direct_ssid_len = (u8) | |
6812 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
6813 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
948c171c MA |
6814 | } else |
6815 | priv->one_direct_scan = 0; | |
b481de9c | 6816 | |
bb8c093b | 6817 | rc = iwl4965_scan_initiate(priv); |
b481de9c ZY |
6818 | |
6819 | IWL_DEBUG_MAC80211("leave\n"); | |
6820 | ||
6821 | out_unlock: | |
6822 | spin_unlock_irqrestore(&priv->lock, flags); | |
052c4b9f | 6823 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
6824 | |
6825 | return rc; | |
6826 | } | |
6827 | ||
ab885f8c EG |
6828 | static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw, |
6829 | struct ieee80211_key_conf *keyconf, const u8 *addr, | |
6830 | u32 iv32, u16 *phase1key) | |
6831 | { | |
6832 | struct iwl_priv *priv = hw->priv; | |
6833 | u8 sta_id = IWL_INVALID_STATION; | |
6834 | unsigned long flags; | |
6835 | __le16 key_flags = 0; | |
6836 | int i; | |
6837 | DECLARE_MAC_BUF(mac); | |
6838 | ||
6839 | IWL_DEBUG_MAC80211("enter\n"); | |
6840 | ||
6841 | sta_id = iwl4965_hw_find_station(priv, addr); | |
6842 | if (sta_id == IWL_INVALID_STATION) { | |
6843 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
6844 | print_mac(mac, addr)); | |
6845 | return; | |
6846 | } | |
6847 | ||
6848 | iwl4965_scan_cancel_timeout(priv, 100); | |
6849 | ||
6850 | key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); | |
6851 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
6852 | key_flags &= ~STA_KEY_FLG_INVALID; | |
6853 | ||
6854 | if (sta_id == priv->hw_setting.bcast_sta_id) | |
6855 | key_flags |= STA_KEY_MULTICAST_MSK; | |
6856 | ||
6857 | spin_lock_irqsave(&priv->sta_lock, flags); | |
6858 | ||
6859 | priv->stations[sta_id].sta.key.key_offset = | |
80fb47a1 | 6860 | iwl_get_free_ucode_key_index(priv); |
ab885f8c EG |
6861 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
6862 | priv->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; | |
6863 | ||
6864 | for (i = 0; i < 5; i++) | |
6865 | priv->stations[sta_id].sta.key.tkip_rx_ttak[i] = | |
6866 | cpu_to_le16(phase1key[i]); | |
6867 | ||
6868 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
6869 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
6870 | ||
6871 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); | |
6872 | ||
6873 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
6874 | ||
6875 | IWL_DEBUG_MAC80211("leave\n"); | |
6876 | } | |
6877 | ||
bb8c093b | 6878 | static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
6879 | const u8 *local_addr, const u8 *addr, |
6880 | struct ieee80211_key_conf *key) | |
6881 | { | |
c79dd5b5 | 6882 | struct iwl_priv *priv = hw->priv; |
0795af57 | 6883 | DECLARE_MAC_BUF(mac); |
deb09c43 EG |
6884 | int ret = 0; |
6885 | u8 sta_id = IWL_INVALID_STATION; | |
6974e363 | 6886 | u8 is_default_wep_key = 0; |
b481de9c ZY |
6887 | |
6888 | IWL_DEBUG_MAC80211("enter\n"); | |
6889 | ||
1ea87396 | 6890 | if (!priv->cfg->mod_params->hw_crypto) { |
b481de9c ZY |
6891 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
6892 | return -EOPNOTSUPP; | |
6893 | } | |
6894 | ||
6895 | if (is_zero_ether_addr(addr)) | |
6896 | /* only support pairwise keys */ | |
6897 | return -EOPNOTSUPP; | |
6898 | ||
6974e363 EG |
6899 | sta_id = iwl4965_hw_find_station(priv, addr); |
6900 | if (sta_id == IWL_INVALID_STATION) { | |
6901 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
6902 | print_mac(mac, addr)); | |
6903 | return -EINVAL; | |
b481de9c | 6904 | |
deb09c43 | 6905 | } |
b481de9c | 6906 | |
6974e363 | 6907 | mutex_lock(&priv->mutex); |
bb8c093b | 6908 | iwl4965_scan_cancel_timeout(priv, 100); |
6974e363 EG |
6909 | mutex_unlock(&priv->mutex); |
6910 | ||
6911 | /* If we are getting WEP group key and we didn't receive any key mapping | |
6912 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
6913 | * in 1X mode. | |
6914 | * In legacy wep mode, we use another host command to the uCode */ | |
6915 | if (key->alg == ALG_WEP && sta_id == priv->hw_setting.bcast_sta_id && | |
6916 | priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
6917 | if (cmd == SET_KEY) | |
6918 | is_default_wep_key = !priv->key_mapping_key; | |
6919 | else | |
6920 | is_default_wep_key = priv->default_wep_key; | |
6921 | } | |
052c4b9f | 6922 | |
b481de9c | 6923 | switch (cmd) { |
deb09c43 | 6924 | case SET_KEY: |
6974e363 EG |
6925 | if (is_default_wep_key) |
6926 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 6927 | else |
7480513f | 6928 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 EG |
6929 | |
6930 | IWL_DEBUG_MAC80211("enable hwcrypto key\n"); | |
b481de9c ZY |
6931 | break; |
6932 | case DISABLE_KEY: | |
6974e363 EG |
6933 | if (is_default_wep_key) |
6934 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 6935 | else |
7480513f | 6936 | ret = iwl_remove_dynamic_key(priv, sta_id); |
deb09c43 EG |
6937 | |
6938 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); | |
b481de9c ZY |
6939 | break; |
6940 | default: | |
deb09c43 | 6941 | ret = -EINVAL; |
b481de9c ZY |
6942 | } |
6943 | ||
6944 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c | 6945 | |
deb09c43 | 6946 | return ret; |
b481de9c ZY |
6947 | } |
6948 | ||
bb8c093b | 6949 | static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue, |
b481de9c ZY |
6950 | const struct ieee80211_tx_queue_params *params) |
6951 | { | |
c79dd5b5 | 6952 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6953 | unsigned long flags; |
6954 | int q; | |
b481de9c ZY |
6955 | |
6956 | IWL_DEBUG_MAC80211("enter\n"); | |
6957 | ||
fee1247a | 6958 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6959 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
6960 | return -EIO; | |
6961 | } | |
6962 | ||
6963 | if (queue >= AC_NUM) { | |
6964 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
6965 | return 0; | |
6966 | } | |
6967 | ||
b481de9c ZY |
6968 | if (!priv->qos_data.qos_enable) { |
6969 | priv->qos_data.qos_active = 0; | |
6970 | IWL_DEBUG_MAC80211("leave - qos not enabled\n"); | |
6971 | return 0; | |
6972 | } | |
6973 | q = AC_NUM - 1 - queue; | |
6974 | ||
6975 | spin_lock_irqsave(&priv->lock, flags); | |
6976 | ||
6977 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
6978 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
6979 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
6980 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 6981 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
6982 | |
6983 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
6984 | priv->qos_data.qos_active = 1; | |
6985 | ||
6986 | spin_unlock_irqrestore(&priv->lock, flags); | |
6987 | ||
6988 | mutex_lock(&priv->mutex); | |
6989 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 6990 | iwl4965_activate_qos(priv, 1); |
3109ece1 | 6991 | else if (priv->assoc_id && iwl_is_associated(priv)) |
bb8c093b | 6992 | iwl4965_activate_qos(priv, 0); |
b481de9c ZY |
6993 | |
6994 | mutex_unlock(&priv->mutex); | |
6995 | ||
b481de9c ZY |
6996 | IWL_DEBUG_MAC80211("leave\n"); |
6997 | return 0; | |
6998 | } | |
6999 | ||
bb8c093b | 7000 | static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7001 | struct ieee80211_tx_queue_stats *stats) |
7002 | { | |
c79dd5b5 | 7003 | struct iwl_priv *priv = hw->priv; |
b481de9c | 7004 | int i, avail; |
bb8c093b CH |
7005 | struct iwl4965_tx_queue *txq; |
7006 | struct iwl4965_queue *q; | |
b481de9c ZY |
7007 | unsigned long flags; |
7008 | ||
7009 | IWL_DEBUG_MAC80211("enter\n"); | |
7010 | ||
fee1247a | 7011 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7012 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7013 | return -EIO; | |
7014 | } | |
7015 | ||
7016 | spin_lock_irqsave(&priv->lock, flags); | |
7017 | ||
7018 | for (i = 0; i < AC_NUM; i++) { | |
7019 | txq = &priv->txq[i]; | |
7020 | q = &txq->q; | |
bb8c093b | 7021 | avail = iwl4965_queue_space(q); |
b481de9c ZY |
7022 | |
7023 | stats->data[i].len = q->n_window - avail; | |
7024 | stats->data[i].limit = q->n_window - q->high_mark; | |
7025 | stats->data[i].count = q->n_window; | |
7026 | ||
7027 | } | |
7028 | spin_unlock_irqrestore(&priv->lock, flags); | |
7029 | ||
7030 | IWL_DEBUG_MAC80211("leave\n"); | |
7031 | ||
7032 | return 0; | |
7033 | } | |
7034 | ||
bb8c093b | 7035 | static int iwl4965_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7036 | struct ieee80211_low_level_stats *stats) |
7037 | { | |
7038 | IWL_DEBUG_MAC80211("enter\n"); | |
7039 | IWL_DEBUG_MAC80211("leave\n"); | |
7040 | ||
7041 | return 0; | |
7042 | } | |
7043 | ||
bb8c093b | 7044 | static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw) |
b481de9c ZY |
7045 | { |
7046 | IWL_DEBUG_MAC80211("enter\n"); | |
7047 | IWL_DEBUG_MAC80211("leave\n"); | |
7048 | ||
7049 | return 0; | |
7050 | } | |
7051 | ||
bb8c093b | 7052 | static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7053 | { |
c79dd5b5 | 7054 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7055 | unsigned long flags; |
7056 | ||
7057 | mutex_lock(&priv->mutex); | |
7058 | IWL_DEBUG_MAC80211("enter\n"); | |
7059 | ||
7060 | priv->lq_mngr.lq_ready = 0; | |
c8b0e6e1 | 7061 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 7062 | spin_lock_irqsave(&priv->lock, flags); |
fd105e79 | 7063 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); |
b481de9c | 7064 | spin_unlock_irqrestore(&priv->lock, flags); |
c8b0e6e1 | 7065 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 7066 | |
bf85ea4f | 7067 | iwlcore_reset_qos(priv); |
b481de9c ZY |
7068 | |
7069 | cancel_delayed_work(&priv->post_associate); | |
7070 | ||
7071 | spin_lock_irqsave(&priv->lock, flags); | |
7072 | priv->assoc_id = 0; | |
7073 | priv->assoc_capability = 0; | |
b481de9c ZY |
7074 | priv->assoc_station_added = 0; |
7075 | ||
7076 | /* new association get rid of ibss beacon skb */ | |
7077 | if (priv->ibss_beacon) | |
7078 | dev_kfree_skb(priv->ibss_beacon); | |
7079 | ||
7080 | priv->ibss_beacon = NULL; | |
7081 | ||
7082 | priv->beacon_int = priv->hw->conf.beacon_int; | |
3109ece1 | 7083 | priv->timestamp = 0; |
b481de9c ZY |
7084 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA)) |
7085 | priv->beacon_int = 0; | |
7086 | ||
7087 | spin_unlock_irqrestore(&priv->lock, flags); | |
7088 | ||
fee1247a | 7089 | if (!iwl_is_ready_rf(priv)) { |
fde3571f MA |
7090 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
7091 | mutex_unlock(&priv->mutex); | |
7092 | return; | |
7093 | } | |
7094 | ||
052c4b9f | 7095 | /* we are restarting association process |
7096 | * clear RXON_FILTER_ASSOC_MSK bit | |
7097 | */ | |
7098 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
bb8c093b | 7099 | iwl4965_scan_cancel_timeout(priv, 100); |
052c4b9f | 7100 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7101 | iwl4965_commit_rxon(priv); |
052c4b9f | 7102 | } |
7103 | ||
b481de9c ZY |
7104 | /* Per mac80211.h: This is only used in IBSS mode... */ |
7105 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
052c4b9f | 7106 | |
b481de9c ZY |
7107 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7108 | mutex_unlock(&priv->mutex); | |
7109 | return; | |
7110 | } | |
7111 | ||
b481de9c ZY |
7112 | priv->only_active_channel = 0; |
7113 | ||
bb8c093b | 7114 | iwl4965_set_rate(priv); |
b481de9c ZY |
7115 | |
7116 | mutex_unlock(&priv->mutex); | |
7117 | ||
7118 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
7119 | } |
7120 | ||
bb8c093b | 7121 | static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
7122 | struct ieee80211_tx_control *control) |
7123 | { | |
c79dd5b5 | 7124 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
7125 | unsigned long flags; |
7126 | ||
7127 | mutex_lock(&priv->mutex); | |
7128 | IWL_DEBUG_MAC80211("enter\n"); | |
7129 | ||
fee1247a | 7130 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
7131 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7132 | mutex_unlock(&priv->mutex); | |
7133 | return -EIO; | |
7134 | } | |
7135 | ||
7136 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
7137 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); | |
7138 | mutex_unlock(&priv->mutex); | |
7139 | return -EIO; | |
7140 | } | |
7141 | ||
7142 | spin_lock_irqsave(&priv->lock, flags); | |
7143 | ||
7144 | if (priv->ibss_beacon) | |
7145 | dev_kfree_skb(priv->ibss_beacon); | |
7146 | ||
7147 | priv->ibss_beacon = skb; | |
7148 | ||
7149 | priv->assoc_id = 0; | |
7150 | ||
7151 | IWL_DEBUG_MAC80211("leave\n"); | |
7152 | spin_unlock_irqrestore(&priv->lock, flags); | |
7153 | ||
bf85ea4f | 7154 | iwlcore_reset_qos(priv); |
b481de9c ZY |
7155 | |
7156 | queue_work(priv->workqueue, &priv->post_associate.work); | |
7157 | ||
7158 | mutex_unlock(&priv->mutex); | |
7159 | ||
7160 | return 0; | |
7161 | } | |
7162 | ||
b481de9c ZY |
7163 | /***************************************************************************** |
7164 | * | |
7165 | * sysfs attributes | |
7166 | * | |
7167 | *****************************************************************************/ | |
7168 | ||
0a6857e7 | 7169 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
7170 | |
7171 | /* | |
7172 | * The following adds a new attribute to the sysfs representation | |
7173 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7174 | * used for controlling the debug level. | |
7175 | * | |
7176 | * See the level definitions in iwl for details. | |
7177 | */ | |
7178 | ||
7179 | static ssize_t show_debug_level(struct device_driver *d, char *buf) | |
7180 | { | |
0a6857e7 | 7181 | return sprintf(buf, "0x%08X\n", iwl_debug_level); |
b481de9c ZY |
7182 | } |
7183 | static ssize_t store_debug_level(struct device_driver *d, | |
7184 | const char *buf, size_t count) | |
7185 | { | |
7186 | char *p = (char *)buf; | |
7187 | u32 val; | |
7188 | ||
7189 | val = simple_strtoul(p, &p, 0); | |
7190 | if (p == buf) | |
7191 | printk(KERN_INFO DRV_NAME | |
7192 | ": %s is not in hex or decimal form.\n", buf); | |
7193 | else | |
0a6857e7 | 7194 | iwl_debug_level = val; |
b481de9c ZY |
7195 | |
7196 | return strnlen(buf, count); | |
7197 | } | |
7198 | ||
7199 | static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
7200 | show_debug_level, store_debug_level); | |
7201 | ||
0a6857e7 | 7202 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 7203 | |
b481de9c ZY |
7204 | |
7205 | static ssize_t show_temperature(struct device *d, | |
7206 | struct device_attribute *attr, char *buf) | |
7207 | { | |
c79dd5b5 | 7208 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 7209 | |
fee1247a | 7210 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7211 | return -EAGAIN; |
7212 | ||
bb8c093b | 7213 | return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv)); |
b481de9c ZY |
7214 | } |
7215 | ||
7216 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7217 | ||
7218 | static ssize_t show_rs_window(struct device *d, | |
7219 | struct device_attribute *attr, | |
7220 | char *buf) | |
7221 | { | |
c79dd5b5 | 7222 | struct iwl_priv *priv = d->driver_data; |
bb8c093b | 7223 | return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID); |
b481de9c ZY |
7224 | } |
7225 | static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL); | |
7226 | ||
7227 | static ssize_t show_tx_power(struct device *d, | |
7228 | struct device_attribute *attr, char *buf) | |
7229 | { | |
c79dd5b5 | 7230 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7231 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7232 | } | |
7233 | ||
7234 | static ssize_t store_tx_power(struct device *d, | |
7235 | struct device_attribute *attr, | |
7236 | const char *buf, size_t count) | |
7237 | { | |
c79dd5b5 | 7238 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7239 | char *p = (char *)buf; |
7240 | u32 val; | |
7241 | ||
7242 | val = simple_strtoul(p, &p, 10); | |
7243 | if (p == buf) | |
7244 | printk(KERN_INFO DRV_NAME | |
7245 | ": %s is not in decimal form.\n", buf); | |
7246 | else | |
bb8c093b | 7247 | iwl4965_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7248 | |
7249 | return count; | |
7250 | } | |
7251 | ||
7252 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7253 | ||
7254 | static ssize_t show_flags(struct device *d, | |
7255 | struct device_attribute *attr, char *buf) | |
7256 | { | |
c79dd5b5 | 7257 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7258 | |
7259 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
7260 | } | |
7261 | ||
7262 | static ssize_t store_flags(struct device *d, | |
7263 | struct device_attribute *attr, | |
7264 | const char *buf, size_t count) | |
7265 | { | |
c79dd5b5 | 7266 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7267 | u32 flags = simple_strtoul(buf, NULL, 0); |
7268 | ||
7269 | mutex_lock(&priv->mutex); | |
7270 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
7271 | /* Cancel any currently running scans... */ | |
bb8c093b | 7272 | if (iwl4965_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7273 | IWL_WARNING("Could not cancel scan.\n"); |
7274 | else { | |
7275 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7276 | flags); | |
7277 | priv->staging_rxon.flags = cpu_to_le32(flags); | |
bb8c093b | 7278 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
7279 | } |
7280 | } | |
7281 | mutex_unlock(&priv->mutex); | |
7282 | ||
7283 | return count; | |
7284 | } | |
7285 | ||
7286 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7287 | ||
7288 | static ssize_t show_filter_flags(struct device *d, | |
7289 | struct device_attribute *attr, char *buf) | |
7290 | { | |
c79dd5b5 | 7291 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7292 | |
7293 | return sprintf(buf, "0x%04X\n", | |
7294 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
7295 | } | |
7296 | ||
7297 | static ssize_t store_filter_flags(struct device *d, | |
7298 | struct device_attribute *attr, | |
7299 | const char *buf, size_t count) | |
7300 | { | |
c79dd5b5 | 7301 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
7302 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7303 | ||
7304 | mutex_lock(&priv->mutex); | |
7305 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
7306 | /* Cancel any currently running scans... */ | |
bb8c093b | 7307 | if (iwl4965_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7308 | IWL_WARNING("Could not cancel scan.\n"); |
7309 | else { | |
7310 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7311 | "0x%04X\n", filter_flags); | |
7312 | priv->staging_rxon.filter_flags = | |
7313 | cpu_to_le32(filter_flags); | |
bb8c093b | 7314 | iwl4965_commit_rxon(priv); |
b481de9c ZY |
7315 | } |
7316 | } | |
7317 | mutex_unlock(&priv->mutex); | |
7318 | ||
7319 | return count; | |
7320 | } | |
7321 | ||
7322 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7323 | store_filter_flags); | |
7324 | ||
c8b0e6e1 | 7325 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7326 | |
7327 | static ssize_t show_measurement(struct device *d, | |
7328 | struct device_attribute *attr, char *buf) | |
7329 | { | |
c79dd5b5 | 7330 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7331 | struct iwl4965_spectrum_notification measure_report; |
b481de9c ZY |
7332 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
7333 | u8 *data = (u8 *) & measure_report; | |
7334 | unsigned long flags; | |
7335 | ||
7336 | spin_lock_irqsave(&priv->lock, flags); | |
7337 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7338 | spin_unlock_irqrestore(&priv->lock, flags); | |
7339 | return 0; | |
7340 | } | |
7341 | memcpy(&measure_report, &priv->measure_report, size); | |
7342 | priv->measurement_status = 0; | |
7343 | spin_unlock_irqrestore(&priv->lock, flags); | |
7344 | ||
7345 | while (size && (PAGE_SIZE - len)) { | |
7346 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7347 | PAGE_SIZE - len, 1); | |
7348 | len = strlen(buf); | |
7349 | if (PAGE_SIZE - len) | |
7350 | buf[len++] = '\n'; | |
7351 | ||
7352 | ofs += 16; | |
7353 | size -= min(size, 16U); | |
7354 | } | |
7355 | ||
7356 | return len; | |
7357 | } | |
7358 | ||
7359 | static ssize_t store_measurement(struct device *d, | |
7360 | struct device_attribute *attr, | |
7361 | const char *buf, size_t count) | |
7362 | { | |
c79dd5b5 | 7363 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7364 | struct ieee80211_measurement_params params = { |
7365 | .channel = le16_to_cpu(priv->active_rxon.channel), | |
7366 | .start_time = cpu_to_le64(priv->last_tsf), | |
7367 | .duration = cpu_to_le16(1), | |
7368 | }; | |
7369 | u8 type = IWL_MEASURE_BASIC; | |
7370 | u8 buffer[32]; | |
7371 | u8 channel; | |
7372 | ||
7373 | if (count) { | |
7374 | char *p = buffer; | |
7375 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7376 | channel = simple_strtoul(p, NULL, 0); | |
7377 | if (channel) | |
7378 | params.channel = channel; | |
7379 | ||
7380 | p = buffer; | |
7381 | while (*p && *p != ' ') | |
7382 | p++; | |
7383 | if (*p) | |
7384 | type = simple_strtoul(p + 1, NULL, 0); | |
7385 | } | |
7386 | ||
7387 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7388 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7389 | iwl4965_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7390 | |
7391 | return count; | |
7392 | } | |
7393 | ||
7394 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7395 | show_measurement, store_measurement); | |
c8b0e6e1 | 7396 | #endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */ |
b481de9c ZY |
7397 | |
7398 | static ssize_t store_retry_rate(struct device *d, | |
7399 | struct device_attribute *attr, | |
7400 | const char *buf, size_t count) | |
7401 | { | |
c79dd5b5 | 7402 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7403 | |
7404 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7405 | if (priv->retry_rate <= 0) | |
7406 | priv->retry_rate = 1; | |
7407 | ||
7408 | return count; | |
7409 | } | |
7410 | ||
7411 | static ssize_t show_retry_rate(struct device *d, | |
7412 | struct device_attribute *attr, char *buf) | |
7413 | { | |
c79dd5b5 | 7414 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7415 | return sprintf(buf, "%d", priv->retry_rate); |
7416 | } | |
7417 | ||
7418 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7419 | store_retry_rate); | |
7420 | ||
7421 | static ssize_t store_power_level(struct device *d, | |
7422 | struct device_attribute *attr, | |
7423 | const char *buf, size_t count) | |
7424 | { | |
c79dd5b5 | 7425 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7426 | int rc; |
7427 | int mode; | |
7428 | ||
7429 | mode = simple_strtoul(buf, NULL, 0); | |
7430 | mutex_lock(&priv->mutex); | |
7431 | ||
fee1247a | 7432 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
7433 | rc = -EAGAIN; |
7434 | goto out; | |
7435 | } | |
7436 | ||
7437 | if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) | |
7438 | mode = IWL_POWER_AC; | |
7439 | else | |
7440 | mode |= IWL_POWER_ENABLED; | |
7441 | ||
7442 | if (mode != priv->power_mode) { | |
bb8c093b | 7443 | rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7444 | if (rc) { |
7445 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7446 | goto out; | |
7447 | } | |
7448 | priv->power_mode = mode; | |
7449 | } | |
7450 | ||
7451 | rc = count; | |
7452 | ||
7453 | out: | |
7454 | mutex_unlock(&priv->mutex); | |
7455 | return rc; | |
7456 | } | |
7457 | ||
7458 | #define MAX_WX_STRING 80 | |
7459 | ||
7460 | /* Values are in microsecond */ | |
7461 | static const s32 timeout_duration[] = { | |
7462 | 350000, | |
7463 | 250000, | |
7464 | 75000, | |
7465 | 37000, | |
7466 | 25000, | |
7467 | }; | |
7468 | static const s32 period_duration[] = { | |
7469 | 400000, | |
7470 | 700000, | |
7471 | 1000000, | |
7472 | 1000000, | |
7473 | 1000000 | |
7474 | }; | |
7475 | ||
7476 | static ssize_t show_power_level(struct device *d, | |
7477 | struct device_attribute *attr, char *buf) | |
7478 | { | |
c79dd5b5 | 7479 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7480 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7481 | char *p = buf; | |
7482 | ||
7483 | p += sprintf(p, "%d ", level); | |
7484 | switch (level) { | |
7485 | case IWL_POWER_MODE_CAM: | |
7486 | case IWL_POWER_AC: | |
7487 | p += sprintf(p, "(AC)"); | |
7488 | break; | |
7489 | case IWL_POWER_BATTERY: | |
7490 | p += sprintf(p, "(BATTERY)"); | |
7491 | break; | |
7492 | default: | |
7493 | p += sprintf(p, | |
7494 | "(Timeout %dms, Period %dms)", | |
7495 | timeout_duration[level - 1] / 1000, | |
7496 | period_duration[level - 1] / 1000); | |
7497 | } | |
7498 | ||
7499 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7500 | p += sprintf(p, " OFF\n"); | |
7501 | else | |
7502 | p += sprintf(p, " \n"); | |
7503 | ||
7504 | return (p - buf + 1); | |
7505 | ||
7506 | } | |
7507 | ||
7508 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7509 | store_power_level); | |
7510 | ||
7511 | static ssize_t show_channels(struct device *d, | |
7512 | struct device_attribute *attr, char *buf) | |
7513 | { | |
8318d78a JB |
7514 | /* all this shit doesn't belong into sysfs anyway */ |
7515 | return 0; | |
b481de9c ZY |
7516 | } |
7517 | ||
7518 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7519 | ||
7520 | static ssize_t show_statistics(struct device *d, | |
7521 | struct device_attribute *attr, char *buf) | |
7522 | { | |
c79dd5b5 | 7523 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 7524 | u32 size = sizeof(struct iwl4965_notif_statistics); |
b481de9c ZY |
7525 | u32 len = 0, ofs = 0; |
7526 | u8 *data = (u8 *) & priv->statistics; | |
7527 | int rc = 0; | |
7528 | ||
fee1247a | 7529 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7530 | return -EAGAIN; |
7531 | ||
7532 | mutex_lock(&priv->mutex); | |
bb8c093b | 7533 | rc = iwl4965_send_statistics_request(priv); |
b481de9c ZY |
7534 | mutex_unlock(&priv->mutex); |
7535 | ||
7536 | if (rc) { | |
7537 | len = sprintf(buf, | |
7538 | "Error sending statistics request: 0x%08X\n", rc); | |
7539 | return len; | |
7540 | } | |
7541 | ||
7542 | while (size && (PAGE_SIZE - len)) { | |
7543 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7544 | PAGE_SIZE - len, 1); | |
7545 | len = strlen(buf); | |
7546 | if (PAGE_SIZE - len) | |
7547 | buf[len++] = '\n'; | |
7548 | ||
7549 | ofs += 16; | |
7550 | size -= min(size, 16U); | |
7551 | } | |
7552 | ||
7553 | return len; | |
7554 | } | |
7555 | ||
7556 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7557 | ||
7558 | static ssize_t show_antenna(struct device *d, | |
7559 | struct device_attribute *attr, char *buf) | |
7560 | { | |
c79dd5b5 | 7561 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 7562 | |
fee1247a | 7563 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7564 | return -EAGAIN; |
7565 | ||
7566 | return sprintf(buf, "%d\n", priv->antenna); | |
7567 | } | |
7568 | ||
7569 | static ssize_t store_antenna(struct device *d, | |
7570 | struct device_attribute *attr, | |
7571 | const char *buf, size_t count) | |
7572 | { | |
7573 | int ant; | |
c79dd5b5 | 7574 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7575 | |
7576 | if (count == 0) | |
7577 | return 0; | |
7578 | ||
7579 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7580 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7581 | return count; | |
7582 | } | |
7583 | ||
7584 | if ((ant >= 0) && (ant <= 2)) { | |
7585 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7586 | priv->antenna = (enum iwl4965_antenna)ant; |
b481de9c ZY |
7587 | } else |
7588 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7589 | ||
7590 | ||
7591 | return count; | |
7592 | } | |
7593 | ||
7594 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7595 | ||
7596 | static ssize_t show_status(struct device *d, | |
7597 | struct device_attribute *attr, char *buf) | |
7598 | { | |
c79dd5b5 | 7599 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
fee1247a | 7600 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7601 | return -EAGAIN; |
7602 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7603 | } | |
7604 | ||
7605 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7606 | ||
7607 | static ssize_t dump_error_log(struct device *d, | |
7608 | struct device_attribute *attr, | |
7609 | const char *buf, size_t count) | |
7610 | { | |
7611 | char *p = (char *)buf; | |
7612 | ||
7613 | if (p[0] == '1') | |
c79dd5b5 | 7614 | iwl4965_dump_nic_error_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7615 | |
7616 | return strnlen(buf, count); | |
7617 | } | |
7618 | ||
7619 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7620 | ||
7621 | static ssize_t dump_event_log(struct device *d, | |
7622 | struct device_attribute *attr, | |
7623 | const char *buf, size_t count) | |
7624 | { | |
7625 | char *p = (char *)buf; | |
7626 | ||
7627 | if (p[0] == '1') | |
c79dd5b5 | 7628 | iwl4965_dump_nic_event_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7629 | |
7630 | return strnlen(buf, count); | |
7631 | } | |
7632 | ||
7633 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7634 | ||
7635 | /***************************************************************************** | |
7636 | * | |
7637 | * driver setup and teardown | |
7638 | * | |
7639 | *****************************************************************************/ | |
7640 | ||
c79dd5b5 | 7641 | static void iwl4965_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
7642 | { |
7643 | priv->workqueue = create_workqueue(DRV_NAME); | |
7644 | ||
7645 | init_waitqueue_head(&priv->wait_command_queue); | |
7646 | ||
bb8c093b CH |
7647 | INIT_WORK(&priv->up, iwl4965_bg_up); |
7648 | INIT_WORK(&priv->restart, iwl4965_bg_restart); | |
7649 | INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish); | |
7650 | INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed); | |
7651 | INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan); | |
7652 | INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan); | |
7653 | INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill); | |
7654 | INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update); | |
7655 | INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate); | |
7656 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start); | |
7657 | INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start); | |
7658 | INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check); | |
7659 | ||
7660 | iwl4965_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7661 | |
7662 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7663 | iwl4965_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7664 | } |
7665 | ||
c79dd5b5 | 7666 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 7667 | { |
bb8c093b | 7668 | iwl4965_hw_cancel_deferred_work(priv); |
b481de9c | 7669 | |
3ae6a054 | 7670 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7671 | cancel_delayed_work(&priv->scan_check); |
7672 | cancel_delayed_work(&priv->alive_start); | |
7673 | cancel_delayed_work(&priv->post_associate); | |
7674 | cancel_work_sync(&priv->beacon_update); | |
7675 | } | |
7676 | ||
bb8c093b | 7677 | static struct attribute *iwl4965_sysfs_entries[] = { |
b481de9c ZY |
7678 | &dev_attr_antenna.attr, |
7679 | &dev_attr_channels.attr, | |
7680 | &dev_attr_dump_errors.attr, | |
7681 | &dev_attr_dump_events.attr, | |
7682 | &dev_attr_flags.attr, | |
7683 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7684 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7685 | &dev_attr_measurement.attr, |
7686 | #endif | |
7687 | &dev_attr_power_level.attr, | |
7688 | &dev_attr_retry_rate.attr, | |
b481de9c ZY |
7689 | &dev_attr_rs_window.attr, |
7690 | &dev_attr_statistics.attr, | |
7691 | &dev_attr_status.attr, | |
7692 | &dev_attr_temperature.attr, | |
b481de9c ZY |
7693 | &dev_attr_tx_power.attr, |
7694 | ||
7695 | NULL | |
7696 | }; | |
7697 | ||
bb8c093b | 7698 | static struct attribute_group iwl4965_attribute_group = { |
b481de9c | 7699 | .name = NULL, /* put in device directory */ |
bb8c093b | 7700 | .attrs = iwl4965_sysfs_entries, |
b481de9c ZY |
7701 | }; |
7702 | ||
bb8c093b CH |
7703 | static struct ieee80211_ops iwl4965_hw_ops = { |
7704 | .tx = iwl4965_mac_tx, | |
7705 | .start = iwl4965_mac_start, | |
7706 | .stop = iwl4965_mac_stop, | |
7707 | .add_interface = iwl4965_mac_add_interface, | |
7708 | .remove_interface = iwl4965_mac_remove_interface, | |
7709 | .config = iwl4965_mac_config, | |
7710 | .config_interface = iwl4965_mac_config_interface, | |
7711 | .configure_filter = iwl4965_configure_filter, | |
7712 | .set_key = iwl4965_mac_set_key, | |
ab885f8c | 7713 | .update_tkip_key = iwl4965_mac_update_tkip_key, |
bb8c093b CH |
7714 | .get_stats = iwl4965_mac_get_stats, |
7715 | .get_tx_stats = iwl4965_mac_get_tx_stats, | |
7716 | .conf_tx = iwl4965_mac_conf_tx, | |
7717 | .get_tsf = iwl4965_mac_get_tsf, | |
7718 | .reset_tsf = iwl4965_mac_reset_tsf, | |
7719 | .beacon_update = iwl4965_mac_beacon_update, | |
471b3efd | 7720 | .bss_info_changed = iwl4965_bss_info_changed, |
c8b0e6e1 | 7721 | #ifdef CONFIG_IWL4965_HT |
9ab46173 | 7722 | .ampdu_action = iwl4965_mac_ampdu_action, |
c8b0e6e1 | 7723 | #endif /* CONFIG_IWL4965_HT */ |
bb8c093b | 7724 | .hw_scan = iwl4965_mac_hw_scan |
b481de9c ZY |
7725 | }; |
7726 | ||
bb8c093b | 7727 | static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7728 | { |
7729 | int err = 0; | |
c79dd5b5 | 7730 | struct iwl_priv *priv; |
b481de9c | 7731 | struct ieee80211_hw *hw; |
82b9a121 | 7732 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 7733 | unsigned long flags; |
5a66926a | 7734 | DECLARE_MAC_BUF(mac); |
b481de9c | 7735 | |
316c30d9 AK |
7736 | /************************ |
7737 | * 1. Allocating HW data | |
7738 | ************************/ | |
7739 | ||
6440adb5 BC |
7740 | /* Disabling hardware scan means that mac80211 will perform scans |
7741 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 7742 | if (cfg->mod_params->disable_hw_scan) { |
b481de9c | 7743 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
bb8c093b | 7744 | iwl4965_hw_ops.hw_scan = NULL; |
b481de9c ZY |
7745 | } |
7746 | ||
1d0a082d AK |
7747 | hw = iwl_alloc_all(cfg, &iwl4965_hw_ops); |
7748 | if (!hw) { | |
b481de9c ZY |
7749 | err = -ENOMEM; |
7750 | goto out; | |
7751 | } | |
1d0a082d AK |
7752 | priv = hw->priv; |
7753 | /* At this point both hw and priv are allocated. */ | |
7754 | ||
b481de9c ZY |
7755 | SET_IEEE80211_DEV(hw, &pdev->dev); |
7756 | ||
7757 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); | |
82b9a121 | 7758 | priv->cfg = cfg; |
b481de9c | 7759 | priv->pci_dev = pdev; |
316c30d9 | 7760 | |
0a6857e7 | 7761 | #ifdef CONFIG_IWLWIFI_DEBUG |
1ea87396 | 7762 | iwl_debug_level = priv->cfg->mod_params->debug; |
b481de9c ZY |
7763 | atomic_set(&priv->restrict_refcnt, 0); |
7764 | #endif | |
b481de9c | 7765 | |
316c30d9 AK |
7766 | /************************** |
7767 | * 2. Initializing PCI bus | |
7768 | **************************/ | |
7769 | if (pci_enable_device(pdev)) { | |
7770 | err = -ENODEV; | |
7771 | goto out_ieee80211_free_hw; | |
7772 | } | |
7773 | ||
7774 | pci_set_master(pdev); | |
7775 | ||
7776 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
7777 | if (!err) | |
7778 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
7779 | if (err) { | |
7780 | printk(KERN_WARNING DRV_NAME | |
7781 | ": No suitable DMA available.\n"); | |
7782 | goto out_pci_disable_device; | |
7783 | } | |
7784 | ||
7785 | err = pci_request_regions(pdev, DRV_NAME); | |
7786 | if (err) | |
7787 | goto out_pci_disable_device; | |
7788 | ||
7789 | pci_set_drvdata(pdev, priv); | |
7790 | ||
7791 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
7792 | * PCI Tx retries from interfering with C3 CPU state */ | |
7793 | pci_write_config_byte(pdev, 0x41, 0x00); | |
7794 | ||
7795 | /*********************** | |
7796 | * 3. Read REV register | |
7797 | ***********************/ | |
7798 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
7799 | if (!priv->hw_base) { | |
7800 | err = -ENODEV; | |
7801 | goto out_pci_release_regions; | |
7802 | } | |
7803 | ||
7804 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
7805 | (unsigned long long) pci_resource_len(pdev, 0)); | |
7806 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
7807 | ||
7808 | printk(KERN_INFO DRV_NAME | |
7809 | ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); | |
7810 | ||
7811 | /***************** | |
7812 | * 4. Read EEPROM | |
7813 | *****************/ | |
7814 | /* nic init */ | |
3395f6e9 | 7815 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
316c30d9 AK |
7816 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
7817 | ||
3395f6e9 TW |
7818 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
7819 | err = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
316c30d9 AK |
7820 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
7821 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
7822 | if (err < 0) { | |
7823 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
7824 | goto out_iounmap; | |
7825 | } | |
7826 | /* Read the EEPROM */ | |
7827 | err = iwl_eeprom_init(priv); | |
7828 | if (err) { | |
7829 | IWL_ERROR("Unable to init EEPROM\n"); | |
7830 | goto out_iounmap; | |
7831 | } | |
7832 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
7833 | iwl_eeprom_get_mac(priv, priv->mac_addr); | |
7834 | IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); | |
7835 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
7836 | ||
7837 | /************************ | |
7838 | * 5. Setup HW constants | |
7839 | ************************/ | |
7840 | /* Device-specific setup */ | |
7841 | if (iwl4965_hw_set_hw_setting(priv)) { | |
7842 | IWL_ERROR("failed to set hw settings\n"); | |
7843 | goto out_iounmap; | |
7844 | } | |
7845 | ||
7846 | /******************* | |
7847 | * 6. Setup hw/priv | |
7848 | *******************/ | |
b481de9c | 7849 | |
bf85ea4f AK |
7850 | err = iwl_setup(priv); |
7851 | if (err) | |
316c30d9 | 7852 | goto out_unset_hw_settings; |
bf85ea4f | 7853 | /* At this point both hw and priv are initialized. */ |
316c30d9 AK |
7854 | |
7855 | /********************************** | |
7856 | * 7. Initialize module parameters | |
7857 | **********************************/ | |
7858 | ||
7859 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
1ea87396 | 7860 | if (priv->cfg->mod_params->disable) { |
316c30d9 AK |
7861 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
7862 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
7863 | } | |
7864 | ||
1ea87396 | 7865 | if (priv->cfg->mod_params->enable_qos) |
316c30d9 AK |
7866 | priv->qos_data.qos_enable = 1; |
7867 | ||
7868 | /******************** | |
7869 | * 8. Setup services | |
7870 | ********************/ | |
0359facc | 7871 | spin_lock_irqsave(&priv->lock, flags); |
316c30d9 | 7872 | iwl4965_disable_interrupts(priv); |
0359facc | 7873 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 AK |
7874 | |
7875 | err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group); | |
7876 | if (err) { | |
7877 | IWL_ERROR("failed to create sysfs device attributes\n"); | |
bf85ea4f | 7878 | goto out_unset_hw_settings; |
316c30d9 AK |
7879 | } |
7880 | ||
7881 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
7882 | if (err) { | |
7883 | IWL_ERROR("failed to create debugfs files\n"); | |
7884 | goto out_remove_sysfs; | |
7885 | } | |
7886 | ||
7887 | iwl4965_setup_deferred_work(priv); | |
7888 | iwl4965_setup_rx_handlers(priv); | |
7889 | ||
7890 | /******************** | |
7891 | * 9. Conclude | |
7892 | ********************/ | |
5a66926a ZY |
7893 | pci_save_state(pdev); |
7894 | pci_disable_device(pdev); | |
b481de9c | 7895 | |
c8381fdc MA |
7896 | /* notify iwlcore to init */ |
7897 | iwlcore_low_level_notify(priv, IWLCORE_INIT_EVT); | |
b481de9c ZY |
7898 | return 0; |
7899 | ||
316c30d9 AK |
7900 | out_remove_sysfs: |
7901 | sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); | |
316c30d9 | 7902 | out_unset_hw_settings: |
bb8c093b | 7903 | iwl4965_unset_hw_setting(priv); |
b481de9c ZY |
7904 | out_iounmap: |
7905 | pci_iounmap(pdev, priv->hw_base); | |
7906 | out_pci_release_regions: | |
7907 | pci_release_regions(pdev); | |
316c30d9 | 7908 | pci_set_drvdata(pdev, NULL); |
b481de9c ZY |
7909 | out_pci_disable_device: |
7910 | pci_disable_device(pdev); | |
b481de9c ZY |
7911 | out_ieee80211_free_hw: |
7912 | ieee80211_free_hw(priv->hw); | |
7913 | out: | |
7914 | return err; | |
7915 | } | |
7916 | ||
c83dbf68 | 7917 | static void __devexit iwl4965_pci_remove(struct pci_dev *pdev) |
b481de9c | 7918 | { |
c79dd5b5 | 7919 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c ZY |
7920 | struct list_head *p, *q; |
7921 | int i; | |
0359facc | 7922 | unsigned long flags; |
b481de9c ZY |
7923 | |
7924 | if (!priv) | |
7925 | return; | |
7926 | ||
7927 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
7928 | ||
c4f55232 RR |
7929 | if (priv->mac80211_registered) { |
7930 | ieee80211_unregister_hw(priv->hw); | |
7931 | priv->mac80211_registered = 0; | |
7932 | } | |
7933 | ||
b481de9c | 7934 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 7935 | |
bb8c093b | 7936 | iwl4965_down(priv); |
b481de9c | 7937 | |
0359facc MA |
7938 | /* make sure we flush any pending irq or |
7939 | * tasklet for the driver | |
7940 | */ | |
7941 | spin_lock_irqsave(&priv->lock, flags); | |
7942 | iwl4965_disable_interrupts(priv); | |
7943 | spin_unlock_irqrestore(&priv->lock, flags); | |
7944 | ||
7945 | iwl_synchronize_irq(priv); | |
7946 | ||
b481de9c ZY |
7947 | /* Free MAC hash list for ADHOC */ |
7948 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) { | |
7949 | list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) { | |
7950 | list_del(p); | |
bb8c093b | 7951 | kfree(list_entry(p, struct iwl4965_ibss_seq, list)); |
b481de9c ZY |
7952 | } |
7953 | } | |
7954 | ||
c8381fdc | 7955 | iwlcore_low_level_notify(priv, IWLCORE_REMOVE_EVT); |
712b6cf5 | 7956 | iwl_dbgfs_unregister(priv); |
bb8c093b | 7957 | sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group); |
b481de9c | 7958 | |
bb8c093b | 7959 | iwl4965_dealloc_ucode_pci(priv); |
b481de9c ZY |
7960 | |
7961 | if (priv->rxq.bd) | |
bb8c093b CH |
7962 | iwl4965_rx_queue_free(priv, &priv->rxq); |
7963 | iwl4965_hw_txq_ctx_free(priv); | |
b481de9c | 7964 | |
bb8c093b | 7965 | iwl4965_unset_hw_setting(priv); |
bf85ea4f | 7966 | iwlcore_clear_stations_table(priv); |
b481de9c | 7967 | |
b481de9c | 7968 | |
948c171c MA |
7969 | /*netif_stop_queue(dev); */ |
7970 | flush_workqueue(priv->workqueue); | |
7971 | ||
bb8c093b | 7972 | /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes |
b481de9c ZY |
7973 | * priv->workqueue... so we can't take down the workqueue |
7974 | * until now... */ | |
7975 | destroy_workqueue(priv->workqueue); | |
7976 | priv->workqueue = NULL; | |
7977 | ||
b481de9c ZY |
7978 | pci_iounmap(pdev, priv->hw_base); |
7979 | pci_release_regions(pdev); | |
7980 | pci_disable_device(pdev); | |
7981 | pci_set_drvdata(pdev, NULL); | |
7982 | ||
bf85ea4f | 7983 | iwl_free_channel_map(priv); |
849e0dce | 7984 | iwl4965_free_geos(priv); |
b481de9c ZY |
7985 | |
7986 | if (priv->ibss_beacon) | |
7987 | dev_kfree_skb(priv->ibss_beacon); | |
7988 | ||
7989 | ieee80211_free_hw(priv->hw); | |
7990 | } | |
7991 | ||
7992 | #ifdef CONFIG_PM | |
7993 | ||
bb8c093b | 7994 | static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 7995 | { |
c79dd5b5 | 7996 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 7997 | |
e655b9f0 ZY |
7998 | if (priv->is_open) { |
7999 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
8000 | iwl4965_mac_stop(priv->hw); | |
8001 | priv->is_open = 1; | |
8002 | } | |
b481de9c | 8003 | |
b481de9c ZY |
8004 | pci_set_power_state(pdev, PCI_D3hot); |
8005 | ||
b481de9c ZY |
8006 | return 0; |
8007 | } | |
8008 | ||
bb8c093b | 8009 | static int iwl4965_pci_resume(struct pci_dev *pdev) |
b481de9c | 8010 | { |
c79dd5b5 | 8011 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8012 | |
b481de9c | 8013 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8014 | |
e655b9f0 ZY |
8015 | if (priv->is_open) |
8016 | iwl4965_mac_start(priv->hw); | |
b481de9c | 8017 | |
e655b9f0 | 8018 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8019 | return 0; |
8020 | } | |
8021 | ||
8022 | #endif /* CONFIG_PM */ | |
8023 | ||
8024 | /***************************************************************************** | |
8025 | * | |
8026 | * driver and module entry point | |
8027 | * | |
8028 | *****************************************************************************/ | |
8029 | ||
bb8c093b | 8030 | static struct pci_driver iwl4965_driver = { |
b481de9c | 8031 | .name = DRV_NAME, |
bb8c093b CH |
8032 | .id_table = iwl4965_hw_card_ids, |
8033 | .probe = iwl4965_pci_probe, | |
8034 | .remove = __devexit_p(iwl4965_pci_remove), | |
b481de9c | 8035 | #ifdef CONFIG_PM |
bb8c093b CH |
8036 | .suspend = iwl4965_pci_suspend, |
8037 | .resume = iwl4965_pci_resume, | |
b481de9c ZY |
8038 | #endif |
8039 | }; | |
8040 | ||
bb8c093b | 8041 | static int __init iwl4965_init(void) |
b481de9c ZY |
8042 | { |
8043 | ||
8044 | int ret; | |
8045 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8046 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
8047 | |
8048 | ret = iwl4965_rate_control_register(); | |
8049 | if (ret) { | |
8050 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); | |
8051 | return ret; | |
8052 | } | |
8053 | ||
bb8c093b | 8054 | ret = pci_register_driver(&iwl4965_driver); |
b481de9c ZY |
8055 | if (ret) { |
8056 | IWL_ERROR("Unable to initialize PCI module\n"); | |
897e1cf2 | 8057 | goto error_register; |
b481de9c | 8058 | } |
0a6857e7 | 8059 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 8060 | ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level); |
b481de9c ZY |
8061 | if (ret) { |
8062 | IWL_ERROR("Unable to create driver sysfs file\n"); | |
897e1cf2 | 8063 | goto error_debug; |
b481de9c ZY |
8064 | } |
8065 | #endif | |
8066 | ||
8067 | return ret; | |
897e1cf2 RC |
8068 | |
8069 | #ifdef CONFIG_IWLWIFI_DEBUG | |
8070 | error_debug: | |
8071 | pci_unregister_driver(&iwl4965_driver); | |
8072 | #endif | |
8073 | error_register: | |
8074 | iwl4965_rate_control_unregister(); | |
8075 | return ret; | |
b481de9c ZY |
8076 | } |
8077 | ||
bb8c093b | 8078 | static void __exit iwl4965_exit(void) |
b481de9c | 8079 | { |
0a6857e7 | 8080 | #ifdef CONFIG_IWLWIFI_DEBUG |
bb8c093b | 8081 | driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level); |
b481de9c | 8082 | #endif |
bb8c093b | 8083 | pci_unregister_driver(&iwl4965_driver); |
897e1cf2 | 8084 | iwl4965_rate_control_unregister(); |
b481de9c ZY |
8085 | } |
8086 | ||
bb8c093b CH |
8087 | module_exit(iwl4965_exit); |
8088 | module_init(iwl4965_init); |