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iwlwifi: pcie: New RBD allocation model
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / iwlwifi / mvm / fw.c
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8ca151b5
JB		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
8ca151b5
JB		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
8ca151b5
JB		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
8d193ca2 35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
8ca151b5
JB		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65#include <net/mac80211.h>
66
67#include "iwl-trans.h"
68#include "iwl-op-mode.h"
69#include "iwl-fw.h"
70#include "iwl-debug.h"
71#include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
72#include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
8c23f95c 73#include "iwl-prph.h"
8ca151b5
JB		 74#include "iwl-eeprom-parse.h"
75
76#include "mvm.h"
77#include "iwl-phy-db.h"
78
79#define MVM_UCODE_ALIVE_TIMEOUT HZ
80#define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
81
82#define UCODE_VALID_OK cpu_to_le32(0x1)
83
8ca151b5
JB		 84struct iwl_mvm_alive_data {
85 bool valid;
86 u32 scd_base_addr;
87};
88
89static inline const struct fw_img *
90iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type)
91{
92 if (ucode_type >= IWL_UCODE_TYPE_MAX)
93 return NULL;
94
95 return &mvm->fw->img[ucode_type];
96}
97
98static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
99{
100 struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
101 .valid = cpu_to_le32(valid_tx_ant),
102 };
103
33223542 104 IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
a1022927 105 return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
8ca151b5
JB		 106 sizeof(tx_ant_cmd), &tx_ant_cmd);
107}
108
a6c4fb44
MG		 109static void iwl_free_fw_paging(struct iwl_mvm *mvm)
110{
111 int i;
112
113 if (!mvm->fw_paging_db[0].fw_paging_block)
114 return;
115
116 for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
117 if (!mvm->fw_paging_db[i].fw_paging_block) {
118 IWL_DEBUG_FW(mvm,
119 "Paging: block %d already freed, continue to next page\n",
120 i);
121
122 continue;
123 }
124
125 __free_pages(mvm->fw_paging_db[i].fw_paging_block,
126 get_order(mvm->fw_paging_db[i].fw_paging_size));
127 }
128 memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
129}
130
131static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
132{
133 int sec_idx, idx;
134 u32 offset = 0;
135
136 /*
137 * find where is the paging image start point:
138 * if CPU2 exist and it's in paging format, then the image looks like:
139 * CPU1 sections (2 or more)
140 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
141 * CPU2 sections (not paged)
142 * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
143 * non paged to CPU2 paging sec
144 * CPU2 paging CSS
145 * CPU2 paging image (including instruction and data)
146 */
147 for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
148 if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
149 sec_idx++;
150 break;
151 }
152 }
153
154 if (sec_idx >= IWL_UCODE_SECTION_MAX) {
155 IWL_ERR(mvm, "driver didn't find paging image\n");
156 iwl_free_fw_paging(mvm);
157 return -EINVAL;
158 }
159
160 /* copy the CSS block to the dram */
161 IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
162 sec_idx);
163
164 memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
165 image->sec[sec_idx].data,
166 mvm->fw_paging_db[0].fw_paging_size);
167
168 IWL_DEBUG_FW(mvm,
169 "Paging: copied %d CSS bytes to first block\n",
170 mvm->fw_paging_db[0].fw_paging_size);
171
172 sec_idx++;
173
174 /*
175 * copy the paging blocks to the dram
176 * loop index start from 1 since that CSS block already copied to dram
177 * and CSS index is 0.
178 * loop stop at num_of_paging_blk since that last block is not full.
179 */
180 for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
181 memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
182 image->sec[sec_idx].data + offset,
183 mvm->fw_paging_db[idx].fw_paging_size);
184
185 IWL_DEBUG_FW(mvm,
186 "Paging: copied %d paging bytes to block %d\n",
187 mvm->fw_paging_db[idx].fw_paging_size,
188 idx);
189
190 offset += mvm->fw_paging_db[idx].fw_paging_size;
191 }
192
193 /* copy the last paging block */
194 if (mvm->num_of_pages_in_last_blk > 0) {
195 memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
196 image->sec[sec_idx].data + offset,
197 FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
198
199 IWL_DEBUG_FW(mvm,
200 "Paging: copied %d pages in the last block %d\n",
201 mvm->num_of_pages_in_last_blk, idx);
202 }
203
204 return 0;
205}
206
207static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
208 const struct fw_img *image)
209{
210 struct page *block;
211 dma_addr_t phys = 0;
212 int blk_idx = 0;
213 int order, num_of_pages;
214 int dma_enabled;
215
216 if (mvm->fw_paging_db[0].fw_paging_block)
217 return 0;
218
219 dma_enabled = is_device_dma_capable(mvm->trans->dev);
220
221 /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
222 BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
223
224 num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
225 mvm->num_of_paging_blk = ((num_of_pages - 1) /
226 NUM_OF_PAGE_PER_GROUP) + 1;
227
228 mvm->num_of_pages_in_last_blk =
229 num_of_pages -
230 NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
231
232 IWL_DEBUG_FW(mvm,
233 "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
234 mvm->num_of_paging_blk,
235 mvm->num_of_pages_in_last_blk);
236
237 /* allocate block of 4Kbytes for paging CSS */
238 order = get_order(FW_PAGING_SIZE);
239 block = alloc_pages(GFP_KERNEL, order);
240 if (!block) {
241 /* free all the previous pages since we failed */
242 iwl_free_fw_paging(mvm);
243 return -ENOMEM;
244 }
245
246 mvm->fw_paging_db[blk_idx].fw_paging_block = block;
247 mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
248
249 if (dma_enabled) {
250 phys = dma_map_page(mvm->trans->dev, block, 0,
251 PAGE_SIZE << order, DMA_BIDIRECTIONAL);
252 if (dma_mapping_error(mvm->trans->dev, phys)) {
253 /*
254 * free the previous pages and the current one since
255 * we failed to map_page.
256 */
257 iwl_free_fw_paging(mvm);
258 return -ENOMEM;
259 }
260 mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
261 }
262
263 IWL_DEBUG_FW(mvm,
264 "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
265 order);
266
267 /*
268 * allocate blocks in dram.
269 * since that CSS allocated in fw_paging_db[0] loop start from index 1
270 */
271 for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
272 /* allocate block of PAGING_BLOCK_SIZE (32K) */
273 order = get_order(PAGING_BLOCK_SIZE);
274 block = alloc_pages(GFP_KERNEL, order);
275 if (!block) {
276 /* free all the previous pages since we failed */
277 iwl_free_fw_paging(mvm);
278 return -ENOMEM;
279 }
280
281 mvm->fw_paging_db[blk_idx].fw_paging_block = block;
282 mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
283
284 if (dma_enabled) {
285 phys = dma_map_page(mvm->trans->dev, block, 0,
286 PAGE_SIZE << order,
287 DMA_BIDIRECTIONAL);
288 if (dma_mapping_error(mvm->trans->dev, phys)) {
289 /*
290 * free the previous pages and the current one
291 * since we failed to map_page.
292 */
293 iwl_free_fw_paging(mvm);
294 return -ENOMEM;
295 }
296 mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
297 }
298
299 IWL_DEBUG_FW(mvm,
300 "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
301 order);
302 }
303
304 return 0;
305}
306
307static int iwl_save_fw_paging(struct iwl_mvm *mvm,
308 const struct fw_img *fw)
309{
310 int ret;
311
312 ret = iwl_alloc_fw_paging_mem(mvm, fw);
313 if (ret)
314 return ret;
315
316 return iwl_fill_paging_mem(mvm, fw);
317}
318
319/* send paging cmd to FW in case CPU2 has paging image */
320static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
321{
322 int blk_idx;
323 __le32 dev_phy_addr;
324 struct iwl_fw_paging_cmd fw_paging_cmd = {
325 .flags =
326 cpu_to_le32(PAGING_CMD_IS_SECURED |
327 PAGING_CMD_IS_ENABLED |
328 (mvm->num_of_pages_in_last_blk <<
329 PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
330 .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
331 .block_num = cpu_to_le32(mvm->num_of_paging_blk),
332 };
333
334 /* loop for for all paging blocks + CSS block */
335 for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
336 dev_phy_addr =
337 cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >>
338 PAGE_2_EXP_SIZE);
339 fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr;
340 }
341
342 return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
343 IWL_ALWAYS_LONG_GROUP, 0),
344 0, sizeof(fw_paging_cmd), &fw_paging_cmd);
345}
346
8ca151b5
JB		 347static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
348 struct iwl_rx_packet *pkt, void *data)
349{
350 struct iwl_mvm *mvm =
351 container_of(notif_wait, struct iwl_mvm, notif_wait);
352 struct iwl_mvm_alive_data *alive_data = data;
7e1223b5 353 struct mvm_alive_resp_ver1 *palive1;
01a9ca51 354 struct mvm_alive_resp_ver2 *palive2;
7e1223b5 355 struct mvm_alive_resp *palive;
01a9ca51 356
7e1223b5
EG		 357 if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
358 palive1 = (void *)pkt->data;
01a9ca51
EH		 359
360 mvm->support_umac_log = false;
361 mvm->error_event_table =
7e1223b5
EG		 362 le32_to_cpu(palive1->error_event_table_ptr);
363 mvm->log_event_table =
364 le32_to_cpu(palive1->log_event_table_ptr);
365 alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
01a9ca51 366
7e1223b5 367 alive_data->valid = le16_to_cpu(palive1->status) ==
01a9ca51
EH		 368 IWL_ALIVE_STATUS_OK;
369 IWL_DEBUG_FW(mvm,
370 "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
7e1223b5
EG		 371 le16_to_cpu(palive1->status), palive1->ver_type,
372 palive1->ver_subtype, palive1->flags);
373 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
01a9ca51
EH		 374 palive2 = (void *)pkt->data;
375
01a9ca51
EH		 376 mvm->error_event_table =
377 le32_to_cpu(palive2->error_event_table_ptr);
378 mvm->log_event_table =
379 le32_to_cpu(palive2->log_event_table_ptr);
380 alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
381 mvm->umac_error_event_table =
382 le32_to_cpu(palive2->error_info_addr);
91479b64
EH		 383 mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
384 mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
01a9ca51
EH		 385
386 alive_data->valid = le16_to_cpu(palive2->status) ==
387 IWL_ALIVE_STATUS_OK;
ffa70264
EG		 388 if (mvm->umac_error_event_table)
389 mvm->support_umac_log = true;
390
01a9ca51
EH		 391 IWL_DEBUG_FW(mvm,
392 "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
393 le16_to_cpu(palive2->status), palive2->ver_type,
394 palive2->ver_subtype, palive2->flags);
395
396 IWL_DEBUG_FW(mvm,
397 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
398 palive2->umac_major, palive2->umac_minor);
7e1223b5
EG		 399 } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
400 palive = (void *)pkt->data;
401
402 mvm->error_event_table =
403 le32_to_cpu(palive->error_event_table_ptr);
404 mvm->log_event_table =
405 le32_to_cpu(palive->log_event_table_ptr);
406 alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
407 mvm->umac_error_event_table =
408 le32_to_cpu(palive->error_info_addr);
409 mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
410 mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
411
412 alive_data->valid = le16_to_cpu(palive->status) ==
413 IWL_ALIVE_STATUS_OK;
414 if (mvm->umac_error_event_table)
415 mvm->support_umac_log = true;
416
417 IWL_DEBUG_FW(mvm,
418 "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
419 le16_to_cpu(palive->status), palive->ver_type,
420 palive->ver_subtype, palive->flags);
421
422 IWL_DEBUG_FW(mvm,
423 "UMAC version: Major - 0x%x, Minor - 0x%x\n",
424 le32_to_cpu(palive->umac_major),
425 le32_to_cpu(palive->umac_minor));
01a9ca51 426 }
8ca151b5
JB		 427
428 return true;
429}
430
431static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
432 struct iwl_rx_packet *pkt, void *data)
433{
434 struct iwl_phy_db *phy_db = data;
435
436 if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
437 WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
438 return true;
439 }
440
441 WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC));
442
443 return false;
444}
445
446static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
447 enum iwl_ucode_type ucode_type)
448{
449 struct iwl_notification_wait alive_wait;
450 struct iwl_mvm_alive_data alive_data;
451 const struct fw_img *fw;
452 int ret, i;
453 enum iwl_ucode_type old_type = mvm->cur_ucode;
6eb031d2 454 static const u16 alive_cmd[] = { MVM_ALIVE };
91479b64 455 struct iwl_sf_region st_fwrd_space;
8ca151b5 456
61df750c 457 if (ucode_type == IWL_UCODE_REGULAR &&
d2709ad7 458 iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE))
61df750c
EH		 459 fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER);
460 else
461 fw = iwl_get_ucode_image(mvm, ucode_type);
befe9b6f 462 if (WARN_ON(!fw))
8ca151b5 463 return -EINVAL;
befe9b6f
JB		 464 mvm->cur_ucode = ucode_type;
465 mvm->ucode_loaded = false;
8ca151b5
JB		 466
467 iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
468 alive_cmd, ARRAY_SIZE(alive_cmd),
469 iwl_alive_fn, &alive_data);
470
471 ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
472 if (ret) {
473 mvm->cur_ucode = old_type;
474 iwl_remove_notification(&mvm->notif_wait, &alive_wait);
475 return ret;
476 }
477
478 /*
479 * Some things may run in the background now, but we
480 * just wait for the ALIVE notification here.
481 */
482 ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
483 MVM_UCODE_ALIVE_TIMEOUT);
484 if (ret) {
192de2b4
DS		 485 if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
486 IWL_ERR(mvm,
487 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
488 iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
489 iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
8ca151b5
JB		 490 mvm->cur_ucode = old_type;
491 return ret;
492 }
493
494 if (!alive_data.valid) {
495 IWL_ERR(mvm, "Loaded ucode is not valid!\n");
496 mvm->cur_ucode = old_type;
497 return -EIO;
498 }
499
91479b64
EH		 500 /*
501 * update the sdio allocation according to the pointer we get in the
502 * alive notification.
503 */
504 st_fwrd_space.addr = mvm->sf_space.addr;
505 st_fwrd_space.size = mvm->sf_space.size;
506 ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
82e8aea0
ES		 507 if (ret) {
508 IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
509 return ret;
510 }
91479b64 511
8ca151b5
JB		 512 iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
513
a6c4fb44
MG		 514 /*
515 * configure and operate fw paging mechanism.
516 * driver configures the paging flow only once, CPU2 paging image
517 * included in the IWL_UCODE_INIT image.
518 */
519 if (fw->paging_mem_size) {
520 ret = iwl_save_fw_paging(mvm, fw);
521 if (ret) {
522 IWL_ERR(mvm, "failed to save the FW paging image\n");
523 return ret;
524 }
525
526 ret = iwl_send_paging_cmd(mvm, fw);
527 if (ret) {
528 IWL_ERR(mvm, "failed to send the paging cmd\n");
529 iwl_free_fw_paging(mvm);
530 return ret;
531 }
532 }
533
8ca151b5
JB		 534 /*
535 * Note: all the queues are enabled as part of the interface
536 * initialization, but in firmware restart scenarios they
537 * could be stopped, so wake them up. In firmware restart,
538 * mac80211 will have the queues stopped as well until the
539 * reconfiguration completes. During normal startup, they
540 * will be empty.
541 */
542
543 for (i = 0; i < IWL_MAX_HW_QUEUES; i++) {
19e737c9 544 if (i < mvm->first_agg_queue && i != IWL_MVM_CMD_QUEUE)
8ca151b5
JB		 545 mvm->queue_to_mac80211[i] = i;
546 else
547 mvm->queue_to_mac80211[i] = IWL_INVALID_MAC80211_QUEUE;
8ca151b5
JB		 548 }
549
df197c00
JB		 550 for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
551 atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
8ca151b5
JB		 552
553 mvm->ucode_loaded = true;
554
555 return 0;
556}
8ca151b5
JB		 557
558static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
559{
560 struct iwl_phy_cfg_cmd phy_cfg_cmd;
561 enum iwl_ucode_type ucode_type = mvm->cur_ucode;
562
563 /* Set parameters */
a0544272 564 phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
8ca151b5
JB		 565 phy_cfg_cmd.calib_control.event_trigger =
566 mvm->fw->default_calib[ucode_type].event_trigger;
567 phy_cfg_cmd.calib_control.flow_trigger =
568 mvm->fw->default_calib[ucode_type].flow_trigger;
569
570 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
571 phy_cfg_cmd.phy_cfg);
572
a1022927 573 return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
8ca151b5
JB		 574 sizeof(phy_cfg_cmd), &phy_cfg_cmd);
575}
576
8ca151b5
JB		 577int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
578{
579 struct iwl_notification_wait calib_wait;
6eb031d2 580 static const u16 init_complete[] = {
8ca151b5
JB		 581 INIT_COMPLETE_NOTIF,
582 CALIB_RES_NOTIF_PHY_DB
583 };
584 int ret;
585
586 lockdep_assert_held(&mvm->mutex);
587
8d193ca2 588 if (WARN_ON_ONCE(mvm->calibrating))
8ca151b5
JB		 589 return 0;
590
591 iwl_init_notification_wait(&mvm->notif_wait,
592 &calib_wait,
593 init_complete,
594 ARRAY_SIZE(init_complete),
595 iwl_wait_phy_db_entry,
596 mvm->phy_db);
597
598 /* Will also start the device */
599 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
600 if (ret) {
601 IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
602 goto error;
603 }
604
ae397472 605 ret = iwl_send_bt_init_conf(mvm);
931d4160
EG		 606 if (ret)
607 goto error;
608
81a67e32 609 /* Read the NVM only at driver load time, no need to do this twice */
8ca151b5
JB		 610 if (read_nvm) {
611 /* Read nvm */
14b485f0 612 ret = iwl_nvm_init(mvm, true);
8ca151b5
JB		 613 if (ret) {
614 IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
615 goto error;
616 }
617 }
618
81a67e32 619 /* In case we read the NVM from external file, load it to the NIC */
e02a9d60 620 if (mvm->nvm_file_name)
81a67e32
EL		 621 iwl_mvm_load_nvm_to_nic(mvm);
622
8ca151b5
JB		 623 ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
624 WARN_ON(ret);
625
4f59334b
EH		 626 /*
627 * abort after reading the nvm in case RF Kill is on, we will complete
628 * the init seq later when RF kill will switch to off
629 */
9ee718aa 630 if (iwl_mvm_is_radio_killed(mvm)) {
4f59334b
EH		 631 IWL_DEBUG_RF_KILL(mvm,
632 "jump over all phy activities due to RF kill\n");
633 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
a4082843
AN		 634 ret = 1;
635 goto out;
4f59334b
EH		 636 }
637
31b8b343
EG		 638 mvm->calibrating = true;
639
e07cbb53 640 /* Send TX valid antennas before triggering calibrations */
a0544272 641 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
e07cbb53
DS		 642 if (ret)
643 goto error;
644
8ca151b5
JB		 645 /*
646 * Send phy configurations command to init uCode
647 * to start the 16.0 uCode init image internal calibrations.
648 */
649 ret = iwl_send_phy_cfg_cmd(mvm);
650 if (ret) {
651 IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
652 ret);
653 goto error;
654 }
655
656 /*
657 * Some things may run in the background now, but we
658 * just wait for the calibration complete notification.
659 */
660 ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
661 MVM_UCODE_CALIB_TIMEOUT);
31b8b343
EG		 662
663 if (ret && iwl_mvm_is_radio_killed(mvm)) {
664 IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
665 ret = 1;
666 }
8ca151b5
JB		 667 goto out;
668
669error:
670 iwl_remove_notification(&mvm->notif_wait, &calib_wait);
671out:
31b8b343 672 mvm->calibrating = false;
a4082843 673 if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
8ca151b5
JB		 674 /* we want to debug INIT and we have no NVM - fake */
675 mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
676 sizeof(struct ieee80211_channel) +
677 sizeof(struct ieee80211_rate),
678 GFP_KERNEL);
679 if (!mvm->nvm_data)
680 return -ENOMEM;
8ca151b5
JB		 681 mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
682 mvm->nvm_data->bands[0].n_channels = 1;
683 mvm->nvm_data->bands[0].n_bitrates = 1;
684 mvm->nvm_data->bands[0].bitrates =
685 (void *)mvm->nvm_data->channels + 1;
686 mvm->nvm_data->bands[0].bitrates->hw_value = 10;
687 }
688
689 return ret;
690}
691
04fd2c28
LK		 692static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
693{
694 struct iwl_host_cmd cmd = {
695 .id = SHARED_MEM_CFG,
696 .flags = CMD_WANT_SKB,
697 .data = { NULL, },
698 .len = { 0, },
699 };
700 struct iwl_rx_packet *pkt;
701 struct iwl_shared_mem_cfg *mem_cfg;
702 u32 i;
703
704 lockdep_assert_held(&mvm->mutex);
705
706 if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
707 return;
708
709 pkt = cmd.resp_pkt;
04fd2c28
LK		 710 mem_cfg = (void *)pkt->data;
711
712 mvm->shared_mem_cfg.shared_mem_addr =
713 le32_to_cpu(mem_cfg->shared_mem_addr);
714 mvm->shared_mem_cfg.shared_mem_size =
715 le32_to_cpu(mem_cfg->shared_mem_size);
716 mvm->shared_mem_cfg.sample_buff_addr =
717 le32_to_cpu(mem_cfg->sample_buff_addr);
718 mvm->shared_mem_cfg.sample_buff_size =
719 le32_to_cpu(mem_cfg->sample_buff_size);
720 mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr);
721 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++)
722 mvm->shared_mem_cfg.txfifo_size[i] =
723 le32_to_cpu(mem_cfg->txfifo_size[i]);
724 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
725 mvm->shared_mem_cfg.rxfifo_size[i] =
726 le32_to_cpu(mem_cfg->rxfifo_size[i]);
727 mvm->shared_mem_cfg.page_buff_addr =
728 le32_to_cpu(mem_cfg->page_buff_addr);
729 mvm->shared_mem_cfg.page_buff_size =
730 le32_to_cpu(mem_cfg->page_buff_size);
731 IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
732
04fd2c28
LK		 733 iwl_free_resp(&cmd);
734}
735
b6eaa45a
EG		 736int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
737 struct iwl_mvm_dump_desc *desc,
36fb9017 738 struct iwl_fw_dbg_trigger_tlv *trigger)
8c23f95c 739{
36fb9017
OG		 740 unsigned int delay = 0;
741
742 if (trigger)
743 delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
744
d2709ad7
EG		 745 if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
746 return -EBUSY;
747
b6eaa45a
EG		 748 if (WARN_ON(mvm->fw_dump_desc))
749 iwl_mvm_free_fw_dump_desc(mvm);
750
751 IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
752 le32_to_cpu(desc->trig_desc.type));
753
754 mvm->fw_dump_desc = desc;
36fb9017 755 mvm->fw_dump_trig = trigger;
d2709ad7 756
d2709ad7
EG		 757 queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay);
758
759 return 0;
760}
761
b6eaa45a 762int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
36fb9017
OG		 763 const char *str, size_t len,
764 struct iwl_fw_dbg_trigger_tlv *trigger)
b6eaa45a
EG		 765{
766 struct iwl_mvm_dump_desc *desc;
767
768 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
769 if (!desc)
770 return -ENOMEM;
771
772 desc->len = len;
773 desc->trig_desc.type = cpu_to_le32(trig);
774 memcpy(desc->trig_desc.data, str, len);
775
36fb9017 776 return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
b6eaa45a
EG		 777}
778
d2709ad7 779int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
b6eaa45a 780 struct iwl_fw_dbg_trigger_tlv *trigger,
5d4f929e 781 const char *fmt, ...)
d2709ad7 782{
d2709ad7 783 u16 occurrences = le16_to_cpu(trigger->occurrences);
5d4f929e
JB		 784 int ret, len = 0;
785 char buf[64];
d2709ad7
EG		 786
787 if (!occurrences)
788 return 0;
789
5d4f929e
JB		 790 if (fmt) {
791 va_list ap;
792
793 buf[sizeof(buf) - 1] = '\0';
794
795 va_start(ap, fmt);
796 vsnprintf(buf, sizeof(buf), fmt, ap);
797 va_end(ap);
798
799 /* check for truncation */
800 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
801 buf[sizeof(buf) - 1] = '\0';
802
803 len = strlen(buf) + 1;
804 }
805
36fb9017
OG		 806 ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
807 trigger);
808
d2709ad7
EG		 809 if (ret)
810 return ret;
811
812 trigger->occurrences = cpu_to_le16(occurrences - 1);
813 return 0;
8c23f95c
EG		 814}
815
945d4202
EG		 816static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
817{
818 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
819 iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
820 else
821 iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
822}
823
d2709ad7 824int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
6a951267
LK		 825{
826 u8 *ptr;
827 int ret;
828 int i;
829
830 if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
831 "Invalid configuration %d\n", conf_id))
832 return -EINVAL;
833
945d4202
EG		 834 /* EARLY START - firmware's configuration is hard coded */
835 if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
836 !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
837 conf_id == FW_DBG_START_FROM_ALIVE) {
838 iwl_mvm_restart_early_start(mvm);
839 return 0;
840 }
841
6a951267
LK		 842 if (!mvm->fw->dbg_conf_tlv[conf_id])
843 return -EINVAL;
844
845 if (mvm->fw_dbg_conf != FW_DBG_INVALID)
846 IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
847 mvm->fw_dbg_conf);
848
849 /* Send all HCMDs for configuring the FW debug */
850 ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
851 for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
852 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
853
854 ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
855 le16_to_cpu(cmd->len), cmd->data);
856 if (ret)
857 return ret;
858
859 ptr += sizeof(*cmd);
860 ptr += le16_to_cpu(cmd->len);
861 }
862
863 mvm->fw_dbg_conf = conf_id;
864 return ret;
865}
866
84bfffa9
EG		 867static int iwl_mvm_config_ltr_v1(struct iwl_mvm *mvm)
868{
869 struct iwl_ltr_config_cmd_v1 cmd_v1 = {
870 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
871 };
872
873 if (!mvm->trans->ltr_enabled)
874 return 0;
875
876 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
877 sizeof(cmd_v1), &cmd_v1);
878}
879
880static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
881{
882 struct iwl_ltr_config_cmd cmd = {
883 .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
884 };
885
886 if (!mvm->trans->ltr_enabled)
887 return 0;
888
859d914c 889 if (!fw_has_api(&mvm->fw->ucode_capa, IWL_UCODE_TLV_API_HDC_PHASE_0))
84bfffa9
EG		 890 return iwl_mvm_config_ltr_v1(mvm);
891
892 return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
893 sizeof(cmd), &cmd);
894}
895
8ca151b5
JB		 896int iwl_mvm_up(struct iwl_mvm *mvm)
897{
898 int ret, i;
53a9d61e
IP		 899 struct ieee80211_channel *chan;
900 struct cfg80211_chan_def chandef;
8ca151b5
JB		 901
902 lockdep_assert_held(&mvm->mutex);
903
904 ret = iwl_trans_start_hw(mvm->trans);
905 if (ret)
906 return ret;
907
ff116373
EL		 908 /*
909 * If we haven't completed the run of the init ucode during
910 * module loading, load init ucode now
911 * (for example, if we were in RFKILL)
912 */
8d193ca2
EH		 913 ret = iwl_run_init_mvm_ucode(mvm, false);
914 if (ret && !iwlmvm_mod_params.init_dbg) {
915 IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
916 /* this can't happen */
917 if (WARN_ON(ret > 0))
918 ret = -ERFKILL;
919 goto error;
920 }
921 if (!iwlmvm_mod_params.init_dbg) {
922 /*
923 * Stop and start the transport without entering low power
924 * mode. This will save the state of other components on the
925 * device that are triggered by the INIT firwmare (MFUART).
926 */
927 _iwl_trans_stop_device(mvm->trans, false);
d643c432 928 ret = _iwl_trans_start_hw(mvm->trans, false);
8d193ca2 929 if (ret)
d643c432 930 goto error;
8ca151b5
JB		 931 }
932
933 if (iwlmvm_mod_params.init_dbg)
934 return 0;
935
936 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
937 if (ret) {
938 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
939 goto error;
940 }
941
6c7d32cf 942 iwl_mvm_get_shared_mem_conf(mvm);
04fd2c28 943
1f3b0ff8
LE		 944 ret = iwl_mvm_sf_update(mvm, NULL, false);
945 if (ret)
946 IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
947
6a951267 948 mvm->fw_dbg_conf = FW_DBG_INVALID;
945d4202
EG		 949 /* if we have a destination, assume EARLY START */
950 if (mvm->fw->dbg_dest_tlv)
951 mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
d2709ad7 952 iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
6a951267 953
a0544272 954 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 955 if (ret)
956 goto error;
957
931d4160
EG		 958 ret = iwl_send_bt_init_conf(mvm);
959 if (ret)
960 goto error;
961
8ca151b5
JB		 962 /* Send phy db control command and then phy db calibration*/
963 ret = iwl_send_phy_db_data(mvm->phy_db);
964 if (ret)
965 goto error;
966
967 ret = iwl_send_phy_cfg_cmd(mvm);
968 if (ret)
969 goto error;
970
971 /* init the fw <-> mac80211 STA mapping */
972 for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
973 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
974
1d3c3f63
AN		 975 mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
976
b2b7875b
JB		 977 /* reset quota debouncing buffer - 0xff will yield invalid data */
978 memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
979
8ca151b5
JB		 980 /* Add auxiliary station for scanning */
981 ret = iwl_mvm_add_aux_sta(mvm);
982 if (ret)
983 goto error;
984
53a9d61e
IP		 985 /* Add all the PHY contexts */
986 chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0];
987 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
988 for (i = 0; i < NUM_PHY_CTX; i++) {
989 /*
990 * The channel used here isn't relevant as it's
991 * going to be overwritten in the other flows.
992 * For now use the first channel we have.
993 */
994 ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
995 &chandef, 1, 1);
996 if (ret)
997 goto error;
998 }
8ca151b5 999
0c0e2c71
IY		 1000 /* Initialize tx backoffs to the minimal possible */
1001 iwl_mvm_tt_tx_backoff(mvm, 0);
1002
84bfffa9 1003 WARN_ON(iwl_mvm_config_ltr(mvm));
9180ac50 1004
c1cb92fc 1005 ret = iwl_mvm_power_update_device(mvm);
64b928c4
AB		 1006 if (ret)
1007 goto error;
1008
35af15d1
AN		 1009 /*
1010 * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
1011 * anyway, so don't init MCC.
1012 */
1013 if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
1014 ret = iwl_mvm_init_mcc(mvm);
1015 if (ret)
1016 goto error;
1017 }
90d4f7db 1018
859d914c 1019 if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
d2496221
DS		 1020 ret = iwl_mvm_config_scan(mvm);
1021 if (ret)
1022 goto error;
1023 }
1024
93190fb0
AA		 1025 if (iwl_mvm_is_csum_supported(mvm) &&
1026 mvm->cfg->features & NETIF_F_RXCSUM)
1027 iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
1028
7498cf4c
EP		 1029 /* allow FW/transport low power modes if not during restart */
1030 if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
1031 iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
1032
53a9d61e 1033 IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
8ca151b5
JB		 1034 return 0;
1035 error:
1036 iwl_trans_stop_device(mvm->trans);
1037 return ret;
1038}
1039
1040int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
1041{
1042 int ret, i;
1043
1044 lockdep_assert_held(&mvm->mutex);
1045
1046 ret = iwl_trans_start_hw(mvm->trans);
1047 if (ret)
1048 return ret;
1049
1050 ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
1051 if (ret) {
1052 IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
1053 goto error;
1054 }
1055
a0544272 1056 ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
8ca151b5
JB		 1057 if (ret)
1058 goto error;
1059
1060 /* Send phy db control command and then phy db calibration*/
1061 ret = iwl_send_phy_db_data(mvm->phy_db);
1062 if (ret)
1063 goto error;
1064
1065 ret = iwl_send_phy_cfg_cmd(mvm);
1066 if (ret)
1067 goto error;
1068
1069 /* init the fw <-> mac80211 STA mapping */
1070 for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
1071 RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
1072
1073 /* Add auxiliary station for scanning */
1074 ret = iwl_mvm_add_aux_sta(mvm);
1075 if (ret)
1076 goto error;
1077
1078 return 0;
1079 error:
1080 iwl_trans_stop_device(mvm->trans);
1081 return ret;
1082}
1083
0416841d
JB		 1084void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
1085 struct iwl_rx_cmd_buffer *rxb)
8ca151b5
JB		 1086{
1087 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1088 struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
1089 u32 flags = le32_to_cpu(card_state_notif->flags);
1090
1091 IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
1092 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
1093 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
1094 (flags & CT_KILL_CARD_DISABLED) ?
1095 "Reached" : "Not reached");
8ca151b5
JB		 1096}
1097
0416841d
JB		 1098void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
1099 struct iwl_rx_cmd_buffer *rxb)
30269c12
CRI		 1100{
1101 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1102 struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
1103
1104 IWL_DEBUG_INFO(mvm,
1105 "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
1106 le32_to_cpu(mfuart_notif->installed_ver),
1107 le32_to_cpu(mfuart_notif->external_ver),
1108 le32_to_cpu(mfuart_notif->status),
1109 le32_to_cpu(mfuart_notif->duration));
30269c12 1110}
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