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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
6238b008 | 77 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 78 | #include "dvm/commands.h" |
0439bb62 | 79 | |
c6f600fc | 80 | #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \ |
035f7ff2 | 81 | (((1<<trans->cfg->base_params->num_of_queues) - 1) &\ |
c6f600fc MV |
82 | (~(1<<(trans_pcie)->cmd_queue))) |
83 | ||
5a878bf6 | 84 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 85 | { |
20d3b647 | 86 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 87 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
1042db2a | 88 | struct device *dev = trans->dev; |
c85eb619 | 89 | |
5a878bf6 | 90 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
91 | |
92 | spin_lock_init(&rxq->lock); | |
c85eb619 EG |
93 | |
94 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
95 | return -EINVAL; | |
96 | ||
97 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
84c816da DH |
98 | rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
99 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
100 | if (!rxq->bd) |
101 | goto err_bd; | |
c85eb619 EG |
102 | |
103 | /*Allocate the driver's pointer to receive buffer status */ | |
84c816da DH |
104 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), |
105 | &rxq->rb_stts_dma, GFP_KERNEL); | |
c85eb619 EG |
106 | if (!rxq->rb_stts) |
107 | goto err_rb_stts; | |
c85eb619 EG |
108 | |
109 | return 0; | |
110 | ||
111 | err_rb_stts: | |
a0f6b0a2 | 112 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
20d3b647 | 113 | rxq->bd, rxq->bd_dma); |
c85eb619 EG |
114 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
115 | rxq->bd = NULL; | |
116 | err_bd: | |
117 | return -ENOMEM; | |
118 | } | |
119 | ||
5a878bf6 | 120 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 121 | { |
20d3b647 | 122 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 123 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
a0f6b0a2 | 124 | int i; |
c85eb619 EG |
125 | |
126 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
127 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
128 | /* In the reset function, these buffers may have been allocated | |
129 | * to an SKB, so we need to unmap and free potential storage */ | |
130 | if (rxq->pool[i].page != NULL) { | |
1042db2a | 131 | dma_unmap_page(trans->dev, rxq->pool[i].page_dma, |
20d3b647 JB |
132 | PAGE_SIZE << trans_pcie->rx_page_order, |
133 | DMA_FROM_DEVICE); | |
790428b6 | 134 | __free_pages(rxq->pool[i].page, |
b2cf410c | 135 | trans_pcie->rx_page_order); |
c85eb619 EG |
136 | rxq->pool[i].page = NULL; |
137 | } | |
138 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
139 | } | |
a0f6b0a2 EG |
140 | } |
141 | ||
fd656935 | 142 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
ab697a9f EG |
143 | struct iwl_rx_queue *rxq) |
144 | { | |
b2cf410c | 145 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab697a9f EG |
146 | u32 rb_size; |
147 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
c17d0681 | 148 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
ab697a9f | 149 | |
b2cf410c | 150 | if (trans_pcie->rx_buf_size_8k) |
ab697a9f EG |
151 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; |
152 | else | |
153 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
154 | ||
155 | /* Stop Rx DMA */ | |
1042db2a | 156 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
ab697a9f EG |
157 | |
158 | /* Reset driver's Rx queue write index */ | |
1042db2a | 159 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
ab697a9f EG |
160 | |
161 | /* Tell device where to find RBD circular buffer in DRAM */ | |
1042db2a | 162 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
ab697a9f EG |
163 | (u32)(rxq->bd_dma >> 8)); |
164 | ||
165 | /* Tell device where in DRAM to update its Rx status */ | |
1042db2a | 166 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG, |
ab697a9f EG |
167 | rxq->rb_stts_dma >> 4); |
168 | ||
169 | /* Enable Rx DMA | |
170 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
171 | * the credit mechanism in 5000 HW RX FIFO | |
172 | * Direct rx interrupts to hosts | |
173 | * Rx buffer size 4 or 8k | |
174 | * RB timeout 0x10 | |
175 | * 256 RBDs | |
176 | */ | |
1042db2a | 177 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
ab697a9f EG |
178 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
179 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
180 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
ab697a9f EG |
181 | rb_size| |
182 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
183 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
184 | ||
185 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
1042db2a | 186 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
ab697a9f EG |
187 | } |
188 | ||
5a878bf6 | 189 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 190 | { |
20d3b647 | 191 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 EG |
192 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
193 | ||
a0f6b0a2 EG |
194 | int i, err; |
195 | unsigned long flags; | |
196 | ||
197 | if (!rxq->bd) { | |
5a878bf6 | 198 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
199 | if (err) |
200 | return err; | |
201 | } | |
202 | ||
203 | spin_lock_irqsave(&rxq->lock, flags); | |
204 | INIT_LIST_HEAD(&rxq->rx_free); | |
205 | INIT_LIST_HEAD(&rxq->rx_used); | |
206 | ||
5a878bf6 | 207 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
208 | |
209 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
210 | rxq->queue[i] = NULL; | |
211 | ||
212 | /* Set us so that we have processed and used all buffers, but have | |
213 | * not restocked the Rx queue with fresh buffers */ | |
214 | rxq->read = rxq->write = 0; | |
215 | rxq->write_actual = 0; | |
216 | rxq->free_count = 0; | |
217 | spin_unlock_irqrestore(&rxq->lock, flags); | |
218 | ||
358a46d4 | 219 | iwl_rx_replenish(trans); |
ab697a9f | 220 | |
fd656935 | 221 | iwl_trans_rx_hw_init(trans, rxq); |
ab697a9f | 222 | |
7b11488f | 223 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f | 224 | rxq->need_update = 1; |
5a878bf6 | 225 | iwl_rx_queue_update_write_ptr(trans, rxq); |
7b11488f | 226 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f | 227 | |
c85eb619 EG |
228 | return 0; |
229 | } | |
230 | ||
5a878bf6 | 231 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 232 | { |
20d3b647 | 233 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 234 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
a0f6b0a2 EG |
235 | unsigned long flags; |
236 | ||
237 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
238 | * exit now */ | |
239 | if (!rxq->bd) { | |
5a878bf6 | 240 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
241 | return; |
242 | } | |
243 | ||
244 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 245 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
246 | spin_unlock_irqrestore(&rxq->lock, flags); |
247 | ||
1042db2a | 248 | dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
249 | rxq->bd, rxq->bd_dma); |
250 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
251 | rxq->bd = NULL; | |
252 | ||
253 | if (rxq->rb_stts) | |
1042db2a | 254 | dma_free_coherent(trans->dev, |
a0f6b0a2 EG |
255 | sizeof(struct iwl_rb_status), |
256 | rxq->rb_stts, rxq->rb_stts_dma); | |
257 | else | |
5a878bf6 | 258 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
259 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
260 | rxq->rb_stts = NULL; | |
261 | } | |
262 | ||
6d8f6eeb | 263 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
c2c52e8b EG |
264 | { |
265 | ||
266 | /* stop Rx DMA */ | |
1042db2a EG |
267 | iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
268 | return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG, | |
20d3b647 | 269 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
c2c52e8b EG |
270 | } |
271 | ||
20d3b647 JB |
272 | static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
273 | struct iwl_dma_ptr *ptr, size_t size) | |
02aca585 EG |
274 | { |
275 | if (WARN_ON(ptr->addr)) | |
276 | return -EINVAL; | |
277 | ||
1042db2a | 278 | ptr->addr = dma_alloc_coherent(trans->dev, size, |
02aca585 EG |
279 | &ptr->dma, GFP_KERNEL); |
280 | if (!ptr->addr) | |
281 | return -ENOMEM; | |
282 | ptr->size = size; | |
283 | return 0; | |
284 | } | |
285 | ||
20d3b647 JB |
286 | static void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
287 | struct iwl_dma_ptr *ptr) | |
1359ca4f EG |
288 | { |
289 | if (unlikely(!ptr->addr)) | |
290 | return; | |
291 | ||
1042db2a | 292 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
293 | memset(ptr, 0, sizeof(*ptr)); |
294 | } | |
295 | ||
7c5ba4a8 JB |
296 | static void iwl_trans_pcie_queue_stuck_timer(unsigned long data) |
297 | { | |
298 | struct iwl_tx_queue *txq = (void *)data; | |
e9d364de | 299 | struct iwl_queue *q = &txq->q; |
7c5ba4a8 JB |
300 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; |
301 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
f22d3328 | 302 | u32 scd_sram_addr = trans_pcie->scd_base_addr + |
0adb52de | 303 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); |
f22d3328 EG |
304 | u8 buf[16]; |
305 | int i; | |
7c5ba4a8 JB |
306 | |
307 | spin_lock(&txq->lock); | |
308 | /* check if triggered erroneously */ | |
309 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
310 | spin_unlock(&txq->lock); | |
311 | return; | |
312 | } | |
313 | spin_unlock(&txq->lock); | |
314 | ||
7c5ba4a8 JB |
315 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, |
316 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
317 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
318 | txq->q.read_ptr, txq->q.write_ptr); | |
7c5ba4a8 | 319 | |
f22d3328 EG |
320 | iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
321 | ||
322 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
323 | ||
324 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
325 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
326 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
327 | ||
12af0468 EG |
328 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { |
329 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
330 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
331 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
332 | u32 tbl_dw = | |
333 | iwl_read_targ_mem(trans, | |
334 | trans_pcie->scd_base_addr + | |
335 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
336 | ||
337 | if (i & 0x1) | |
338 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
339 | else | |
340 | tbl_dw = tbl_dw & 0x0000FFFF; | |
341 | ||
342 | IWL_ERR(trans, | |
343 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
344 | i, active ? "" : "in", fifo, tbl_dw, | |
345 | iwl_read_prph(trans, | |
346 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
347 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
348 | } | |
7c5ba4a8 | 349 | |
e9d364de EG |
350 | for (i = q->read_ptr; i != q->write_ptr; |
351 | i = iwl_queue_inc_wrap(i, q->n_bd)) { | |
352 | struct iwl_tx_cmd *tx_cmd = | |
353 | (struct iwl_tx_cmd *)txq->entries[i].cmd->payload; | |
354 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, | |
355 | get_unaligned_le32(&tx_cmd->scratch)); | |
356 | } | |
357 | ||
7c5ba4a8 JB |
358 | iwl_op_mode_nic_error(trans->op_mode); |
359 | } | |
360 | ||
6d8f6eeb | 361 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
20d3b647 JB |
362 | struct iwl_tx_queue *txq, int slots_num, |
363 | u32 txq_id) | |
02aca585 | 364 | { |
20d3b647 | 365 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab9e212e | 366 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
02aca585 EG |
367 | int i; |
368 | ||
bf8440e6 | 369 | if (WARN_ON(txq->entries || txq->tfds)) |
02aca585 EG |
370 | return -EINVAL; |
371 | ||
7c5ba4a8 JB |
372 | setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer, |
373 | (unsigned long)txq); | |
374 | txq->trans_pcie = trans_pcie; | |
375 | ||
1359ca4f EG |
376 | txq->q.n_window = slots_num; |
377 | ||
bf8440e6 JB |
378 | txq->entries = kcalloc(slots_num, |
379 | sizeof(struct iwl_pcie_tx_queue_entry), | |
380 | GFP_KERNEL); | |
02aca585 | 381 | |
bf8440e6 | 382 | if (!txq->entries) |
02aca585 EG |
383 | goto error; |
384 | ||
c6f600fc | 385 | if (txq_id == trans_pcie->cmd_queue) |
dfa2bdba | 386 | for (i = 0; i < slots_num; i++) { |
bf8440e6 JB |
387 | txq->entries[i].cmd = |
388 | kmalloc(sizeof(struct iwl_device_cmd), | |
389 | GFP_KERNEL); | |
390 | if (!txq->entries[i].cmd) | |
dfa2bdba EG |
391 | goto error; |
392 | } | |
02aca585 | 393 | |
02aca585 EG |
394 | /* Circular buffer of transmit frame descriptors (TFDs), |
395 | * shared with device */ | |
1042db2a | 396 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, |
6d8f6eeb | 397 | &txq->q.dma_addr, GFP_KERNEL); |
02aca585 | 398 | if (!txq->tfds) { |
6d8f6eeb | 399 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
02aca585 EG |
400 | goto error; |
401 | } | |
402 | txq->q.id = txq_id; | |
403 | ||
404 | return 0; | |
405 | error: | |
bf8440e6 | 406 | if (txq->entries && txq_id == trans_pcie->cmd_queue) |
02aca585 | 407 | for (i = 0; i < slots_num; i++) |
bf8440e6 JB |
408 | kfree(txq->entries[i].cmd); |
409 | kfree(txq->entries); | |
410 | txq->entries = NULL; | |
02aca585 EG |
411 | |
412 | return -ENOMEM; | |
413 | ||
414 | } | |
415 | ||
6d8f6eeb | 416 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
9eae88fa | 417 | int slots_num, u32 txq_id) |
02aca585 EG |
418 | { |
419 | int ret; | |
420 | ||
421 | txq->need_update = 0; | |
02aca585 | 422 | |
02aca585 EG |
423 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
424 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
425 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
426 | ||
427 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
6d8f6eeb | 428 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
02aca585 EG |
429 | txq_id); |
430 | if (ret) | |
431 | return ret; | |
432 | ||
015c15e1 JB |
433 | spin_lock_init(&txq->lock); |
434 | ||
02aca585 EG |
435 | /* |
436 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
437 | * given Tx queue, and enable the DMA channel used for that queue. | |
438 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
1042db2a | 439 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), |
02aca585 EG |
440 | txq->q.dma_addr >> 8); |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
c170b867 EG |
445 | /** |
446 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
447 | */ | |
6d8f6eeb | 448 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
c170b867 | 449 | { |
8ad71bef EG |
450 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
451 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
c170b867 | 452 | struct iwl_queue *q = &txq->q; |
39644e9a | 453 | enum dma_data_direction dma_dir; |
c170b867 EG |
454 | |
455 | if (!q->n_bd) | |
456 | return; | |
457 | ||
39644e9a EG |
458 | /* In the command queue, all the TBs are mapped as BIDI |
459 | * so unmap them as such. | |
460 | */ | |
c6f600fc | 461 | if (txq_id == trans_pcie->cmd_queue) |
39644e9a | 462 | dma_dir = DMA_BIDIRECTIONAL; |
015c15e1 | 463 | else |
39644e9a EG |
464 | dma_dir = DMA_TO_DEVICE; |
465 | ||
015c15e1 | 466 | spin_lock_bh(&txq->lock); |
c170b867 | 467 | while (q->write_ptr != q->read_ptr) { |
bc2529c3 | 468 | iwl_txq_free_tfd(trans, txq, dma_dir); |
c170b867 EG |
469 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
470 | } | |
015c15e1 | 471 | spin_unlock_bh(&txq->lock); |
c170b867 EG |
472 | } |
473 | ||
1359ca4f EG |
474 | /** |
475 | * iwl_tx_queue_free - Deallocate DMA queue. | |
476 | * @txq: Transmit queue to deallocate. | |
477 | * | |
478 | * Empty queue by removing and destroying all BD's. | |
479 | * Free all buffers. | |
480 | * 0-fill, but do not free "txq" descriptor structure. | |
481 | */ | |
6d8f6eeb | 482 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
1359ca4f | 483 | { |
8ad71bef EG |
484 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
485 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
1042db2a | 486 | struct device *dev = trans->dev; |
1359ca4f | 487 | int i; |
20d3b647 | 488 | |
1359ca4f EG |
489 | if (WARN_ON(!txq)) |
490 | return; | |
491 | ||
6d8f6eeb | 492 | iwl_tx_queue_unmap(trans, txq_id); |
1359ca4f EG |
493 | |
494 | /* De-alloc array of command/tx buffers */ | |
c6f600fc | 495 | if (txq_id == trans_pcie->cmd_queue) |
96791422 | 496 | for (i = 0; i < txq->q.n_window; i++) { |
bf8440e6 | 497 | kfree(txq->entries[i].cmd); |
96791422 EG |
498 | kfree(txq->entries[i].copy_cmd); |
499 | } | |
1359ca4f EG |
500 | |
501 | /* De-alloc circular buffer of TFDs */ | |
502 | if (txq->q.n_bd) { | |
ab9e212e | 503 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
1359ca4f EG |
504 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
505 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
506 | } | |
507 | ||
bf8440e6 JB |
508 | kfree(txq->entries); |
509 | txq->entries = NULL; | |
1359ca4f | 510 | |
7c5ba4a8 JB |
511 | del_timer_sync(&txq->stuck_timer); |
512 | ||
1359ca4f EG |
513 | /* 0-fill queue descriptor structure */ |
514 | memset(txq, 0, sizeof(*txq)); | |
515 | } | |
516 | ||
517 | /** | |
518 | * iwl_trans_tx_free - Free TXQ Context | |
519 | * | |
520 | * Destroy all TX DMA queues and structures | |
521 | */ | |
6d8f6eeb | 522 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
1359ca4f EG |
523 | { |
524 | int txq_id; | |
8ad71bef | 525 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1359ca4f EG |
526 | |
527 | /* Tx queues */ | |
8ad71bef | 528 | if (trans_pcie->txq) { |
d6189124 | 529 | for (txq_id = 0; |
035f7ff2 | 530 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) |
6d8f6eeb | 531 | iwl_tx_queue_free(trans, txq_id); |
1359ca4f EG |
532 | } |
533 | ||
8ad71bef EG |
534 | kfree(trans_pcie->txq); |
535 | trans_pcie->txq = NULL; | |
1359ca4f | 536 | |
9d6b2cb1 | 537 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
1359ca4f | 538 | |
6d8f6eeb | 539 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
540 | } |
541 | ||
02aca585 EG |
542 | /** |
543 | * iwl_trans_tx_alloc - allocate TX context | |
544 | * Allocate all Tx DMA structures and initialize them | |
545 | * | |
546 | * @param priv | |
547 | * @return error code | |
548 | */ | |
6d8f6eeb | 549 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
02aca585 EG |
550 | { |
551 | int ret; | |
552 | int txq_id, slots_num; | |
8ad71bef | 553 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 554 | |
035f7ff2 | 555 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * |
ab9e212e EG |
556 | sizeof(struct iwlagn_scd_bc_tbl); |
557 | ||
02aca585 EG |
558 | /*It is not allowed to alloc twice, so warn when this happens. |
559 | * We cannot rely on the previous allocation, so free and fail */ | |
8ad71bef | 560 | if (WARN_ON(trans_pcie->txq)) { |
02aca585 EG |
561 | ret = -EINVAL; |
562 | goto error; | |
563 | } | |
564 | ||
6d8f6eeb | 565 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
ab9e212e | 566 | scd_bc_tbls_size); |
02aca585 | 567 | if (ret) { |
6d8f6eeb | 568 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
02aca585 EG |
569 | goto error; |
570 | } | |
571 | ||
572 | /* Alloc keep-warm buffer */ | |
9d6b2cb1 | 573 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
02aca585 | 574 | if (ret) { |
6d8f6eeb | 575 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
02aca585 EG |
576 | goto error; |
577 | } | |
578 | ||
035f7ff2 | 579 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, |
7f90dce1 | 580 | sizeof(struct iwl_tx_queue), GFP_KERNEL); |
8ad71bef | 581 | if (!trans_pcie->txq) { |
6d8f6eeb | 582 | IWL_ERR(trans, "Not enough memory for txq\n"); |
02aca585 EG |
583 | ret = ENOMEM; |
584 | goto error; | |
585 | } | |
586 | ||
587 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
035f7ff2 | 588 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
1745e440 | 589 | txq_id++) { |
9ba1947a | 590 | slots_num = (txq_id == trans_pcie->cmd_queue) ? |
02aca585 | 591 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
592 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
593 | slots_num, txq_id); | |
02aca585 | 594 | if (ret) { |
6d8f6eeb | 595 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
02aca585 EG |
596 | goto error; |
597 | } | |
598 | } | |
599 | ||
600 | return 0; | |
601 | ||
602 | error: | |
ae2c30bf | 603 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
604 | |
605 | return ret; | |
606 | } | |
6d8f6eeb | 607 | static int iwl_tx_init(struct iwl_trans *trans) |
02aca585 | 608 | { |
20d3b647 | 609 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 EG |
610 | int ret; |
611 | int txq_id, slots_num; | |
612 | unsigned long flags; | |
613 | bool alloc = false; | |
614 | ||
8ad71bef | 615 | if (!trans_pcie->txq) { |
6d8f6eeb | 616 | ret = iwl_trans_tx_alloc(trans); |
02aca585 EG |
617 | if (ret) |
618 | goto error; | |
619 | alloc = true; | |
620 | } | |
621 | ||
7b11488f | 622 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
02aca585 EG |
623 | |
624 | /* Turn off all Tx DMA fifos */ | |
1042db2a | 625 | iwl_write_prph(trans, SCD_TXFACT, 0); |
02aca585 EG |
626 | |
627 | /* Tell NIC where to find the "keep warm" buffer */ | |
1042db2a | 628 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, |
83ed9015 | 629 | trans_pcie->kw.dma >> 4); |
02aca585 | 630 | |
7b11488f | 631 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
02aca585 EG |
632 | |
633 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
035f7ff2 | 634 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
1745e440 | 635 | txq_id++) { |
9ba1947a | 636 | slots_num = (txq_id == trans_pcie->cmd_queue) ? |
02aca585 | 637 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
638 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
639 | slots_num, txq_id); | |
02aca585 | 640 | if (ret) { |
6d8f6eeb | 641 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
02aca585 EG |
642 | goto error; |
643 | } | |
644 | } | |
645 | ||
646 | return 0; | |
647 | error: | |
648 | /*Upon error, free only if we allocated something */ | |
649 | if (alloc) | |
ae2c30bf | 650 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
651 | return ret; |
652 | } | |
653 | ||
3e10caeb | 654 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
655 | { |
656 | /* | |
657 | * (for documentation purposes) | |
658 | * to set power to V_AUX, do: | |
659 | ||
660 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
1042db2a | 661 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
662 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
663 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
664 | */ | |
665 | ||
1042db2a | 666 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, |
392f8b78 EG |
667 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
668 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
669 | } | |
670 | ||
af634bee EG |
671 | /* PCI registers */ |
672 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
673 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
674 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
675 | ||
676 | static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans) | |
677 | { | |
20d3b647 | 678 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
af634bee | 679 | u16 pci_lnk_ctl; |
af634bee | 680 | |
a7238b37 JL |
681 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, |
682 | &pci_lnk_ctl); | |
af634bee EG |
683 | return pci_lnk_ctl; |
684 | } | |
685 | ||
686 | static void iwl_apm_config(struct iwl_trans *trans) | |
687 | { | |
688 | /* | |
689 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
690 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
691 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
692 | * costs negligible amount of power savings. | |
693 | * If not (unlikely), enable L0S, so there is at least some | |
694 | * power savings, even without L1. | |
695 | */ | |
696 | u16 lctl = iwl_pciexp_link_ctrl(trans); | |
697 | ||
698 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == | |
699 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { | |
700 | /* L1-ASPM enabled; disable(!) L0S */ | |
701 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
702 | dev_printk(KERN_INFO, trans->dev, | |
703 | "L1 Enabled; Disabling L0S\n"); | |
704 | } else { | |
705 | /* L1-ASPM disabled; enable(!) L0S */ | |
706 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
707 | dev_printk(KERN_INFO, trans->dev, | |
708 | "L1 Disabled; Enabling L0S\n"); | |
709 | } | |
f6d0e9be | 710 | trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); |
af634bee EG |
711 | } |
712 | ||
a6c684ee EG |
713 | /* |
714 | * Start up NIC's basic functionality after it has been reset | |
715 | * (e.g. after platform boot, or shutdown via iwl_apm_stop()) | |
716 | * NOTE: This does not load uCode nor start the embedded processor | |
717 | */ | |
718 | static int iwl_apm_init(struct iwl_trans *trans) | |
719 | { | |
83626404 | 720 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
721 | int ret = 0; |
722 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
723 | ||
724 | /* | |
725 | * Use "set_bit" below rather than "write", to preserve any hardware | |
726 | * bits already set by default after reset. | |
727 | */ | |
728 | ||
729 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
730 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 731 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
732 | |
733 | /* | |
734 | * Disable L0s without affecting L1; | |
735 | * don't wait for ICH L0s (ICH bug W/A) | |
736 | */ | |
737 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 738 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
739 | |
740 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
741 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
742 | ||
743 | /* | |
744 | * Enable HAP INTA (interrupt from management bus) to | |
745 | * wake device's PCI Express link L1a -> L0s | |
746 | */ | |
747 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 748 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 749 | |
af634bee | 750 | iwl_apm_config(trans); |
a6c684ee EG |
751 | |
752 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 753 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 754 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 755 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
756 | |
757 | /* | |
758 | * Set "initialization complete" bit to move adapter from | |
759 | * D0U* --> D0A* (powered-up active) state. | |
760 | */ | |
761 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
762 | ||
763 | /* | |
764 | * Wait for clock stabilization; once stabilized, access to | |
765 | * device-internal resources is supported, e.g. iwl_write_prph() | |
766 | * and accesses to uCode SRAM. | |
767 | */ | |
768 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
769 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
770 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
771 | if (ret < 0) { |
772 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
773 | goto out; | |
774 | } | |
775 | ||
776 | /* | |
777 | * Enable DMA clock and wait for it to stabilize. | |
778 | * | |
779 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
780 | * do not disable clocks. This preserves any hardware bits already | |
781 | * set by default in "CLK_CTRL_REG" after reset. | |
782 | */ | |
783 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
784 | udelay(20); | |
785 | ||
786 | /* Disable L1-Active */ | |
787 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
788 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
789 | ||
83626404 | 790 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
791 | |
792 | out: | |
793 | return ret; | |
794 | } | |
795 | ||
cc56feb2 EG |
796 | static int iwl_apm_stop_master(struct iwl_trans *trans) |
797 | { | |
798 | int ret = 0; | |
799 | ||
800 | /* stop device's busmaster DMA activity */ | |
801 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
802 | ||
803 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
804 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
805 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
806 | if (ret) |
807 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
808 | ||
809 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
810 | ||
811 | return ret; | |
812 | } | |
813 | ||
814 | static void iwl_apm_stop(struct iwl_trans *trans) | |
815 | { | |
83626404 | 816 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
817 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
818 | ||
83626404 | 819 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
820 | |
821 | /* Stop device's DMA activity */ | |
822 | iwl_apm_stop_master(trans); | |
823 | ||
824 | /* Reset the entire device */ | |
825 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
826 | ||
827 | udelay(10); | |
828 | ||
829 | /* | |
830 | * Clear "initialization complete" bit to move adapter from | |
831 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
832 | */ | |
833 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
834 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
835 | } | |
836 | ||
6d8f6eeb | 837 | static int iwl_nic_init(struct iwl_trans *trans) |
392f8b78 | 838 | { |
7b11488f | 839 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
840 | unsigned long flags; |
841 | ||
842 | /* nic_init */ | |
7b11488f | 843 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
a6c684ee | 844 | iwl_apm_init(trans); |
392f8b78 EG |
845 | |
846 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
20d3b647 | 847 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 848 | |
7b11488f | 849 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 850 | |
3e10caeb | 851 | iwl_set_pwr_vmain(trans); |
392f8b78 | 852 | |
ecdb975c | 853 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
854 | |
855 | /* Allocate the RX queue, or reset if it is already allocated */ | |
6d8f6eeb | 856 | iwl_rx_init(trans); |
392f8b78 EG |
857 | |
858 | /* Allocate or reset and init all Tx and Command queues */ | |
6d8f6eeb | 859 | if (iwl_tx_init(trans)) |
392f8b78 EG |
860 | return -ENOMEM; |
861 | ||
035f7ff2 | 862 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 863 | /* enable shadow regs in HW */ |
20d3b647 | 864 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 865 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
866 | } |
867 | ||
392f8b78 EG |
868 | return 0; |
869 | } | |
870 | ||
871 | #define HW_READY_TIMEOUT (50) | |
872 | ||
873 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
6d8f6eeb | 874 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
875 | { |
876 | int ret; | |
877 | ||
1042db2a | 878 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 879 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
880 | |
881 | /* See if we got it */ | |
1042db2a | 882 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
883 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
884 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
885 | HW_READY_TIMEOUT); | |
392f8b78 | 886 | |
6d8f6eeb | 887 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
888 | return ret; |
889 | } | |
890 | ||
891 | /* Note: returns standard 0/-ERROR code */ | |
ebb7678d | 892 | static int iwl_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
893 | { |
894 | int ret; | |
289e5501 | 895 | int t = 0; |
392f8b78 | 896 | |
6d8f6eeb | 897 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 898 | |
6d8f6eeb | 899 | ret = iwl_set_hw_ready(trans); |
ebb7678d | 900 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
901 | if (ret >= 0) |
902 | return 0; | |
903 | ||
904 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 905 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 906 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 907 | |
289e5501 EG |
908 | do { |
909 | ret = iwl_set_hw_ready(trans); | |
910 | if (ret >= 0) | |
911 | return 0; | |
392f8b78 | 912 | |
289e5501 EG |
913 | usleep_range(200, 1000); |
914 | t += 200; | |
915 | } while (t < 150000); | |
392f8b78 | 916 | |
392f8b78 EG |
917 | return ret; |
918 | } | |
919 | ||
cf614297 EG |
920 | /* |
921 | * ucode | |
922 | */ | |
83f84d7b JB |
923 | static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
924 | dma_addr_t phy_addr, u32 byte_cnt) | |
cf614297 | 925 | { |
13df1aab | 926 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
927 | int ret; |
928 | ||
13df1aab | 929 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
930 | |
931 | iwl_write_direct32(trans, | |
20d3b647 JB |
932 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
933 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
934 | |
935 | iwl_write_direct32(trans, | |
20d3b647 JB |
936 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
937 | dst_addr); | |
cf614297 EG |
938 | |
939 | iwl_write_direct32(trans, | |
83f84d7b JB |
940 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
941 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
942 | |
943 | iwl_write_direct32(trans, | |
20d3b647 JB |
944 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
945 | (iwl_get_dma_hi_addr(phy_addr) | |
946 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
947 | |
948 | iwl_write_direct32(trans, | |
20d3b647 JB |
949 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
950 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
951 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
952 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
953 | |
954 | iwl_write_direct32(trans, | |
20d3b647 JB |
955 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
956 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
957 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
958 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 959 | |
13df1aab JB |
960 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
961 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 962 | if (!ret) { |
83f84d7b | 963 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
964 | return -ETIMEDOUT; |
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
83f84d7b JB |
970 | static int iwl_load_section(struct iwl_trans *trans, u8 section_num, |
971 | const struct fw_desc *section) | |
cf614297 | 972 | { |
83f84d7b JB |
973 | u8 *v_addr; |
974 | dma_addr_t p_addr; | |
975 | u32 offset; | |
cf614297 EG |
976 | int ret = 0; |
977 | ||
83f84d7b JB |
978 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
979 | section_num); | |
980 | ||
981 | v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL); | |
982 | if (!v_addr) | |
983 | return -ENOMEM; | |
984 | ||
985 | for (offset = 0; offset < section->len; offset += PAGE_SIZE) { | |
986 | u32 copy_size; | |
987 | ||
988 | copy_size = min_t(u32, PAGE_SIZE, section->len - offset); | |
cf614297 | 989 | |
83f84d7b JB |
990 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
991 | ret = iwl_load_firmware_chunk(trans, section->offset + offset, | |
992 | p_addr, copy_size); | |
993 | if (ret) { | |
994 | IWL_ERR(trans, | |
995 | "Could not load the [%d] uCode section\n", | |
996 | section_num); | |
997 | break; | |
6dfa8d01 | 998 | } |
83f84d7b JB |
999 | } |
1000 | ||
1001 | dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr); | |
1002 | return ret; | |
1003 | } | |
1004 | ||
0692fe41 JB |
1005 | static int iwl_load_given_ucode(struct iwl_trans *trans, |
1006 | const struct fw_img *image) | |
cf614297 | 1007 | { |
2d1c0044 | 1008 | int i, ret = 0; |
cf614297 | 1009 | |
2d1c0044 | 1010 | for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) { |
83f84d7b | 1011 | if (!image->sec[i].data) |
2d1c0044 | 1012 | break; |
cf614297 | 1013 | |
2d1c0044 JB |
1014 | ret = iwl_load_section(trans, i, &image->sec[i]); |
1015 | if (ret) | |
1016 | return ret; | |
1017 | } | |
cf614297 EG |
1018 | |
1019 | /* Remove all resets to allow NIC to operate */ | |
1020 | iwl_write32(trans, CSR_RESET, 0); | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
0692fe41 JB |
1025 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
1026 | const struct fw_img *fw) | |
392f8b78 EG |
1027 | { |
1028 | int ret; | |
c9eec95c | 1029 | bool hw_rfkill; |
392f8b78 | 1030 | |
496bab39 JB |
1031 | /* This may fail if AMT took ownership of the device */ |
1032 | if (iwl_prepare_card_hw(trans)) { | |
6d8f6eeb | 1033 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
1034 | return -EIO; |
1035 | } | |
1036 | ||
8c46bb70 EG |
1037 | iwl_enable_rfkill_int(trans); |
1038 | ||
392f8b78 | 1039 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 1040 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 1041 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8c46bb70 | 1042 | if (hw_rfkill) |
392f8b78 | 1043 | return -ERFKILL; |
392f8b78 | 1044 | |
1042db2a | 1045 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 1046 | |
6d8f6eeb | 1047 | ret = iwl_nic_init(trans); |
392f8b78 | 1048 | if (ret) { |
6d8f6eeb | 1049 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
1050 | return ret; |
1051 | } | |
1052 | ||
1053 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1054 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1055 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
1056 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1057 | ||
1058 | /* clear (again), then enable host interrupts */ | |
1042db2a | 1059 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 1060 | iwl_enable_interrupts(trans); |
392f8b78 EG |
1061 | |
1062 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1063 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1064 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 1065 | |
cf614297 | 1066 | /* Load the given image to the HW */ |
9441b85d | 1067 | return iwl_load_given_ucode(trans, fw); |
392f8b78 EG |
1068 | } |
1069 | ||
b3c2ce13 EG |
1070 | /* |
1071 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
b3c2ce13 | 1072 | */ |
6d8f6eeb | 1073 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
b3c2ce13 | 1074 | { |
7b11488f JB |
1075 | struct iwl_trans_pcie __maybe_unused *trans_pcie = |
1076 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1077 | ||
1042db2a | 1078 | iwl_write_prph(trans, SCD_TXFACT, mask); |
b3c2ce13 EG |
1079 | } |
1080 | ||
ed6a3803 | 1081 | static void iwl_tx_start(struct iwl_trans *trans) |
b3c2ce13 | 1082 | { |
9eae88fa | 1083 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
b3c2ce13 | 1084 | u32 a; |
b04db9ac | 1085 | int chan; |
b3c2ce13 EG |
1086 | u32 reg_val; |
1087 | ||
fc248615 EG |
1088 | /* make sure all queue are not stopped/used */ |
1089 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
1090 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
1091 | ||
83ed9015 | 1092 | trans_pcie->scd_base_addr = |
1042db2a | 1093 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); |
105183b1 | 1094 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
b3c2ce13 | 1095 | /* reset conext data memory */ |
105183b1 | 1096 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 | 1097 | a += 4) |
1042db2a | 1098 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1099 | /* reset tx status memory */ |
105183b1 | 1100 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 | 1101 | a += 4) |
1042db2a | 1102 | iwl_write_targ_mem(trans, a, 0); |
105183b1 | 1103 | for (; a < trans_pcie->scd_base_addr + |
1745e440 | 1104 | SCD_TRANS_TBL_OFFSET_QUEUE( |
035f7ff2 | 1105 | trans->cfg->base_params->num_of_queues); |
d6189124 | 1106 | a += 4) |
1042db2a | 1107 | iwl_write_targ_mem(trans, a, 0); |
b3c2ce13 | 1108 | |
1042db2a | 1109 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, |
105183b1 | 1110 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 | 1111 | |
d012d04e EG |
1112 | /* The chain extension of the SCD doesn't work well. This feature is |
1113 | * enabled by default by the HW, so we need to disable it manually. | |
1114 | */ | |
1115 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
1116 | ||
b04db9ac EG |
1117 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, |
1118 | trans_pcie->cmd_fifo); | |
b3c2ce13 | 1119 | |
fc248615 EG |
1120 | /* Activate all Tx DMA/FIFO channels */ |
1121 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); | |
1122 | ||
b3c2ce13 EG |
1123 | /* Enable DMA channel */ |
1124 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
1042db2a | 1125 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
fc248615 EG |
1126 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
1127 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
b3c2ce13 EG |
1128 | |
1129 | /* Update FH chicken bits */ | |
1042db2a EG |
1130 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); |
1131 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
b3c2ce13 EG |
1132 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
1133 | ||
b3c2ce13 | 1134 | /* Enable L1-Active */ |
1042db2a | 1135 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, |
20d3b647 | 1136 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
b3c2ce13 EG |
1137 | } |
1138 | ||
ed6a3803 EG |
1139 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) |
1140 | { | |
1141 | iwl_reset_ict(trans); | |
1142 | iwl_tx_start(trans); | |
1143 | } | |
1144 | ||
c170b867 EG |
1145 | /** |
1146 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
1147 | */ | |
6d8f6eeb | 1148 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
c170b867 | 1149 | { |
20d3b647 | 1150 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c2945f39 | 1151 | int ch, txq_id, ret; |
c170b867 EG |
1152 | unsigned long flags; |
1153 | ||
1154 | /* Turn off all Tx DMA fifos */ | |
7b11488f | 1155 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
c170b867 | 1156 | |
6d8f6eeb | 1157 | iwl_trans_txq_set_sched(trans, 0); |
c170b867 EG |
1158 | |
1159 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 1160 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
1042db2a | 1161 | iwl_write_direct32(trans, |
6d8f6eeb | 1162 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
c2945f39 | 1163 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, |
20d3b647 | 1164 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); |
c2945f39 | 1165 | if (ret < 0) |
20d3b647 | 1166 | IWL_ERR(trans, |
d6f1c316 | 1167 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", |
20d3b647 JB |
1168 | ch, |
1169 | iwl_read_direct32(trans, | |
1170 | FH_TSSR_TX_STATUS_REG)); | |
c170b867 | 1171 | } |
7b11488f | 1172 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
c170b867 | 1173 | |
8ad71bef | 1174 | if (!trans_pcie->txq) { |
d6f1c316 JB |
1175 | IWL_WARN(trans, |
1176 | "Stopping tx queues that aren't allocated...\n"); | |
c170b867 EG |
1177 | return 0; |
1178 | } | |
1179 | ||
1180 | /* Unmap DMA from host system and free skb's */ | |
035f7ff2 | 1181 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; |
1745e440 | 1182 | txq_id++) |
6d8f6eeb | 1183 | iwl_tx_queue_unmap(trans, txq_id); |
c170b867 EG |
1184 | |
1185 | return 0; | |
1186 | } | |
1187 | ||
43e58856 | 1188 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 1189 | { |
43e58856 | 1190 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 1191 | unsigned long flags; |
ae2c30bf | 1192 | |
43e58856 | 1193 | /* tell the device to stop sending interrupts */ |
7b11488f | 1194 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1195 | iwl_disable_interrupts(trans); |
7b11488f | 1196 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 1197 | |
ab6cf8e8 | 1198 | /* device going down, Stop using ICT table */ |
6d8f6eeb | 1199 | iwl_disable_ict(trans); |
ab6cf8e8 EG |
1200 | |
1201 | /* | |
1202 | * If a HW restart happens during firmware loading, | |
1203 | * then the firmware loading might call this function | |
1204 | * and later it might be called again due to the | |
1205 | * restart. So don't process again if the device is | |
1206 | * already dead. | |
1207 | */ | |
83626404 | 1208 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
6d8f6eeb EG |
1209 | iwl_trans_tx_stop(trans); |
1210 | iwl_trans_rx_stop(trans); | |
6379103e | 1211 | |
ab6cf8e8 | 1212 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 1213 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1214 | APMG_CLK_VAL_DMA_CLK_RQT); |
1215 | udelay(5); | |
1216 | } | |
1217 | ||
1218 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1219 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 1220 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1221 | |
1222 | /* Stop the device, and put it in low power state */ | |
cc56feb2 | 1223 | iwl_apm_stop(trans); |
43e58856 EG |
1224 | |
1225 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1226 | * Clean again the interrupt here | |
1227 | */ | |
7b11488f | 1228 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 1229 | iwl_disable_interrupts(trans); |
7b11488f | 1230 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 1231 | |
218733cf EG |
1232 | iwl_enable_rfkill_int(trans); |
1233 | ||
43e58856 | 1234 | /* wait to make sure we flush pending tasklet*/ |
75595536 | 1235 | synchronize_irq(trans_pcie->irq); |
43e58856 EG |
1236 | tasklet_kill(&trans_pcie->irq_tasklet); |
1237 | ||
1ee158d8 JB |
1238 | cancel_work_sync(&trans_pcie->rx_replenish); |
1239 | ||
43e58856 | 1240 | /* stop and reset the on-board processor */ |
1042db2a | 1241 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
1242 | |
1243 | /* clear all status bits */ | |
1244 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); | |
1245 | clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); | |
1246 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); | |
01d651d4 | 1247 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
ab6cf8e8 EG |
1248 | } |
1249 | ||
2dd4f9f7 JB |
1250 | static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans) |
1251 | { | |
1252 | /* let the ucode operate on its own */ | |
1253 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
1254 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
1255 | ||
1256 | iwl_disable_interrupts(trans); | |
1257 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
1258 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1259 | } | |
1260 | ||
e13c0c59 | 1261 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
9eae88fa | 1262 | struct iwl_device_cmd *dev_cmd, int txq_id) |
47c1b496 | 1263 | { |
e13c0c59 EG |
1264 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1265 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
132f98c2 | 1266 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
47c1b496 | 1267 | struct iwl_cmd_meta *out_meta; |
e13c0c59 EG |
1268 | struct iwl_tx_queue *txq; |
1269 | struct iwl_queue *q; | |
47c1b496 EG |
1270 | dma_addr_t phys_addr = 0; |
1271 | dma_addr_t txcmd_phys; | |
1272 | dma_addr_t scratch_phys; | |
1273 | u16 len, firstlen, secondlen; | |
1274 | u8 wait_write_ptr = 0; | |
e13c0c59 | 1275 | __le16 fc = hdr->frame_control; |
47c1b496 | 1276 | u8 hdr_len = ieee80211_hdrlen(fc); |
631b84c5 | 1277 | u16 __maybe_unused wifi_seq; |
47c1b496 | 1278 | |
8ad71bef | 1279 | txq = &trans_pcie->txq[txq_id]; |
e13c0c59 EG |
1280 | q = &txq->q; |
1281 | ||
9eae88fa JB |
1282 | if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) { |
1283 | WARN_ON_ONCE(1); | |
1284 | return -EINVAL; | |
1285 | } | |
015c15e1 | 1286 | |
9eae88fa | 1287 | spin_lock(&txq->lock); |
631b84c5 | 1288 | |
7bc057ff EG |
1289 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1290 | * sequence number. This is a HW requirements to help the SCD to parse | |
1291 | * the BA. | |
1292 | * Check here that the packets are in the right place on the ring. | |
1293 | */ | |
1294 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1295 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1296 | WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) && | |
1297 | ((wifi_seq & 0xff) != q->write_ptr), | |
1298 | "Q: %d WiFi Seq %d tfdNum %d", | |
1299 | txq_id, wifi_seq, q->write_ptr); | |
1300 | #endif | |
1301 | ||
47c1b496 | 1302 | /* Set up driver data for this TFD */ |
bf8440e6 JB |
1303 | txq->entries[q->write_ptr].skb = skb; |
1304 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
dfa2bdba EG |
1305 | |
1306 | dev_cmd->hdr.cmd = REPLY_TX; | |
20d3b647 JB |
1307 | dev_cmd->hdr.sequence = |
1308 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1309 | INDEX_TO_SEQ(q->write_ptr))); | |
47c1b496 EG |
1310 | |
1311 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
bf8440e6 | 1312 | out_meta = &txq->entries[q->write_ptr].meta; |
47c1b496 EG |
1313 | |
1314 | /* | |
1315 | * Use the first empty entry in this queue's command buffer array | |
1316 | * to contain the Tx command and MAC header concatenated together | |
1317 | * (payload data will be in another buffer). | |
1318 | * Size of this varies, due to varying MAC header length. | |
1319 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1320 | * of the MAC header (device reads on dword boundaries). | |
1321 | * We'll tell device about this padding later. | |
1322 | */ | |
1323 | len = sizeof(struct iwl_tx_cmd) + | |
1324 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1325 | firstlen = (len + 3) & ~3; | |
1326 | ||
1327 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1328 | if (firstlen != len) | |
1329 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1330 | ||
1331 | /* Physical address of this Tx command's header (not MAC header!), | |
1332 | * within command buffer array. */ | |
1042db2a | 1333 | txcmd_phys = dma_map_single(trans->dev, |
47c1b496 EG |
1334 | &dev_cmd->hdr, firstlen, |
1335 | DMA_BIDIRECTIONAL); | |
1042db2a | 1336 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) |
015c15e1 | 1337 | goto out_err; |
47c1b496 EG |
1338 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
1339 | dma_unmap_len_set(out_meta, len, firstlen); | |
1340 | ||
1341 | if (!ieee80211_has_morefrags(fc)) { | |
1342 | txq->need_update = 1; | |
1343 | } else { | |
1344 | wait_write_ptr = 1; | |
1345 | txq->need_update = 0; | |
1346 | } | |
1347 | ||
1348 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1349 | * if any (802.11 null frames have no payload). */ | |
1350 | secondlen = skb->len - hdr_len; | |
1351 | if (secondlen > 0) { | |
1042db2a | 1352 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, |
47c1b496 | 1353 | secondlen, DMA_TO_DEVICE); |
1042db2a EG |
1354 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
1355 | dma_unmap_single(trans->dev, | |
47c1b496 EG |
1356 | dma_unmap_addr(out_meta, mapping), |
1357 | dma_unmap_len(out_meta, len), | |
1358 | DMA_BIDIRECTIONAL); | |
015c15e1 | 1359 | goto out_err; |
47c1b496 EG |
1360 | } |
1361 | } | |
1362 | ||
1363 | /* Attach buffers to TFD */ | |
e13c0c59 | 1364 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
47c1b496 | 1365 | if (secondlen > 0) |
e13c0c59 | 1366 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
47c1b496 EG |
1367 | secondlen, 0); |
1368 | ||
1369 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1370 | offsetof(struct iwl_tx_cmd, scratch); | |
1371 | ||
1372 | /* take back ownership of DMA buffer to enable update */ | |
1042db2a | 1373 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, |
20d3b647 | 1374 | DMA_BIDIRECTIONAL); |
47c1b496 EG |
1375 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
1376 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1377 | ||
e13c0c59 | 1378 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
47c1b496 | 1379 | le16_to_cpu(dev_cmd->hdr.sequence)); |
e13c0c59 | 1380 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
47c1b496 EG |
1381 | |
1382 | /* Set up entry for this TFD in Tx byte-count array */ | |
96f1f05a | 1383 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); |
47c1b496 | 1384 | |
1042db2a | 1385 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
20d3b647 | 1386 | DMA_BIDIRECTIONAL); |
47c1b496 | 1387 | |
f042c2eb | 1388 | trace_iwlwifi_dev_tx(trans->dev, skb, |
2c208890 | 1389 | &txq->tfds[txq->q.write_ptr], |
47c1b496 EG |
1390 | sizeof(struct iwl_tfd), |
1391 | &dev_cmd->hdr, firstlen, | |
1392 | skb->data + hdr_len, secondlen); | |
f042c2eb JB |
1393 | trace_iwlwifi_dev_tx_data(trans->dev, skb, |
1394 | skb->data + hdr_len, secondlen); | |
47c1b496 | 1395 | |
7c5ba4a8 | 1396 | /* start timer if queue currently empty */ |
49a4fc20 EG |
1397 | if (txq->need_update && q->read_ptr == q->write_ptr && |
1398 | trans_pcie->wd_timeout) | |
7c5ba4a8 JB |
1399 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); |
1400 | ||
47c1b496 EG |
1401 | /* Tell device the write index *just past* this latest filled TFD */ |
1402 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
e13c0c59 EG |
1403 | iwl_txq_update_write_ptr(trans, txq); |
1404 | ||
47c1b496 EG |
1405 | /* |
1406 | * At this point the frame is "transmitted" successfully | |
1407 | * and we will get a TX status notification eventually, | |
1408 | * regardless of the value of ret. "ret" only indicates | |
1409 | * whether or not we should update the write pointer. | |
1410 | */ | |
a0eaad71 | 1411 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1412 | if (wait_write_ptr) { |
1413 | txq->need_update = 1; | |
e13c0c59 | 1414 | iwl_txq_update_write_ptr(trans, txq); |
47c1b496 | 1415 | } else { |
bada991b | 1416 | iwl_stop_queue(trans, txq); |
47c1b496 EG |
1417 | } |
1418 | } | |
015c15e1 | 1419 | spin_unlock(&txq->lock); |
47c1b496 | 1420 | return 0; |
015c15e1 JB |
1421 | out_err: |
1422 | spin_unlock(&txq->lock); | |
1423 | return -1; | |
47c1b496 EG |
1424 | } |
1425 | ||
57a1dc89 | 1426 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 1427 | { |
20d3b647 | 1428 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e6bb4c9c | 1429 | int err; |
c9eec95c | 1430 | bool hw_rfkill; |
e6bb4c9c | 1431 | |
0c325769 EG |
1432 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1433 | ||
57a1dc89 EG |
1434 | if (!trans_pcie->irq_requested) { |
1435 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1436 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1437 | |
57a1dc89 | 1438 | iwl_alloc_isr_ict(trans); |
e6bb4c9c | 1439 | |
75595536 | 1440 | err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED, |
20d3b647 | 1441 | DRV_NAME, trans); |
57a1dc89 EG |
1442 | if (err) { |
1443 | IWL_ERR(trans, "Error allocating IRQ %d\n", | |
75595536 | 1444 | trans_pcie->irq); |
ebb7678d | 1445 | goto error; |
57a1dc89 EG |
1446 | } |
1447 | ||
1448 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); | |
1449 | trans_pcie->irq_requested = true; | |
e6bb4c9c EG |
1450 | } |
1451 | ||
ebb7678d EG |
1452 | err = iwl_prepare_card_hw(trans); |
1453 | if (err) { | |
d6f1c316 | 1454 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
f057ac4e | 1455 | goto err_free_irq; |
ebb7678d | 1456 | } |
a6c684ee EG |
1457 | |
1458 | iwl_apm_init(trans); | |
1459 | ||
226c02ca EG |
1460 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1461 | iwl_enable_rfkill_int(trans); | |
1462 | ||
8d425517 | 1463 | hw_rfkill = iwl_is_rfkill_set(trans); |
c9eec95c | 1464 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 1465 | |
ebb7678d EG |
1466 | return err; |
1467 | ||
f057ac4e | 1468 | err_free_irq: |
a7be50b7 | 1469 | trans_pcie->irq_requested = false; |
75595536 | 1470 | free_irq(trans_pcie->irq, trans); |
ebb7678d EG |
1471 | error: |
1472 | iwl_free_isr_ict(trans); | |
1473 | tasklet_kill(&trans_pcie->irq_tasklet); | |
1474 | return err; | |
e6bb4c9c EG |
1475 | } |
1476 | ||
218733cf EG |
1477 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, |
1478 | bool op_mode_leaving) | |
cc56feb2 | 1479 | { |
20d3b647 | 1480 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1481 | bool hw_rfkill; |
218733cf | 1482 | unsigned long flags; |
d23f78e6 | 1483 | |
ee7d737c DS |
1484 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1485 | iwl_disable_interrupts(trans); | |
1486 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1487 | ||
cc56feb2 EG |
1488 | iwl_apm_stop(trans); |
1489 | ||
218733cf EG |
1490 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1491 | iwl_disable_interrupts(trans); | |
1492 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 1493 | |
218733cf EG |
1494 | if (!op_mode_leaving) { |
1495 | /* | |
1496 | * Even if we stop the HW, we still want the RF kill | |
1497 | * interrupt | |
1498 | */ | |
1499 | iwl_enable_rfkill_int(trans); | |
1500 | ||
1501 | /* | |
1502 | * Check again since the RF kill state may have changed while | |
1503 | * all the interrupts were disabled, in this case we couldn't | |
1504 | * receive the RF kill interrupt and update the state in the | |
1505 | * op_mode. | |
1506 | */ | |
1507 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1508 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
1509 | } | |
cc56feb2 EG |
1510 | } |
1511 | ||
9eae88fa JB |
1512 | static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
1513 | struct sk_buff_head *skbs) | |
464021ff | 1514 | { |
8ad71bef EG |
1515 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1516 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 EG |
1517 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
1518 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
a0eaad71 | 1519 | |
015c15e1 JB |
1520 | spin_lock(&txq->lock); |
1521 | ||
a0eaad71 | 1522 | if (txq->q.read_ptr != tfd_num) { |
9eae88fa JB |
1523 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", |
1524 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
26c7af7c | 1525 | iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
e755f882 | 1526 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
bada991b | 1527 | iwl_wake_queue(trans, txq); |
a0eaad71 | 1528 | } |
015c15e1 JB |
1529 | |
1530 | spin_unlock(&txq->lock); | |
a0eaad71 EG |
1531 | } |
1532 | ||
03905495 EG |
1533 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1534 | { | |
05f5b97e | 1535 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1536 | } |
1537 | ||
1538 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1539 | { | |
05f5b97e | 1540 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1541 | } |
1542 | ||
1543 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1544 | { | |
05f5b97e | 1545 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1546 | } |
1547 | ||
c6f600fc | 1548 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1549 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1550 | { |
1551 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1552 | ||
1553 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 1554 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
1555 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1556 | trans_pcie->n_no_reclaim_cmds = 0; | |
1557 | else | |
1558 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1559 | if (trans_pcie->n_no_reclaim_cmds) | |
1560 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1561 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 1562 | |
b2cf410c JB |
1563 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
1564 | if (trans_pcie->rx_buf_size_8k) | |
1565 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
1566 | else | |
1567 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
1568 | |
1569 | trans_pcie->wd_timeout = | |
1570 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
1571 | |
1572 | trans_pcie->command_names = trans_cfg->command_names; | |
c6f600fc MV |
1573 | } |
1574 | ||
d1ff5253 | 1575 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1576 | { |
20d3b647 | 1577 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 1578 | |
ae2c30bf EG |
1579 | iwl_trans_pcie_tx_free(trans); |
1580 | iwl_trans_pcie_rx_free(trans); | |
6379103e | 1581 | |
57a1dc89 | 1582 | if (trans_pcie->irq_requested == true) { |
75595536 | 1583 | free_irq(trans_pcie->irq, trans); |
57a1dc89 EG |
1584 | iwl_free_isr_ict(trans); |
1585 | } | |
a42a1844 EG |
1586 | |
1587 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 1588 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
1589 | pci_release_regions(trans_pcie->pci_dev); |
1590 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 1591 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 1592 | |
6d8f6eeb | 1593 | kfree(trans); |
34c1b7ba EG |
1594 | } |
1595 | ||
47107e84 DF |
1596 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1597 | { | |
1598 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1599 | ||
1600 | if (state) | |
01d651d4 | 1601 | set_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 | 1602 | else |
01d651d4 | 1603 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 DF |
1604 | } |
1605 | ||
c01a4047 | 1606 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1607 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
1608 | { | |
57210f7c EG |
1609 | return 0; |
1610 | } | |
1611 | ||
1612 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1613 | { | |
c9eec95c | 1614 | bool hw_rfkill; |
57210f7c | 1615 | |
8c46bb70 EG |
1616 | iwl_enable_rfkill_int(trans); |
1617 | ||
8d425517 | 1618 | hw_rfkill = iwl_is_rfkill_set(trans); |
8c46bb70 | 1619 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8722c899 | 1620 | |
8c46bb70 | 1621 | if (!hw_rfkill) |
8722c899 SG |
1622 | iwl_enable_interrupts(trans); |
1623 | ||
57210f7c EG |
1624 | return 0; |
1625 | } | |
c01a4047 | 1626 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 1627 | |
5f178cd2 EG |
1628 | #define IWL_FLUSH_WAIT_MS 2000 |
1629 | ||
1630 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) | |
1631 | { | |
8ad71bef | 1632 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5f178cd2 EG |
1633 | struct iwl_tx_queue *txq; |
1634 | struct iwl_queue *q; | |
1635 | int cnt; | |
1636 | unsigned long now = jiffies; | |
1637 | int ret = 0; | |
1638 | ||
1639 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1640 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 1641 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1642 | continue; |
8ad71bef | 1643 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1644 | q = &txq->q; |
1645 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1646 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1647 | msleep(1); | |
1648 | ||
1649 | if (q->read_ptr != q->write_ptr) { | |
1650 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
1651 | ret = -ETIMEDOUT; | |
1652 | break; | |
1653 | } | |
1654 | } | |
1655 | return ret; | |
1656 | } | |
1657 | ||
ff620849 EG |
1658 | static const char *get_fh_string(int cmd) |
1659 | { | |
d9fb6465 | 1660 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1661 | switch (cmd) { |
1662 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1663 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1664 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1665 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1666 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1667 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1668 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1669 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1670 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1671 | default: | |
1672 | return "UNKNOWN"; | |
1673 | } | |
d9fb6465 | 1674 | #undef IWL_CMD |
ff620849 EG |
1675 | } |
1676 | ||
94543a8d | 1677 | int iwl_dump_fh(struct iwl_trans *trans, char **buf) |
ff620849 EG |
1678 | { |
1679 | int i; | |
ff620849 EG |
1680 | static const u32 fh_tbl[] = { |
1681 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1682 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1683 | FH_RSCSR_CHNL0_WPTR, | |
1684 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1685 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1686 | FH_MEM_RSSR_RX_STATUS_REG, | |
1687 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1688 | FH_TSSR_TX_STATUS_REG, | |
1689 | FH_TSSR_TX_ERROR_REG | |
1690 | }; | |
94543a8d JB |
1691 | |
1692 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
1693 | if (buf) { | |
1694 | int pos = 0; | |
1695 | size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1696 | ||
ff620849 EG |
1697 | *buf = kmalloc(bufsz, GFP_KERNEL); |
1698 | if (!*buf) | |
1699 | return -ENOMEM; | |
94543a8d | 1700 | |
ff620849 EG |
1701 | pos += scnprintf(*buf + pos, bufsz - pos, |
1702 | "FH register values:\n"); | |
94543a8d JB |
1703 | |
1704 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) | |
ff620849 EG |
1705 | pos += scnprintf(*buf + pos, bufsz - pos, |
1706 | " %34s: 0X%08x\n", | |
1707 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1708 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 1709 | |
ff620849 EG |
1710 | return pos; |
1711 | } | |
1712 | #endif | |
94543a8d | 1713 | |
ff620849 | 1714 | IWL_ERR(trans, "FH register values:\n"); |
94543a8d | 1715 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) |
ff620849 EG |
1716 | IWL_ERR(trans, " %34s: 0X%08x\n", |
1717 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1718 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 1719 | |
ff620849 EG |
1720 | return 0; |
1721 | } | |
1722 | ||
1723 | static const char *get_csr_string(int cmd) | |
1724 | { | |
d9fb6465 | 1725 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1726 | switch (cmd) { |
1727 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1728 | IWL_CMD(CSR_INT_COALESCING); | |
1729 | IWL_CMD(CSR_INT); | |
1730 | IWL_CMD(CSR_INT_MASK); | |
1731 | IWL_CMD(CSR_FH_INT_STATUS); | |
1732 | IWL_CMD(CSR_GPIO_IN); | |
1733 | IWL_CMD(CSR_RESET); | |
1734 | IWL_CMD(CSR_GP_CNTRL); | |
1735 | IWL_CMD(CSR_HW_REV); | |
1736 | IWL_CMD(CSR_EEPROM_REG); | |
1737 | IWL_CMD(CSR_EEPROM_GP); | |
1738 | IWL_CMD(CSR_OTP_GP_REG); | |
1739 | IWL_CMD(CSR_GIO_REG); | |
1740 | IWL_CMD(CSR_GP_UCODE_REG); | |
1741 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1742 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1743 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1744 | IWL_CMD(CSR_LED_REG); | |
1745 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1746 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1747 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1748 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1749 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1750 | default: | |
1751 | return "UNKNOWN"; | |
1752 | } | |
d9fb6465 | 1753 | #undef IWL_CMD |
ff620849 EG |
1754 | } |
1755 | ||
1756 | void iwl_dump_csr(struct iwl_trans *trans) | |
1757 | { | |
1758 | int i; | |
1759 | static const u32 csr_tbl[] = { | |
1760 | CSR_HW_IF_CONFIG_REG, | |
1761 | CSR_INT_COALESCING, | |
1762 | CSR_INT, | |
1763 | CSR_INT_MASK, | |
1764 | CSR_FH_INT_STATUS, | |
1765 | CSR_GPIO_IN, | |
1766 | CSR_RESET, | |
1767 | CSR_GP_CNTRL, | |
1768 | CSR_HW_REV, | |
1769 | CSR_EEPROM_REG, | |
1770 | CSR_EEPROM_GP, | |
1771 | CSR_OTP_GP_REG, | |
1772 | CSR_GIO_REG, | |
1773 | CSR_GP_UCODE_REG, | |
1774 | CSR_GP_DRIVER_REG, | |
1775 | CSR_UCODE_DRV_GP1, | |
1776 | CSR_UCODE_DRV_GP2, | |
1777 | CSR_LED_REG, | |
1778 | CSR_DRAM_INT_TBL_REG, | |
1779 | CSR_GIO_CHICKEN_BITS, | |
1780 | CSR_ANA_PLL_CFG, | |
1781 | CSR_HW_REV_WA_REG, | |
1782 | CSR_DBG_HPET_MEM_REG | |
1783 | }; | |
1784 | IWL_ERR(trans, "CSR values:\n"); | |
1785 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1786 | "CSR_INT_PERIODIC_REG)\n"); | |
1787 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1788 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1789 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1790 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1791 | } |
1792 | } | |
1793 | ||
87e5666c EG |
1794 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1795 | /* create and remove of files */ | |
1796 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1797 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1798 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1799 | goto err; \ |
87e5666c EG |
1800 | } while (0) |
1801 | ||
1802 | /* file operation */ | |
1803 | #define DEBUGFS_READ_FUNC(name) \ | |
1804 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1805 | char __user *user_buf, \ | |
1806 | size_t count, loff_t *ppos); | |
1807 | ||
1808 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1809 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1810 | const char __user *user_buf, \ | |
1811 | size_t count, loff_t *ppos); | |
1812 | ||
1813 | ||
87e5666c EG |
1814 | #define DEBUGFS_READ_FILE_OPS(name) \ |
1815 | DEBUGFS_READ_FUNC(name); \ | |
1816 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1817 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1818 | .open = simple_open, \ |
87e5666c EG |
1819 | .llseek = generic_file_llseek, \ |
1820 | }; | |
1821 | ||
16db88ba EG |
1822 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1823 | DEBUGFS_WRITE_FUNC(name); \ | |
1824 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1825 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1826 | .open = simple_open, \ |
16db88ba EG |
1827 | .llseek = generic_file_llseek, \ |
1828 | }; | |
1829 | ||
87e5666c EG |
1830 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1831 | DEBUGFS_READ_FUNC(name); \ | |
1832 | DEBUGFS_WRITE_FUNC(name); \ | |
1833 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1834 | .write = iwl_dbgfs_##name##_write, \ | |
1835 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1836 | .open = simple_open, \ |
87e5666c EG |
1837 | .llseek = generic_file_llseek, \ |
1838 | }; | |
1839 | ||
87e5666c | 1840 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1841 | char __user *user_buf, |
1842 | size_t count, loff_t *ppos) | |
8ad71bef | 1843 | { |
5a878bf6 | 1844 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1845 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
87e5666c EG |
1846 | struct iwl_tx_queue *txq; |
1847 | struct iwl_queue *q; | |
1848 | char *buf; | |
1849 | int pos = 0; | |
1850 | int cnt; | |
1851 | int ret; | |
1745e440 WYG |
1852 | size_t bufsz; |
1853 | ||
035f7ff2 | 1854 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1855 | |
f9e75447 | 1856 | if (!trans_pcie->txq) |
87e5666c | 1857 | return -EAGAIN; |
f9e75447 | 1858 | |
87e5666c EG |
1859 | buf = kzalloc(bufsz, GFP_KERNEL); |
1860 | if (!buf) | |
1861 | return -ENOMEM; | |
1862 | ||
035f7ff2 | 1863 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1864 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1865 | q = &txq->q; |
1866 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1867 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1868 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1869 | !!test_bit(cnt, trans_pcie->queue_used), |
1870 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1871 | } |
1872 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1873 | kfree(buf); | |
1874 | return ret; | |
1875 | } | |
1876 | ||
1877 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1878 | char __user *user_buf, |
1879 | size_t count, loff_t *ppos) | |
1880 | { | |
5a878bf6 | 1881 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1882 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 1883 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
87e5666c EG |
1884 | char buf[256]; |
1885 | int pos = 0; | |
1886 | const size_t bufsz = sizeof(buf); | |
1887 | ||
1888 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1889 | rxq->read); | |
1890 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1891 | rxq->write); | |
1892 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1893 | rxq->free_count); | |
1894 | if (rxq->rb_stts) { | |
1895 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1896 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1897 | } else { | |
1898 | pos += scnprintf(buf + pos, bufsz - pos, | |
1899 | "closed_rb_num: Not Allocated\n"); | |
1900 | } | |
1901 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1902 | } | |
1903 | ||
1f7b6172 EG |
1904 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1905 | char __user *user_buf, | |
20d3b647 JB |
1906 | size_t count, loff_t *ppos) |
1907 | { | |
1f7b6172 | 1908 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1909 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1910 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1911 | ||
1912 | int pos = 0; | |
1913 | char *buf; | |
1914 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1915 | ssize_t ret; | |
1916 | ||
1917 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1918 | if (!buf) |
1f7b6172 | 1919 | return -ENOMEM; |
1f7b6172 EG |
1920 | |
1921 | pos += scnprintf(buf + pos, bufsz - pos, | |
1922 | "Interrupt Statistics Report:\n"); | |
1923 | ||
1924 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1925 | isr_stats->hw); | |
1926 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1927 | isr_stats->sw); | |
1928 | if (isr_stats->sw || isr_stats->hw) { | |
1929 | pos += scnprintf(buf + pos, bufsz - pos, | |
1930 | "\tLast Restarting Code: 0x%X\n", | |
1931 | isr_stats->err_code); | |
1932 | } | |
1933 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1934 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1935 | isr_stats->sch); | |
1936 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1937 | isr_stats->alive); | |
1938 | #endif | |
1939 | pos += scnprintf(buf + pos, bufsz - pos, | |
1940 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1941 | ||
1942 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1943 | isr_stats->ctkill); | |
1944 | ||
1945 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1946 | isr_stats->wakeup); | |
1947 | ||
1948 | pos += scnprintf(buf + pos, bufsz - pos, | |
1949 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1950 | ||
1951 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1952 | isr_stats->tx); | |
1953 | ||
1954 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1955 | isr_stats->unhandled); | |
1956 | ||
1957 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1958 | kfree(buf); | |
1959 | return ret; | |
1960 | } | |
1961 | ||
1962 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1963 | const char __user *user_buf, | |
1964 | size_t count, loff_t *ppos) | |
1965 | { | |
1966 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1967 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1968 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1969 | ||
1970 | char buf[8]; | |
1971 | int buf_size; | |
1972 | u32 reset_flag; | |
1973 | ||
1974 | memset(buf, 0, sizeof(buf)); | |
1975 | buf_size = min(count, sizeof(buf) - 1); | |
1976 | if (copy_from_user(buf, user_buf, buf_size)) | |
1977 | return -EFAULT; | |
1978 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1979 | return -EFAULT; | |
1980 | if (reset_flag == 0) | |
1981 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1982 | ||
1983 | return count; | |
1984 | } | |
1985 | ||
16db88ba | 1986 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1987 | const char __user *user_buf, |
1988 | size_t count, loff_t *ppos) | |
16db88ba EG |
1989 | { |
1990 | struct iwl_trans *trans = file->private_data; | |
1991 | char buf[8]; | |
1992 | int buf_size; | |
1993 | int csr; | |
1994 | ||
1995 | memset(buf, 0, sizeof(buf)); | |
1996 | buf_size = min(count, sizeof(buf) - 1); | |
1997 | if (copy_from_user(buf, user_buf, buf_size)) | |
1998 | return -EFAULT; | |
1999 | if (sscanf(buf, "%d", &csr) != 1) | |
2000 | return -EFAULT; | |
2001 | ||
2002 | iwl_dump_csr(trans); | |
2003 | ||
2004 | return count; | |
2005 | } | |
2006 | ||
16db88ba | 2007 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
2008 | char __user *user_buf, |
2009 | size_t count, loff_t *ppos) | |
16db88ba EG |
2010 | { |
2011 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 2012 | char *buf = NULL; |
16db88ba EG |
2013 | int pos = 0; |
2014 | ssize_t ret = -EFAULT; | |
2015 | ||
94543a8d | 2016 | ret = pos = iwl_dump_fh(trans, &buf); |
16db88ba EG |
2017 | if (buf) { |
2018 | ret = simple_read_from_buffer(user_buf, | |
2019 | count, ppos, buf, pos); | |
2020 | kfree(buf); | |
2021 | } | |
2022 | ||
2023 | return ret; | |
2024 | } | |
2025 | ||
48dffd39 JB |
2026 | static ssize_t iwl_dbgfs_fw_restart_write(struct file *file, |
2027 | const char __user *user_buf, | |
2028 | size_t count, loff_t *ppos) | |
2029 | { | |
2030 | struct iwl_trans *trans = file->private_data; | |
2031 | ||
2032 | if (!trans->op_mode) | |
2033 | return -EAGAIN; | |
2034 | ||
24172f39 | 2035 | local_bh_disable(); |
48dffd39 | 2036 | iwl_op_mode_nic_error(trans->op_mode); |
24172f39 | 2037 | local_bh_enable(); |
48dffd39 JB |
2038 | |
2039 | return count; | |
2040 | } | |
2041 | ||
1f7b6172 | 2042 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 2043 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
2044 | DEBUGFS_READ_FILE_OPS(rx_queue); |
2045 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 2046 | DEBUGFS_WRITE_FILE_OPS(csr); |
48dffd39 | 2047 | DEBUGFS_WRITE_FILE_OPS(fw_restart); |
87e5666c EG |
2048 | |
2049 | /* | |
2050 | * Create the debugfs files and directories | |
2051 | * | |
2052 | */ | |
2053 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 2054 | struct dentry *dir) |
87e5666c | 2055 | { |
87e5666c EG |
2056 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
2057 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 2058 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
2059 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
2060 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
48dffd39 | 2061 | DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR); |
87e5666c | 2062 | return 0; |
9da987ac MV |
2063 | |
2064 | err: | |
2065 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
2066 | return -ENOMEM; | |
87e5666c EG |
2067 | } |
2068 | #else | |
2069 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
2070 | struct dentry *dir) |
2071 | { | |
2072 | return 0; | |
2073 | } | |
87e5666c EG |
2074 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
2075 | ||
d1ff5253 | 2076 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2077 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 2078 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 2079 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2080 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2081 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2082 | |
2dd4f9f7 JB |
2083 | .wowlan_suspend = iwl_trans_pcie_wowlan_suspend, |
2084 | ||
e6bb4c9c | 2085 | .send_cmd = iwl_trans_pcie_send_cmd, |
c85eb619 | 2086 | |
e6bb4c9c | 2087 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2088 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2089 | |
d0624be6 | 2090 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 2091 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 2092 | |
87e5666c | 2093 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 EG |
2094 | |
2095 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, | |
2096 | ||
c01a4047 | 2097 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
2098 | .suspend = iwl_trans_pcie_suspend, |
2099 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 2100 | #endif |
03905495 EG |
2101 | .write8 = iwl_trans_pcie_write8, |
2102 | .write32 = iwl_trans_pcie_write32, | |
2103 | .read32 = iwl_trans_pcie_read32, | |
c6f600fc | 2104 | .configure = iwl_trans_pcie_configure, |
47107e84 | 2105 | .set_pmi = iwl_trans_pcie_set_pmi, |
e6bb4c9c | 2106 | }; |
a42a1844 | 2107 | |
87ce05a2 | 2108 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
2109 | const struct pci_device_id *ent, |
2110 | const struct iwl_cfg *cfg) | |
a42a1844 | 2111 | { |
a42a1844 EG |
2112 | struct iwl_trans_pcie *trans_pcie; |
2113 | struct iwl_trans *trans; | |
2114 | u16 pci_cmd; | |
2115 | int err; | |
2116 | ||
2117 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 2118 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
a42a1844 EG |
2119 | |
2120 | if (WARN_ON(!trans)) | |
2121 | return NULL; | |
2122 | ||
2123 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2124 | ||
2125 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 2126 | trans->cfg = cfg; |
a42a1844 | 2127 | trans_pcie->trans = trans; |
7b11488f | 2128 | spin_lock_init(&trans_pcie->irq_lock); |
13df1aab | 2129 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
2130 | |
2131 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
2132 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
2133 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
20d3b647 | 2134 | PCIE_LINK_STATE_CLKPM); |
a42a1844 EG |
2135 | |
2136 | if (pci_enable_device(pdev)) { | |
2137 | err = -ENODEV; | |
2138 | goto out_no_pci; | |
2139 | } | |
2140 | ||
2141 | pci_set_master(pdev); | |
2142 | ||
2143 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2144 | if (!err) | |
2145 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2146 | if (err) { | |
2147 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2148 | if (!err) | |
2149 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 2150 | DMA_BIT_MASK(32)); |
a42a1844 EG |
2151 | /* both attempts failed: */ |
2152 | if (err) { | |
2153 | dev_printk(KERN_ERR, &pdev->dev, | |
2154 | "No suitable DMA available.\n"); | |
2155 | goto out_pci_disable_device; | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | err = pci_request_regions(pdev, DRV_NAME); | |
2160 | if (err) { | |
d6f1c316 JB |
2161 | dev_printk(KERN_ERR, &pdev->dev, |
2162 | "pci_request_regions failed\n"); | |
a42a1844 EG |
2163 | goto out_pci_disable_device; |
2164 | } | |
2165 | ||
05f5b97e | 2166 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 2167 | if (!trans_pcie->hw_base) { |
d6f1c316 | 2168 | dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
2169 | err = -ENODEV; |
2170 | goto out_pci_release_regions; | |
2171 | } | |
2172 | ||
a42a1844 | 2173 | dev_printk(KERN_INFO, &pdev->dev, |
20d3b647 JB |
2174 | "pci_resource_len = 0x%08llx\n", |
2175 | (unsigned long long) pci_resource_len(pdev, 0)); | |
a42a1844 | 2176 | dev_printk(KERN_INFO, &pdev->dev, |
20d3b647 | 2177 | "pci_resource_base = %p\n", trans_pcie->hw_base); |
a42a1844 EG |
2178 | |
2179 | dev_printk(KERN_INFO, &pdev->dev, | |
20d3b647 | 2180 | "HW Revision ID = 0x%X\n", pdev->revision); |
a42a1844 EG |
2181 | |
2182 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
2183 | * PCI Tx retries from interfering with C3 CPU state */ | |
2184 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2185 | ||
2186 | err = pci_enable_msi(pdev); | |
2187 | if (err) | |
2188 | dev_printk(KERN_ERR, &pdev->dev, | |
d6f1c316 | 2189 | "pci_enable_msi failed(0X%x)\n", err); |
a42a1844 EG |
2190 | |
2191 | trans->dev = &pdev->dev; | |
75595536 | 2192 | trans_pcie->irq = pdev->irq; |
a42a1844 | 2193 | trans_pcie->pci_dev = pdev; |
08079a49 | 2194 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 2195 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2196 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2197 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 EG |
2198 | |
2199 | /* TODO: Move this away, not needed if not MSI */ | |
2200 | /* enable rfkill interrupt: hw bug w/a */ | |
2201 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2202 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2203 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2204 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2205 | } | |
2206 | ||
69a10b29 MV |
2207 | /* Initialize the wait queue for commands */ |
2208 | init_waitqueue_head(&trans->wait_command_queue); | |
8b5bed90 | 2209 | spin_lock_init(&trans->reg_lock); |
69a10b29 | 2210 | |
3ec45882 JB |
2211 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
2212 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
2213 | |
2214 | trans->dev_cmd_headroom = 0; | |
2215 | trans->dev_cmd_pool = | |
3ec45882 | 2216 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
2217 | sizeof(struct iwl_device_cmd) |
2218 | + trans->dev_cmd_headroom, | |
2219 | sizeof(void *), | |
2220 | SLAB_HWCACHE_ALIGN, | |
2221 | NULL); | |
2222 | ||
2223 | if (!trans->dev_cmd_pool) | |
2224 | goto out_pci_disable_msi; | |
2225 | ||
a42a1844 EG |
2226 | return trans; |
2227 | ||
59c647b6 EG |
2228 | out_pci_disable_msi: |
2229 | pci_disable_msi(pdev); | |
a42a1844 EG |
2230 | out_pci_release_regions: |
2231 | pci_release_regions(pdev); | |
2232 | out_pci_disable_device: | |
2233 | pci_disable_device(pdev); | |
2234 | out_no_pci: | |
2235 | kfree(trans); | |
2236 | return NULL; | |
2237 | } |