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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
c85eb619 EG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
c85eb619 EG |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
c85eb619 EG |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
a42a1844 EG |
65 | #include <linux/pci.h> |
66 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 67 | #include <linux/interrupt.h> |
87e5666c | 68 | #include <linux/debugfs.h> |
cf614297 | 69 | #include <linux/sched.h> |
6d8f6eeb EG |
70 | #include <linux/bitops.h> |
71 | #include <linux/gfp.h> | |
48eb7b34 | 72 | #include <linux/vmalloc.h> |
e6bb4c9c | 73 | |
82575102 | 74 | #include "iwl-drv.h" |
c85eb619 | 75 | #include "iwl-trans.h" |
522376d2 EG |
76 | #include "iwl-csr.h" |
77 | #include "iwl-prph.h" | |
7a10e3e4 | 78 | #include "iwl-agn-hw.h" |
4d075007 | 79 | #include "iwl-fw-error-dump.h" |
6468a01a | 80 | #include "internal.h" |
06d51e0d | 81 | #include "iwl-fh.h" |
0439bb62 | 82 | |
fe45773b AN |
83 | /* extended range in FW SRAM */ |
84 | #define IWL_FW_MEM_EXTENDED_START 0x40000 | |
85 | #define IWL_FW_MEM_EXTENDED_END 0x57FFF | |
86 | ||
c2d20201 EG |
87 | static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) |
88 | { | |
89 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
90 | ||
91 | if (!trans_pcie->fw_mon_page) | |
92 | return; | |
93 | ||
94 | dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, | |
95 | trans_pcie->fw_mon_size, DMA_FROM_DEVICE); | |
96 | __free_pages(trans_pcie->fw_mon_page, | |
97 | get_order(trans_pcie->fw_mon_size)); | |
98 | trans_pcie->fw_mon_page = NULL; | |
99 | trans_pcie->fw_mon_phys = 0; | |
100 | trans_pcie->fw_mon_size = 0; | |
101 | } | |
102 | ||
103 | static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans) | |
104 | { | |
105 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
106 | struct page *page; | |
107 | dma_addr_t phys; | |
108 | u32 size; | |
109 | u8 power; | |
110 | ||
111 | if (trans_pcie->fw_mon_page) { | |
112 | dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, | |
113 | trans_pcie->fw_mon_size, | |
114 | DMA_FROM_DEVICE); | |
115 | return; | |
116 | } | |
117 | ||
118 | phys = 0; | |
119 | for (power = 26; power >= 11; power--) { | |
120 | int order; | |
121 | ||
122 | size = BIT(power); | |
123 | order = get_order(size); | |
124 | page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, | |
125 | order); | |
126 | if (!page) | |
127 | continue; | |
128 | ||
129 | phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, | |
130 | DMA_FROM_DEVICE); | |
131 | if (dma_mapping_error(trans->dev, phys)) { | |
132 | __free_pages(page, order); | |
133 | continue; | |
134 | } | |
135 | IWL_INFO(trans, | |
136 | "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", | |
137 | size, order); | |
138 | break; | |
139 | } | |
140 | ||
40a76905 | 141 | if (WARN_ON_ONCE(!page)) |
c2d20201 EG |
142 | return; |
143 | ||
144 | trans_pcie->fw_mon_page = page; | |
145 | trans_pcie->fw_mon_phys = phys; | |
146 | trans_pcie->fw_mon_size = size; | |
147 | } | |
148 | ||
a812cba9 AB |
149 | static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) |
150 | { | |
151 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
152 | ((reg & 0x0000ffff) | (2 << 28))); | |
153 | return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); | |
154 | } | |
155 | ||
156 | static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) | |
157 | { | |
158 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); | |
159 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
160 | ((reg & 0x0000ffff) | (3 << 28))); | |
161 | } | |
162 | ||
ddaf5a5b | 163 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 164 | { |
ddaf5a5b JB |
165 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
166 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
167 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
168 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
169 | else | |
170 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
171 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
172 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
173 | } |
174 | ||
af634bee EG |
175 | /* PCI registers */ |
176 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 177 | |
7afe3705 | 178 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 179 | { |
20d3b647 | 180 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 181 | u16 lctl; |
9180ac50 | 182 | u16 cap; |
af634bee | 183 | |
af634bee EG |
184 | /* |
185 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
186 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
187 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
188 | * costs negligible amount of power savings. | |
189 | * If not (unlikely), enable L0S, so there is at least some | |
190 | * power savings, even without L1. | |
191 | */ | |
7afe3705 | 192 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
9180ac50 | 193 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) |
af634bee | 194 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
9180ac50 | 195 | else |
af634bee | 196 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
438a0f0a | 197 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
9180ac50 EG |
198 | |
199 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); | |
200 | trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; | |
201 | dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", | |
202 | (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", | |
203 | trans->ltr_enabled ? "En" : "Dis"); | |
af634bee EG |
204 | } |
205 | ||
a6c684ee EG |
206 | /* |
207 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 208 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
209 | * NOTE: This does not load uCode nor start the embedded processor |
210 | */ | |
7afe3705 | 211 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee EG |
212 | { |
213 | int ret = 0; | |
214 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
215 | ||
216 | /* | |
217 | * Use "set_bit" below rather than "write", to preserve any hardware | |
218 | * bits already set by default after reset. | |
219 | */ | |
220 | ||
221 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
e4a9f8ce EH |
222 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
223 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
224 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
a6c684ee EG |
225 | |
226 | /* | |
227 | * Disable L0s without affecting L1; | |
228 | * don't wait for ICH L0s (ICH bug W/A) | |
229 | */ | |
230 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 231 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
232 | |
233 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
234 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
235 | ||
236 | /* | |
237 | * Enable HAP INTA (interrupt from management bus) to | |
238 | * wake device's PCI Express link L1a -> L0s | |
239 | */ | |
240 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 241 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 242 | |
7afe3705 | 243 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
244 | |
245 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 246 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 247 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 248 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
249 | |
250 | /* | |
251 | * Set "initialization complete" bit to move adapter from | |
252 | * D0U* --> D0A* (powered-up active) state. | |
253 | */ | |
254 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
255 | ||
256 | /* | |
257 | * Wait for clock stabilization; once stabilized, access to | |
258 | * device-internal resources is supported, e.g. iwl_write_prph() | |
259 | * and accesses to uCode SRAM. | |
260 | */ | |
261 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
262 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
263 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
264 | if (ret < 0) { |
265 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
266 | goto out; | |
267 | } | |
268 | ||
2d93aee1 EG |
269 | if (trans->cfg->host_interrupt_operation_mode) { |
270 | /* | |
271 | * This is a bit of an abuse - This is needed for 7260 / 3160 | |
272 | * only check host_interrupt_operation_mode even if this is | |
273 | * not related to host_interrupt_operation_mode. | |
274 | * | |
275 | * Enable the oscillator to count wake up time for L1 exit. This | |
276 | * consumes slightly more power (100uA) - but allows to be sure | |
277 | * that we wake up from L1 on time. | |
278 | * | |
279 | * This looks weird: read twice the same register, discard the | |
280 | * value, set a bit, and yet again, read that same register | |
281 | * just to discard the value. But that's the way the hardware | |
282 | * seems to like it. | |
283 | */ | |
284 | iwl_read_prph(trans, OSC_CLK); | |
285 | iwl_read_prph(trans, OSC_CLK); | |
286 | iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); | |
287 | iwl_read_prph(trans, OSC_CLK); | |
288 | iwl_read_prph(trans, OSC_CLK); | |
289 | } | |
290 | ||
a6c684ee EG |
291 | /* |
292 | * Enable DMA clock and wait for it to stabilize. | |
293 | * | |
3073d8c0 EH |
294 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" |
295 | * bits do not disable clocks. This preserves any hardware | |
296 | * bits already set by default in "CLK_CTRL_REG" after reset. | |
a6c684ee | 297 | */ |
3073d8c0 EH |
298 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
299 | iwl_write_prph(trans, APMG_CLK_EN_REG, | |
300 | APMG_CLK_VAL_DMA_CLK_RQT); | |
301 | udelay(20); | |
302 | ||
303 | /* Disable L1-Active */ | |
304 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
305 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
306 | ||
307 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ | |
308 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, | |
309 | APMG_RTC_INT_STT_RFKILL); | |
310 | } | |
889b1696 | 311 | |
eb7ff77e | 312 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee EG |
313 | |
314 | out: | |
315 | return ret; | |
316 | } | |
317 | ||
a812cba9 AB |
318 | /* |
319 | * Enable LP XTAL to avoid HW bug where device may consume much power if | |
320 | * FW is not loaded after device reset. LP XTAL is disabled by default | |
321 | * after device HW reset. Do it only if XTAL is fed by internal source. | |
322 | * Configure device's "persistence" mode to avoid resetting XTAL again when | |
323 | * SHRD_HW_RST occurs in S3. | |
324 | */ | |
325 | static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) | |
326 | { | |
327 | int ret; | |
328 | u32 apmg_gp1_reg; | |
329 | u32 apmg_xtal_cfg_reg; | |
330 | u32 dl_cfg_reg; | |
331 | ||
332 | /* Force XTAL ON */ | |
333 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
334 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
335 | ||
336 | /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ | |
337 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
338 | ||
339 | udelay(10); | |
340 | ||
341 | /* | |
342 | * Set "initialization complete" bit to move adapter from | |
343 | * D0U* --> D0A* (powered-up active) state. | |
344 | */ | |
345 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
346 | ||
347 | /* | |
348 | * Wait for clock stabilization; once stabilized, access to | |
349 | * device-internal resources is possible. | |
350 | */ | |
351 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
352 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
353 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
354 | 25000); | |
355 | if (WARN_ON(ret < 0)) { | |
356 | IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); | |
357 | /* Release XTAL ON request */ | |
358 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
359 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
360 | return; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Clear "disable persistence" to avoid LP XTAL resetting when | |
365 | * SHRD_HW_RST is applied in S3. | |
366 | */ | |
367 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
368 | APMG_PCIDEV_STT_VAL_PERSIST_DIS); | |
369 | ||
370 | /* | |
371 | * Force APMG XTAL to be active to prevent its disabling by HW | |
372 | * caused by APMG idle state. | |
373 | */ | |
374 | apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, | |
375 | SHR_APMG_XTAL_CFG_REG); | |
376 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
377 | apmg_xtal_cfg_reg | | |
378 | SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
379 | ||
380 | /* | |
381 | * Reset entire device again - do controller reset (results in | |
382 | * SHRD_HW_RST). Turn MAC off before proceeding. | |
383 | */ | |
384 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
385 | ||
386 | udelay(10); | |
387 | ||
388 | /* Enable LP XTAL by indirect access through CSR */ | |
389 | apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); | |
390 | iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | | |
391 | SHR_APMG_GP1_WF_XTAL_LP_EN | | |
392 | SHR_APMG_GP1_CHICKEN_BIT_SELECT); | |
393 | ||
394 | /* Clear delay line clock power up */ | |
395 | dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); | |
396 | iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & | |
397 | ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); | |
398 | ||
399 | /* | |
400 | * Enable persistence mode to avoid LP XTAL resetting when | |
401 | * SHRD_HW_RST is applied in S3. | |
402 | */ | |
403 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
404 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
405 | ||
406 | /* | |
407 | * Clear "initialization complete" bit to move adapter from | |
408 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
409 | */ | |
410 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
411 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
412 | ||
413 | /* Activates XTAL resources monitor */ | |
414 | __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, | |
415 | CSR_MONITOR_XTAL_RESOURCES); | |
416 | ||
417 | /* Release XTAL ON request */ | |
418 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
419 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
420 | udelay(10); | |
421 | ||
422 | /* Release APMG XTAL */ | |
423 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
424 | apmg_xtal_cfg_reg & | |
425 | ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
426 | } | |
427 | ||
7afe3705 | 428 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
429 | { |
430 | int ret = 0; | |
431 | ||
432 | /* stop device's busmaster DMA activity */ | |
433 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
434 | ||
435 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
436 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
437 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
7f2ac8fb | 438 | if (ret < 0) |
cc56feb2 EG |
439 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); |
440 | ||
441 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
442 | ||
443 | return ret; | |
444 | } | |
445 | ||
b7aaeae4 | 446 | static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) |
cc56feb2 EG |
447 | { |
448 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
449 | ||
b7aaeae4 EG |
450 | if (op_mode_leave) { |
451 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
452 | iwl_pcie_apm_init(trans); | |
453 | ||
454 | /* inform ME that we are leaving */ | |
455 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) | |
456 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
457 | APMG_PCIDEV_STT_VAL_WAKE_ME); | |
458 | else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) | |
459 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
460 | CSR_HW_IF_CONFIG_REG_PREPARE | | |
461 | CSR_HW_IF_CONFIG_REG_ENABLE_PME); | |
462 | mdelay(5); | |
463 | } | |
464 | ||
eb7ff77e | 465 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
466 | |
467 | /* Stop device's DMA activity */ | |
7afe3705 | 468 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 | 469 | |
a812cba9 AB |
470 | if (trans->cfg->lp_xtal_workaround) { |
471 | iwl_pcie_apm_lp_xtal_enable(trans); | |
472 | return; | |
473 | } | |
474 | ||
cc56feb2 EG |
475 | /* Reset the entire device */ |
476 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
477 | ||
478 | udelay(10); | |
479 | ||
480 | /* | |
481 | * Clear "initialization complete" bit to move adapter from | |
482 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
483 | */ | |
484 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
485 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
486 | } | |
487 | ||
7afe3705 | 488 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 489 | { |
7b11488f | 490 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
491 | |
492 | /* nic_init */ | |
7b70bd63 | 493 | spin_lock(&trans_pcie->irq_lock); |
7afe3705 | 494 | iwl_pcie_apm_init(trans); |
392f8b78 | 495 | |
7b70bd63 | 496 | spin_unlock(&trans_pcie->irq_lock); |
392f8b78 | 497 | |
3073d8c0 EH |
498 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
499 | iwl_pcie_set_pwr(trans, false); | |
392f8b78 | 500 | |
ecdb975c | 501 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
502 | |
503 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 504 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
505 | |
506 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 507 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
508 | return -ENOMEM; |
509 | ||
035f7ff2 | 510 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 511 | /* enable shadow regs in HW */ |
20d3b647 | 512 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 513 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
514 | } |
515 | ||
392f8b78 EG |
516 | return 0; |
517 | } | |
518 | ||
519 | #define HW_READY_TIMEOUT (50) | |
520 | ||
521 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 522 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
523 | { |
524 | int ret; | |
525 | ||
1042db2a | 526 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 527 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
528 | |
529 | /* See if we got it */ | |
1042db2a | 530 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
531 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
532 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
533 | HW_READY_TIMEOUT); | |
392f8b78 | 534 | |
6a08f514 EG |
535 | if (ret >= 0) |
536 | iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); | |
537 | ||
6d8f6eeb | 538 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
539 | return ret; |
540 | } | |
541 | ||
542 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 543 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
544 | { |
545 | int ret; | |
289e5501 | 546 | int t = 0; |
501fd989 | 547 | int iter; |
392f8b78 | 548 | |
6d8f6eeb | 549 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 550 | |
7afe3705 | 551 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 552 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
553 | if (ret >= 0) |
554 | return 0; | |
555 | ||
501fd989 EG |
556 | for (iter = 0; iter < 10; iter++) { |
557 | /* If HW is not ready, prepare the conditions to check again */ | |
558 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
559 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
560 | ||
561 | do { | |
562 | ret = iwl_pcie_set_hw_ready(trans); | |
563 | if (ret >= 0) | |
564 | return 0; | |
392f8b78 | 565 | |
501fd989 EG |
566 | usleep_range(200, 1000); |
567 | t += 200; | |
568 | } while (t < 150000); | |
569 | msleep(25); | |
570 | } | |
392f8b78 | 571 | |
7f2ac8fb | 572 | IWL_ERR(trans, "Couldn't prepare the card\n"); |
392f8b78 | 573 | |
392f8b78 EG |
574 | return ret; |
575 | } | |
576 | ||
cf614297 EG |
577 | /* |
578 | * ucode | |
579 | */ | |
7afe3705 | 580 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 581 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 582 | { |
13df1aab | 583 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
584 | int ret; |
585 | ||
13df1aab | 586 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
587 | |
588 | iwl_write_direct32(trans, | |
20d3b647 JB |
589 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
590 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
591 | |
592 | iwl_write_direct32(trans, | |
20d3b647 JB |
593 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
594 | dst_addr); | |
cf614297 EG |
595 | |
596 | iwl_write_direct32(trans, | |
83f84d7b JB |
597 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
598 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
599 | |
600 | iwl_write_direct32(trans, | |
20d3b647 JB |
601 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
602 | (iwl_get_dma_hi_addr(phy_addr) | |
603 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
604 | |
605 | iwl_write_direct32(trans, | |
20d3b647 JB |
606 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
607 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
608 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
609 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
610 | |
611 | iwl_write_direct32(trans, | |
20d3b647 JB |
612 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
613 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
614 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
615 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 616 | |
13df1aab JB |
617 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
618 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 619 | if (!ret) { |
83f84d7b | 620 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
621 | return -ETIMEDOUT; |
622 | } | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
7afe3705 | 627 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 628 | const struct fw_desc *section) |
cf614297 | 629 | { |
83f84d7b JB |
630 | u8 *v_addr; |
631 | dma_addr_t p_addr; | |
baa21e83 | 632 | u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); |
cf614297 EG |
633 | int ret = 0; |
634 | ||
83f84d7b JB |
635 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
636 | section_num); | |
637 | ||
c571573a EG |
638 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
639 | GFP_KERNEL | __GFP_NOWARN); | |
640 | if (!v_addr) { | |
641 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
642 | chunk_sz = PAGE_SIZE; | |
643 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
644 | &p_addr, GFP_KERNEL); | |
645 | if (!v_addr) | |
646 | return -ENOMEM; | |
647 | } | |
83f84d7b | 648 | |
c571573a | 649 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
fe45773b AN |
650 | u32 copy_size, dst_addr; |
651 | bool extended_addr = false; | |
83f84d7b | 652 | |
c571573a | 653 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
fe45773b AN |
654 | dst_addr = section->offset + offset; |
655 | ||
656 | if (dst_addr >= IWL_FW_MEM_EXTENDED_START && | |
657 | dst_addr <= IWL_FW_MEM_EXTENDED_END) | |
658 | extended_addr = true; | |
659 | ||
660 | if (extended_addr) | |
661 | iwl_set_bits_prph(trans, LMPM_CHICK, | |
662 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
cf614297 | 663 | |
83f84d7b | 664 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
fe45773b AN |
665 | ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, |
666 | copy_size); | |
667 | ||
668 | if (extended_addr) | |
669 | iwl_clear_bits_prph(trans, LMPM_CHICK, | |
670 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
671 | ||
83f84d7b JB |
672 | if (ret) { |
673 | IWL_ERR(trans, | |
674 | "Could not load the [%d] uCode section\n", | |
675 | section_num); | |
676 | break; | |
6dfa8d01 | 677 | } |
83f84d7b JB |
678 | } |
679 | ||
c571573a | 680 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
681 | return ret; |
682 | } | |
683 | ||
dcab8ecd EH |
684 | static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans, |
685 | const struct fw_img *image, | |
686 | int cpu, | |
687 | int *first_ucode_section) | |
e2d6f4e7 EH |
688 | { |
689 | int shift_param; | |
dcab8ecd EH |
690 | int i, ret = 0, sec_num = 0x1; |
691 | u32 val, last_read_idx = 0; | |
e2d6f4e7 EH |
692 | |
693 | if (cpu == 1) { | |
694 | shift_param = 0; | |
034846cf | 695 | *first_ucode_section = 0; |
e2d6f4e7 EH |
696 | } else { |
697 | shift_param = 16; | |
034846cf | 698 | (*first_ucode_section)++; |
e2d6f4e7 EH |
699 | } |
700 | ||
034846cf EH |
701 | for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { |
702 | last_read_idx = i; | |
703 | ||
704 | if (!image->sec[i].data || | |
705 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) { | |
706 | IWL_DEBUG_FW(trans, | |
707 | "Break since Data not valid or Empty section, sec = %d\n", | |
708 | i); | |
189fa2fa | 709 | break; |
034846cf EH |
710 | } |
711 | ||
189fa2fa EH |
712 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
713 | if (ret) | |
714 | return ret; | |
dcab8ecd EH |
715 | |
716 | /* Notify the ucode of the loaded section number and status */ | |
717 | val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); | |
718 | val = val | (sec_num << shift_param); | |
719 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); | |
720 | sec_num = (sec_num << 1) | 0x1; | |
e2d6f4e7 EH |
721 | } |
722 | ||
034846cf EH |
723 | *first_ucode_section = last_read_idx; |
724 | ||
afb88917 EH |
725 | if (cpu == 1) |
726 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); | |
727 | else | |
728 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); | |
729 | ||
189fa2fa EH |
730 | return 0; |
731 | } | |
e2d6f4e7 | 732 | |
189fa2fa EH |
733 | static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, |
734 | const struct fw_img *image, | |
034846cf EH |
735 | int cpu, |
736 | int *first_ucode_section) | |
189fa2fa EH |
737 | { |
738 | int shift_param; | |
189fa2fa | 739 | int i, ret = 0; |
034846cf | 740 | u32 last_read_idx = 0; |
189fa2fa EH |
741 | |
742 | if (cpu == 1) { | |
743 | shift_param = 0; | |
034846cf | 744 | *first_ucode_section = 0; |
189fa2fa EH |
745 | } else { |
746 | shift_param = 16; | |
034846cf | 747 | (*first_ucode_section)++; |
189fa2fa EH |
748 | } |
749 | ||
034846cf EH |
750 | for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { |
751 | last_read_idx = i; | |
752 | ||
753 | if (!image->sec[i].data || | |
754 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) { | |
755 | IWL_DEBUG_FW(trans, | |
756 | "Break since Data not valid or Empty section, sec = %d\n", | |
757 | i); | |
189fa2fa | 758 | break; |
034846cf EH |
759 | } |
760 | ||
189fa2fa EH |
761 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
762 | if (ret) | |
763 | return ret; | |
e2d6f4e7 EH |
764 | } |
765 | ||
189fa2fa EH |
766 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
767 | iwl_set_bits_prph(trans, | |
768 | CSR_UCODE_LOAD_STATUS_ADDR, | |
769 | (LMPM_CPU_UCODE_LOADING_COMPLETED | | |
770 | LMPM_CPU_HDRS_LOADING_COMPLETED | | |
771 | LMPM_CPU_UCODE_LOADING_STARTED) << | |
772 | shift_param); | |
773 | ||
034846cf EH |
774 | *first_ucode_section = last_read_idx; |
775 | ||
e2d6f4e7 EH |
776 | return 0; |
777 | } | |
778 | ||
09e350f7 LK |
779 | static void iwl_pcie_apply_destination(struct iwl_trans *trans) |
780 | { | |
781 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
782 | const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; | |
783 | int i; | |
784 | ||
785 | if (dest->version) | |
786 | IWL_ERR(trans, | |
787 | "DBG DEST version is %d - expect issues\n", | |
788 | dest->version); | |
789 | ||
790 | IWL_INFO(trans, "Applying debug destination %s\n", | |
791 | get_fw_dbg_mode_string(dest->monitor_mode)); | |
792 | ||
793 | if (dest->monitor_mode == EXTERNAL_MODE) | |
794 | iwl_pcie_alloc_fw_monitor(trans); | |
795 | else | |
796 | IWL_WARN(trans, "PCI should have external buffer debug\n"); | |
797 | ||
798 | for (i = 0; i < trans->dbg_dest_reg_num; i++) { | |
799 | u32 addr = le32_to_cpu(dest->reg_ops[i].addr); | |
800 | u32 val = le32_to_cpu(dest->reg_ops[i].val); | |
801 | ||
802 | switch (dest->reg_ops[i].op) { | |
803 | case CSR_ASSIGN: | |
804 | iwl_write32(trans, addr, val); | |
805 | break; | |
806 | case CSR_SETBIT: | |
807 | iwl_set_bit(trans, addr, BIT(val)); | |
808 | break; | |
809 | case CSR_CLEARBIT: | |
810 | iwl_clear_bit(trans, addr, BIT(val)); | |
811 | break; | |
812 | case PRPH_ASSIGN: | |
813 | iwl_write_prph(trans, addr, val); | |
814 | break; | |
815 | case PRPH_SETBIT: | |
816 | iwl_set_bits_prph(trans, addr, BIT(val)); | |
817 | break; | |
818 | case PRPH_CLEARBIT: | |
819 | iwl_clear_bits_prph(trans, addr, BIT(val)); | |
820 | break; | |
821 | default: | |
822 | IWL_ERR(trans, "FW debug - unknown OP %d\n", | |
823 | dest->reg_ops[i].op); | |
824 | break; | |
825 | } | |
826 | } | |
827 | ||
828 | if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { | |
829 | iwl_write_prph(trans, le32_to_cpu(dest->base_reg), | |
830 | trans_pcie->fw_mon_phys >> dest->base_shift); | |
831 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), | |
832 | (trans_pcie->fw_mon_phys + | |
833 | trans_pcie->fw_mon_size) >> dest->end_shift); | |
834 | } | |
835 | } | |
836 | ||
7afe3705 | 837 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 838 | const struct fw_img *image) |
cf614297 | 839 | { |
c2d20201 | 840 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
189fa2fa | 841 | int ret = 0; |
034846cf | 842 | int first_ucode_section; |
cf614297 | 843 | |
dcab8ecd | 844 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
e2d6f4e7 EH |
845 | image->is_dual_cpus ? "Dual" : "Single"); |
846 | ||
dcab8ecd EH |
847 | /* load to FW the binary non secured sections of CPU1 */ |
848 | ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); | |
849 | if (ret) | |
850 | return ret; | |
e2d6f4e7 EH |
851 | |
852 | if (image->is_dual_cpus) { | |
189fa2fa EH |
853 | /* set CPU2 header address */ |
854 | iwl_write_prph(trans, | |
855 | LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, | |
856 | LMPM_SECURE_CPU2_HDR_MEM_SPACE); | |
e2d6f4e7 | 857 | |
189fa2fa | 858 | /* load to FW the binary sections of CPU2 */ |
dcab8ecd EH |
859 | ret = iwl_pcie_load_cpu_sections(trans, image, 2, |
860 | &first_ucode_section); | |
189fa2fa EH |
861 | if (ret) |
862 | return ret; | |
e2d6f4e7 | 863 | } |
cf614297 | 864 | |
c2d20201 EG |
865 | /* supported for 7000 only for the moment */ |
866 | if (iwlwifi_mod_params.fw_monitor && | |
867 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { | |
868 | iwl_pcie_alloc_fw_monitor(trans); | |
869 | ||
870 | if (trans_pcie->fw_mon_size) { | |
871 | iwl_write_prph(trans, MON_BUFF_BASE_ADDR, | |
872 | trans_pcie->fw_mon_phys >> 4); | |
873 | iwl_write_prph(trans, MON_BUFF_END_ADDR, | |
874 | (trans_pcie->fw_mon_phys + | |
875 | trans_pcie->fw_mon_size) >> 4); | |
876 | } | |
09e350f7 LK |
877 | } else if (trans->dbg_dest_tlv) { |
878 | iwl_pcie_apply_destination(trans); | |
c2d20201 EG |
879 | } |
880 | ||
e12ba844 EH |
881 | /* release CPU reset */ |
882 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) | |
883 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); | |
884 | else | |
885 | iwl_write32(trans, CSR_RESET, 0); | |
886 | ||
dcab8ecd EH |
887 | return 0; |
888 | } | |
189fa2fa | 889 | |
dcab8ecd EH |
890 | static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans, |
891 | const struct fw_img *image) | |
892 | { | |
893 | int ret = 0; | |
894 | int first_ucode_section; | |
895 | u32 reg; | |
896 | ||
897 | IWL_DEBUG_FW(trans, "working with %s CPU\n", | |
898 | image->is_dual_cpus ? "Dual" : "Single"); | |
899 | ||
900 | /* configure the ucode to be ready to get the secured image */ | |
901 | /* release CPU reset */ | |
902 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); | |
903 | ||
904 | /* load to FW the binary Secured sections of CPU1 */ | |
905 | ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1, | |
906 | &first_ucode_section); | |
907 | if (ret) | |
908 | return ret; | |
909 | ||
910 | /* load to FW the binary sections of CPU2 */ | |
911 | ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2, | |
912 | &first_ucode_section); | |
913 | if (ret) | |
914 | return ret; | |
915 | ||
ff298624 EH |
916 | if (trans->dbg_dest_tlv) |
917 | iwl_pcie_apply_destination(trans); | |
918 | ||
dcab8ecd EH |
919 | /* wait for image verification to complete */ |
920 | ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0, | |
921 | LMPM_SECURE_BOOT_STATUS_SUCCESS, | |
922 | LMPM_SECURE_BOOT_STATUS_SUCCESS, | |
923 | LMPM_SECURE_TIME_OUT); | |
924 | if (ret < 0) { | |
925 | reg = iwl_read_prph(trans, | |
926 | LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0); | |
927 | ||
928 | IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n", | |
929 | reg); | |
930 | return ret; | |
189fa2fa EH |
931 | } |
932 | ||
cf614297 EG |
933 | return 0; |
934 | } | |
935 | ||
0692fe41 | 936 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 937 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 | 938 | { |
7616f334 | 939 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 | 940 | int ret; |
c9eec95c | 941 | bool hw_rfkill; |
392f8b78 | 942 | |
496bab39 | 943 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 944 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 945 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
946 | return -EIO; |
947 | } | |
948 | ||
8c46bb70 EG |
949 | iwl_enable_rfkill_int(trans); |
950 | ||
392f8b78 | 951 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 952 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 953 | if (hw_rfkill) |
eb7ff77e | 954 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 955 | else |
eb7ff77e | 956 | clear_bit(STATUS_RFKILL, &trans->status); |
14cfca71 | 957 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
6ae02f3e | 958 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 959 | return -ERFKILL; |
392f8b78 | 960 | |
1042db2a | 961 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 962 | |
7afe3705 | 963 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 964 | if (ret) { |
6d8f6eeb | 965 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
966 | return ret; |
967 | } | |
968 | ||
7616f334 EP |
969 | /* init ref_count to 1 (should be cleared when ucode is loaded) */ |
970 | trans_pcie->ref_count = 1; | |
971 | ||
392f8b78 | 972 | /* make sure rfkill handshake bits are cleared */ |
1042db2a EG |
973 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
974 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
975 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
976 | ||
977 | /* clear (again), then enable host interrupts */ | |
1042db2a | 978 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 979 | iwl_enable_interrupts(trans); |
392f8b78 EG |
980 | |
981 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
982 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
983 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 984 | |
cf614297 | 985 | /* Load the given image to the HW */ |
dcab8ecd | 986 | if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) && |
716e48a6 | 987 | (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP)) |
dcab8ecd EH |
988 | return iwl_pcie_load_given_ucode_8000b(trans, fw); |
989 | else | |
990 | return iwl_pcie_load_given_ucode(trans, fw); | |
b3c2ce13 EG |
991 | } |
992 | ||
adca1235 | 993 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 994 | { |
990aa6d7 | 995 | iwl_pcie_reset_ict(trans); |
f02831be | 996 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
997 | } |
998 | ||
43e58856 | 999 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 1000 | { |
43e58856 | 1001 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3dc3374f EG |
1002 | bool hw_rfkill, was_hw_rfkill; |
1003 | ||
1004 | was_hw_rfkill = iwl_is_rfkill_set(trans); | |
ae2c30bf | 1005 | |
43e58856 | 1006 | /* tell the device to stop sending interrupts */ |
7b70bd63 | 1007 | spin_lock(&trans_pcie->irq_lock); |
ae2c30bf | 1008 | iwl_disable_interrupts(trans); |
7b70bd63 | 1009 | spin_unlock(&trans_pcie->irq_lock); |
ae2c30bf | 1010 | |
ab6cf8e8 | 1011 | /* device going down, Stop using ICT table */ |
990aa6d7 | 1012 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
1013 | |
1014 | /* | |
1015 | * If a HW restart happens during firmware loading, | |
1016 | * then the firmware loading might call this function | |
1017 | * and later it might be called again due to the | |
1018 | * restart. So don't process again if the device is | |
1019 | * already dead. | |
1020 | */ | |
31b8b343 EG |
1021 | if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
1022 | IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n"); | |
f02831be | 1023 | iwl_pcie_tx_stop(trans); |
9805c446 | 1024 | iwl_pcie_rx_stop(trans); |
6379103e | 1025 | |
ab6cf8e8 | 1026 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 1027 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1028 | APMG_CLK_VAL_DMA_CLK_RQT); |
1029 | udelay(5); | |
1030 | } | |
1031 | ||
1032 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1033 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 1034 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1035 | |
1036 | /* Stop the device, and put it in low power state */ | |
b7aaeae4 | 1037 | iwl_pcie_apm_stop(trans, false); |
43e58856 | 1038 | |
03d6c3b0 EG |
1039 | /* stop and reset the on-board processor */ |
1040 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
1041 | udelay(20); | |
1042 | ||
1043 | /* | |
1044 | * Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1045 | * This is a bug in certain verions of the hardware. | |
1046 | * Certain devices also keep sending HW RF kill interrupt all | |
1047 | * the time, unless the interrupt is ACKed even if the interrupt | |
1048 | * should be masked. Re-ACK all the interrupts here. | |
43e58856 | 1049 | */ |
7b70bd63 | 1050 | spin_lock(&trans_pcie->irq_lock); |
43e58856 | 1051 | iwl_disable_interrupts(trans); |
7b70bd63 | 1052 | spin_unlock(&trans_pcie->irq_lock); |
43e58856 | 1053 | |
74fda971 DF |
1054 | |
1055 | /* clear all status bits */ | |
eb7ff77e AN |
1056 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
1057 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
eb7ff77e AN |
1058 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
1059 | clear_bit(STATUS_RFKILL, &trans->status); | |
a4082843 AN |
1060 | |
1061 | /* | |
1062 | * Even if we stop the HW, we still want the RF kill | |
1063 | * interrupt | |
1064 | */ | |
1065 | iwl_enable_rfkill_int(trans); | |
1066 | ||
1067 | /* | |
1068 | * Check again since the RF kill state may have changed while | |
1069 | * all the interrupts were disabled, in this case we couldn't | |
1070 | * receive the RF kill interrupt and update the state in the | |
1071 | * op_mode. | |
3dc3374f EG |
1072 | * Don't call the op_mode if the rkfill state hasn't changed. |
1073 | * This allows the op_mode to call stop_device from the rfkill | |
1074 | * notification without endless recursion. Under very rare | |
1075 | * circumstances, we might have a small recursion if the rfkill | |
1076 | * state changed exactly now while we were called from stop_device. | |
1077 | * This is very unlikely but can happen and is supported. | |
a4082843 AN |
1078 | */ |
1079 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1080 | if (hw_rfkill) | |
eb7ff77e | 1081 | set_bit(STATUS_RFKILL, &trans->status); |
a4082843 | 1082 | else |
eb7ff77e | 1083 | clear_bit(STATUS_RFKILL, &trans->status); |
3dc3374f | 1084 | if (hw_rfkill != was_hw_rfkill) |
14cfca71 | 1085 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
655e5cf0 EG |
1086 | |
1087 | /* re-take ownership to prevent other users from stealing the deivce */ | |
1088 | iwl_pcie_prepare_card_hw(trans); | |
14cfca71 JB |
1089 | } |
1090 | ||
1091 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) | |
1092 | { | |
1093 | if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) | |
1094 | iwl_trans_pcie_stop_device(trans); | |
ab6cf8e8 EG |
1095 | } |
1096 | ||
debff618 | 1097 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) |
2dd4f9f7 | 1098 | { |
2dd4f9f7 | 1099 | iwl_disable_interrupts(trans); |
debff618 JB |
1100 | |
1101 | /* | |
1102 | * in testing mode, the host stays awake and the | |
1103 | * hardware won't be reset (not even partially) | |
1104 | */ | |
1105 | if (test) | |
1106 | return; | |
1107 | ||
ddaf5a5b JB |
1108 | iwl_pcie_disable_ict(trans); |
1109 | ||
2dd4f9f7 JB |
1110 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1111 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
1112 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1113 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1114 | ||
1115 | /* | |
1116 | * reset TX queues -- some of their registers reset during S3 | |
1117 | * so if we don't reset everything here the D3 image would try | |
1118 | * to execute some invalid memory upon resume | |
1119 | */ | |
1120 | iwl_trans_pcie_tx_reset(trans); | |
1121 | ||
1122 | iwl_pcie_set_pwr(trans, true); | |
1123 | } | |
1124 | ||
1125 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
1126 | enum iwl_d3_status *status, |
1127 | bool test) | |
ddaf5a5b JB |
1128 | { |
1129 | u32 val; | |
1130 | int ret; | |
1131 | ||
debff618 JB |
1132 | if (test) { |
1133 | iwl_enable_interrupts(trans); | |
1134 | *status = IWL_D3_STATUS_ALIVE; | |
1135 | return 0; | |
1136 | } | |
1137 | ||
ddaf5a5b JB |
1138 | /* |
1139 | * Also enables interrupts - none will happen as the device doesn't | |
1140 | * know we're waking it up, only when the opmode actually tells it | |
1141 | * after this call. | |
1142 | */ | |
1143 | iwl_pcie_reset_ict(trans); | |
1144 | ||
1145 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1146 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1147 | ||
01e58a28 EG |
1148 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1149 | udelay(2); | |
1150 | ||
ddaf5a5b JB |
1151 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, |
1152 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1153 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1154 | 25000); | |
7f2ac8fb | 1155 | if (ret < 0) { |
ddaf5a5b JB |
1156 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); |
1157 | return ret; | |
1158 | } | |
1159 | ||
a3ead656 EG |
1160 | iwl_pcie_set_pwr(trans, false); |
1161 | ||
ddaf5a5b JB |
1162 | iwl_trans_pcie_tx_reset(trans); |
1163 | ||
1164 | ret = iwl_pcie_rx_init(trans); | |
1165 | if (ret) { | |
1166 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
1167 | return ret; | |
1168 | } | |
1169 | ||
a3ead656 EG |
1170 | val = iwl_read32(trans, CSR_RESET); |
1171 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) | |
1172 | *status = IWL_D3_STATUS_RESET; | |
1173 | else | |
1174 | *status = IWL_D3_STATUS_ALIVE; | |
1175 | ||
ddaf5a5b | 1176 | return 0; |
2dd4f9f7 JB |
1177 | } |
1178 | ||
57a1dc89 | 1179 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 1180 | { |
c9eec95c | 1181 | bool hw_rfkill; |
a8b691e6 | 1182 | int err; |
e6bb4c9c | 1183 | |
7afe3705 | 1184 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 1185 | if (err) { |
d6f1c316 | 1186 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 1187 | return err; |
ebb7678d | 1188 | } |
a6c684ee | 1189 | |
2997494f | 1190 | /* Reset the entire device */ |
ce836c76 | 1191 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
2997494f EG |
1192 | |
1193 | usleep_range(10, 15); | |
1194 | ||
7afe3705 | 1195 | iwl_pcie_apm_init(trans); |
a6c684ee | 1196 | |
226c02ca EG |
1197 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1198 | iwl_enable_rfkill_int(trans); | |
1199 | ||
8d425517 | 1200 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 1201 | if (hw_rfkill) |
eb7ff77e | 1202 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 1203 | else |
eb7ff77e | 1204 | clear_bit(STATUS_RFKILL, &trans->status); |
14cfca71 | 1205 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
d48e2074 | 1206 | |
a8b691e6 | 1207 | return 0; |
e6bb4c9c EG |
1208 | } |
1209 | ||
a4082843 | 1210 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 1211 | { |
20d3b647 | 1212 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1213 | |
a4082843 | 1214 | /* disable interrupts - don't enable HW RF kill interrupt */ |
7b70bd63 | 1215 | spin_lock(&trans_pcie->irq_lock); |
ee7d737c | 1216 | iwl_disable_interrupts(trans); |
7b70bd63 | 1217 | spin_unlock(&trans_pcie->irq_lock); |
ee7d737c | 1218 | |
b7aaeae4 | 1219 | iwl_pcie_apm_stop(trans, true); |
cc56feb2 | 1220 | |
7b70bd63 | 1221 | spin_lock(&trans_pcie->irq_lock); |
218733cf | 1222 | iwl_disable_interrupts(trans); |
7b70bd63 | 1223 | spin_unlock(&trans_pcie->irq_lock); |
1df06bdc | 1224 | |
8d96bb61 | 1225 | iwl_pcie_disable_ict(trans); |
cc56feb2 EG |
1226 | } |
1227 | ||
03905495 EG |
1228 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1229 | { | |
05f5b97e | 1230 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1231 | } |
1232 | ||
1233 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1234 | { | |
05f5b97e | 1235 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1236 | } |
1237 | ||
1238 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1239 | { | |
05f5b97e | 1240 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1241 | } |
1242 | ||
6a06b6c1 EG |
1243 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
1244 | { | |
f9477c17 AP |
1245 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
1246 | ((reg & 0x000FFFFF) | (3 << 24))); | |
6a06b6c1 EG |
1247 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
1248 | } | |
1249 | ||
1250 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
1251 | u32 val) | |
1252 | { | |
1253 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
f9477c17 | 1254 | ((addr & 0x000FFFFF) | (3 << 24))); |
6a06b6c1 EG |
1255 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
1256 | } | |
1257 | ||
f14d6b39 JB |
1258 | static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) |
1259 | { | |
1260 | WARN_ON(1); | |
1261 | return 0; | |
1262 | } | |
1263 | ||
c6f600fc | 1264 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1265 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1266 | { |
1267 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1268 | ||
1269 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 1270 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
1271 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1272 | trans_pcie->n_no_reclaim_cmds = 0; | |
1273 | else | |
1274 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1275 | if (trans_pcie->n_no_reclaim_cmds) | |
1276 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1277 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 1278 | |
b2cf410c JB |
1279 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
1280 | if (trans_pcie->rx_buf_size_8k) | |
1281 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
1282 | else | |
1283 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
1284 | |
1285 | trans_pcie->wd_timeout = | |
1286 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
1287 | |
1288 | trans_pcie->command_names = trans_cfg->command_names; | |
046db346 | 1289 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
3a736bcb | 1290 | trans_pcie->scd_set_active = trans_cfg->scd_set_active; |
f14d6b39 JB |
1291 | |
1292 | /* Initialize NAPI here - it should be before registering to mac80211 | |
1293 | * in the opmode but after the HW struct is allocated. | |
1294 | * As this function may be called again in some corner cases don't | |
1295 | * do anything if NAPI was already initialized. | |
1296 | */ | |
1297 | if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) { | |
1298 | init_dummy_netdev(&trans_pcie->napi_dev); | |
1299 | iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi, | |
1300 | &trans_pcie->napi_dev, | |
1301 | iwl_pcie_dummy_napi_poll, 64); | |
1302 | } | |
c6f600fc MV |
1303 | } |
1304 | ||
d1ff5253 | 1305 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1306 | { |
20d3b647 | 1307 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 1308 | |
0aa86df6 | 1309 | synchronize_irq(trans_pcie->pci_dev->irq); |
0aa86df6 | 1310 | |
f02831be | 1311 | iwl_pcie_tx_free(trans); |
9805c446 | 1312 | iwl_pcie_rx_free(trans); |
6379103e | 1313 | |
a8b691e6 JB |
1314 | free_irq(trans_pcie->pci_dev->irq, trans); |
1315 | iwl_pcie_free_ict(trans); | |
a42a1844 EG |
1316 | |
1317 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 1318 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
1319 | pci_release_regions(trans_pcie->pci_dev); |
1320 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 1321 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 1322 | |
f14d6b39 JB |
1323 | if (trans_pcie->napi.poll) |
1324 | netif_napi_del(&trans_pcie->napi); | |
1325 | ||
c2d20201 EG |
1326 | iwl_pcie_free_fw_monitor(trans); |
1327 | ||
6d8f6eeb | 1328 | kfree(trans); |
34c1b7ba EG |
1329 | } |
1330 | ||
47107e84 DF |
1331 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1332 | { | |
47107e84 | 1333 | if (state) |
eb7ff77e | 1334 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 1335 | else |
eb7ff77e | 1336 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
1337 | } |
1338 | ||
e56b04ef LE |
1339 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, |
1340 | unsigned long *flags) | |
7a65d170 EG |
1341 | { |
1342 | int ret; | |
cfb4e624 JB |
1343 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1344 | ||
1345 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 | 1346 | |
b9439491 EG |
1347 | if (trans_pcie->cmd_in_flight) |
1348 | goto out; | |
1349 | ||
7a65d170 | 1350 | /* this bit wakes up the NIC */ |
e139dc4a LE |
1351 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1352 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
01e58a28 EG |
1353 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1354 | udelay(2); | |
7a65d170 EG |
1355 | |
1356 | /* | |
1357 | * These bits say the device is running, and should keep running for | |
1358 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
1359 | * but they do not indicate that embedded SRAM is restored yet; | |
1360 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
1361 | * to/from host DRAM when sleeping/waking for power-saving. | |
1362 | * Each direction takes approximately 1/4 millisecond; with this | |
1363 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
1364 | * series of register accesses are expected (e.g. reading Event Log), | |
1365 | * to keep device from sleeping. | |
1366 | * | |
1367 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
1368 | * SRAM is okay/restored. We don't check that here because this call | |
1369 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
1370 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
1371 | * | |
1372 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
1373 | * and do not save/restore SRAM when power cycling. | |
1374 | */ | |
1375 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1376 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1377 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1378 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
1379 | if (unlikely(ret < 0)) { | |
1380 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
1381 | if (!silent) { | |
1382 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
1383 | WARN_ONCE(1, | |
1384 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
1385 | val); | |
cfb4e624 | 1386 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
1387 | return false; |
1388 | } | |
1389 | } | |
1390 | ||
b9439491 | 1391 | out: |
e56b04ef LE |
1392 | /* |
1393 | * Fool sparse by faking we release the lock - sparse will | |
1394 | * track nic_access anyway. | |
1395 | */ | |
cfb4e624 | 1396 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
1397 | return true; |
1398 | } | |
1399 | ||
e56b04ef LE |
1400 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
1401 | unsigned long *flags) | |
7a65d170 | 1402 | { |
cfb4e624 | 1403 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 1404 | |
cfb4e624 | 1405 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
1406 | |
1407 | /* | |
1408 | * Fool sparse by faking we acquiring the lock - sparse will | |
1409 | * track nic_access anyway. | |
1410 | */ | |
cfb4e624 | 1411 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 1412 | |
b9439491 EG |
1413 | if (trans_pcie->cmd_in_flight) |
1414 | goto out; | |
1415 | ||
e139dc4a LE |
1416 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
1417 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
1418 | /* |
1419 | * Above we read the CSR_GP_CNTRL register, which will flush | |
1420 | * any previous writes, but we need the write that clears the | |
1421 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
1422 | * scheduled on different CPUs (after we drop reg_lock). | |
1423 | */ | |
1424 | mmiowb(); | |
b9439491 | 1425 | out: |
cfb4e624 | 1426 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
1427 | } |
1428 | ||
4fd442db EG |
1429 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
1430 | void *buf, int dwords) | |
1431 | { | |
1432 | unsigned long flags; | |
1433 | int offs, ret = 0; | |
1434 | u32 *vals = buf; | |
1435 | ||
e56b04ef | 1436 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1437 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
1438 | for (offs = 0; offs < dwords; offs++) | |
1439 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 1440 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1441 | } else { |
1442 | ret = -EBUSY; | |
1443 | } | |
4fd442db EG |
1444 | return ret; |
1445 | } | |
1446 | ||
1447 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1448 | const void *buf, int dwords) |
4fd442db EG |
1449 | { |
1450 | unsigned long flags; | |
1451 | int offs, ret = 0; | |
bf0fd5da | 1452 | const u32 *vals = buf; |
4fd442db | 1453 | |
e56b04ef | 1454 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1455 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
1456 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
1457 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
1458 | vals ? vals[offs] : 0); | |
e56b04ef | 1459 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1460 | } else { |
1461 | ret = -EBUSY; | |
1462 | } | |
4fd442db EG |
1463 | return ret; |
1464 | } | |
7a65d170 | 1465 | |
5f178cd2 EG |
1466 | #define IWL_FLUSH_WAIT_MS 2000 |
1467 | ||
3cafdbe6 | 1468 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) |
5f178cd2 | 1469 | { |
8ad71bef | 1470 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1471 | struct iwl_txq *txq; |
5f178cd2 EG |
1472 | struct iwl_queue *q; |
1473 | int cnt; | |
1474 | unsigned long now = jiffies; | |
1c3fea82 EG |
1475 | u32 scd_sram_addr; |
1476 | u8 buf[16]; | |
5f178cd2 EG |
1477 | int ret = 0; |
1478 | ||
1479 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1480 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
fa1a91fd EG |
1481 | u8 wr_ptr; |
1482 | ||
9ba1947a | 1483 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1484 | continue; |
3cafdbe6 EG |
1485 | if (!test_bit(cnt, trans_pcie->queue_used)) |
1486 | continue; | |
1487 | if (!(BIT(cnt) & txq_bm)) | |
1488 | continue; | |
748fa67c EG |
1489 | |
1490 | IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); | |
8ad71bef | 1491 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 | 1492 | q = &txq->q; |
fa1a91fd EG |
1493 | wr_ptr = ACCESS_ONCE(q->write_ptr); |
1494 | ||
1495 | while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && | |
1496 | !time_after(jiffies, | |
1497 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { | |
1498 | u8 write_ptr = ACCESS_ONCE(q->write_ptr); | |
1499 | ||
1500 | if (WARN_ONCE(wr_ptr != write_ptr, | |
1501 | "WR pointer moved while flushing %d -> %d\n", | |
1502 | wr_ptr, write_ptr)) | |
1503 | return -ETIMEDOUT; | |
5f178cd2 | 1504 | msleep(1); |
fa1a91fd | 1505 | } |
5f178cd2 EG |
1506 | |
1507 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
1508 | IWL_ERR(trans, |
1509 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
1510 | ret = -ETIMEDOUT; |
1511 | break; | |
1512 | } | |
748fa67c | 1513 | IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); |
5f178cd2 | 1514 | } |
1c3fea82 EG |
1515 | |
1516 | if (!ret) | |
1517 | return 0; | |
1518 | ||
1519 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
1520 | txq->q.read_ptr, txq->q.write_ptr); | |
1521 | ||
1522 | scd_sram_addr = trans_pcie->scd_base_addr + | |
1523 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
1524 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
1525 | ||
1526 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
1527 | ||
1528 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
1529 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
1530 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
1531 | ||
1532 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1533 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
1534 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
1535 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
1536 | u32 tbl_dw = | |
1537 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
1538 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
1539 | ||
1540 | if (cnt & 0x1) | |
1541 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
1542 | else | |
1543 | tbl_dw = tbl_dw & 0x0000FFFF; | |
1544 | ||
1545 | IWL_ERR(trans, | |
1546 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
1547 | cnt, active ? "" : "in", fifo, tbl_dw, | |
83f32a4b JB |
1548 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & |
1549 | (TFD_QUEUE_SIZE_MAX - 1), | |
1c3fea82 EG |
1550 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); |
1551 | } | |
1552 | ||
5f178cd2 EG |
1553 | return ret; |
1554 | } | |
1555 | ||
e139dc4a LE |
1556 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
1557 | u32 mask, u32 value) | |
1558 | { | |
e56b04ef | 1559 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
1560 | unsigned long flags; |
1561 | ||
e56b04ef | 1562 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 1563 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 1564 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
1565 | } |
1566 | ||
7616f334 EP |
1567 | void iwl_trans_pcie_ref(struct iwl_trans *trans) |
1568 | { | |
1569 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1570 | unsigned long flags; | |
1571 | ||
1572 | if (iwlwifi_mod_params.d0i3_disable) | |
1573 | return; | |
1574 | ||
1575 | spin_lock_irqsave(&trans_pcie->ref_lock, flags); | |
1576 | IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); | |
1577 | trans_pcie->ref_count++; | |
1578 | spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); | |
1579 | } | |
1580 | ||
1581 | void iwl_trans_pcie_unref(struct iwl_trans *trans) | |
1582 | { | |
1583 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1584 | unsigned long flags; | |
1585 | ||
1586 | if (iwlwifi_mod_params.d0i3_disable) | |
1587 | return; | |
1588 | ||
1589 | spin_lock_irqsave(&trans_pcie->ref_lock, flags); | |
1590 | IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); | |
1591 | if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) { | |
1592 | spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); | |
1593 | return; | |
1594 | } | |
1595 | trans_pcie->ref_count--; | |
1596 | spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); | |
1597 | } | |
1598 | ||
ff620849 EG |
1599 | static const char *get_csr_string(int cmd) |
1600 | { | |
d9fb6465 | 1601 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1602 | switch (cmd) { |
1603 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1604 | IWL_CMD(CSR_INT_COALESCING); | |
1605 | IWL_CMD(CSR_INT); | |
1606 | IWL_CMD(CSR_INT_MASK); | |
1607 | IWL_CMD(CSR_FH_INT_STATUS); | |
1608 | IWL_CMD(CSR_GPIO_IN); | |
1609 | IWL_CMD(CSR_RESET); | |
1610 | IWL_CMD(CSR_GP_CNTRL); | |
1611 | IWL_CMD(CSR_HW_REV); | |
1612 | IWL_CMD(CSR_EEPROM_REG); | |
1613 | IWL_CMD(CSR_EEPROM_GP); | |
1614 | IWL_CMD(CSR_OTP_GP_REG); | |
1615 | IWL_CMD(CSR_GIO_REG); | |
1616 | IWL_CMD(CSR_GP_UCODE_REG); | |
1617 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1618 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1619 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1620 | IWL_CMD(CSR_LED_REG); | |
1621 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1622 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1623 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1624 | IWL_CMD(CSR_HW_REV_WA_REG); | |
a812cba9 | 1625 | IWL_CMD(CSR_MONITOR_STATUS_REG); |
ff620849 EG |
1626 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
1627 | default: | |
1628 | return "UNKNOWN"; | |
1629 | } | |
d9fb6465 | 1630 | #undef IWL_CMD |
ff620849 EG |
1631 | } |
1632 | ||
990aa6d7 | 1633 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
1634 | { |
1635 | int i; | |
1636 | static const u32 csr_tbl[] = { | |
1637 | CSR_HW_IF_CONFIG_REG, | |
1638 | CSR_INT_COALESCING, | |
1639 | CSR_INT, | |
1640 | CSR_INT_MASK, | |
1641 | CSR_FH_INT_STATUS, | |
1642 | CSR_GPIO_IN, | |
1643 | CSR_RESET, | |
1644 | CSR_GP_CNTRL, | |
1645 | CSR_HW_REV, | |
1646 | CSR_EEPROM_REG, | |
1647 | CSR_EEPROM_GP, | |
1648 | CSR_OTP_GP_REG, | |
1649 | CSR_GIO_REG, | |
1650 | CSR_GP_UCODE_REG, | |
1651 | CSR_GP_DRIVER_REG, | |
1652 | CSR_UCODE_DRV_GP1, | |
1653 | CSR_UCODE_DRV_GP2, | |
1654 | CSR_LED_REG, | |
1655 | CSR_DRAM_INT_TBL_REG, | |
1656 | CSR_GIO_CHICKEN_BITS, | |
1657 | CSR_ANA_PLL_CFG, | |
a812cba9 | 1658 | CSR_MONITOR_STATUS_REG, |
ff620849 EG |
1659 | CSR_HW_REV_WA_REG, |
1660 | CSR_DBG_HPET_MEM_REG | |
1661 | }; | |
1662 | IWL_ERR(trans, "CSR values:\n"); | |
1663 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1664 | "CSR_INT_PERIODIC_REG)\n"); | |
1665 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1666 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1667 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1668 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1669 | } |
1670 | } | |
1671 | ||
87e5666c EG |
1672 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1673 | /* create and remove of files */ | |
1674 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1675 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1676 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1677 | goto err; \ |
87e5666c EG |
1678 | } while (0) |
1679 | ||
1680 | /* file operation */ | |
87e5666c | 1681 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
1682 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1683 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1684 | .open = simple_open, \ |
87e5666c EG |
1685 | .llseek = generic_file_llseek, \ |
1686 | }; | |
1687 | ||
16db88ba | 1688 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
1689 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1690 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1691 | .open = simple_open, \ |
16db88ba EG |
1692 | .llseek = generic_file_llseek, \ |
1693 | }; | |
1694 | ||
87e5666c | 1695 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
1696 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1697 | .write = iwl_dbgfs_##name##_write, \ | |
1698 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1699 | .open = simple_open, \ |
87e5666c EG |
1700 | .llseek = generic_file_llseek, \ |
1701 | }; | |
1702 | ||
87e5666c | 1703 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1704 | char __user *user_buf, |
1705 | size_t count, loff_t *ppos) | |
8ad71bef | 1706 | { |
5a878bf6 | 1707 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1708 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1709 | struct iwl_txq *txq; |
87e5666c EG |
1710 | struct iwl_queue *q; |
1711 | char *buf; | |
1712 | int pos = 0; | |
1713 | int cnt; | |
1714 | int ret; | |
1745e440 WYG |
1715 | size_t bufsz; |
1716 | ||
035f7ff2 | 1717 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1718 | |
f9e75447 | 1719 | if (!trans_pcie->txq) |
87e5666c | 1720 | return -EAGAIN; |
f9e75447 | 1721 | |
87e5666c EG |
1722 | buf = kzalloc(bufsz, GFP_KERNEL); |
1723 | if (!buf) | |
1724 | return -ENOMEM; | |
1725 | ||
035f7ff2 | 1726 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1727 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1728 | q = &txq->q; |
1729 | pos += scnprintf(buf + pos, bufsz - pos, | |
f40faf62 | 1730 | "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n", |
87e5666c | 1731 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa | 1732 | !!test_bit(cnt, trans_pcie->queue_used), |
f40faf62 AL |
1733 | !!test_bit(cnt, trans_pcie->queue_stopped), |
1734 | txq->need_update, | |
1735 | (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); | |
87e5666c EG |
1736 | } |
1737 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1738 | kfree(buf); | |
1739 | return ret; | |
1740 | } | |
1741 | ||
1742 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1743 | char __user *user_buf, |
1744 | size_t count, loff_t *ppos) | |
1745 | { | |
5a878bf6 | 1746 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1747 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1748 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1749 | char buf[256]; |
1750 | int pos = 0; | |
1751 | const size_t bufsz = sizeof(buf); | |
1752 | ||
1753 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1754 | rxq->read); | |
1755 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1756 | rxq->write); | |
f40faf62 AL |
1757 | pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n", |
1758 | rxq->write_actual); | |
1759 | pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n", | |
1760 | rxq->need_update); | |
87e5666c EG |
1761 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", |
1762 | rxq->free_count); | |
1763 | if (rxq->rb_stts) { | |
1764 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1765 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1766 | } else { | |
1767 | pos += scnprintf(buf + pos, bufsz - pos, | |
1768 | "closed_rb_num: Not Allocated\n"); | |
1769 | } | |
1770 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1771 | } | |
1772 | ||
1f7b6172 EG |
1773 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1774 | char __user *user_buf, | |
20d3b647 JB |
1775 | size_t count, loff_t *ppos) |
1776 | { | |
1f7b6172 | 1777 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1778 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1779 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1780 | ||
1781 | int pos = 0; | |
1782 | char *buf; | |
1783 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1784 | ssize_t ret; | |
1785 | ||
1786 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1787 | if (!buf) |
1f7b6172 | 1788 | return -ENOMEM; |
1f7b6172 EG |
1789 | |
1790 | pos += scnprintf(buf + pos, bufsz - pos, | |
1791 | "Interrupt Statistics Report:\n"); | |
1792 | ||
1793 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1794 | isr_stats->hw); | |
1795 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1796 | isr_stats->sw); | |
1797 | if (isr_stats->sw || isr_stats->hw) { | |
1798 | pos += scnprintf(buf + pos, bufsz - pos, | |
1799 | "\tLast Restarting Code: 0x%X\n", | |
1800 | isr_stats->err_code); | |
1801 | } | |
1802 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1803 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1804 | isr_stats->sch); | |
1805 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1806 | isr_stats->alive); | |
1807 | #endif | |
1808 | pos += scnprintf(buf + pos, bufsz - pos, | |
1809 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1810 | ||
1811 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1812 | isr_stats->ctkill); | |
1813 | ||
1814 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1815 | isr_stats->wakeup); | |
1816 | ||
1817 | pos += scnprintf(buf + pos, bufsz - pos, | |
1818 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1819 | ||
1820 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1821 | isr_stats->tx); | |
1822 | ||
1823 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1824 | isr_stats->unhandled); | |
1825 | ||
1826 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1827 | kfree(buf); | |
1828 | return ret; | |
1829 | } | |
1830 | ||
1831 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1832 | const char __user *user_buf, | |
1833 | size_t count, loff_t *ppos) | |
1834 | { | |
1835 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1836 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1837 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1838 | ||
1839 | char buf[8]; | |
1840 | int buf_size; | |
1841 | u32 reset_flag; | |
1842 | ||
1843 | memset(buf, 0, sizeof(buf)); | |
1844 | buf_size = min(count, sizeof(buf) - 1); | |
1845 | if (copy_from_user(buf, user_buf, buf_size)) | |
1846 | return -EFAULT; | |
1847 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1848 | return -EFAULT; | |
1849 | if (reset_flag == 0) | |
1850 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1851 | ||
1852 | return count; | |
1853 | } | |
1854 | ||
16db88ba | 1855 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1856 | const char __user *user_buf, |
1857 | size_t count, loff_t *ppos) | |
16db88ba EG |
1858 | { |
1859 | struct iwl_trans *trans = file->private_data; | |
1860 | char buf[8]; | |
1861 | int buf_size; | |
1862 | int csr; | |
1863 | ||
1864 | memset(buf, 0, sizeof(buf)); | |
1865 | buf_size = min(count, sizeof(buf) - 1); | |
1866 | if (copy_from_user(buf, user_buf, buf_size)) | |
1867 | return -EFAULT; | |
1868 | if (sscanf(buf, "%d", &csr) != 1) | |
1869 | return -EFAULT; | |
1870 | ||
990aa6d7 | 1871 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1872 | |
1873 | return count; | |
1874 | } | |
1875 | ||
16db88ba | 1876 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1877 | char __user *user_buf, |
1878 | size_t count, loff_t *ppos) | |
16db88ba EG |
1879 | { |
1880 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1881 | char *buf = NULL; |
56c2477f | 1882 | ssize_t ret; |
16db88ba | 1883 | |
56c2477f JB |
1884 | ret = iwl_dump_fh(trans, &buf); |
1885 | if (ret < 0) | |
1886 | return ret; | |
1887 | if (!buf) | |
1888 | return -EINVAL; | |
1889 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); | |
1890 | kfree(buf); | |
16db88ba EG |
1891 | return ret; |
1892 | } | |
1893 | ||
1f7b6172 | 1894 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1895 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1896 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1897 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1898 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
1899 | |
1900 | /* | |
1901 | * Create the debugfs files and directories | |
1902 | * | |
1903 | */ | |
1904 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1905 | struct dentry *dir) |
87e5666c | 1906 | { |
87e5666c EG |
1907 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1908 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1909 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1910 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1911 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c | 1912 | return 0; |
9da987ac MV |
1913 | |
1914 | err: | |
1915 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1916 | return -ENOMEM; | |
87e5666c | 1917 | } |
aadede6e JB |
1918 | #else |
1919 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1920 | struct dentry *dir) | |
1921 | { | |
1922 | return 0; | |
1923 | } | |
1924 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
4d075007 JB |
1925 | |
1926 | static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) | |
1927 | { | |
1928 | u32 cmdlen = 0; | |
1929 | int i; | |
1930 | ||
1931 | for (i = 0; i < IWL_NUM_OF_TBS; i++) | |
1932 | cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); | |
1933 | ||
1934 | return cmdlen; | |
1935 | } | |
1936 | ||
67c65f2c EG |
1937 | static const struct { |
1938 | u32 start, end; | |
1939 | } iwl_prph_dump_addr[] = { | |
1940 | { .start = 0x00a00000, .end = 0x00a00000 }, | |
1941 | { .start = 0x00a0000c, .end = 0x00a00024 }, | |
1942 | { .start = 0x00a0002c, .end = 0x00a0003c }, | |
1943 | { .start = 0x00a00410, .end = 0x00a00418 }, | |
1944 | { .start = 0x00a00420, .end = 0x00a00420 }, | |
1945 | { .start = 0x00a00428, .end = 0x00a00428 }, | |
1946 | { .start = 0x00a00430, .end = 0x00a0043c }, | |
1947 | { .start = 0x00a00444, .end = 0x00a00444 }, | |
1948 | { .start = 0x00a004c0, .end = 0x00a004cc }, | |
1949 | { .start = 0x00a004d8, .end = 0x00a004d8 }, | |
1950 | { .start = 0x00a004e0, .end = 0x00a004f0 }, | |
1951 | { .start = 0x00a00840, .end = 0x00a00840 }, | |
1952 | { .start = 0x00a00850, .end = 0x00a00858 }, | |
1953 | { .start = 0x00a01004, .end = 0x00a01008 }, | |
1954 | { .start = 0x00a01010, .end = 0x00a01010 }, | |
1955 | { .start = 0x00a01018, .end = 0x00a01018 }, | |
1956 | { .start = 0x00a01024, .end = 0x00a01024 }, | |
1957 | { .start = 0x00a0102c, .end = 0x00a01034 }, | |
1958 | { .start = 0x00a0103c, .end = 0x00a01040 }, | |
1959 | { .start = 0x00a01048, .end = 0x00a01094 }, | |
1960 | { .start = 0x00a01c00, .end = 0x00a01c20 }, | |
1961 | { .start = 0x00a01c58, .end = 0x00a01c58 }, | |
1962 | { .start = 0x00a01c7c, .end = 0x00a01c7c }, | |
1963 | { .start = 0x00a01c28, .end = 0x00a01c54 }, | |
1964 | { .start = 0x00a01c5c, .end = 0x00a01c5c }, | |
1965 | { .start = 0x00a01c84, .end = 0x00a01c84 }, | |
1966 | { .start = 0x00a01ce0, .end = 0x00a01d0c }, | |
1967 | { .start = 0x00a01d18, .end = 0x00a01d20 }, | |
1968 | { .start = 0x00a01d2c, .end = 0x00a01d30 }, | |
1969 | { .start = 0x00a01d40, .end = 0x00a01d5c }, | |
1970 | { .start = 0x00a01d80, .end = 0x00a01d80 }, | |
1971 | { .start = 0x00a01d98, .end = 0x00a01d98 }, | |
1972 | { .start = 0x00a01dc0, .end = 0x00a01dfc }, | |
1973 | { .start = 0x00a01e00, .end = 0x00a01e2c }, | |
1974 | { .start = 0x00a01e40, .end = 0x00a01e60 }, | |
1975 | { .start = 0x00a01e84, .end = 0x00a01e90 }, | |
1976 | { .start = 0x00a01e9c, .end = 0x00a01ec4 }, | |
1977 | { .start = 0x00a01ed0, .end = 0x00a01ed0 }, | |
1978 | { .start = 0x00a01f00, .end = 0x00a01f14 }, | |
1979 | { .start = 0x00a01f44, .end = 0x00a01f58 }, | |
1980 | { .start = 0x00a01f80, .end = 0x00a01fa8 }, | |
1981 | { .start = 0x00a01fb0, .end = 0x00a01fbc }, | |
1982 | { .start = 0x00a01ff8, .end = 0x00a01ffc }, | |
1983 | { .start = 0x00a02000, .end = 0x00a02048 }, | |
1984 | { .start = 0x00a02068, .end = 0x00a020f0 }, | |
1985 | { .start = 0x00a02100, .end = 0x00a02118 }, | |
1986 | { .start = 0x00a02140, .end = 0x00a0214c }, | |
1987 | { .start = 0x00a02168, .end = 0x00a0218c }, | |
1988 | { .start = 0x00a021c0, .end = 0x00a021c0 }, | |
1989 | { .start = 0x00a02400, .end = 0x00a02410 }, | |
1990 | { .start = 0x00a02418, .end = 0x00a02420 }, | |
1991 | { .start = 0x00a02428, .end = 0x00a0242c }, | |
1992 | { .start = 0x00a02434, .end = 0x00a02434 }, | |
1993 | { .start = 0x00a02440, .end = 0x00a02460 }, | |
1994 | { .start = 0x00a02468, .end = 0x00a024b0 }, | |
1995 | { .start = 0x00a024c8, .end = 0x00a024cc }, | |
1996 | { .start = 0x00a02500, .end = 0x00a02504 }, | |
1997 | { .start = 0x00a0250c, .end = 0x00a02510 }, | |
1998 | { .start = 0x00a02540, .end = 0x00a02554 }, | |
1999 | { .start = 0x00a02580, .end = 0x00a025f4 }, | |
2000 | { .start = 0x00a02600, .end = 0x00a0260c }, | |
2001 | { .start = 0x00a02648, .end = 0x00a02650 }, | |
2002 | { .start = 0x00a02680, .end = 0x00a02680 }, | |
2003 | { .start = 0x00a026c0, .end = 0x00a026d0 }, | |
2004 | { .start = 0x00a02700, .end = 0x00a0270c }, | |
2005 | { .start = 0x00a02804, .end = 0x00a02804 }, | |
2006 | { .start = 0x00a02818, .end = 0x00a0281c }, | |
2007 | { .start = 0x00a02c00, .end = 0x00a02db4 }, | |
2008 | { .start = 0x00a02df4, .end = 0x00a02fb0 }, | |
2009 | { .start = 0x00a03000, .end = 0x00a03014 }, | |
2010 | { .start = 0x00a0301c, .end = 0x00a0302c }, | |
2011 | { .start = 0x00a03034, .end = 0x00a03038 }, | |
2012 | { .start = 0x00a03040, .end = 0x00a03048 }, | |
2013 | { .start = 0x00a03060, .end = 0x00a03068 }, | |
2014 | { .start = 0x00a03070, .end = 0x00a03074 }, | |
2015 | { .start = 0x00a0307c, .end = 0x00a0307c }, | |
2016 | { .start = 0x00a03080, .end = 0x00a03084 }, | |
2017 | { .start = 0x00a0308c, .end = 0x00a03090 }, | |
2018 | { .start = 0x00a03098, .end = 0x00a03098 }, | |
2019 | { .start = 0x00a030a0, .end = 0x00a030a0 }, | |
2020 | { .start = 0x00a030a8, .end = 0x00a030b4 }, | |
2021 | { .start = 0x00a030bc, .end = 0x00a030bc }, | |
2022 | { .start = 0x00a030c0, .end = 0x00a0312c }, | |
2023 | { .start = 0x00a03c00, .end = 0x00a03c5c }, | |
2024 | { .start = 0x00a04400, .end = 0x00a04454 }, | |
2025 | { .start = 0x00a04460, .end = 0x00a04474 }, | |
2026 | { .start = 0x00a044c0, .end = 0x00a044ec }, | |
2027 | { .start = 0x00a04500, .end = 0x00a04504 }, | |
2028 | { .start = 0x00a04510, .end = 0x00a04538 }, | |
2029 | { .start = 0x00a04540, .end = 0x00a04548 }, | |
2030 | { .start = 0x00a04560, .end = 0x00a0457c }, | |
2031 | { .start = 0x00a04590, .end = 0x00a04598 }, | |
2032 | { .start = 0x00a045c0, .end = 0x00a045f4 }, | |
2033 | }; | |
2034 | ||
2035 | static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans, | |
2036 | struct iwl_fw_error_dump_data **data) | |
2037 | { | |
2038 | struct iwl_fw_error_dump_prph *prph; | |
2039 | unsigned long flags; | |
2040 | u32 prph_len = 0, i; | |
2041 | ||
2042 | if (!iwl_trans_grab_nic_access(trans, false, &flags)) | |
2043 | return 0; | |
2044 | ||
2045 | for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) { | |
2046 | /* The range includes both boundaries */ | |
2047 | int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - | |
2048 | iwl_prph_dump_addr[i].start + 4; | |
2049 | int reg; | |
2050 | __le32 *val; | |
2051 | ||
87dd634a | 2052 | prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk; |
67c65f2c EG |
2053 | |
2054 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); | |
2055 | (*data)->len = cpu_to_le32(sizeof(*prph) + | |
2056 | num_bytes_in_chunk); | |
2057 | prph = (void *)(*data)->data; | |
2058 | prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); | |
2059 | val = (void *)prph->data; | |
2060 | ||
2061 | for (reg = iwl_prph_dump_addr[i].start; | |
2062 | reg <= iwl_prph_dump_addr[i].end; | |
2063 | reg += 4) | |
2064 | *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, | |
2065 | reg)); | |
2066 | *data = iwl_fw_error_next_data(*data); | |
2067 | } | |
2068 | ||
2069 | iwl_trans_release_nic_access(trans, &flags); | |
2070 | ||
2071 | return prph_len; | |
2072 | } | |
2073 | ||
473ad712 EG |
2074 | #define IWL_CSR_TO_DUMP (0x250) |
2075 | ||
2076 | static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, | |
2077 | struct iwl_fw_error_dump_data **data) | |
2078 | { | |
2079 | u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; | |
2080 | __le32 *val; | |
2081 | int i; | |
2082 | ||
2083 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); | |
2084 | (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); | |
2085 | val = (void *)(*data)->data; | |
2086 | ||
2087 | for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) | |
2088 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2089 | ||
2090 | *data = iwl_fw_error_next_data(*data); | |
2091 | ||
2092 | return csr_len; | |
2093 | } | |
2094 | ||
06d51e0d LK |
2095 | static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, |
2096 | struct iwl_fw_error_dump_data **data) | |
2097 | { | |
2098 | u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; | |
2099 | unsigned long flags; | |
2100 | __le32 *val; | |
2101 | int i; | |
2102 | ||
2103 | if (!iwl_trans_grab_nic_access(trans, false, &flags)) | |
2104 | return 0; | |
2105 | ||
2106 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); | |
2107 | (*data)->len = cpu_to_le32(fh_regs_len); | |
2108 | val = (void *)(*data)->data; | |
2109 | ||
2110 | for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) | |
2111 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2112 | ||
2113 | iwl_trans_release_nic_access(trans, &flags); | |
2114 | ||
2115 | *data = iwl_fw_error_next_data(*data); | |
2116 | ||
2117 | return sizeof(**data) + fh_regs_len; | |
2118 | } | |
2119 | ||
48eb7b34 EG |
2120 | static |
2121 | struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans) | |
4d075007 JB |
2122 | { |
2123 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2124 | struct iwl_fw_error_dump_data *data; | |
2125 | struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; | |
2126 | struct iwl_fw_error_dump_txcmd *txcmd; | |
48eb7b34 | 2127 | struct iwl_trans_dump_data *dump_data; |
4d075007 | 2128 | u32 len; |
99684ae3 | 2129 | u32 monitor_len; |
4d075007 JB |
2130 | int i, ptr; |
2131 | ||
473ad712 EG |
2132 | /* transport dump header */ |
2133 | len = sizeof(*dump_data); | |
2134 | ||
2135 | /* host commands */ | |
2136 | len += sizeof(*data) + | |
c2d20201 EG |
2137 | cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); |
2138 | ||
473ad712 EG |
2139 | /* CSR registers */ |
2140 | len += sizeof(*data) + IWL_CSR_TO_DUMP; | |
2141 | ||
2142 | /* PRPH registers */ | |
67c65f2c EG |
2143 | for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) { |
2144 | /* The range includes both boundaries */ | |
2145 | int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - | |
2146 | iwl_prph_dump_addr[i].start + 4; | |
2147 | ||
2148 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) + | |
2149 | num_bytes_in_chunk; | |
2150 | } | |
2151 | ||
06d51e0d LK |
2152 | /* FH registers */ |
2153 | len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); | |
2154 | ||
473ad712 | 2155 | /* FW monitor */ |
99684ae3 | 2156 | if (trans_pcie->fw_mon_page) { |
c544e9c4 | 2157 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + |
99684ae3 LK |
2158 | trans_pcie->fw_mon_size; |
2159 | monitor_len = trans_pcie->fw_mon_size; | |
2160 | } else if (trans->dbg_dest_tlv) { | |
2161 | u32 base, end; | |
2162 | ||
2163 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
2164 | end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); | |
2165 | ||
2166 | base = iwl_read_prph(trans, base) << | |
2167 | trans->dbg_dest_tlv->base_shift; | |
2168 | end = iwl_read_prph(trans, end) << | |
2169 | trans->dbg_dest_tlv->end_shift; | |
2170 | ||
2171 | /* Make "end" point to the actual end */ | |
2172 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) | |
2173 | end += (1 << trans->dbg_dest_tlv->end_shift); | |
2174 | monitor_len = end - base; | |
2175 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + | |
2176 | monitor_len; | |
2177 | } else { | |
2178 | monitor_len = 0; | |
2179 | } | |
c2d20201 | 2180 | |
48eb7b34 EG |
2181 | dump_data = vzalloc(len); |
2182 | if (!dump_data) | |
2183 | return NULL; | |
4d075007 JB |
2184 | |
2185 | len = 0; | |
48eb7b34 | 2186 | data = (void *)dump_data->data; |
4d075007 JB |
2187 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); |
2188 | txcmd = (void *)data->data; | |
2189 | spin_lock_bh(&cmdq->lock); | |
2190 | ptr = cmdq->q.write_ptr; | |
2191 | for (i = 0; i < cmdq->q.n_window; i++) { | |
2192 | u8 idx = get_cmd_index(&cmdq->q, ptr); | |
2193 | u32 caplen, cmdlen; | |
2194 | ||
2195 | cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); | |
2196 | caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); | |
2197 | ||
2198 | if (cmdlen) { | |
2199 | len += sizeof(*txcmd) + caplen; | |
2200 | txcmd->cmdlen = cpu_to_le32(cmdlen); | |
2201 | txcmd->caplen = cpu_to_le32(caplen); | |
2202 | memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); | |
2203 | txcmd = (void *)((u8 *)txcmd->data + caplen); | |
2204 | } | |
2205 | ||
2206 | ptr = iwl_queue_dec_wrap(ptr); | |
2207 | } | |
2208 | spin_unlock_bh(&cmdq->lock); | |
2209 | ||
2210 | data->len = cpu_to_le32(len); | |
c2d20201 | 2211 | len += sizeof(*data); |
67c65f2c EG |
2212 | data = iwl_fw_error_next_data(data); |
2213 | ||
2214 | len += iwl_trans_pcie_dump_prph(trans, &data); | |
473ad712 | 2215 | len += iwl_trans_pcie_dump_csr(trans, &data); |
06d51e0d | 2216 | len += iwl_trans_pcie_fh_regs_dump(trans, &data); |
67c65f2c | 2217 | /* data is already pointing to the next section */ |
c2d20201 | 2218 | |
99684ae3 LK |
2219 | if ((trans_pcie->fw_mon_page && |
2220 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || | |
2221 | trans->dbg_dest_tlv) { | |
c544e9c4 | 2222 | struct iwl_fw_error_dump_fw_mon *fw_mon_data; |
99684ae3 LK |
2223 | u32 base, write_ptr, wrap_cnt; |
2224 | ||
2225 | /* If there was a dest TLV - use the values from there */ | |
2226 | if (trans->dbg_dest_tlv) { | |
2227 | write_ptr = | |
2228 | le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); | |
2229 | wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); | |
2230 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
2231 | } else { | |
2232 | base = MON_BUFF_BASE_ADDR; | |
2233 | write_ptr = MON_BUFF_WRPTR; | |
2234 | wrap_cnt = MON_BUFF_CYCLE_CNT; | |
2235 | } | |
c2d20201 | 2236 | |
c2d20201 | 2237 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); |
c2d20201 EG |
2238 | fw_mon_data = (void *)data->data; |
2239 | fw_mon_data->fw_mon_wr_ptr = | |
99684ae3 | 2240 | cpu_to_le32(iwl_read_prph(trans, write_ptr)); |
c2d20201 | 2241 | fw_mon_data->fw_mon_cycle_cnt = |
99684ae3 | 2242 | cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); |
c2d20201 | 2243 | fw_mon_data->fw_mon_base_ptr = |
99684ae3 LK |
2244 | cpu_to_le32(iwl_read_prph(trans, base)); |
2245 | ||
2246 | len += sizeof(*data) + sizeof(*fw_mon_data); | |
2247 | if (trans_pcie->fw_mon_page) { | |
2248 | data->len = cpu_to_le32(trans_pcie->fw_mon_size + | |
2249 | sizeof(*fw_mon_data)); | |
2250 | ||
2251 | /* | |
2252 | * The firmware is now asserted, it won't write anything | |
2253 | * to the buffer. CPU can take ownership to fetch the | |
2254 | * data. The buffer will be handed back to the device | |
2255 | * before the firmware will be restarted. | |
2256 | */ | |
2257 | dma_sync_single_for_cpu(trans->dev, | |
2258 | trans_pcie->fw_mon_phys, | |
2259 | trans_pcie->fw_mon_size, | |
2260 | DMA_FROM_DEVICE); | |
2261 | memcpy(fw_mon_data->data, | |
2262 | page_address(trans_pcie->fw_mon_page), | |
2263 | trans_pcie->fw_mon_size); | |
2264 | ||
2265 | len += trans_pcie->fw_mon_size; | |
2266 | } else { | |
2267 | /* If we are here then the buffer is internal */ | |
2268 | ||
2269 | /* | |
2270 | * Update pointers to reflect actual values after | |
2271 | * shifting | |
2272 | */ | |
2273 | base = iwl_read_prph(trans, base) << | |
2274 | trans->dbg_dest_tlv->base_shift; | |
2275 | iwl_trans_read_mem(trans, base, fw_mon_data->data, | |
2276 | monitor_len / sizeof(u32)); | |
2277 | data->len = cpu_to_le32(sizeof(*fw_mon_data) + | |
2278 | monitor_len); | |
2279 | len += monitor_len; | |
2280 | } | |
c2d20201 EG |
2281 | } |
2282 | ||
48eb7b34 EG |
2283 | dump_data->len = len; |
2284 | ||
2285 | return dump_data; | |
4d075007 | 2286 | } |
87e5666c | 2287 | |
d1ff5253 | 2288 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2289 | .start_hw = iwl_trans_pcie_start_hw, |
a4082843 | 2290 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, |
ed6a3803 | 2291 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2292 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2293 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2294 | |
ddaf5a5b JB |
2295 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
2296 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 2297 | |
f02831be | 2298 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 2299 | |
e6bb4c9c | 2300 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2301 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2302 | |
d0624be6 | 2303 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 2304 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 2305 | |
87e5666c | 2306 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 2307 | |
990aa6d7 | 2308 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 2309 | |
03905495 EG |
2310 | .write8 = iwl_trans_pcie_write8, |
2311 | .write32 = iwl_trans_pcie_write32, | |
2312 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
2313 | .read_prph = iwl_trans_pcie_read_prph, |
2314 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
2315 | .read_mem = iwl_trans_pcie_read_mem, |
2316 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 2317 | .configure = iwl_trans_pcie_configure, |
47107e84 | 2318 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 2319 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
2320 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
2321 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
4d075007 | 2322 | |
7616f334 EP |
2323 | .ref = iwl_trans_pcie_ref, |
2324 | .unref = iwl_trans_pcie_unref, | |
2325 | ||
4d075007 | 2326 | .dump_data = iwl_trans_pcie_dump_data, |
e6bb4c9c | 2327 | }; |
a42a1844 | 2328 | |
87ce05a2 | 2329 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
2330 | const struct pci_device_id *ent, |
2331 | const struct iwl_cfg *cfg) | |
a42a1844 | 2332 | { |
a42a1844 EG |
2333 | struct iwl_trans_pcie *trans_pcie; |
2334 | struct iwl_trans *trans; | |
2335 | u16 pci_cmd; | |
2336 | int err; | |
2337 | ||
2338 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 2339 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
6965a354 LC |
2340 | if (!trans) { |
2341 | err = -ENOMEM; | |
2342 | goto out; | |
2343 | } | |
a42a1844 EG |
2344 | |
2345 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2346 | ||
2347 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 2348 | trans->cfg = cfg; |
2bfb5092 | 2349 | trans_lockdep_init(trans); |
a42a1844 | 2350 | trans_pcie->trans = trans; |
7b11488f | 2351 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 2352 | spin_lock_init(&trans_pcie->reg_lock); |
dad33ecf | 2353 | spin_lock_init(&trans_pcie->ref_lock); |
13df1aab | 2354 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 | 2355 | |
d819c6cf JB |
2356 | err = pci_enable_device(pdev); |
2357 | if (err) | |
2358 | goto out_no_pci; | |
2359 | ||
f2532b04 EG |
2360 | if (!cfg->base_params->pcie_l1_allowed) { |
2361 | /* | |
2362 | * W/A - seems to solve weird behavior. We need to remove this | |
2363 | * if we don't want to stay in L1 all the time. This wastes a | |
2364 | * lot of power. | |
2365 | */ | |
2366 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
2367 | PCIE_LINK_STATE_L1 | | |
2368 | PCIE_LINK_STATE_CLKPM); | |
2369 | } | |
a42a1844 | 2370 | |
a42a1844 EG |
2371 | pci_set_master(pdev); |
2372 | ||
2373 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2374 | if (!err) | |
2375 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2376 | if (err) { | |
2377 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2378 | if (!err) | |
2379 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 2380 | DMA_BIT_MASK(32)); |
a42a1844 EG |
2381 | /* both attempts failed: */ |
2382 | if (err) { | |
6a4b09f8 | 2383 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
2384 | goto out_pci_disable_device; |
2385 | } | |
2386 | } | |
2387 | ||
2388 | err = pci_request_regions(pdev, DRV_NAME); | |
2389 | if (err) { | |
6a4b09f8 | 2390 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
2391 | goto out_pci_disable_device; |
2392 | } | |
2393 | ||
05f5b97e | 2394 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 2395 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 2396 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
2397 | err = -ENODEV; |
2398 | goto out_pci_release_regions; | |
2399 | } | |
2400 | ||
a42a1844 EG |
2401 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
2402 | * PCI Tx retries from interfering with C3 CPU state */ | |
2403 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2404 | ||
83f7a85f EG |
2405 | trans->dev = &pdev->dev; |
2406 | trans_pcie->pci_dev = pdev; | |
2407 | iwl_disable_interrupts(trans); | |
2408 | ||
a42a1844 | 2409 | err = pci_enable_msi(pdev); |
9f904b38 | 2410 | if (err) { |
6a4b09f8 | 2411 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
2412 | /* enable rfkill interrupt: hw bug w/a */ |
2413 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2414 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2415 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2416 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2417 | } | |
2418 | } | |
a42a1844 | 2419 | |
08079a49 | 2420 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
b513ee7f LK |
2421 | /* |
2422 | * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have | |
2423 | * changed, and now the revision step also includes bit 0-1 (no more | |
2424 | * "dash" value). To keep hw_rev backwards compatible - we'll store it | |
2425 | * in the old format. | |
2426 | */ | |
2427 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) | |
2428 | trans->hw_rev = (trans->hw_rev & 0xfff0) | | |
1fc0e221 | 2429 | (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); |
b513ee7f | 2430 | |
99673ee5 | 2431 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2432 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2433 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 2434 | |
69a10b29 | 2435 | /* Initialize the wait queue for commands */ |
f946b529 | 2436 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 2437 | |
3ec45882 JB |
2438 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
2439 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
2440 | |
2441 | trans->dev_cmd_headroom = 0; | |
2442 | trans->dev_cmd_pool = | |
3ec45882 | 2443 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
2444 | sizeof(struct iwl_device_cmd) |
2445 | + trans->dev_cmd_headroom, | |
2446 | sizeof(void *), | |
2447 | SLAB_HWCACHE_ALIGN, | |
2448 | NULL); | |
2449 | ||
6965a354 LC |
2450 | if (!trans->dev_cmd_pool) { |
2451 | err = -ENOMEM; | |
59c647b6 | 2452 | goto out_pci_disable_msi; |
6965a354 | 2453 | } |
59c647b6 | 2454 | |
a8b691e6 JB |
2455 | if (iwl_pcie_alloc_ict(trans)) |
2456 | goto out_free_cmd_pool; | |
2457 | ||
85bf9da1 | 2458 | err = request_threaded_irq(pdev->irq, iwl_pcie_isr, |
6965a354 LC |
2459 | iwl_pcie_irq_handler, |
2460 | IRQF_SHARED, DRV_NAME, trans); | |
2461 | if (err) { | |
a8b691e6 JB |
2462 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
2463 | goto out_free_ict; | |
2464 | } | |
2465 | ||
83f7a85f | 2466 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
6735943f | 2467 | trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND; |
83f7a85f | 2468 | |
a42a1844 EG |
2469 | return trans; |
2470 | ||
a8b691e6 JB |
2471 | out_free_ict: |
2472 | iwl_pcie_free_ict(trans); | |
2473 | out_free_cmd_pool: | |
2474 | kmem_cache_destroy(trans->dev_cmd_pool); | |
59c647b6 EG |
2475 | out_pci_disable_msi: |
2476 | pci_disable_msi(pdev); | |
a42a1844 EG |
2477 | out_pci_release_regions: |
2478 | pci_release_regions(pdev); | |
2479 | out_pci_disable_device: | |
2480 | pci_disable_device(pdev); | |
2481 | out_no_pci: | |
2482 | kfree(trans); | |
6965a354 LC |
2483 | out: |
2484 | return ERR_PTR(err); | |
a42a1844 | 2485 | } |