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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
c85eb619 EG |
26 | * |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
51368bf7 | 33 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
0439bb62 | 77 | |
ddaf5a5b | 78 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 79 | { |
ddaf5a5b JB |
80 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
81 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
82 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
83 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
84 | else | |
85 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
86 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
87 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
88 | } |
89 | ||
af634bee EG |
90 | /* PCI registers */ |
91 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 92 | |
7afe3705 | 93 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 94 | { |
20d3b647 | 95 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 96 | u16 lctl; |
af634bee | 97 | |
af634bee EG |
98 | /* |
99 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
100 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
101 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
102 | * costs negligible amount of power savings. | |
103 | * If not (unlikely), enable L0S, so there is at least some | |
104 | * power savings, even without L1. | |
105 | */ | |
7afe3705 | 106 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
438a0f0a | 107 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { |
af634bee EG |
108 | /* L1-ASPM enabled; disable(!) L0S */ |
109 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 110 | dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); |
af634bee EG |
111 | } else { |
112 | /* L1-ASPM disabled; enable(!) L0S */ | |
113 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 114 | dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); |
af634bee | 115 | } |
438a0f0a | 116 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
af634bee EG |
117 | } |
118 | ||
a6c684ee EG |
119 | /* |
120 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 121 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
122 | * NOTE: This does not load uCode nor start the embedded processor |
123 | */ | |
7afe3705 | 124 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee EG |
125 | { |
126 | int ret = 0; | |
127 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
128 | ||
129 | /* | |
130 | * Use "set_bit" below rather than "write", to preserve any hardware | |
131 | * bits already set by default after reset. | |
132 | */ | |
133 | ||
134 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
135 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 136 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
137 | |
138 | /* | |
139 | * Disable L0s without affecting L1; | |
140 | * don't wait for ICH L0s (ICH bug W/A) | |
141 | */ | |
142 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 143 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
144 | |
145 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
146 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
147 | ||
148 | /* | |
149 | * Enable HAP INTA (interrupt from management bus) to | |
150 | * wake device's PCI Express link L1a -> L0s | |
151 | */ | |
152 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 153 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 154 | |
7afe3705 | 155 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
156 | |
157 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 158 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 159 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 160 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
161 | |
162 | /* | |
163 | * Set "initialization complete" bit to move adapter from | |
164 | * D0U* --> D0A* (powered-up active) state. | |
165 | */ | |
166 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
167 | ||
168 | /* | |
169 | * Wait for clock stabilization; once stabilized, access to | |
170 | * device-internal resources is supported, e.g. iwl_write_prph() | |
171 | * and accesses to uCode SRAM. | |
172 | */ | |
173 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
174 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
175 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
176 | if (ret < 0) { |
177 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
178 | goto out; | |
179 | } | |
180 | ||
181 | /* | |
182 | * Enable DMA clock and wait for it to stabilize. | |
183 | * | |
184 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
185 | * do not disable clocks. This preserves any hardware bits already | |
186 | * set by default in "CLK_CTRL_REG" after reset. | |
187 | */ | |
188 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
189 | udelay(20); | |
190 | ||
191 | /* Disable L1-Active */ | |
192 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
193 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
194 | ||
889b1696 EG |
195 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ |
196 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL); | |
197 | ||
eb7ff77e | 198 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee EG |
199 | |
200 | out: | |
201 | return ret; | |
202 | } | |
203 | ||
7afe3705 | 204 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
205 | { |
206 | int ret = 0; | |
207 | ||
208 | /* stop device's busmaster DMA activity */ | |
209 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
210 | ||
211 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
212 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
213 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
214 | if (ret) |
215 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
216 | ||
217 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
218 | ||
219 | return ret; | |
220 | } | |
221 | ||
7afe3705 | 222 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) |
cc56feb2 EG |
223 | { |
224 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
225 | ||
eb7ff77e | 226 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
227 | |
228 | /* Stop device's DMA activity */ | |
7afe3705 | 229 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 EG |
230 | |
231 | /* Reset the entire device */ | |
232 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
233 | ||
234 | udelay(10); | |
235 | ||
236 | /* | |
237 | * Clear "initialization complete" bit to move adapter from | |
238 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
239 | */ | |
240 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
241 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
242 | } | |
243 | ||
7afe3705 | 244 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 245 | { |
7b11488f | 246 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
247 | |
248 | /* nic_init */ | |
7b70bd63 | 249 | spin_lock(&trans_pcie->irq_lock); |
7afe3705 | 250 | iwl_pcie_apm_init(trans); |
392f8b78 | 251 | |
7b70bd63 | 252 | spin_unlock(&trans_pcie->irq_lock); |
392f8b78 | 253 | |
ddaf5a5b | 254 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 255 | |
ecdb975c | 256 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
257 | |
258 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 259 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
260 | |
261 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 262 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
263 | return -ENOMEM; |
264 | ||
035f7ff2 | 265 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 266 | /* enable shadow regs in HW */ |
20d3b647 | 267 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 268 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
269 | } |
270 | ||
392f8b78 EG |
271 | return 0; |
272 | } | |
273 | ||
274 | #define HW_READY_TIMEOUT (50) | |
275 | ||
276 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 277 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
278 | { |
279 | int ret; | |
280 | ||
1042db2a | 281 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 282 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
283 | |
284 | /* See if we got it */ | |
1042db2a | 285 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
286 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
287 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
288 | HW_READY_TIMEOUT); | |
392f8b78 | 289 | |
6d8f6eeb | 290 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
291 | return ret; |
292 | } | |
293 | ||
294 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 295 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
296 | { |
297 | int ret; | |
289e5501 | 298 | int t = 0; |
392f8b78 | 299 | |
6d8f6eeb | 300 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 301 | |
7afe3705 | 302 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 303 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
304 | if (ret >= 0) |
305 | return 0; | |
306 | ||
307 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 308 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 309 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 310 | |
289e5501 | 311 | do { |
7afe3705 | 312 | ret = iwl_pcie_set_hw_ready(trans); |
289e5501 EG |
313 | if (ret >= 0) |
314 | return 0; | |
392f8b78 | 315 | |
289e5501 EG |
316 | usleep_range(200, 1000); |
317 | t += 200; | |
318 | } while (t < 150000); | |
392f8b78 | 319 | |
392f8b78 EG |
320 | return ret; |
321 | } | |
322 | ||
cf614297 EG |
323 | /* |
324 | * ucode | |
325 | */ | |
7afe3705 | 326 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 327 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 328 | { |
13df1aab | 329 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
330 | int ret; |
331 | ||
13df1aab | 332 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
333 | |
334 | iwl_write_direct32(trans, | |
20d3b647 JB |
335 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
336 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
337 | |
338 | iwl_write_direct32(trans, | |
20d3b647 JB |
339 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
340 | dst_addr); | |
cf614297 EG |
341 | |
342 | iwl_write_direct32(trans, | |
83f84d7b JB |
343 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
344 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
345 | |
346 | iwl_write_direct32(trans, | |
20d3b647 JB |
347 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
348 | (iwl_get_dma_hi_addr(phy_addr) | |
349 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
350 | |
351 | iwl_write_direct32(trans, | |
20d3b647 JB |
352 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
353 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
354 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
355 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
356 | |
357 | iwl_write_direct32(trans, | |
20d3b647 JB |
358 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
359 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
360 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
361 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 362 | |
13df1aab JB |
363 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
364 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 365 | if (!ret) { |
83f84d7b | 366 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
367 | return -ETIMEDOUT; |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
7afe3705 | 373 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 374 | const struct fw_desc *section) |
cf614297 | 375 | { |
83f84d7b JB |
376 | u8 *v_addr; |
377 | dma_addr_t p_addr; | |
c571573a | 378 | u32 offset, chunk_sz = section->len; |
cf614297 EG |
379 | int ret = 0; |
380 | ||
83f84d7b JB |
381 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
382 | section_num); | |
383 | ||
c571573a EG |
384 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
385 | GFP_KERNEL | __GFP_NOWARN); | |
386 | if (!v_addr) { | |
387 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
388 | chunk_sz = PAGE_SIZE; | |
389 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
390 | &p_addr, GFP_KERNEL); | |
391 | if (!v_addr) | |
392 | return -ENOMEM; | |
393 | } | |
83f84d7b | 394 | |
c571573a | 395 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
83f84d7b JB |
396 | u32 copy_size; |
397 | ||
c571573a | 398 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
cf614297 | 399 | |
83f84d7b | 400 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
7afe3705 EG |
401 | ret = iwl_pcie_load_firmware_chunk(trans, |
402 | section->offset + offset, | |
403 | p_addr, copy_size); | |
83f84d7b JB |
404 | if (ret) { |
405 | IWL_ERR(trans, | |
406 | "Could not load the [%d] uCode section\n", | |
407 | section_num); | |
408 | break; | |
6dfa8d01 | 409 | } |
83f84d7b JB |
410 | } |
411 | ||
c571573a | 412 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
413 | return ret; |
414 | } | |
415 | ||
e2d6f4e7 EH |
416 | static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu) |
417 | { | |
418 | int shift_param; | |
419 | u32 address; | |
420 | int ret = 0; | |
421 | ||
422 | if (cpu == 1) { | |
423 | shift_param = 0; | |
424 | address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR; | |
425 | } else { | |
426 | shift_param = 16; | |
427 | address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR; | |
428 | } | |
429 | ||
430 | /* set CPU to started */ | |
431 | iwl_trans_set_bits_mask(trans, | |
432 | CSR_UCODE_LOAD_STATUS_ADDR, | |
433 | CSR_CPU_STATUS_LOADING_STARTED << shift_param, | |
434 | 1); | |
435 | ||
436 | /* set last complete descriptor number */ | |
437 | iwl_trans_set_bits_mask(trans, | |
438 | CSR_UCODE_LOAD_STATUS_ADDR, | |
439 | CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED | |
440 | << shift_param, | |
441 | 1); | |
442 | ||
443 | /* set last loaded block */ | |
444 | iwl_trans_set_bits_mask(trans, | |
445 | CSR_UCODE_LOAD_STATUS_ADDR, | |
446 | CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK | |
447 | << shift_param, | |
448 | 1); | |
449 | ||
450 | /* image loading complete */ | |
451 | iwl_trans_set_bits_mask(trans, | |
452 | CSR_UCODE_LOAD_STATUS_ADDR, | |
453 | CSR_CPU_STATUS_LOADING_COMPLETED | |
454 | << shift_param, | |
455 | 1); | |
456 | ||
457 | /* set FH_TCSR_0_REG */ | |
458 | iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1); | |
459 | ||
460 | /* verify image verification started */ | |
461 | ret = iwl_poll_bit(trans, address, | |
462 | CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS, | |
463 | CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS, | |
464 | CSR_SECURE_TIME_OUT); | |
465 | if (ret < 0) { | |
466 | IWL_ERR(trans, "secure boot process didn't start\n"); | |
467 | return ret; | |
468 | } | |
469 | ||
470 | /* wait for image verification to complete */ | |
471 | ret = iwl_poll_bit(trans, address, | |
472 | CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED, | |
473 | CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED, | |
474 | CSR_SECURE_TIME_OUT); | |
475 | ||
476 | if (ret < 0) { | |
477 | IWL_ERR(trans, "Time out on secure boot process\n"); | |
478 | return ret; | |
479 | } | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
7afe3705 | 484 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 485 | const struct fw_img *image) |
cf614297 | 486 | { |
2d1c0044 | 487 | int i, ret = 0; |
cf614297 | 488 | |
e2d6f4e7 EH |
489 | IWL_DEBUG_FW(trans, |
490 | "working with %s image\n", | |
491 | image->is_secure ? "Secured" : "Non Secured"); | |
492 | IWL_DEBUG_FW(trans, | |
493 | "working with %s CPU\n", | |
494 | image->is_dual_cpus ? "Dual" : "Single"); | |
495 | ||
496 | /* configure the ucode to be ready to get the secured image */ | |
497 | if (image->is_secure) { | |
498 | /* set secure boot inspector addresses */ | |
499 | iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0); | |
500 | iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0); | |
501 | ||
502 | /* release CPU1 reset if secure inspector image burned in OTP */ | |
503 | iwl_write32(trans, CSR_RESET, 0); | |
504 | } | |
505 | ||
506 | /* load to FW the binary sections of CPU1 */ | |
507 | IWL_DEBUG_INFO(trans, "Loading CPU1\n"); | |
508 | for (i = 0; | |
509 | i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU; | |
510 | i++) { | |
83f84d7b | 511 | if (!image->sec[i].data) |
2d1c0044 | 512 | break; |
7afe3705 | 513 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
2d1c0044 JB |
514 | if (ret) |
515 | return ret; | |
516 | } | |
cf614297 | 517 | |
e2d6f4e7 EH |
518 | /* configure the ucode to start secure process on CPU1 */ |
519 | if (image->is_secure) { | |
520 | /* config CPU1 to start secure protocol */ | |
521 | ret = iwl_pcie_secure_set(trans, 1); | |
522 | if (ret) | |
523 | return ret; | |
524 | } else { | |
525 | /* Remove all resets to allow NIC to operate */ | |
526 | iwl_write32(trans, CSR_RESET, 0); | |
527 | } | |
528 | ||
529 | if (image->is_dual_cpus) { | |
530 | /* load to FW the binary sections of CPU2 */ | |
531 | IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n"); | |
532 | for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU; | |
533 | i < IWL_UCODE_SECTION_MAX; i++) { | |
534 | if (!image->sec[i].data) | |
535 | break; | |
536 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); | |
537 | if (ret) | |
538 | return ret; | |
539 | } | |
540 | ||
541 | if (image->is_secure) { | |
542 | /* set CPU2 for secure protocol */ | |
543 | ret = iwl_pcie_secure_set(trans, 2); | |
544 | if (ret) | |
545 | return ret; | |
546 | } | |
547 | } | |
cf614297 EG |
548 | |
549 | return 0; | |
550 | } | |
551 | ||
0692fe41 | 552 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 553 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 EG |
554 | { |
555 | int ret; | |
c9eec95c | 556 | bool hw_rfkill; |
392f8b78 | 557 | |
496bab39 | 558 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 559 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 560 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
561 | return -EIO; |
562 | } | |
563 | ||
8c46bb70 EG |
564 | iwl_enable_rfkill_int(trans); |
565 | ||
392f8b78 | 566 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 567 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 568 | if (hw_rfkill) |
eb7ff77e | 569 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 570 | else |
eb7ff77e | 571 | clear_bit(STATUS_RFKILL, &trans->status); |
c9eec95c | 572 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
6ae02f3e | 573 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 574 | return -ERFKILL; |
392f8b78 | 575 | |
1042db2a | 576 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 577 | |
7afe3705 | 578 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 579 | if (ret) { |
6d8f6eeb | 580 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
581 | return ret; |
582 | } | |
583 | ||
584 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
585 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
586 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
587 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
588 | ||
589 | /* clear (again), then enable host interrupts */ | |
1042db2a | 590 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 591 | iwl_enable_interrupts(trans); |
392f8b78 EG |
592 | |
593 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
594 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
595 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 596 | |
cf614297 | 597 | /* Load the given image to the HW */ |
7afe3705 | 598 | return iwl_pcie_load_given_ucode(trans, fw); |
b3c2ce13 EG |
599 | } |
600 | ||
adca1235 | 601 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 602 | { |
990aa6d7 | 603 | iwl_pcie_reset_ict(trans); |
f02831be | 604 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
605 | } |
606 | ||
43e58856 | 607 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 608 | { |
43e58856 | 609 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3dc3374f EG |
610 | bool hw_rfkill, was_hw_rfkill; |
611 | ||
612 | was_hw_rfkill = iwl_is_rfkill_set(trans); | |
ae2c30bf | 613 | |
43e58856 | 614 | /* tell the device to stop sending interrupts */ |
7b70bd63 | 615 | spin_lock(&trans_pcie->irq_lock); |
ae2c30bf | 616 | iwl_disable_interrupts(trans); |
7b70bd63 | 617 | spin_unlock(&trans_pcie->irq_lock); |
ae2c30bf | 618 | |
ab6cf8e8 | 619 | /* device going down, Stop using ICT table */ |
990aa6d7 | 620 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
621 | |
622 | /* | |
623 | * If a HW restart happens during firmware loading, | |
624 | * then the firmware loading might call this function | |
625 | * and later it might be called again due to the | |
626 | * restart. So don't process again if the device is | |
627 | * already dead. | |
628 | */ | |
eb7ff77e | 629 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
f02831be | 630 | iwl_pcie_tx_stop(trans); |
9805c446 | 631 | iwl_pcie_rx_stop(trans); |
6379103e | 632 | |
ab6cf8e8 | 633 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 634 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
635 | APMG_CLK_VAL_DMA_CLK_RQT); |
636 | udelay(5); | |
637 | } | |
638 | ||
639 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 640 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 641 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
642 | |
643 | /* Stop the device, and put it in low power state */ | |
7afe3705 | 644 | iwl_pcie_apm_stop(trans); |
43e58856 EG |
645 | |
646 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
647 | * Clean again the interrupt here | |
648 | */ | |
7b70bd63 | 649 | spin_lock(&trans_pcie->irq_lock); |
43e58856 | 650 | iwl_disable_interrupts(trans); |
7b70bd63 | 651 | spin_unlock(&trans_pcie->irq_lock); |
43e58856 | 652 | |
43e58856 | 653 | /* stop and reset the on-board processor */ |
1042db2a | 654 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
655 | |
656 | /* clear all status bits */ | |
eb7ff77e AN |
657 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
658 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
659 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); | |
660 | clear_bit(STATUS_TPOWER_PMI, &trans->status); | |
661 | clear_bit(STATUS_RFKILL, &trans->status); | |
a4082843 AN |
662 | |
663 | /* | |
664 | * Even if we stop the HW, we still want the RF kill | |
665 | * interrupt | |
666 | */ | |
667 | iwl_enable_rfkill_int(trans); | |
668 | ||
669 | /* | |
670 | * Check again since the RF kill state may have changed while | |
671 | * all the interrupts were disabled, in this case we couldn't | |
672 | * receive the RF kill interrupt and update the state in the | |
673 | * op_mode. | |
3dc3374f EG |
674 | * Don't call the op_mode if the rkfill state hasn't changed. |
675 | * This allows the op_mode to call stop_device from the rfkill | |
676 | * notification without endless recursion. Under very rare | |
677 | * circumstances, we might have a small recursion if the rfkill | |
678 | * state changed exactly now while we were called from stop_device. | |
679 | * This is very unlikely but can happen and is supported. | |
a4082843 AN |
680 | */ |
681 | hw_rfkill = iwl_is_rfkill_set(trans); | |
682 | if (hw_rfkill) | |
eb7ff77e | 683 | set_bit(STATUS_RFKILL, &trans->status); |
a4082843 | 684 | else |
eb7ff77e | 685 | clear_bit(STATUS_RFKILL, &trans->status); |
3dc3374f EG |
686 | if (hw_rfkill != was_hw_rfkill) |
687 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); | |
ab6cf8e8 EG |
688 | } |
689 | ||
debff618 | 690 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) |
2dd4f9f7 | 691 | { |
2dd4f9f7 | 692 | iwl_disable_interrupts(trans); |
debff618 JB |
693 | |
694 | /* | |
695 | * in testing mode, the host stays awake and the | |
696 | * hardware won't be reset (not even partially) | |
697 | */ | |
698 | if (test) | |
699 | return; | |
700 | ||
ddaf5a5b JB |
701 | iwl_pcie_disable_ict(trans); |
702 | ||
2dd4f9f7 JB |
703 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
704 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
705 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
706 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
707 | ||
708 | /* | |
709 | * reset TX queues -- some of their registers reset during S3 | |
710 | * so if we don't reset everything here the D3 image would try | |
711 | * to execute some invalid memory upon resume | |
712 | */ | |
713 | iwl_trans_pcie_tx_reset(trans); | |
714 | ||
715 | iwl_pcie_set_pwr(trans, true); | |
716 | } | |
717 | ||
718 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
719 | enum iwl_d3_status *status, |
720 | bool test) | |
ddaf5a5b JB |
721 | { |
722 | u32 val; | |
723 | int ret; | |
724 | ||
debff618 JB |
725 | if (test) { |
726 | iwl_enable_interrupts(trans); | |
727 | *status = IWL_D3_STATUS_ALIVE; | |
728 | return 0; | |
729 | } | |
730 | ||
ddaf5a5b JB |
731 | iwl_pcie_set_pwr(trans, false); |
732 | ||
733 | val = iwl_read32(trans, CSR_RESET); | |
734 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { | |
735 | *status = IWL_D3_STATUS_RESET; | |
736 | return 0; | |
737 | } | |
738 | ||
739 | /* | |
740 | * Also enables interrupts - none will happen as the device doesn't | |
741 | * know we're waking it up, only when the opmode actually tells it | |
742 | * after this call. | |
743 | */ | |
744 | iwl_pcie_reset_ict(trans); | |
745 | ||
746 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
747 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
748 | ||
749 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
750 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
751 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
752 | 25000); | |
753 | if (ret) { | |
754 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); | |
755 | return ret; | |
756 | } | |
757 | ||
758 | iwl_trans_pcie_tx_reset(trans); | |
759 | ||
760 | ret = iwl_pcie_rx_init(trans); | |
761 | if (ret) { | |
762 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
763 | return ret; | |
764 | } | |
765 | ||
ddaf5a5b JB |
766 | *status = IWL_D3_STATUS_ALIVE; |
767 | return 0; | |
2dd4f9f7 JB |
768 | } |
769 | ||
57a1dc89 | 770 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 771 | { |
c9eec95c | 772 | bool hw_rfkill; |
a8b691e6 | 773 | int err; |
e6bb4c9c | 774 | |
7afe3705 | 775 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 776 | if (err) { |
d6f1c316 | 777 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 778 | return err; |
ebb7678d | 779 | } |
a6c684ee | 780 | |
2997494f | 781 | /* Reset the entire device */ |
ce836c76 | 782 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
2997494f EG |
783 | |
784 | usleep_range(10, 15); | |
785 | ||
7afe3705 | 786 | iwl_pcie_apm_init(trans); |
a6c684ee | 787 | |
226c02ca EG |
788 | /* From now on, the op_mode will be kept updated about RF kill state */ |
789 | iwl_enable_rfkill_int(trans); | |
790 | ||
8d425517 | 791 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 792 | if (hw_rfkill) |
eb7ff77e | 793 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 794 | else |
eb7ff77e | 795 | clear_bit(STATUS_RFKILL, &trans->status); |
c9eec95c | 796 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 797 | |
a8b691e6 | 798 | return 0; |
e6bb4c9c EG |
799 | } |
800 | ||
a4082843 | 801 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 802 | { |
20d3b647 | 803 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 804 | |
a4082843 | 805 | /* disable interrupts - don't enable HW RF kill interrupt */ |
7b70bd63 | 806 | spin_lock(&trans_pcie->irq_lock); |
ee7d737c | 807 | iwl_disable_interrupts(trans); |
7b70bd63 | 808 | spin_unlock(&trans_pcie->irq_lock); |
ee7d737c | 809 | |
7afe3705 | 810 | iwl_pcie_apm_stop(trans); |
cc56feb2 | 811 | |
7b70bd63 | 812 | spin_lock(&trans_pcie->irq_lock); |
218733cf | 813 | iwl_disable_interrupts(trans); |
7b70bd63 | 814 | spin_unlock(&trans_pcie->irq_lock); |
1df06bdc | 815 | |
8d96bb61 | 816 | iwl_pcie_disable_ict(trans); |
cc56feb2 EG |
817 | } |
818 | ||
03905495 EG |
819 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
820 | { | |
05f5b97e | 821 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
822 | } |
823 | ||
824 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
825 | { | |
05f5b97e | 826 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
827 | } |
828 | ||
829 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
830 | { | |
05f5b97e | 831 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
832 | } |
833 | ||
6a06b6c1 EG |
834 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
835 | { | |
f9477c17 AP |
836 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
837 | ((reg & 0x000FFFFF) | (3 << 24))); | |
6a06b6c1 EG |
838 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
839 | } | |
840 | ||
841 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
842 | u32 val) | |
843 | { | |
844 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
f9477c17 | 845 | ((addr & 0x000FFFFF) | (3 << 24))); |
6a06b6c1 EG |
846 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
847 | } | |
848 | ||
c6f600fc | 849 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 850 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
851 | { |
852 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
853 | ||
854 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 855 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
856 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
857 | trans_pcie->n_no_reclaim_cmds = 0; | |
858 | else | |
859 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
860 | if (trans_pcie->n_no_reclaim_cmds) | |
861 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
862 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 863 | |
b2cf410c JB |
864 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
865 | if (trans_pcie->rx_buf_size_8k) | |
866 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
867 | else | |
868 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
869 | |
870 | trans_pcie->wd_timeout = | |
871 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
872 | |
873 | trans_pcie->command_names = trans_cfg->command_names; | |
046db346 | 874 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
c6f600fc MV |
875 | } |
876 | ||
d1ff5253 | 877 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 878 | { |
20d3b647 | 879 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 880 | |
0aa86df6 | 881 | synchronize_irq(trans_pcie->pci_dev->irq); |
0aa86df6 | 882 | |
f02831be | 883 | iwl_pcie_tx_free(trans); |
9805c446 | 884 | iwl_pcie_rx_free(trans); |
6379103e | 885 | |
a8b691e6 JB |
886 | free_irq(trans_pcie->pci_dev->irq, trans); |
887 | iwl_pcie_free_ict(trans); | |
a42a1844 EG |
888 | |
889 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 890 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
891 | pci_release_regions(trans_pcie->pci_dev); |
892 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 893 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 894 | |
6d8f6eeb | 895 | kfree(trans); |
34c1b7ba EG |
896 | } |
897 | ||
47107e84 DF |
898 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
899 | { | |
47107e84 | 900 | if (state) |
eb7ff77e | 901 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 902 | else |
eb7ff77e | 903 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
904 | } |
905 | ||
e56b04ef LE |
906 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, |
907 | unsigned long *flags) | |
7a65d170 EG |
908 | { |
909 | int ret; | |
cfb4e624 JB |
910 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
911 | ||
912 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 | 913 | |
b9439491 EG |
914 | if (trans_pcie->cmd_in_flight) |
915 | goto out; | |
916 | ||
7a65d170 | 917 | /* this bit wakes up the NIC */ |
e139dc4a LE |
918 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
919 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
920 | |
921 | /* | |
922 | * These bits say the device is running, and should keep running for | |
923 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
924 | * but they do not indicate that embedded SRAM is restored yet; | |
925 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
926 | * to/from host DRAM when sleeping/waking for power-saving. | |
927 | * Each direction takes approximately 1/4 millisecond; with this | |
928 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
929 | * series of register accesses are expected (e.g. reading Event Log), | |
930 | * to keep device from sleeping. | |
931 | * | |
932 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
933 | * SRAM is okay/restored. We don't check that here because this call | |
934 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
935 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
936 | * | |
937 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
938 | * and do not save/restore SRAM when power cycling. | |
939 | */ | |
940 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
941 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
942 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
943 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
944 | if (unlikely(ret < 0)) { | |
945 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
946 | if (!silent) { | |
947 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
948 | WARN_ONCE(1, | |
949 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
950 | val); | |
cfb4e624 | 951 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
952 | return false; |
953 | } | |
954 | } | |
955 | ||
b9439491 | 956 | out: |
e56b04ef LE |
957 | /* |
958 | * Fool sparse by faking we release the lock - sparse will | |
959 | * track nic_access anyway. | |
960 | */ | |
cfb4e624 | 961 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
962 | return true; |
963 | } | |
964 | ||
e56b04ef LE |
965 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
966 | unsigned long *flags) | |
7a65d170 | 967 | { |
cfb4e624 | 968 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 969 | |
cfb4e624 | 970 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
971 | |
972 | /* | |
973 | * Fool sparse by faking we acquiring the lock - sparse will | |
974 | * track nic_access anyway. | |
975 | */ | |
cfb4e624 | 976 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 977 | |
b9439491 EG |
978 | if (trans_pcie->cmd_in_flight) |
979 | goto out; | |
980 | ||
e139dc4a LE |
981 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
982 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
983 | /* |
984 | * Above we read the CSR_GP_CNTRL register, which will flush | |
985 | * any previous writes, but we need the write that clears the | |
986 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
987 | * scheduled on different CPUs (after we drop reg_lock). | |
988 | */ | |
989 | mmiowb(); | |
b9439491 | 990 | out: |
cfb4e624 | 991 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
992 | } |
993 | ||
4fd442db EG |
994 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
995 | void *buf, int dwords) | |
996 | { | |
997 | unsigned long flags; | |
998 | int offs, ret = 0; | |
999 | u32 *vals = buf; | |
1000 | ||
e56b04ef | 1001 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1002 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
1003 | for (offs = 0; offs < dwords; offs++) | |
1004 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 1005 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1006 | } else { |
1007 | ret = -EBUSY; | |
1008 | } | |
4fd442db EG |
1009 | return ret; |
1010 | } | |
1011 | ||
1012 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1013 | const void *buf, int dwords) |
4fd442db EG |
1014 | { |
1015 | unsigned long flags; | |
1016 | int offs, ret = 0; | |
bf0fd5da | 1017 | const u32 *vals = buf; |
4fd442db | 1018 | |
e56b04ef | 1019 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1020 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
1021 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
1022 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
1023 | vals ? vals[offs] : 0); | |
e56b04ef | 1024 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1025 | } else { |
1026 | ret = -EBUSY; | |
1027 | } | |
4fd442db EG |
1028 | return ret; |
1029 | } | |
7a65d170 | 1030 | |
5f178cd2 EG |
1031 | #define IWL_FLUSH_WAIT_MS 2000 |
1032 | ||
990aa6d7 | 1033 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) |
5f178cd2 | 1034 | { |
8ad71bef | 1035 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1036 | struct iwl_txq *txq; |
5f178cd2 EG |
1037 | struct iwl_queue *q; |
1038 | int cnt; | |
1039 | unsigned long now = jiffies; | |
1c3fea82 EG |
1040 | u32 scd_sram_addr; |
1041 | u8 buf[16]; | |
5f178cd2 EG |
1042 | int ret = 0; |
1043 | ||
1044 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1045 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 1046 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1047 | continue; |
8ad71bef | 1048 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1049 | q = &txq->q; |
1050 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1051 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1052 | msleep(1); | |
1053 | ||
1054 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
1055 | IWL_ERR(trans, |
1056 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
1057 | ret = -ETIMEDOUT; |
1058 | break; | |
1059 | } | |
1060 | } | |
1c3fea82 EG |
1061 | |
1062 | if (!ret) | |
1063 | return 0; | |
1064 | ||
1065 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
1066 | txq->q.read_ptr, txq->q.write_ptr); | |
1067 | ||
1068 | scd_sram_addr = trans_pcie->scd_base_addr + | |
1069 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
1070 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
1071 | ||
1072 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
1073 | ||
1074 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
1075 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
1076 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
1077 | ||
1078 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1079 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
1080 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
1081 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
1082 | u32 tbl_dw = | |
1083 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
1084 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
1085 | ||
1086 | if (cnt & 0x1) | |
1087 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
1088 | else | |
1089 | tbl_dw = tbl_dw & 0x0000FFFF; | |
1090 | ||
1091 | IWL_ERR(trans, | |
1092 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
1093 | cnt, active ? "" : "in", fifo, tbl_dw, | |
1094 | iwl_read_prph(trans, | |
1095 | SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1), | |
1096 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); | |
1097 | } | |
1098 | ||
5f178cd2 EG |
1099 | return ret; |
1100 | } | |
1101 | ||
e139dc4a LE |
1102 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
1103 | u32 mask, u32 value) | |
1104 | { | |
e56b04ef | 1105 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
1106 | unsigned long flags; |
1107 | ||
e56b04ef | 1108 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 1109 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 1110 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
1111 | } |
1112 | ||
ff620849 EG |
1113 | static const char *get_csr_string(int cmd) |
1114 | { | |
d9fb6465 | 1115 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1116 | switch (cmd) { |
1117 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1118 | IWL_CMD(CSR_INT_COALESCING); | |
1119 | IWL_CMD(CSR_INT); | |
1120 | IWL_CMD(CSR_INT_MASK); | |
1121 | IWL_CMD(CSR_FH_INT_STATUS); | |
1122 | IWL_CMD(CSR_GPIO_IN); | |
1123 | IWL_CMD(CSR_RESET); | |
1124 | IWL_CMD(CSR_GP_CNTRL); | |
1125 | IWL_CMD(CSR_HW_REV); | |
1126 | IWL_CMD(CSR_EEPROM_REG); | |
1127 | IWL_CMD(CSR_EEPROM_GP); | |
1128 | IWL_CMD(CSR_OTP_GP_REG); | |
1129 | IWL_CMD(CSR_GIO_REG); | |
1130 | IWL_CMD(CSR_GP_UCODE_REG); | |
1131 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1132 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1133 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1134 | IWL_CMD(CSR_LED_REG); | |
1135 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1136 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1137 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1138 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1139 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1140 | default: | |
1141 | return "UNKNOWN"; | |
1142 | } | |
d9fb6465 | 1143 | #undef IWL_CMD |
ff620849 EG |
1144 | } |
1145 | ||
990aa6d7 | 1146 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
1147 | { |
1148 | int i; | |
1149 | static const u32 csr_tbl[] = { | |
1150 | CSR_HW_IF_CONFIG_REG, | |
1151 | CSR_INT_COALESCING, | |
1152 | CSR_INT, | |
1153 | CSR_INT_MASK, | |
1154 | CSR_FH_INT_STATUS, | |
1155 | CSR_GPIO_IN, | |
1156 | CSR_RESET, | |
1157 | CSR_GP_CNTRL, | |
1158 | CSR_HW_REV, | |
1159 | CSR_EEPROM_REG, | |
1160 | CSR_EEPROM_GP, | |
1161 | CSR_OTP_GP_REG, | |
1162 | CSR_GIO_REG, | |
1163 | CSR_GP_UCODE_REG, | |
1164 | CSR_GP_DRIVER_REG, | |
1165 | CSR_UCODE_DRV_GP1, | |
1166 | CSR_UCODE_DRV_GP2, | |
1167 | CSR_LED_REG, | |
1168 | CSR_DRAM_INT_TBL_REG, | |
1169 | CSR_GIO_CHICKEN_BITS, | |
1170 | CSR_ANA_PLL_CFG, | |
1171 | CSR_HW_REV_WA_REG, | |
1172 | CSR_DBG_HPET_MEM_REG | |
1173 | }; | |
1174 | IWL_ERR(trans, "CSR values:\n"); | |
1175 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1176 | "CSR_INT_PERIODIC_REG)\n"); | |
1177 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1178 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1179 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1180 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1181 | } |
1182 | } | |
1183 | ||
87e5666c EG |
1184 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1185 | /* create and remove of files */ | |
1186 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1187 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1188 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1189 | goto err; \ |
87e5666c EG |
1190 | } while (0) |
1191 | ||
1192 | /* file operation */ | |
87e5666c | 1193 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
1194 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1195 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1196 | .open = simple_open, \ |
87e5666c EG |
1197 | .llseek = generic_file_llseek, \ |
1198 | }; | |
1199 | ||
16db88ba | 1200 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
1201 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1202 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1203 | .open = simple_open, \ |
16db88ba EG |
1204 | .llseek = generic_file_llseek, \ |
1205 | }; | |
1206 | ||
87e5666c | 1207 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
1208 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1209 | .write = iwl_dbgfs_##name##_write, \ | |
1210 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1211 | .open = simple_open, \ |
87e5666c EG |
1212 | .llseek = generic_file_llseek, \ |
1213 | }; | |
1214 | ||
87e5666c | 1215 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1216 | char __user *user_buf, |
1217 | size_t count, loff_t *ppos) | |
8ad71bef | 1218 | { |
5a878bf6 | 1219 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1220 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1221 | struct iwl_txq *txq; |
87e5666c EG |
1222 | struct iwl_queue *q; |
1223 | char *buf; | |
1224 | int pos = 0; | |
1225 | int cnt; | |
1226 | int ret; | |
1745e440 WYG |
1227 | size_t bufsz; |
1228 | ||
035f7ff2 | 1229 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1230 | |
f9e75447 | 1231 | if (!trans_pcie->txq) |
87e5666c | 1232 | return -EAGAIN; |
f9e75447 | 1233 | |
87e5666c EG |
1234 | buf = kzalloc(bufsz, GFP_KERNEL); |
1235 | if (!buf) | |
1236 | return -ENOMEM; | |
1237 | ||
035f7ff2 | 1238 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1239 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1240 | q = &txq->q; |
1241 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1242 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1243 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1244 | !!test_bit(cnt, trans_pcie->queue_used), |
1245 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1246 | } |
1247 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1248 | kfree(buf); | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1253 | char __user *user_buf, |
1254 | size_t count, loff_t *ppos) | |
1255 | { | |
5a878bf6 | 1256 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1257 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1258 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1259 | char buf[256]; |
1260 | int pos = 0; | |
1261 | const size_t bufsz = sizeof(buf); | |
1262 | ||
1263 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1264 | rxq->read); | |
1265 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1266 | rxq->write); | |
1267 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1268 | rxq->free_count); | |
1269 | if (rxq->rb_stts) { | |
1270 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1271 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1272 | } else { | |
1273 | pos += scnprintf(buf + pos, bufsz - pos, | |
1274 | "closed_rb_num: Not Allocated\n"); | |
1275 | } | |
1276 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1277 | } | |
1278 | ||
1f7b6172 EG |
1279 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1280 | char __user *user_buf, | |
20d3b647 JB |
1281 | size_t count, loff_t *ppos) |
1282 | { | |
1f7b6172 | 1283 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1284 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1285 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1286 | ||
1287 | int pos = 0; | |
1288 | char *buf; | |
1289 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1290 | ssize_t ret; | |
1291 | ||
1292 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1293 | if (!buf) |
1f7b6172 | 1294 | return -ENOMEM; |
1f7b6172 EG |
1295 | |
1296 | pos += scnprintf(buf + pos, bufsz - pos, | |
1297 | "Interrupt Statistics Report:\n"); | |
1298 | ||
1299 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1300 | isr_stats->hw); | |
1301 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1302 | isr_stats->sw); | |
1303 | if (isr_stats->sw || isr_stats->hw) { | |
1304 | pos += scnprintf(buf + pos, bufsz - pos, | |
1305 | "\tLast Restarting Code: 0x%X\n", | |
1306 | isr_stats->err_code); | |
1307 | } | |
1308 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1309 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1310 | isr_stats->sch); | |
1311 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1312 | isr_stats->alive); | |
1313 | #endif | |
1314 | pos += scnprintf(buf + pos, bufsz - pos, | |
1315 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1316 | ||
1317 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1318 | isr_stats->ctkill); | |
1319 | ||
1320 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1321 | isr_stats->wakeup); | |
1322 | ||
1323 | pos += scnprintf(buf + pos, bufsz - pos, | |
1324 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1325 | ||
1326 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1327 | isr_stats->tx); | |
1328 | ||
1329 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1330 | isr_stats->unhandled); | |
1331 | ||
1332 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1333 | kfree(buf); | |
1334 | return ret; | |
1335 | } | |
1336 | ||
1337 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1338 | const char __user *user_buf, | |
1339 | size_t count, loff_t *ppos) | |
1340 | { | |
1341 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1342 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1343 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1344 | ||
1345 | char buf[8]; | |
1346 | int buf_size; | |
1347 | u32 reset_flag; | |
1348 | ||
1349 | memset(buf, 0, sizeof(buf)); | |
1350 | buf_size = min(count, sizeof(buf) - 1); | |
1351 | if (copy_from_user(buf, user_buf, buf_size)) | |
1352 | return -EFAULT; | |
1353 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1354 | return -EFAULT; | |
1355 | if (reset_flag == 0) | |
1356 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1357 | ||
1358 | return count; | |
1359 | } | |
1360 | ||
16db88ba | 1361 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1362 | const char __user *user_buf, |
1363 | size_t count, loff_t *ppos) | |
16db88ba EG |
1364 | { |
1365 | struct iwl_trans *trans = file->private_data; | |
1366 | char buf[8]; | |
1367 | int buf_size; | |
1368 | int csr; | |
1369 | ||
1370 | memset(buf, 0, sizeof(buf)); | |
1371 | buf_size = min(count, sizeof(buf) - 1); | |
1372 | if (copy_from_user(buf, user_buf, buf_size)) | |
1373 | return -EFAULT; | |
1374 | if (sscanf(buf, "%d", &csr) != 1) | |
1375 | return -EFAULT; | |
1376 | ||
990aa6d7 | 1377 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1378 | |
1379 | return count; | |
1380 | } | |
1381 | ||
16db88ba | 1382 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1383 | char __user *user_buf, |
1384 | size_t count, loff_t *ppos) | |
16db88ba EG |
1385 | { |
1386 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1387 | char *buf = NULL; |
16db88ba EG |
1388 | int pos = 0; |
1389 | ssize_t ret = -EFAULT; | |
1390 | ||
313b0a29 | 1391 | ret = pos = iwl_dump_fh(trans, &buf); |
16db88ba EG |
1392 | if (buf) { |
1393 | ret = simple_read_from_buffer(user_buf, | |
1394 | count, ppos, buf, pos); | |
1395 | kfree(buf); | |
1396 | } | |
1397 | ||
1398 | return ret; | |
1399 | } | |
1400 | ||
1f7b6172 | 1401 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1402 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1403 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1404 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1405 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
1406 | |
1407 | /* | |
1408 | * Create the debugfs files and directories | |
1409 | * | |
1410 | */ | |
1411 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1412 | struct dentry *dir) |
87e5666c | 1413 | { |
87e5666c EG |
1414 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1415 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1416 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1417 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1418 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c | 1419 | return 0; |
9da987ac MV |
1420 | |
1421 | err: | |
1422 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1423 | return -ENOMEM; | |
87e5666c EG |
1424 | } |
1425 | #else | |
1426 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
1427 | struct dentry *dir) |
1428 | { | |
1429 | return 0; | |
1430 | } | |
87e5666c EG |
1431 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
1432 | ||
d1ff5253 | 1433 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 1434 | .start_hw = iwl_trans_pcie_start_hw, |
a4082843 | 1435 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, |
ed6a3803 | 1436 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 1437 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 1438 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 1439 | |
ddaf5a5b JB |
1440 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
1441 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 1442 | |
f02831be | 1443 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 1444 | |
e6bb4c9c | 1445 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1446 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1447 | |
d0624be6 | 1448 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 1449 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 1450 | |
87e5666c | 1451 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 1452 | |
990aa6d7 | 1453 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 1454 | |
03905495 EG |
1455 | .write8 = iwl_trans_pcie_write8, |
1456 | .write32 = iwl_trans_pcie_write32, | |
1457 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
1458 | .read_prph = iwl_trans_pcie_read_prph, |
1459 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
1460 | .read_mem = iwl_trans_pcie_read_mem, |
1461 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 1462 | .configure = iwl_trans_pcie_configure, |
47107e84 | 1463 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 1464 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
1465 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
1466 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
e6bb4c9c | 1467 | }; |
a42a1844 | 1468 | |
87ce05a2 | 1469 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
1470 | const struct pci_device_id *ent, |
1471 | const struct iwl_cfg *cfg) | |
a42a1844 | 1472 | { |
a42a1844 EG |
1473 | struct iwl_trans_pcie *trans_pcie; |
1474 | struct iwl_trans *trans; | |
1475 | u16 pci_cmd; | |
1476 | int err; | |
1477 | ||
1478 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 1479 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
6965a354 LC |
1480 | if (!trans) { |
1481 | err = -ENOMEM; | |
1482 | goto out; | |
1483 | } | |
a42a1844 EG |
1484 | |
1485 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1486 | ||
1487 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 1488 | trans->cfg = cfg; |
2bfb5092 | 1489 | trans_lockdep_init(trans); |
a42a1844 | 1490 | trans_pcie->trans = trans; |
7b11488f | 1491 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 1492 | spin_lock_init(&trans_pcie->reg_lock); |
13df1aab | 1493 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 | 1494 | |
d819c6cf JB |
1495 | err = pci_enable_device(pdev); |
1496 | if (err) | |
1497 | goto out_no_pci; | |
1498 | ||
f2532b04 EG |
1499 | if (!cfg->base_params->pcie_l1_allowed) { |
1500 | /* | |
1501 | * W/A - seems to solve weird behavior. We need to remove this | |
1502 | * if we don't want to stay in L1 all the time. This wastes a | |
1503 | * lot of power. | |
1504 | */ | |
1505 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
1506 | PCIE_LINK_STATE_L1 | | |
1507 | PCIE_LINK_STATE_CLKPM); | |
1508 | } | |
a42a1844 | 1509 | |
a42a1844 EG |
1510 | pci_set_master(pdev); |
1511 | ||
1512 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1513 | if (!err) | |
1514 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1515 | if (err) { | |
1516 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1517 | if (!err) | |
1518 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 1519 | DMA_BIT_MASK(32)); |
a42a1844 EG |
1520 | /* both attempts failed: */ |
1521 | if (err) { | |
6a4b09f8 | 1522 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
1523 | goto out_pci_disable_device; |
1524 | } | |
1525 | } | |
1526 | ||
1527 | err = pci_request_regions(pdev, DRV_NAME); | |
1528 | if (err) { | |
6a4b09f8 | 1529 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
1530 | goto out_pci_disable_device; |
1531 | } | |
1532 | ||
05f5b97e | 1533 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 1534 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 1535 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
1536 | err = -ENODEV; |
1537 | goto out_pci_release_regions; | |
1538 | } | |
1539 | ||
a42a1844 EG |
1540 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
1541 | * PCI Tx retries from interfering with C3 CPU state */ | |
1542 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1543 | ||
1544 | err = pci_enable_msi(pdev); | |
9f904b38 | 1545 | if (err) { |
6a4b09f8 | 1546 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
1547 | /* enable rfkill interrupt: hw bug w/a */ |
1548 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1549 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1550 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1551 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1552 | } | |
1553 | } | |
a42a1844 EG |
1554 | |
1555 | trans->dev = &pdev->dev; | |
a42a1844 | 1556 | trans_pcie->pci_dev = pdev; |
08079a49 | 1557 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 1558 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
1559 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
1560 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 1561 | |
69a10b29 | 1562 | /* Initialize the wait queue for commands */ |
f946b529 | 1563 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 1564 | |
3ec45882 JB |
1565 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
1566 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
1567 | |
1568 | trans->dev_cmd_headroom = 0; | |
1569 | trans->dev_cmd_pool = | |
3ec45882 | 1570 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
1571 | sizeof(struct iwl_device_cmd) |
1572 | + trans->dev_cmd_headroom, | |
1573 | sizeof(void *), | |
1574 | SLAB_HWCACHE_ALIGN, | |
1575 | NULL); | |
1576 | ||
6965a354 LC |
1577 | if (!trans->dev_cmd_pool) { |
1578 | err = -ENOMEM; | |
59c647b6 | 1579 | goto out_pci_disable_msi; |
6965a354 | 1580 | } |
59c647b6 | 1581 | |
a8b691e6 JB |
1582 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1583 | ||
a8b691e6 JB |
1584 | if (iwl_pcie_alloc_ict(trans)) |
1585 | goto out_free_cmd_pool; | |
1586 | ||
85bf9da1 | 1587 | err = request_threaded_irq(pdev->irq, iwl_pcie_isr, |
6965a354 LC |
1588 | iwl_pcie_irq_handler, |
1589 | IRQF_SHARED, DRV_NAME, trans); | |
1590 | if (err) { | |
a8b691e6 JB |
1591 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
1592 | goto out_free_ict; | |
1593 | } | |
1594 | ||
a42a1844 EG |
1595 | return trans; |
1596 | ||
a8b691e6 JB |
1597 | out_free_ict: |
1598 | iwl_pcie_free_ict(trans); | |
1599 | out_free_cmd_pool: | |
1600 | kmem_cache_destroy(trans->dev_cmd_pool); | |
59c647b6 EG |
1601 | out_pci_disable_msi: |
1602 | pci_disable_msi(pdev); | |
a42a1844 EG |
1603 | out_pci_release_regions: |
1604 | pci_release_regions(pdev); | |
1605 | out_pci_disable_device: | |
1606 | pci_disable_device(pdev); | |
1607 | out_no_pci: | |
1608 | kfree(trans); | |
6965a354 LC |
1609 | out: |
1610 | return ERR_PTR(err); | |
a42a1844 | 1611 | } |