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iwlwifi: mvm: document switch case fall-through in iwl_mvm_send_sta_key
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8b4139dc 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
7a10e3e4 78#include "iwl-agn-hw.h"
4d075007 79#include "iwl-fw-error-dump.h"
6468a01a 80#include "internal.h"
06d51e0d 81#include "iwl-fh.h"
0439bb62 82
fe45773b
AN		 83/* extended range in FW SRAM */
84#define IWL_FW_MEM_EXTENDED_START 0x40000
85#define IWL_FW_MEM_EXTENDED_END 0x57FFF
86
c2d20201
EG		 87static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
88{
89 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
90
91 if (!trans_pcie->fw_mon_page)
92 return;
93
94 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
95 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
96 __free_pages(trans_pcie->fw_mon_page,
97 get_order(trans_pcie->fw_mon_size));
98 trans_pcie->fw_mon_page = NULL;
99 trans_pcie->fw_mon_phys = 0;
100 trans_pcie->fw_mon_size = 0;
101}
102
103static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
104{
105 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
106 struct page *page;
107 dma_addr_t phys;
108 u32 size;
109 u8 power;
110
111 if (trans_pcie->fw_mon_page) {
112 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
113 trans_pcie->fw_mon_size,
114 DMA_FROM_DEVICE);
115 return;
116 }
117
118 phys = 0;
119 for (power = 26; power >= 11; power--) {
120 int order;
121
122 size = BIT(power);
123 order = get_order(size);
124 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
125 order);
126 if (!page)
127 continue;
128
129 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
130 DMA_FROM_DEVICE);
131 if (dma_mapping_error(trans->dev, phys)) {
132 __free_pages(page, order);
133 continue;
134 }
135 IWL_INFO(trans,
136 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
137 size, order);
138 break;
139 }
140
40a76905 141 if (WARN_ON_ONCE(!page))
c2d20201
EG		 142 return;
143
144 trans_pcie->fw_mon_page = page;
145 trans_pcie->fw_mon_phys = phys;
146 trans_pcie->fw_mon_size = size;
147}
148
a812cba9
AB		 149static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
150{
151 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
152 ((reg & 0x0000ffff) | (2 << 28)));
153 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
154}
155
156static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
157{
158 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
159 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
160 ((reg & 0x0000ffff) | (3 << 28)));
161}
162
ddaf5a5b 163static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 164{
ddaf5a5b
JB		 165 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
166 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
167 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
168 ~APMG_PS_CTRL_MSK_PWR_SRC);
169 else
170 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
171 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
172 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 173}
174
af634bee
EG		 175/* PCI registers */
176#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 177
7afe3705 178static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 179{
20d3b647 180 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 181 u16 lctl;
9180ac50 182 u16 cap;
af634bee 183
af634bee
EG		 184 /*
185 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
186 * Check if BIOS (or OS) enabled L1-ASPM on this device.
187 * If so (likely), disable L0S, so device moves directly L0->L1;
188 * costs negligible amount of power savings.
189 * If not (unlikely), enable L0S, so there is at least some
190 * power savings, even without L1.
191 */
7afe3705 192 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 193 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 194 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 195 else
af634bee 196 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 197 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 198
199 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
200 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
201 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
202 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
203 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 204}
205
a6c684ee
EG		 206/*
207 * Start up NIC's basic functionality after it has been reset
7afe3705 208 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 209 * NOTE: This does not load uCode nor start the embedded processor
210 */
7afe3705 211static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 212{
213 int ret = 0;
214 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
215
216 /*
217 * Use "set_bit" below rather than "write", to preserve any hardware
218 * bits already set by default after reset.
219 */
220
221 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 222 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
223 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
224 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 225
226 /*
227 * Disable L0s without affecting L1;
228 * don't wait for ICH L0s (ICH bug W/A)
229 */
230 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 231 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 232
233 /* Set FH wait threshold to maximum (HW error during stress W/A) */
234 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
235
236 /*
237 * Enable HAP INTA (interrupt from management bus) to
238 * wake device's PCI Express link L1a -> L0s
239 */
240 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 241 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 242
7afe3705 243 iwl_pcie_apm_config(trans);
a6c684ee
EG		 244
245 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 246 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 247 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 248 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 249
250 /*
251 * Set "initialization complete" bit to move adapter from
252 * D0U* --> D0A* (powered-up active) state.
253 */
254 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
255
256 /*
257 * Wait for clock stabilization; once stabilized, access to
258 * device-internal resources is supported, e.g. iwl_write_prph()
259 * and accesses to uCode SRAM.
260 */
261 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 262 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 264 if (ret < 0) {
265 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
266 goto out;
267 }
268
2d93aee1
EG		 269 if (trans->cfg->host_interrupt_operation_mode) {
270 /*
271 * This is a bit of an abuse - This is needed for 7260 / 3160
272 * only check host_interrupt_operation_mode even if this is
273 * not related to host_interrupt_operation_mode.
274 *
275 * Enable the oscillator to count wake up time for L1 exit. This
276 * consumes slightly more power (100uA) - but allows to be sure
277 * that we wake up from L1 on time.
278 *
279 * This looks weird: read twice the same register, discard the
280 * value, set a bit, and yet again, read that same register
281 * just to discard the value. But that's the way the hardware
282 * seems to like it.
283 */
284 iwl_read_prph(trans, OSC_CLK);
285 iwl_read_prph(trans, OSC_CLK);
286 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
287 iwl_read_prph(trans, OSC_CLK);
288 iwl_read_prph(trans, OSC_CLK);
289 }
290
a6c684ee
EG		 291 /*
292 * Enable DMA clock and wait for it to stabilize.
293 *
3073d8c0
EH		 294 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
295 * bits do not disable clocks. This preserves any hardware
296 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 297 */
3073d8c0
EH		 298 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
299 iwl_write_prph(trans, APMG_CLK_EN_REG,
300 APMG_CLK_VAL_DMA_CLK_RQT);
301 udelay(20);
302
303 /* Disable L1-Active */
304 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
305 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
306
307 /* Clear the interrupt in APMG if the NIC is in RFKILL */
308 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
309 APMG_RTC_INT_STT_RFKILL);
310 }
889b1696 311
eb7ff77e 312 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 313
314out:
315 return ret;
316}
317
a812cba9
AB		 318/*
319 * Enable LP XTAL to avoid HW bug where device may consume much power if
320 * FW is not loaded after device reset. LP XTAL is disabled by default
321 * after device HW reset. Do it only if XTAL is fed by internal source.
322 * Configure device's "persistence" mode to avoid resetting XTAL again when
323 * SHRD_HW_RST occurs in S3.
324 */
325static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
326{
327 int ret;
328 u32 apmg_gp1_reg;
329 u32 apmg_xtal_cfg_reg;
330 u32 dl_cfg_reg;
331
332 /* Force XTAL ON */
333 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
334 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
335
336 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
337 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
338
339 udelay(10);
340
341 /*
342 * Set "initialization complete" bit to move adapter from
343 * D0U* --> D0A* (powered-up active) state.
344 */
345 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
346
347 /*
348 * Wait for clock stabilization; once stabilized, access to
349 * device-internal resources is possible.
350 */
351 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
352 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 25000);
355 if (WARN_ON(ret < 0)) {
356 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
357 /* Release XTAL ON request */
358 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360 return;
361 }
362
363 /*
364 * Clear "disable persistence" to avoid LP XTAL resetting when
365 * SHRD_HW_RST is applied in S3.
366 */
367 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
368 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
369
370 /*
371 * Force APMG XTAL to be active to prevent its disabling by HW
372 * caused by APMG idle state.
373 */
374 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
375 SHR_APMG_XTAL_CFG_REG);
376 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
377 apmg_xtal_cfg_reg |
378 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
379
380 /*
381 * Reset entire device again - do controller reset (results in
382 * SHRD_HW_RST). Turn MAC off before proceeding.
383 */
384 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
385
386 udelay(10);
387
388 /* Enable LP XTAL by indirect access through CSR */
389 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
390 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
391 SHR_APMG_GP1_WF_XTAL_LP_EN |
392 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
393
394 /* Clear delay line clock power up */
395 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
396 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
397 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
398
399 /*
400 * Enable persistence mode to avoid LP XTAL resetting when
401 * SHRD_HW_RST is applied in S3.
402 */
403 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
404 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
405
406 /*
407 * Clear "initialization complete" bit to move adapter from
408 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
409 */
410 iwl_clear_bit(trans, CSR_GP_CNTRL,
411 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
412
413 /* Activates XTAL resources monitor */
414 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
415 CSR_MONITOR_XTAL_RESOURCES);
416
417 /* Release XTAL ON request */
418 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
419 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
420 udelay(10);
421
422 /* Release APMG XTAL */
423 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
424 apmg_xtal_cfg_reg &
425 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
426}
427
7afe3705 428static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 429{
430 int ret = 0;
431
432 /* stop device's busmaster DMA activity */
433 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
434
435 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 436 CSR_RESET_REG_FLAG_MASTER_DISABLED,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 438 if (ret < 0)
cc56feb2
EG		 439 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
440
441 IWL_DEBUG_INFO(trans, "stop master\n");
442
443 return ret;
444}
445
b7aaeae4 446static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 447{
448 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
449
b7aaeae4
EG		 450 if (op_mode_leave) {
451 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
452 iwl_pcie_apm_init(trans);
453
454 /* inform ME that we are leaving */
455 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
456 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
457 APMG_PCIDEV_STT_VAL_WAKE_ME);
458 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
459 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
460 CSR_HW_IF_CONFIG_REG_PREPARE |
461 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
462 mdelay(5);
463 }
464
eb7ff77e 465 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 466
467 /* Stop device's DMA activity */
7afe3705 468 iwl_pcie_apm_stop_master(trans);
cc56feb2 469
a812cba9
AB		 470 if (trans->cfg->lp_xtal_workaround) {
471 iwl_pcie_apm_lp_xtal_enable(trans);
472 return;
473 }
474
cc56feb2
EG		 475 /* Reset the entire device */
476 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
477
478 udelay(10);
479
480 /*
481 * Clear "initialization complete" bit to move adapter from
482 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
483 */
484 iwl_clear_bit(trans, CSR_GP_CNTRL,
485 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
486}
487
7afe3705 488static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 489{
7b11488f 490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 491
492 /* nic_init */
7b70bd63 493 spin_lock(&trans_pcie->irq_lock);
7afe3705 494 iwl_pcie_apm_init(trans);
392f8b78 495
7b70bd63 496 spin_unlock(&trans_pcie->irq_lock);
392f8b78 497
3073d8c0
EH		 498 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
499 iwl_pcie_set_pwr(trans, false);
392f8b78 500
ecdb975c 501 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 502
503 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 504 iwl_pcie_rx_init(trans);
392f8b78
EG		 505
506 /* Allocate or reset and init all Tx and Command queues */
f02831be 507 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 508 return -ENOMEM;
509
035f7ff2 510 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 511 /* enable shadow regs in HW */
20d3b647 512 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 513 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 514 }
515
392f8b78
EG		 516 return 0;
517}
518
519#define HW_READY_TIMEOUT (50)
520
521/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 522static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 523{
524 int ret;
525
1042db2a 526 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 527 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 528
529 /* See if we got it */
1042db2a 530 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 531 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
532 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
533 HW_READY_TIMEOUT);
392f8b78 534
6a08f514
EG		 535 if (ret >= 0)
536 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
537
6d8f6eeb 538 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 539 return ret;
540}
541
542/* Note: returns standard 0/-ERROR code */
7afe3705 543static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 544{
545 int ret;
289e5501 546 int t = 0;
501fd989 547 int iter;
392f8b78 548
6d8f6eeb 549 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 550
7afe3705 551 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 552 /* If the card is ready, exit 0 */
392f8b78
EG		 553 if (ret >= 0)
554 return 0;
555
501fd989
EG		 556 for (iter = 0; iter < 10; iter++) {
557 /* If HW is not ready, prepare the conditions to check again */
558 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
559 CSR_HW_IF_CONFIG_REG_PREPARE);
560
561 do {
562 ret = iwl_pcie_set_hw_ready(trans);
563 if (ret >= 0)
564 return 0;
392f8b78 565
501fd989
EG		 566 usleep_range(200, 1000);
567 t += 200;
568 } while (t < 150000);
569 msleep(25);
570 }
392f8b78 571
7f2ac8fb 572 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 573
392f8b78
EG		 574 return ret;
575}
576
cf614297
EG		 577/*
578 * ucode
579 */
7afe3705 580static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 581 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 582{
13df1aab 583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 584 int ret;
585
13df1aab 586 trans_pcie->ucode_write_complete = false;
cf614297
EG		 587
588 iwl_write_direct32(trans,
20d3b647
JB		 589 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
590 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 591
592 iwl_write_direct32(trans,
20d3b647
JB		 593 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
594 dst_addr);
cf614297
EG		 595
596 iwl_write_direct32(trans,
83f84d7b
JB		 597 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
598 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 599
600 iwl_write_direct32(trans,
20d3b647
JB		 601 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
602 (iwl_get_dma_hi_addr(phy_addr)
603 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 604
605 iwl_write_direct32(trans,
20d3b647
JB		 606 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
607 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
608 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
609 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 610
611 iwl_write_direct32(trans,
20d3b647
JB		 612 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
613 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
614 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
615 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 616
13df1aab
JB		 617 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
618 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 619 if (!ret) {
83f84d7b 620 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 621 return -ETIMEDOUT;
622 }
623
624 return 0;
625}
626
7afe3705 627static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 628 const struct fw_desc *section)
cf614297 629{
83f84d7b
JB		 630 u8 *v_addr;
631 dma_addr_t p_addr;
baa21e83 632 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 633 int ret = 0;
634
83f84d7b
JB		 635 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
636 section_num);
637
c571573a
EG		 638 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
639 GFP_KERNEL | __GFP_NOWARN);
640 if (!v_addr) {
641 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
642 chunk_sz = PAGE_SIZE;
643 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
644 &p_addr, GFP_KERNEL);
645 if (!v_addr)
646 return -ENOMEM;
647 }
83f84d7b 648
c571573a 649 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 650 u32 copy_size, dst_addr;
651 bool extended_addr = false;
83f84d7b 652
c571573a 653 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 654 dst_addr = section->offset + offset;
655
656 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
657 dst_addr <= IWL_FW_MEM_EXTENDED_END)
658 extended_addr = true;
659
660 if (extended_addr)
661 iwl_set_bits_prph(trans, LMPM_CHICK,
662 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 663
83f84d7b 664 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 665 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
666 copy_size);
667
668 if (extended_addr)
669 iwl_clear_bits_prph(trans, LMPM_CHICK,
670 LMPM_CHICK_EXTENDED_ADDR_SPACE);
671
83f84d7b
JB		 672 if (ret) {
673 IWL_ERR(trans,
674 "Could not load the [%d] uCode section\n",
675 section_num);
676 break;
6dfa8d01 677 }
83f84d7b
JB		 678 }
679
c571573a 680 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 681 return ret;
682}
683
dcab8ecd
EH		 684static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
685 const struct fw_img *image,
686 int cpu,
687 int *first_ucode_section)
e2d6f4e7
EH		 688{
689 int shift_param;
dcab8ecd
EH		 690 int i, ret = 0, sec_num = 0x1;
691 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 692
693 if (cpu == 1) {
694 shift_param = 0;
034846cf 695 *first_ucode_section = 0;
e2d6f4e7
EH		 696 } else {
697 shift_param = 16;
034846cf 698 (*first_ucode_section)++;
e2d6f4e7
EH		 699 }
700
034846cf
EH		 701 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
702 last_read_idx = i;
703
704 if (!image->sec[i].data ||
705 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
706 IWL_DEBUG_FW(trans,
707 "Break since Data not valid or Empty section, sec = %d\n",
708 i);
189fa2fa 709 break;
034846cf
EH		 710 }
711
189fa2fa
EH		 712 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
713 if (ret)
714 return ret;
dcab8ecd
EH		 715
716 /* Notify the ucode of the loaded section number and status */
717 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
718 val = val | (sec_num << shift_param);
719 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
720 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 721 }
722
034846cf
EH		 723 *first_ucode_section = last_read_idx;
724
189fa2fa
EH		 725 return 0;
726}
e2d6f4e7 727
189fa2fa
EH		 728static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
729 const struct fw_img *image,
034846cf
EH		 730 int cpu,
731 int *first_ucode_section)
189fa2fa
EH		 732{
733 int shift_param;
189fa2fa 734 int i, ret = 0;
034846cf 735 u32 last_read_idx = 0;
189fa2fa
EH		 736
737 if (cpu == 1) {
738 shift_param = 0;
034846cf 739 *first_ucode_section = 0;
189fa2fa
EH		 740 } else {
741 shift_param = 16;
034846cf 742 (*first_ucode_section)++;
189fa2fa
EH		 743 }
744
034846cf
EH		 745 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
746 last_read_idx = i;
747
748 if (!image->sec[i].data ||
749 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
750 IWL_DEBUG_FW(trans,
751 "Break since Data not valid or Empty section, sec = %d\n",
752 i);
189fa2fa 753 break;
034846cf
EH		 754 }
755
189fa2fa
EH		 756 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
757 if (ret)
758 return ret;
e2d6f4e7
EH		 759 }
760
189fa2fa
EH		 761 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
762 iwl_set_bits_prph(trans,
763 CSR_UCODE_LOAD_STATUS_ADDR,
764 (LMPM_CPU_UCODE_LOADING_COMPLETED |
765 LMPM_CPU_HDRS_LOADING_COMPLETED |
766 LMPM_CPU_UCODE_LOADING_STARTED) <<
767 shift_param);
768
034846cf
EH		 769 *first_ucode_section = last_read_idx;
770
e2d6f4e7
EH		 771 return 0;
772}
773
09e350f7
LK		 774static void iwl_pcie_apply_destination(struct iwl_trans *trans)
775{
776 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
777 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
778 int i;
779
780 if (dest->version)
781 IWL_ERR(trans,
782 "DBG DEST version is %d - expect issues\n",
783 dest->version);
784
785 IWL_INFO(trans, "Applying debug destination %s\n",
786 get_fw_dbg_mode_string(dest->monitor_mode));
787
788 if (dest->monitor_mode == EXTERNAL_MODE)
789 iwl_pcie_alloc_fw_monitor(trans);
790 else
791 IWL_WARN(trans, "PCI should have external buffer debug\n");
792
793 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
794 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
795 u32 val = le32_to_cpu(dest->reg_ops[i].val);
796
797 switch (dest->reg_ops[i].op) {
798 case CSR_ASSIGN:
799 iwl_write32(trans, addr, val);
800 break;
801 case CSR_SETBIT:
802 iwl_set_bit(trans, addr, BIT(val));
803 break;
804 case CSR_CLEARBIT:
805 iwl_clear_bit(trans, addr, BIT(val));
806 break;
807 case PRPH_ASSIGN:
808 iwl_write_prph(trans, addr, val);
809 break;
810 case PRPH_SETBIT:
811 iwl_set_bits_prph(trans, addr, BIT(val));
812 break;
813 case PRPH_CLEARBIT:
814 iwl_clear_bits_prph(trans, addr, BIT(val));
815 break;
816 default:
817 IWL_ERR(trans, "FW debug - unknown OP %d\n",
818 dest->reg_ops[i].op);
819 break;
820 }
821 }
822
823 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
824 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
825 trans_pcie->fw_mon_phys >> dest->base_shift);
826 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
827 (trans_pcie->fw_mon_phys +
828 trans_pcie->fw_mon_size) >> dest->end_shift);
829 }
830}
831
7afe3705 832static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 833 const struct fw_img *image)
cf614297 834{
c2d20201 835 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 836 int ret = 0;
034846cf 837 int first_ucode_section;
cf614297 838
dcab8ecd 839 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 840 image->is_dual_cpus ? "Dual" : "Single");
841
dcab8ecd
EH		 842 /* load to FW the binary non secured sections of CPU1 */
843 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
844 if (ret)
845 return ret;
e2d6f4e7
EH		 846
847 if (image->is_dual_cpus) {
189fa2fa
EH		 848 /* set CPU2 header address */
849 iwl_write_prph(trans,
850 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
851 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 852
189fa2fa 853 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 854 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
855 &first_ucode_section);
189fa2fa
EH		 856 if (ret)
857 return ret;
e2d6f4e7 858 }
cf614297 859
c2d20201
EG		 860 /* supported for 7000 only for the moment */
861 if (iwlwifi_mod_params.fw_monitor &&
862 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
863 iwl_pcie_alloc_fw_monitor(trans);
864
865 if (trans_pcie->fw_mon_size) {
866 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
867 trans_pcie->fw_mon_phys >> 4);
868 iwl_write_prph(trans, MON_BUFF_END_ADDR,
869 (trans_pcie->fw_mon_phys +
870 trans_pcie->fw_mon_size) >> 4);
871 }
09e350f7
LK		 872 } else if (trans->dbg_dest_tlv) {
873 iwl_pcie_apply_destination(trans);
c2d20201
EG		 874 }
875
e12ba844
EH		 876 /* release CPU reset */
877 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
878 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
879 else
880 iwl_write32(trans, CSR_RESET, 0);
881
dcab8ecd
EH		 882 return 0;
883}
189fa2fa 884
dcab8ecd
EH		 885static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
886 const struct fw_img *image)
887{
888 int ret = 0;
889 int first_ucode_section;
890 u32 reg;
891
892 IWL_DEBUG_FW(trans, "working with %s CPU\n",
893 image->is_dual_cpus ? "Dual" : "Single");
894
895 /* configure the ucode to be ready to get the secured image */
896 /* release CPU reset */
897 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
898
899 /* load to FW the binary Secured sections of CPU1 */
900 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
901 &first_ucode_section);
902 if (ret)
903 return ret;
904
905 /* load to FW the binary sections of CPU2 */
906 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
907 &first_ucode_section);
908 if (ret)
909 return ret;
910
ff298624
EH		 911 if (trans->dbg_dest_tlv)
912 iwl_pcie_apply_destination(trans);
913
dcab8ecd
EH		 914 /* Notify FW loading is done */
915 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
916
917 /* wait for image verification to complete */
918 ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
919 LMPM_SECURE_BOOT_STATUS_SUCCESS,
920 LMPM_SECURE_BOOT_STATUS_SUCCESS,
921 LMPM_SECURE_TIME_OUT);
922 if (ret < 0) {
923 reg = iwl_read_prph(trans,
924 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
925
926 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
927 reg);
928 return ret;
189fa2fa
EH		 929 }
930
cf614297
EG		 931 return 0;
932}
933
0692fe41 934static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 935 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 936{
7616f334 937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78 938 int ret;
c9eec95c 939 bool hw_rfkill;
392f8b78 940
496bab39 941 /* This may fail if AMT took ownership of the device */
7afe3705 942 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 943 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 944 return -EIO;
945 }
946
8c46bb70
EG		 947 iwl_enable_rfkill_int(trans);
948
392f8b78 949 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 950 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 951 if (hw_rfkill)
eb7ff77e 952 set_bit(STATUS_RFKILL, &trans->status);
4620020b 953 else
eb7ff77e 954 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 955 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 956 if (hw_rfkill && !run_in_rfkill)
392f8b78 957 return -ERFKILL;
392f8b78 958
1042db2a 959 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 960
7afe3705 961 ret = iwl_pcie_nic_init(trans);
392f8b78 962 if (ret) {
6d8f6eeb 963 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 964 return ret;
965 }
966
7616f334
EP		 967 /* init ref_count to 1 (should be cleared when ucode is loaded) */
968 trans_pcie->ref_count = 1;
969
392f8b78 970 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 971 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
972 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 973 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
974
975 /* clear (again), then enable host interrupts */
1042db2a 976 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 977 iwl_enable_interrupts(trans);
392f8b78
EG		 978
979 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 980 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
981 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 982
cf614297 983 /* Load the given image to the HW */
dcab8ecd
EH		 984 if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
985 (CSR_HW_REV_STEP(trans->hw_rev) == SILICON_B_STEP))
986 return iwl_pcie_load_given_ucode_8000b(trans, fw);
987 else
988 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 989}
990
adca1235 991static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 992{
990aa6d7 993 iwl_pcie_reset_ict(trans);
f02831be 994 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 995}
996
43e58856 997static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 998{
43e58856 999 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1000 bool hw_rfkill, was_hw_rfkill;
1001
1002 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1003
43e58856 1004 /* tell the device to stop sending interrupts */
7b70bd63 1005 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1006 iwl_disable_interrupts(trans);
7b70bd63 1007 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1008
ab6cf8e8 1009 /* device going down, Stop using ICT table */
990aa6d7 1010 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1011
1012 /*
1013 * If a HW restart happens during firmware loading,
1014 * then the firmware loading might call this function
1015 * and later it might be called again due to the
1016 * restart. So don't process again if the device is
1017 * already dead.
1018 */
31b8b343
EG		 1019 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1020 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1021 iwl_pcie_tx_stop(trans);
9805c446 1022 iwl_pcie_rx_stop(trans);
6379103e 1023
ab6cf8e8 1024 /* Power-down device's busmaster DMA clocks */
1042db2a 1025 iwl_write_prph(trans, APMG_CLK_DIS_REG,
ab6cf8e8
EG		 1026 APMG_CLK_VAL_DMA_CLK_RQT);
1027 udelay(5);
1028 }
1029
1030 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1031 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1032 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1033
1034 /* Stop the device, and put it in low power state */
b7aaeae4 1035 iwl_pcie_apm_stop(trans, false);
43e58856 1036
03d6c3b0
EG		 1037 /* stop and reset the on-board processor */
1038 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1039 udelay(20);
1040
1041 /*
1042 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1043 * This is a bug in certain verions of the hardware.
1044 * Certain devices also keep sending HW RF kill interrupt all
1045 * the time, unless the interrupt is ACKed even if the interrupt
1046 * should be masked. Re-ACK all the interrupts here.
43e58856 1047 */
7b70bd63 1048 spin_lock(&trans_pcie->irq_lock);
43e58856 1049 iwl_disable_interrupts(trans);
7b70bd63 1050 spin_unlock(&trans_pcie->irq_lock);
43e58856 1051
74fda971
DF		 1052
1053 /* clear all status bits */
eb7ff77e
AN		 1054 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1055 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1056 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1057 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1058
1059 /*
1060 * Even if we stop the HW, we still want the RF kill
1061 * interrupt
1062 */
1063 iwl_enable_rfkill_int(trans);
1064
1065 /*
1066 * Check again since the RF kill state may have changed while
1067 * all the interrupts were disabled, in this case we couldn't
1068 * receive the RF kill interrupt and update the state in the
1069 * op_mode.
3dc3374f
EG		 1070 * Don't call the op_mode if the rkfill state hasn't changed.
1071 * This allows the op_mode to call stop_device from the rfkill
1072 * notification without endless recursion. Under very rare
1073 * circumstances, we might have a small recursion if the rfkill
1074 * state changed exactly now while we were called from stop_device.
1075 * This is very unlikely but can happen and is supported.
a4082843
AN		 1076 */
1077 hw_rfkill = iwl_is_rfkill_set(trans);
1078 if (hw_rfkill)
eb7ff77e 1079 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1080 else
eb7ff77e 1081 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1082 if (hw_rfkill != was_hw_rfkill)
14cfca71 1083 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1084
1085 /* re-take ownership to prevent other users from stealing the deivce */
1086 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1087}
1088
1089void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1090{
1091 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1092 iwl_trans_pcie_stop_device(trans);
ab6cf8e8
EG		 1093}
1094
debff618 1095static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1096{
2dd4f9f7 1097 iwl_disable_interrupts(trans);
debff618
JB		 1098
1099 /*
1100 * in testing mode, the host stays awake and the
1101 * hardware won't be reset (not even partially)
1102 */
1103 if (test)
1104 return;
1105
ddaf5a5b
JB		 1106 iwl_pcie_disable_ict(trans);
1107
2dd4f9f7
JB		 1108 iwl_clear_bit(trans, CSR_GP_CNTRL,
1109 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1110 iwl_clear_bit(trans, CSR_GP_CNTRL,
1111 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1112
1113 /*
1114 * reset TX queues -- some of their registers reset during S3
1115 * so if we don't reset everything here the D3 image would try
1116 * to execute some invalid memory upon resume
1117 */
1118 iwl_trans_pcie_tx_reset(trans);
1119
1120 iwl_pcie_set_pwr(trans, true);
1121}
1122
1123static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1124 enum iwl_d3_status *status,
1125 bool test)
ddaf5a5b
JB		 1126{
1127 u32 val;
1128 int ret;
1129
debff618
JB		 1130 if (test) {
1131 iwl_enable_interrupts(trans);
1132 *status = IWL_D3_STATUS_ALIVE;
1133 return 0;
1134 }
1135
ddaf5a5b
JB		 1136 /*
1137 * Also enables interrupts - none will happen as the device doesn't
1138 * know we're waking it up, only when the opmode actually tells it
1139 * after this call.
1140 */
1141 iwl_pcie_reset_ict(trans);
1142
1143 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1144 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1145
01e58a28
EG		 1146 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1147 udelay(2);
1148
ddaf5a5b
JB		 1149 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1150 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1151 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1152 25000);
7f2ac8fb 1153 if (ret < 0) {
ddaf5a5b
JB		 1154 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1155 return ret;
1156 }
1157
a3ead656
EG		 1158 iwl_pcie_set_pwr(trans, false);
1159
ddaf5a5b
JB		 1160 iwl_trans_pcie_tx_reset(trans);
1161
1162 ret = iwl_pcie_rx_init(trans);
1163 if (ret) {
1164 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1165 return ret;
1166 }
1167
a3ead656
EG		 1168 val = iwl_read32(trans, CSR_RESET);
1169 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1170 *status = IWL_D3_STATUS_RESET;
1171 else
1172 *status = IWL_D3_STATUS_ALIVE;
1173
ddaf5a5b 1174 return 0;
2dd4f9f7
JB		 1175}
1176
57a1dc89 1177static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
e6bb4c9c 1178{
c9eec95c 1179 bool hw_rfkill;
a8b691e6 1180 int err;
e6bb4c9c 1181
7afe3705 1182 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1183 if (err) {
d6f1c316 1184 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1185 return err;
ebb7678d 1186 }
a6c684ee 1187
2997494f 1188 /* Reset the entire device */
ce836c76 1189 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1190
1191 usleep_range(10, 15);
1192
7afe3705 1193 iwl_pcie_apm_init(trans);
a6c684ee 1194
226c02ca
EG		 1195 /* From now on, the op_mode will be kept updated about RF kill state */
1196 iwl_enable_rfkill_int(trans);
1197
8d425517 1198 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1199 if (hw_rfkill)
eb7ff77e 1200 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1201 else
eb7ff77e 1202 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1203 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1204
a8b691e6 1205 return 0;
e6bb4c9c
EG		 1206}
1207
a4082843 1208static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1209{
20d3b647 1210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1211
a4082843 1212 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1213 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1214 iwl_disable_interrupts(trans);
7b70bd63 1215 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1216
b7aaeae4 1217 iwl_pcie_apm_stop(trans, true);
cc56feb2 1218
7b70bd63 1219 spin_lock(&trans_pcie->irq_lock);
218733cf 1220 iwl_disable_interrupts(trans);
7b70bd63 1221 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1222
8d96bb61 1223 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1224}
1225
03905495
EG		 1226static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1227{
05f5b97e 1228 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1229}
1230
1231static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1232{
05f5b97e 1233 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1234}
1235
1236static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1237{
05f5b97e 1238 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1239}
1240
6a06b6c1
EG		 1241static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1242{
f9477c17
AP		 1243 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1244 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1245 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1246}
1247
1248static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1249 u32 val)
1250{
1251 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1252 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1253 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1254}
1255
f14d6b39
JB		 1256static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1257{
1258 WARN_ON(1);
1259 return 0;
1260}
1261
c6f600fc 1262static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1263 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1264{
1265 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1266
1267 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1268 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
d663ee73
JB		 1269 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1270 trans_pcie->n_no_reclaim_cmds = 0;
1271 else
1272 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1273 if (trans_pcie->n_no_reclaim_cmds)
1274 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1275 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1276
b2cf410c
JB		 1277 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1278 if (trans_pcie->rx_buf_size_8k)
1279 trans_pcie->rx_page_order = get_order(8 * 1024);
1280 else
1281 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8
JB		 1282
1283 trans_pcie->wd_timeout =
1284 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
d9fb6465
JB		 1285
1286 trans_pcie->command_names = trans_cfg->command_names;
046db346 1287 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1288 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39
JB		 1289
1290 /* Initialize NAPI here - it should be before registering to mac80211
1291 * in the opmode but after the HW struct is allocated.
1292 * As this function may be called again in some corner cases don't
1293 * do anything if NAPI was already initialized.
1294 */
1295 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1296 init_dummy_netdev(&trans_pcie->napi_dev);
1297 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1298 &trans_pcie->napi_dev,
1299 iwl_pcie_dummy_napi_poll, 64);
1300 }
c6f600fc
MV		 1301}
1302
d1ff5253 1303void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1304{
20d3b647 1305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1306
0aa86df6 1307 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1308
f02831be 1309 iwl_pcie_tx_free(trans);
9805c446 1310 iwl_pcie_rx_free(trans);
6379103e 1311
a8b691e6
JB		 1312 free_irq(trans_pcie->pci_dev->irq, trans);
1313 iwl_pcie_free_ict(trans);
a42a1844
EG		 1314
1315 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1316 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1317 pci_release_regions(trans_pcie->pci_dev);
1318 pci_disable_device(trans_pcie->pci_dev);
59c647b6 1319 kmem_cache_destroy(trans->dev_cmd_pool);
a42a1844 1320
f14d6b39
JB		 1321 if (trans_pcie->napi.poll)
1322 netif_napi_del(&trans_pcie->napi);
1323
c2d20201
EG		 1324 iwl_pcie_free_fw_monitor(trans);
1325
6d8f6eeb 1326 kfree(trans);
34c1b7ba
EG		 1327}
1328
47107e84
DF		 1329static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1330{
47107e84 1331 if (state)
eb7ff77e 1332 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1333 else
eb7ff77e 1334 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1335}
1336
e56b04ef
LE		 1337static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1338 unsigned long *flags)
7a65d170
EG		 1339{
1340 int ret;
cfb4e624
JB		 1341 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1342
1343 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1344
b9439491
EG		 1345 if (trans_pcie->cmd_in_flight)
1346 goto out;
1347
7a65d170 1348 /* this bit wakes up the NIC */
e139dc4a
LE		 1349 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1350 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1351 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1352 udelay(2);
7a65d170
EG		 1353
1354 /*
1355 * These bits say the device is running, and should keep running for
1356 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1357 * but they do not indicate that embedded SRAM is restored yet;
1358 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1359 * to/from host DRAM when sleeping/waking for power-saving.
1360 * Each direction takes approximately 1/4 millisecond; with this
1361 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1362 * series of register accesses are expected (e.g. reading Event Log),
1363 * to keep device from sleeping.
1364 *
1365 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1366 * SRAM is okay/restored. We don't check that here because this call
1367 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1368 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1369 *
1370 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1371 * and do not save/restore SRAM when power cycling.
1372 */
1373 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1374 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1375 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1376 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1377 if (unlikely(ret < 0)) {
1378 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1379 if (!silent) {
1380 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1381 WARN_ONCE(1,
1382 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1383 val);
cfb4e624 1384 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1385 return false;
1386 }
1387 }
1388
b9439491 1389out:
e56b04ef
LE		 1390 /*
1391 * Fool sparse by faking we release the lock - sparse will
1392 * track nic_access anyway.
1393 */
cfb4e624 1394 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1395 return true;
1396}
1397
e56b04ef
LE		 1398static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1399 unsigned long *flags)
7a65d170 1400{
cfb4e624 1401 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1402
cfb4e624 1403 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1404
1405 /*
1406 * Fool sparse by faking we acquiring the lock - sparse will
1407 * track nic_access anyway.
1408 */
cfb4e624 1409 __acquire(&trans_pcie->reg_lock);
e56b04ef 1410
b9439491
EG		 1411 if (trans_pcie->cmd_in_flight)
1412 goto out;
1413
e139dc4a
LE		 1414 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1415 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1416 /*
1417 * Above we read the CSR_GP_CNTRL register, which will flush
1418 * any previous writes, but we need the write that clears the
1419 * MAC_ACCESS_REQ bit to be performed before any other writes
1420 * scheduled on different CPUs (after we drop reg_lock).
1421 */
1422 mmiowb();
b9439491 1423out:
cfb4e624 1424 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1425}
1426
4fd442db
EG		 1427static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1428 void *buf, int dwords)
1429{
1430 unsigned long flags;
1431 int offs, ret = 0;
1432 u32 *vals = buf;
1433
e56b04ef 1434 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1435 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1436 for (offs = 0; offs < dwords; offs++)
1437 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1438 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1439 } else {
1440 ret = -EBUSY;
1441 }
4fd442db
EG		 1442 return ret;
1443}
1444
1445static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1446 const void *buf, int dwords)
4fd442db
EG		 1447{
1448 unsigned long flags;
1449 int offs, ret = 0;
bf0fd5da 1450 const u32 *vals = buf;
4fd442db 1451
e56b04ef 1452 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1453 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1454 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1455 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1456 vals ? vals[offs] : 0);
e56b04ef 1457 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1458 } else {
1459 ret = -EBUSY;
1460 }
4fd442db
EG		 1461 return ret;
1462}
7a65d170 1463
5f178cd2
EG		 1464#define IWL_FLUSH_WAIT_MS 2000
1465
3cafdbe6 1466static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1467{
8ad71bef 1468 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1469 struct iwl_txq *txq;
5f178cd2
EG		 1470 struct iwl_queue *q;
1471 int cnt;
1472 unsigned long now = jiffies;
1c3fea82
EG		 1473 u32 scd_sram_addr;
1474 u8 buf[16];
5f178cd2
EG		 1475 int ret = 0;
1476
1477 /* waiting for all the tx frames complete might take a while */
035f7ff2 1478 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1479 u8 wr_ptr;
1480
9ba1947a 1481 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1482 continue;
3cafdbe6
EG		 1483 if (!test_bit(cnt, trans_pcie->queue_used))
1484 continue;
1485 if (!(BIT(cnt) & txq_bm))
1486 continue;
748fa67c
EG		 1487
1488 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1489 txq = &trans_pcie->txq[cnt];
5f178cd2 1490 q = &txq->q;
fa1a91fd
EG		 1491 wr_ptr = ACCESS_ONCE(q->write_ptr);
1492
1493 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1494 !time_after(jiffies,
1495 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1496 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1497
1498 if (WARN_ONCE(wr_ptr != write_ptr,
1499 "WR pointer moved while flushing %d -> %d\n",
1500 wr_ptr, write_ptr))
1501 return -ETIMEDOUT;
5f178cd2 1502 msleep(1);
fa1a91fd 1503 }
5f178cd2
EG		 1504
1505 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1506 IWL_ERR(trans,
1507 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1508 ret = -ETIMEDOUT;
1509 break;
1510 }
748fa67c 1511 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1512 }
1c3fea82
EG		 1513
1514 if (!ret)
1515 return 0;
1516
1517 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1518 txq->q.read_ptr, txq->q.write_ptr);
1519
1520 scd_sram_addr = trans_pcie->scd_base_addr +
1521 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1522 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1523
1524 iwl_print_hex_error(trans, buf, sizeof(buf));
1525
1526 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1527 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1528 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1529
1530 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1531 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1532 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1533 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1534 u32 tbl_dw =
1535 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1536 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1537
1538 if (cnt & 0x1)
1539 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1540 else
1541 tbl_dw = tbl_dw & 0x0000FFFF;
1542
1543 IWL_ERR(trans,
1544 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1545 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1546 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1547 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1548 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1549 }
1550
5f178cd2
EG		 1551 return ret;
1552}
1553
e139dc4a
LE		 1554static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1555 u32 mask, u32 value)
1556{
e56b04ef 1557 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1558 unsigned long flags;
1559
e56b04ef 1560 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1561 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1562 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1563}
1564
7616f334
EP		 1565void iwl_trans_pcie_ref(struct iwl_trans *trans)
1566{
1567 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1568 unsigned long flags;
1569
1570 if (iwlwifi_mod_params.d0i3_disable)
1571 return;
1572
1573 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1574 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1575 trans_pcie->ref_count++;
1576 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1577}
1578
1579void iwl_trans_pcie_unref(struct iwl_trans *trans)
1580{
1581 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1582 unsigned long flags;
1583
1584 if (iwlwifi_mod_params.d0i3_disable)
1585 return;
1586
1587 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1588 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1589 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1590 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1591 return;
1592 }
1593 trans_pcie->ref_count--;
1594 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1595}
1596
ff620849
EG		 1597static const char *get_csr_string(int cmd)
1598{
d9fb6465 1599#define IWL_CMD(x) case x: return #x
ff620849
EG		 1600 switch (cmd) {
1601 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1602 IWL_CMD(CSR_INT_COALESCING);
1603 IWL_CMD(CSR_INT);
1604 IWL_CMD(CSR_INT_MASK);
1605 IWL_CMD(CSR_FH_INT_STATUS);
1606 IWL_CMD(CSR_GPIO_IN);
1607 IWL_CMD(CSR_RESET);
1608 IWL_CMD(CSR_GP_CNTRL);
1609 IWL_CMD(CSR_HW_REV);
1610 IWL_CMD(CSR_EEPROM_REG);
1611 IWL_CMD(CSR_EEPROM_GP);
1612 IWL_CMD(CSR_OTP_GP_REG);
1613 IWL_CMD(CSR_GIO_REG);
1614 IWL_CMD(CSR_GP_UCODE_REG);
1615 IWL_CMD(CSR_GP_DRIVER_REG);
1616 IWL_CMD(CSR_UCODE_DRV_GP1);
1617 IWL_CMD(CSR_UCODE_DRV_GP2);
1618 IWL_CMD(CSR_LED_REG);
1619 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1620 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1621 IWL_CMD(CSR_ANA_PLL_CFG);
1622 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1623 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1624 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1625 default:
1626 return "UNKNOWN";
1627 }
d9fb6465 1628#undef IWL_CMD
ff620849
EG		 1629}
1630
990aa6d7 1631void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1632{
1633 int i;
1634 static const u32 csr_tbl[] = {
1635 CSR_HW_IF_CONFIG_REG,
1636 CSR_INT_COALESCING,
1637 CSR_INT,
1638 CSR_INT_MASK,
1639 CSR_FH_INT_STATUS,
1640 CSR_GPIO_IN,
1641 CSR_RESET,
1642 CSR_GP_CNTRL,
1643 CSR_HW_REV,
1644 CSR_EEPROM_REG,
1645 CSR_EEPROM_GP,
1646 CSR_OTP_GP_REG,
1647 CSR_GIO_REG,
1648 CSR_GP_UCODE_REG,
1649 CSR_GP_DRIVER_REG,
1650 CSR_UCODE_DRV_GP1,
1651 CSR_UCODE_DRV_GP2,
1652 CSR_LED_REG,
1653 CSR_DRAM_INT_TBL_REG,
1654 CSR_GIO_CHICKEN_BITS,
1655 CSR_ANA_PLL_CFG,
a812cba9 1656 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1657 CSR_HW_REV_WA_REG,
1658 CSR_DBG_HPET_MEM_REG
1659 };
1660 IWL_ERR(trans, "CSR values:\n");
1661 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1662 "CSR_INT_PERIODIC_REG)\n");
1663 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1664 IWL_ERR(trans, " %25s: 0X%08x\n",
1665 get_csr_string(csr_tbl[i]),
1042db2a 1666 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1667 }
1668}
1669
87e5666c
EG		 1670#ifdef CONFIG_IWLWIFI_DEBUGFS
1671/* create and remove of files */
1672#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1673 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1674 &iwl_dbgfs_##name##_ops)) \
9da987ac 1675 goto err; \
87e5666c
EG		 1676} while (0)
1677
1678/* file operation */
87e5666c 1679#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1680static const struct file_operations iwl_dbgfs_##name##_ops = { \
1681 .read = iwl_dbgfs_##name##_read, \
234e3405 1682 .open = simple_open, \
87e5666c
EG		 1683 .llseek = generic_file_llseek, \
1684};
1685
16db88ba 1686#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1687static const struct file_operations iwl_dbgfs_##name##_ops = { \
1688 .write = iwl_dbgfs_##name##_write, \
234e3405 1689 .open = simple_open, \
16db88ba
EG		 1690 .llseek = generic_file_llseek, \
1691};
1692
87e5666c 1693#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1694static const struct file_operations iwl_dbgfs_##name##_ops = { \
1695 .write = iwl_dbgfs_##name##_write, \
1696 .read = iwl_dbgfs_##name##_read, \
234e3405 1697 .open = simple_open, \
87e5666c
EG		 1698 .llseek = generic_file_llseek, \
1699};
1700
87e5666c 1701static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1702 char __user *user_buf,
1703 size_t count, loff_t *ppos)
8ad71bef 1704{
5a878bf6 1705 struct iwl_trans *trans = file->private_data;
8ad71bef 1706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1707 struct iwl_txq *txq;
87e5666c
EG		 1708 struct iwl_queue *q;
1709 char *buf;
1710 int pos = 0;
1711 int cnt;
1712 int ret;
1745e440
WYG		 1713 size_t bufsz;
1714
035f7ff2 1715 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
87e5666c 1716
f9e75447 1717 if (!trans_pcie->txq)
87e5666c 1718 return -EAGAIN;
f9e75447 1719
87e5666c
EG		 1720 buf = kzalloc(bufsz, GFP_KERNEL);
1721 if (!buf)
1722 return -ENOMEM;
1723
035f7ff2 1724 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1725 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1726 q = &txq->q;
1727 pos += scnprintf(buf + pos, bufsz - pos,
f40faf62 1728 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
87e5666c 1729 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1730 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62
AL		 1731 !!test_bit(cnt, trans_pcie->queue_stopped),
1732 txq->need_update,
1733 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1734 }
1735 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1736 kfree(buf);
1737 return ret;
1738}
1739
1740static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1741 char __user *user_buf,
1742 size_t count, loff_t *ppos)
1743{
5a878bf6 1744 struct iwl_trans *trans = file->private_data;
20d3b647 1745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1746 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1747 char buf[256];
1748 int pos = 0;
1749 const size_t bufsz = sizeof(buf);
1750
1751 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1752 rxq->read);
1753 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1754 rxq->write);
f40faf62
AL		 1755 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1756 rxq->write_actual);
1757 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1758 rxq->need_update);
87e5666c
EG		 1759 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1760 rxq->free_count);
1761 if (rxq->rb_stts) {
1762 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1763 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1764 } else {
1765 pos += scnprintf(buf + pos, bufsz - pos,
1766 "closed_rb_num: Not Allocated\n");
1767 }
1768 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1769}
1770
1f7b6172
EG		 1771static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1772 char __user *user_buf,
20d3b647
JB		 1773 size_t count, loff_t *ppos)
1774{
1f7b6172 1775 struct iwl_trans *trans = file->private_data;
20d3b647 1776 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1777 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1778
1779 int pos = 0;
1780 char *buf;
1781 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1782 ssize_t ret;
1783
1784 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1785 if (!buf)
1f7b6172 1786 return -ENOMEM;
1f7b6172
EG		 1787
1788 pos += scnprintf(buf + pos, bufsz - pos,
1789 "Interrupt Statistics Report:\n");
1790
1791 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1792 isr_stats->hw);
1793 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1794 isr_stats->sw);
1795 if (isr_stats->sw || isr_stats->hw) {
1796 pos += scnprintf(buf + pos, bufsz - pos,
1797 "\tLast Restarting Code: 0x%X\n",
1798 isr_stats->err_code);
1799 }
1800#ifdef CONFIG_IWLWIFI_DEBUG
1801 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1802 isr_stats->sch);
1803 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1804 isr_stats->alive);
1805#endif
1806 pos += scnprintf(buf + pos, bufsz - pos,
1807 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1808
1809 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1810 isr_stats->ctkill);
1811
1812 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1813 isr_stats->wakeup);
1814
1815 pos += scnprintf(buf + pos, bufsz - pos,
1816 "Rx command responses:\t\t %u\n", isr_stats->rx);
1817
1818 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1819 isr_stats->tx);
1820
1821 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1822 isr_stats->unhandled);
1823
1824 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1825 kfree(buf);
1826 return ret;
1827}
1828
1829static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1830 const char __user *user_buf,
1831 size_t count, loff_t *ppos)
1832{
1833 struct iwl_trans *trans = file->private_data;
20d3b647 1834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1835 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1836
1837 char buf[8];
1838 int buf_size;
1839 u32 reset_flag;
1840
1841 memset(buf, 0, sizeof(buf));
1842 buf_size = min(count, sizeof(buf) - 1);
1843 if (copy_from_user(buf, user_buf, buf_size))
1844 return -EFAULT;
1845 if (sscanf(buf, "%x", &reset_flag) != 1)
1846 return -EFAULT;
1847 if (reset_flag == 0)
1848 memset(isr_stats, 0, sizeof(*isr_stats));
1849
1850 return count;
1851}
1852
16db88ba 1853static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1854 const char __user *user_buf,
1855 size_t count, loff_t *ppos)
16db88ba
EG		 1856{
1857 struct iwl_trans *trans = file->private_data;
1858 char buf[8];
1859 int buf_size;
1860 int csr;
1861
1862 memset(buf, 0, sizeof(buf));
1863 buf_size = min(count, sizeof(buf) - 1);
1864 if (copy_from_user(buf, user_buf, buf_size))
1865 return -EFAULT;
1866 if (sscanf(buf, "%d", &csr) != 1)
1867 return -EFAULT;
1868
990aa6d7 1869 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1870
1871 return count;
1872}
1873
16db88ba 1874static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1875 char __user *user_buf,
1876 size_t count, loff_t *ppos)
16db88ba
EG		 1877{
1878 struct iwl_trans *trans = file->private_data;
94543a8d 1879 char *buf = NULL;
56c2477f 1880 ssize_t ret;
16db88ba 1881
56c2477f
JB		 1882 ret = iwl_dump_fh(trans, &buf);
1883 if (ret < 0)
1884 return ret;
1885 if (!buf)
1886 return -EINVAL;
1887 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1888 kfree(buf);
16db88ba
EG		 1889 return ret;
1890}
1891
1f7b6172 1892DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1893DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1894DEBUGFS_READ_FILE_OPS(rx_queue);
1895DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1896DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 1897
1898/*
1899 * Create the debugfs files and directories
1900 *
1901 */
1902static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 1903 struct dentry *dir)
87e5666c 1904{
87e5666c
EG		 1905 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1906 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 1907 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 1908 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1909 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 1910 return 0;
9da987ac
MV		 1911
1912err:
1913 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1914 return -ENOMEM;
87e5666c 1915}
aadede6e
JB		 1916#else
1917static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1918 struct dentry *dir)
1919{
1920 return 0;
1921}
1922#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 1923
1924static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1925{
1926 u32 cmdlen = 0;
1927 int i;
1928
1929 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1930 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1931
1932 return cmdlen;
1933}
1934
67c65f2c
EG		 1935static const struct {
1936 u32 start, end;
1937} iwl_prph_dump_addr[] = {
1938 { .start = 0x00a00000, .end = 0x00a00000 },
1939 { .start = 0x00a0000c, .end = 0x00a00024 },
1940 { .start = 0x00a0002c, .end = 0x00a0003c },
1941 { .start = 0x00a00410, .end = 0x00a00418 },
1942 { .start = 0x00a00420, .end = 0x00a00420 },
1943 { .start = 0x00a00428, .end = 0x00a00428 },
1944 { .start = 0x00a00430, .end = 0x00a0043c },
1945 { .start = 0x00a00444, .end = 0x00a00444 },
1946 { .start = 0x00a004c0, .end = 0x00a004cc },
1947 { .start = 0x00a004d8, .end = 0x00a004d8 },
1948 { .start = 0x00a004e0, .end = 0x00a004f0 },
1949 { .start = 0x00a00840, .end = 0x00a00840 },
1950 { .start = 0x00a00850, .end = 0x00a00858 },
1951 { .start = 0x00a01004, .end = 0x00a01008 },
1952 { .start = 0x00a01010, .end = 0x00a01010 },
1953 { .start = 0x00a01018, .end = 0x00a01018 },
1954 { .start = 0x00a01024, .end = 0x00a01024 },
1955 { .start = 0x00a0102c, .end = 0x00a01034 },
1956 { .start = 0x00a0103c, .end = 0x00a01040 },
1957 { .start = 0x00a01048, .end = 0x00a01094 },
1958 { .start = 0x00a01c00, .end = 0x00a01c20 },
1959 { .start = 0x00a01c58, .end = 0x00a01c58 },
1960 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1961 { .start = 0x00a01c28, .end = 0x00a01c54 },
1962 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1963 { .start = 0x00a01c84, .end = 0x00a01c84 },
1964 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1965 { .start = 0x00a01d18, .end = 0x00a01d20 },
1966 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1967 { .start = 0x00a01d40, .end = 0x00a01d5c },
1968 { .start = 0x00a01d80, .end = 0x00a01d80 },
1969 { .start = 0x00a01d98, .end = 0x00a01d98 },
1970 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1971 { .start = 0x00a01e00, .end = 0x00a01e2c },
1972 { .start = 0x00a01e40, .end = 0x00a01e60 },
1973 { .start = 0x00a01e84, .end = 0x00a01e90 },
1974 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1975 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1976 { .start = 0x00a01f00, .end = 0x00a01f14 },
1977 { .start = 0x00a01f44, .end = 0x00a01f58 },
1978 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1979 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1980 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1981 { .start = 0x00a02000, .end = 0x00a02048 },
1982 { .start = 0x00a02068, .end = 0x00a020f0 },
1983 { .start = 0x00a02100, .end = 0x00a02118 },
1984 { .start = 0x00a02140, .end = 0x00a0214c },
1985 { .start = 0x00a02168, .end = 0x00a0218c },
1986 { .start = 0x00a021c0, .end = 0x00a021c0 },
1987 { .start = 0x00a02400, .end = 0x00a02410 },
1988 { .start = 0x00a02418, .end = 0x00a02420 },
1989 { .start = 0x00a02428, .end = 0x00a0242c },
1990 { .start = 0x00a02434, .end = 0x00a02434 },
1991 { .start = 0x00a02440, .end = 0x00a02460 },
1992 { .start = 0x00a02468, .end = 0x00a024b0 },
1993 { .start = 0x00a024c8, .end = 0x00a024cc },
1994 { .start = 0x00a02500, .end = 0x00a02504 },
1995 { .start = 0x00a0250c, .end = 0x00a02510 },
1996 { .start = 0x00a02540, .end = 0x00a02554 },
1997 { .start = 0x00a02580, .end = 0x00a025f4 },
1998 { .start = 0x00a02600, .end = 0x00a0260c },
1999 { .start = 0x00a02648, .end = 0x00a02650 },
2000 { .start = 0x00a02680, .end = 0x00a02680 },
2001 { .start = 0x00a026c0, .end = 0x00a026d0 },
2002 { .start = 0x00a02700, .end = 0x00a0270c },
2003 { .start = 0x00a02804, .end = 0x00a02804 },
2004 { .start = 0x00a02818, .end = 0x00a0281c },
2005 { .start = 0x00a02c00, .end = 0x00a02db4 },
2006 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2007 { .start = 0x00a03000, .end = 0x00a03014 },
2008 { .start = 0x00a0301c, .end = 0x00a0302c },
2009 { .start = 0x00a03034, .end = 0x00a03038 },
2010 { .start = 0x00a03040, .end = 0x00a03048 },
2011 { .start = 0x00a03060, .end = 0x00a03068 },
2012 { .start = 0x00a03070, .end = 0x00a03074 },
2013 { .start = 0x00a0307c, .end = 0x00a0307c },
2014 { .start = 0x00a03080, .end = 0x00a03084 },
2015 { .start = 0x00a0308c, .end = 0x00a03090 },
2016 { .start = 0x00a03098, .end = 0x00a03098 },
2017 { .start = 0x00a030a0, .end = 0x00a030a0 },
2018 { .start = 0x00a030a8, .end = 0x00a030b4 },
2019 { .start = 0x00a030bc, .end = 0x00a030bc },
2020 { .start = 0x00a030c0, .end = 0x00a0312c },
2021 { .start = 0x00a03c00, .end = 0x00a03c5c },
2022 { .start = 0x00a04400, .end = 0x00a04454 },
2023 { .start = 0x00a04460, .end = 0x00a04474 },
2024 { .start = 0x00a044c0, .end = 0x00a044ec },
2025 { .start = 0x00a04500, .end = 0x00a04504 },
2026 { .start = 0x00a04510, .end = 0x00a04538 },
2027 { .start = 0x00a04540, .end = 0x00a04548 },
2028 { .start = 0x00a04560, .end = 0x00a0457c },
2029 { .start = 0x00a04590, .end = 0x00a04598 },
2030 { .start = 0x00a045c0, .end = 0x00a045f4 },
2031};
2032
2033static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2034 struct iwl_fw_error_dump_data **data)
2035{
2036 struct iwl_fw_error_dump_prph *prph;
2037 unsigned long flags;
2038 u32 prph_len = 0, i;
2039
2040 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2041 return 0;
2042
2043 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2044 /* The range includes both boundaries */
2045 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2046 iwl_prph_dump_addr[i].start + 4;
2047 int reg;
2048 __le32 *val;
2049
87dd634a 2050 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2051
2052 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2053 (*data)->len = cpu_to_le32(sizeof(*prph) +
2054 num_bytes_in_chunk);
2055 prph = (void *)(*data)->data;
2056 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2057 val = (void *)prph->data;
2058
2059 for (reg = iwl_prph_dump_addr[i].start;
2060 reg <= iwl_prph_dump_addr[i].end;
2061 reg += 4)
2062 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2063 reg));
2064 *data = iwl_fw_error_next_data(*data);
2065 }
2066
2067 iwl_trans_release_nic_access(trans, &flags);
2068
2069 return prph_len;
2070}
2071
473ad712
EG		 2072#define IWL_CSR_TO_DUMP (0x250)
2073
2074static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2075 struct iwl_fw_error_dump_data **data)
2076{
2077 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2078 __le32 *val;
2079 int i;
2080
2081 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2082 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2083 val = (void *)(*data)->data;
2084
2085 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2086 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2087
2088 *data = iwl_fw_error_next_data(*data);
2089
2090 return csr_len;
2091}
2092
06d51e0d
LK		 2093static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2094 struct iwl_fw_error_dump_data **data)
2095{
2096 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2097 unsigned long flags;
2098 __le32 *val;
2099 int i;
2100
2101 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2102 return 0;
2103
2104 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2105 (*data)->len = cpu_to_le32(fh_regs_len);
2106 val = (void *)(*data)->data;
2107
2108 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2109 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2110
2111 iwl_trans_release_nic_access(trans, &flags);
2112
2113 *data = iwl_fw_error_next_data(*data);
2114
2115 return sizeof(**data) + fh_regs_len;
2116}
2117
48eb7b34
EG		 2118static
2119struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2120{
2121 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2122 struct iwl_fw_error_dump_data *data;
2123 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2124 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2125 struct iwl_trans_dump_data *dump_data;
4d075007 2126 u32 len;
99684ae3 2127 u32 monitor_len;
4d075007
JB		 2128 int i, ptr;
2129
473ad712
EG		 2130 /* transport dump header */
2131 len = sizeof(*dump_data);
2132
2133 /* host commands */
2134 len += sizeof(*data) +
c2d20201
EG		 2135 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2136
473ad712
EG		 2137 /* CSR registers */
2138 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2139
2140 /* PRPH registers */
67c65f2c
EG		 2141 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2142 /* The range includes both boundaries */
2143 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2144 iwl_prph_dump_addr[i].start + 4;
2145
2146 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2147 num_bytes_in_chunk;
2148 }
2149
06d51e0d
LK		 2150 /* FH registers */
2151 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2152
473ad712 2153 /* FW monitor */
99684ae3 2154 if (trans_pcie->fw_mon_page) {
c544e9c4 2155 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2156 trans_pcie->fw_mon_size;
2157 monitor_len = trans_pcie->fw_mon_size;
2158 } else if (trans->dbg_dest_tlv) {
2159 u32 base, end;
2160
2161 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2162 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2163
2164 base = iwl_read_prph(trans, base) <<
2165 trans->dbg_dest_tlv->base_shift;
2166 end = iwl_read_prph(trans, end) <<
2167 trans->dbg_dest_tlv->end_shift;
2168
2169 /* Make "end" point to the actual end */
2170 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2171 end += (1 << trans->dbg_dest_tlv->end_shift);
2172 monitor_len = end - base;
2173 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2174 monitor_len;
2175 } else {
2176 monitor_len = 0;
2177 }
c2d20201 2178
48eb7b34
EG		 2179 dump_data = vzalloc(len);
2180 if (!dump_data)
2181 return NULL;
4d075007
JB		 2182
2183 len = 0;
48eb7b34 2184 data = (void *)dump_data->data;
4d075007
JB		 2185 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2186 txcmd = (void *)data->data;
2187 spin_lock_bh(&cmdq->lock);
2188 ptr = cmdq->q.write_ptr;
2189 for (i = 0; i < cmdq->q.n_window; i++) {
2190 u8 idx = get_cmd_index(&cmdq->q, ptr);
2191 u32 caplen, cmdlen;
2192
2193 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2194 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2195
2196 if (cmdlen) {
2197 len += sizeof(*txcmd) + caplen;
2198 txcmd->cmdlen = cpu_to_le32(cmdlen);
2199 txcmd->caplen = cpu_to_le32(caplen);
2200 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2201 txcmd = (void *)((u8 *)txcmd->data + caplen);
2202 }
2203
2204 ptr = iwl_queue_dec_wrap(ptr);
2205 }
2206 spin_unlock_bh(&cmdq->lock);
2207
2208 data->len = cpu_to_le32(len);
c2d20201 2209 len += sizeof(*data);
67c65f2c
EG		 2210 data = iwl_fw_error_next_data(data);
2211
2212 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2213 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2214 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2215 /* data is already pointing to the next section */
c2d20201 2216
99684ae3
LK		 2217 if ((trans_pcie->fw_mon_page &&
2218 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2219 trans->dbg_dest_tlv) {
c544e9c4 2220 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2221 u32 base, write_ptr, wrap_cnt;
2222
2223 /* If there was a dest TLV - use the values from there */
2224 if (trans->dbg_dest_tlv) {
2225 write_ptr =
2226 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2227 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2228 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2229 } else {
2230 base = MON_BUFF_BASE_ADDR;
2231 write_ptr = MON_BUFF_WRPTR;
2232 wrap_cnt = MON_BUFF_CYCLE_CNT;
2233 }
c2d20201 2234
c2d20201 2235 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2236 fw_mon_data = (void *)data->data;
2237 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2238 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2239 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2240 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2241 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2242 cpu_to_le32(iwl_read_prph(trans, base));
2243
2244 len += sizeof(*data) + sizeof(*fw_mon_data);
2245 if (trans_pcie->fw_mon_page) {
2246 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2247 sizeof(*fw_mon_data));
2248
2249 /*
2250 * The firmware is now asserted, it won't write anything
2251 * to the buffer. CPU can take ownership to fetch the
2252 * data. The buffer will be handed back to the device
2253 * before the firmware will be restarted.
2254 */
2255 dma_sync_single_for_cpu(trans->dev,
2256 trans_pcie->fw_mon_phys,
2257 trans_pcie->fw_mon_size,
2258 DMA_FROM_DEVICE);
2259 memcpy(fw_mon_data->data,
2260 page_address(trans_pcie->fw_mon_page),
2261 trans_pcie->fw_mon_size);
2262
2263 len += trans_pcie->fw_mon_size;
2264 } else {
2265 /* If we are here then the buffer is internal */
2266
2267 /*
2268 * Update pointers to reflect actual values after
2269 * shifting
2270 */
2271 base = iwl_read_prph(trans, base) <<
2272 trans->dbg_dest_tlv->base_shift;
2273 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2274 monitor_len / sizeof(u32));
2275 data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2276 monitor_len);
2277 len += monitor_len;
2278 }
c2d20201
EG		 2279 }
2280
48eb7b34
EG		 2281 dump_data->len = len;
2282
2283 return dump_data;
4d075007 2284}
87e5666c 2285
d1ff5253 2286static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2287 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2288 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2289 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2290 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2291 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2292
ddaf5a5b
JB		 2293 .d3_suspend = iwl_trans_pcie_d3_suspend,
2294 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2295
f02831be 2296 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2297
e6bb4c9c 2298 .tx = iwl_trans_pcie_tx,
a0eaad71 2299 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2300
d0624be6 2301 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2302 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2303
87e5666c 2304 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2305
990aa6d7 2306 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
5f178cd2 2307
03905495
EG		 2308 .write8 = iwl_trans_pcie_write8,
2309 .write32 = iwl_trans_pcie_write32,
2310 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2311 .read_prph = iwl_trans_pcie_read_prph,
2312 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2313 .read_mem = iwl_trans_pcie_read_mem,
2314 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2315 .configure = iwl_trans_pcie_configure,
47107e84 2316 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2317 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2318 .release_nic_access = iwl_trans_pcie_release_nic_access,
2319 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2320
7616f334
EP		 2321 .ref = iwl_trans_pcie_ref,
2322 .unref = iwl_trans_pcie_unref,
2323
4d075007 2324 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2325};
a42a1844 2326
87ce05a2 2327struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2328 const struct pci_device_id *ent,
2329 const struct iwl_cfg *cfg)
a42a1844 2330{
a42a1844
EG		 2331 struct iwl_trans_pcie *trans_pcie;
2332 struct iwl_trans *trans;
2333 u16 pci_cmd;
2334 int err;
2335
2336 trans = kzalloc(sizeof(struct iwl_trans) +
20d3b647 2337 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
6965a354
LC		 2338 if (!trans) {
2339 err = -ENOMEM;
2340 goto out;
2341 }
a42a1844
EG		 2342
2343 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2344
2345 trans->ops = &trans_ops_pcie;
035f7ff2 2346 trans->cfg = cfg;
2bfb5092 2347 trans_lockdep_init(trans);
a42a1844 2348 trans_pcie->trans = trans;
7b11488f 2349 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2350 spin_lock_init(&trans_pcie->reg_lock);
13df1aab 2351 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2352
d819c6cf
JB		 2353 err = pci_enable_device(pdev);
2354 if (err)
2355 goto out_no_pci;
2356
f2532b04
EG		 2357 if (!cfg->base_params->pcie_l1_allowed) {
2358 /*
2359 * W/A - seems to solve weird behavior. We need to remove this
2360 * if we don't want to stay in L1 all the time. This wastes a
2361 * lot of power.
2362 */
2363 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2364 PCIE_LINK_STATE_L1 |
2365 PCIE_LINK_STATE_CLKPM);
2366 }
a42a1844 2367
a42a1844
EG		 2368 pci_set_master(pdev);
2369
2370 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2371 if (!err)
2372 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2373 if (err) {
2374 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2375 if (!err)
2376 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2377 DMA_BIT_MASK(32));
a42a1844
EG		 2378 /* both attempts failed: */
2379 if (err) {
6a4b09f8 2380 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2381 goto out_pci_disable_device;
2382 }
2383 }
2384
2385 err = pci_request_regions(pdev, DRV_NAME);
2386 if (err) {
6a4b09f8 2387 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2388 goto out_pci_disable_device;
2389 }
2390
05f5b97e 2391 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2392 if (!trans_pcie->hw_base) {
6a4b09f8 2393 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2394 err = -ENODEV;
2395 goto out_pci_release_regions;
2396 }
2397
a42a1844
EG		 2398 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2399 * PCI Tx retries from interfering with C3 CPU state */
2400 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2401
83f7a85f
EG		 2402 trans->dev = &pdev->dev;
2403 trans_pcie->pci_dev = pdev;
2404 iwl_disable_interrupts(trans);
2405
a42a1844 2406 err = pci_enable_msi(pdev);
9f904b38 2407 if (err) {
6a4b09f8 2408 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2409 /* enable rfkill interrupt: hw bug w/a */
2410 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2411 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2412 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2413 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2414 }
2415 }
a42a1844 2416
08079a49 2417 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2418 /*
2419 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2420 * changed, and now the revision step also includes bit 0-1 (no more
2421 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2422 * in the old format.
2423 */
2424 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2425 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2426 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2427
99673ee5 2428 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2429 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2430 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2431
69a10b29 2432 /* Initialize the wait queue for commands */
f946b529 2433 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2434
3ec45882
JB		 2435 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2436 "iwl_cmd_pool:%s", dev_name(trans->dev));
59c647b6
EG		 2437
2438 trans->dev_cmd_headroom = 0;
2439 trans->dev_cmd_pool =
3ec45882 2440 kmem_cache_create(trans->dev_cmd_pool_name,
59c647b6
EG		 2441 sizeof(struct iwl_device_cmd)
2442 + trans->dev_cmd_headroom,
2443 sizeof(void *),
2444 SLAB_HWCACHE_ALIGN,
2445 NULL);
2446
6965a354
LC		 2447 if (!trans->dev_cmd_pool) {
2448 err = -ENOMEM;
59c647b6 2449 goto out_pci_disable_msi;
6965a354 2450 }
59c647b6 2451
a8b691e6
JB		 2452 if (iwl_pcie_alloc_ict(trans))
2453 goto out_free_cmd_pool;
2454
85bf9da1 2455 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2456 iwl_pcie_irq_handler,
2457 IRQF_SHARED, DRV_NAME, trans);
2458 if (err) {
a8b691e6
JB		 2459 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2460 goto out_free_ict;
2461 }
2462
83f7a85f 2463 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2464 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2465
a42a1844
EG		 2466 return trans;
2467
a8b691e6
JB		 2468out_free_ict:
2469 iwl_pcie_free_ict(trans);
2470out_free_cmd_pool:
2471 kmem_cache_destroy(trans->dev_cmd_pool);
59c647b6
EG		 2472out_pci_disable_msi:
2473 pci_disable_msi(pdev);
a42a1844
EG		 2474out_pci_release_regions:
2475 pci_release_regions(pdev);
2476out_pci_disable_device:
2477 pci_disable_device(pdev);
2478out_no_pci:
2479 kfree(trans);
6965a354
LC		 2480out:
2481 return ERR_PTR(err);
a42a1844 2482}
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