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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
128e63ef | 8 | * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
128e63ef | 33 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
cf614297 | 67 | #include <linux/sched.h> |
6d8f6eeb EG |
68 | #include <linux/bitops.h> |
69 | #include <linux/gfp.h> | |
e6bb4c9c | 70 | |
82575102 | 71 | #include "iwl-drv.h" |
c85eb619 | 72 | #include "iwl-trans.h" |
522376d2 EG |
73 | #include "iwl-csr.h" |
74 | #include "iwl-prph.h" | |
7a10e3e4 | 75 | #include "iwl-agn-hw.h" |
6468a01a | 76 | #include "internal.h" |
0439bb62 | 77 | |
e139dc4a LE |
78 | static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, |
79 | u32 reg, u32 mask, u32 value) | |
80 | { | |
81 | u32 v; | |
82 | ||
83 | #ifdef CONFIG_IWLWIFI_DEBUG | |
84 | WARN_ON_ONCE(value & ~mask); | |
85 | #endif | |
86 | ||
87 | v = iwl_read32(trans, reg); | |
88 | v &= ~mask; | |
89 | v |= value; | |
90 | iwl_write32(trans, reg, v); | |
91 | } | |
92 | ||
93 | static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, | |
94 | u32 reg, u32 mask) | |
95 | { | |
96 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); | |
97 | } | |
98 | ||
99 | static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, | |
100 | u32 reg, u32 mask) | |
101 | { | |
102 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); | |
103 | } | |
104 | ||
ddaf5a5b | 105 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 106 | { |
ddaf5a5b JB |
107 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
108 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
109 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
110 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
111 | else | |
112 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
113 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
114 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
115 | } |
116 | ||
af634bee EG |
117 | /* PCI registers */ |
118 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 119 | |
7afe3705 | 120 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 121 | { |
20d3b647 | 122 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 123 | u16 lctl; |
af634bee | 124 | |
af634bee EG |
125 | /* |
126 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
127 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
128 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
129 | * costs negligible amount of power savings. | |
130 | * If not (unlikely), enable L0S, so there is at least some | |
131 | * power savings, even without L1. | |
132 | */ | |
7afe3705 | 133 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
438a0f0a | 134 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { |
af634bee EG |
135 | /* L1-ASPM enabled; disable(!) L0S */ |
136 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 137 | dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); |
af634bee EG |
138 | } else { |
139 | /* L1-ASPM disabled; enable(!) L0S */ | |
140 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
6a4b09f8 | 141 | dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); |
af634bee | 142 | } |
438a0f0a | 143 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
af634bee EG |
144 | } |
145 | ||
a6c684ee EG |
146 | /* |
147 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 148 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
149 | * NOTE: This does not load uCode nor start the embedded processor |
150 | */ | |
7afe3705 | 151 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee | 152 | { |
83626404 | 153 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a6c684ee EG |
154 | int ret = 0; |
155 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
156 | ||
157 | /* | |
158 | * Use "set_bit" below rather than "write", to preserve any hardware | |
159 | * bits already set by default after reset. | |
160 | */ | |
161 | ||
162 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
163 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 164 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
a6c684ee EG |
165 | |
166 | /* | |
167 | * Disable L0s without affecting L1; | |
168 | * don't wait for ICH L0s (ICH bug W/A) | |
169 | */ | |
170 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 171 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
172 | |
173 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
174 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
175 | ||
176 | /* | |
177 | * Enable HAP INTA (interrupt from management bus) to | |
178 | * wake device's PCI Express link L1a -> L0s | |
179 | */ | |
180 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 181 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 182 | |
7afe3705 | 183 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
184 | |
185 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 186 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 187 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 188 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
189 | |
190 | /* | |
191 | * Set "initialization complete" bit to move adapter from | |
192 | * D0U* --> D0A* (powered-up active) state. | |
193 | */ | |
194 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
195 | ||
196 | /* | |
197 | * Wait for clock stabilization; once stabilized, access to | |
198 | * device-internal resources is supported, e.g. iwl_write_prph() | |
199 | * and accesses to uCode SRAM. | |
200 | */ | |
201 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
202 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
203 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
204 | if (ret < 0) { |
205 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
206 | goto out; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Enable DMA clock and wait for it to stabilize. | |
211 | * | |
212 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
213 | * do not disable clocks. This preserves any hardware bits already | |
214 | * set by default in "CLK_CTRL_REG" after reset. | |
215 | */ | |
216 | iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
217 | udelay(20); | |
218 | ||
219 | /* Disable L1-Active */ | |
220 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
221 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
222 | ||
83626404 | 223 | set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
a6c684ee EG |
224 | |
225 | out: | |
226 | return ret; | |
227 | } | |
228 | ||
7afe3705 | 229 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
230 | { |
231 | int ret = 0; | |
232 | ||
233 | /* stop device's busmaster DMA activity */ | |
234 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
235 | ||
236 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
237 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
238 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
cc56feb2 EG |
239 | if (ret) |
240 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); | |
241 | ||
242 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
7afe3705 | 247 | static void iwl_pcie_apm_stop(struct iwl_trans *trans) |
cc56feb2 | 248 | { |
83626404 | 249 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cc56feb2 EG |
250 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); |
251 | ||
83626404 | 252 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); |
cc56feb2 EG |
253 | |
254 | /* Stop device's DMA activity */ | |
7afe3705 | 255 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 EG |
256 | |
257 | /* Reset the entire device */ | |
258 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
259 | ||
260 | udelay(10); | |
261 | ||
262 | /* | |
263 | * Clear "initialization complete" bit to move adapter from | |
264 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
265 | */ | |
266 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
267 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
268 | } | |
269 | ||
7afe3705 | 270 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 271 | { |
7b11488f | 272 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
273 | unsigned long flags; |
274 | ||
275 | /* nic_init */ | |
7b11488f | 276 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
7afe3705 | 277 | iwl_pcie_apm_init(trans); |
392f8b78 EG |
278 | |
279 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
20d3b647 | 280 | iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
392f8b78 | 281 | |
7b11488f | 282 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
392f8b78 | 283 | |
ddaf5a5b | 284 | iwl_pcie_set_pwr(trans, false); |
392f8b78 | 285 | |
ecdb975c | 286 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
287 | |
288 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 289 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
290 | |
291 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 292 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
293 | return -ENOMEM; |
294 | ||
035f7ff2 | 295 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 296 | /* enable shadow regs in HW */ |
20d3b647 | 297 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 298 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
299 | } |
300 | ||
392f8b78 EG |
301 | return 0; |
302 | } | |
303 | ||
304 | #define HW_READY_TIMEOUT (50) | |
305 | ||
306 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 307 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
308 | { |
309 | int ret; | |
310 | ||
1042db2a | 311 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 312 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
313 | |
314 | /* See if we got it */ | |
1042db2a | 315 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
316 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
317 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
318 | HW_READY_TIMEOUT); | |
392f8b78 | 319 | |
6d8f6eeb | 320 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
321 | return ret; |
322 | } | |
323 | ||
324 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 325 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
326 | { |
327 | int ret; | |
289e5501 | 328 | int t = 0; |
392f8b78 | 329 | |
6d8f6eeb | 330 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 331 | |
7afe3705 | 332 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 333 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
334 | if (ret >= 0) |
335 | return 0; | |
336 | ||
337 | /* If HW is not ready, prepare the conditions to check again */ | |
1042db2a | 338 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 339 | CSR_HW_IF_CONFIG_REG_PREPARE); |
392f8b78 | 340 | |
289e5501 | 341 | do { |
7afe3705 | 342 | ret = iwl_pcie_set_hw_ready(trans); |
289e5501 EG |
343 | if (ret >= 0) |
344 | return 0; | |
392f8b78 | 345 | |
289e5501 EG |
346 | usleep_range(200, 1000); |
347 | t += 200; | |
348 | } while (t < 150000); | |
392f8b78 | 349 | |
392f8b78 EG |
350 | return ret; |
351 | } | |
352 | ||
cf614297 EG |
353 | /* |
354 | * ucode | |
355 | */ | |
7afe3705 | 356 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 357 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 358 | { |
13df1aab | 359 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
360 | int ret; |
361 | ||
13df1aab | 362 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
363 | |
364 | iwl_write_direct32(trans, | |
20d3b647 JB |
365 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
366 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
367 | |
368 | iwl_write_direct32(trans, | |
20d3b647 JB |
369 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
370 | dst_addr); | |
cf614297 EG |
371 | |
372 | iwl_write_direct32(trans, | |
83f84d7b JB |
373 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
374 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
375 | |
376 | iwl_write_direct32(trans, | |
20d3b647 JB |
377 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
378 | (iwl_get_dma_hi_addr(phy_addr) | |
379 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
380 | |
381 | iwl_write_direct32(trans, | |
20d3b647 JB |
382 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
383 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
384 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
385 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
386 | |
387 | iwl_write_direct32(trans, | |
20d3b647 JB |
388 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
389 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
390 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
391 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 392 | |
13df1aab JB |
393 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
394 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 395 | if (!ret) { |
83f84d7b | 396 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
397 | return -ETIMEDOUT; |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
7afe3705 | 403 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 404 | const struct fw_desc *section) |
cf614297 | 405 | { |
83f84d7b JB |
406 | u8 *v_addr; |
407 | dma_addr_t p_addr; | |
408 | u32 offset; | |
cf614297 EG |
409 | int ret = 0; |
410 | ||
83f84d7b JB |
411 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
412 | section_num); | |
413 | ||
414 | v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL); | |
415 | if (!v_addr) | |
416 | return -ENOMEM; | |
417 | ||
418 | for (offset = 0; offset < section->len; offset += PAGE_SIZE) { | |
419 | u32 copy_size; | |
420 | ||
421 | copy_size = min_t(u32, PAGE_SIZE, section->len - offset); | |
cf614297 | 422 | |
83f84d7b | 423 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
7afe3705 EG |
424 | ret = iwl_pcie_load_firmware_chunk(trans, |
425 | section->offset + offset, | |
426 | p_addr, copy_size); | |
83f84d7b JB |
427 | if (ret) { |
428 | IWL_ERR(trans, | |
429 | "Could not load the [%d] uCode section\n", | |
430 | section_num); | |
431 | break; | |
6dfa8d01 | 432 | } |
83f84d7b JB |
433 | } |
434 | ||
435 | dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr); | |
436 | return ret; | |
437 | } | |
438 | ||
7afe3705 | 439 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 440 | const struct fw_img *image) |
cf614297 | 441 | { |
2d1c0044 | 442 | int i, ret = 0; |
cf614297 | 443 | |
2d1c0044 | 444 | for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) { |
83f84d7b | 445 | if (!image->sec[i].data) |
2d1c0044 | 446 | break; |
cf614297 | 447 | |
7afe3705 | 448 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
2d1c0044 JB |
449 | if (ret) |
450 | return ret; | |
451 | } | |
cf614297 EG |
452 | |
453 | /* Remove all resets to allow NIC to operate */ | |
454 | iwl_write32(trans, CSR_RESET, 0); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
0692fe41 | 459 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 460 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 | 461 | { |
d18aa87f | 462 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 | 463 | int ret; |
c9eec95c | 464 | bool hw_rfkill; |
392f8b78 | 465 | |
496bab39 | 466 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 467 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 468 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
469 | return -EIO; |
470 | } | |
471 | ||
d18aa87f JB |
472 | clear_bit(STATUS_FW_ERROR, &trans_pcie->status); |
473 | ||
8c46bb70 EG |
474 | iwl_enable_rfkill_int(trans); |
475 | ||
392f8b78 | 476 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 477 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b EG |
478 | if (hw_rfkill) |
479 | set_bit(STATUS_RFKILL, &trans_pcie->status); | |
480 | else | |
481 | clear_bit(STATUS_RFKILL, &trans_pcie->status); | |
c9eec95c | 482 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
6ae02f3e | 483 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 484 | return -ERFKILL; |
392f8b78 | 485 | |
1042db2a | 486 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 487 | |
7afe3705 | 488 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 489 | if (ret) { |
6d8f6eeb | 490 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
491 | return ret; |
492 | } | |
493 | ||
494 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
495 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
496 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
497 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
498 | ||
499 | /* clear (again), then enable host interrupts */ | |
1042db2a | 500 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 501 | iwl_enable_interrupts(trans); |
392f8b78 EG |
502 | |
503 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
504 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
505 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 506 | |
cf614297 | 507 | /* Load the given image to the HW */ |
7afe3705 | 508 | return iwl_pcie_load_given_ucode(trans, fw); |
b3c2ce13 EG |
509 | } |
510 | ||
adca1235 | 511 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 512 | { |
990aa6d7 | 513 | iwl_pcie_reset_ict(trans); |
f02831be | 514 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
515 | } |
516 | ||
43e58856 | 517 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf | 518 | { |
43e58856 | 519 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
20d3b647 | 520 | unsigned long flags; |
ae2c30bf | 521 | |
43e58856 | 522 | /* tell the device to stop sending interrupts */ |
7b11488f | 523 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ae2c30bf | 524 | iwl_disable_interrupts(trans); |
7b11488f | 525 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ae2c30bf | 526 | |
ab6cf8e8 | 527 | /* device going down, Stop using ICT table */ |
990aa6d7 | 528 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
529 | |
530 | /* | |
531 | * If a HW restart happens during firmware loading, | |
532 | * then the firmware loading might call this function | |
533 | * and later it might be called again due to the | |
534 | * restart. So don't process again if the device is | |
535 | * already dead. | |
536 | */ | |
83626404 | 537 | if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) { |
f02831be | 538 | iwl_pcie_tx_stop(trans); |
9805c446 | 539 | iwl_pcie_rx_stop(trans); |
6379103e | 540 | |
ab6cf8e8 | 541 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 542 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
543 | APMG_CLK_VAL_DMA_CLK_RQT); |
544 | udelay(5); | |
545 | } | |
546 | ||
547 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 548 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 549 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
550 | |
551 | /* Stop the device, and put it in low power state */ | |
7afe3705 | 552 | iwl_pcie_apm_stop(trans); |
43e58856 EG |
553 | |
554 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
555 | * Clean again the interrupt here | |
556 | */ | |
7b11488f | 557 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
43e58856 | 558 | iwl_disable_interrupts(trans); |
7b11488f | 559 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
43e58856 | 560 | |
218733cf EG |
561 | iwl_enable_rfkill_int(trans); |
562 | ||
43e58856 | 563 | /* stop and reset the on-board processor */ |
1042db2a | 564 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
74fda971 DF |
565 | |
566 | /* clear all status bits */ | |
567 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); | |
568 | clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); | |
569 | clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status); | |
01d651d4 | 570 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
f946b529 | 571 | clear_bit(STATUS_RFKILL, &trans_pcie->status); |
ab6cf8e8 EG |
572 | } |
573 | ||
ddaf5a5b | 574 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans) |
2dd4f9f7 JB |
575 | { |
576 | /* let the ucode operate on its own */ | |
577 | iwl_write32(trans, CSR_UCODE_DRV_GP1_SET, | |
578 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
579 | ||
580 | iwl_disable_interrupts(trans); | |
ddaf5a5b JB |
581 | iwl_pcie_disable_ict(trans); |
582 | ||
2dd4f9f7 JB |
583 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
584 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
585 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
586 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
587 | ||
588 | /* | |
589 | * reset TX queues -- some of their registers reset during S3 | |
590 | * so if we don't reset everything here the D3 image would try | |
591 | * to execute some invalid memory upon resume | |
592 | */ | |
593 | iwl_trans_pcie_tx_reset(trans); | |
594 | ||
595 | iwl_pcie_set_pwr(trans, true); | |
596 | } | |
597 | ||
598 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
599 | enum iwl_d3_status *status) | |
600 | { | |
601 | u32 val; | |
602 | int ret; | |
603 | ||
604 | iwl_pcie_set_pwr(trans, false); | |
605 | ||
606 | val = iwl_read32(trans, CSR_RESET); | |
607 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { | |
608 | *status = IWL_D3_STATUS_RESET; | |
609 | return 0; | |
610 | } | |
611 | ||
612 | /* | |
613 | * Also enables interrupts - none will happen as the device doesn't | |
614 | * know we're waking it up, only when the opmode actually tells it | |
615 | * after this call. | |
616 | */ | |
617 | iwl_pcie_reset_ict(trans); | |
618 | ||
619 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
620 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
621 | ||
622 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
623 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
624 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
625 | 25000); | |
626 | if (ret) { | |
627 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); | |
628 | return ret; | |
629 | } | |
630 | ||
631 | iwl_trans_pcie_tx_reset(trans); | |
632 | ||
633 | ret = iwl_pcie_rx_init(trans); | |
634 | if (ret) { | |
635 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
636 | return ret; | |
637 | } | |
638 | ||
639 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
640 | CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); | |
641 | ||
642 | *status = IWL_D3_STATUS_ALIVE; | |
643 | return 0; | |
2dd4f9f7 JB |
644 | } |
645 | ||
57a1dc89 | 646 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) |
e6bb4c9c | 647 | { |
4620020b | 648 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c9eec95c | 649 | bool hw_rfkill; |
a8b691e6 | 650 | int err; |
e6bb4c9c | 651 | |
7afe3705 | 652 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 653 | if (err) { |
d6f1c316 | 654 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 655 | return err; |
ebb7678d | 656 | } |
a6c684ee | 657 | |
7afe3705 | 658 | iwl_pcie_apm_init(trans); |
a6c684ee | 659 | |
226c02ca EG |
660 | /* From now on, the op_mode will be kept updated about RF kill state */ |
661 | iwl_enable_rfkill_int(trans); | |
662 | ||
8d425517 | 663 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b EG |
664 | if (hw_rfkill) |
665 | set_bit(STATUS_RFKILL, &trans_pcie->status); | |
666 | else | |
667 | clear_bit(STATUS_RFKILL, &trans_pcie->status); | |
c9eec95c | 668 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
d48e2074 | 669 | |
a8b691e6 | 670 | return 0; |
e6bb4c9c EG |
671 | } |
672 | ||
218733cf EG |
673 | static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, |
674 | bool op_mode_leaving) | |
cc56feb2 | 675 | { |
20d3b647 | 676 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 677 | bool hw_rfkill; |
218733cf | 678 | unsigned long flags; |
d23f78e6 | 679 | |
ee7d737c DS |
680 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
681 | iwl_disable_interrupts(trans); | |
682 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
683 | ||
7afe3705 | 684 | iwl_pcie_apm_stop(trans); |
cc56feb2 | 685 | |
218733cf EG |
686 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
687 | iwl_disable_interrupts(trans); | |
688 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
1df06bdc | 689 | |
8d96bb61 EG |
690 | iwl_pcie_disable_ict(trans); |
691 | ||
218733cf EG |
692 | if (!op_mode_leaving) { |
693 | /* | |
694 | * Even if we stop the HW, we still want the RF kill | |
695 | * interrupt | |
696 | */ | |
697 | iwl_enable_rfkill_int(trans); | |
698 | ||
699 | /* | |
700 | * Check again since the RF kill state may have changed while | |
701 | * all the interrupts were disabled, in this case we couldn't | |
702 | * receive the RF kill interrupt and update the state in the | |
703 | * op_mode. | |
704 | */ | |
705 | hw_rfkill = iwl_is_rfkill_set(trans); | |
4620020b EG |
706 | if (hw_rfkill) |
707 | set_bit(STATUS_RFKILL, &trans_pcie->status); | |
708 | else | |
709 | clear_bit(STATUS_RFKILL, &trans_pcie->status); | |
218733cf EG |
710 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
711 | } | |
cc56feb2 EG |
712 | } |
713 | ||
03905495 EG |
714 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
715 | { | |
05f5b97e | 716 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
717 | } |
718 | ||
719 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
720 | { | |
05f5b97e | 721 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
722 | } |
723 | ||
724 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
725 | { | |
05f5b97e | 726 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
727 | } |
728 | ||
6a06b6c1 EG |
729 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
730 | { | |
731 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); | |
732 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); | |
733 | } | |
734 | ||
735 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
736 | u32 val) | |
737 | { | |
738 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
739 | ((addr & 0x0000FFFF) | (3 << 24))); | |
740 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); | |
741 | } | |
742 | ||
c6f600fc | 743 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 744 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
745 | { |
746 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
747 | ||
748 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 749 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
d663ee73 JB |
750 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
751 | trans_pcie->n_no_reclaim_cmds = 0; | |
752 | else | |
753 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
754 | if (trans_pcie->n_no_reclaim_cmds) | |
755 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
756 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 757 | |
b2cf410c JB |
758 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
759 | if (trans_pcie->rx_buf_size_8k) | |
760 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
761 | else | |
762 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 JB |
763 | |
764 | trans_pcie->wd_timeout = | |
765 | msecs_to_jiffies(trans_cfg->queue_watchdog_timeout); | |
d9fb6465 JB |
766 | |
767 | trans_pcie->command_names = trans_cfg->command_names; | |
046db346 | 768 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
c6f600fc MV |
769 | } |
770 | ||
d1ff5253 | 771 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 772 | { |
20d3b647 | 773 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 774 | |
0aa86df6 | 775 | synchronize_irq(trans_pcie->pci_dev->irq); |
0aa86df6 | 776 | |
f02831be | 777 | iwl_pcie_tx_free(trans); |
9805c446 | 778 | iwl_pcie_rx_free(trans); |
6379103e | 779 | |
a8b691e6 JB |
780 | free_irq(trans_pcie->pci_dev->irq, trans); |
781 | iwl_pcie_free_ict(trans); | |
a42a1844 EG |
782 | |
783 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 784 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
785 | pci_release_regions(trans_pcie->pci_dev); |
786 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 787 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 788 | |
6d8f6eeb | 789 | kfree(trans); |
34c1b7ba EG |
790 | } |
791 | ||
47107e84 DF |
792 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
793 | { | |
794 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
795 | ||
796 | if (state) | |
01d651d4 | 797 | set_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 | 798 | else |
01d651d4 | 799 | clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status); |
47107e84 DF |
800 | } |
801 | ||
c01a4047 | 802 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
803 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
804 | { | |
57210f7c EG |
805 | return 0; |
806 | } | |
807 | ||
808 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
809 | { | |
c9eec95c | 810 | bool hw_rfkill; |
57210f7c | 811 | |
8c46bb70 EG |
812 | iwl_enable_rfkill_int(trans); |
813 | ||
8d425517 | 814 | hw_rfkill = iwl_is_rfkill_set(trans); |
8c46bb70 | 815 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); |
8722c899 | 816 | |
57210f7c EG |
817 | return 0; |
818 | } | |
c01a4047 | 819 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 820 | |
e56b04ef LE |
821 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, |
822 | unsigned long *flags) | |
7a65d170 EG |
823 | { |
824 | int ret; | |
e56b04ef LE |
825 | struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans); |
826 | spin_lock_irqsave(&pcie_trans->reg_lock, *flags); | |
7a65d170 EG |
827 | |
828 | /* this bit wakes up the NIC */ | |
e139dc4a LE |
829 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
830 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
831 | |
832 | /* | |
833 | * These bits say the device is running, and should keep running for | |
834 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
835 | * but they do not indicate that embedded SRAM is restored yet; | |
836 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
837 | * to/from host DRAM when sleeping/waking for power-saving. | |
838 | * Each direction takes approximately 1/4 millisecond; with this | |
839 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
840 | * series of register accesses are expected (e.g. reading Event Log), | |
841 | * to keep device from sleeping. | |
842 | * | |
843 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
844 | * SRAM is okay/restored. We don't check that here because this call | |
845 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
846 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
847 | * | |
848 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
849 | * and do not save/restore SRAM when power cycling. | |
850 | */ | |
851 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
852 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
853 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
854 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
855 | if (unlikely(ret < 0)) { | |
856 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
857 | if (!silent) { | |
858 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
859 | WARN_ONCE(1, | |
860 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
861 | val); | |
e56b04ef | 862 | spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags); |
7a65d170 EG |
863 | return false; |
864 | } | |
865 | } | |
866 | ||
e56b04ef LE |
867 | /* |
868 | * Fool sparse by faking we release the lock - sparse will | |
869 | * track nic_access anyway. | |
870 | */ | |
871 | __release(&pcie_trans->reg_lock); | |
7a65d170 EG |
872 | return true; |
873 | } | |
874 | ||
e56b04ef LE |
875 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
876 | unsigned long *flags) | |
7a65d170 | 877 | { |
e56b04ef LE |
878 | struct iwl_trans_pcie *pcie_trans = IWL_TRANS_GET_PCIE_TRANS(trans); |
879 | ||
880 | lockdep_assert_held(&pcie_trans->reg_lock); | |
881 | ||
882 | /* | |
883 | * Fool sparse by faking we acquiring the lock - sparse will | |
884 | * track nic_access anyway. | |
885 | */ | |
886 | __acquire(&pcie_trans->reg_lock); | |
887 | ||
e139dc4a LE |
888 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
889 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
890 | /* |
891 | * Above we read the CSR_GP_CNTRL register, which will flush | |
892 | * any previous writes, but we need the write that clears the | |
893 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
894 | * scheduled on different CPUs (after we drop reg_lock). | |
895 | */ | |
896 | mmiowb(); | |
e56b04ef | 897 | spin_unlock_irqrestore(&pcie_trans->reg_lock, *flags); |
7a65d170 EG |
898 | } |
899 | ||
4fd442db EG |
900 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
901 | void *buf, int dwords) | |
902 | { | |
903 | unsigned long flags; | |
904 | int offs, ret = 0; | |
905 | u32 *vals = buf; | |
906 | ||
e56b04ef | 907 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
908 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
909 | for (offs = 0; offs < dwords; offs++) | |
910 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 911 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
912 | } else { |
913 | ret = -EBUSY; | |
914 | } | |
4fd442db EG |
915 | return ret; |
916 | } | |
917 | ||
918 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
919 | void *buf, int dwords) | |
920 | { | |
921 | unsigned long flags; | |
922 | int offs, ret = 0; | |
923 | u32 *vals = buf; | |
924 | ||
e56b04ef | 925 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
926 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
927 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
928 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
929 | vals ? vals[offs] : 0); | |
e56b04ef | 930 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
931 | } else { |
932 | ret = -EBUSY; | |
933 | } | |
4fd442db EG |
934 | return ret; |
935 | } | |
7a65d170 | 936 | |
5f178cd2 EG |
937 | #define IWL_FLUSH_WAIT_MS 2000 |
938 | ||
990aa6d7 | 939 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans) |
5f178cd2 | 940 | { |
8ad71bef | 941 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 942 | struct iwl_txq *txq; |
5f178cd2 EG |
943 | struct iwl_queue *q; |
944 | int cnt; | |
945 | unsigned long now = jiffies; | |
1c3fea82 EG |
946 | u32 scd_sram_addr; |
947 | u8 buf[16]; | |
5f178cd2 EG |
948 | int ret = 0; |
949 | ||
950 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 951 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
9ba1947a | 952 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 953 | continue; |
8ad71bef | 954 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
955 | q = &txq->q; |
956 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
957 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
958 | msleep(1); | |
959 | ||
960 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
961 | IWL_ERR(trans, |
962 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
963 | ret = -ETIMEDOUT; |
964 | break; | |
965 | } | |
966 | } | |
1c3fea82 EG |
967 | |
968 | if (!ret) | |
969 | return 0; | |
970 | ||
971 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
972 | txq->q.read_ptr, txq->q.write_ptr); | |
973 | ||
974 | scd_sram_addr = trans_pcie->scd_base_addr + | |
975 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
976 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
977 | ||
978 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
979 | ||
980 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
981 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
982 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
983 | ||
984 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
985 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
986 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
987 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
988 | u32 tbl_dw = | |
989 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
990 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
991 | ||
992 | if (cnt & 0x1) | |
993 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
994 | else | |
995 | tbl_dw = tbl_dw & 0x0000FFFF; | |
996 | ||
997 | IWL_ERR(trans, | |
998 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
999 | cnt, active ? "" : "in", fifo, tbl_dw, | |
1000 | iwl_read_prph(trans, | |
1001 | SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1), | |
1002 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); | |
1003 | } | |
1004 | ||
5f178cd2 EG |
1005 | return ret; |
1006 | } | |
1007 | ||
e139dc4a LE |
1008 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
1009 | u32 mask, u32 value) | |
1010 | { | |
e56b04ef | 1011 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
1012 | unsigned long flags; |
1013 | ||
e56b04ef | 1014 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 1015 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 1016 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
1017 | } |
1018 | ||
ff620849 EG |
1019 | static const char *get_fh_string(int cmd) |
1020 | { | |
d9fb6465 | 1021 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1022 | switch (cmd) { |
1023 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1024 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1025 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1026 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1027 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1028 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1029 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1030 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1031 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1032 | default: | |
1033 | return "UNKNOWN"; | |
1034 | } | |
d9fb6465 | 1035 | #undef IWL_CMD |
ff620849 EG |
1036 | } |
1037 | ||
990aa6d7 | 1038 | int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf) |
ff620849 EG |
1039 | { |
1040 | int i; | |
ff620849 EG |
1041 | static const u32 fh_tbl[] = { |
1042 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1043 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1044 | FH_RSCSR_CHNL0_WPTR, | |
1045 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1046 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1047 | FH_MEM_RSSR_RX_STATUS_REG, | |
1048 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1049 | FH_TSSR_TX_STATUS_REG, | |
1050 | FH_TSSR_TX_ERROR_REG | |
1051 | }; | |
94543a8d JB |
1052 | |
1053 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
1054 | if (buf) { | |
1055 | int pos = 0; | |
1056 | size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1057 | ||
ff620849 EG |
1058 | *buf = kmalloc(bufsz, GFP_KERNEL); |
1059 | if (!*buf) | |
1060 | return -ENOMEM; | |
94543a8d | 1061 | |
ff620849 EG |
1062 | pos += scnprintf(*buf + pos, bufsz - pos, |
1063 | "FH register values:\n"); | |
94543a8d JB |
1064 | |
1065 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) | |
ff620849 EG |
1066 | pos += scnprintf(*buf + pos, bufsz - pos, |
1067 | " %34s: 0X%08x\n", | |
1068 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1069 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 1070 | |
ff620849 EG |
1071 | return pos; |
1072 | } | |
1073 | #endif | |
94543a8d | 1074 | |
ff620849 | 1075 | IWL_ERR(trans, "FH register values:\n"); |
94543a8d | 1076 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) |
ff620849 EG |
1077 | IWL_ERR(trans, " %34s: 0X%08x\n", |
1078 | get_fh_string(fh_tbl[i]), | |
1042db2a | 1079 | iwl_read_direct32(trans, fh_tbl[i])); |
94543a8d | 1080 | |
ff620849 EG |
1081 | return 0; |
1082 | } | |
1083 | ||
1084 | static const char *get_csr_string(int cmd) | |
1085 | { | |
d9fb6465 | 1086 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1087 | switch (cmd) { |
1088 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1089 | IWL_CMD(CSR_INT_COALESCING); | |
1090 | IWL_CMD(CSR_INT); | |
1091 | IWL_CMD(CSR_INT_MASK); | |
1092 | IWL_CMD(CSR_FH_INT_STATUS); | |
1093 | IWL_CMD(CSR_GPIO_IN); | |
1094 | IWL_CMD(CSR_RESET); | |
1095 | IWL_CMD(CSR_GP_CNTRL); | |
1096 | IWL_CMD(CSR_HW_REV); | |
1097 | IWL_CMD(CSR_EEPROM_REG); | |
1098 | IWL_CMD(CSR_EEPROM_GP); | |
1099 | IWL_CMD(CSR_OTP_GP_REG); | |
1100 | IWL_CMD(CSR_GIO_REG); | |
1101 | IWL_CMD(CSR_GP_UCODE_REG); | |
1102 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1103 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1104 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1105 | IWL_CMD(CSR_LED_REG); | |
1106 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1107 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1108 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1109 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1110 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1111 | default: | |
1112 | return "UNKNOWN"; | |
1113 | } | |
d9fb6465 | 1114 | #undef IWL_CMD |
ff620849 EG |
1115 | } |
1116 | ||
990aa6d7 | 1117 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
1118 | { |
1119 | int i; | |
1120 | static const u32 csr_tbl[] = { | |
1121 | CSR_HW_IF_CONFIG_REG, | |
1122 | CSR_INT_COALESCING, | |
1123 | CSR_INT, | |
1124 | CSR_INT_MASK, | |
1125 | CSR_FH_INT_STATUS, | |
1126 | CSR_GPIO_IN, | |
1127 | CSR_RESET, | |
1128 | CSR_GP_CNTRL, | |
1129 | CSR_HW_REV, | |
1130 | CSR_EEPROM_REG, | |
1131 | CSR_EEPROM_GP, | |
1132 | CSR_OTP_GP_REG, | |
1133 | CSR_GIO_REG, | |
1134 | CSR_GP_UCODE_REG, | |
1135 | CSR_GP_DRIVER_REG, | |
1136 | CSR_UCODE_DRV_GP1, | |
1137 | CSR_UCODE_DRV_GP2, | |
1138 | CSR_LED_REG, | |
1139 | CSR_DRAM_INT_TBL_REG, | |
1140 | CSR_GIO_CHICKEN_BITS, | |
1141 | CSR_ANA_PLL_CFG, | |
1142 | CSR_HW_REV_WA_REG, | |
1143 | CSR_DBG_HPET_MEM_REG | |
1144 | }; | |
1145 | IWL_ERR(trans, "CSR values:\n"); | |
1146 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1147 | "CSR_INT_PERIODIC_REG)\n"); | |
1148 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1149 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1150 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1151 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1152 | } |
1153 | } | |
1154 | ||
87e5666c EG |
1155 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1156 | /* create and remove of files */ | |
1157 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1158 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1159 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1160 | goto err; \ |
87e5666c EG |
1161 | } while (0) |
1162 | ||
1163 | /* file operation */ | |
1164 | #define DEBUGFS_READ_FUNC(name) \ | |
1165 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1166 | char __user *user_buf, \ | |
1167 | size_t count, loff_t *ppos); | |
1168 | ||
1169 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1170 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1171 | const char __user *user_buf, \ | |
1172 | size_t count, loff_t *ppos); | |
1173 | ||
87e5666c EG |
1174 | #define DEBUGFS_READ_FILE_OPS(name) \ |
1175 | DEBUGFS_READ_FUNC(name); \ | |
1176 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1177 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1178 | .open = simple_open, \ |
87e5666c EG |
1179 | .llseek = generic_file_llseek, \ |
1180 | }; | |
1181 | ||
16db88ba EG |
1182 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1183 | DEBUGFS_WRITE_FUNC(name); \ | |
1184 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1185 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1186 | .open = simple_open, \ |
16db88ba EG |
1187 | .llseek = generic_file_llseek, \ |
1188 | }; | |
1189 | ||
87e5666c EG |
1190 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1191 | DEBUGFS_READ_FUNC(name); \ | |
1192 | DEBUGFS_WRITE_FUNC(name); \ | |
1193 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1194 | .write = iwl_dbgfs_##name##_write, \ | |
1195 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1196 | .open = simple_open, \ |
87e5666c EG |
1197 | .llseek = generic_file_llseek, \ |
1198 | }; | |
1199 | ||
87e5666c | 1200 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1201 | char __user *user_buf, |
1202 | size_t count, loff_t *ppos) | |
8ad71bef | 1203 | { |
5a878bf6 | 1204 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1205 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1206 | struct iwl_txq *txq; |
87e5666c EG |
1207 | struct iwl_queue *q; |
1208 | char *buf; | |
1209 | int pos = 0; | |
1210 | int cnt; | |
1211 | int ret; | |
1745e440 WYG |
1212 | size_t bufsz; |
1213 | ||
035f7ff2 | 1214 | bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1215 | |
f9e75447 | 1216 | if (!trans_pcie->txq) |
87e5666c | 1217 | return -EAGAIN; |
f9e75447 | 1218 | |
87e5666c EG |
1219 | buf = kzalloc(bufsz, GFP_KERNEL); |
1220 | if (!buf) | |
1221 | return -ENOMEM; | |
1222 | ||
035f7ff2 | 1223 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1224 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1225 | q = &txq->q; |
1226 | pos += scnprintf(buf + pos, bufsz - pos, | |
9eae88fa | 1227 | "hwq %.2d: read=%u write=%u use=%d stop=%d\n", |
87e5666c | 1228 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa JB |
1229 | !!test_bit(cnt, trans_pcie->queue_used), |
1230 | !!test_bit(cnt, trans_pcie->queue_stopped)); | |
87e5666c EG |
1231 | } |
1232 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1233 | kfree(buf); | |
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1238 | char __user *user_buf, |
1239 | size_t count, loff_t *ppos) | |
1240 | { | |
5a878bf6 | 1241 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1242 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1243 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1244 | char buf[256]; |
1245 | int pos = 0; | |
1246 | const size_t bufsz = sizeof(buf); | |
1247 | ||
1248 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1249 | rxq->read); | |
1250 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1251 | rxq->write); | |
1252 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1253 | rxq->free_count); | |
1254 | if (rxq->rb_stts) { | |
1255 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1256 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1257 | } else { | |
1258 | pos += scnprintf(buf + pos, bufsz - pos, | |
1259 | "closed_rb_num: Not Allocated\n"); | |
1260 | } | |
1261 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1262 | } | |
1263 | ||
1f7b6172 EG |
1264 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1265 | char __user *user_buf, | |
20d3b647 JB |
1266 | size_t count, loff_t *ppos) |
1267 | { | |
1f7b6172 | 1268 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1269 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1270 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1271 | ||
1272 | int pos = 0; | |
1273 | char *buf; | |
1274 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1275 | ssize_t ret; | |
1276 | ||
1277 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1278 | if (!buf) |
1f7b6172 | 1279 | return -ENOMEM; |
1f7b6172 EG |
1280 | |
1281 | pos += scnprintf(buf + pos, bufsz - pos, | |
1282 | "Interrupt Statistics Report:\n"); | |
1283 | ||
1284 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1285 | isr_stats->hw); | |
1286 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1287 | isr_stats->sw); | |
1288 | if (isr_stats->sw || isr_stats->hw) { | |
1289 | pos += scnprintf(buf + pos, bufsz - pos, | |
1290 | "\tLast Restarting Code: 0x%X\n", | |
1291 | isr_stats->err_code); | |
1292 | } | |
1293 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1294 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1295 | isr_stats->sch); | |
1296 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1297 | isr_stats->alive); | |
1298 | #endif | |
1299 | pos += scnprintf(buf + pos, bufsz - pos, | |
1300 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1301 | ||
1302 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1303 | isr_stats->ctkill); | |
1304 | ||
1305 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1306 | isr_stats->wakeup); | |
1307 | ||
1308 | pos += scnprintf(buf + pos, bufsz - pos, | |
1309 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1310 | ||
1311 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1312 | isr_stats->tx); | |
1313 | ||
1314 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1315 | isr_stats->unhandled); | |
1316 | ||
1317 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1318 | kfree(buf); | |
1319 | return ret; | |
1320 | } | |
1321 | ||
1322 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1323 | const char __user *user_buf, | |
1324 | size_t count, loff_t *ppos) | |
1325 | { | |
1326 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1327 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1328 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1329 | ||
1330 | char buf[8]; | |
1331 | int buf_size; | |
1332 | u32 reset_flag; | |
1333 | ||
1334 | memset(buf, 0, sizeof(buf)); | |
1335 | buf_size = min(count, sizeof(buf) - 1); | |
1336 | if (copy_from_user(buf, user_buf, buf_size)) | |
1337 | return -EFAULT; | |
1338 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1339 | return -EFAULT; | |
1340 | if (reset_flag == 0) | |
1341 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1342 | ||
1343 | return count; | |
1344 | } | |
1345 | ||
16db88ba | 1346 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1347 | const char __user *user_buf, |
1348 | size_t count, loff_t *ppos) | |
16db88ba EG |
1349 | { |
1350 | struct iwl_trans *trans = file->private_data; | |
1351 | char buf[8]; | |
1352 | int buf_size; | |
1353 | int csr; | |
1354 | ||
1355 | memset(buf, 0, sizeof(buf)); | |
1356 | buf_size = min(count, sizeof(buf) - 1); | |
1357 | if (copy_from_user(buf, user_buf, buf_size)) | |
1358 | return -EFAULT; | |
1359 | if (sscanf(buf, "%d", &csr) != 1) | |
1360 | return -EFAULT; | |
1361 | ||
990aa6d7 | 1362 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1363 | |
1364 | return count; | |
1365 | } | |
1366 | ||
16db88ba | 1367 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1368 | char __user *user_buf, |
1369 | size_t count, loff_t *ppos) | |
16db88ba EG |
1370 | { |
1371 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1372 | char *buf = NULL; |
16db88ba EG |
1373 | int pos = 0; |
1374 | ssize_t ret = -EFAULT; | |
1375 | ||
990aa6d7 | 1376 | ret = pos = iwl_pcie_dump_fh(trans, &buf); |
16db88ba EG |
1377 | if (buf) { |
1378 | ret = simple_read_from_buffer(user_buf, | |
1379 | count, ppos, buf, pos); | |
1380 | kfree(buf); | |
1381 | } | |
1382 | ||
1383 | return ret; | |
1384 | } | |
1385 | ||
48dffd39 JB |
1386 | static ssize_t iwl_dbgfs_fw_restart_write(struct file *file, |
1387 | const char __user *user_buf, | |
1388 | size_t count, loff_t *ppos) | |
1389 | { | |
1390 | struct iwl_trans *trans = file->private_data; | |
1391 | ||
1392 | if (!trans->op_mode) | |
1393 | return -EAGAIN; | |
1394 | ||
24172f39 | 1395 | local_bh_disable(); |
48dffd39 | 1396 | iwl_op_mode_nic_error(trans->op_mode); |
24172f39 | 1397 | local_bh_enable(); |
48dffd39 JB |
1398 | |
1399 | return count; | |
1400 | } | |
1401 | ||
1f7b6172 | 1402 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1403 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1404 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1405 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1406 | DEBUGFS_WRITE_FILE_OPS(csr); |
48dffd39 | 1407 | DEBUGFS_WRITE_FILE_OPS(fw_restart); |
87e5666c EG |
1408 | |
1409 | /* | |
1410 | * Create the debugfs files and directories | |
1411 | * | |
1412 | */ | |
1413 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1414 | struct dentry *dir) |
87e5666c | 1415 | { |
87e5666c EG |
1416 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1417 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1418 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1419 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1420 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
48dffd39 | 1421 | DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR); |
87e5666c | 1422 | return 0; |
9da987ac MV |
1423 | |
1424 | err: | |
1425 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1426 | return -ENOMEM; | |
87e5666c EG |
1427 | } |
1428 | #else | |
1429 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 JB |
1430 | struct dentry *dir) |
1431 | { | |
1432 | return 0; | |
1433 | } | |
87e5666c EG |
1434 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
1435 | ||
d1ff5253 | 1436 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 1437 | .start_hw = iwl_trans_pcie_start_hw, |
cc56feb2 | 1438 | .stop_hw = iwl_trans_pcie_stop_hw, |
ed6a3803 | 1439 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 1440 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 1441 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 1442 | |
ddaf5a5b JB |
1443 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
1444 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 1445 | |
f02831be | 1446 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 1447 | |
e6bb4c9c | 1448 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1449 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1450 | |
d0624be6 | 1451 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 1452 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 1453 | |
87e5666c | 1454 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 1455 | |
990aa6d7 | 1456 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
5f178cd2 | 1457 | |
c01a4047 | 1458 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1459 | .suspend = iwl_trans_pcie_suspend, |
1460 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 1461 | #endif |
03905495 EG |
1462 | .write8 = iwl_trans_pcie_write8, |
1463 | .write32 = iwl_trans_pcie_write32, | |
1464 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
1465 | .read_prph = iwl_trans_pcie_read_prph, |
1466 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
1467 | .read_mem = iwl_trans_pcie_read_mem, |
1468 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 1469 | .configure = iwl_trans_pcie_configure, |
47107e84 | 1470 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 1471 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
1472 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
1473 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
e6bb4c9c | 1474 | }; |
a42a1844 | 1475 | |
87ce05a2 | 1476 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
1477 | const struct pci_device_id *ent, |
1478 | const struct iwl_cfg *cfg) | |
a42a1844 | 1479 | { |
a42a1844 EG |
1480 | struct iwl_trans_pcie *trans_pcie; |
1481 | struct iwl_trans *trans; | |
1482 | u16 pci_cmd; | |
1483 | int err; | |
1484 | ||
1485 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 1486 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
a42a1844 | 1487 | |
dbeca583 | 1488 | if (!trans) |
a42a1844 EG |
1489 | return NULL; |
1490 | ||
1491 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1492 | ||
1493 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 1494 | trans->cfg = cfg; |
2bfb5092 | 1495 | trans_lockdep_init(trans); |
a42a1844 | 1496 | trans_pcie->trans = trans; |
7b11488f | 1497 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 1498 | spin_lock_init(&trans_pcie->reg_lock); |
13df1aab | 1499 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 EG |
1500 | |
1501 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
1502 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
1503 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
20d3b647 | 1504 | PCIE_LINK_STATE_CLKPM); |
a42a1844 EG |
1505 | |
1506 | if (pci_enable_device(pdev)) { | |
1507 | err = -ENODEV; | |
1508 | goto out_no_pci; | |
1509 | } | |
1510 | ||
1511 | pci_set_master(pdev); | |
1512 | ||
1513 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1514 | if (!err) | |
1515 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1516 | if (err) { | |
1517 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1518 | if (!err) | |
1519 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 1520 | DMA_BIT_MASK(32)); |
a42a1844 EG |
1521 | /* both attempts failed: */ |
1522 | if (err) { | |
6a4b09f8 | 1523 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
1524 | goto out_pci_disable_device; |
1525 | } | |
1526 | } | |
1527 | ||
1528 | err = pci_request_regions(pdev, DRV_NAME); | |
1529 | if (err) { | |
6a4b09f8 | 1530 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
1531 | goto out_pci_disable_device; |
1532 | } | |
1533 | ||
05f5b97e | 1534 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 1535 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 1536 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
1537 | err = -ENODEV; |
1538 | goto out_pci_release_regions; | |
1539 | } | |
1540 | ||
a42a1844 EG |
1541 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
1542 | * PCI Tx retries from interfering with C3 CPU state */ | |
1543 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
1544 | ||
1545 | err = pci_enable_msi(pdev); | |
9f904b38 | 1546 | if (err) { |
6a4b09f8 | 1547 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
1548 | /* enable rfkill interrupt: hw bug w/a */ |
1549 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1550 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
1551 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1552 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1553 | } | |
1554 | } | |
a42a1844 EG |
1555 | |
1556 | trans->dev = &pdev->dev; | |
a42a1844 | 1557 | trans_pcie->pci_dev = pdev; |
08079a49 | 1558 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
99673ee5 | 1559 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
1560 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
1561 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 1562 | |
69a10b29 | 1563 | /* Initialize the wait queue for commands */ |
f946b529 | 1564 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 1565 | |
3ec45882 JB |
1566 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
1567 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
1568 | |
1569 | trans->dev_cmd_headroom = 0; | |
1570 | trans->dev_cmd_pool = | |
3ec45882 | 1571 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
1572 | sizeof(struct iwl_device_cmd) |
1573 | + trans->dev_cmd_headroom, | |
1574 | sizeof(void *), | |
1575 | SLAB_HWCACHE_ALIGN, | |
1576 | NULL); | |
1577 | ||
1578 | if (!trans->dev_cmd_pool) | |
1579 | goto out_pci_disable_msi; | |
1580 | ||
a8b691e6 JB |
1581 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1582 | ||
a8b691e6 JB |
1583 | if (iwl_pcie_alloc_ict(trans)) |
1584 | goto out_free_cmd_pool; | |
1585 | ||
2bfb5092 JB |
1586 | if (request_threaded_irq(pdev->irq, iwl_pcie_isr_ict, |
1587 | iwl_pcie_irq_handler, | |
1588 | IRQF_SHARED, DRV_NAME, trans)) { | |
a8b691e6 JB |
1589 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
1590 | goto out_free_ict; | |
1591 | } | |
1592 | ||
a42a1844 EG |
1593 | return trans; |
1594 | ||
a8b691e6 JB |
1595 | out_free_ict: |
1596 | iwl_pcie_free_ict(trans); | |
1597 | out_free_cmd_pool: | |
1598 | kmem_cache_destroy(trans->dev_cmd_pool); | |
59c647b6 EG |
1599 | out_pci_disable_msi: |
1600 | pci_disable_msi(pdev); | |
a42a1844 EG |
1601 | out_pci_release_regions: |
1602 | pci_release_regions(pdev); | |
1603 | out_pci_disable_device: | |
1604 | pci_disable_device(pdev); | |
1605 | out_no_pci: | |
1606 | kfree(trans); | |
1607 | return NULL; | |
1608 | } |