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iwlwifi: mvm: enable watchdog on Tx queues for mvm
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
c85eb619
EG		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8b4139dc 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
c85eb619
EG		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
a42a1844
EG		 65#include <linux/pci.h>
66#include <linux/pci-aspm.h>
e6bb4c9c 67#include <linux/interrupt.h>
87e5666c 68#include <linux/debugfs.h>
cf614297 69#include <linux/sched.h>
6d8f6eeb
EG		 70#include <linux/bitops.h>
71#include <linux/gfp.h>
48eb7b34 72#include <linux/vmalloc.h>
e6bb4c9c 73
82575102 74#include "iwl-drv.h"
c85eb619 75#include "iwl-trans.h"
522376d2
EG		 76#include "iwl-csr.h"
77#include "iwl-prph.h"
cb6bb128 78#include "iwl-scd.h"
7a10e3e4 79#include "iwl-agn-hw.h"
4d075007 80#include "iwl-fw-error-dump.h"
6468a01a 81#include "internal.h"
06d51e0d 82#include "iwl-fh.h"
0439bb62 83
fe45773b
AN		 84/* extended range in FW SRAM */
85#define IWL_FW_MEM_EXTENDED_START 0x40000
86#define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
c2d20201
EG		 88static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89{
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102}
103
104static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
105{
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
107 struct page *page;
108 dma_addr_t phys;
109 u32 size;
110 u8 power;
111
112 if (trans_pcie->fw_mon_page) {
113 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
114 trans_pcie->fw_mon_size,
115 DMA_FROM_DEVICE);
116 return;
117 }
118
119 phys = 0;
120 for (power = 26; power >= 11; power--) {
121 int order;
122
123 size = BIT(power);
124 order = get_order(size);
125 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
126 order);
127 if (!page)
128 continue;
129
130 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
131 DMA_FROM_DEVICE);
132 if (dma_mapping_error(trans->dev, phys)) {
133 __free_pages(page, order);
134 continue;
135 }
136 IWL_INFO(trans,
137 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
138 size, order);
139 break;
140 }
141
40a76905 142 if (WARN_ON_ONCE(!page))
c2d20201
EG		 143 return;
144
145 trans_pcie->fw_mon_page = page;
146 trans_pcie->fw_mon_phys = phys;
147 trans_pcie->fw_mon_size = size;
148}
149
a812cba9
AB		 150static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
151{
152 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
153 ((reg & 0x0000ffff) | (2 << 28)));
154 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
155}
156
157static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
158{
159 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
160 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
161 ((reg & 0x0000ffff) | (3 << 28)));
162}
163
ddaf5a5b 164static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 165{
ddaf5a5b
JB		 166 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
167 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
168 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
169 ~APMG_PS_CTRL_MSK_PWR_SRC);
170 else
171 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
172 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
173 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 174}
175
af634bee
EG		 176/* PCI registers */
177#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 178
7afe3705 179static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 180{
20d3b647 181 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 182 u16 lctl;
9180ac50 183 u16 cap;
af634bee 184
af634bee
EG		 185 /*
186 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
187 * Check if BIOS (or OS) enabled L1-ASPM on this device.
188 * If so (likely), disable L0S, so device moves directly L0->L1;
189 * costs negligible amount of power savings.
190 * If not (unlikely), enable L0S, so there is at least some
191 * power savings, even without L1.
192 */
7afe3705 193 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
9180ac50 194 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
af634bee 195 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
9180ac50 196 else
af634bee 197 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
438a0f0a 198 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
9180ac50
EG		 199
200 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
201 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
202 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
203 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
204 trans->ltr_enabled ? "En" : "Dis");
af634bee
EG		 205}
206
a6c684ee
EG		 207/*
208 * Start up NIC's basic functionality after it has been reset
7afe3705 209 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 210 * NOTE: This does not load uCode nor start the embedded processor
211 */
7afe3705 212static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 213{
214 int ret = 0;
215 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
216
217 /*
218 * Use "set_bit" below rather than "write", to preserve any hardware
219 * bits already set by default after reset.
220 */
221
222 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 223 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
224 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
225 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 226
227 /*
228 * Disable L0s without affecting L1;
229 * don't wait for ICH L0s (ICH bug W/A)
230 */
231 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 232 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 233
234 /* Set FH wait threshold to maximum (HW error during stress W/A) */
235 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
236
237 /*
238 * Enable HAP INTA (interrupt from management bus) to
239 * wake device's PCI Express link L1a -> L0s
240 */
241 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 242 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 243
7afe3705 244 iwl_pcie_apm_config(trans);
a6c684ee
EG		 245
246 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 247 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 248 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 249 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 250
251 /*
252 * Set "initialization complete" bit to move adapter from
253 * D0U* --> D0A* (powered-up active) state.
254 */
255 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
256
257 /*
258 * Wait for clock stabilization; once stabilized, access to
259 * device-internal resources is supported, e.g. iwl_write_prph()
260 * and accesses to uCode SRAM.
261 */
262 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
264 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 265 if (ret < 0) {
266 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
267 goto out;
268 }
269
2d93aee1
EG		 270 if (trans->cfg->host_interrupt_operation_mode) {
271 /*
272 * This is a bit of an abuse - This is needed for 7260 / 3160
273 * only check host_interrupt_operation_mode even if this is
274 * not related to host_interrupt_operation_mode.
275 *
276 * Enable the oscillator to count wake up time for L1 exit. This
277 * consumes slightly more power (100uA) - but allows to be sure
278 * that we wake up from L1 on time.
279 *
280 * This looks weird: read twice the same register, discard the
281 * value, set a bit, and yet again, read that same register
282 * just to discard the value. But that's the way the hardware
283 * seems to like it.
284 */
285 iwl_read_prph(trans, OSC_CLK);
286 iwl_read_prph(trans, OSC_CLK);
287 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
288 iwl_read_prph(trans, OSC_CLK);
289 iwl_read_prph(trans, OSC_CLK);
290 }
291
a6c684ee
EG		 292 /*
293 * Enable DMA clock and wait for it to stabilize.
294 *
3073d8c0
EH		 295 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
296 * bits do not disable clocks. This preserves any hardware
297 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 298 */
3073d8c0
EH		 299 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
300 iwl_write_prph(trans, APMG_CLK_EN_REG,
301 APMG_CLK_VAL_DMA_CLK_RQT);
302 udelay(20);
303
304 /* Disable L1-Active */
305 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
306 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
307
308 /* Clear the interrupt in APMG if the NIC is in RFKILL */
309 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
310 APMG_RTC_INT_STT_RFKILL);
311 }
889b1696 312
eb7ff77e 313 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 314
315out:
316 return ret;
317}
318
a812cba9
AB		 319/*
320 * Enable LP XTAL to avoid HW bug where device may consume much power if
321 * FW is not loaded after device reset. LP XTAL is disabled by default
322 * after device HW reset. Do it only if XTAL is fed by internal source.
323 * Configure device's "persistence" mode to avoid resetting XTAL again when
324 * SHRD_HW_RST occurs in S3.
325 */
326static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
327{
328 int ret;
329 u32 apmg_gp1_reg;
330 u32 apmg_xtal_cfg_reg;
331 u32 dl_cfg_reg;
332
333 /* Force XTAL ON */
334 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
335 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
336
337 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
338 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
339
340 udelay(10);
341
342 /*
343 * Set "initialization complete" bit to move adapter from
344 * D0U* --> D0A* (powered-up active) state.
345 */
346 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
347
348 /*
349 * Wait for clock stabilization; once stabilized, access to
350 * device-internal resources is possible.
351 */
352 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
355 25000);
356 if (WARN_ON(ret < 0)) {
357 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
358 /* Release XTAL ON request */
359 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
360 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
361 return;
362 }
363
364 /*
365 * Clear "disable persistence" to avoid LP XTAL resetting when
366 * SHRD_HW_RST is applied in S3.
367 */
368 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
369 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
370
371 /*
372 * Force APMG XTAL to be active to prevent its disabling by HW
373 * caused by APMG idle state.
374 */
375 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
376 SHR_APMG_XTAL_CFG_REG);
377 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
378 apmg_xtal_cfg_reg |
379 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
380
381 /*
382 * Reset entire device again - do controller reset (results in
383 * SHRD_HW_RST). Turn MAC off before proceeding.
384 */
385 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
386
387 udelay(10);
388
389 /* Enable LP XTAL by indirect access through CSR */
390 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
391 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
392 SHR_APMG_GP1_WF_XTAL_LP_EN |
393 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
394
395 /* Clear delay line clock power up */
396 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
397 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
398 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
399
400 /*
401 * Enable persistence mode to avoid LP XTAL resetting when
402 * SHRD_HW_RST is applied in S3.
403 */
404 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
405 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
406
407 /*
408 * Clear "initialization complete" bit to move adapter from
409 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
410 */
411 iwl_clear_bit(trans, CSR_GP_CNTRL,
412 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
413
414 /* Activates XTAL resources monitor */
415 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
416 CSR_MONITOR_XTAL_RESOURCES);
417
418 /* Release XTAL ON request */
419 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
420 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
421 udelay(10);
422
423 /* Release APMG XTAL */
424 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
425 apmg_xtal_cfg_reg &
426 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
427}
428
7afe3705 429static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 430{
431 int ret = 0;
432
433 /* stop device's busmaster DMA activity */
434 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
435
436 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 437 CSR_RESET_REG_FLAG_MASTER_DISABLED,
438 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
7f2ac8fb 439 if (ret < 0)
cc56feb2
EG		 440 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
441
442 IWL_DEBUG_INFO(trans, "stop master\n");
443
444 return ret;
445}
446
b7aaeae4 447static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
cc56feb2
EG		 448{
449 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
450
b7aaeae4
EG		 451 if (op_mode_leave) {
452 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
453 iwl_pcie_apm_init(trans);
454
455 /* inform ME that we are leaving */
456 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
457 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
458 APMG_PCIDEV_STT_VAL_WAKE_ME);
459 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
460 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
461 CSR_HW_IF_CONFIG_REG_PREPARE |
462 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
463 mdelay(5);
464 }
465
eb7ff77e 466 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 467
468 /* Stop device's DMA activity */
7afe3705 469 iwl_pcie_apm_stop_master(trans);
cc56feb2 470
a812cba9
AB		 471 if (trans->cfg->lp_xtal_workaround) {
472 iwl_pcie_apm_lp_xtal_enable(trans);
473 return;
474 }
475
cc56feb2
EG		 476 /* Reset the entire device */
477 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
478
479 udelay(10);
480
481 /*
482 * Clear "initialization complete" bit to move adapter from
483 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
484 */
485 iwl_clear_bit(trans, CSR_GP_CNTRL,
486 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
487}
488
7afe3705 489static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 490{
7b11488f 491 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 492
493 /* nic_init */
7b70bd63 494 spin_lock(&trans_pcie->irq_lock);
7afe3705 495 iwl_pcie_apm_init(trans);
392f8b78 496
7b70bd63 497 spin_unlock(&trans_pcie->irq_lock);
392f8b78 498
3073d8c0
EH		 499 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
500 iwl_pcie_set_pwr(trans, false);
392f8b78 501
ecdb975c 502 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 503
504 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 505 iwl_pcie_rx_init(trans);
392f8b78
EG		 506
507 /* Allocate or reset and init all Tx and Command queues */
f02831be 508 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 509 return -ENOMEM;
510
035f7ff2 511 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 512 /* enable shadow regs in HW */
20d3b647 513 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 514 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 515 }
516
392f8b78
EG		 517 return 0;
518}
519
520#define HW_READY_TIMEOUT (50)
521
522/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 523static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 524{
525 int ret;
526
1042db2a 527 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 528 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 529
530 /* See if we got it */
1042db2a 531 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 532 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
533 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
534 HW_READY_TIMEOUT);
392f8b78 535
6a08f514
EG		 536 if (ret >= 0)
537 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
538
6d8f6eeb 539 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 540 return ret;
541}
542
543/* Note: returns standard 0/-ERROR code */
7afe3705 544static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 545{
546 int ret;
289e5501 547 int t = 0;
501fd989 548 int iter;
392f8b78 549
6d8f6eeb 550 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 551
7afe3705 552 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 553 /* If the card is ready, exit 0 */
392f8b78
EG		 554 if (ret >= 0)
555 return 0;
556
501fd989
EG		 557 for (iter = 0; iter < 10; iter++) {
558 /* If HW is not ready, prepare the conditions to check again */
559 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
560 CSR_HW_IF_CONFIG_REG_PREPARE);
561
562 do {
563 ret = iwl_pcie_set_hw_ready(trans);
564 if (ret >= 0)
565 return 0;
392f8b78 566
501fd989
EG		 567 usleep_range(200, 1000);
568 t += 200;
569 } while (t < 150000);
570 msleep(25);
571 }
392f8b78 572
7f2ac8fb 573 IWL_ERR(trans, "Couldn't prepare the card\n");
392f8b78 574
392f8b78
EG		 575 return ret;
576}
577
cf614297
EG		 578/*
579 * ucode
580 */
7afe3705 581static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 582 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 583{
13df1aab 584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 585 int ret;
586
13df1aab 587 trans_pcie->ucode_write_complete = false;
cf614297
EG		 588
589 iwl_write_direct32(trans,
20d3b647
JB		 590 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
591 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 592
593 iwl_write_direct32(trans,
20d3b647
JB		 594 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
595 dst_addr);
cf614297
EG		 596
597 iwl_write_direct32(trans,
83f84d7b
JB		 598 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
599 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 600
601 iwl_write_direct32(trans,
20d3b647
JB		 602 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
603 (iwl_get_dma_hi_addr(phy_addr)
604 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 605
606 iwl_write_direct32(trans,
20d3b647
JB		 607 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
608 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
609 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
610 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 611
612 iwl_write_direct32(trans,
20d3b647
JB		 613 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
614 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
615 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
616 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 617
13df1aab
JB		 618 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
619 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 620 if (!ret) {
83f84d7b 621 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 622 return -ETIMEDOUT;
623 }
624
625 return 0;
626}
627
7afe3705 628static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 629 const struct fw_desc *section)
cf614297 630{
83f84d7b
JB		 631 u8 *v_addr;
632 dma_addr_t p_addr;
baa21e83 633 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
cf614297
EG		 634 int ret = 0;
635
83f84d7b
JB		 636 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
637 section_num);
638
c571573a
EG		 639 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
640 GFP_KERNEL | __GFP_NOWARN);
641 if (!v_addr) {
642 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
643 chunk_sz = PAGE_SIZE;
644 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
645 &p_addr, GFP_KERNEL);
646 if (!v_addr)
647 return -ENOMEM;
648 }
83f84d7b 649
c571573a 650 for (offset = 0; offset < section->len; offset += chunk_sz) {
fe45773b
AN		 651 u32 copy_size, dst_addr;
652 bool extended_addr = false;
83f84d7b 653
c571573a 654 copy_size = min_t(u32, chunk_sz, section->len - offset);
fe45773b
AN		 655 dst_addr = section->offset + offset;
656
657 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
658 dst_addr <= IWL_FW_MEM_EXTENDED_END)
659 extended_addr = true;
660
661 if (extended_addr)
662 iwl_set_bits_prph(trans, LMPM_CHICK,
663 LMPM_CHICK_EXTENDED_ADDR_SPACE);
cf614297 664
83f84d7b 665 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
fe45773b
AN		 666 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
667 copy_size);
668
669 if (extended_addr)
670 iwl_clear_bits_prph(trans, LMPM_CHICK,
671 LMPM_CHICK_EXTENDED_ADDR_SPACE);
672
83f84d7b
JB		 673 if (ret) {
674 IWL_ERR(trans,
675 "Could not load the [%d] uCode section\n",
676 section_num);
677 break;
6dfa8d01 678 }
83f84d7b
JB		 679 }
680
c571573a 681 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 682 return ret;
683}
684
dcab8ecd
EH		 685static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
686 const struct fw_img *image,
687 int cpu,
688 int *first_ucode_section)
e2d6f4e7
EH		 689{
690 int shift_param;
dcab8ecd
EH		 691 int i, ret = 0, sec_num = 0x1;
692 u32 val, last_read_idx = 0;
e2d6f4e7
EH		 693
694 if (cpu == 1) {
695 shift_param = 0;
034846cf 696 *first_ucode_section = 0;
e2d6f4e7
EH		 697 } else {
698 shift_param = 16;
034846cf 699 (*first_ucode_section)++;
e2d6f4e7
EH		 700 }
701
034846cf
EH		 702 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
703 last_read_idx = i;
704
705 if (!image->sec[i].data ||
706 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
707 IWL_DEBUG_FW(trans,
708 "Break since Data not valid or Empty section, sec = %d\n",
709 i);
189fa2fa 710 break;
034846cf
EH		 711 }
712
189fa2fa
EH		 713 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
714 if (ret)
715 return ret;
dcab8ecd
EH		 716
717 /* Notify the ucode of the loaded section number and status */
718 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
719 val = val | (sec_num << shift_param);
720 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
721 sec_num = (sec_num << 1) | 0x1;
e2d6f4e7
EH		 722 }
723
034846cf
EH		 724 *first_ucode_section = last_read_idx;
725
afb88917
EH		 726 if (cpu == 1)
727 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
728 else
729 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
730
189fa2fa
EH		 731 return 0;
732}
e2d6f4e7 733
189fa2fa
EH		 734static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
735 const struct fw_img *image,
034846cf
EH		 736 int cpu,
737 int *first_ucode_section)
189fa2fa
EH		 738{
739 int shift_param;
189fa2fa 740 int i, ret = 0;
034846cf 741 u32 last_read_idx = 0;
189fa2fa
EH		 742
743 if (cpu == 1) {
744 shift_param = 0;
034846cf 745 *first_ucode_section = 0;
189fa2fa
EH		 746 } else {
747 shift_param = 16;
034846cf 748 (*first_ucode_section)++;
189fa2fa
EH		 749 }
750
034846cf
EH		 751 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
752 last_read_idx = i;
753
754 if (!image->sec[i].data ||
755 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
756 IWL_DEBUG_FW(trans,
757 "Break since Data not valid or Empty section, sec = %d\n",
758 i);
189fa2fa 759 break;
034846cf
EH		 760 }
761
189fa2fa
EH		 762 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
763 if (ret)
764 return ret;
e2d6f4e7
EH		 765 }
766
189fa2fa
EH		 767 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
768 iwl_set_bits_prph(trans,
769 CSR_UCODE_LOAD_STATUS_ADDR,
770 (LMPM_CPU_UCODE_LOADING_COMPLETED |
771 LMPM_CPU_HDRS_LOADING_COMPLETED |
772 LMPM_CPU_UCODE_LOADING_STARTED) <<
773 shift_param);
774
034846cf
EH		 775 *first_ucode_section = last_read_idx;
776
e2d6f4e7
EH		 777 return 0;
778}
779
09e350f7
LK		 780static void iwl_pcie_apply_destination(struct iwl_trans *trans)
781{
782 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
783 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
784 int i;
785
786 if (dest->version)
787 IWL_ERR(trans,
788 "DBG DEST version is %d - expect issues\n",
789 dest->version);
790
791 IWL_INFO(trans, "Applying debug destination %s\n",
792 get_fw_dbg_mode_string(dest->monitor_mode));
793
794 if (dest->monitor_mode == EXTERNAL_MODE)
795 iwl_pcie_alloc_fw_monitor(trans);
796 else
797 IWL_WARN(trans, "PCI should have external buffer debug\n");
798
799 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
800 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
801 u32 val = le32_to_cpu(dest->reg_ops[i].val);
802
803 switch (dest->reg_ops[i].op) {
804 case CSR_ASSIGN:
805 iwl_write32(trans, addr, val);
806 break;
807 case CSR_SETBIT:
808 iwl_set_bit(trans, addr, BIT(val));
809 break;
810 case CSR_CLEARBIT:
811 iwl_clear_bit(trans, addr, BIT(val));
812 break;
813 case PRPH_ASSIGN:
814 iwl_write_prph(trans, addr, val);
815 break;
816 case PRPH_SETBIT:
817 iwl_set_bits_prph(trans, addr, BIT(val));
818 break;
819 case PRPH_CLEARBIT:
820 iwl_clear_bits_prph(trans, addr, BIT(val));
821 break;
822 default:
823 IWL_ERR(trans, "FW debug - unknown OP %d\n",
824 dest->reg_ops[i].op);
825 break;
826 }
827 }
828
829 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
830 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
831 trans_pcie->fw_mon_phys >> dest->base_shift);
832 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
833 (trans_pcie->fw_mon_phys +
834 trans_pcie->fw_mon_size) >> dest->end_shift);
835 }
836}
837
7afe3705 838static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 839 const struct fw_img *image)
cf614297 840{
c2d20201 841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
189fa2fa 842 int ret = 0;
034846cf 843 int first_ucode_section;
cf614297 844
dcab8ecd 845 IWL_DEBUG_FW(trans, "working with %s CPU\n",
e2d6f4e7
EH		 846 image->is_dual_cpus ? "Dual" : "Single");
847
dcab8ecd
EH		 848 /* load to FW the binary non secured sections of CPU1 */
849 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
850 if (ret)
851 return ret;
e2d6f4e7
EH		 852
853 if (image->is_dual_cpus) {
189fa2fa
EH		 854 /* set CPU2 header address */
855 iwl_write_prph(trans,
856 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
857 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 858
189fa2fa 859 /* load to FW the binary sections of CPU2 */
dcab8ecd
EH		 860 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
861 &first_ucode_section);
189fa2fa
EH		 862 if (ret)
863 return ret;
e2d6f4e7 864 }
cf614297 865
c2d20201
EG		 866 /* supported for 7000 only for the moment */
867 if (iwlwifi_mod_params.fw_monitor &&
868 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
869 iwl_pcie_alloc_fw_monitor(trans);
870
871 if (trans_pcie->fw_mon_size) {
872 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
873 trans_pcie->fw_mon_phys >> 4);
874 iwl_write_prph(trans, MON_BUFF_END_ADDR,
875 (trans_pcie->fw_mon_phys +
876 trans_pcie->fw_mon_size) >> 4);
877 }
09e350f7
LK		 878 } else if (trans->dbg_dest_tlv) {
879 iwl_pcie_apply_destination(trans);
c2d20201
EG		 880 }
881
e12ba844
EH		 882 /* release CPU reset */
883 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
884 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
885 else
886 iwl_write32(trans, CSR_RESET, 0);
887
dcab8ecd
EH		 888 return 0;
889}
189fa2fa 890
dcab8ecd
EH		 891static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
892 const struct fw_img *image)
893{
894 int ret = 0;
895 int first_ucode_section;
896 u32 reg;
897
898 IWL_DEBUG_FW(trans, "working with %s CPU\n",
899 image->is_dual_cpus ? "Dual" : "Single");
900
901 /* configure the ucode to be ready to get the secured image */
902 /* release CPU reset */
903 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
904
905 /* load to FW the binary Secured sections of CPU1 */
906 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
907 &first_ucode_section);
908 if (ret)
909 return ret;
910
911 /* load to FW the binary sections of CPU2 */
912 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
913 &first_ucode_section);
914 if (ret)
915 return ret;
916
ff298624
EH		 917 if (trans->dbg_dest_tlv)
918 iwl_pcie_apply_destination(trans);
919
dcab8ecd
EH		 920 /* wait for image verification to complete */
921 ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
922 LMPM_SECURE_BOOT_STATUS_SUCCESS,
923 LMPM_SECURE_BOOT_STATUS_SUCCESS,
924 LMPM_SECURE_TIME_OUT);
925 if (ret < 0) {
926 reg = iwl_read_prph(trans,
927 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
928
929 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
930 reg);
931 return ret;
189fa2fa
EH		 932 }
933
cf614297
EG		 934 return 0;
935}
936
0692fe41 937static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 938 const struct fw_img *fw, bool run_in_rfkill)
392f8b78 939{
7616f334 940 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78 941 int ret;
c9eec95c 942 bool hw_rfkill;
392f8b78 943
496bab39 944 /* This may fail if AMT took ownership of the device */
7afe3705 945 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 946 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 947 return -EIO;
948 }
949
8c46bb70
EG		 950 iwl_enable_rfkill_int(trans);
951
392f8b78 952 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 953 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 954 if (hw_rfkill)
eb7ff77e 955 set_bit(STATUS_RFKILL, &trans->status);
4620020b 956 else
eb7ff77e 957 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 958 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 959 if (hw_rfkill && !run_in_rfkill)
392f8b78 960 return -ERFKILL;
392f8b78 961
1042db2a 962 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 963
7afe3705 964 ret = iwl_pcie_nic_init(trans);
392f8b78 965 if (ret) {
6d8f6eeb 966 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 967 return ret;
968 }
969
7616f334
EP		 970 /* init ref_count to 1 (should be cleared when ucode is loaded) */
971 trans_pcie->ref_count = 1;
972
392f8b78 973 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 974 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
975 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 976 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
977
978 /* clear (again), then enable host interrupts */
1042db2a 979 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 980 iwl_enable_interrupts(trans);
392f8b78
EG		 981
982 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 983 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
984 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 985
cf614297 986 /* Load the given image to the HW */
dcab8ecd 987 if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
716e48a6 988 (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP))
dcab8ecd
EH		 989 return iwl_pcie_load_given_ucode_8000b(trans, fw);
990 else
991 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 992}
993
adca1235 994static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 995{
990aa6d7 996 iwl_pcie_reset_ict(trans);
f02831be 997 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 998}
999
43e58856 1000static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 1001{
43e58856 1002 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 1003 bool hw_rfkill, was_hw_rfkill;
1004
1005 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 1006
43e58856 1007 /* tell the device to stop sending interrupts */
7b70bd63 1008 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 1009 iwl_disable_interrupts(trans);
7b70bd63 1010 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 1011
ab6cf8e8 1012 /* device going down, Stop using ICT table */
990aa6d7 1013 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 1014
1015 /*
1016 * If a HW restart happens during firmware loading,
1017 * then the firmware loading might call this function
1018 * and later it might be called again due to the
1019 * restart. So don't process again if the device is
1020 * already dead.
1021 */
31b8b343
EG		 1022 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1023 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
f02831be 1024 iwl_pcie_tx_stop(trans);
9805c446 1025 iwl_pcie_rx_stop(trans);
6379103e 1026
ab6cf8e8 1027 /* Power-down device's busmaster DMA clocks */
1042db2a 1028 iwl_write_prph(trans, APMG_CLK_DIS_REG,
ab6cf8e8
EG		 1029 APMG_CLK_VAL_DMA_CLK_RQT);
1030 udelay(5);
1031 }
1032
1033 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 1034 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 1035 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 1036
1037 /* Stop the device, and put it in low power state */
b7aaeae4 1038 iwl_pcie_apm_stop(trans, false);
43e58856 1039
03d6c3b0
EG		 1040 /* stop and reset the on-board processor */
1041 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1042 udelay(20);
1043
1044 /*
1045 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1046 * This is a bug in certain verions of the hardware.
1047 * Certain devices also keep sending HW RF kill interrupt all
1048 * the time, unless the interrupt is ACKed even if the interrupt
1049 * should be masked. Re-ACK all the interrupts here.
43e58856 1050 */
7b70bd63 1051 spin_lock(&trans_pcie->irq_lock);
43e58856 1052 iwl_disable_interrupts(trans);
7b70bd63 1053 spin_unlock(&trans_pcie->irq_lock);
43e58856 1054
74fda971
DF		 1055
1056 /* clear all status bits */
eb7ff77e
AN		 1057 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1058 clear_bit(STATUS_INT_ENABLED, &trans->status);
eb7ff77e
AN		 1059 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1060 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 1061
1062 /*
1063 * Even if we stop the HW, we still want the RF kill
1064 * interrupt
1065 */
1066 iwl_enable_rfkill_int(trans);
1067
1068 /*
1069 * Check again since the RF kill state may have changed while
1070 * all the interrupts were disabled, in this case we couldn't
1071 * receive the RF kill interrupt and update the state in the
1072 * op_mode.
3dc3374f
EG		 1073 * Don't call the op_mode if the rkfill state hasn't changed.
1074 * This allows the op_mode to call stop_device from the rfkill
1075 * notification without endless recursion. Under very rare
1076 * circumstances, we might have a small recursion if the rfkill
1077 * state changed exactly now while we were called from stop_device.
1078 * This is very unlikely but can happen and is supported.
a4082843
AN		 1079 */
1080 hw_rfkill = iwl_is_rfkill_set(trans);
1081 if (hw_rfkill)
eb7ff77e 1082 set_bit(STATUS_RFKILL, &trans->status);
a4082843 1083 else
eb7ff77e 1084 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 1085 if (hw_rfkill != was_hw_rfkill)
14cfca71 1086 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
655e5cf0
EG		 1087
1088 /* re-take ownership to prevent other users from stealing the deivce */
1089 iwl_pcie_prepare_card_hw(trans);
14cfca71
JB		 1090}
1091
1092void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1093{
1094 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1095 iwl_trans_pcie_stop_device(trans);
ab6cf8e8
EG		 1096}
1097
debff618 1098static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 1099{
2dd4f9f7 1100 iwl_disable_interrupts(trans);
debff618
JB		 1101
1102 /*
1103 * in testing mode, the host stays awake and the
1104 * hardware won't be reset (not even partially)
1105 */
1106 if (test)
1107 return;
1108
ddaf5a5b
JB		 1109 iwl_pcie_disable_ict(trans);
1110
2dd4f9f7
JB		 1111 iwl_clear_bit(trans, CSR_GP_CNTRL,
1112 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 1113 iwl_clear_bit(trans, CSR_GP_CNTRL,
1114 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1115
1116 /*
1117 * reset TX queues -- some of their registers reset during S3
1118 * so if we don't reset everything here the D3 image would try
1119 * to execute some invalid memory upon resume
1120 */
1121 iwl_trans_pcie_tx_reset(trans);
1122
1123 iwl_pcie_set_pwr(trans, true);
1124}
1125
1126static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 1127 enum iwl_d3_status *status,
1128 bool test)
ddaf5a5b
JB		 1129{
1130 u32 val;
1131 int ret;
1132
debff618
JB		 1133 if (test) {
1134 iwl_enable_interrupts(trans);
1135 *status = IWL_D3_STATUS_ALIVE;
1136 return 0;
1137 }
1138
ddaf5a5b
JB		 1139 /*
1140 * Also enables interrupts - none will happen as the device doesn't
1141 * know we're waking it up, only when the opmode actually tells it
1142 * after this call.
1143 */
1144 iwl_pcie_reset_ict(trans);
1145
1146 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1147 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1148
01e58a28
EG		 1149 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1150 udelay(2);
1151
ddaf5a5b
JB		 1152 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1153 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1154 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1155 25000);
7f2ac8fb 1156 if (ret < 0) {
ddaf5a5b
JB		 1157 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1158 return ret;
1159 }
1160
a3ead656
EG		 1161 iwl_pcie_set_pwr(trans, false);
1162
ddaf5a5b
JB		 1163 iwl_trans_pcie_tx_reset(trans);
1164
1165 ret = iwl_pcie_rx_init(trans);
1166 if (ret) {
1167 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1168 return ret;
1169 }
1170
a3ead656
EG		 1171 val = iwl_read32(trans, CSR_RESET);
1172 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1173 *status = IWL_D3_STATUS_RESET;
1174 else
1175 *status = IWL_D3_STATUS_ALIVE;
1176
ddaf5a5b 1177 return 0;
2dd4f9f7
JB		 1178}
1179
57a1dc89 1180static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
e6bb4c9c 1181{
c9eec95c 1182 bool hw_rfkill;
a8b691e6 1183 int err;
e6bb4c9c 1184
7afe3705 1185 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 1186 if (err) {
d6f1c316 1187 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 1188 return err;
ebb7678d 1189 }
a6c684ee 1190
2997494f 1191 /* Reset the entire device */
ce836c76 1192 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 1193
1194 usleep_range(10, 15);
1195
7afe3705 1196 iwl_pcie_apm_init(trans);
a6c684ee 1197
226c02ca
EG		 1198 /* From now on, the op_mode will be kept updated about RF kill state */
1199 iwl_enable_rfkill_int(trans);
1200
8d425517 1201 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 1202 if (hw_rfkill)
eb7ff77e 1203 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1204 else
eb7ff77e 1205 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1206 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1207
a8b691e6 1208 return 0;
e6bb4c9c
EG		 1209}
1210
a4082843 1211static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1212{
20d3b647 1213 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1214
a4082843 1215 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1216 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1217 iwl_disable_interrupts(trans);
7b70bd63 1218 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1219
b7aaeae4 1220 iwl_pcie_apm_stop(trans, true);
cc56feb2 1221
7b70bd63 1222 spin_lock(&trans_pcie->irq_lock);
218733cf 1223 iwl_disable_interrupts(trans);
7b70bd63 1224 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1225
8d96bb61 1226 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1227}
1228
03905495
EG		 1229static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1230{
05f5b97e 1231 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1232}
1233
1234static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1235{
05f5b97e 1236 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1237}
1238
1239static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1240{
05f5b97e 1241 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1242}
1243
6a06b6c1
EG		 1244static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1245{
f9477c17
AP		 1246 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1247 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1248 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1249}
1250
1251static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1252 u32 val)
1253{
1254 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1255 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1256 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1257}
1258
f14d6b39
JB		 1259static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1260{
1261 WARN_ON(1);
1262 return 0;
1263}
1264
c6f600fc 1265static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1266 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1267{
1268 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1269
1270 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1271 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
d663ee73
JB		 1272 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1273 trans_pcie->n_no_reclaim_cmds = 0;
1274 else
1275 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1276 if (trans_pcie->n_no_reclaim_cmds)
1277 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1278 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1279
b2cf410c
JB		 1280 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1281 if (trans_pcie->rx_buf_size_8k)
1282 trans_pcie->rx_page_order = get_order(8 * 1024);
1283 else
1284 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8
JB		 1285
1286 trans_pcie->wd_timeout =
1287 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
d9fb6465
JB		 1288
1289 trans_pcie->command_names = trans_cfg->command_names;
046db346 1290 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
3a736bcb 1291 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
f14d6b39
JB		 1292
1293 /* Initialize NAPI here - it should be before registering to mac80211
1294 * in the opmode but after the HW struct is allocated.
1295 * As this function may be called again in some corner cases don't
1296 * do anything if NAPI was already initialized.
1297 */
1298 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1299 init_dummy_netdev(&trans_pcie->napi_dev);
1300 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1301 &trans_pcie->napi_dev,
1302 iwl_pcie_dummy_napi_poll, 64);
1303 }
c6f600fc
MV		 1304}
1305
d1ff5253 1306void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1307{
20d3b647 1308 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1309
0aa86df6 1310 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1311
f02831be 1312 iwl_pcie_tx_free(trans);
9805c446 1313 iwl_pcie_rx_free(trans);
6379103e 1314
a8b691e6
JB		 1315 free_irq(trans_pcie->pci_dev->irq, trans);
1316 iwl_pcie_free_ict(trans);
a42a1844
EG		 1317
1318 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1319 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1320 pci_release_regions(trans_pcie->pci_dev);
1321 pci_disable_device(trans_pcie->pci_dev);
59c647b6 1322 kmem_cache_destroy(trans->dev_cmd_pool);
a42a1844 1323
f14d6b39
JB		 1324 if (trans_pcie->napi.poll)
1325 netif_napi_del(&trans_pcie->napi);
1326
c2d20201
EG		 1327 iwl_pcie_free_fw_monitor(trans);
1328
6d8f6eeb 1329 kfree(trans);
34c1b7ba
EG		 1330}
1331
47107e84
DF		 1332static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1333{
47107e84 1334 if (state)
eb7ff77e 1335 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1336 else
eb7ff77e 1337 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1338}
1339
e56b04ef
LE		 1340static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1341 unsigned long *flags)
7a65d170
EG		 1342{
1343 int ret;
cfb4e624
JB		 1344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1345
1346 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1347
b9439491
EG		 1348 if (trans_pcie->cmd_in_flight)
1349 goto out;
1350
7a65d170 1351 /* this bit wakes up the NIC */
e139dc4a
LE		 1352 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1353 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
01e58a28
EG		 1354 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1355 udelay(2);
7a65d170
EG		 1356
1357 /*
1358 * These bits say the device is running, and should keep running for
1359 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1360 * but they do not indicate that embedded SRAM is restored yet;
1361 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1362 * to/from host DRAM when sleeping/waking for power-saving.
1363 * Each direction takes approximately 1/4 millisecond; with this
1364 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1365 * series of register accesses are expected (e.g. reading Event Log),
1366 * to keep device from sleeping.
1367 *
1368 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1369 * SRAM is okay/restored. We don't check that here because this call
1370 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1371 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1372 *
1373 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1374 * and do not save/restore SRAM when power cycling.
1375 */
1376 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1377 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1378 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1379 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1380 if (unlikely(ret < 0)) {
1381 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1382 if (!silent) {
1383 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1384 WARN_ONCE(1,
1385 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1386 val);
cfb4e624 1387 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1388 return false;
1389 }
1390 }
1391
b9439491 1392out:
e56b04ef
LE		 1393 /*
1394 * Fool sparse by faking we release the lock - sparse will
1395 * track nic_access anyway.
1396 */
cfb4e624 1397 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1398 return true;
1399}
1400
e56b04ef
LE		 1401static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1402 unsigned long *flags)
7a65d170 1403{
cfb4e624 1404 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1405
cfb4e624 1406 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1407
1408 /*
1409 * Fool sparse by faking we acquiring the lock - sparse will
1410 * track nic_access anyway.
1411 */
cfb4e624 1412 __acquire(&trans_pcie->reg_lock);
e56b04ef 1413
b9439491
EG		 1414 if (trans_pcie->cmd_in_flight)
1415 goto out;
1416
e139dc4a
LE		 1417 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1418 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1419 /*
1420 * Above we read the CSR_GP_CNTRL register, which will flush
1421 * any previous writes, but we need the write that clears the
1422 * MAC_ACCESS_REQ bit to be performed before any other writes
1423 * scheduled on different CPUs (after we drop reg_lock).
1424 */
1425 mmiowb();
b9439491 1426out:
cfb4e624 1427 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1428}
1429
4fd442db
EG		 1430static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1431 void *buf, int dwords)
1432{
1433 unsigned long flags;
1434 int offs, ret = 0;
1435 u32 *vals = buf;
1436
e56b04ef 1437 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1438 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1439 for (offs = 0; offs < dwords; offs++)
1440 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1441 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1442 } else {
1443 ret = -EBUSY;
1444 }
4fd442db
EG		 1445 return ret;
1446}
1447
1448static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1449 const void *buf, int dwords)
4fd442db
EG		 1450{
1451 unsigned long flags;
1452 int offs, ret = 0;
bf0fd5da 1453 const u32 *vals = buf;
4fd442db 1454
e56b04ef 1455 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1456 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1457 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1458 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1459 vals ? vals[offs] : 0);
e56b04ef 1460 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1461 } else {
1462 ret = -EBUSY;
1463 }
4fd442db
EG		 1464 return ret;
1465}
7a65d170 1466
5f178cd2
EG		 1467#define IWL_FLUSH_WAIT_MS 2000
1468
3cafdbe6 1469static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
5f178cd2 1470{
8ad71bef 1471 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1472 struct iwl_txq *txq;
5f178cd2
EG		 1473 struct iwl_queue *q;
1474 int cnt;
1475 unsigned long now = jiffies;
1c3fea82
EG		 1476 u32 scd_sram_addr;
1477 u8 buf[16];
5f178cd2
EG		 1478 int ret = 0;
1479
1480 /* waiting for all the tx frames complete might take a while */
035f7ff2 1481 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
fa1a91fd
EG		 1482 u8 wr_ptr;
1483
9ba1947a 1484 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1485 continue;
3cafdbe6
EG		 1486 if (!test_bit(cnt, trans_pcie->queue_used))
1487 continue;
1488 if (!(BIT(cnt) & txq_bm))
1489 continue;
748fa67c
EG		 1490
1491 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
8ad71bef 1492 txq = &trans_pcie->txq[cnt];
5f178cd2 1493 q = &txq->q;
fa1a91fd
EG		 1494 wr_ptr = ACCESS_ONCE(q->write_ptr);
1495
1496 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1497 !time_after(jiffies,
1498 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1499 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1500
1501 if (WARN_ONCE(wr_ptr != write_ptr,
1502 "WR pointer moved while flushing %d -> %d\n",
1503 wr_ptr, write_ptr))
1504 return -ETIMEDOUT;
5f178cd2 1505 msleep(1);
fa1a91fd 1506 }
5f178cd2
EG		 1507
1508 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1509 IWL_ERR(trans,
1510 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1511 ret = -ETIMEDOUT;
1512 break;
1513 }
748fa67c 1514 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
5f178cd2 1515 }
1c3fea82
EG		 1516
1517 if (!ret)
1518 return 0;
1519
1520 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1521 txq->q.read_ptr, txq->q.write_ptr);
1522
1523 scd_sram_addr = trans_pcie->scd_base_addr +
1524 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1525 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1526
1527 iwl_print_hex_error(trans, buf, sizeof(buf));
1528
1529 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1530 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1531 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1532
1533 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1534 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1535 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1536 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1537 u32 tbl_dw =
1538 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1539 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1540
1541 if (cnt & 0x1)
1542 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1543 else
1544 tbl_dw = tbl_dw & 0x0000FFFF;
1545
1546 IWL_ERR(trans,
1547 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1548 cnt, active ? "" : "in", fifo, tbl_dw,
83f32a4b
JB		 1549 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1550 (TFD_QUEUE_SIZE_MAX - 1),
1c3fea82
EG		 1551 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1552 }
1553
5f178cd2
EG		 1554 return ret;
1555}
1556
e139dc4a
LE		 1557static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1558 u32 mask, u32 value)
1559{
e56b04ef 1560 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1561 unsigned long flags;
1562
e56b04ef 1563 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1564 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1565 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1566}
1567
7616f334
EP		 1568void iwl_trans_pcie_ref(struct iwl_trans *trans)
1569{
1570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1571 unsigned long flags;
1572
1573 if (iwlwifi_mod_params.d0i3_disable)
1574 return;
1575
1576 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1577 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1578 trans_pcie->ref_count++;
1579 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1580}
1581
1582void iwl_trans_pcie_unref(struct iwl_trans *trans)
1583{
1584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1585 unsigned long flags;
1586
1587 if (iwlwifi_mod_params.d0i3_disable)
1588 return;
1589
1590 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1591 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1592 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1593 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1594 return;
1595 }
1596 trans_pcie->ref_count--;
1597 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1598}
1599
ff620849
EG		 1600static const char *get_csr_string(int cmd)
1601{
d9fb6465 1602#define IWL_CMD(x) case x: return #x
ff620849
EG		 1603 switch (cmd) {
1604 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1605 IWL_CMD(CSR_INT_COALESCING);
1606 IWL_CMD(CSR_INT);
1607 IWL_CMD(CSR_INT_MASK);
1608 IWL_CMD(CSR_FH_INT_STATUS);
1609 IWL_CMD(CSR_GPIO_IN);
1610 IWL_CMD(CSR_RESET);
1611 IWL_CMD(CSR_GP_CNTRL);
1612 IWL_CMD(CSR_HW_REV);
1613 IWL_CMD(CSR_EEPROM_REG);
1614 IWL_CMD(CSR_EEPROM_GP);
1615 IWL_CMD(CSR_OTP_GP_REG);
1616 IWL_CMD(CSR_GIO_REG);
1617 IWL_CMD(CSR_GP_UCODE_REG);
1618 IWL_CMD(CSR_GP_DRIVER_REG);
1619 IWL_CMD(CSR_UCODE_DRV_GP1);
1620 IWL_CMD(CSR_UCODE_DRV_GP2);
1621 IWL_CMD(CSR_LED_REG);
1622 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1623 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1624 IWL_CMD(CSR_ANA_PLL_CFG);
1625 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1626 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1627 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1628 default:
1629 return "UNKNOWN";
1630 }
d9fb6465 1631#undef IWL_CMD
ff620849
EG		 1632}
1633
990aa6d7 1634void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1635{
1636 int i;
1637 static const u32 csr_tbl[] = {
1638 CSR_HW_IF_CONFIG_REG,
1639 CSR_INT_COALESCING,
1640 CSR_INT,
1641 CSR_INT_MASK,
1642 CSR_FH_INT_STATUS,
1643 CSR_GPIO_IN,
1644 CSR_RESET,
1645 CSR_GP_CNTRL,
1646 CSR_HW_REV,
1647 CSR_EEPROM_REG,
1648 CSR_EEPROM_GP,
1649 CSR_OTP_GP_REG,
1650 CSR_GIO_REG,
1651 CSR_GP_UCODE_REG,
1652 CSR_GP_DRIVER_REG,
1653 CSR_UCODE_DRV_GP1,
1654 CSR_UCODE_DRV_GP2,
1655 CSR_LED_REG,
1656 CSR_DRAM_INT_TBL_REG,
1657 CSR_GIO_CHICKEN_BITS,
1658 CSR_ANA_PLL_CFG,
a812cba9 1659 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1660 CSR_HW_REV_WA_REG,
1661 CSR_DBG_HPET_MEM_REG
1662 };
1663 IWL_ERR(trans, "CSR values:\n");
1664 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1665 "CSR_INT_PERIODIC_REG)\n");
1666 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1667 IWL_ERR(trans, " %25s: 0X%08x\n",
1668 get_csr_string(csr_tbl[i]),
1042db2a 1669 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1670 }
1671}
1672
87e5666c
EG		 1673#ifdef CONFIG_IWLWIFI_DEBUGFS
1674/* create and remove of files */
1675#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1676 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1677 &iwl_dbgfs_##name##_ops)) \
9da987ac 1678 goto err; \
87e5666c
EG		 1679} while (0)
1680
1681/* file operation */
87e5666c 1682#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1683static const struct file_operations iwl_dbgfs_##name##_ops = { \
1684 .read = iwl_dbgfs_##name##_read, \
234e3405 1685 .open = simple_open, \
87e5666c
EG		 1686 .llseek = generic_file_llseek, \
1687};
1688
16db88ba 1689#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1690static const struct file_operations iwl_dbgfs_##name##_ops = { \
1691 .write = iwl_dbgfs_##name##_write, \
234e3405 1692 .open = simple_open, \
16db88ba
EG		 1693 .llseek = generic_file_llseek, \
1694};
1695
87e5666c 1696#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1697static const struct file_operations iwl_dbgfs_##name##_ops = { \
1698 .write = iwl_dbgfs_##name##_write, \
1699 .read = iwl_dbgfs_##name##_read, \
234e3405 1700 .open = simple_open, \
87e5666c
EG		 1701 .llseek = generic_file_llseek, \
1702};
1703
87e5666c 1704static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1705 char __user *user_buf,
1706 size_t count, loff_t *ppos)
8ad71bef 1707{
5a878bf6 1708 struct iwl_trans *trans = file->private_data;
8ad71bef 1709 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1710 struct iwl_txq *txq;
87e5666c
EG		 1711 struct iwl_queue *q;
1712 char *buf;
1713 int pos = 0;
1714 int cnt;
1715 int ret;
1745e440
WYG		 1716 size_t bufsz;
1717
035f7ff2 1718 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
87e5666c 1719
f9e75447 1720 if (!trans_pcie->txq)
87e5666c 1721 return -EAGAIN;
f9e75447 1722
87e5666c
EG		 1723 buf = kzalloc(bufsz, GFP_KERNEL);
1724 if (!buf)
1725 return -ENOMEM;
1726
035f7ff2 1727 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1728 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1729 q = &txq->q;
1730 pos += scnprintf(buf + pos, bufsz - pos,
f40faf62 1731 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
87e5666c 1732 cnt, q->read_ptr, q->write_ptr,
9eae88fa 1733 !!test_bit(cnt, trans_pcie->queue_used),
f40faf62
AL		 1734 !!test_bit(cnt, trans_pcie->queue_stopped),
1735 txq->need_update,
1736 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
87e5666c
EG		 1737 }
1738 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1739 kfree(buf);
1740 return ret;
1741}
1742
1743static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1744 char __user *user_buf,
1745 size_t count, loff_t *ppos)
1746{
5a878bf6 1747 struct iwl_trans *trans = file->private_data;
20d3b647 1748 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1749 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1750 char buf[256];
1751 int pos = 0;
1752 const size_t bufsz = sizeof(buf);
1753
1754 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1755 rxq->read);
1756 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1757 rxq->write);
f40faf62
AL		 1758 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1759 rxq->write_actual);
1760 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1761 rxq->need_update);
87e5666c
EG		 1762 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1763 rxq->free_count);
1764 if (rxq->rb_stts) {
1765 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1766 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1767 } else {
1768 pos += scnprintf(buf + pos, bufsz - pos,
1769 "closed_rb_num: Not Allocated\n");
1770 }
1771 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1772}
1773
1f7b6172
EG		 1774static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1775 char __user *user_buf,
20d3b647
JB		 1776 size_t count, loff_t *ppos)
1777{
1f7b6172 1778 struct iwl_trans *trans = file->private_data;
20d3b647 1779 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1780 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1781
1782 int pos = 0;
1783 char *buf;
1784 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1785 ssize_t ret;
1786
1787 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1788 if (!buf)
1f7b6172 1789 return -ENOMEM;
1f7b6172
EG		 1790
1791 pos += scnprintf(buf + pos, bufsz - pos,
1792 "Interrupt Statistics Report:\n");
1793
1794 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1795 isr_stats->hw);
1796 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1797 isr_stats->sw);
1798 if (isr_stats->sw || isr_stats->hw) {
1799 pos += scnprintf(buf + pos, bufsz - pos,
1800 "\tLast Restarting Code: 0x%X\n",
1801 isr_stats->err_code);
1802 }
1803#ifdef CONFIG_IWLWIFI_DEBUG
1804 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1805 isr_stats->sch);
1806 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1807 isr_stats->alive);
1808#endif
1809 pos += scnprintf(buf + pos, bufsz - pos,
1810 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1811
1812 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1813 isr_stats->ctkill);
1814
1815 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1816 isr_stats->wakeup);
1817
1818 pos += scnprintf(buf + pos, bufsz - pos,
1819 "Rx command responses:\t\t %u\n", isr_stats->rx);
1820
1821 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1822 isr_stats->tx);
1823
1824 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1825 isr_stats->unhandled);
1826
1827 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1828 kfree(buf);
1829 return ret;
1830}
1831
1832static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1833 const char __user *user_buf,
1834 size_t count, loff_t *ppos)
1835{
1836 struct iwl_trans *trans = file->private_data;
20d3b647 1837 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1838 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1839
1840 char buf[8];
1841 int buf_size;
1842 u32 reset_flag;
1843
1844 memset(buf, 0, sizeof(buf));
1845 buf_size = min(count, sizeof(buf) - 1);
1846 if (copy_from_user(buf, user_buf, buf_size))
1847 return -EFAULT;
1848 if (sscanf(buf, "%x", &reset_flag) != 1)
1849 return -EFAULT;
1850 if (reset_flag == 0)
1851 memset(isr_stats, 0, sizeof(*isr_stats));
1852
1853 return count;
1854}
1855
16db88ba 1856static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1857 const char __user *user_buf,
1858 size_t count, loff_t *ppos)
16db88ba
EG		 1859{
1860 struct iwl_trans *trans = file->private_data;
1861 char buf[8];
1862 int buf_size;
1863 int csr;
1864
1865 memset(buf, 0, sizeof(buf));
1866 buf_size = min(count, sizeof(buf) - 1);
1867 if (copy_from_user(buf, user_buf, buf_size))
1868 return -EFAULT;
1869 if (sscanf(buf, "%d", &csr) != 1)
1870 return -EFAULT;
1871
990aa6d7 1872 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1873
1874 return count;
1875}
1876
16db88ba 1877static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1878 char __user *user_buf,
1879 size_t count, loff_t *ppos)
16db88ba
EG		 1880{
1881 struct iwl_trans *trans = file->private_data;
94543a8d 1882 char *buf = NULL;
56c2477f 1883 ssize_t ret;
16db88ba 1884
56c2477f
JB		 1885 ret = iwl_dump_fh(trans, &buf);
1886 if (ret < 0)
1887 return ret;
1888 if (!buf)
1889 return -EINVAL;
1890 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1891 kfree(buf);
16db88ba
EG		 1892 return ret;
1893}
1894
1f7b6172 1895DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1896DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1897DEBUGFS_READ_FILE_OPS(rx_queue);
1898DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1899DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 1900
1901/*
1902 * Create the debugfs files and directories
1903 *
1904 */
1905static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 1906 struct dentry *dir)
87e5666c 1907{
87e5666c
EG		 1908 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1909 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 1910 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 1911 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1912 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 1913 return 0;
9da987ac
MV		 1914
1915err:
1916 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1917 return -ENOMEM;
87e5666c 1918}
aadede6e
JB		 1919#else
1920static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1921 struct dentry *dir)
1922{
1923 return 0;
1924}
1925#endif /*CONFIG_IWLWIFI_DEBUGFS */
4d075007
JB		 1926
1927static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1928{
1929 u32 cmdlen = 0;
1930 int i;
1931
1932 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1933 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1934
1935 return cmdlen;
1936}
1937
67c65f2c
EG		 1938static const struct {
1939 u32 start, end;
1940} iwl_prph_dump_addr[] = {
1941 { .start = 0x00a00000, .end = 0x00a00000 },
1942 { .start = 0x00a0000c, .end = 0x00a00024 },
1943 { .start = 0x00a0002c, .end = 0x00a0003c },
1944 { .start = 0x00a00410, .end = 0x00a00418 },
1945 { .start = 0x00a00420, .end = 0x00a00420 },
1946 { .start = 0x00a00428, .end = 0x00a00428 },
1947 { .start = 0x00a00430, .end = 0x00a0043c },
1948 { .start = 0x00a00444, .end = 0x00a00444 },
1949 { .start = 0x00a004c0, .end = 0x00a004cc },
1950 { .start = 0x00a004d8, .end = 0x00a004d8 },
1951 { .start = 0x00a004e0, .end = 0x00a004f0 },
1952 { .start = 0x00a00840, .end = 0x00a00840 },
1953 { .start = 0x00a00850, .end = 0x00a00858 },
1954 { .start = 0x00a01004, .end = 0x00a01008 },
1955 { .start = 0x00a01010, .end = 0x00a01010 },
1956 { .start = 0x00a01018, .end = 0x00a01018 },
1957 { .start = 0x00a01024, .end = 0x00a01024 },
1958 { .start = 0x00a0102c, .end = 0x00a01034 },
1959 { .start = 0x00a0103c, .end = 0x00a01040 },
1960 { .start = 0x00a01048, .end = 0x00a01094 },
1961 { .start = 0x00a01c00, .end = 0x00a01c20 },
1962 { .start = 0x00a01c58, .end = 0x00a01c58 },
1963 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1964 { .start = 0x00a01c28, .end = 0x00a01c54 },
1965 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1966 { .start = 0x00a01c84, .end = 0x00a01c84 },
1967 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1968 { .start = 0x00a01d18, .end = 0x00a01d20 },
1969 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1970 { .start = 0x00a01d40, .end = 0x00a01d5c },
1971 { .start = 0x00a01d80, .end = 0x00a01d80 },
1972 { .start = 0x00a01d98, .end = 0x00a01d98 },
1973 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1974 { .start = 0x00a01e00, .end = 0x00a01e2c },
1975 { .start = 0x00a01e40, .end = 0x00a01e60 },
1976 { .start = 0x00a01e84, .end = 0x00a01e90 },
1977 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1978 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1979 { .start = 0x00a01f00, .end = 0x00a01f14 },
1980 { .start = 0x00a01f44, .end = 0x00a01f58 },
1981 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1982 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1983 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1984 { .start = 0x00a02000, .end = 0x00a02048 },
1985 { .start = 0x00a02068, .end = 0x00a020f0 },
1986 { .start = 0x00a02100, .end = 0x00a02118 },
1987 { .start = 0x00a02140, .end = 0x00a0214c },
1988 { .start = 0x00a02168, .end = 0x00a0218c },
1989 { .start = 0x00a021c0, .end = 0x00a021c0 },
1990 { .start = 0x00a02400, .end = 0x00a02410 },
1991 { .start = 0x00a02418, .end = 0x00a02420 },
1992 { .start = 0x00a02428, .end = 0x00a0242c },
1993 { .start = 0x00a02434, .end = 0x00a02434 },
1994 { .start = 0x00a02440, .end = 0x00a02460 },
1995 { .start = 0x00a02468, .end = 0x00a024b0 },
1996 { .start = 0x00a024c8, .end = 0x00a024cc },
1997 { .start = 0x00a02500, .end = 0x00a02504 },
1998 { .start = 0x00a0250c, .end = 0x00a02510 },
1999 { .start = 0x00a02540, .end = 0x00a02554 },
2000 { .start = 0x00a02580, .end = 0x00a025f4 },
2001 { .start = 0x00a02600, .end = 0x00a0260c },
2002 { .start = 0x00a02648, .end = 0x00a02650 },
2003 { .start = 0x00a02680, .end = 0x00a02680 },
2004 { .start = 0x00a026c0, .end = 0x00a026d0 },
2005 { .start = 0x00a02700, .end = 0x00a0270c },
2006 { .start = 0x00a02804, .end = 0x00a02804 },
2007 { .start = 0x00a02818, .end = 0x00a0281c },
2008 { .start = 0x00a02c00, .end = 0x00a02db4 },
2009 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2010 { .start = 0x00a03000, .end = 0x00a03014 },
2011 { .start = 0x00a0301c, .end = 0x00a0302c },
2012 { .start = 0x00a03034, .end = 0x00a03038 },
2013 { .start = 0x00a03040, .end = 0x00a03048 },
2014 { .start = 0x00a03060, .end = 0x00a03068 },
2015 { .start = 0x00a03070, .end = 0x00a03074 },
2016 { .start = 0x00a0307c, .end = 0x00a0307c },
2017 { .start = 0x00a03080, .end = 0x00a03084 },
2018 { .start = 0x00a0308c, .end = 0x00a03090 },
2019 { .start = 0x00a03098, .end = 0x00a03098 },
2020 { .start = 0x00a030a0, .end = 0x00a030a0 },
2021 { .start = 0x00a030a8, .end = 0x00a030b4 },
2022 { .start = 0x00a030bc, .end = 0x00a030bc },
2023 { .start = 0x00a030c0, .end = 0x00a0312c },
2024 { .start = 0x00a03c00, .end = 0x00a03c5c },
2025 { .start = 0x00a04400, .end = 0x00a04454 },
2026 { .start = 0x00a04460, .end = 0x00a04474 },
2027 { .start = 0x00a044c0, .end = 0x00a044ec },
2028 { .start = 0x00a04500, .end = 0x00a04504 },
2029 { .start = 0x00a04510, .end = 0x00a04538 },
2030 { .start = 0x00a04540, .end = 0x00a04548 },
2031 { .start = 0x00a04560, .end = 0x00a0457c },
2032 { .start = 0x00a04590, .end = 0x00a04598 },
2033 { .start = 0x00a045c0, .end = 0x00a045f4 },
2034};
2035
2036static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2037 struct iwl_fw_error_dump_data **data)
2038{
2039 struct iwl_fw_error_dump_prph *prph;
2040 unsigned long flags;
2041 u32 prph_len = 0, i;
2042
2043 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2044 return 0;
2045
2046 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2047 /* The range includes both boundaries */
2048 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2049 iwl_prph_dump_addr[i].start + 4;
2050 int reg;
2051 __le32 *val;
2052
87dd634a 2053 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
67c65f2c
EG		 2054
2055 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2056 (*data)->len = cpu_to_le32(sizeof(*prph) +
2057 num_bytes_in_chunk);
2058 prph = (void *)(*data)->data;
2059 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2060 val = (void *)prph->data;
2061
2062 for (reg = iwl_prph_dump_addr[i].start;
2063 reg <= iwl_prph_dump_addr[i].end;
2064 reg += 4)
2065 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2066 reg));
2067 *data = iwl_fw_error_next_data(*data);
2068 }
2069
2070 iwl_trans_release_nic_access(trans, &flags);
2071
2072 return prph_len;
2073}
2074
473ad712
EG		 2075#define IWL_CSR_TO_DUMP (0x250)
2076
2077static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2078 struct iwl_fw_error_dump_data **data)
2079{
2080 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2081 __le32 *val;
2082 int i;
2083
2084 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2085 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2086 val = (void *)(*data)->data;
2087
2088 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2089 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2090
2091 *data = iwl_fw_error_next_data(*data);
2092
2093 return csr_len;
2094}
2095
06d51e0d
LK		 2096static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2097 struct iwl_fw_error_dump_data **data)
2098{
2099 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2100 unsigned long flags;
2101 __le32 *val;
2102 int i;
2103
2104 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2105 return 0;
2106
2107 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2108 (*data)->len = cpu_to_le32(fh_regs_len);
2109 val = (void *)(*data)->data;
2110
2111 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2112 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2113
2114 iwl_trans_release_nic_access(trans, &flags);
2115
2116 *data = iwl_fw_error_next_data(*data);
2117
2118 return sizeof(**data) + fh_regs_len;
2119}
2120
48eb7b34
EG		 2121static
2122struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
4d075007
JB		 2123{
2124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2125 struct iwl_fw_error_dump_data *data;
2126 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2127 struct iwl_fw_error_dump_txcmd *txcmd;
48eb7b34 2128 struct iwl_trans_dump_data *dump_data;
4d075007 2129 u32 len;
99684ae3 2130 u32 monitor_len;
4d075007
JB		 2131 int i, ptr;
2132
473ad712
EG		 2133 /* transport dump header */
2134 len = sizeof(*dump_data);
2135
2136 /* host commands */
2137 len += sizeof(*data) +
c2d20201
EG		 2138 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2139
473ad712
EG		 2140 /* CSR registers */
2141 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2142
2143 /* PRPH registers */
67c65f2c
EG		 2144 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2145 /* The range includes both boundaries */
2146 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2147 iwl_prph_dump_addr[i].start + 4;
2148
2149 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2150 num_bytes_in_chunk;
2151 }
2152
06d51e0d
LK		 2153 /* FH registers */
2154 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2155
473ad712 2156 /* FW monitor */
99684ae3 2157 if (trans_pcie->fw_mon_page) {
c544e9c4 2158 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
99684ae3
LK		 2159 trans_pcie->fw_mon_size;
2160 monitor_len = trans_pcie->fw_mon_size;
2161 } else if (trans->dbg_dest_tlv) {
2162 u32 base, end;
2163
2164 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2165 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2166
2167 base = iwl_read_prph(trans, base) <<
2168 trans->dbg_dest_tlv->base_shift;
2169 end = iwl_read_prph(trans, end) <<
2170 trans->dbg_dest_tlv->end_shift;
2171
2172 /* Make "end" point to the actual end */
2173 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2174 end += (1 << trans->dbg_dest_tlv->end_shift);
2175 monitor_len = end - base;
2176 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2177 monitor_len;
2178 } else {
2179 monitor_len = 0;
2180 }
c2d20201 2181
48eb7b34
EG		 2182 dump_data = vzalloc(len);
2183 if (!dump_data)
2184 return NULL;
4d075007
JB		 2185
2186 len = 0;
48eb7b34 2187 data = (void *)dump_data->data;
4d075007
JB		 2188 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2189 txcmd = (void *)data->data;
2190 spin_lock_bh(&cmdq->lock);
2191 ptr = cmdq->q.write_ptr;
2192 for (i = 0; i < cmdq->q.n_window; i++) {
2193 u8 idx = get_cmd_index(&cmdq->q, ptr);
2194 u32 caplen, cmdlen;
2195
2196 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2197 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2198
2199 if (cmdlen) {
2200 len += sizeof(*txcmd) + caplen;
2201 txcmd->cmdlen = cpu_to_le32(cmdlen);
2202 txcmd->caplen = cpu_to_le32(caplen);
2203 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2204 txcmd = (void *)((u8 *)txcmd->data + caplen);
2205 }
2206
2207 ptr = iwl_queue_dec_wrap(ptr);
2208 }
2209 spin_unlock_bh(&cmdq->lock);
2210
2211 data->len = cpu_to_le32(len);
c2d20201 2212 len += sizeof(*data);
67c65f2c
EG		 2213 data = iwl_fw_error_next_data(data);
2214
2215 len += iwl_trans_pcie_dump_prph(trans, &data);
473ad712 2216 len += iwl_trans_pcie_dump_csr(trans, &data);
06d51e0d 2217 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
67c65f2c 2218 /* data is already pointing to the next section */
c2d20201 2219
99684ae3
LK		 2220 if ((trans_pcie->fw_mon_page &&
2221 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2222 trans->dbg_dest_tlv) {
c544e9c4 2223 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
99684ae3
LK		 2224 u32 base, write_ptr, wrap_cnt;
2225
2226 /* If there was a dest TLV - use the values from there */
2227 if (trans->dbg_dest_tlv) {
2228 write_ptr =
2229 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2230 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2231 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2232 } else {
2233 base = MON_BUFF_BASE_ADDR;
2234 write_ptr = MON_BUFF_WRPTR;
2235 wrap_cnt = MON_BUFF_CYCLE_CNT;
2236 }
c2d20201 2237
c2d20201 2238 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
c2d20201
EG		 2239 fw_mon_data = (void *)data->data;
2240 fw_mon_data->fw_mon_wr_ptr =
99684ae3 2241 cpu_to_le32(iwl_read_prph(trans, write_ptr));
c2d20201 2242 fw_mon_data->fw_mon_cycle_cnt =
99684ae3 2243 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
c2d20201 2244 fw_mon_data->fw_mon_base_ptr =
99684ae3
LK		 2245 cpu_to_le32(iwl_read_prph(trans, base));
2246
2247 len += sizeof(*data) + sizeof(*fw_mon_data);
2248 if (trans_pcie->fw_mon_page) {
2249 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2250 sizeof(*fw_mon_data));
2251
2252 /*
2253 * The firmware is now asserted, it won't write anything
2254 * to the buffer. CPU can take ownership to fetch the
2255 * data. The buffer will be handed back to the device
2256 * before the firmware will be restarted.
2257 */
2258 dma_sync_single_for_cpu(trans->dev,
2259 trans_pcie->fw_mon_phys,
2260 trans_pcie->fw_mon_size,
2261 DMA_FROM_DEVICE);
2262 memcpy(fw_mon_data->data,
2263 page_address(trans_pcie->fw_mon_page),
2264 trans_pcie->fw_mon_size);
2265
2266 len += trans_pcie->fw_mon_size;
2267 } else {
2268 /* If we are here then the buffer is internal */
2269
2270 /*
2271 * Update pointers to reflect actual values after
2272 * shifting
2273 */
2274 base = iwl_read_prph(trans, base) <<
2275 trans->dbg_dest_tlv->base_shift;
2276 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2277 monitor_len / sizeof(u32));
2278 data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2279 monitor_len);
2280 len += monitor_len;
2281 }
c2d20201
EG		 2282 }
2283
48eb7b34
EG		 2284 dump_data->len = len;
2285
2286 return dump_data;
4d075007 2287}
87e5666c 2288
d1ff5253 2289static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 2290 .start_hw = iwl_trans_pcie_start_hw,
a4082843 2291 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 2292 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 2293 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 2294 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 2295
ddaf5a5b
JB		 2296 .d3_suspend = iwl_trans_pcie_d3_suspend,
2297 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 2298
f02831be 2299 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 2300
e6bb4c9c 2301 .tx = iwl_trans_pcie_tx,
a0eaad71 2302 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 2303
d0624be6 2304 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 2305 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 2306
87e5666c 2307 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 2308
990aa6d7 2309 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
5f178cd2 2310
03905495
EG		 2311 .write8 = iwl_trans_pcie_write8,
2312 .write32 = iwl_trans_pcie_write32,
2313 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 2314 .read_prph = iwl_trans_pcie_read_prph,
2315 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 2316 .read_mem = iwl_trans_pcie_read_mem,
2317 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 2318 .configure = iwl_trans_pcie_configure,
47107e84 2319 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 2320 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 2321 .release_nic_access = iwl_trans_pcie_release_nic_access,
2322 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
4d075007 2323
7616f334
EP		 2324 .ref = iwl_trans_pcie_ref,
2325 .unref = iwl_trans_pcie_unref,
2326
4d075007 2327 .dump_data = iwl_trans_pcie_dump_data,
e6bb4c9c 2328};
a42a1844 2329
87ce05a2 2330struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 2331 const struct pci_device_id *ent,
2332 const struct iwl_cfg *cfg)
a42a1844 2333{
a42a1844
EG		 2334 struct iwl_trans_pcie *trans_pcie;
2335 struct iwl_trans *trans;
2336 u16 pci_cmd;
2337 int err;
2338
2339 trans = kzalloc(sizeof(struct iwl_trans) +
20d3b647 2340 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
6965a354
LC		 2341 if (!trans) {
2342 err = -ENOMEM;
2343 goto out;
2344 }
a42a1844
EG		 2345
2346 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2347
2348 trans->ops = &trans_ops_pcie;
035f7ff2 2349 trans->cfg = cfg;
2bfb5092 2350 trans_lockdep_init(trans);
a42a1844 2351 trans_pcie->trans = trans;
7b11488f 2352 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 2353 spin_lock_init(&trans_pcie->reg_lock);
dad33ecf 2354 spin_lock_init(&trans_pcie->ref_lock);
13df1aab 2355 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 2356
d819c6cf
JB		 2357 err = pci_enable_device(pdev);
2358 if (err)
2359 goto out_no_pci;
2360
f2532b04
EG		 2361 if (!cfg->base_params->pcie_l1_allowed) {
2362 /*
2363 * W/A - seems to solve weird behavior. We need to remove this
2364 * if we don't want to stay in L1 all the time. This wastes a
2365 * lot of power.
2366 */
2367 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2368 PCIE_LINK_STATE_L1 |
2369 PCIE_LINK_STATE_CLKPM);
2370 }
a42a1844 2371
a42a1844
EG		 2372 pci_set_master(pdev);
2373
2374 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2375 if (!err)
2376 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2377 if (err) {
2378 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2379 if (!err)
2380 err = pci_set_consistent_dma_mask(pdev,
20d3b647 2381 DMA_BIT_MASK(32));
a42a1844
EG		 2382 /* both attempts failed: */
2383 if (err) {
6a4b09f8 2384 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 2385 goto out_pci_disable_device;
2386 }
2387 }
2388
2389 err = pci_request_regions(pdev, DRV_NAME);
2390 if (err) {
6a4b09f8 2391 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 2392 goto out_pci_disable_device;
2393 }
2394
05f5b97e 2395 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 2396 if (!trans_pcie->hw_base) {
6a4b09f8 2397 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 2398 err = -ENODEV;
2399 goto out_pci_release_regions;
2400 }
2401
a42a1844
EG		 2402 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2403 * PCI Tx retries from interfering with C3 CPU state */
2404 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2405
83f7a85f
EG		 2406 trans->dev = &pdev->dev;
2407 trans_pcie->pci_dev = pdev;
2408 iwl_disable_interrupts(trans);
2409
a42a1844 2410 err = pci_enable_msi(pdev);
9f904b38 2411 if (err) {
6a4b09f8 2412 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 2413 /* enable rfkill interrupt: hw bug w/a */
2414 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2415 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2416 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2417 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2418 }
2419 }
a42a1844 2420
08079a49 2421 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
b513ee7f
LK		 2422 /*
2423 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2424 * changed, and now the revision step also includes bit 0-1 (no more
2425 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2426 * in the old format.
2427 */
2428 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2429 trans->hw_rev = (trans->hw_rev & 0xfff0) |
1fc0e221 2430 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
b513ee7f 2431
99673ee5 2432 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 2433 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2434 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 2435
69a10b29 2436 /* Initialize the wait queue for commands */
f946b529 2437 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 2438
3ec45882
JB		 2439 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2440 "iwl_cmd_pool:%s", dev_name(trans->dev));
59c647b6
EG		 2441
2442 trans->dev_cmd_headroom = 0;
2443 trans->dev_cmd_pool =
3ec45882 2444 kmem_cache_create(trans->dev_cmd_pool_name,
59c647b6
EG		 2445 sizeof(struct iwl_device_cmd)
2446 + trans->dev_cmd_headroom,
2447 sizeof(void *),
2448 SLAB_HWCACHE_ALIGN,
2449 NULL);
2450
6965a354
LC		 2451 if (!trans->dev_cmd_pool) {
2452 err = -ENOMEM;
59c647b6 2453 goto out_pci_disable_msi;
6965a354 2454 }
59c647b6 2455
a8b691e6
JB		 2456 if (iwl_pcie_alloc_ict(trans))
2457 goto out_free_cmd_pool;
2458
85bf9da1 2459 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 2460 iwl_pcie_irq_handler,
2461 IRQF_SHARED, DRV_NAME, trans);
2462 if (err) {
a8b691e6
JB		 2463 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2464 goto out_free_ict;
2465 }
2466
83f7a85f 2467 trans_pcie->inta_mask = CSR_INI_SET_MASK;
6735943f 2468 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
83f7a85f 2469
a42a1844
EG		 2470 return trans;
2471
a8b691e6
JB		 2472out_free_ict:
2473 iwl_pcie_free_ict(trans);
2474out_free_cmd_pool:
2475 kmem_cache_destroy(trans->dev_cmd_pool);
59c647b6
EG		 2476out_pci_disable_msi:
2477 pci_disable_msi(pdev);
a42a1844
EG		 2478out_pci_release_regions:
2479 pci_release_regions(pdev);
2480out_pci_disable_device:
2481 pci_disable_device(pdev);
2482out_no_pci:
2483 kfree(trans);
6965a354
LC		 2484out:
2485 return ERR_PTR(err);
a42a1844 2486}
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