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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
68 | int s = q->read_ptr - q->write_ptr; | |
69 | ||
70 | if (q->read_ptr > q->write_ptr) | |
71 | s -= q->n_bd; | |
72 | ||
73 | if (s <= 0) | |
74 | s += q->n_window; | |
75 | /* keep some reserve to not confuse empty and full situations */ | |
76 | s -= 2; | |
77 | if (s < 0) | |
78 | s = 0; | |
79 | return s; | |
80 | } | |
81 | ||
82 | /* | |
83 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
84 | */ | |
85 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
86 | { | |
87 | q->n_bd = count; | |
88 | q->n_window = slots_num; | |
89 | q->id = id; | |
90 | ||
91 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
92 | * and iwl_queue_dec_wrap are broken. */ | |
93 | if (WARN_ON(!is_power_of_2(count))) | |
94 | return -EINVAL; | |
95 | ||
96 | /* slots_num must be power-of-two size, otherwise | |
97 | * get_cmd_index is broken. */ | |
98 | if (WARN_ON(!is_power_of_2(slots_num))) | |
99 | return -EINVAL; | |
100 | ||
101 | q->low_mark = q->n_window / 4; | |
102 | if (q->low_mark < 4) | |
103 | q->low_mark = 4; | |
104 | ||
105 | q->high_mark = q->n_window / 8; | |
106 | if (q->high_mark < 2) | |
107 | q->high_mark = 2; | |
108 | ||
109 | q->write_ptr = 0; | |
110 | q->read_ptr = 0; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | ||
116 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, | |
117 | struct iwl_dma_ptr *ptr, size_t size) | |
118 | { | |
119 | if (WARN_ON(ptr->addr)) | |
120 | return -EINVAL; | |
121 | ||
122 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
123 | &ptr->dma, GFP_KERNEL); | |
124 | if (!ptr->addr) | |
125 | return -ENOMEM; | |
126 | ptr->size = size; | |
127 | return 0; | |
128 | } | |
129 | ||
130 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
131 | struct iwl_dma_ptr *ptr) | |
132 | { | |
133 | if (unlikely(!ptr->addr)) | |
134 | return; | |
135 | ||
136 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
137 | memset(ptr, 0, sizeof(*ptr)); | |
138 | } | |
139 | ||
140 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
141 | { | |
142 | struct iwl_txq *txq = (void *)data; | |
143 | struct iwl_queue *q = &txq->q; | |
144 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
145 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
146 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
147 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
148 | u8 buf[16]; | |
149 | int i; | |
150 | ||
151 | spin_lock(&txq->lock); | |
152 | /* check if triggered erroneously */ | |
153 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
154 | spin_unlock(&txq->lock); | |
155 | return; | |
156 | } | |
157 | spin_unlock(&txq->lock); | |
158 | ||
159 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
160 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
161 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
162 | txq->q.read_ptr, txq->q.write_ptr); | |
163 | ||
164 | iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
165 | ||
166 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
167 | ||
168 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
169 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
170 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
171 | ||
172 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
173 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
174 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
175 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
176 | u32 tbl_dw = | |
177 | iwl_read_targ_mem(trans, | |
178 | trans_pcie->scd_base_addr + | |
179 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
180 | ||
181 | if (i & 0x1) | |
182 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
183 | else | |
184 | tbl_dw = tbl_dw & 0x0000FFFF; | |
185 | ||
186 | IWL_ERR(trans, | |
187 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
188 | i, active ? "" : "in", fifo, tbl_dw, | |
189 | iwl_read_prph(trans, | |
190 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
191 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
192 | } | |
193 | ||
194 | for (i = q->read_ptr; i != q->write_ptr; | |
195 | i = iwl_queue_inc_wrap(i, q->n_bd)) { | |
196 | struct iwl_tx_cmd *tx_cmd = | |
197 | (struct iwl_tx_cmd *)txq->entries[i].cmd->payload; | |
198 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, | |
199 | get_unaligned_le32(&tx_cmd->scratch)); | |
200 | } | |
201 | ||
202 | iwl_op_mode_nic_error(trans->op_mode); | |
203 | } | |
204 | ||
990aa6d7 EG |
205 | /* |
206 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 207 | */ |
f02831be EG |
208 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
209 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 210 | { |
105183b1 | 211 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 212 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
213 | int write_ptr = txq->q.write_ptr; |
214 | int txq_id = txq->q.id; | |
215 | u8 sec_ctl = 0; | |
216 | u8 sta_id = 0; | |
217 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
218 | __le16 bc_ent; | |
132f98c2 | 219 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 220 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 221 | |
105183b1 EG |
222 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
223 | ||
48d42c42 EG |
224 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
225 | ||
132f98c2 EG |
226 | sta_id = tx_cmd->sta_id; |
227 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
228 | |
229 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
230 | case TX_CMD_SEC_CCM: | |
231 | len += CCMP_MIC_LEN; | |
232 | break; | |
233 | case TX_CMD_SEC_TKIP: | |
234 | len += TKIP_ICV_LEN; | |
235 | break; | |
236 | case TX_CMD_SEC_WEP: | |
237 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
238 | break; | |
239 | } | |
240 | ||
241 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
242 | ||
243 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
244 | ||
245 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
246 | scd_bc_tbl[txq_id]. | |
247 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
248 | } | |
249 | ||
f02831be EG |
250 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
251 | struct iwl_txq *txq) | |
252 | { | |
253 | struct iwl_trans_pcie *trans_pcie = | |
254 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
255 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
256 | int txq_id = txq->q.id; | |
257 | int read_ptr = txq->q.read_ptr; | |
258 | u8 sta_id = 0; | |
259 | __le16 bc_ent; | |
260 | struct iwl_tx_cmd *tx_cmd = | |
261 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
262 | ||
263 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
264 | ||
265 | if (txq_id != trans_pcie->cmd_queue) | |
266 | sta_id = tx_cmd->sta_id; | |
267 | ||
268 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
269 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
270 | ||
271 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
272 | scd_bc_tbl[txq_id]. | |
273 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
274 | } | |
275 | ||
990aa6d7 EG |
276 | /* |
277 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 278 | */ |
990aa6d7 | 279 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 TW |
280 | { |
281 | u32 reg = 0; | |
fd4abac5 TW |
282 | int txq_id = txq->q.id; |
283 | ||
284 | if (txq->need_update == 0) | |
7bfedc59 | 285 | return; |
fd4abac5 | 286 | |
035f7ff2 | 287 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 288 | /* shadow register enabled */ |
1042db2a | 289 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
290 | txq->q.write_ptr | (txq_id << 8)); |
291 | } else { | |
47107e84 DF |
292 | struct iwl_trans_pcie *trans_pcie = |
293 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 294 | /* if we're trying to save power */ |
01d651d4 | 295 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
296 | /* wake up nic if it's powered down ... |
297 | * uCode will wake up, and interrupt us again, so next | |
298 | * time we'll skip this part. */ | |
1042db2a | 299 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 300 | |
f81c1f48 | 301 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 302 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
303 | "Tx queue %d requesting wakeup," |
304 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 305 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
306 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
307 | return; | |
308 | } | |
fd4abac5 | 309 | |
1042db2a | 310 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 311 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 312 | |
f81c1f48 WYG |
313 | /* |
314 | * else not in power-save mode, | |
315 | * uCode will never sleep when we're | |
316 | * trying to tx (during RFKILL, we're not trying to tx). | |
317 | */ | |
318 | } else | |
1042db2a | 319 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
320 | txq->q.write_ptr | (txq_id << 8)); |
321 | } | |
fd4abac5 | 322 | txq->need_update = 0; |
fd4abac5 | 323 | } |
fd4abac5 | 324 | |
f02831be | 325 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
326 | { |
327 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
328 | ||
329 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
330 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
331 | addr |= | |
332 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
333 | ||
334 | return addr; | |
335 | } | |
336 | ||
f02831be | 337 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
338 | { |
339 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
340 | ||
341 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
342 | } | |
343 | ||
f02831be EG |
344 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
345 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
346 | { |
347 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
348 | u16 hi_n_len = len << 4; | |
349 | ||
350 | put_unaligned_le32(addr, &tb->lo); | |
351 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
352 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
353 | ||
354 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
355 | ||
356 | tfd->num_tbs = idx + 1; | |
357 | } | |
358 | ||
f02831be | 359 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
360 | { |
361 | return tfd->num_tbs & 0x1f; | |
362 | } | |
363 | ||
f02831be EG |
364 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
365 | struct iwl_cmd_meta *meta, struct iwl_tfd *tfd, | |
366 | enum dma_data_direction dma_dir) | |
214d14d4 | 367 | { |
214d14d4 JB |
368 | int i; |
369 | int num_tbs; | |
370 | ||
214d14d4 | 371 | /* Sanity check on number of chunks */ |
f02831be | 372 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
373 | |
374 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 375 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
376 | /* @todo issue fatal error, it is quite serious situation */ |
377 | return; | |
378 | } | |
379 | ||
380 | /* Unmap tx_cmd */ | |
381 | if (num_tbs) | |
1042db2a | 382 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
383 | dma_unmap_addr(meta, mapping), |
384 | dma_unmap_len(meta, len), | |
795414db | 385 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
386 | |
387 | /* Unmap chunks, if any. */ | |
388 | for (i = 1; i < num_tbs; i++) | |
f02831be EG |
389 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
390 | iwl_pcie_tfd_tb_get_len(tfd, i), dma_dir); | |
ebed633c EG |
391 | |
392 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
393 | } |
394 | ||
990aa6d7 EG |
395 | /* |
396 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 397 | * @trans - transport private data |
4ce7cc2b | 398 | * @txq - tx queue |
ebed633c | 399 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
400 | * |
401 | * Does NOT advance any TFD circular buffer read/write indexes | |
402 | * Does NOT free the TFD itself (which is within circular buffer) | |
403 | */ | |
f02831be EG |
404 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
405 | enum dma_data_direction dma_dir) | |
4ce7cc2b JB |
406 | { |
407 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 408 | |
ebed633c EG |
409 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
410 | int rd_ptr = txq->q.read_ptr; | |
411 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
412 | ||
015c15e1 JB |
413 | lockdep_assert_held(&txq->lock); |
414 | ||
ebed633c | 415 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
f02831be EG |
416 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr], |
417 | dma_dir); | |
214d14d4 JB |
418 | |
419 | /* free SKB */ | |
bf8440e6 | 420 | if (txq->entries) { |
214d14d4 JB |
421 | struct sk_buff *skb; |
422 | ||
ebed633c | 423 | skb = txq->entries[idx].skb; |
214d14d4 | 424 | |
909e9b23 EG |
425 | /* Can be called from irqs-disabled context |
426 | * If skb is not NULL, it means that the whole queue is being | |
427 | * freed and that the queue is not empty - free the skb | |
428 | */ | |
214d14d4 | 429 | if (skb) { |
ed277c93 | 430 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 431 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
432 | } |
433 | } | |
434 | } | |
435 | ||
f02831be EG |
436 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
437 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
438 | { |
439 | struct iwl_queue *q; | |
440 | struct iwl_tfd *tfd, *tfd_tmp; | |
441 | u32 num_tbs; | |
442 | ||
443 | q = &txq->q; | |
4ce7cc2b | 444 | tfd_tmp = txq->tfds; |
214d14d4 JB |
445 | tfd = &tfd_tmp[q->write_ptr]; |
446 | ||
f02831be EG |
447 | if (reset) |
448 | memset(tfd, 0, sizeof(*tfd)); | |
449 | ||
450 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
451 | ||
452 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
453 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
454 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
455 | IWL_NUM_OF_TBS); | |
456 | return -EINVAL; | |
457 | } | |
458 | ||
459 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
460 | return -EINVAL; | |
461 | ||
462 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
463 | IWL_ERR(trans, "Unaligned address = %llx\n", | |
464 | (unsigned long long)addr); | |
465 | ||
466 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
472 | struct iwl_txq *txq, int slots_num, | |
473 | u32 txq_id) | |
474 | { | |
475 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
476 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
477 | int i; | |
478 | ||
479 | if (WARN_ON(txq->entries || txq->tfds)) | |
480 | return -EINVAL; | |
481 | ||
482 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
483 | (unsigned long)txq); | |
484 | txq->trans_pcie = trans_pcie; | |
485 | ||
486 | txq->q.n_window = slots_num; | |
487 | ||
488 | txq->entries = kcalloc(slots_num, | |
489 | sizeof(struct iwl_pcie_txq_entry), | |
490 | GFP_KERNEL); | |
491 | ||
492 | if (!txq->entries) | |
493 | goto error; | |
494 | ||
495 | if (txq_id == trans_pcie->cmd_queue) | |
496 | for (i = 0; i < slots_num; i++) { | |
497 | txq->entries[i].cmd = | |
498 | kmalloc(sizeof(struct iwl_device_cmd), | |
499 | GFP_KERNEL); | |
500 | if (!txq->entries[i].cmd) | |
501 | goto error; | |
502 | } | |
503 | ||
504 | /* Circular buffer of transmit frame descriptors (TFDs), | |
505 | * shared with device */ | |
506 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
507 | &txq->q.dma_addr, GFP_KERNEL); | |
508 | if (!txq->tfds) { | |
509 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); | |
510 | goto error; | |
511 | } | |
512 | txq->q.id = txq_id; | |
513 | ||
514 | return 0; | |
515 | error: | |
516 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
517 | for (i = 0; i < slots_num; i++) | |
518 | kfree(txq->entries[i].cmd); | |
519 | kfree(txq->entries); | |
520 | txq->entries = NULL; | |
521 | ||
522 | return -ENOMEM; | |
523 | ||
524 | } | |
525 | ||
526 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
527 | int slots_num, u32 txq_id) | |
528 | { | |
529 | int ret; | |
530 | ||
531 | txq->need_update = 0; | |
532 | ||
533 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
534 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
535 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
536 | ||
537 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
538 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
539 | txq_id); | |
540 | if (ret) | |
541 | return ret; | |
542 | ||
543 | spin_lock_init(&txq->lock); | |
544 | ||
545 | /* | |
546 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
547 | * given Tx queue, and enable the DMA channel used for that queue. | |
548 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
549 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
550 | txq->q.dma_addr >> 8); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | /* | |
556 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
557 | */ | |
558 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
559 | { | |
560 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
561 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
562 | struct iwl_queue *q = &txq->q; | |
563 | enum dma_data_direction dma_dir; | |
564 | ||
565 | if (!q->n_bd) | |
566 | return; | |
567 | ||
568 | /* In the command queue, all the TBs are mapped as BIDI | |
569 | * so unmap them as such. | |
570 | */ | |
571 | if (txq_id == trans_pcie->cmd_queue) | |
572 | dma_dir = DMA_BIDIRECTIONAL; | |
573 | else | |
574 | dma_dir = DMA_TO_DEVICE; | |
575 | ||
576 | spin_lock_bh(&txq->lock); | |
577 | while (q->write_ptr != q->read_ptr) { | |
578 | iwl_pcie_txq_free_tfd(trans, txq, dma_dir); | |
579 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); | |
580 | } | |
581 | spin_unlock_bh(&txq->lock); | |
582 | } | |
583 | ||
584 | /* | |
585 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
586 | * @txq: Transmit queue to deallocate. | |
587 | * | |
588 | * Empty queue by removing and destroying all BD's. | |
589 | * Free all buffers. | |
590 | * 0-fill, but do not free "txq" descriptor structure. | |
591 | */ | |
592 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
593 | { | |
594 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
595 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
596 | struct device *dev = trans->dev; | |
597 | int i; | |
598 | ||
599 | if (WARN_ON(!txq)) | |
600 | return; | |
601 | ||
602 | iwl_pcie_txq_unmap(trans, txq_id); | |
603 | ||
604 | /* De-alloc array of command/tx buffers */ | |
605 | if (txq_id == trans_pcie->cmd_queue) | |
606 | for (i = 0; i < txq->q.n_window; i++) { | |
607 | kfree(txq->entries[i].cmd); | |
608 | kfree(txq->entries[i].copy_cmd); | |
609 | kfree(txq->entries[i].free_buf); | |
610 | } | |
611 | ||
612 | /* De-alloc circular buffer of TFDs */ | |
613 | if (txq->q.n_bd) { | |
614 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
615 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
616 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
617 | } | |
618 | ||
619 | kfree(txq->entries); | |
620 | txq->entries = NULL; | |
621 | ||
622 | del_timer_sync(&txq->stuck_timer); | |
623 | ||
624 | /* 0-fill queue descriptor structure */ | |
625 | memset(txq, 0, sizeof(*txq)); | |
626 | } | |
627 | ||
628 | /* | |
629 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
630 | */ | |
631 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
632 | { | |
633 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
634 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
635 | ||
636 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
637 | } | |
638 | ||
639 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
640 | { | |
641 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
642 | u32 a; | |
643 | int chan; | |
644 | u32 reg_val; | |
645 | ||
646 | /* make sure all queue are not stopped/used */ | |
647 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
648 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
649 | ||
650 | trans_pcie->scd_base_addr = | |
651 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
652 | ||
653 | WARN_ON(scd_base_addr != 0 && | |
654 | scd_base_addr != trans_pcie->scd_base_addr); | |
655 | ||
656 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; | |
657 | /* reset conext data memory */ | |
658 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; | |
659 | a += 4) | |
660 | iwl_write_targ_mem(trans, a, 0); | |
661 | /* reset tx status memory */ | |
662 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; | |
663 | a += 4) | |
664 | iwl_write_targ_mem(trans, a, 0); | |
665 | for (; a < trans_pcie->scd_base_addr + | |
666 | SCD_TRANS_TBL_OFFSET_QUEUE( | |
667 | trans->cfg->base_params->num_of_queues); | |
668 | a += 4) | |
669 | iwl_write_targ_mem(trans, a, 0); | |
670 | ||
671 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
672 | trans_pcie->scd_bc_tbls.dma >> 10); | |
673 | ||
674 | /* The chain extension of the SCD doesn't work well. This feature is | |
675 | * enabled by default by the HW, so we need to disable it manually. | |
676 | */ | |
677 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
678 | ||
679 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
680 | trans_pcie->cmd_fifo); | |
681 | ||
682 | /* Activate all Tx DMA/FIFO channels */ | |
683 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
684 | ||
685 | /* Enable DMA channel */ | |
686 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
687 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
688 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
689 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
690 | ||
691 | /* Update FH chicken bits */ | |
692 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
693 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
694 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
695 | ||
696 | /* Enable L1-Active */ | |
697 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
698 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
699 | } | |
700 | ||
701 | /* | |
702 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
703 | */ | |
704 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
705 | { | |
706 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
707 | int ch, txq_id, ret; | |
708 | unsigned long flags; | |
709 | ||
710 | /* Turn off all Tx DMA fifos */ | |
711 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
712 | ||
713 | iwl_pcie_txq_set_sched(trans, 0); | |
714 | ||
715 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
716 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
717 | iwl_write_direct32(trans, | |
718 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
719 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
720 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
721 | if (ret < 0) | |
722 | IWL_ERR(trans, | |
723 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
724 | ch, | |
725 | iwl_read_direct32(trans, | |
726 | FH_TSSR_TX_STATUS_REG)); | |
727 | } | |
728 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
729 | ||
730 | if (!trans_pcie->txq) { | |
731 | IWL_WARN(trans, | |
732 | "Stopping tx queues that aren't allocated...\n"); | |
733 | return 0; | |
734 | } | |
735 | ||
736 | /* Unmap DMA from host system and free skb's */ | |
737 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
738 | txq_id++) | |
739 | iwl_pcie_txq_unmap(trans, txq_id); | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
744 | /* | |
745 | * iwl_trans_tx_free - Free TXQ Context | |
746 | * | |
747 | * Destroy all TX DMA queues and structures | |
748 | */ | |
749 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
750 | { | |
751 | int txq_id; | |
752 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
753 | ||
754 | /* Tx queues */ | |
755 | if (trans_pcie->txq) { | |
756 | for (txq_id = 0; | |
757 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
758 | iwl_pcie_txq_free(trans, txq_id); | |
759 | } | |
760 | ||
761 | kfree(trans_pcie->txq); | |
762 | trans_pcie->txq = NULL; | |
763 | ||
764 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
765 | ||
766 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
767 | } | |
768 | ||
769 | /* | |
770 | * iwl_pcie_tx_alloc - allocate TX context | |
771 | * Allocate all Tx DMA structures and initialize them | |
772 | */ | |
773 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
774 | { | |
775 | int ret; | |
776 | int txq_id, slots_num; | |
777 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
778 | ||
779 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
780 | sizeof(struct iwlagn_scd_bc_tbl); | |
781 | ||
782 | /*It is not allowed to alloc twice, so warn when this happens. | |
783 | * We cannot rely on the previous allocation, so free and fail */ | |
784 | if (WARN_ON(trans_pcie->txq)) { | |
785 | ret = -EINVAL; | |
786 | goto error; | |
787 | } | |
788 | ||
789 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
790 | scd_bc_tbls_size); | |
791 | if (ret) { | |
792 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
793 | goto error; | |
794 | } | |
795 | ||
796 | /* Alloc keep-warm buffer */ | |
797 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
798 | if (ret) { | |
799 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
800 | goto error; | |
801 | } | |
802 | ||
803 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
804 | sizeof(struct iwl_txq), GFP_KERNEL); | |
805 | if (!trans_pcie->txq) { | |
806 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
807 | ret = ENOMEM; | |
808 | goto error; | |
809 | } | |
810 | ||
811 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
812 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
813 | txq_id++) { | |
814 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
815 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
816 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
817 | slots_num, txq_id); | |
818 | if (ret) { | |
819 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
820 | goto error; | |
821 | } | |
822 | } | |
823 | ||
824 | return 0; | |
825 | ||
826 | error: | |
827 | iwl_pcie_tx_free(trans); | |
828 | ||
829 | return ret; | |
830 | } | |
831 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
832 | { | |
833 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
834 | int ret; | |
835 | int txq_id, slots_num; | |
836 | unsigned long flags; | |
837 | bool alloc = false; | |
838 | ||
839 | if (!trans_pcie->txq) { | |
840 | ret = iwl_pcie_tx_alloc(trans); | |
841 | if (ret) | |
842 | goto error; | |
843 | alloc = true; | |
844 | } | |
845 | ||
846 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
847 | ||
848 | /* Turn off all Tx DMA fifos */ | |
849 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
850 | ||
851 | /* Tell NIC where to find the "keep warm" buffer */ | |
852 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
853 | trans_pcie->kw.dma >> 4); | |
854 | ||
855 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
856 | ||
857 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
858 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
859 | txq_id++) { | |
860 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
861 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
862 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
863 | slots_num, txq_id); | |
864 | if (ret) { | |
865 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
866 | goto error; | |
867 | } | |
868 | } | |
869 | ||
870 | return 0; | |
871 | error: | |
872 | /*Upon error, free only if we allocated something */ | |
873 | if (alloc) | |
874 | iwl_pcie_tx_free(trans); | |
875 | return ret; | |
876 | } | |
877 | ||
878 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
879 | struct iwl_txq *txq) | |
880 | { | |
881 | if (!trans_pcie->wd_timeout) | |
882 | return; | |
883 | ||
884 | /* | |
885 | * if empty delete timer, otherwise move timer forward | |
886 | * since we're making progress on this queue | |
887 | */ | |
888 | if (txq->q.read_ptr == txq->q.write_ptr) | |
889 | del_timer(&txq->stuck_timer); | |
890 | else | |
891 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
892 | } | |
893 | ||
894 | /* Frees buffers until index _not_ inclusive */ | |
895 | static int iwl_pcie_txq_reclaim(struct iwl_trans *trans, int txq_id, int index, | |
896 | struct sk_buff_head *skbs) | |
897 | { | |
898 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
899 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
900 | struct iwl_queue *q = &txq->q; | |
901 | int last_to_free; | |
902 | int freed = 0; | |
903 | ||
904 | /* This function is not meant to release cmd queue*/ | |
905 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
906 | return 0; | |
214d14d4 | 907 | |
f02831be | 908 | lockdep_assert_held(&txq->lock); |
214d14d4 | 909 | |
f02831be EG |
910 | /*Since we free until index _not_ inclusive, the one before index is |
911 | * the last we will free. This one must be used */ | |
912 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
913 | ||
914 | if ((index >= q->n_bd) || | |
915 | (iwl_queue_used(q, last_to_free) == 0)) { | |
916 | IWL_ERR(trans, | |
917 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
918 | __func__, txq_id, last_to_free, q->n_bd, | |
919 | q->write_ptr, q->read_ptr); | |
920 | return 0; | |
214d14d4 JB |
921 | } |
922 | ||
f02831be EG |
923 | if (WARN_ON(!skb_queue_empty(skbs))) |
924 | return 0; | |
214d14d4 | 925 | |
f02831be EG |
926 | for (; |
927 | q->read_ptr != index; | |
928 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
214d14d4 | 929 | |
f02831be EG |
930 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
931 | continue; | |
214d14d4 | 932 | |
f02831be | 933 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 934 | |
f02831be | 935 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 936 | |
f02831be | 937 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 938 | |
f02831be EG |
939 | iwl_pcie_txq_free_tfd(trans, txq, DMA_TO_DEVICE); |
940 | freed++; | |
941 | } | |
fd4abac5 | 942 | |
f02831be EG |
943 | iwl_pcie_txq_progress(trans_pcie, txq); |
944 | ||
945 | return freed; | |
fd4abac5 | 946 | } |
fd4abac5 | 947 | |
f02831be EG |
948 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
949 | struct sk_buff_head *skbs) | |
1053d35f | 950 | { |
f02831be EG |
951 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
952 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
953 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ | |
954 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
1053d35f | 955 | |
f02831be | 956 | spin_lock(&txq->lock); |
1053d35f | 957 | |
f02831be EG |
958 | if (txq->q.read_ptr != tfd_num) { |
959 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
960 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
961 | iwl_pcie_txq_reclaim(trans, txq_id, tfd_num, skbs); | |
962 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) | |
963 | iwl_wake_queue(trans, txq); | |
964 | } | |
1053d35f | 965 | |
f02831be | 966 | spin_unlock(&txq->lock); |
1053d35f RR |
967 | } |
968 | ||
f02831be EG |
969 | /* |
970 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
971 | * | |
972 | * When FW advances 'R' index, all entries between old and new 'R' index | |
973 | * need to be reclaimed. As result, some free space forms. If there is | |
974 | * enough free space (> low mark), wake the stack that feeds us. | |
975 | */ | |
976 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 977 | { |
f02831be EG |
978 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
979 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
980 | struct iwl_queue *q = &txq->q; | |
981 | int nfreed = 0; | |
48d42c42 | 982 | |
f02831be | 983 | lockdep_assert_held(&txq->lock); |
48d42c42 | 984 | |
f02831be EG |
985 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
986 | IWL_ERR(trans, | |
987 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
988 | __func__, txq_id, idx, q->n_bd, | |
989 | q->write_ptr, q->read_ptr); | |
990 | return; | |
991 | } | |
48d42c42 | 992 | |
f02831be EG |
993 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
994 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 995 | |
f02831be EG |
996 | if (nfreed++ > 0) { |
997 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
998 | idx, q->write_ptr, q->read_ptr); | |
999 | iwl_op_mode_nic_error(trans->op_mode); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | iwl_pcie_txq_progress(trans_pcie, txq); | |
48d42c42 EG |
1004 | } |
1005 | ||
f02831be | 1006 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1007 | u16 txq_id) |
48d42c42 | 1008 | { |
20d3b647 | 1009 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1010 | u32 tbl_dw_addr; |
1011 | u32 tbl_dw; | |
1012 | u16 scd_q2ratid; | |
1013 | ||
1014 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1015 | ||
105183b1 | 1016 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1017 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1018 | ||
1042db2a | 1019 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
1020 | |
1021 | if (txq_id & 0x1) | |
1022 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1023 | else | |
1024 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1025 | ||
1042db2a | 1026 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1027 | |
1028 | return 0; | |
1029 | } | |
1030 | ||
f02831be EG |
1031 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1032 | u16 txq_id) | |
48d42c42 EG |
1033 | { |
1034 | /* Simply stop the queue, but don't change any configuration; | |
1035 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1036 | iwl_write_prph(trans, |
48d42c42 EG |
1037 | SCD_QUEUE_STATUS_BITS(txq_id), |
1038 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1039 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1040 | } | |
1041 | ||
f02831be EG |
1042 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1043 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1044 | { |
9eae88fa | 1045 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1046 | |
9eae88fa JB |
1047 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1048 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1049 | |
48d42c42 | 1050 | /* Stop this Tx queue before configuring it */ |
f02831be | 1051 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1052 | |
4beaf6c2 EG |
1053 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1054 | if (txq_id != trans_pcie->cmd_queue) | |
1055 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1056 | ||
1057 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
1058 | if (sta_id != IWL_INVALID_STATION) { | |
1059 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); | |
48d42c42 | 1060 | |
4beaf6c2 | 1061 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1062 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1063 | |
4beaf6c2 EG |
1064 | /* enable aggregations for the queue */ |
1065 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
1ce8658c EG |
1066 | } else { |
1067 | /* | |
1068 | * disable aggregations for the queue, this will also make the | |
1069 | * ra_tid mapping configuration irrelevant since it is now a | |
1070 | * non-AGG queue. | |
1071 | */ | |
1072 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
4beaf6c2 | 1073 | } |
48d42c42 EG |
1074 | |
1075 | /* Place first TFD at index corresponding to start sequence number. | |
1076 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1077 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1078 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1079 | |
1080 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1081 | (ssn & 0xff) | (txq_id << 8)); | |
1082 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1083 | |
1084 | /* Set up Tx window size and frame limit for this queue */ | |
4beaf6c2 EG |
1085 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
1086 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | |
1042db2a | 1087 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1088 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1089 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1090 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1091 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1092 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1093 | |
48d42c42 | 1094 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1095 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1096 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1097 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1098 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1099 | SCD_QUEUE_STTS_REG_MSK); | |
1100 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", | |
1101 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1102 | } |
1103 | ||
f02831be | 1104 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1105 | { |
8ad71bef | 1106 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1107 | u32 stts_addr = trans_pcie->scd_base_addr + |
1108 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1109 | static const u32 zero_val[4] = {}; | |
288712a6 | 1110 | |
9eae88fa JB |
1111 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
1112 | WARN_ONCE(1, "queue %d not used", txq_id); | |
1113 | return; | |
48d42c42 EG |
1114 | } |
1115 | ||
f02831be | 1116 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1117 | |
986ea6c9 EG |
1118 | _iwl_write_targ_mem_dwords(trans, stts_addr, |
1119 | zero_val, ARRAY_SIZE(zero_val)); | |
1120 | ||
990aa6d7 | 1121 | iwl_pcie_txq_unmap(trans, txq_id); |
6c3fd3f0 | 1122 | |
1ce8658c | 1123 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1124 | } |
1125 | ||
fd4abac5 TW |
1126 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1127 | ||
990aa6d7 | 1128 | /* |
f02831be | 1129 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 TW |
1130 | * @priv: device private data point |
1131 | * @cmd: a point to the ucode command structure | |
1132 | * | |
1133 | * The function returns < 0 values to indicate the operation is | |
1134 | * failed. On success, it turns the index (> 0) of command in the | |
1135 | * command queue. | |
1136 | */ | |
f02831be EG |
1137 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1138 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1139 | { |
8ad71bef | 1140 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1141 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1142 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1143 | struct iwl_device_cmd *out_cmd; |
1144 | struct iwl_cmd_meta *out_meta; | |
f4feb8ac | 1145 | void *dup_buf = NULL; |
fd4abac5 | 1146 | dma_addr_t phys_addr; |
f4feb8ac | 1147 | int idx; |
4ce7cc2b | 1148 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
1149 | bool had_nocopy = false; |
1150 | int i; | |
96791422 | 1151 | u32 cmd_pos; |
fd4abac5 | 1152 | |
4ce7cc2b JB |
1153 | copy_size = sizeof(out_cmd->hdr); |
1154 | cmd_size = sizeof(out_cmd->hdr); | |
1155 | ||
1156 | /* need one for the header if the first is NOCOPY */ | |
1157 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
1158 | ||
1159 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
1160 | if (!cmd->len[i]) | |
1161 | continue; | |
1162 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
1163 | had_nocopy = true; | |
f4feb8ac JB |
1164 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1165 | idx = -EINVAL; | |
1166 | goto free_dup_buf; | |
1167 | } | |
1168 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1169 | /* | |
1170 | * This is also a chunk that isn't copied | |
1171 | * to the static buffer so set had_nocopy. | |
1172 | */ | |
1173 | had_nocopy = true; | |
1174 | ||
1175 | /* only allowed once */ | |
1176 | if (WARN_ON(dup_buf)) { | |
1177 | idx = -EINVAL; | |
1178 | goto free_dup_buf; | |
1179 | } | |
1180 | ||
1181 | dup_buf = kmemdup(cmd->data[i], cmd->len[i], | |
1182 | GFP_ATOMIC); | |
1183 | if (!dup_buf) | |
1184 | return -ENOMEM; | |
4ce7cc2b JB |
1185 | } else { |
1186 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1187 | if (WARN_ON(had_nocopy)) { |
1188 | idx = -EINVAL; | |
1189 | goto free_dup_buf; | |
1190 | } | |
4ce7cc2b JB |
1191 | copy_size += cmd->len[i]; |
1192 | } | |
1193 | cmd_size += cmd->len[i]; | |
1194 | } | |
fd4abac5 | 1195 | |
3e41ace5 JB |
1196 | /* |
1197 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1198 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1199 | * allocated into separate TFDs, then we will need to | |
1200 | * increase the size of the buffers. | |
3e41ace5 | 1201 | */ |
2a79e45e JB |
1202 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1203 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1204 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1205 | idx = -EINVAL; |
1206 | goto free_dup_buf; | |
1207 | } | |
fd4abac5 | 1208 | |
015c15e1 | 1209 | spin_lock_bh(&txq->lock); |
3598e177 | 1210 | |
c2acea8e | 1211 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1212 | spin_unlock_bh(&txq->lock); |
3598e177 | 1213 | |
6d8f6eeb | 1214 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1215 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1216 | idx = -ENOSPC; |
1217 | goto free_dup_buf; | |
fd4abac5 TW |
1218 | } |
1219 | ||
4ce7cc2b | 1220 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1221 | out_cmd = txq->entries[idx].cmd; |
1222 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1223 | |
8ce73f3a | 1224 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1225 | if (cmd->flags & CMD_WANT_SKB) |
1226 | out_meta->source = cmd; | |
fd4abac5 | 1227 | |
4ce7cc2b | 1228 | /* set up the header */ |
fd4abac5 | 1229 | |
4ce7cc2b | 1230 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1231 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1232 | out_cmd->hdr.sequence = |
c6f600fc | 1233 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1234 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1235 | |
1236 | /* and copy the data that needs to be copied */ | |
96791422 | 1237 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
4ce7cc2b JB |
1238 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
1239 | if (!cmd->len[i]) | |
1240 | continue; | |
f4feb8ac JB |
1241 | if (cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1242 | IWL_HCMD_DFL_DUP)) | |
4ce7cc2b | 1243 | break; |
96791422 EG |
1244 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], cmd->len[i]); |
1245 | cmd_pos += cmd->len[i]; | |
1246 | } | |
1247 | ||
1248 | WARN_ON_ONCE(txq->entries[idx].copy_cmd); | |
1249 | ||
1250 | /* | |
1251 | * since out_cmd will be the source address of the FH, it will write | |
1252 | * the retry count there. So when the user needs to receivce the HCMD | |
1253 | * that corresponds to the response in the response handler, it needs | |
1254 | * to set CMD_WANT_HCMD. | |
1255 | */ | |
1256 | if (cmd->flags & CMD_WANT_HCMD) { | |
1257 | txq->entries[idx].copy_cmd = | |
1258 | kmemdup(out_cmd, cmd_pos, GFP_ATOMIC); | |
1259 | if (unlikely(!txq->entries[idx].copy_cmd)) { | |
1260 | idx = -ENOMEM; | |
1261 | goto out; | |
1262 | } | |
ded2ae7c | 1263 | } |
4ce7cc2b | 1264 | |
d9fb6465 | 1265 | IWL_DEBUG_HC(trans, |
20d3b647 | 1266 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1267 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1268 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1269 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1270 | |
1042db2a | 1271 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
20d3b647 | 1272 | DMA_BIDIRECTIONAL); |
1042db2a | 1273 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
1274 | idx = -ENOMEM; |
1275 | goto out; | |
1276 | } | |
1277 | ||
2e724443 | 1278 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
1279 | dma_unmap_len_set(out_meta, len, copy_size); |
1280 | ||
f02831be | 1281 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, copy_size, 1); |
4ce7cc2b JB |
1282 | |
1283 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
f4feb8ac JB |
1284 | const void *data = cmd->data[i]; |
1285 | ||
4ce7cc2b JB |
1286 | if (!cmd->len[i]) |
1287 | continue; | |
f4feb8ac JB |
1288 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1289 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1290 | continue; |
f4feb8ac JB |
1291 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1292 | data = dup_buf; | |
1293 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
3be3fdb5 | 1294 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 1295 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be EG |
1296 | iwl_pcie_tfd_unmap(trans, out_meta, |
1297 | &txq->tfds[q->write_ptr], | |
1298 | DMA_BIDIRECTIONAL); | |
4ce7cc2b JB |
1299 | idx = -ENOMEM; |
1300 | goto out; | |
1301 | } | |
1302 | ||
f02831be | 1303 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmd->len[i], 0); |
4ce7cc2b | 1304 | } |
df833b1d | 1305 | |
afaf6b57 | 1306 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1307 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1308 | kfree(txq->entries[idx].free_buf); | |
1309 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e JB |
1310 | |
1311 | txq->need_update = 1; | |
1312 | ||
45eab7cc JB |
1313 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, |
1314 | &out_cmd->hdr, copy_size); | |
df833b1d | 1315 | |
7c5ba4a8 JB |
1316 | /* start timer if queue currently empty */ |
1317 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1318 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1319 | ||
fd4abac5 TW |
1320 | /* Increment and update queue's write index */ |
1321 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1322 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1323 | |
2c46f72e | 1324 | out: |
015c15e1 | 1325 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1326 | free_dup_buf: |
1327 | if (idx < 0) | |
1328 | kfree(dup_buf); | |
7bfedc59 | 1329 | return idx; |
fd4abac5 TW |
1330 | } |
1331 | ||
990aa6d7 EG |
1332 | /* |
1333 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1334 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1335 | * @handler_status: return value of the handler of the command |
1336 | * (put in setup_rx_handlers) | |
17b88929 TW |
1337 | * |
1338 | * If an Rx buffer has an async callback associated with it the callback | |
1339 | * will be executed. The attached skb (if present) will only be freed | |
1340 | * if the callback returns 1 | |
1341 | */ | |
990aa6d7 EG |
1342 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1343 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1344 | { |
2f301227 | 1345 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1346 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1347 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1348 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1349 | int cmd_index; |
c2acea8e JB |
1350 | struct iwl_device_cmd *cmd; |
1351 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1352 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1353 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1354 | |
1355 | /* If a Tx command is being handled and it isn't in the actual | |
1356 | * command queue then there a command routing bug has been introduced | |
1357 | * in the queue management code. */ | |
c6f600fc | 1358 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1359 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1360 | txq_id, trans_pcie->cmd_queue, sequence, |
1361 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1362 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1363 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1364 | return; |
01ef9323 | 1365 | } |
17b88929 | 1366 | |
015c15e1 JB |
1367 | spin_lock(&txq->lock); |
1368 | ||
4ce7cc2b | 1369 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1370 | cmd = txq->entries[cmd_index].cmd; |
1371 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1372 | |
f02831be | 1373 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
c33de625 | 1374 | |
17b88929 | 1375 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1376 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1377 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1378 | |
65b94a4a JB |
1379 | meta->source->resp_pkt = pkt; |
1380 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1381 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1382 | meta->source->handler_status = handler_status; |
247c61d6 | 1383 | } |
2624e96c | 1384 | |
f02831be | 1385 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1386 | |
c2acea8e | 1387 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 1388 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
1389 | IWL_WARN(trans, |
1390 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1391 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1392 | } |
74fda971 | 1393 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 1394 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1395 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1396 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1397 | } |
3598e177 | 1398 | |
dd487449 | 1399 | meta->flags = 0; |
3598e177 | 1400 | |
015c15e1 | 1401 | spin_unlock(&txq->lock); |
17b88929 | 1402 | } |
253a634c | 1403 | |
253a634c EG |
1404 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
1405 | ||
f02831be EG |
1406 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1407 | struct iwl_host_cmd *cmd) | |
253a634c | 1408 | { |
d9fb6465 | 1409 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1410 | int ret; |
1411 | ||
1412 | /* An asynchronous command can not expect an SKB to be set. */ | |
1413 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1414 | return -EINVAL; | |
1415 | ||
253a634c | 1416 | |
f02831be | 1417 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1418 | if (ret < 0) { |
721c32f7 | 1419 | IWL_ERR(trans, |
b36b110c | 1420 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1421 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1422 | return ret; |
1423 | } | |
1424 | return 0; | |
1425 | } | |
1426 | ||
f02831be EG |
1427 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1428 | struct iwl_host_cmd *cmd) | |
253a634c | 1429 | { |
8ad71bef | 1430 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1431 | int cmd_idx; |
1432 | int ret; | |
1433 | ||
6d8f6eeb | 1434 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1435 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1436 | |
2cc39c94 | 1437 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 1438 | &trans_pcie->status))) { |
2cc39c94 | 1439 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
990aa6d7 | 1440 | get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
1441 | return -EIO; |
1442 | } | |
1443 | ||
6d8f6eeb | 1444 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1445 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1446 | |
f02831be | 1447 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1448 | if (cmd_idx < 0) { |
1449 | ret = cmd_idx; | |
74fda971 | 1450 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 1451 | IWL_ERR(trans, |
b36b110c | 1452 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1453 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1454 | return ret; |
1455 | } | |
1456 | ||
f946b529 | 1457 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
20d3b647 JB |
1458 | !test_bit(STATUS_HCMD_ACTIVE, |
1459 | &trans_pcie->status), | |
1460 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1461 | if (!ret) { |
74fda971 | 1462 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
990aa6d7 | 1463 | struct iwl_txq *txq = |
c6f600fc | 1464 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
1465 | struct iwl_queue *q = &txq->q; |
1466 | ||
721c32f7 | 1467 | IWL_ERR(trans, |
253a634c | 1468 | "Error sending %s: time out after %dms.\n", |
990aa6d7 | 1469 | get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
1470 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
1471 | ||
721c32f7 | 1472 | IWL_ERR(trans, |
d10630af WYG |
1473 | "Current CMD queue read_ptr %d write_ptr %d\n", |
1474 | q->read_ptr, q->write_ptr); | |
1475 | ||
74fda971 | 1476 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
1477 | IWL_DEBUG_INFO(trans, |
1478 | "Clearing HCMD_ACTIVE for command %s\n", | |
990aa6d7 | 1479 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1480 | ret = -ETIMEDOUT; |
1481 | goto cancel; | |
1482 | } | |
1483 | } | |
1484 | ||
d18aa87f JB |
1485 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) { |
1486 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", | |
990aa6d7 | 1487 | get_cmd_string(trans_pcie, cmd->id)); |
d18aa87f JB |
1488 | ret = -EIO; |
1489 | goto cancel; | |
1490 | } | |
1491 | ||
f946b529 EG |
1492 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) { |
1493 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); | |
1494 | ret = -ERFKILL; | |
1495 | goto cancel; | |
1496 | } | |
1497 | ||
65b94a4a | 1498 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1499 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1500 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1501 | ret = -EIO; |
1502 | goto cancel; | |
1503 | } | |
1504 | ||
1505 | return 0; | |
1506 | ||
1507 | cancel: | |
1508 | if (cmd->flags & CMD_WANT_SKB) { | |
1509 | /* | |
1510 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1511 | * TX cmd queue. Otherwise in case the cmd comes | |
1512 | * in later, it will possibly set an invalid | |
1513 | * address (cmd->meta.source). | |
1514 | */ | |
bf8440e6 JB |
1515 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1516 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1517 | } |
9cac4943 | 1518 | |
65b94a4a JB |
1519 | if (cmd->resp_pkt) { |
1520 | iwl_free_resp(cmd); | |
1521 | cmd->resp_pkt = NULL; | |
253a634c EG |
1522 | } |
1523 | ||
1524 | return ret; | |
1525 | } | |
1526 | ||
f02831be | 1527 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1528 | { |
f946b529 EG |
1529 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1530 | ||
d18aa87f JB |
1531 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) |
1532 | return -EIO; | |
1533 | ||
f946b529 EG |
1534 | if (test_bit(STATUS_RFKILL, &trans_pcie->status)) |
1535 | return -ERFKILL; | |
1536 | ||
253a634c | 1537 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1538 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1539 | |
f946b529 | 1540 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1541 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1542 | } |
1543 | ||
f02831be EG |
1544 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1545 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1546 | { |
8ad71bef | 1547 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1548 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1549 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1550 | struct iwl_cmd_meta *out_meta; | |
1551 | struct iwl_txq *txq; | |
1552 | struct iwl_queue *q; | |
1553 | dma_addr_t phys_addr = 0; | |
1554 | dma_addr_t txcmd_phys; | |
1555 | dma_addr_t scratch_phys; | |
1556 | u16 len, firstlen, secondlen; | |
1557 | u8 wait_write_ptr = 0; | |
1558 | __le16 fc = hdr->frame_control; | |
1559 | u8 hdr_len = ieee80211_hdrlen(fc); | |
1560 | u16 __maybe_unused wifi_seq; | |
1561 | ||
1562 | txq = &trans_pcie->txq[txq_id]; | |
1563 | q = &txq->q; | |
a0eaad71 | 1564 | |
f02831be EG |
1565 | if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) { |
1566 | WARN_ON_ONCE(1); | |
1567 | return -EINVAL; | |
1568 | } | |
39644e9a | 1569 | |
f02831be | 1570 | spin_lock(&txq->lock); |
015c15e1 | 1571 | |
f02831be EG |
1572 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1573 | * sequence number. This is a HW requirements to help the SCD to parse | |
1574 | * the BA. | |
1575 | * Check here that the packets are in the right place on the ring. | |
1576 | */ | |
1577 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1578 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1579 | WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) && | |
1580 | ((wifi_seq & 0xff) != q->write_ptr), | |
1581 | "Q: %d WiFi Seq %d tfdNum %d", | |
1582 | txq_id, wifi_seq, q->write_ptr); | |
1583 | #endif | |
1584 | ||
1585 | /* Set up driver data for this TFD */ | |
1586 | txq->entries[q->write_ptr].skb = skb; | |
1587 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1588 | ||
1589 | dev_cmd->hdr.cmd = REPLY_TX; | |
1590 | dev_cmd->hdr.sequence = | |
1591 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1592 | INDEX_TO_SEQ(q->write_ptr))); | |
1593 | ||
1594 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1595 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1596 | |
f02831be EG |
1597 | /* |
1598 | * Use the first empty entry in this queue's command buffer array | |
1599 | * to contain the Tx command and MAC header concatenated together | |
1600 | * (payload data will be in another buffer). | |
1601 | * Size of this varies, due to varying MAC header length. | |
1602 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1603 | * of the MAC header (device reads on dword boundaries). | |
1604 | * We'll tell device about this padding later. | |
1605 | */ | |
1606 | len = sizeof(struct iwl_tx_cmd) + | |
1607 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1608 | firstlen = (len + 3) & ~3; | |
1609 | ||
1610 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1611 | if (firstlen != len) | |
1612 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1613 | ||
1614 | /* Physical address of this Tx command's header (not MAC header!), | |
1615 | * within command buffer array. */ | |
1616 | txcmd_phys = dma_map_single(trans->dev, | |
1617 | &dev_cmd->hdr, firstlen, | |
1618 | DMA_BIDIRECTIONAL); | |
1619 | if (unlikely(dma_mapping_error(trans->dev, txcmd_phys))) | |
1620 | goto out_err; | |
1621 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
1622 | dma_unmap_len_set(out_meta, len, firstlen); | |
1623 | ||
1624 | if (!ieee80211_has_morefrags(fc)) { | |
1625 | txq->need_update = 1; | |
1626 | } else { | |
1627 | wait_write_ptr = 1; | |
1628 | txq->need_update = 0; | |
a0eaad71 EG |
1629 | } |
1630 | ||
f02831be EG |
1631 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
1632 | * if any (802.11 null frames have no payload). */ | |
1633 | secondlen = skb->len - hdr_len; | |
1634 | if (secondlen > 0) { | |
1635 | phys_addr = dma_map_single(trans->dev, skb->data + hdr_len, | |
1636 | secondlen, DMA_TO_DEVICE); | |
1637 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { | |
1638 | dma_unmap_single(trans->dev, | |
1639 | dma_unmap_addr(out_meta, mapping), | |
1640 | dma_unmap_len(out_meta, len), | |
1641 | DMA_BIDIRECTIONAL); | |
1642 | goto out_err; | |
1643 | } | |
1644 | } | |
a0eaad71 | 1645 | |
f02831be EG |
1646 | /* Attach buffers to TFD */ |
1647 | iwl_pcie_txq_build_tfd(trans, txq, txcmd_phys, firstlen, 1); | |
1648 | if (secondlen > 0) | |
1649 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, secondlen, 0); | |
a0eaad71 | 1650 | |
f02831be EG |
1651 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
1652 | offsetof(struct iwl_tx_cmd, scratch); | |
a0eaad71 | 1653 | |
f02831be EG |
1654 | /* take back ownership of DMA buffer to enable update */ |
1655 | dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen, | |
1656 | DMA_BIDIRECTIONAL); | |
1657 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1658 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
a0eaad71 | 1659 | |
f02831be EG |
1660 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
1661 | le16_to_cpu(dev_cmd->hdr.sequence)); | |
1662 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); | |
a0eaad71 | 1663 | |
f02831be EG |
1664 | /* Set up entry for this TFD in Tx byte-count array */ |
1665 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1666 | |
f02831be EG |
1667 | dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen, |
1668 | DMA_BIDIRECTIONAL); | |
7c5ba4a8 | 1669 | |
f02831be EG |
1670 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1671 | &txq->tfds[txq->q.write_ptr], | |
1672 | sizeof(struct iwl_tfd), | |
1673 | &dev_cmd->hdr, firstlen, | |
1674 | skb->data + hdr_len, secondlen); | |
1675 | trace_iwlwifi_dev_tx_data(trans->dev, skb, | |
1676 | skb->data + hdr_len, secondlen); | |
7c5ba4a8 | 1677 | |
f02831be EG |
1678 | /* start timer if queue currently empty */ |
1679 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1680 | trans_pcie->wd_timeout) | |
1681 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1682 | ||
1683 | /* Tell device the write index *just past* this latest filled TFD */ | |
1684 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1685 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1686 | ||
1687 | /* | |
1688 | * At this point the frame is "transmitted" successfully | |
1689 | * and we will get a TX status notification eventually, | |
1690 | * regardless of the value of ret. "ret" only indicates | |
1691 | * whether or not we should update the write pointer. | |
1692 | */ | |
1693 | if (iwl_queue_space(q) < q->high_mark) { | |
1694 | if (wait_write_ptr) { | |
1695 | txq->need_update = 1; | |
1696 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1697 | } else { | |
1698 | iwl_stop_queue(trans, txq); | |
1699 | } | |
1700 | } | |
1701 | spin_unlock(&txq->lock); | |
1702 | return 0; | |
1703 | out_err: | |
1704 | spin_unlock(&txq->lock); | |
1705 | return -1; | |
a0eaad71 | 1706 | } |