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mwifiex: resolve races between async FW init (failure) and device removal
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / marvell / mwifiex / sdio.h
CommitLineData
5e6e3a92
BZ		 1/*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
65da33f5 4 * Copyright (C) 2011-2014, Marvell International Ltd.
5e6e3a92
BZ		 5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#ifndef _MWIFIEX_SDIO_H
21#define _MWIFIEX_SDIO_H
22
23
4a79aa17 24#include <linux/completion.h>
5e6e3a92
BZ		 25#include <linux/mmc/sdio.h>
26#include <linux/mmc/sdio_ids.h>
27#include <linux/mmc/sdio_func.h>
28#include <linux/mmc/card.h>
d31ab357 29#include <linux/mmc/host.h>
5e6e3a92
BZ		 30
31#include "main.h"
32
98e6b9df 33#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1 34#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8 35#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
b60186f8 36#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
030bb75a 37#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
52bd3d20 38#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
6d85ef00 39#define SD8997_DEFAULT_FW_NAME "mrvl/sd8997_uapsta.bin"
4a7f5db1 40
5e6e3a92
BZ		 41#define BLOCK_MODE 1
42#define BYTE_MODE 0
43
44#define REG_PORT 0
5e6e3a92
BZ		 45
46#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
47
48#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
49
809c6ea8
XH		 50#define MWIFIEX_MAX_FUNC2_REG_NUM 13
51#define MWIFIEX_SDIO_SCRATCH_SIZE 10
52
248eb4c6 53#define SDIO_MPA_ADDR_BASE 0x1000
5e6e3a92
BZ		 54#define CTRL_PORT 0
55#define CTRL_PORT_MASK 0x0001
5e6e3a92 56
b60186f8
YAP		 57#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
58#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
59#define HOST_TERM_CMD53 (0x1U << 2)
60#define REG_PORT 0
61#define MEM_PORT 0x10000
554a0113 62
b60186f8 63#define CMD53_NEW_MODE (0x1U << 0)
b60186f8 64#define CMD_PORT_RD_LEN_EN (0x1U << 2)
b60186f8
YAP		 65#define CMD_PORT_AUTO_EN (0x1U << 0)
66#define CMD_PORT_SLCT 0x8000
67#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
68#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
69
e1aa93a4
AK		 70#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
71#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
ea44f4d0
AP		 72/* we leave one block of 256 bytes for DMA alignment*/
73#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
5e6e3a92
BZ		 74
75/* Misc. Config Register : Auto Re-enable interrupts */
76#define AUTO_RE_ENABLE_INT BIT(4)
77
5e6e3a92
BZ		 78/* Host Control Registers : Configuration */
79#define CONFIGURATION_REG 0x00
5e6e3a92
BZ		 80/* Host Control Registers : Host power up */
81#define HOST_POWER_UP (0x1U << 1)
5e6e3a92 82
5e6e3a92
BZ		 83/* Host Control Registers : Upload host interrupt mask */
84#define UP_LD_HOST_INT_MASK (0x1U)
85/* Host Control Registers : Download host interrupt mask */
86#define DN_LD_HOST_INT_MASK (0x2U)
b60186f8 87
5e6e3a92
BZ		 88/* Host Control Registers : Upload host interrupt status */
89#define UP_LD_HOST_INT_STATUS (0x1U)
90/* Host Control Registers : Download host interrupt status */
91#define DN_LD_HOST_INT_STATUS (0x2U)
92
5e6e3a92 93/* Host Control Registers : Host interrupt status */
554a0113 94#define CARD_INT_STATUS_REG 0x28
5e6e3a92 95
5e6e3a92
BZ		 96/* Card Control Registers : Card I/O ready */
97#define CARD_IO_READY (0x1U << 3)
5e6e3a92
BZ		 98/* Card Control Registers : Download card ready */
99#define DN_LD_CARD_RDY (0x1U << 0)
100
5e6e3a92
BZ		 101/* Max retry number of CMD53 write */
102#define MAX_WRITE_IOMEM_RETRY 2
103
104/* SDIO Tx aggregation in progress ? */
105#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
106
107/* SDIO Tx aggregation buffer room for next packet ? */
108#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
109 <= a->mpa_tx.buf_size)
110
111/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
112#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
113 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
114 payload, pkt_len); \
115 a->mpa_tx.buf_len += pkt_len; \
116 if (!a->mpa_tx.pkt_cnt) \
117 a->mpa_tx.start_port = port; \
118 if (a->mpa_tx.start_port <= port) \
119 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
120 else \
05889f82
AK		 121 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
122 (a->max_ports - \
5e6e3a92
BZ		 123 a->mp_end_port))); \
124 a->mpa_tx.pkt_cnt++; \
da951c24 125} while (0)
5e6e3a92
BZ		 126
127/* SDIO Tx aggregation limit ? */
128#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
129 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
130
5e6e3a92
BZ		 131/* Reset SDIO Tx aggregation buffer parameters */
132#define MP_TX_AGGR_BUF_RESET(a) do { \
133 a->mpa_tx.pkt_cnt = 0; \
134 a->mpa_tx.buf_len = 0; \
135 a->mpa_tx.ports = 0; \
136 a->mpa_tx.start_port = 0; \
da951c24 137} while (0)
5e6e3a92
BZ		 138
139/* SDIO Rx aggregation limit ? */
140#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
141 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
142
5e6e3a92
BZ		 143/* SDIO Rx aggregation in progress ? */
144#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
145
146/* SDIO Rx aggregation buffer room for next packet ? */
147#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
148 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
149
5e6e3a92
BZ		 150/* Reset SDIO Rx aggregation buffer parameters */
151#define MP_RX_AGGR_BUF_RESET(a) do { \
152 a->mpa_rx.pkt_cnt = 0; \
153 a->mpa_rx.buf_len = 0; \
154 a->mpa_rx.ports = 0; \
155 a->mpa_rx.start_port = 0; \
da951c24 156} while (0)
5e6e3a92 157
5e6e3a92
BZ		 158/* data structure for SDIO MPA TX */
159struct mwifiex_sdio_mpa_tx {
160 /* multiport tx aggregation buffer pointer */
161 u8 *buf;
162 u32 buf_len;
163 u32 pkt_cnt;
5ac253d5 164 u32 ports;
5e6e3a92
BZ		 165 u16 start_port;
166 u8 enabled;
167 u32 buf_size;
168 u32 pkt_aggr_limit;
169};
170
171struct mwifiex_sdio_mpa_rx {
172 u8 *buf;
173 u32 buf_len;
174 u32 pkt_cnt;
5ac253d5 175 u32 ports;
5e6e3a92
BZ		 176 u16 start_port;
177
c23b7c8f
AK		 178 struct sk_buff **skb_arr;
179 u32 *len_arr;
5e6e3a92
BZ		 180
181 u8 enabled;
182 u32 buf_size;
183 u32 pkt_aggr_limit;
184};
185
186int mwifiex_bus_register(void);
187void mwifiex_bus_unregister(void);
188
05889f82
AK		 189struct mwifiex_sdio_card_reg {
190 u8 start_rd_port;
191 u8 start_wr_port;
192 u8 base_0_reg;
193 u8 base_1_reg;
194 u8 poll_reg;
195 u8 host_int_enable;
554a0113
AP		 196 u8 host_int_rsr_reg;
197 u8 host_int_status_reg;
198 u8 host_int_mask_reg;
05889f82
AK		 199 u8 status_reg_0;
200 u8 status_reg_1;
201 u8 sdio_int_mask;
202 u32 data_port_mask;
554a0113
AP		 203 u8 io_port_0_reg;
204 u8 io_port_1_reg;
205 u8 io_port_2_reg;
05889f82
AK		 206 u8 max_mp_regs;
207 u8 rd_bitmap_l;
208 u8 rd_bitmap_u;
b60186f8
YAP		 209 u8 rd_bitmap_1l;
210 u8 rd_bitmap_1u;
05889f82
AK		 211 u8 wr_bitmap_l;
212 u8 wr_bitmap_u;
b60186f8
YAP		 213 u8 wr_bitmap_1l;
214 u8 wr_bitmap_1u;
05889f82
AK		 215 u8 rd_len_p0_l;
216 u8 rd_len_p0_u;
217 u8 card_misc_cfg_reg;
554a0113
AP		 218 u8 card_cfg_2_1_reg;
219 u8 cmd_rd_len_0;
220 u8 cmd_rd_len_1;
221 u8 cmd_rd_len_2;
222 u8 cmd_rd_len_3;
223 u8 cmd_cfg_0;
224 u8 cmd_cfg_1;
225 u8 cmd_cfg_2;
226 u8 cmd_cfg_3;
eee7f196 227 u8 fw_dump_host_ready;
54881c6b
AK		 228 u8 fw_dump_ctrl;
229 u8 fw_dump_start;
230 u8 fw_dump_end;
809c6ea8
XH		 231 u8 func1_dump_reg_start;
232 u8 func1_dump_reg_end;
233 u8 func1_scratch_reg;
234 u8 func1_spec_reg_num;
235 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
05889f82
AK		 236};
237
5e6e3a92
BZ		 238struct sdio_mmc_card {
239 struct sdio_func *func;
240 struct mwifiex_adapter *adapter;
241
4a79aa17 242 struct completion fw_done;
05889f82
AK		 243 const char *firmware;
244 const struct mwifiex_sdio_card_reg *reg;
245 u8 max_ports;
246 u8 mp_agg_pkt_limit;
828cf222 247 u16 tx_buf_size;
e1aa93a4
AK		 248 u32 mp_tx_agg_buf_size;
249 u32 mp_rx_agg_buf_size;
05889f82 250
5ac253d5
AK		 251 u32 mp_rd_bitmap;
252 u32 mp_wr_bitmap;
5e6e3a92
BZ		 253
254 u16 mp_end_port;
5ac253d5 255 u32 mp_data_port_mask;
5e6e3a92
BZ		 256
257 u8 curr_rd_port;
258 u8 curr_wr_port;
259
260 u8 *mp_regs;
b4e8aebb
AP		 261 bool supports_sdio_new_mode;
262 bool has_control_mask;
263 bool can_dump_fw;
eee7f196 264 bool fw_dump_enh;
b4e8aebb 265 bool can_auto_tdls;
1fe192d8 266 bool can_ext_scan;
5e6e3a92
BZ		 267
268 struct mwifiex_sdio_mpa_tx mpa_tx;
269 struct mwifiex_sdio_mpa_rx mpa_rx;
b4336a28
AF		 270
271 /* needed for card reset */
272 const struct sdio_device_id *device_id;
5e6e3a92 273};
d930faee 274
05889f82
AK		 275struct mwifiex_sdio_device {
276 const char *firmware;
277 const struct mwifiex_sdio_card_reg *reg;
278 u8 max_ports;
279 u8 mp_agg_pkt_limit;
828cf222 280 u16 tx_buf_size;
e1aa93a4
AK		 281 u32 mp_tx_agg_buf_size;
282 u32 mp_rx_agg_buf_size;
b4e8aebb
AP		 283 bool supports_sdio_new_mode;
284 bool has_control_mask;
285 bool can_dump_fw;
eee7f196 286 bool fw_dump_enh;
b4e8aebb 287 bool can_auto_tdls;
1fe192d8 288 bool can_ext_scan;
05889f82
AK		 289};
290
291static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
292 .start_rd_port = 1,
293 .start_wr_port = 1,
294 .base_0_reg = 0x0040,
295 .base_1_reg = 0x0041,
296 .poll_reg = 0x30,
297 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
554a0113
AP		 298 .host_int_rsr_reg = 0x1,
299 .host_int_mask_reg = 0x02,
300 .host_int_status_reg = 0x03,
05889f82
AK		 301 .status_reg_0 = 0x60,
302 .status_reg_1 = 0x61,
303 .sdio_int_mask = 0x3f,
304 .data_port_mask = 0x0000fffe,
554a0113
AP		 305 .io_port_0_reg = 0x78,
306 .io_port_1_reg = 0x79,
307 .io_port_2_reg = 0x7A,
05889f82
AK		 308 .max_mp_regs = 64,
309 .rd_bitmap_l = 0x04,
310 .rd_bitmap_u = 0x05,
311 .wr_bitmap_l = 0x06,
312 .wr_bitmap_u = 0x07,
313 .rd_len_p0_l = 0x08,
314 .rd_len_p0_u = 0x09,
315 .card_misc_cfg_reg = 0x6c,
809c6ea8
XH		 316 .func1_dump_reg_start = 0x0,
317 .func1_dump_reg_end = 0x9,
318 .func1_scratch_reg = 0x60,
319 .func1_spec_reg_num = 5,
320 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
05889f82
AK		 321};
322
b60186f8
YAP		 323static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
324 .start_rd_port = 0,
325 .start_wr_port = 0,
326 .base_0_reg = 0x60,
327 .base_1_reg = 0x61,
328 .poll_reg = 0x50,
329 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
330 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
554a0113
AP		 331 .host_int_rsr_reg = 0x1,
332 .host_int_status_reg = 0x03,
333 .host_int_mask_reg = 0x02,
b60186f8
YAP		 334 .status_reg_0 = 0xc0,
335 .status_reg_1 = 0xc1,
336 .sdio_int_mask = 0xff,
337 .data_port_mask = 0xffffffff,
554a0113
AP		 338 .io_port_0_reg = 0xD8,
339 .io_port_1_reg = 0xD9,
340 .io_port_2_reg = 0xDA,
b60186f8
YAP		 341 .max_mp_regs = 184,
342 .rd_bitmap_l = 0x04,
343 .rd_bitmap_u = 0x05,
344 .rd_bitmap_1l = 0x06,
345 .rd_bitmap_1u = 0x07,
346 .wr_bitmap_l = 0x08,
347 .wr_bitmap_u = 0x09,
348 .wr_bitmap_1l = 0x0a,
349 .wr_bitmap_1u = 0x0b,
350 .rd_len_p0_l = 0x0c,
351 .rd_len_p0_u = 0x0d,
352 .card_misc_cfg_reg = 0xcc,
554a0113
AP		 353 .card_cfg_2_1_reg = 0xcd,
354 .cmd_rd_len_0 = 0xb4,
355 .cmd_rd_len_1 = 0xb5,
356 .cmd_rd_len_2 = 0xb6,
357 .cmd_rd_len_3 = 0xb7,
358 .cmd_cfg_0 = 0xb8,
359 .cmd_cfg_1 = 0xb9,
360 .cmd_cfg_2 = 0xba,
361 .cmd_cfg_3 = 0xbb,
eee7f196 362 .fw_dump_host_ready = 0xee,
54881c6b
AK		 363 .fw_dump_ctrl = 0xe2,
364 .fw_dump_start = 0xe3,
365 .fw_dump_end = 0xea,
809c6ea8
XH		 366 .func1_dump_reg_start = 0x0,
367 .func1_dump_reg_end = 0xb,
368 .func1_scratch_reg = 0xc0,
369 .func1_spec_reg_num = 8,
370 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
371 0x59, 0x5c, 0x5d},
b60186f8
YAP		 372};
373
6d85ef00
ZL		 374static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = {
375 .start_rd_port = 0,
376 .start_wr_port = 0,
377 .base_0_reg = 0xF8,
378 .base_1_reg = 0xF9,
379 .poll_reg = 0x5C,
380 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
381 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
382 .host_int_rsr_reg = 0x4,
383 .host_int_status_reg = 0x0C,
384 .host_int_mask_reg = 0x08,
385 .status_reg_0 = 0xE8,
386 .status_reg_1 = 0xE9,
387 .sdio_int_mask = 0xff,
388 .data_port_mask = 0xffffffff,
389 .io_port_0_reg = 0xE4,
390 .io_port_1_reg = 0xE5,
391 .io_port_2_reg = 0xE6,
392 .max_mp_regs = 196,
393 .rd_bitmap_l = 0x10,
394 .rd_bitmap_u = 0x11,
395 .rd_bitmap_1l = 0x12,
396 .rd_bitmap_1u = 0x13,
397 .wr_bitmap_l = 0x14,
398 .wr_bitmap_u = 0x15,
399 .wr_bitmap_1l = 0x16,
400 .wr_bitmap_1u = 0x17,
401 .rd_len_p0_l = 0x18,
402 .rd_len_p0_u = 0x19,
403 .card_misc_cfg_reg = 0xd8,
404 .card_cfg_2_1_reg = 0xd9,
405 .cmd_rd_len_0 = 0xc0,
406 .cmd_rd_len_1 = 0xc1,
407 .cmd_rd_len_2 = 0xc2,
408 .cmd_rd_len_3 = 0xc3,
409 .cmd_cfg_0 = 0xc4,
410 .cmd_cfg_1 = 0xc5,
411 .cmd_cfg_2 = 0xc6,
412 .cmd_cfg_3 = 0xc7,
eee7f196
ZL		 413 .fw_dump_host_ready = 0xcc,
414 .fw_dump_ctrl = 0xf0,
415 .fw_dump_start = 0xf1,
416 .fw_dump_end = 0xf8,
6d85ef00
ZL		 417 .func1_dump_reg_start = 0x10,
418 .func1_dump_reg_end = 0x17,
419 .func1_scratch_reg = 0xe8,
420 .func1_spec_reg_num = 13,
421 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D,
422 0x60, 0x61, 0x62, 0x64,
423 0x65, 0x66, 0x68, 0x69,
424 0x6a},
425};
426
030bb75a
AP		 427static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
428 .start_rd_port = 0,
429 .start_wr_port = 0,
430 .base_0_reg = 0x6C,
431 .base_1_reg = 0x6D,
432 .poll_reg = 0x5C,
433 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
434 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
435 .host_int_rsr_reg = 0x4,
436 .host_int_status_reg = 0x0C,
437 .host_int_mask_reg = 0x08,
438 .status_reg_0 = 0x90,
439 .status_reg_1 = 0x91,
440 .sdio_int_mask = 0xff,
441 .data_port_mask = 0xffffffff,
442 .io_port_0_reg = 0xE4,
443 .io_port_1_reg = 0xE5,
444 .io_port_2_reg = 0xE6,
445 .max_mp_regs = 196,
446 .rd_bitmap_l = 0x10,
447 .rd_bitmap_u = 0x11,
448 .rd_bitmap_1l = 0x12,
449 .rd_bitmap_1u = 0x13,
450 .wr_bitmap_l = 0x14,
451 .wr_bitmap_u = 0x15,
452 .wr_bitmap_1l = 0x16,
453 .wr_bitmap_1u = 0x17,
454 .rd_len_p0_l = 0x18,
455 .rd_len_p0_u = 0x19,
456 .card_misc_cfg_reg = 0xd8,
457 .card_cfg_2_1_reg = 0xd9,
458 .cmd_rd_len_0 = 0xc0,
459 .cmd_rd_len_1 = 0xc1,
460 .cmd_rd_len_2 = 0xc2,
461 .cmd_rd_len_3 = 0xc3,
462 .cmd_cfg_0 = 0xc4,
463 .cmd_cfg_1 = 0xc5,
464 .cmd_cfg_2 = 0xc6,
465 .cmd_cfg_3 = 0xc7,
809c6ea8
XH		 466 .func1_dump_reg_start = 0x10,
467 .func1_dump_reg_end = 0x17,
468 .func1_scratch_reg = 0x90,
469 .func1_spec_reg_num = 13,
470 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
471 0x61, 0x62, 0x64, 0x65, 0x66,
472 0x68, 0x69, 0x6a},
030bb75a
AP		 473};
474
05889f82
AK		 475static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
476 .firmware = SD8786_DEFAULT_FW_NAME,
477 .reg = &mwifiex_reg_sd87xx,
478 .max_ports = 16,
479 .mp_agg_pkt_limit = 8,
828cf222 480 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4
AK		 481 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
482 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 483 .supports_sdio_new_mode = false,
484 .has_control_mask = true,
485 .can_dump_fw = false,
486 .can_auto_tdls = false,
1fe192d8 487 .can_ext_scan = false,
05889f82
AK		 488};
489
490static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
491 .firmware = SD8787_DEFAULT_FW_NAME,
492 .reg = &mwifiex_reg_sd87xx,
493 .max_ports = 16,
494 .mp_agg_pkt_limit = 8,
828cf222 495 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4
AK		 496 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
497 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 498 .supports_sdio_new_mode = false,
499 .has_control_mask = true,
500 .can_dump_fw = false,
501 .can_auto_tdls = false,
1fe192d8 502 .can_ext_scan = true,
05889f82
AK		 503};
504
505static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
506 .firmware = SD8797_DEFAULT_FW_NAME,
507 .reg = &mwifiex_reg_sd87xx,
508 .max_ports = 16,
509 .mp_agg_pkt_limit = 8,
828cf222 510 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4
AK		 511 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
512 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 513 .supports_sdio_new_mode = false,
514 .has_control_mask = true,
515 .can_dump_fw = false,
516 .can_auto_tdls = false,
1fe192d8 517 .can_ext_scan = true,
b60186f8
YAP		 518};
519
520static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
521 .firmware = SD8897_DEFAULT_FW_NAME,
522 .reg = &mwifiex_reg_sd8897,
523 .max_ports = 32,
524 .mp_agg_pkt_limit = 16,
828cf222 525 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
ea44f4d0
AP		 526 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
527 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
b4e8aebb
AP		 528 .supports_sdio_new_mode = true,
529 .has_control_mask = false,
530 .can_dump_fw = true,
531 .can_auto_tdls = false,
6d85ef00
ZL		 532 .can_ext_scan = true,
533};
534
535static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = {
536 .firmware = SD8997_DEFAULT_FW_NAME,
537 .reg = &mwifiex_reg_sd8997,
538 .max_ports = 32,
539 .mp_agg_pkt_limit = 16,
540 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
541 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
542 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
543 .supports_sdio_new_mode = true,
544 .has_control_mask = false,
eee7f196
ZL		 545 .can_dump_fw = true,
546 .fw_dump_enh = true,
6d85ef00 547 .can_auto_tdls = false,
1fe192d8 548 .can_ext_scan = true,
05889f82
AK		 549};
550
030bb75a
AP		 551static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
552 .firmware = SD8887_DEFAULT_FW_NAME,
553 .reg = &mwifiex_reg_sd8887,
554 .max_ports = 32,
555 .mp_agg_pkt_limit = 16,
1c4c24eb 556 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
030bb75a
AP		 557 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
558 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
b4e8aebb
AP		 559 .supports_sdio_new_mode = true,
560 .has_control_mask = false,
561 .can_dump_fw = false,
562 .can_auto_tdls = true,
1fe192d8 563 .can_ext_scan = true,
030bb75a
AP		 564};
565
52bd3d20
YAP		 566static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
567 .firmware = SD8801_DEFAULT_FW_NAME,
568 .reg = &mwifiex_reg_sd87xx,
569 .max_ports = 16,
570 .mp_agg_pkt_limit = 8,
571 .supports_sdio_new_mode = false,
572 .has_control_mask = true,
573 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
574 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
575 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 576 .can_dump_fw = false,
577 .can_auto_tdls = false,
1fe192d8 578 .can_ext_scan = true,
52bd3d20
YAP		 579};
580
d930faee
AK		 581/*
582 * .cmdrsp_complete handler
583 */
584static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
585 struct sk_buff *skb)
586{
587 dev_kfree_skb_any(skb);
588 return 0;
589}
590
591/*
592 * .event_complete handler
593 */
594static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
595 struct sk_buff *skb)
596{
597 dev_kfree_skb_any(skb);
598 return 0;
599}
600
c23b7c8f
AK		 601static inline bool
602mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
603{
604 u8 tmp;
605
606 if (card->curr_rd_port < card->mpa_rx.start_port) {
b60186f8
YAP		 607 if (card->supports_sdio_new_mode)
608 tmp = card->mp_end_port >> 1;
609 else
610 tmp = card->mp_agg_pkt_limit;
c23b7c8f
AK		 611
612 if (((card->max_ports - card->mpa_rx.start_port) +
613 card->curr_rd_port) >= tmp)
614 return true;
615 }
616
b60186f8
YAP		 617 if (!card->supports_sdio_new_mode)
618 return false;
619
620 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
621 (card->mp_end_port >> 1))
622 return true;
623
c23b7c8f
AK		 624 return false;
625}
626
627static inline bool
628mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
629{
630 u16 tmp;
631
632 if (card->curr_wr_port < card->mpa_tx.start_port) {
b60186f8
YAP		 633 if (card->supports_sdio_new_mode)
634 tmp = card->mp_end_port >> 1;
635 else
636 tmp = card->mp_agg_pkt_limit;
c23b7c8f
AK		 637
638 if (((card->max_ports - card->mpa_tx.start_port) +
639 card->curr_wr_port) >= tmp)
640 return true;
641 }
642
b60186f8
YAP		 643 if (!card->supports_sdio_new_mode)
644 return false;
645
646 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
647 (card->mp_end_port >> 1))
648 return true;
649
c23b7c8f
AK		 650 return false;
651}
652
653/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
654static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
960d6d08 655 u16 rx_len, u8 port)
c23b7c8f 656{
960d6d08 657 card->mpa_rx.buf_len += rx_len;
c23b7c8f
AK		 658
659 if (!card->mpa_rx.pkt_cnt)
660 card->mpa_rx.start_port = port;
661
b60186f8
YAP		 662 if (card->supports_sdio_new_mode) {
663 card->mpa_rx.ports |= (1 << port);
664 } else {
665 if (card->mpa_rx.start_port <= port)
666 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
667 else
668 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
669 }
960d6d08
ZL		 670 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
671 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
c23b7c8f
AK		 672 card->mpa_rx.pkt_cnt++;
673}
5e6e3a92 674#endif /* _MWIFIEX_SDIO_H */
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