]>
Commit | Line | Data |
---|---|---|
a66098da | 1 | /* |
ce9e2e1b LB |
2 | * drivers/net/wireless/mwl8k.c |
3 | * Driver for Marvell TOPDOG 802.11 Wireless cards | |
a66098da | 4 | * |
a145d575 | 5 | * Copyright (C) 2008-2009 Marvell Semiconductor Inc. |
a66098da LB |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
3d76e82c | 15 | #include <linux/sched.h> |
a66098da LB |
16 | #include <linux/spinlock.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/workqueue.h> | |
26 | ||
27 | #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" | |
28 | #define MWL8K_NAME KBUILD_MODNAME | |
6976b665 | 29 | #define MWL8K_VERSION "0.11" |
a66098da | 30 | |
a66098da LB |
31 | /* Register definitions */ |
32 | #define MWL8K_HIU_GEN_PTR 0x00000c10 | |
ce9e2e1b LB |
33 | #define MWL8K_MODE_STA 0x0000005a |
34 | #define MWL8K_MODE_AP 0x000000a5 | |
a66098da | 35 | #define MWL8K_HIU_INT_CODE 0x00000c14 |
ce9e2e1b LB |
36 | #define MWL8K_FWSTA_READY 0xf0f1f2f4 |
37 | #define MWL8K_FWAP_READY 0xf1f2f4a5 | |
38 | #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 | |
a66098da LB |
39 | #define MWL8K_HIU_SCRATCH 0x00000c40 |
40 | ||
41 | /* Host->device communications */ | |
42 | #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 | |
43 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c | |
44 | #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 | |
45 | #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 | |
46 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 | |
ce9e2e1b LB |
47 | #define MWL8K_H2A_INT_DUMMY (1 << 20) |
48 | #define MWL8K_H2A_INT_RESET (1 << 15) | |
49 | #define MWL8K_H2A_INT_DOORBELL (1 << 1) | |
50 | #define MWL8K_H2A_INT_PPA_READY (1 << 0) | |
a66098da LB |
51 | |
52 | /* Device->host communications */ | |
53 | #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c | |
54 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 | |
55 | #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 | |
56 | #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 | |
57 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c | |
ce9e2e1b LB |
58 | #define MWL8K_A2H_INT_DUMMY (1 << 20) |
59 | #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) | |
60 | #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) | |
61 | #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) | |
62 | #define MWL8K_A2H_INT_RADIO_ON (1 << 6) | |
63 | #define MWL8K_A2H_INT_RADIO_OFF (1 << 5) | |
64 | #define MWL8K_A2H_INT_MAC_EVENT (1 << 3) | |
65 | #define MWL8K_A2H_INT_OPC_DONE (1 << 2) | |
66 | #define MWL8K_A2H_INT_RX_READY (1 << 1) | |
67 | #define MWL8K_A2H_INT_TX_DONE (1 << 0) | |
a66098da LB |
68 | |
69 | #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ | |
70 | MWL8K_A2H_INT_CHNL_SWITCHED | \ | |
71 | MWL8K_A2H_INT_QUEUE_EMPTY | \ | |
72 | MWL8K_A2H_INT_RADAR_DETECT | \ | |
73 | MWL8K_A2H_INT_RADIO_ON | \ | |
74 | MWL8K_A2H_INT_RADIO_OFF | \ | |
75 | MWL8K_A2H_INT_MAC_EVENT | \ | |
76 | MWL8K_A2H_INT_OPC_DONE | \ | |
77 | MWL8K_A2H_INT_RX_READY | \ | |
78 | MWL8K_A2H_INT_TX_DONE) | |
79 | ||
a66098da LB |
80 | #define MWL8K_RX_QUEUES 1 |
81 | #define MWL8K_TX_QUEUES 4 | |
82 | ||
54bc3a0d LB |
83 | struct rxd_ops { |
84 | int rxd_size; | |
85 | void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); | |
86 | void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); | |
20f09c3d LB |
87 | int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, |
88 | __le16 *qos); | |
54bc3a0d LB |
89 | }; |
90 | ||
45a390dd | 91 | struct mwl8k_device_info { |
a74b295e LB |
92 | char *part_name; |
93 | char *helper_image; | |
94 | char *fw_image; | |
89a91f4f | 95 | struct rxd_ops *ap_rxd_ops; |
45a390dd LB |
96 | }; |
97 | ||
a66098da | 98 | struct mwl8k_rx_queue { |
45eb400d | 99 | int rxd_count; |
a66098da LB |
100 | |
101 | /* hw receives here */ | |
45eb400d | 102 | int head; |
a66098da LB |
103 | |
104 | /* refill descs here */ | |
45eb400d | 105 | int tail; |
a66098da | 106 | |
54bc3a0d | 107 | void *rxd; |
45eb400d | 108 | dma_addr_t rxd_dma; |
788838eb LB |
109 | struct { |
110 | struct sk_buff *skb; | |
111 | DECLARE_PCI_UNMAP_ADDR(dma) | |
112 | } *buf; | |
a66098da LB |
113 | }; |
114 | ||
a66098da LB |
115 | struct mwl8k_tx_queue { |
116 | /* hw transmits here */ | |
45eb400d | 117 | int head; |
a66098da LB |
118 | |
119 | /* sw appends here */ | |
45eb400d | 120 | int tail; |
a66098da | 121 | |
45eb400d LB |
122 | struct ieee80211_tx_queue_stats stats; |
123 | struct mwl8k_tx_desc *txd; | |
124 | dma_addr_t txd_dma; | |
125 | struct sk_buff **skb; | |
a66098da LB |
126 | }; |
127 | ||
a66098da | 128 | struct mwl8k_priv { |
a66098da | 129 | struct ieee80211_hw *hw; |
a66098da | 130 | struct pci_dev *pdev; |
a66098da | 131 | |
45a390dd LB |
132 | struct mwl8k_device_info *device_info; |
133 | ||
be695fc4 LB |
134 | void __iomem *sram; |
135 | void __iomem *regs; | |
136 | ||
137 | /* firmware */ | |
22be40d9 LB |
138 | struct firmware *fw_helper; |
139 | struct firmware *fw_ucode; | |
a66098da | 140 | |
be695fc4 LB |
141 | /* hardware/firmware parameters */ |
142 | bool ap_fw; | |
143 | struct rxd_ops *rxd_ops; | |
144 | ||
618952a7 LB |
145 | /* firmware access */ |
146 | struct mutex fw_mutex; | |
147 | struct task_struct *fw_mutex_owner; | |
148 | int fw_mutex_depth; | |
618952a7 LB |
149 | struct completion *hostcmd_wait; |
150 | ||
a66098da LB |
151 | /* lock held over TX and TX reap */ |
152 | spinlock_t tx_lock; | |
a66098da | 153 | |
88de754a LB |
154 | /* TX quiesce completion, protected by fw_mutex and tx_lock */ |
155 | struct completion *tx_wait; | |
156 | ||
a66098da | 157 | struct ieee80211_vif *vif; |
a66098da LB |
158 | |
159 | struct ieee80211_channel *current_channel; | |
160 | ||
161 | /* power management status cookie from firmware */ | |
162 | u32 *cookie; | |
163 | dma_addr_t cookie_dma; | |
164 | ||
165 | u16 num_mcaddrs; | |
a66098da | 166 | u8 hw_rev; |
2aa7b01f | 167 | u32 fw_rev; |
a66098da LB |
168 | |
169 | /* | |
170 | * Running count of TX packets in flight, to avoid | |
171 | * iterating over the transmit rings each time. | |
172 | */ | |
173 | int pending_tx_pkts; | |
174 | ||
175 | struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; | |
176 | struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; | |
177 | ||
178 | /* PHY parameters */ | |
179 | struct ieee80211_supported_band band; | |
180 | struct ieee80211_channel channels[14]; | |
140eb5e2 | 181 | struct ieee80211_rate rates[14]; |
a66098da | 182 | |
c46563b7 | 183 | bool radio_on; |
68ce3884 | 184 | bool radio_short_preamble; |
a43c49a8 | 185 | bool sniffer_enabled; |
0439b1f5 | 186 | bool wmm_enabled; |
a66098da | 187 | |
bbfd9128 LB |
188 | struct work_struct sta_notify_worker; |
189 | spinlock_t sta_notify_list_lock; | |
190 | struct list_head sta_notify_list; | |
191 | ||
a66098da LB |
192 | /* XXX need to convert this to handle multiple interfaces */ |
193 | bool capture_beacon; | |
d89173f2 | 194 | u8 capture_bssid[ETH_ALEN]; |
a66098da LB |
195 | struct sk_buff *beacon_skb; |
196 | ||
197 | /* | |
198 | * This FJ worker has to be global as it is scheduled from the | |
199 | * RX handler. At this point we don't know which interface it | |
200 | * belongs to until the list of bssids waiting to complete join | |
201 | * is checked. | |
202 | */ | |
203 | struct work_struct finalize_join_worker; | |
204 | ||
205 | /* Tasklet to reclaim TX descriptors and buffers after tx */ | |
206 | struct tasklet_struct tx_reclaim_task; | |
a66098da LB |
207 | }; |
208 | ||
209 | /* Per interface specific private data */ | |
210 | struct mwl8k_vif { | |
c2c2b12a | 211 | /* Non AMPDU sequence number assigned by driver. */ |
a680400e | 212 | u16 seqno; |
a66098da | 213 | }; |
a94cc97e | 214 | #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) |
a66098da | 215 | |
a680400e LB |
216 | struct mwl8k_sta { |
217 | /* Index into station database. Returned by UPDATE_STADB. */ | |
218 | u8 peer_id; | |
219 | }; | |
220 | #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv)) | |
221 | ||
a66098da LB |
222 | static const struct ieee80211_channel mwl8k_channels[] = { |
223 | { .center_freq = 2412, .hw_value = 1, }, | |
224 | { .center_freq = 2417, .hw_value = 2, }, | |
225 | { .center_freq = 2422, .hw_value = 3, }, | |
226 | { .center_freq = 2427, .hw_value = 4, }, | |
227 | { .center_freq = 2432, .hw_value = 5, }, | |
228 | { .center_freq = 2437, .hw_value = 6, }, | |
229 | { .center_freq = 2442, .hw_value = 7, }, | |
230 | { .center_freq = 2447, .hw_value = 8, }, | |
231 | { .center_freq = 2452, .hw_value = 9, }, | |
232 | { .center_freq = 2457, .hw_value = 10, }, | |
233 | { .center_freq = 2462, .hw_value = 11, }, | |
647ca6b0 LB |
234 | { .center_freq = 2467, .hw_value = 12, }, |
235 | { .center_freq = 2472, .hw_value = 13, }, | |
236 | { .center_freq = 2484, .hw_value = 14, }, | |
a66098da LB |
237 | }; |
238 | ||
239 | static const struct ieee80211_rate mwl8k_rates[] = { | |
240 | { .bitrate = 10, .hw_value = 2, }, | |
241 | { .bitrate = 20, .hw_value = 4, }, | |
242 | { .bitrate = 55, .hw_value = 11, }, | |
5dfd3e2c LB |
243 | { .bitrate = 110, .hw_value = 22, }, |
244 | { .bitrate = 220, .hw_value = 44, }, | |
a66098da LB |
245 | { .bitrate = 60, .hw_value = 12, }, |
246 | { .bitrate = 90, .hw_value = 18, }, | |
a66098da LB |
247 | { .bitrate = 120, .hw_value = 24, }, |
248 | { .bitrate = 180, .hw_value = 36, }, | |
249 | { .bitrate = 240, .hw_value = 48, }, | |
250 | { .bitrate = 360, .hw_value = 72, }, | |
251 | { .bitrate = 480, .hw_value = 96, }, | |
252 | { .bitrate = 540, .hw_value = 108, }, | |
140eb5e2 LB |
253 | { .bitrate = 720, .hw_value = 144, }, |
254 | }; | |
255 | ||
a66098da LB |
256 | /* Set or get info from Firmware */ |
257 | #define MWL8K_CMD_SET 0x0001 | |
258 | #define MWL8K_CMD_GET 0x0000 | |
259 | ||
260 | /* Firmware command codes */ | |
261 | #define MWL8K_CMD_CODE_DNLD 0x0001 | |
262 | #define MWL8K_CMD_GET_HW_SPEC 0x0003 | |
42fba21d | 263 | #define MWL8K_CMD_SET_HW_SPEC 0x0004 |
a66098da LB |
264 | #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 |
265 | #define MWL8K_CMD_GET_STAT 0x0014 | |
ff45fc60 LB |
266 | #define MWL8K_CMD_RADIO_CONTROL 0x001c |
267 | #define MWL8K_CMD_RF_TX_POWER 0x001e | |
08b06347 | 268 | #define MWL8K_CMD_RF_ANTENNA 0x0020 |
a66098da LB |
269 | #define MWL8K_CMD_SET_PRE_SCAN 0x0107 |
270 | #define MWL8K_CMD_SET_POST_SCAN 0x0108 | |
ff45fc60 LB |
271 | #define MWL8K_CMD_SET_RF_CHANNEL 0x010a |
272 | #define MWL8K_CMD_SET_AID 0x010d | |
273 | #define MWL8K_CMD_SET_RATE 0x0110 | |
274 | #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 | |
275 | #define MWL8K_CMD_RTS_THRESHOLD 0x0113 | |
a66098da | 276 | #define MWL8K_CMD_SET_SLOT 0x0114 |
ff45fc60 LB |
277 | #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 |
278 | #define MWL8K_CMD_SET_WMM_MODE 0x0123 | |
a66098da | 279 | #define MWL8K_CMD_MIMO_CONFIG 0x0125 |
ff45fc60 | 280 | #define MWL8K_CMD_USE_FIXED_RATE 0x0126 |
a66098da | 281 | #define MWL8K_CMD_ENABLE_SNIFFER 0x0150 |
32060e1b | 282 | #define MWL8K_CMD_SET_MAC_ADDR 0x0202 |
a66098da | 283 | #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 |
ff45fc60 | 284 | #define MWL8K_CMD_UPDATE_STADB 0x1123 |
a66098da LB |
285 | |
286 | static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) | |
287 | { | |
288 | #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ | |
289 | snprintf(buf, bufsize, "%s", #x);\ | |
290 | return buf;\ | |
291 | } while (0) | |
ce9e2e1b | 292 | switch (cmd & ~0x8000) { |
a66098da LB |
293 | MWL8K_CMDNAME(CODE_DNLD); |
294 | MWL8K_CMDNAME(GET_HW_SPEC); | |
42fba21d | 295 | MWL8K_CMDNAME(SET_HW_SPEC); |
a66098da LB |
296 | MWL8K_CMDNAME(MAC_MULTICAST_ADR); |
297 | MWL8K_CMDNAME(GET_STAT); | |
298 | MWL8K_CMDNAME(RADIO_CONTROL); | |
299 | MWL8K_CMDNAME(RF_TX_POWER); | |
08b06347 | 300 | MWL8K_CMDNAME(RF_ANTENNA); |
a66098da LB |
301 | MWL8K_CMDNAME(SET_PRE_SCAN); |
302 | MWL8K_CMDNAME(SET_POST_SCAN); | |
303 | MWL8K_CMDNAME(SET_RF_CHANNEL); | |
ff45fc60 LB |
304 | MWL8K_CMDNAME(SET_AID); |
305 | MWL8K_CMDNAME(SET_RATE); | |
306 | MWL8K_CMDNAME(SET_FINALIZE_JOIN); | |
307 | MWL8K_CMDNAME(RTS_THRESHOLD); | |
a66098da | 308 | MWL8K_CMDNAME(SET_SLOT); |
ff45fc60 LB |
309 | MWL8K_CMDNAME(SET_EDCA_PARAMS); |
310 | MWL8K_CMDNAME(SET_WMM_MODE); | |
a66098da | 311 | MWL8K_CMDNAME(MIMO_CONFIG); |
ff45fc60 | 312 | MWL8K_CMDNAME(USE_FIXED_RATE); |
a66098da | 313 | MWL8K_CMDNAME(ENABLE_SNIFFER); |
32060e1b | 314 | MWL8K_CMDNAME(SET_MAC_ADDR); |
a66098da | 315 | MWL8K_CMDNAME(SET_RATEADAPT_MODE); |
ff45fc60 | 316 | MWL8K_CMDNAME(UPDATE_STADB); |
a66098da LB |
317 | default: |
318 | snprintf(buf, bufsize, "0x%x", cmd); | |
319 | } | |
320 | #undef MWL8K_CMDNAME | |
321 | ||
322 | return buf; | |
323 | } | |
324 | ||
325 | /* Hardware and firmware reset */ | |
326 | static void mwl8k_hw_reset(struct mwl8k_priv *priv) | |
327 | { | |
328 | iowrite32(MWL8K_H2A_INT_RESET, | |
329 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
330 | iowrite32(MWL8K_H2A_INT_RESET, | |
331 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
332 | msleep(20); | |
333 | } | |
334 | ||
335 | /* Release fw image */ | |
336 | static void mwl8k_release_fw(struct firmware **fw) | |
337 | { | |
338 | if (*fw == NULL) | |
339 | return; | |
340 | release_firmware(*fw); | |
341 | *fw = NULL; | |
342 | } | |
343 | ||
344 | static void mwl8k_release_firmware(struct mwl8k_priv *priv) | |
345 | { | |
22be40d9 LB |
346 | mwl8k_release_fw(&priv->fw_ucode); |
347 | mwl8k_release_fw(&priv->fw_helper); | |
a66098da LB |
348 | } |
349 | ||
350 | /* Request fw image */ | |
351 | static int mwl8k_request_fw(struct mwl8k_priv *priv, | |
c2c357ce | 352 | const char *fname, struct firmware **fw) |
a66098da LB |
353 | { |
354 | /* release current image */ | |
355 | if (*fw != NULL) | |
356 | mwl8k_release_fw(fw); | |
357 | ||
358 | return request_firmware((const struct firmware **)fw, | |
c2c357ce | 359 | fname, &priv->pdev->dev); |
a66098da LB |
360 | } |
361 | ||
45a390dd | 362 | static int mwl8k_request_firmware(struct mwl8k_priv *priv) |
a66098da | 363 | { |
a74b295e | 364 | struct mwl8k_device_info *di = priv->device_info; |
a66098da LB |
365 | int rc; |
366 | ||
a74b295e | 367 | if (di->helper_image != NULL) { |
22be40d9 | 368 | rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper); |
a74b295e LB |
369 | if (rc) { |
370 | printk(KERN_ERR "%s: Error requesting helper " | |
371 | "firmware file %s\n", pci_name(priv->pdev), | |
372 | di->helper_image); | |
373 | return rc; | |
374 | } | |
a66098da LB |
375 | } |
376 | ||
22be40d9 | 377 | rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode); |
a66098da | 378 | if (rc) { |
c2c357ce | 379 | printk(KERN_ERR "%s: Error requesting firmware file %s\n", |
a74b295e | 380 | pci_name(priv->pdev), di->fw_image); |
22be40d9 | 381 | mwl8k_release_fw(&priv->fw_helper); |
a66098da LB |
382 | return rc; |
383 | } | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
7e75b942 BH |
388 | MODULE_FIRMWARE("mwl8k/helper_8687.fw"); |
389 | MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); | |
390 | ||
a66098da LB |
391 | struct mwl8k_cmd_pkt { |
392 | __le16 code; | |
393 | __le16 length; | |
394 | __le16 seq_num; | |
395 | __le16 result; | |
396 | char payload[0]; | |
397 | } __attribute__((packed)); | |
398 | ||
399 | /* | |
400 | * Firmware loading. | |
401 | */ | |
402 | static int | |
403 | mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) | |
404 | { | |
405 | void __iomem *regs = priv->regs; | |
406 | dma_addr_t dma_addr; | |
a66098da LB |
407 | int loops; |
408 | ||
409 | dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); | |
410 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
411 | return -ENOMEM; | |
412 | ||
413 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
414 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
415 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
416 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
417 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
418 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
419 | ||
a66098da LB |
420 | loops = 1000; |
421 | do { | |
422 | u32 int_code; | |
423 | ||
424 | int_code = ioread32(regs + MWL8K_HIU_INT_CODE); | |
425 | if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { | |
426 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
a66098da LB |
427 | break; |
428 | } | |
429 | ||
3d76e82c | 430 | cond_resched(); |
a66098da LB |
431 | udelay(1); |
432 | } while (--loops); | |
433 | ||
434 | pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); | |
435 | ||
d4b70570 | 436 | return loops ? 0 : -ETIMEDOUT; |
a66098da LB |
437 | } |
438 | ||
439 | static int mwl8k_load_fw_image(struct mwl8k_priv *priv, | |
440 | const u8 *data, size_t length) | |
441 | { | |
442 | struct mwl8k_cmd_pkt *cmd; | |
443 | int done; | |
444 | int rc = 0; | |
445 | ||
446 | cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); | |
447 | if (cmd == NULL) | |
448 | return -ENOMEM; | |
449 | ||
450 | cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); | |
451 | cmd->seq_num = 0; | |
452 | cmd->result = 0; | |
453 | ||
454 | done = 0; | |
455 | while (length) { | |
456 | int block_size = length > 256 ? 256 : length; | |
457 | ||
458 | memcpy(cmd->payload, data + done, block_size); | |
459 | cmd->length = cpu_to_le16(block_size); | |
460 | ||
461 | rc = mwl8k_send_fw_load_cmd(priv, cmd, | |
462 | sizeof(*cmd) + block_size); | |
463 | if (rc) | |
464 | break; | |
465 | ||
466 | done += block_size; | |
467 | length -= block_size; | |
468 | } | |
469 | ||
470 | if (!rc) { | |
471 | cmd->length = 0; | |
472 | rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); | |
473 | } | |
474 | ||
475 | kfree(cmd); | |
476 | ||
477 | return rc; | |
478 | } | |
479 | ||
480 | static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, | |
481 | const u8 *data, size_t length) | |
482 | { | |
483 | unsigned char *buffer; | |
484 | int may_continue, rc = 0; | |
485 | u32 done, prev_block_size; | |
486 | ||
487 | buffer = kmalloc(1024, GFP_KERNEL); | |
488 | if (buffer == NULL) | |
489 | return -ENOMEM; | |
490 | ||
491 | done = 0; | |
492 | prev_block_size = 0; | |
493 | may_continue = 1000; | |
494 | while (may_continue > 0) { | |
495 | u32 block_size; | |
496 | ||
497 | block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); | |
498 | if (block_size & 1) { | |
499 | block_size &= ~1; | |
500 | may_continue--; | |
501 | } else { | |
502 | done += prev_block_size; | |
503 | length -= prev_block_size; | |
504 | } | |
505 | ||
506 | if (block_size > 1024 || block_size > length) { | |
507 | rc = -EOVERFLOW; | |
508 | break; | |
509 | } | |
510 | ||
511 | if (length == 0) { | |
512 | rc = 0; | |
513 | break; | |
514 | } | |
515 | ||
516 | if (block_size == 0) { | |
517 | rc = -EPROTO; | |
518 | may_continue--; | |
519 | udelay(1); | |
520 | continue; | |
521 | } | |
522 | ||
523 | prev_block_size = block_size; | |
524 | memcpy(buffer, data + done, block_size); | |
525 | ||
526 | rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); | |
527 | if (rc) | |
528 | break; | |
529 | } | |
530 | ||
531 | if (!rc && length != 0) | |
532 | rc = -EREMOTEIO; | |
533 | ||
534 | kfree(buffer); | |
535 | ||
536 | return rc; | |
537 | } | |
538 | ||
c2c357ce | 539 | static int mwl8k_load_firmware(struct ieee80211_hw *hw) |
a66098da | 540 | { |
c2c357ce | 541 | struct mwl8k_priv *priv = hw->priv; |
22be40d9 | 542 | struct firmware *fw = priv->fw_ucode; |
c2c357ce LB |
543 | int rc; |
544 | int loops; | |
545 | ||
546 | if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { | |
22be40d9 | 547 | struct firmware *helper = priv->fw_helper; |
a66098da | 548 | |
c2c357ce LB |
549 | if (helper == NULL) { |
550 | printk(KERN_ERR "%s: helper image needed but none " | |
551 | "given\n", pci_name(priv->pdev)); | |
552 | return -EINVAL; | |
553 | } | |
a66098da | 554 | |
c2c357ce | 555 | rc = mwl8k_load_fw_image(priv, helper->data, helper->size); |
a66098da LB |
556 | if (rc) { |
557 | printk(KERN_ERR "%s: unable to load firmware " | |
c2c357ce | 558 | "helper image\n", pci_name(priv->pdev)); |
a66098da LB |
559 | return rc; |
560 | } | |
89b872e2 | 561 | msleep(5); |
a66098da | 562 | |
c2c357ce | 563 | rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); |
a66098da | 564 | } else { |
c2c357ce | 565 | rc = mwl8k_load_fw_image(priv, fw->data, fw->size); |
a66098da LB |
566 | } |
567 | ||
568 | if (rc) { | |
c2c357ce LB |
569 | printk(KERN_ERR "%s: unable to load firmware image\n", |
570 | pci_name(priv->pdev)); | |
a66098da LB |
571 | return rc; |
572 | } | |
573 | ||
89a91f4f | 574 | iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); |
a66098da | 575 | |
89b872e2 | 576 | loops = 500000; |
a66098da | 577 | do { |
eae74e65 LB |
578 | u32 ready_code; |
579 | ||
580 | ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
581 | if (ready_code == MWL8K_FWAP_READY) { | |
582 | priv->ap_fw = 1; | |
583 | break; | |
584 | } else if (ready_code == MWL8K_FWSTA_READY) { | |
585 | priv->ap_fw = 0; | |
a66098da | 586 | break; |
eae74e65 LB |
587 | } |
588 | ||
589 | cond_resched(); | |
a66098da LB |
590 | udelay(1); |
591 | } while (--loops); | |
592 | ||
593 | return loops ? 0 : -ETIMEDOUT; | |
594 | } | |
595 | ||
596 | ||
a66098da LB |
597 | /* DMA header used by firmware and hardware. */ |
598 | struct mwl8k_dma_data { | |
599 | __le16 fwlen; | |
600 | struct ieee80211_hdr wh; | |
20f09c3d | 601 | char data[0]; |
a66098da LB |
602 | } __attribute__((packed)); |
603 | ||
604 | /* Routines to add/remove DMA header from skb. */ | |
20f09c3d | 605 | static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) |
a66098da | 606 | { |
20f09c3d LB |
607 | struct mwl8k_dma_data *tr; |
608 | int hdrlen; | |
609 | ||
610 | tr = (struct mwl8k_dma_data *)skb->data; | |
611 | hdrlen = ieee80211_hdrlen(tr->wh.frame_control); | |
612 | ||
613 | if (hdrlen != sizeof(tr->wh)) { | |
614 | if (ieee80211_is_data_qos(tr->wh.frame_control)) { | |
615 | memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); | |
616 | *((__le16 *)(tr->data - 2)) = qos; | |
617 | } else { | |
618 | memmove(tr->data - hdrlen, &tr->wh, hdrlen); | |
619 | } | |
a66098da | 620 | } |
20f09c3d LB |
621 | |
622 | if (hdrlen != sizeof(*tr)) | |
623 | skb_pull(skb, sizeof(*tr) - hdrlen); | |
a66098da LB |
624 | } |
625 | ||
76266b2a | 626 | static inline void mwl8k_add_dma_header(struct sk_buff *skb) |
a66098da LB |
627 | { |
628 | struct ieee80211_hdr *wh; | |
ca009301 | 629 | int hdrlen; |
a66098da LB |
630 | struct mwl8k_dma_data *tr; |
631 | ||
ca009301 LB |
632 | /* |
633 | * Add a firmware DMA header; the firmware requires that we | |
634 | * present a 2-byte payload length followed by a 4-address | |
635 | * header (without QoS field), followed (optionally) by any | |
636 | * WEP/ExtIV header (but only filled in for CCMP). | |
637 | */ | |
a66098da | 638 | wh = (struct ieee80211_hdr *)skb->data; |
ca009301 | 639 | |
a66098da | 640 | hdrlen = ieee80211_hdrlen(wh->frame_control); |
ca009301 LB |
641 | if (hdrlen != sizeof(*tr)) |
642 | skb_push(skb, sizeof(*tr) - hdrlen); | |
a66098da | 643 | |
ca009301 LB |
644 | if (ieee80211_is_data_qos(wh->frame_control)) |
645 | hdrlen -= 2; | |
a66098da LB |
646 | |
647 | tr = (struct mwl8k_dma_data *)skb->data; | |
648 | if (wh != &tr->wh) | |
649 | memmove(&tr->wh, wh, hdrlen); | |
ca009301 LB |
650 | if (hdrlen != sizeof(tr->wh)) |
651 | memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); | |
a66098da LB |
652 | |
653 | /* | |
654 | * Firmware length is the length of the fully formed "802.11 | |
655 | * payload". That is, everything except for the 802.11 header. | |
656 | * This includes all crypto material including the MIC. | |
657 | */ | |
ca009301 | 658 | tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr)); |
a66098da LB |
659 | } |
660 | ||
661 | ||
662 | /* | |
89a91f4f | 663 | * Packet reception for 88w8366 AP firmware. |
6f6d1e9a | 664 | */ |
89a91f4f | 665 | struct mwl8k_rxd_8366_ap { |
6f6d1e9a LB |
666 | __le16 pkt_len; |
667 | __u8 sq2; | |
668 | __u8 rate; | |
669 | __le32 pkt_phys_addr; | |
670 | __le32 next_rxd_phys_addr; | |
671 | __le16 qos_control; | |
672 | __le16 htsig2; | |
673 | __le32 hw_rssi_info; | |
674 | __le32 hw_noise_floor_info; | |
675 | __u8 noise_floor; | |
676 | __u8 pad0[3]; | |
677 | __u8 rssi; | |
678 | __u8 rx_status; | |
679 | __u8 channel; | |
680 | __u8 rx_ctrl; | |
681 | } __attribute__((packed)); | |
682 | ||
89a91f4f LB |
683 | #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80 |
684 | #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40 | |
685 | #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) | |
8e9f33f0 | 686 | |
89a91f4f | 687 | #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80 |
6f6d1e9a | 688 | |
89a91f4f | 689 | static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr) |
6f6d1e9a | 690 | { |
89a91f4f | 691 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
692 | |
693 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 694 | rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST; |
6f6d1e9a LB |
695 | } |
696 | ||
89a91f4f | 697 | static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len) |
6f6d1e9a | 698 | { |
89a91f4f | 699 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
700 | |
701 | rxd->pkt_len = cpu_to_le16(len); | |
702 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
703 | wmb(); | |
704 | rxd->rx_ctrl = 0; | |
705 | } | |
706 | ||
707 | static int | |
89a91f4f LB |
708 | mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status, |
709 | __le16 *qos) | |
6f6d1e9a | 710 | { |
89a91f4f | 711 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a | 712 | |
89a91f4f | 713 | if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST)) |
6f6d1e9a LB |
714 | return -1; |
715 | rmb(); | |
716 | ||
717 | memset(status, 0, sizeof(*status)); | |
718 | ||
719 | status->signal = -rxd->rssi; | |
720 | status->noise = -rxd->noise_floor; | |
721 | ||
89a91f4f | 722 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) { |
6f6d1e9a | 723 | status->flag |= RX_FLAG_HT; |
89a91f4f | 724 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ) |
8e9f33f0 | 725 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 726 | status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate); |
6f6d1e9a LB |
727 | } else { |
728 | int i; | |
729 | ||
730 | for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { | |
731 | if (mwl8k_rates[i].hw_value == rxd->rate) { | |
732 | status->rate_idx = i; | |
733 | break; | |
734 | } | |
735 | } | |
736 | } | |
737 | ||
738 | status->band = IEEE80211_BAND_2GHZ; | |
739 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
740 | ||
20f09c3d LB |
741 | *qos = rxd->qos_control; |
742 | ||
6f6d1e9a LB |
743 | return le16_to_cpu(rxd->pkt_len); |
744 | } | |
745 | ||
89a91f4f LB |
746 | static struct rxd_ops rxd_8366_ap_ops = { |
747 | .rxd_size = sizeof(struct mwl8k_rxd_8366_ap), | |
748 | .rxd_init = mwl8k_rxd_8366_ap_init, | |
749 | .rxd_refill = mwl8k_rxd_8366_ap_refill, | |
750 | .rxd_process = mwl8k_rxd_8366_ap_process, | |
6f6d1e9a LB |
751 | }; |
752 | ||
753 | /* | |
89a91f4f | 754 | * Packet reception for STA firmware. |
a66098da | 755 | */ |
89a91f4f | 756 | struct mwl8k_rxd_sta { |
a66098da LB |
757 | __le16 pkt_len; |
758 | __u8 link_quality; | |
759 | __u8 noise_level; | |
760 | __le32 pkt_phys_addr; | |
45eb400d | 761 | __le32 next_rxd_phys_addr; |
a66098da LB |
762 | __le16 qos_control; |
763 | __le16 rate_info; | |
764 | __le32 pad0[4]; | |
765 | __u8 rssi; | |
766 | __u8 channel; | |
767 | __le16 pad1; | |
768 | __u8 rx_ctrl; | |
769 | __u8 rx_status; | |
770 | __u8 pad2[2]; | |
771 | } __attribute__((packed)); | |
772 | ||
89a91f4f LB |
773 | #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 |
774 | #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) | |
775 | #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) | |
776 | #define MWL8K_STA_RATE_INFO_40MHZ 0x0004 | |
777 | #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 | |
778 | #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 | |
54bc3a0d | 779 | |
89a91f4f | 780 | #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 |
54bc3a0d | 781 | |
89a91f4f | 782 | static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) |
54bc3a0d | 783 | { |
89a91f4f | 784 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
785 | |
786 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 787 | rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; |
54bc3a0d LB |
788 | } |
789 | ||
89a91f4f | 790 | static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) |
54bc3a0d | 791 | { |
89a91f4f | 792 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
793 | |
794 | rxd->pkt_len = cpu_to_le16(len); | |
795 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
796 | wmb(); | |
797 | rxd->rx_ctrl = 0; | |
798 | } | |
799 | ||
800 | static int | |
89a91f4f | 801 | mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, |
20f09c3d | 802 | __le16 *qos) |
54bc3a0d | 803 | { |
89a91f4f | 804 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
805 | u16 rate_info; |
806 | ||
89a91f4f | 807 | if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) |
54bc3a0d LB |
808 | return -1; |
809 | rmb(); | |
810 | ||
811 | rate_info = le16_to_cpu(rxd->rate_info); | |
812 | ||
813 | memset(status, 0, sizeof(*status)); | |
814 | ||
815 | status->signal = -rxd->rssi; | |
816 | status->noise = -rxd->noise_level; | |
89a91f4f LB |
817 | status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); |
818 | status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); | |
54bc3a0d | 819 | |
89a91f4f | 820 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) |
54bc3a0d | 821 | status->flag |= RX_FLAG_SHORTPRE; |
89a91f4f | 822 | if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) |
54bc3a0d | 823 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 824 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) |
54bc3a0d | 825 | status->flag |= RX_FLAG_SHORT_GI; |
89a91f4f | 826 | if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) |
54bc3a0d LB |
827 | status->flag |= RX_FLAG_HT; |
828 | ||
829 | status->band = IEEE80211_BAND_2GHZ; | |
830 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
831 | ||
20f09c3d LB |
832 | *qos = rxd->qos_control; |
833 | ||
54bc3a0d LB |
834 | return le16_to_cpu(rxd->pkt_len); |
835 | } | |
836 | ||
89a91f4f LB |
837 | static struct rxd_ops rxd_sta_ops = { |
838 | .rxd_size = sizeof(struct mwl8k_rxd_sta), | |
839 | .rxd_init = mwl8k_rxd_sta_init, | |
840 | .rxd_refill = mwl8k_rxd_sta_refill, | |
841 | .rxd_process = mwl8k_rxd_sta_process, | |
54bc3a0d LB |
842 | }; |
843 | ||
844 | ||
a66098da LB |
845 | #define MWL8K_RX_DESCS 256 |
846 | #define MWL8K_RX_MAXSZ 3800 | |
847 | ||
848 | static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) | |
849 | { | |
850 | struct mwl8k_priv *priv = hw->priv; | |
851 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
852 | int size; | |
853 | int i; | |
854 | ||
45eb400d LB |
855 | rxq->rxd_count = 0; |
856 | rxq->head = 0; | |
857 | rxq->tail = 0; | |
a66098da | 858 | |
54bc3a0d | 859 | size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; |
a66098da | 860 | |
45eb400d LB |
861 | rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); |
862 | if (rxq->rxd == NULL) { | |
a66098da | 863 | printk(KERN_ERR "%s: failed to alloc RX descriptors\n", |
c2c357ce | 864 | wiphy_name(hw->wiphy)); |
a66098da LB |
865 | return -ENOMEM; |
866 | } | |
45eb400d | 867 | memset(rxq->rxd, 0, size); |
a66098da | 868 | |
788838eb LB |
869 | rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); |
870 | if (rxq->buf == NULL) { | |
a66098da | 871 | printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", |
c2c357ce | 872 | wiphy_name(hw->wiphy)); |
45eb400d | 873 | pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); |
a66098da LB |
874 | return -ENOMEM; |
875 | } | |
788838eb | 876 | memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); |
a66098da LB |
877 | |
878 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
54bc3a0d LB |
879 | int desc_size; |
880 | void *rxd; | |
a66098da | 881 | int nexti; |
54bc3a0d LB |
882 | dma_addr_t next_dma_addr; |
883 | ||
884 | desc_size = priv->rxd_ops->rxd_size; | |
885 | rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); | |
a66098da | 886 | |
54bc3a0d LB |
887 | nexti = i + 1; |
888 | if (nexti == MWL8K_RX_DESCS) | |
889 | nexti = 0; | |
890 | next_dma_addr = rxq->rxd_dma + (nexti * desc_size); | |
a66098da | 891 | |
54bc3a0d | 892 | priv->rxd_ops->rxd_init(rxd, next_dma_addr); |
a66098da LB |
893 | } |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) | |
899 | { | |
900 | struct mwl8k_priv *priv = hw->priv; | |
901 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
902 | int refilled; | |
903 | ||
904 | refilled = 0; | |
45eb400d | 905 | while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { |
a66098da | 906 | struct sk_buff *skb; |
788838eb | 907 | dma_addr_t addr; |
a66098da | 908 | int rx; |
54bc3a0d | 909 | void *rxd; |
a66098da LB |
910 | |
911 | skb = dev_alloc_skb(MWL8K_RX_MAXSZ); | |
912 | if (skb == NULL) | |
913 | break; | |
914 | ||
788838eb LB |
915 | addr = pci_map_single(priv->pdev, skb->data, |
916 | MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); | |
a66098da | 917 | |
54bc3a0d LB |
918 | rxq->rxd_count++; |
919 | rx = rxq->tail++; | |
920 | if (rxq->tail == MWL8K_RX_DESCS) | |
921 | rxq->tail = 0; | |
788838eb LB |
922 | rxq->buf[rx].skb = skb; |
923 | pci_unmap_addr_set(&rxq->buf[rx], dma, addr); | |
54bc3a0d LB |
924 | |
925 | rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); | |
926 | priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); | |
a66098da LB |
927 | |
928 | refilled++; | |
929 | } | |
930 | ||
931 | return refilled; | |
932 | } | |
933 | ||
934 | /* Must be called only when the card's reception is completely halted */ | |
935 | static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) | |
936 | { | |
937 | struct mwl8k_priv *priv = hw->priv; | |
938 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
939 | int i; | |
940 | ||
941 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
788838eb LB |
942 | if (rxq->buf[i].skb != NULL) { |
943 | pci_unmap_single(priv->pdev, | |
944 | pci_unmap_addr(&rxq->buf[i], dma), | |
945 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
946 | pci_unmap_addr_set(&rxq->buf[i], dma, 0); | |
947 | ||
948 | kfree_skb(rxq->buf[i].skb); | |
949 | rxq->buf[i].skb = NULL; | |
a66098da LB |
950 | } |
951 | } | |
952 | ||
788838eb LB |
953 | kfree(rxq->buf); |
954 | rxq->buf = NULL; | |
a66098da LB |
955 | |
956 | pci_free_consistent(priv->pdev, | |
54bc3a0d | 957 | MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, |
45eb400d LB |
958 | rxq->rxd, rxq->rxd_dma); |
959 | rxq->rxd = NULL; | |
a66098da LB |
960 | } |
961 | ||
962 | ||
963 | /* | |
964 | * Scan a list of BSSIDs to process for finalize join. | |
965 | * Allows for extension to process multiple BSSIDs. | |
966 | */ | |
967 | static inline int | |
968 | mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) | |
969 | { | |
970 | return priv->capture_beacon && | |
971 | ieee80211_is_beacon(wh->frame_control) && | |
972 | !compare_ether_addr(wh->addr3, priv->capture_bssid); | |
973 | } | |
974 | ||
3779752d LB |
975 | static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, |
976 | struct sk_buff *skb) | |
a66098da | 977 | { |
3779752d LB |
978 | struct mwl8k_priv *priv = hw->priv; |
979 | ||
a66098da | 980 | priv->capture_beacon = false; |
d89173f2 | 981 | memset(priv->capture_bssid, 0, ETH_ALEN); |
a66098da LB |
982 | |
983 | /* | |
984 | * Use GFP_ATOMIC as rxq_process is called from | |
985 | * the primary interrupt handler, memory allocation call | |
986 | * must not sleep. | |
987 | */ | |
988 | priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); | |
989 | if (priv->beacon_skb != NULL) | |
3779752d | 990 | ieee80211_queue_work(hw, &priv->finalize_join_worker); |
a66098da LB |
991 | } |
992 | ||
993 | static int rxq_process(struct ieee80211_hw *hw, int index, int limit) | |
994 | { | |
995 | struct mwl8k_priv *priv = hw->priv; | |
996 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
997 | int processed; | |
998 | ||
999 | processed = 0; | |
45eb400d | 1000 | while (rxq->rxd_count && limit--) { |
a66098da | 1001 | struct sk_buff *skb; |
54bc3a0d LB |
1002 | void *rxd; |
1003 | int pkt_len; | |
a66098da | 1004 | struct ieee80211_rx_status status; |
20f09c3d | 1005 | __le16 qos; |
a66098da | 1006 | |
788838eb | 1007 | skb = rxq->buf[rxq->head].skb; |
d25f9f13 LB |
1008 | if (skb == NULL) |
1009 | break; | |
54bc3a0d LB |
1010 | |
1011 | rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); | |
1012 | ||
20f09c3d | 1013 | pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos); |
54bc3a0d LB |
1014 | if (pkt_len < 0) |
1015 | break; | |
1016 | ||
788838eb LB |
1017 | rxq->buf[rxq->head].skb = NULL; |
1018 | ||
1019 | pci_unmap_single(priv->pdev, | |
1020 | pci_unmap_addr(&rxq->buf[rxq->head], dma), | |
1021 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1022 | pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); | |
a66098da | 1023 | |
54bc3a0d LB |
1024 | rxq->head++; |
1025 | if (rxq->head == MWL8K_RX_DESCS) | |
1026 | rxq->head = 0; | |
1027 | ||
45eb400d | 1028 | rxq->rxd_count--; |
a66098da | 1029 | |
54bc3a0d | 1030 | skb_put(skb, pkt_len); |
20f09c3d | 1031 | mwl8k_remove_dma_header(skb, qos); |
a66098da | 1032 | |
a66098da | 1033 | /* |
c2c357ce LB |
1034 | * Check for a pending join operation. Save a |
1035 | * copy of the beacon and schedule a tasklet to | |
1036 | * send a FINALIZE_JOIN command to the firmware. | |
a66098da | 1037 | */ |
54bc3a0d | 1038 | if (mwl8k_capture_bssid(priv, (void *)skb->data)) |
3779752d | 1039 | mwl8k_save_beacon(hw, skb); |
a66098da | 1040 | |
f1d58c25 JB |
1041 | memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); |
1042 | ieee80211_rx_irqsafe(hw, skb); | |
a66098da LB |
1043 | |
1044 | processed++; | |
1045 | } | |
1046 | ||
1047 | return processed; | |
1048 | } | |
1049 | ||
1050 | ||
1051 | /* | |
1052 | * Packet transmission. | |
1053 | */ | |
1054 | ||
a66098da LB |
1055 | #define MWL8K_TXD_STATUS_OK 0x00000001 |
1056 | #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 | |
1057 | #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 | |
1058 | #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 | |
a66098da | 1059 | #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 |
a66098da | 1060 | |
e0493a8d LB |
1061 | #define MWL8K_QOS_QLEN_UNSPEC 0xff00 |
1062 | #define MWL8K_QOS_ACK_POLICY_MASK 0x0060 | |
1063 | #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 | |
1064 | #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 | |
1065 | #define MWL8K_QOS_EOSP 0x0010 | |
1066 | ||
a66098da LB |
1067 | struct mwl8k_tx_desc { |
1068 | __le32 status; | |
1069 | __u8 data_rate; | |
1070 | __u8 tx_priority; | |
1071 | __le16 qos_control; | |
1072 | __le32 pkt_phys_addr; | |
1073 | __le16 pkt_len; | |
d89173f2 | 1074 | __u8 dest_MAC_addr[ETH_ALEN]; |
45eb400d | 1075 | __le32 next_txd_phys_addr; |
a66098da LB |
1076 | __le32 reserved; |
1077 | __le16 rate_info; | |
1078 | __u8 peer_id; | |
1079 | __u8 tx_frag_cnt; | |
1080 | } __attribute__((packed)); | |
1081 | ||
1082 | #define MWL8K_TX_DESCS 128 | |
1083 | ||
1084 | static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) | |
1085 | { | |
1086 | struct mwl8k_priv *priv = hw->priv; | |
1087 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1088 | int size; | |
1089 | int i; | |
1090 | ||
45eb400d LB |
1091 | memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); |
1092 | txq->stats.limit = MWL8K_TX_DESCS; | |
1093 | txq->head = 0; | |
1094 | txq->tail = 0; | |
a66098da LB |
1095 | |
1096 | size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); | |
1097 | ||
45eb400d LB |
1098 | txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); |
1099 | if (txq->txd == NULL) { | |
a66098da | 1100 | printk(KERN_ERR "%s: failed to alloc TX descriptors\n", |
c2c357ce | 1101 | wiphy_name(hw->wiphy)); |
a66098da LB |
1102 | return -ENOMEM; |
1103 | } | |
45eb400d | 1104 | memset(txq->txd, 0, size); |
a66098da | 1105 | |
45eb400d LB |
1106 | txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); |
1107 | if (txq->skb == NULL) { | |
a66098da | 1108 | printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", |
c2c357ce | 1109 | wiphy_name(hw->wiphy)); |
45eb400d | 1110 | pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); |
a66098da LB |
1111 | return -ENOMEM; |
1112 | } | |
45eb400d | 1113 | memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); |
a66098da LB |
1114 | |
1115 | for (i = 0; i < MWL8K_TX_DESCS; i++) { | |
1116 | struct mwl8k_tx_desc *tx_desc; | |
1117 | int nexti; | |
1118 | ||
45eb400d | 1119 | tx_desc = txq->txd + i; |
a66098da LB |
1120 | nexti = (i + 1) % MWL8K_TX_DESCS; |
1121 | ||
1122 | tx_desc->status = 0; | |
45eb400d LB |
1123 | tx_desc->next_txd_phys_addr = |
1124 | cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); | |
a66098da LB |
1125 | } |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static inline void mwl8k_tx_start(struct mwl8k_priv *priv) | |
1131 | { | |
1132 | iowrite32(MWL8K_H2A_INT_PPA_READY, | |
1133 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1134 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1135 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1136 | ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
1137 | } | |
1138 | ||
7e1112d3 | 1139 | static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) |
a66098da | 1140 | { |
7e1112d3 LB |
1141 | struct mwl8k_priv *priv = hw->priv; |
1142 | int i; | |
1143 | ||
1144 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { | |
1145 | struct mwl8k_tx_queue *txq = priv->txq + i; | |
1146 | int fw_owned = 0; | |
1147 | int drv_owned = 0; | |
1148 | int unused = 0; | |
1149 | int desc; | |
1150 | ||
a66098da | 1151 | for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { |
7e1112d3 LB |
1152 | struct mwl8k_tx_desc *tx_desc = txq->txd + desc; |
1153 | u32 status; | |
a66098da | 1154 | |
7e1112d3 | 1155 | status = le32_to_cpu(tx_desc->status); |
a66098da | 1156 | if (status & MWL8K_TXD_STATUS_FW_OWNED) |
7e1112d3 | 1157 | fw_owned++; |
a66098da | 1158 | else |
7e1112d3 | 1159 | drv_owned++; |
a66098da LB |
1160 | |
1161 | if (tx_desc->pkt_len == 0) | |
7e1112d3 | 1162 | unused++; |
a66098da | 1163 | } |
a66098da | 1164 | |
7e1112d3 LB |
1165 | printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d " |
1166 | "fw_owned=%d drv_owned=%d unused=%d\n", | |
1167 | wiphy_name(hw->wiphy), i, | |
1168 | txq->stats.len, txq->head, txq->tail, | |
1169 | fw_owned, drv_owned, unused); | |
1170 | } | |
a66098da LB |
1171 | } |
1172 | ||
618952a7 | 1173 | /* |
88de754a | 1174 | * Must be called with priv->fw_mutex held and tx queues stopped. |
618952a7 | 1175 | */ |
62abd3cf | 1176 | #define MWL8K_TX_WAIT_TIMEOUT_MS 5000 |
7e1112d3 | 1177 | |
950d5b01 | 1178 | static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) |
a66098da | 1179 | { |
a66098da | 1180 | struct mwl8k_priv *priv = hw->priv; |
88de754a | 1181 | DECLARE_COMPLETION_ONSTACK(tx_wait); |
7e1112d3 LB |
1182 | int retry; |
1183 | int rc; | |
a66098da LB |
1184 | |
1185 | might_sleep(); | |
1186 | ||
7e1112d3 LB |
1187 | /* |
1188 | * The TX queues are stopped at this point, so this test | |
1189 | * doesn't need to take ->tx_lock. | |
1190 | */ | |
1191 | if (!priv->pending_tx_pkts) | |
1192 | return 0; | |
1193 | ||
1194 | retry = 0; | |
1195 | rc = 0; | |
1196 | ||
a66098da | 1197 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1198 | priv->tx_wait = &tx_wait; |
1199 | while (!rc) { | |
1200 | int oldcount; | |
1201 | unsigned long timeout; | |
a66098da | 1202 | |
7e1112d3 | 1203 | oldcount = priv->pending_tx_pkts; |
a66098da | 1204 | |
7e1112d3 | 1205 | spin_unlock_bh(&priv->tx_lock); |
88de754a | 1206 | timeout = wait_for_completion_timeout(&tx_wait, |
7e1112d3 | 1207 | msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); |
a66098da | 1208 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1209 | |
1210 | if (timeout) { | |
1211 | WARN_ON(priv->pending_tx_pkts); | |
1212 | if (retry) { | |
1213 | printk(KERN_NOTICE "%s: tx rings drained\n", | |
1214 | wiphy_name(hw->wiphy)); | |
1215 | } | |
1216 | break; | |
1217 | } | |
1218 | ||
1219 | if (priv->pending_tx_pkts < oldcount) { | |
9a2303b9 LB |
1220 | printk(KERN_NOTICE "%s: waiting for tx rings " |
1221 | "to drain (%d -> %d pkts)\n", | |
7e1112d3 LB |
1222 | wiphy_name(hw->wiphy), oldcount, |
1223 | priv->pending_tx_pkts); | |
1224 | retry = 1; | |
1225 | continue; | |
1226 | } | |
1227 | ||
a66098da | 1228 | priv->tx_wait = NULL; |
a66098da | 1229 | |
7e1112d3 LB |
1230 | printk(KERN_ERR "%s: tx rings stuck for %d ms\n", |
1231 | wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS); | |
1232 | mwl8k_dump_tx_rings(hw); | |
1233 | ||
1234 | rc = -ETIMEDOUT; | |
a66098da | 1235 | } |
7e1112d3 | 1236 | spin_unlock_bh(&priv->tx_lock); |
a66098da | 1237 | |
7e1112d3 | 1238 | return rc; |
a66098da LB |
1239 | } |
1240 | ||
c23b5a69 LB |
1241 | #define MWL8K_TXD_SUCCESS(status) \ |
1242 | ((status) & (MWL8K_TXD_STATUS_OK | \ | |
1243 | MWL8K_TXD_STATUS_OK_RETRY | \ | |
1244 | MWL8K_TXD_STATUS_OK_MORE_RETRY)) | |
a66098da LB |
1245 | |
1246 | static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) | |
1247 | { | |
1248 | struct mwl8k_priv *priv = hw->priv; | |
1249 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1250 | int wake = 0; | |
1251 | ||
45eb400d | 1252 | while (txq->stats.len > 0) { |
a66098da | 1253 | int tx; |
a66098da LB |
1254 | struct mwl8k_tx_desc *tx_desc; |
1255 | unsigned long addr; | |
ce9e2e1b | 1256 | int size; |
a66098da LB |
1257 | struct sk_buff *skb; |
1258 | struct ieee80211_tx_info *info; | |
1259 | u32 status; | |
1260 | ||
45eb400d LB |
1261 | tx = txq->head; |
1262 | tx_desc = txq->txd + tx; | |
a66098da LB |
1263 | |
1264 | status = le32_to_cpu(tx_desc->status); | |
1265 | ||
1266 | if (status & MWL8K_TXD_STATUS_FW_OWNED) { | |
1267 | if (!force) | |
1268 | break; | |
1269 | tx_desc->status &= | |
1270 | ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); | |
1271 | } | |
1272 | ||
45eb400d LB |
1273 | txq->head = (tx + 1) % MWL8K_TX_DESCS; |
1274 | BUG_ON(txq->stats.len == 0); | |
1275 | txq->stats.len--; | |
a66098da LB |
1276 | priv->pending_tx_pkts--; |
1277 | ||
1278 | addr = le32_to_cpu(tx_desc->pkt_phys_addr); | |
ce9e2e1b | 1279 | size = le16_to_cpu(tx_desc->pkt_len); |
45eb400d LB |
1280 | skb = txq->skb[tx]; |
1281 | txq->skb[tx] = NULL; | |
a66098da LB |
1282 | |
1283 | BUG_ON(skb == NULL); | |
1284 | pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); | |
1285 | ||
20f09c3d | 1286 | mwl8k_remove_dma_header(skb, tx_desc->qos_control); |
a66098da LB |
1287 | |
1288 | /* Mark descriptor as unused */ | |
1289 | tx_desc->pkt_phys_addr = 0; | |
1290 | tx_desc->pkt_len = 0; | |
1291 | ||
a66098da LB |
1292 | info = IEEE80211_SKB_CB(skb); |
1293 | ieee80211_tx_info_clear_status(info); | |
ce9e2e1b | 1294 | if (MWL8K_TXD_SUCCESS(status)) |
a66098da | 1295 | info->flags |= IEEE80211_TX_STAT_ACK; |
a66098da LB |
1296 | |
1297 | ieee80211_tx_status_irqsafe(hw, skb); | |
1298 | ||
618952a7 | 1299 | wake = 1; |
a66098da LB |
1300 | } |
1301 | ||
618952a7 | 1302 | if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) |
a66098da LB |
1303 | ieee80211_wake_queue(hw, index); |
1304 | } | |
1305 | ||
1306 | /* must be called only when the card's transmit is completely halted */ | |
1307 | static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) | |
1308 | { | |
1309 | struct mwl8k_priv *priv = hw->priv; | |
1310 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1311 | ||
1312 | mwl8k_txq_reclaim(hw, index, 1); | |
1313 | ||
45eb400d LB |
1314 | kfree(txq->skb); |
1315 | txq->skb = NULL; | |
a66098da LB |
1316 | |
1317 | pci_free_consistent(priv->pdev, | |
1318 | MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), | |
45eb400d LB |
1319 | txq->txd, txq->txd_dma); |
1320 | txq->txd = NULL; | |
a66098da LB |
1321 | } |
1322 | ||
1323 | static int | |
1324 | mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) | |
1325 | { | |
1326 | struct mwl8k_priv *priv = hw->priv; | |
1327 | struct ieee80211_tx_info *tx_info; | |
23b33906 | 1328 | struct mwl8k_vif *mwl8k_vif; |
a66098da LB |
1329 | struct ieee80211_hdr *wh; |
1330 | struct mwl8k_tx_queue *txq; | |
1331 | struct mwl8k_tx_desc *tx; | |
a66098da | 1332 | dma_addr_t dma; |
23b33906 LB |
1333 | u32 txstatus; |
1334 | u8 txdatarate; | |
1335 | u16 qos; | |
a66098da | 1336 | |
23b33906 LB |
1337 | wh = (struct ieee80211_hdr *)skb->data; |
1338 | if (ieee80211_is_data_qos(wh->frame_control)) | |
1339 | qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); | |
1340 | else | |
1341 | qos = 0; | |
a66098da | 1342 | |
76266b2a | 1343 | mwl8k_add_dma_header(skb); |
23b33906 | 1344 | wh = &((struct mwl8k_dma_data *)skb->data)->wh; |
a66098da LB |
1345 | |
1346 | tx_info = IEEE80211_SKB_CB(skb); | |
1347 | mwl8k_vif = MWL8K_VIF(tx_info->control.vif); | |
a66098da LB |
1348 | |
1349 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
1350 | u16 seqno = mwl8k_vif->seqno; | |
23b33906 | 1351 | |
a66098da LB |
1352 | wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
1353 | wh->seq_ctrl |= cpu_to_le16(seqno << 4); | |
1354 | mwl8k_vif->seqno = seqno++ % 4096; | |
1355 | } | |
1356 | ||
23b33906 LB |
1357 | /* Setup firmware control bit fields for each frame type. */ |
1358 | txstatus = 0; | |
1359 | txdatarate = 0; | |
1360 | if (ieee80211_is_mgmt(wh->frame_control) || | |
1361 | ieee80211_is_ctl(wh->frame_control)) { | |
1362 | txdatarate = 0; | |
e0493a8d | 1363 | qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; |
23b33906 LB |
1364 | } else if (ieee80211_is_data(wh->frame_control)) { |
1365 | txdatarate = 1; | |
1366 | if (is_multicast_ether_addr(wh->addr1)) | |
1367 | txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; | |
1368 | ||
e0493a8d | 1369 | qos &= ~MWL8K_QOS_ACK_POLICY_MASK; |
23b33906 | 1370 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) |
e0493a8d | 1371 | qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; |
23b33906 | 1372 | else |
e0493a8d | 1373 | qos |= MWL8K_QOS_ACK_POLICY_NORMAL; |
23b33906 | 1374 | } |
a66098da LB |
1375 | |
1376 | dma = pci_map_single(priv->pdev, skb->data, | |
1377 | skb->len, PCI_DMA_TODEVICE); | |
1378 | ||
1379 | if (pci_dma_mapping_error(priv->pdev, dma)) { | |
1380 | printk(KERN_DEBUG "%s: failed to dma map skb, " | |
c2c357ce | 1381 | "dropping TX frame.\n", wiphy_name(hw->wiphy)); |
23b33906 | 1382 | dev_kfree_skb(skb); |
a66098da LB |
1383 | return NETDEV_TX_OK; |
1384 | } | |
1385 | ||
23b33906 | 1386 | spin_lock_bh(&priv->tx_lock); |
a66098da | 1387 | |
23b33906 | 1388 | txq = priv->txq + index; |
a66098da | 1389 | |
45eb400d LB |
1390 | BUG_ON(txq->skb[txq->tail] != NULL); |
1391 | txq->skb[txq->tail] = skb; | |
a66098da | 1392 | |
45eb400d | 1393 | tx = txq->txd + txq->tail; |
23b33906 LB |
1394 | tx->data_rate = txdatarate; |
1395 | tx->tx_priority = index; | |
a66098da | 1396 | tx->qos_control = cpu_to_le16(qos); |
a66098da LB |
1397 | tx->pkt_phys_addr = cpu_to_le32(dma); |
1398 | tx->pkt_len = cpu_to_le16(skb->len); | |
23b33906 | 1399 | tx->rate_info = 0; |
a680400e LB |
1400 | if (!priv->ap_fw && tx_info->control.sta != NULL) |
1401 | tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id; | |
1402 | else | |
1403 | tx->peer_id = 0; | |
a66098da | 1404 | wmb(); |
23b33906 LB |
1405 | tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); |
1406 | ||
45eb400d LB |
1407 | txq->stats.count++; |
1408 | txq->stats.len++; | |
a66098da | 1409 | priv->pending_tx_pkts++; |
a66098da | 1410 | |
45eb400d LB |
1411 | txq->tail++; |
1412 | if (txq->tail == MWL8K_TX_DESCS) | |
1413 | txq->tail = 0; | |
23b33906 | 1414 | |
45eb400d | 1415 | if (txq->head == txq->tail) |
a66098da LB |
1416 | ieee80211_stop_queue(hw, index); |
1417 | ||
23b33906 | 1418 | mwl8k_tx_start(priv); |
a66098da LB |
1419 | |
1420 | spin_unlock_bh(&priv->tx_lock); | |
1421 | ||
1422 | return NETDEV_TX_OK; | |
1423 | } | |
1424 | ||
1425 | ||
618952a7 LB |
1426 | /* |
1427 | * Firmware access. | |
1428 | * | |
1429 | * We have the following requirements for issuing firmware commands: | |
1430 | * - Some commands require that the packet transmit path is idle when | |
1431 | * the command is issued. (For simplicity, we'll just quiesce the | |
1432 | * transmit path for every command.) | |
1433 | * - There are certain sequences of commands that need to be issued to | |
1434 | * the hardware sequentially, with no other intervening commands. | |
1435 | * | |
1436 | * This leads to an implementation of a "firmware lock" as a mutex that | |
1437 | * can be taken recursively, and which is taken by both the low-level | |
1438 | * command submission function (mwl8k_post_cmd) as well as any users of | |
1439 | * that function that require issuing of an atomic sequence of commands, | |
1440 | * and quiesces the transmit path whenever it's taken. | |
1441 | */ | |
1442 | static int mwl8k_fw_lock(struct ieee80211_hw *hw) | |
1443 | { | |
1444 | struct mwl8k_priv *priv = hw->priv; | |
1445 | ||
1446 | if (priv->fw_mutex_owner != current) { | |
1447 | int rc; | |
1448 | ||
1449 | mutex_lock(&priv->fw_mutex); | |
1450 | ieee80211_stop_queues(hw); | |
1451 | ||
1452 | rc = mwl8k_tx_wait_empty(hw); | |
1453 | if (rc) { | |
1454 | ieee80211_wake_queues(hw); | |
1455 | mutex_unlock(&priv->fw_mutex); | |
1456 | ||
1457 | return rc; | |
1458 | } | |
1459 | ||
1460 | priv->fw_mutex_owner = current; | |
1461 | } | |
1462 | ||
1463 | priv->fw_mutex_depth++; | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | static void mwl8k_fw_unlock(struct ieee80211_hw *hw) | |
1469 | { | |
1470 | struct mwl8k_priv *priv = hw->priv; | |
1471 | ||
1472 | if (!--priv->fw_mutex_depth) { | |
1473 | ieee80211_wake_queues(hw); | |
1474 | priv->fw_mutex_owner = NULL; | |
1475 | mutex_unlock(&priv->fw_mutex); | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | ||
a66098da LB |
1480 | /* |
1481 | * Command processing. | |
1482 | */ | |
1483 | ||
0c9cc640 LB |
1484 | /* Timeout firmware commands after 10s */ |
1485 | #define MWL8K_CMD_TIMEOUT_MS 10000 | |
a66098da LB |
1486 | |
1487 | static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) | |
1488 | { | |
1489 | DECLARE_COMPLETION_ONSTACK(cmd_wait); | |
1490 | struct mwl8k_priv *priv = hw->priv; | |
1491 | void __iomem *regs = priv->regs; | |
1492 | dma_addr_t dma_addr; | |
1493 | unsigned int dma_size; | |
1494 | int rc; | |
a66098da LB |
1495 | unsigned long timeout = 0; |
1496 | u8 buf[32]; | |
1497 | ||
c2c357ce | 1498 | cmd->result = 0xffff; |
a66098da LB |
1499 | dma_size = le16_to_cpu(cmd->length); |
1500 | dma_addr = pci_map_single(priv->pdev, cmd, dma_size, | |
1501 | PCI_DMA_BIDIRECTIONAL); | |
1502 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
1503 | return -ENOMEM; | |
1504 | ||
618952a7 | 1505 | rc = mwl8k_fw_lock(hw); |
39a1e42e LB |
1506 | if (rc) { |
1507 | pci_unmap_single(priv->pdev, dma_addr, dma_size, | |
1508 | PCI_DMA_BIDIRECTIONAL); | |
618952a7 | 1509 | return rc; |
39a1e42e | 1510 | } |
a66098da | 1511 | |
a66098da LB |
1512 | priv->hostcmd_wait = &cmd_wait; |
1513 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
1514 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
1515 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1516 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1517 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
a66098da LB |
1518 | |
1519 | timeout = wait_for_completion_timeout(&cmd_wait, | |
1520 | msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); | |
1521 | ||
618952a7 LB |
1522 | priv->hostcmd_wait = NULL; |
1523 | ||
1524 | mwl8k_fw_unlock(hw); | |
1525 | ||
37055bd4 LB |
1526 | pci_unmap_single(priv->pdev, dma_addr, dma_size, |
1527 | PCI_DMA_BIDIRECTIONAL); | |
1528 | ||
a66098da | 1529 | if (!timeout) { |
a66098da | 1530 | printk(KERN_ERR "%s: Command %s timeout after %u ms\n", |
c2c357ce | 1531 | wiphy_name(hw->wiphy), |
a66098da LB |
1532 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
1533 | MWL8K_CMD_TIMEOUT_MS); | |
1534 | rc = -ETIMEDOUT; | |
1535 | } else { | |
0c9cc640 LB |
1536 | int ms; |
1537 | ||
1538 | ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout); | |
1539 | ||
ce9e2e1b | 1540 | rc = cmd->result ? -EINVAL : 0; |
a66098da LB |
1541 | if (rc) |
1542 | printk(KERN_ERR "%s: Command %s error 0x%x\n", | |
c2c357ce | 1543 | wiphy_name(hw->wiphy), |
a66098da | 1544 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
76c962a2 | 1545 | le16_to_cpu(cmd->result)); |
0c9cc640 LB |
1546 | else if (ms > 2000) |
1547 | printk(KERN_NOTICE "%s: Command %s took %d ms\n", | |
1548 | wiphy_name(hw->wiphy), | |
1549 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), | |
1550 | ms); | |
a66098da LB |
1551 | } |
1552 | ||
a66098da LB |
1553 | return rc; |
1554 | } | |
1555 | ||
1556 | /* | |
04b147b1 | 1557 | * CMD_GET_HW_SPEC (STA version). |
a66098da | 1558 | */ |
04b147b1 | 1559 | struct mwl8k_cmd_get_hw_spec_sta { |
a66098da LB |
1560 | struct mwl8k_cmd_pkt header; |
1561 | __u8 hw_rev; | |
1562 | __u8 host_interface; | |
1563 | __le16 num_mcaddrs; | |
d89173f2 | 1564 | __u8 perm_addr[ETH_ALEN]; |
a66098da LB |
1565 | __le16 region_code; |
1566 | __le32 fw_rev; | |
1567 | __le32 ps_cookie; | |
1568 | __le32 caps; | |
1569 | __u8 mcs_bitmap[16]; | |
1570 | __le32 rx_queue_ptr; | |
1571 | __le32 num_tx_queues; | |
1572 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1573 | __le32 caps2; | |
1574 | __le32 num_tx_desc_per_queue; | |
45eb400d | 1575 | __le32 total_rxd; |
a66098da LB |
1576 | } __attribute__((packed)); |
1577 | ||
341c9791 LB |
1578 | #define MWL8K_CAP_MAX_AMSDU 0x20000000 |
1579 | #define MWL8K_CAP_GREENFIELD 0x08000000 | |
1580 | #define MWL8K_CAP_AMPDU 0x04000000 | |
1581 | #define MWL8K_CAP_RX_STBC 0x01000000 | |
1582 | #define MWL8K_CAP_TX_STBC 0x00800000 | |
1583 | #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000 | |
1584 | #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000 | |
1585 | #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000 | |
1586 | #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000 | |
1587 | #define MWL8K_CAP_DELAY_BA 0x00003000 | |
1588 | #define MWL8K_CAP_MIMO 0x00000200 | |
1589 | #define MWL8K_CAP_40MHZ 0x00000100 | |
1590 | ||
1591 | static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap) | |
1592 | { | |
1593 | struct mwl8k_priv *priv = hw->priv; | |
1594 | int rx_streams; | |
1595 | int tx_streams; | |
1596 | ||
1597 | priv->band.ht_cap.ht_supported = 1; | |
1598 | ||
1599 | if (cap & MWL8K_CAP_MAX_AMSDU) | |
1600 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU; | |
1601 | if (cap & MWL8K_CAP_GREENFIELD) | |
1602 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD; | |
1603 | if (cap & MWL8K_CAP_AMPDU) { | |
1604 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
1605 | priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; | |
1606 | priv->band.ht_cap.ampdu_density = | |
1607 | IEEE80211_HT_MPDU_DENSITY_NONE; | |
1608 | } | |
1609 | if (cap & MWL8K_CAP_RX_STBC) | |
1610 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC; | |
1611 | if (cap & MWL8K_CAP_TX_STBC) | |
1612 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC; | |
1613 | if (cap & MWL8K_CAP_SHORTGI_40MHZ) | |
1614 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; | |
1615 | if (cap & MWL8K_CAP_SHORTGI_20MHZ) | |
1616 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20; | |
1617 | if (cap & MWL8K_CAP_DELAY_BA) | |
1618 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA; | |
1619 | if (cap & MWL8K_CAP_40MHZ) | |
1620 | priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; | |
1621 | ||
1622 | rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK); | |
1623 | tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK); | |
1624 | ||
1625 | priv->band.ht_cap.mcs.rx_mask[0] = 0xff; | |
1626 | if (rx_streams >= 2) | |
1627 | priv->band.ht_cap.mcs.rx_mask[1] = 0xff; | |
1628 | if (rx_streams >= 3) | |
1629 | priv->band.ht_cap.mcs.rx_mask[2] = 0xff; | |
1630 | priv->band.ht_cap.mcs.rx_mask[4] = 0x01; | |
1631 | priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
1632 | ||
1633 | if (rx_streams != tx_streams) { | |
1634 | priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
1635 | priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) << | |
1636 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; | |
1637 | } | |
1638 | } | |
1639 | ||
04b147b1 | 1640 | static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) |
a66098da LB |
1641 | { |
1642 | struct mwl8k_priv *priv = hw->priv; | |
04b147b1 | 1643 | struct mwl8k_cmd_get_hw_spec_sta *cmd; |
a66098da LB |
1644 | int rc; |
1645 | int i; | |
1646 | ||
1647 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1648 | if (cmd == NULL) | |
1649 | return -ENOMEM; | |
1650 | ||
1651 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1652 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1653 | ||
1654 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1655 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
45eb400d | 1656 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); |
4ff6432e | 1657 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); |
a66098da | 1658 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
45eb400d | 1659 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); |
4ff6432e | 1660 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
45eb400d | 1661 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); |
a66098da LB |
1662 | |
1663 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1664 | ||
1665 | if (!rc) { | |
1666 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1667 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
4ff6432e | 1668 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); |
a66098da | 1669 | priv->hw_rev = cmd->hw_rev; |
341c9791 LB |
1670 | if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO)) |
1671 | mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps)); | |
a66098da LB |
1672 | } |
1673 | ||
1674 | kfree(cmd); | |
1675 | return rc; | |
1676 | } | |
1677 | ||
42fba21d LB |
1678 | /* |
1679 | * CMD_GET_HW_SPEC (AP version). | |
1680 | */ | |
1681 | struct mwl8k_cmd_get_hw_spec_ap { | |
1682 | struct mwl8k_cmd_pkt header; | |
1683 | __u8 hw_rev; | |
1684 | __u8 host_interface; | |
1685 | __le16 num_wcb; | |
1686 | __le16 num_mcaddrs; | |
1687 | __u8 perm_addr[ETH_ALEN]; | |
1688 | __le16 region_code; | |
1689 | __le16 num_antenna; | |
1690 | __le32 fw_rev; | |
1691 | __le32 wcbbase0; | |
1692 | __le32 rxwrptr; | |
1693 | __le32 rxrdptr; | |
1694 | __le32 ps_cookie; | |
1695 | __le32 wcbbase1; | |
1696 | __le32 wcbbase2; | |
1697 | __le32 wcbbase3; | |
1698 | } __attribute__((packed)); | |
1699 | ||
1700 | static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) | |
1701 | { | |
1702 | struct mwl8k_priv *priv = hw->priv; | |
1703 | struct mwl8k_cmd_get_hw_spec_ap *cmd; | |
1704 | int rc; | |
1705 | ||
1706 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1707 | if (cmd == NULL) | |
1708 | return -ENOMEM; | |
1709 | ||
1710 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1711 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1712 | ||
1713 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1714 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1715 | ||
1716 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1717 | ||
1718 | if (!rc) { | |
1719 | int off; | |
1720 | ||
1721 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1722 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
1723 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); | |
1724 | priv->hw_rev = cmd->hw_rev; | |
1725 | ||
1726 | off = le32_to_cpu(cmd->wcbbase0) & 0xffff; | |
1727 | iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); | |
1728 | ||
1729 | off = le32_to_cpu(cmd->rxwrptr) & 0xffff; | |
1730 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1731 | ||
1732 | off = le32_to_cpu(cmd->rxrdptr) & 0xffff; | |
1733 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1734 | ||
1735 | off = le32_to_cpu(cmd->wcbbase1) & 0xffff; | |
1736 | iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); | |
1737 | ||
1738 | off = le32_to_cpu(cmd->wcbbase2) & 0xffff; | |
1739 | iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); | |
1740 | ||
1741 | off = le32_to_cpu(cmd->wcbbase3) & 0xffff; | |
1742 | iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); | |
1743 | } | |
1744 | ||
1745 | kfree(cmd); | |
1746 | return rc; | |
1747 | } | |
1748 | ||
1749 | /* | |
1750 | * CMD_SET_HW_SPEC. | |
1751 | */ | |
1752 | struct mwl8k_cmd_set_hw_spec { | |
1753 | struct mwl8k_cmd_pkt header; | |
1754 | __u8 hw_rev; | |
1755 | __u8 host_interface; | |
1756 | __le16 num_mcaddrs; | |
1757 | __u8 perm_addr[ETH_ALEN]; | |
1758 | __le16 region_code; | |
1759 | __le32 fw_rev; | |
1760 | __le32 ps_cookie; | |
1761 | __le32 caps; | |
1762 | __le32 rx_queue_ptr; | |
1763 | __le32 num_tx_queues; | |
1764 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1765 | __le32 flags; | |
1766 | __le32 num_tx_desc_per_queue; | |
1767 | __le32 total_rxd; | |
1768 | } __attribute__((packed)); | |
1769 | ||
1770 | #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 | |
1771 | ||
1772 | static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) | |
1773 | { | |
1774 | struct mwl8k_priv *priv = hw->priv; | |
1775 | struct mwl8k_cmd_set_hw_spec *cmd; | |
1776 | int rc; | |
1777 | int i; | |
1778 | ||
1779 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1780 | if (cmd == NULL) | |
1781 | return -ENOMEM; | |
1782 | ||
1783 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); | |
1784 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1785 | ||
1786 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1787 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); | |
1788 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); | |
1789 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
1790 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); | |
1791 | cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); | |
1792 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); | |
1793 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); | |
1794 | ||
1795 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1796 | kfree(cmd); | |
1797 | ||
1798 | return rc; | |
1799 | } | |
1800 | ||
a66098da LB |
1801 | /* |
1802 | * CMD_MAC_MULTICAST_ADR. | |
1803 | */ | |
1804 | struct mwl8k_cmd_mac_multicast_adr { | |
1805 | struct mwl8k_cmd_pkt header; | |
1806 | __le16 action; | |
1807 | __le16 numaddr; | |
ce9e2e1b | 1808 | __u8 addr[0][ETH_ALEN]; |
a66098da LB |
1809 | }; |
1810 | ||
d5e30845 LB |
1811 | #define MWL8K_ENABLE_RX_DIRECTED 0x0001 |
1812 | #define MWL8K_ENABLE_RX_MULTICAST 0x0002 | |
1813 | #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 | |
1814 | #define MWL8K_ENABLE_RX_BROADCAST 0x0008 | |
ce9e2e1b | 1815 | |
e81cd2d6 | 1816 | static struct mwl8k_cmd_pkt * |
447ced07 | 1817 | __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, |
e81cd2d6 | 1818 | int mc_count, struct dev_addr_list *mclist) |
a66098da | 1819 | { |
e81cd2d6 | 1820 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1821 | struct mwl8k_cmd_mac_multicast_adr *cmd; |
e81cd2d6 | 1822 | int size; |
e81cd2d6 | 1823 | |
447ced07 | 1824 | if (allmulti || mc_count > priv->num_mcaddrs) { |
d5e30845 LB |
1825 | allmulti = 1; |
1826 | mc_count = 0; | |
1827 | } | |
e81cd2d6 LB |
1828 | |
1829 | size = sizeof(*cmd) + mc_count * ETH_ALEN; | |
ce9e2e1b | 1830 | |
e81cd2d6 | 1831 | cmd = kzalloc(size, GFP_ATOMIC); |
a66098da | 1832 | if (cmd == NULL) |
e81cd2d6 | 1833 | return NULL; |
a66098da LB |
1834 | |
1835 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); | |
1836 | cmd->header.length = cpu_to_le16(size); | |
d5e30845 LB |
1837 | cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | |
1838 | MWL8K_ENABLE_RX_BROADCAST); | |
1839 | ||
1840 | if (allmulti) { | |
1841 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); | |
1842 | } else if (mc_count) { | |
1843 | int i; | |
1844 | ||
1845 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); | |
1846 | cmd->numaddr = cpu_to_le16(mc_count); | |
1847 | for (i = 0; i < mc_count && mclist; i++) { | |
1848 | if (mclist->da_addrlen != ETH_ALEN) { | |
1849 | kfree(cmd); | |
1850 | return NULL; | |
1851 | } | |
1852 | memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); | |
1853 | mclist = mclist->next; | |
a66098da | 1854 | } |
a66098da LB |
1855 | } |
1856 | ||
e81cd2d6 | 1857 | return &cmd->header; |
a66098da LB |
1858 | } |
1859 | ||
1860 | /* | |
55489b6e | 1861 | * CMD_GET_STAT. |
a66098da | 1862 | */ |
55489b6e | 1863 | struct mwl8k_cmd_get_stat { |
a66098da | 1864 | struct mwl8k_cmd_pkt header; |
a66098da LB |
1865 | __le32 stats[64]; |
1866 | } __attribute__((packed)); | |
1867 | ||
1868 | #define MWL8K_STAT_ACK_FAILURE 9 | |
1869 | #define MWL8K_STAT_RTS_FAILURE 12 | |
1870 | #define MWL8K_STAT_FCS_ERROR 24 | |
1871 | #define MWL8K_STAT_RTS_SUCCESS 11 | |
1872 | ||
55489b6e LB |
1873 | static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw, |
1874 | struct ieee80211_low_level_stats *stats) | |
a66098da | 1875 | { |
55489b6e | 1876 | struct mwl8k_cmd_get_stat *cmd; |
a66098da LB |
1877 | int rc; |
1878 | ||
1879 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1880 | if (cmd == NULL) | |
1881 | return -ENOMEM; | |
1882 | ||
1883 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); | |
1884 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
1885 | |
1886 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1887 | if (!rc) { | |
1888 | stats->dot11ACKFailureCount = | |
1889 | le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); | |
1890 | stats->dot11RTSFailureCount = | |
1891 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); | |
1892 | stats->dot11FCSErrorCount = | |
1893 | le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); | |
1894 | stats->dot11RTSSuccessCount = | |
1895 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); | |
1896 | } | |
1897 | kfree(cmd); | |
1898 | ||
1899 | return rc; | |
1900 | } | |
1901 | ||
1902 | /* | |
55489b6e | 1903 | * CMD_RADIO_CONTROL. |
a66098da | 1904 | */ |
55489b6e | 1905 | struct mwl8k_cmd_radio_control { |
a66098da LB |
1906 | struct mwl8k_cmd_pkt header; |
1907 | __le16 action; | |
1908 | __le16 control; | |
1909 | __le16 radio_on; | |
1910 | } __attribute__((packed)); | |
1911 | ||
c46563b7 | 1912 | static int |
55489b6e | 1913 | mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force) |
a66098da LB |
1914 | { |
1915 | struct mwl8k_priv *priv = hw->priv; | |
55489b6e | 1916 | struct mwl8k_cmd_radio_control *cmd; |
a66098da LB |
1917 | int rc; |
1918 | ||
c46563b7 | 1919 | if (enable == priv->radio_on && !force) |
a66098da LB |
1920 | return 0; |
1921 | ||
a66098da LB |
1922 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
1923 | if (cmd == NULL) | |
1924 | return -ENOMEM; | |
1925 | ||
1926 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); | |
1927 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1928 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
68ce3884 | 1929 | cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); |
a66098da LB |
1930 | cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); |
1931 | ||
1932 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1933 | kfree(cmd); | |
1934 | ||
1935 | if (!rc) | |
c46563b7 | 1936 | priv->radio_on = enable; |
a66098da LB |
1937 | |
1938 | return rc; | |
1939 | } | |
1940 | ||
55489b6e | 1941 | static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw) |
c46563b7 | 1942 | { |
55489b6e | 1943 | return mwl8k_cmd_radio_control(hw, 0, 0); |
c46563b7 LB |
1944 | } |
1945 | ||
55489b6e | 1946 | static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw) |
c46563b7 | 1947 | { |
55489b6e | 1948 | return mwl8k_cmd_radio_control(hw, 1, 0); |
c46563b7 LB |
1949 | } |
1950 | ||
a66098da LB |
1951 | static int |
1952 | mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) | |
1953 | { | |
99200a99 | 1954 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1955 | |
68ce3884 | 1956 | priv->radio_short_preamble = short_preamble; |
a66098da | 1957 | |
55489b6e | 1958 | return mwl8k_cmd_radio_control(hw, 1, 1); |
a66098da LB |
1959 | } |
1960 | ||
1961 | /* | |
55489b6e | 1962 | * CMD_RF_TX_POWER. |
a66098da LB |
1963 | */ |
1964 | #define MWL8K_TX_POWER_LEVEL_TOTAL 8 | |
1965 | ||
55489b6e | 1966 | struct mwl8k_cmd_rf_tx_power { |
a66098da LB |
1967 | struct mwl8k_cmd_pkt header; |
1968 | __le16 action; | |
1969 | __le16 support_level; | |
1970 | __le16 current_level; | |
1971 | __le16 reserved; | |
1972 | __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; | |
1973 | } __attribute__((packed)); | |
1974 | ||
55489b6e | 1975 | static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm) |
a66098da | 1976 | { |
55489b6e | 1977 | struct mwl8k_cmd_rf_tx_power *cmd; |
a66098da LB |
1978 | int rc; |
1979 | ||
1980 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1981 | if (cmd == NULL) | |
1982 | return -ENOMEM; | |
1983 | ||
1984 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); | |
1985 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1986 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
1987 | cmd->support_level = cpu_to_le16(dBm); | |
1988 | ||
1989 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1990 | kfree(cmd); | |
1991 | ||
1992 | return rc; | |
1993 | } | |
1994 | ||
08b06347 LB |
1995 | /* |
1996 | * CMD_RF_ANTENNA. | |
1997 | */ | |
1998 | struct mwl8k_cmd_rf_antenna { | |
1999 | struct mwl8k_cmd_pkt header; | |
2000 | __le16 antenna; | |
2001 | __le16 mode; | |
2002 | } __attribute__((packed)); | |
2003 | ||
2004 | #define MWL8K_RF_ANTENNA_RX 1 | |
2005 | #define MWL8K_RF_ANTENNA_TX 2 | |
2006 | ||
2007 | static int | |
2008 | mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) | |
2009 | { | |
2010 | struct mwl8k_cmd_rf_antenna *cmd; | |
2011 | int rc; | |
2012 | ||
2013 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2014 | if (cmd == NULL) | |
2015 | return -ENOMEM; | |
2016 | ||
2017 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); | |
2018 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2019 | cmd->antenna = cpu_to_le16(antenna); | |
2020 | cmd->mode = cpu_to_le16(mask); | |
2021 | ||
2022 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2023 | kfree(cmd); | |
2024 | ||
2025 | return rc; | |
2026 | } | |
2027 | ||
a66098da LB |
2028 | /* |
2029 | * CMD_SET_PRE_SCAN. | |
2030 | */ | |
2031 | struct mwl8k_cmd_set_pre_scan { | |
2032 | struct mwl8k_cmd_pkt header; | |
2033 | } __attribute__((packed)); | |
2034 | ||
2035 | static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) | |
2036 | { | |
2037 | struct mwl8k_cmd_set_pre_scan *cmd; | |
2038 | int rc; | |
2039 | ||
2040 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2041 | if (cmd == NULL) | |
2042 | return -ENOMEM; | |
2043 | ||
2044 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); | |
2045 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2046 | ||
2047 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2048 | kfree(cmd); | |
2049 | ||
2050 | return rc; | |
2051 | } | |
2052 | ||
2053 | /* | |
2054 | * CMD_SET_POST_SCAN. | |
2055 | */ | |
2056 | struct mwl8k_cmd_set_post_scan { | |
2057 | struct mwl8k_cmd_pkt header; | |
2058 | __le32 isibss; | |
d89173f2 | 2059 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2060 | } __attribute__((packed)); |
2061 | ||
2062 | static int | |
0a11dfc3 | 2063 | mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac) |
a66098da LB |
2064 | { |
2065 | struct mwl8k_cmd_set_post_scan *cmd; | |
2066 | int rc; | |
2067 | ||
2068 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2069 | if (cmd == NULL) | |
2070 | return -ENOMEM; | |
2071 | ||
2072 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); | |
2073 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2074 | cmd->isibss = 0; | |
d89173f2 | 2075 | memcpy(cmd->bssid, mac, ETH_ALEN); |
a66098da LB |
2076 | |
2077 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2078 | kfree(cmd); | |
2079 | ||
2080 | return rc; | |
2081 | } | |
2082 | ||
2083 | /* | |
2084 | * CMD_SET_RF_CHANNEL. | |
2085 | */ | |
2086 | struct mwl8k_cmd_set_rf_channel { | |
2087 | struct mwl8k_cmd_pkt header; | |
2088 | __le16 action; | |
2089 | __u8 current_channel; | |
2090 | __le32 channel_flags; | |
2091 | } __attribute__((packed)); | |
2092 | ||
2093 | static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, | |
610677d2 | 2094 | struct ieee80211_conf *conf) |
a66098da | 2095 | { |
610677d2 | 2096 | struct ieee80211_channel *channel = conf->channel; |
a66098da LB |
2097 | struct mwl8k_cmd_set_rf_channel *cmd; |
2098 | int rc; | |
2099 | ||
2100 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2101 | if (cmd == NULL) | |
2102 | return -ENOMEM; | |
2103 | ||
2104 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); | |
2105 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2106 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2107 | cmd->current_channel = channel->hw_value; | |
610677d2 | 2108 | |
a66098da | 2109 | if (channel->band == IEEE80211_BAND_2GHZ) |
610677d2 LB |
2110 | cmd->channel_flags |= cpu_to_le32(0x00000001); |
2111 | ||
2112 | if (conf->channel_type == NL80211_CHAN_NO_HT || | |
2113 | conf->channel_type == NL80211_CHAN_HT20) | |
2114 | cmd->channel_flags |= cpu_to_le32(0x00000080); | |
2115 | else if (conf->channel_type == NL80211_CHAN_HT40MINUS) | |
2116 | cmd->channel_flags |= cpu_to_le32(0x000001900); | |
2117 | else if (conf->channel_type == NL80211_CHAN_HT40PLUS) | |
2118 | cmd->channel_flags |= cpu_to_le32(0x000000900); | |
a66098da LB |
2119 | |
2120 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2121 | kfree(cmd); | |
2122 | ||
2123 | return rc; | |
2124 | } | |
2125 | ||
2126 | /* | |
55489b6e | 2127 | * CMD_SET_AID. |
a66098da | 2128 | */ |
55489b6e LB |
2129 | #define MWL8K_FRAME_PROT_DISABLED 0x00 |
2130 | #define MWL8K_FRAME_PROT_11G 0x07 | |
2131 | #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 | |
2132 | #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 | |
a66098da | 2133 | |
55489b6e LB |
2134 | struct mwl8k_cmd_update_set_aid { |
2135 | struct mwl8k_cmd_pkt header; | |
2136 | __le16 aid; | |
a66098da | 2137 | |
55489b6e LB |
2138 | /* AP's MAC address (BSSID) */ |
2139 | __u8 bssid[ETH_ALEN]; | |
2140 | __le16 protection_mode; | |
2141 | __u8 supp_rates[14]; | |
a66098da LB |
2142 | } __attribute__((packed)); |
2143 | ||
c6e96010 LB |
2144 | static void legacy_rate_mask_to_array(u8 *rates, u32 mask) |
2145 | { | |
2146 | int i; | |
2147 | int j; | |
2148 | ||
2149 | /* | |
2150 | * Clear nonstandard rates 4 and 13. | |
2151 | */ | |
2152 | mask &= 0x1fef; | |
2153 | ||
2154 | for (i = 0, j = 0; i < 14; i++) { | |
2155 | if (mask & (1 << i)) | |
2156 | rates[j++] = mwl8k_rates[i].hw_value; | |
2157 | } | |
2158 | } | |
2159 | ||
55489b6e | 2160 | static int |
c6e96010 LB |
2161 | mwl8k_cmd_set_aid(struct ieee80211_hw *hw, |
2162 | struct ieee80211_vif *vif, u32 legacy_rate_mask) | |
a66098da | 2163 | { |
55489b6e LB |
2164 | struct mwl8k_cmd_update_set_aid *cmd; |
2165 | u16 prot_mode; | |
a66098da LB |
2166 | int rc; |
2167 | ||
2168 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2169 | if (cmd == NULL) | |
2170 | return -ENOMEM; | |
2171 | ||
55489b6e | 2172 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); |
a66098da | 2173 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
7dc6a7a7 | 2174 | cmd->aid = cpu_to_le16(vif->bss_conf.aid); |
0a11dfc3 | 2175 | memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN); |
a66098da | 2176 | |
7dc6a7a7 | 2177 | if (vif->bss_conf.use_cts_prot) { |
55489b6e LB |
2178 | prot_mode = MWL8K_FRAME_PROT_11G; |
2179 | } else { | |
7dc6a7a7 | 2180 | switch (vif->bss_conf.ht_operation_mode & |
55489b6e LB |
2181 | IEEE80211_HT_OP_MODE_PROTECTION) { |
2182 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
2183 | prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; | |
2184 | break; | |
2185 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
2186 | prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; | |
2187 | break; | |
2188 | default: | |
2189 | prot_mode = MWL8K_FRAME_PROT_DISABLED; | |
2190 | break; | |
2191 | } | |
2192 | } | |
2193 | cmd->protection_mode = cpu_to_le16(prot_mode); | |
a66098da | 2194 | |
c6e96010 | 2195 | legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask); |
a66098da LB |
2196 | |
2197 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2198 | kfree(cmd); | |
2199 | ||
2200 | return rc; | |
2201 | } | |
2202 | ||
32060e1b | 2203 | /* |
55489b6e | 2204 | * CMD_SET_RATE. |
32060e1b | 2205 | */ |
55489b6e LB |
2206 | struct mwl8k_cmd_set_rate { |
2207 | struct mwl8k_cmd_pkt header; | |
2208 | __u8 legacy_rates[14]; | |
2209 | ||
2210 | /* Bitmap for supported MCS codes. */ | |
2211 | __u8 mcs_set[16]; | |
2212 | __u8 reserved[16]; | |
32060e1b LB |
2213 | } __attribute__((packed)); |
2214 | ||
55489b6e | 2215 | static int |
c6e96010 | 2216 | mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
13935e2c | 2217 | u32 legacy_rate_mask, u8 *mcs_rates) |
32060e1b | 2218 | { |
55489b6e | 2219 | struct mwl8k_cmd_set_rate *cmd; |
32060e1b LB |
2220 | int rc; |
2221 | ||
2222 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2223 | if (cmd == NULL) | |
2224 | return -ENOMEM; | |
2225 | ||
55489b6e | 2226 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); |
32060e1b | 2227 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
c6e96010 | 2228 | legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask); |
13935e2c | 2229 | memcpy(cmd->mcs_set, mcs_rates, 16); |
32060e1b LB |
2230 | |
2231 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2232 | kfree(cmd); | |
2233 | ||
2234 | return rc; | |
2235 | } | |
2236 | ||
a66098da | 2237 | /* |
55489b6e | 2238 | * CMD_FINALIZE_JOIN. |
a66098da | 2239 | */ |
55489b6e LB |
2240 | #define MWL8K_FJ_BEACON_MAXLEN 128 |
2241 | ||
2242 | struct mwl8k_cmd_finalize_join { | |
a66098da | 2243 | struct mwl8k_cmd_pkt header; |
55489b6e LB |
2244 | __le32 sleep_interval; /* Number of beacon periods to sleep */ |
2245 | __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; | |
a66098da LB |
2246 | } __attribute__((packed)); |
2247 | ||
55489b6e LB |
2248 | static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame, |
2249 | int framelen, int dtim) | |
a66098da | 2250 | { |
55489b6e LB |
2251 | struct mwl8k_cmd_finalize_join *cmd; |
2252 | struct ieee80211_mgmt *payload = frame; | |
2253 | int payload_len; | |
a66098da LB |
2254 | int rc; |
2255 | ||
2256 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2257 | if (cmd == NULL) | |
2258 | return -ENOMEM; | |
2259 | ||
55489b6e | 2260 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); |
a66098da | 2261 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2262 | cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); |
2263 | ||
2264 | payload_len = framelen - ieee80211_hdrlen(payload->frame_control); | |
2265 | if (payload_len < 0) | |
2266 | payload_len = 0; | |
2267 | else if (payload_len > MWL8K_FJ_BEACON_MAXLEN) | |
2268 | payload_len = MWL8K_FJ_BEACON_MAXLEN; | |
2269 | ||
2270 | memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); | |
a66098da LB |
2271 | |
2272 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2273 | kfree(cmd); | |
2274 | ||
2275 | return rc; | |
2276 | } | |
2277 | ||
2278 | /* | |
55489b6e | 2279 | * CMD_SET_RTS_THRESHOLD. |
a66098da | 2280 | */ |
55489b6e | 2281 | struct mwl8k_cmd_set_rts_threshold { |
a66098da LB |
2282 | struct mwl8k_cmd_pkt header; |
2283 | __le16 action; | |
55489b6e | 2284 | __le16 threshold; |
a66098da LB |
2285 | } __attribute__((packed)); |
2286 | ||
c2c2b12a LB |
2287 | static int |
2288 | mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh) | |
a66098da | 2289 | { |
55489b6e | 2290 | struct mwl8k_cmd_set_rts_threshold *cmd; |
a66098da LB |
2291 | int rc; |
2292 | ||
2293 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2294 | if (cmd == NULL) | |
2295 | return -ENOMEM; | |
2296 | ||
55489b6e | 2297 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); |
a66098da | 2298 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
c2c2b12a LB |
2299 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); |
2300 | cmd->threshold = cpu_to_le16(rts_thresh); | |
a66098da LB |
2301 | |
2302 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2303 | kfree(cmd); | |
2304 | ||
a66098da LB |
2305 | return rc; |
2306 | } | |
2307 | ||
2308 | /* | |
55489b6e | 2309 | * CMD_SET_SLOT. |
a66098da | 2310 | */ |
55489b6e | 2311 | struct mwl8k_cmd_set_slot { |
a66098da LB |
2312 | struct mwl8k_cmd_pkt header; |
2313 | __le16 action; | |
55489b6e | 2314 | __u8 short_slot; |
a66098da LB |
2315 | } __attribute__((packed)); |
2316 | ||
55489b6e | 2317 | static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) |
a66098da | 2318 | { |
55489b6e | 2319 | struct mwl8k_cmd_set_slot *cmd; |
a66098da LB |
2320 | int rc; |
2321 | ||
2322 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2323 | if (cmd == NULL) | |
2324 | return -ENOMEM; | |
2325 | ||
55489b6e | 2326 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); |
a66098da | 2327 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2328 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); |
2329 | cmd->short_slot = short_slot_time; | |
a66098da LB |
2330 | |
2331 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2332 | kfree(cmd); | |
2333 | ||
2334 | return rc; | |
2335 | } | |
2336 | ||
2337 | /* | |
2338 | * CMD_SET_EDCA_PARAMS. | |
2339 | */ | |
2340 | struct mwl8k_cmd_set_edca_params { | |
2341 | struct mwl8k_cmd_pkt header; | |
2342 | ||
2343 | /* See MWL8K_SET_EDCA_XXX below */ | |
2344 | __le16 action; | |
2345 | ||
2346 | /* TX opportunity in units of 32 us */ | |
2347 | __le16 txop; | |
2348 | ||
2e484c89 LB |
2349 | union { |
2350 | struct { | |
2351 | /* Log exponent of max contention period: 0...15 */ | |
2352 | __le32 log_cw_max; | |
2353 | ||
2354 | /* Log exponent of min contention period: 0...15 */ | |
2355 | __le32 log_cw_min; | |
2356 | ||
2357 | /* Adaptive interframe spacing in units of 32us */ | |
2358 | __u8 aifs; | |
2359 | ||
2360 | /* TX queue to configure */ | |
2361 | __u8 txq; | |
2362 | } ap; | |
2363 | struct { | |
2364 | /* Log exponent of max contention period: 0...15 */ | |
2365 | __u8 log_cw_max; | |
a66098da | 2366 | |
2e484c89 LB |
2367 | /* Log exponent of min contention period: 0...15 */ |
2368 | __u8 log_cw_min; | |
a66098da | 2369 | |
2e484c89 LB |
2370 | /* Adaptive interframe spacing in units of 32us */ |
2371 | __u8 aifs; | |
a66098da | 2372 | |
2e484c89 LB |
2373 | /* TX queue to configure */ |
2374 | __u8 txq; | |
2375 | } sta; | |
2376 | }; | |
a66098da LB |
2377 | } __attribute__((packed)); |
2378 | ||
a66098da LB |
2379 | #define MWL8K_SET_EDCA_CW 0x01 |
2380 | #define MWL8K_SET_EDCA_TXOP 0x02 | |
2381 | #define MWL8K_SET_EDCA_AIFS 0x04 | |
2382 | ||
2383 | #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ | |
2384 | MWL8K_SET_EDCA_TXOP | \ | |
2385 | MWL8K_SET_EDCA_AIFS) | |
2386 | ||
2387 | static int | |
55489b6e LB |
2388 | mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, |
2389 | __u16 cw_min, __u16 cw_max, | |
2390 | __u8 aifs, __u16 txop) | |
a66098da | 2391 | { |
2e484c89 | 2392 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2393 | struct mwl8k_cmd_set_edca_params *cmd; |
a66098da LB |
2394 | int rc; |
2395 | ||
2396 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2397 | if (cmd == NULL) | |
2398 | return -ENOMEM; | |
2399 | ||
a66098da LB |
2400 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); |
2401 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
2402 | cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); |
2403 | cmd->txop = cpu_to_le16(txop); | |
2e484c89 LB |
2404 | if (priv->ap_fw) { |
2405 | cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); | |
2406 | cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); | |
2407 | cmd->ap.aifs = aifs; | |
2408 | cmd->ap.txq = qnum; | |
2409 | } else { | |
2410 | cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); | |
2411 | cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); | |
2412 | cmd->sta.aifs = aifs; | |
2413 | cmd->sta.txq = qnum; | |
2414 | } | |
a66098da LB |
2415 | |
2416 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2417 | kfree(cmd); | |
2418 | ||
2419 | return rc; | |
2420 | } | |
2421 | ||
2422 | /* | |
55489b6e | 2423 | * CMD_SET_WMM_MODE. |
a66098da | 2424 | */ |
55489b6e | 2425 | struct mwl8k_cmd_set_wmm_mode { |
a66098da | 2426 | struct mwl8k_cmd_pkt header; |
55489b6e | 2427 | __le16 action; |
a66098da LB |
2428 | } __attribute__((packed)); |
2429 | ||
55489b6e | 2430 | static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable) |
a66098da | 2431 | { |
55489b6e LB |
2432 | struct mwl8k_priv *priv = hw->priv; |
2433 | struct mwl8k_cmd_set_wmm_mode *cmd; | |
a66098da LB |
2434 | int rc; |
2435 | ||
a66098da LB |
2436 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
2437 | if (cmd == NULL) | |
2438 | return -ENOMEM; | |
2439 | ||
55489b6e | 2440 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); |
a66098da | 2441 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e | 2442 | cmd->action = cpu_to_le16(!!enable); |
a66098da LB |
2443 | |
2444 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2445 | kfree(cmd); | |
16cec43d | 2446 | |
55489b6e LB |
2447 | if (!rc) |
2448 | priv->wmm_enabled = enable; | |
a66098da LB |
2449 | |
2450 | return rc; | |
2451 | } | |
2452 | ||
2453 | /* | |
55489b6e | 2454 | * CMD_MIMO_CONFIG. |
a66098da | 2455 | */ |
55489b6e LB |
2456 | struct mwl8k_cmd_mimo_config { |
2457 | struct mwl8k_cmd_pkt header; | |
2458 | __le32 action; | |
2459 | __u8 rx_antenna_map; | |
2460 | __u8 tx_antenna_map; | |
a66098da LB |
2461 | } __attribute__((packed)); |
2462 | ||
55489b6e | 2463 | static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) |
a66098da | 2464 | { |
55489b6e | 2465 | struct mwl8k_cmd_mimo_config *cmd; |
a66098da LB |
2466 | int rc; |
2467 | ||
2468 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2469 | if (cmd == NULL) | |
2470 | return -ENOMEM; | |
2471 | ||
55489b6e | 2472 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); |
a66098da | 2473 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2474 | cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); |
2475 | cmd->rx_antenna_map = rx; | |
2476 | cmd->tx_antenna_map = tx; | |
a66098da LB |
2477 | |
2478 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2479 | kfree(cmd); | |
2480 | ||
2481 | return rc; | |
2482 | } | |
2483 | ||
2484 | /* | |
b71ed2c6 | 2485 | * CMD_USE_FIXED_RATE (STA version). |
a66098da | 2486 | */ |
b71ed2c6 LB |
2487 | struct mwl8k_cmd_use_fixed_rate_sta { |
2488 | struct mwl8k_cmd_pkt header; | |
2489 | __le32 action; | |
2490 | __le32 allow_rate_drop; | |
2491 | __le32 num_rates; | |
2492 | struct { | |
2493 | __le32 is_ht_rate; | |
2494 | __le32 enable_retry; | |
2495 | __le32 rate; | |
2496 | __le32 retry_count; | |
2497 | } rate_entry[8]; | |
2498 | __le32 rate_type; | |
2499 | __le32 reserved1; | |
2500 | __le32 reserved2; | |
a66098da LB |
2501 | } __attribute__((packed)); |
2502 | ||
b71ed2c6 LB |
2503 | #define MWL8K_USE_AUTO_RATE 0x0002 |
2504 | #define MWL8K_UCAST_RATE 0 | |
a66098da | 2505 | |
b71ed2c6 | 2506 | static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw) |
a66098da | 2507 | { |
b71ed2c6 | 2508 | struct mwl8k_cmd_use_fixed_rate_sta *cmd; |
a66098da LB |
2509 | int rc; |
2510 | ||
2511 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2512 | if (cmd == NULL) | |
2513 | return -ENOMEM; | |
2514 | ||
2515 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2516 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
b71ed2c6 LB |
2517 | cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE); |
2518 | cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE); | |
a66098da LB |
2519 | |
2520 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2521 | kfree(cmd); | |
2522 | ||
2523 | return rc; | |
2524 | } | |
2525 | ||
55489b6e LB |
2526 | /* |
2527 | * CMD_ENABLE_SNIFFER. | |
2528 | */ | |
2529 | struct mwl8k_cmd_enable_sniffer { | |
2530 | struct mwl8k_cmd_pkt header; | |
2531 | __le32 action; | |
2532 | } __attribute__((packed)); | |
2533 | ||
2534 | static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable) | |
2535 | { | |
2536 | struct mwl8k_cmd_enable_sniffer *cmd; | |
2537 | int rc; | |
2538 | ||
2539 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2540 | if (cmd == NULL) | |
2541 | return -ENOMEM; | |
2542 | ||
2543 | cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); | |
2544 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2545 | cmd->action = cpu_to_le32(!!enable); | |
2546 | ||
2547 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2548 | kfree(cmd); | |
2549 | ||
2550 | return rc; | |
2551 | } | |
2552 | ||
2553 | /* | |
2554 | * CMD_SET_MAC_ADDR. | |
2555 | */ | |
2556 | struct mwl8k_cmd_set_mac_addr { | |
2557 | struct mwl8k_cmd_pkt header; | |
2558 | union { | |
2559 | struct { | |
2560 | __le16 mac_type; | |
2561 | __u8 mac_addr[ETH_ALEN]; | |
2562 | } mbss; | |
2563 | __u8 mac_addr[ETH_ALEN]; | |
2564 | }; | |
2565 | } __attribute__((packed)); | |
2566 | ||
2567 | static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) | |
2568 | { | |
2569 | struct mwl8k_priv *priv = hw->priv; | |
2570 | struct mwl8k_cmd_set_mac_addr *cmd; | |
2571 | int rc; | |
2572 | ||
2573 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2574 | if (cmd == NULL) | |
2575 | return -ENOMEM; | |
2576 | ||
2577 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); | |
2578 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2579 | if (priv->ap_fw) { | |
2580 | cmd->mbss.mac_type = 0; | |
2581 | memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); | |
2582 | } else { | |
2583 | memcpy(cmd->mac_addr, mac, ETH_ALEN); | |
2584 | } | |
2585 | ||
2586 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2587 | kfree(cmd); | |
2588 | ||
2589 | return rc; | |
2590 | } | |
2591 | ||
2592 | /* | |
2593 | * CMD_SET_RATEADAPT_MODE. | |
2594 | */ | |
2595 | struct mwl8k_cmd_set_rate_adapt_mode { | |
2596 | struct mwl8k_cmd_pkt header; | |
2597 | __le16 action; | |
2598 | __le16 mode; | |
2599 | } __attribute__((packed)); | |
2600 | ||
2601 | static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode) | |
2602 | { | |
2603 | struct mwl8k_cmd_set_rate_adapt_mode *cmd; | |
2604 | int rc; | |
2605 | ||
2606 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2607 | if (cmd == NULL) | |
2608 | return -ENOMEM; | |
2609 | ||
2610 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); | |
2611 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2612 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2613 | cmd->mode = cpu_to_le16(mode); | |
2614 | ||
2615 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2616 | kfree(cmd); | |
2617 | ||
2618 | return rc; | |
2619 | } | |
2620 | ||
2621 | /* | |
2622 | * CMD_UPDATE_STADB. | |
2623 | */ | |
25d81b1e LB |
2624 | struct ewc_ht_info { |
2625 | __le16 control1; | |
2626 | __le16 control2; | |
2627 | __le16 control3; | |
2628 | } __attribute__((packed)); | |
2629 | ||
2630 | struct peer_capability_info { | |
2631 | /* Peer type - AP vs. STA. */ | |
2632 | __u8 peer_type; | |
2633 | ||
2634 | /* Basic 802.11 capabilities from assoc resp. */ | |
2635 | __le16 basic_caps; | |
2636 | ||
2637 | /* Set if peer supports 802.11n high throughput (HT). */ | |
2638 | __u8 ht_support; | |
2639 | ||
2640 | /* Valid if HT is supported. */ | |
2641 | __le16 ht_caps; | |
2642 | __u8 extended_ht_caps; | |
2643 | struct ewc_ht_info ewc_info; | |
2644 | ||
2645 | /* Legacy rate table. Intersection of our rates and peer rates. */ | |
2646 | __u8 legacy_rates[12]; | |
2647 | ||
2648 | /* HT rate table. Intersection of our rates and peer rates. */ | |
2649 | __u8 ht_rates[16]; | |
2650 | __u8 pad[16]; | |
2651 | ||
2652 | /* If set, interoperability mode, no proprietary extensions. */ | |
2653 | __u8 interop; | |
2654 | __u8 pad2; | |
2655 | __u8 station_id; | |
2656 | __le16 amsdu_enabled; | |
2657 | } __attribute__((packed)); | |
2658 | ||
55489b6e LB |
2659 | struct mwl8k_cmd_update_stadb { |
2660 | struct mwl8k_cmd_pkt header; | |
2661 | ||
2662 | /* See STADB_ACTION_TYPE */ | |
2663 | __le32 action; | |
2664 | ||
2665 | /* Peer MAC address */ | |
2666 | __u8 peer_addr[ETH_ALEN]; | |
2667 | ||
2668 | __le32 reserved; | |
2669 | ||
2670 | /* Peer info - valid during add/update. */ | |
2671 | struct peer_capability_info peer_info; | |
2672 | } __attribute__((packed)); | |
2673 | ||
a680400e LB |
2674 | #define MWL8K_STA_DB_MODIFY_ENTRY 1 |
2675 | #define MWL8K_STA_DB_DEL_ENTRY 2 | |
2676 | ||
2677 | /* Peer Entry flags - used to define the type of the peer node */ | |
2678 | #define MWL8K_PEER_TYPE_ACCESSPOINT 2 | |
2679 | ||
2680 | static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw, | |
c6e96010 | 2681 | struct ieee80211_vif *vif, |
13935e2c | 2682 | struct ieee80211_sta *sta) |
55489b6e | 2683 | { |
55489b6e | 2684 | struct mwl8k_cmd_update_stadb *cmd; |
a680400e | 2685 | struct peer_capability_info *p; |
55489b6e LB |
2686 | int rc; |
2687 | ||
2688 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2689 | if (cmd == NULL) | |
2690 | return -ENOMEM; | |
2691 | ||
2692 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2693 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a680400e | 2694 | cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY); |
13935e2c | 2695 | memcpy(cmd->peer_addr, sta->addr, ETH_ALEN); |
55489b6e | 2696 | |
a680400e LB |
2697 | p = &cmd->peer_info; |
2698 | p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; | |
2699 | p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability); | |
13935e2c LB |
2700 | p->ht_support = sta->ht_cap.ht_supported; |
2701 | p->ht_caps = sta->ht_cap.cap; | |
2702 | p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) | | |
2703 | ((sta->ht_cap.ampdu_density & 7) << 2); | |
2704 | legacy_rate_mask_to_array(p->legacy_rates, | |
2705 | sta->supp_rates[IEEE80211_BAND_2GHZ]); | |
2706 | memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16); | |
a680400e LB |
2707 | p->interop = 1; |
2708 | p->amsdu_enabled = 0; | |
2709 | ||
2710 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2711 | kfree(cmd); | |
2712 | ||
2713 | return rc ? rc : p->station_id; | |
2714 | } | |
2715 | ||
2716 | static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw, | |
2717 | struct ieee80211_vif *vif, u8 *addr) | |
2718 | { | |
2719 | struct mwl8k_cmd_update_stadb *cmd; | |
2720 | int rc; | |
2721 | ||
2722 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2723 | if (cmd == NULL) | |
2724 | return -ENOMEM; | |
2725 | ||
2726 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2727 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2728 | cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY); | |
bbfd9128 | 2729 | memcpy(cmd->peer_addr, addr, ETH_ALEN); |
55489b6e | 2730 | |
a680400e | 2731 | rc = mwl8k_post_cmd(hw, &cmd->header); |
55489b6e LB |
2732 | kfree(cmd); |
2733 | ||
2734 | return rc; | |
2735 | } | |
2736 | ||
a66098da LB |
2737 | |
2738 | /* | |
2739 | * Interrupt handling. | |
2740 | */ | |
2741 | static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) | |
2742 | { | |
2743 | struct ieee80211_hw *hw = dev_id; | |
2744 | struct mwl8k_priv *priv = hw->priv; | |
2745 | u32 status; | |
2746 | ||
2747 | status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2748 | iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2749 | ||
a66098da LB |
2750 | if (!status) |
2751 | return IRQ_NONE; | |
2752 | ||
2753 | if (status & MWL8K_A2H_INT_TX_DONE) | |
2754 | tasklet_schedule(&priv->tx_reclaim_task); | |
2755 | ||
2756 | if (status & MWL8K_A2H_INT_RX_READY) { | |
2757 | while (rxq_process(hw, 0, 1)) | |
2758 | rxq_refill(hw, 0, 1); | |
2759 | } | |
2760 | ||
2761 | if (status & MWL8K_A2H_INT_OPC_DONE) { | |
618952a7 | 2762 | if (priv->hostcmd_wait != NULL) |
a66098da | 2763 | complete(priv->hostcmd_wait); |
a66098da LB |
2764 | } |
2765 | ||
2766 | if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { | |
618952a7 | 2767 | if (!mutex_is_locked(&priv->fw_mutex) && |
88de754a | 2768 | priv->radio_on && priv->pending_tx_pkts) |
618952a7 | 2769 | mwl8k_tx_start(priv); |
a66098da LB |
2770 | } |
2771 | ||
2772 | return IRQ_HANDLED; | |
2773 | } | |
2774 | ||
2775 | ||
2776 | /* | |
2777 | * Core driver operations. | |
2778 | */ | |
2779 | static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
2780 | { | |
2781 | struct mwl8k_priv *priv = hw->priv; | |
2782 | int index = skb_get_queue_mapping(skb); | |
2783 | int rc; | |
2784 | ||
2785 | if (priv->current_channel == NULL) { | |
2786 | printk(KERN_DEBUG "%s: dropped TX frame since radio " | |
c2c357ce | 2787 | "disabled\n", wiphy_name(hw->wiphy)); |
a66098da LB |
2788 | dev_kfree_skb(skb); |
2789 | return NETDEV_TX_OK; | |
2790 | } | |
2791 | ||
2792 | rc = mwl8k_txq_xmit(hw, index, skb); | |
2793 | ||
2794 | return rc; | |
2795 | } | |
2796 | ||
a66098da LB |
2797 | static int mwl8k_start(struct ieee80211_hw *hw) |
2798 | { | |
a66098da LB |
2799 | struct mwl8k_priv *priv = hw->priv; |
2800 | int rc; | |
2801 | ||
a0607fd3 | 2802 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
2803 | IRQF_SHARED, MWL8K_NAME, hw); |
2804 | if (rc) { | |
2805 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 2806 | wiphy_name(hw->wiphy)); |
2ec610cb | 2807 | return -EIO; |
a66098da LB |
2808 | } |
2809 | ||
2ec610cb LB |
2810 | /* Enable tx reclaim tasklet */ |
2811 | tasklet_enable(&priv->tx_reclaim_task); | |
2812 | ||
a66098da | 2813 | /* Enable interrupts */ |
c23b5a69 | 2814 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da | 2815 | |
2ec610cb LB |
2816 | rc = mwl8k_fw_lock(hw); |
2817 | if (!rc) { | |
55489b6e | 2818 | rc = mwl8k_cmd_radio_enable(hw); |
a66098da | 2819 | |
5e4cf166 LB |
2820 | if (!priv->ap_fw) { |
2821 | if (!rc) | |
55489b6e | 2822 | rc = mwl8k_cmd_enable_sniffer(hw, 0); |
a66098da | 2823 | |
5e4cf166 LB |
2824 | if (!rc) |
2825 | rc = mwl8k_cmd_set_pre_scan(hw); | |
2826 | ||
2827 | if (!rc) | |
2828 | rc = mwl8k_cmd_set_post_scan(hw, | |
2829 | "\x00\x00\x00\x00\x00\x00"); | |
2830 | } | |
2ec610cb LB |
2831 | |
2832 | if (!rc) | |
55489b6e | 2833 | rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); |
a66098da | 2834 | |
2ec610cb | 2835 | if (!rc) |
55489b6e | 2836 | rc = mwl8k_cmd_set_wmm_mode(hw, 0); |
a66098da | 2837 | |
2ec610cb LB |
2838 | mwl8k_fw_unlock(hw); |
2839 | } | |
2840 | ||
2841 | if (rc) { | |
2842 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); | |
2843 | free_irq(priv->pdev->irq, hw); | |
2844 | tasklet_disable(&priv->tx_reclaim_task); | |
2845 | } | |
a66098da LB |
2846 | |
2847 | return rc; | |
2848 | } | |
2849 | ||
a66098da LB |
2850 | static void mwl8k_stop(struct ieee80211_hw *hw) |
2851 | { | |
a66098da LB |
2852 | struct mwl8k_priv *priv = hw->priv; |
2853 | int i; | |
2854 | ||
55489b6e | 2855 | mwl8k_cmd_radio_disable(hw); |
a66098da LB |
2856 | |
2857 | ieee80211_stop_queues(hw); | |
2858 | ||
a66098da | 2859 | /* Disable interrupts */ |
a66098da | 2860 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
2861 | free_irq(priv->pdev->irq, hw); |
2862 | ||
2863 | /* Stop finalize join worker */ | |
2864 | cancel_work_sync(&priv->finalize_join_worker); | |
2865 | if (priv->beacon_skb != NULL) | |
2866 | dev_kfree_skb(priv->beacon_skb); | |
2867 | ||
2868 | /* Stop tx reclaim tasklet */ | |
2869 | tasklet_disable(&priv->tx_reclaim_task); | |
2870 | ||
a66098da LB |
2871 | /* Return all skbs to mac80211 */ |
2872 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
2873 | mwl8k_txq_reclaim(hw, i, 1); | |
2874 | } | |
2875 | ||
2876 | static int mwl8k_add_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 2877 | struct ieee80211_vif *vif) |
a66098da LB |
2878 | { |
2879 | struct mwl8k_priv *priv = hw->priv; | |
2880 | struct mwl8k_vif *mwl8k_vif; | |
2881 | ||
2882 | /* | |
2883 | * We only support one active interface at a time. | |
2884 | */ | |
2885 | if (priv->vif != NULL) | |
2886 | return -EBUSY; | |
2887 | ||
2888 | /* | |
2889 | * We only support managed interfaces for now. | |
2890 | */ | |
1ed32e4f | 2891 | if (vif->type != NL80211_IFTYPE_STATION) |
a66098da LB |
2892 | return -EINVAL; |
2893 | ||
a43c49a8 LB |
2894 | /* |
2895 | * Reject interface creation if sniffer mode is active, as | |
2896 | * STA operation is mutually exclusive with hardware sniffer | |
2897 | * mode. | |
2898 | */ | |
2899 | if (priv->sniffer_enabled) { | |
2900 | printk(KERN_INFO "%s: unable to create STA " | |
2901 | "interface due to sniffer mode being enabled\n", | |
2902 | wiphy_name(hw->wiphy)); | |
2903 | return -EINVAL; | |
2904 | } | |
2905 | ||
c2c2b12a LB |
2906 | /* Set the mac address. */ |
2907 | mwl8k_cmd_set_mac_addr(hw, vif->addr); | |
2908 | ||
a66098da | 2909 | /* Clean out driver private area */ |
1ed32e4f | 2910 | mwl8k_vif = MWL8K_VIF(vif); |
a66098da LB |
2911 | memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); |
2912 | ||
a66098da LB |
2913 | /* Set Initial sequence number to zero */ |
2914 | mwl8k_vif->seqno = 0; | |
2915 | ||
1ed32e4f | 2916 | priv->vif = vif; |
a66098da LB |
2917 | priv->current_channel = NULL; |
2918 | ||
2919 | return 0; | |
2920 | } | |
2921 | ||
2922 | static void mwl8k_remove_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 2923 | struct ieee80211_vif *vif) |
a66098da LB |
2924 | { |
2925 | struct mwl8k_priv *priv = hw->priv; | |
2926 | ||
55489b6e | 2927 | mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b | 2928 | |
a66098da LB |
2929 | priv->vif = NULL; |
2930 | } | |
2931 | ||
ee03a932 | 2932 | static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) |
a66098da | 2933 | { |
a66098da LB |
2934 | struct ieee80211_conf *conf = &hw->conf; |
2935 | struct mwl8k_priv *priv = hw->priv; | |
ee03a932 | 2936 | int rc; |
a66098da | 2937 | |
7595d67a | 2938 | if (conf->flags & IEEE80211_CONF_IDLE) { |
55489b6e | 2939 | mwl8k_cmd_radio_disable(hw); |
7595d67a | 2940 | priv->current_channel = NULL; |
ee03a932 | 2941 | return 0; |
7595d67a LB |
2942 | } |
2943 | ||
ee03a932 LB |
2944 | rc = mwl8k_fw_lock(hw); |
2945 | if (rc) | |
2946 | return rc; | |
a66098da | 2947 | |
55489b6e | 2948 | rc = mwl8k_cmd_radio_enable(hw); |
ee03a932 LB |
2949 | if (rc) |
2950 | goto out; | |
a66098da | 2951 | |
610677d2 | 2952 | rc = mwl8k_cmd_set_rf_channel(hw, conf); |
ee03a932 LB |
2953 | if (rc) |
2954 | goto out; | |
2955 | ||
2956 | priv->current_channel = conf->channel; | |
a66098da LB |
2957 | |
2958 | if (conf->power_level > 18) | |
2959 | conf->power_level = 18; | |
55489b6e | 2960 | rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level); |
ee03a932 LB |
2961 | if (rc) |
2962 | goto out; | |
a66098da | 2963 | |
08b06347 LB |
2964 | if (priv->ap_fw) { |
2965 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); | |
2966 | if (!rc) | |
2967 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); | |
2968 | } else { | |
2969 | rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); | |
2970 | } | |
a66098da | 2971 | |
ee03a932 LB |
2972 | out: |
2973 | mwl8k_fw_unlock(hw); | |
a66098da | 2974 | |
ee03a932 | 2975 | return rc; |
a66098da LB |
2976 | } |
2977 | ||
3a980d0a LB |
2978 | static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, |
2979 | struct ieee80211_vif *vif, | |
2980 | struct ieee80211_bss_conf *info, | |
2981 | u32 changed) | |
a66098da | 2982 | { |
a66098da | 2983 | struct mwl8k_priv *priv = hw->priv; |
c3cbbe8a | 2984 | u32 ap_legacy_rates; |
13935e2c | 2985 | u8 ap_mcs_rates[16]; |
3a980d0a LB |
2986 | int rc; |
2987 | ||
c3cbbe8a | 2988 | if (mwl8k_fw_lock(hw)) |
3a980d0a | 2989 | return; |
a66098da | 2990 | |
c3cbbe8a LB |
2991 | /* |
2992 | * No need to capture a beacon if we're no longer associated. | |
2993 | */ | |
2994 | if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc) | |
2995 | priv->capture_beacon = false; | |
3a980d0a | 2996 | |
c3cbbe8a | 2997 | /* |
13935e2c | 2998 | * Get the AP's legacy and MCS rates. |
c3cbbe8a LB |
2999 | */ |
3000 | ap_legacy_rates = 0; | |
7dc6a7a7 | 3001 | if (vif->bss_conf.assoc) { |
c6e96010 | 3002 | struct ieee80211_sta *ap; |
c6e96010 | 3003 | rcu_read_lock(); |
c6e96010 | 3004 | |
c3cbbe8a LB |
3005 | ap = ieee80211_find_sta(vif, vif->bss_conf.bssid); |
3006 | if (ap == NULL) { | |
3007 | rcu_read_unlock(); | |
c6e96010 | 3008 | goto out; |
c3cbbe8a LB |
3009 | } |
3010 | ||
3011 | ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ]; | |
13935e2c | 3012 | memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16); |
c3cbbe8a LB |
3013 | |
3014 | rcu_read_unlock(); | |
3015 | } | |
c6e96010 | 3016 | |
c3cbbe8a | 3017 | if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) { |
13935e2c | 3018 | rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates); |
3a980d0a LB |
3019 | if (rc) |
3020 | goto out; | |
a66098da | 3021 | |
b71ed2c6 | 3022 | rc = mwl8k_cmd_use_fixed_rate_sta(hw); |
3a980d0a LB |
3023 | if (rc) |
3024 | goto out; | |
c3cbbe8a | 3025 | } |
a66098da | 3026 | |
c3cbbe8a | 3027 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
7dc6a7a7 LB |
3028 | rc = mwl8k_set_radio_preamble(hw, |
3029 | vif->bss_conf.use_short_preamble); | |
3a980d0a LB |
3030 | if (rc) |
3031 | goto out; | |
c3cbbe8a | 3032 | } |
a66098da | 3033 | |
c3cbbe8a | 3034 | if (changed & BSS_CHANGED_ERP_SLOT) { |
7dc6a7a7 | 3035 | rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot); |
3a980d0a LB |
3036 | if (rc) |
3037 | goto out; | |
c3cbbe8a | 3038 | } |
a66098da | 3039 | |
c3cbbe8a LB |
3040 | if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) || |
3041 | (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) { | |
3042 | rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates); | |
3a980d0a LB |
3043 | if (rc) |
3044 | goto out; | |
c3cbbe8a | 3045 | } |
a66098da | 3046 | |
c3cbbe8a LB |
3047 | if (vif->bss_conf.assoc && |
3048 | (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) { | |
a66098da LB |
3049 | /* |
3050 | * Finalize the join. Tell rx handler to process | |
3051 | * next beacon from our BSSID. | |
3052 | */ | |
0a11dfc3 | 3053 | memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN); |
a66098da | 3054 | priv->capture_beacon = true; |
a66098da LB |
3055 | } |
3056 | ||
3a980d0a LB |
3057 | out: |
3058 | mwl8k_fw_unlock(hw); | |
a66098da LB |
3059 | } |
3060 | ||
e81cd2d6 LB |
3061 | static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, |
3062 | int mc_count, struct dev_addr_list *mclist) | |
3063 | { | |
3064 | struct mwl8k_cmd_pkt *cmd; | |
3065 | ||
447ced07 LB |
3066 | /* |
3067 | * Synthesize and return a command packet that programs the | |
3068 | * hardware multicast address filter. At this point we don't | |
3069 | * know whether FIF_ALLMULTI is being requested, but if it is, | |
3070 | * we'll end up throwing this packet away and creating a new | |
3071 | * one in mwl8k_configure_filter(). | |
3072 | */ | |
3073 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); | |
e81cd2d6 LB |
3074 | |
3075 | return (unsigned long)cmd; | |
3076 | } | |
3077 | ||
a43c49a8 LB |
3078 | static int |
3079 | mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, | |
3080 | unsigned int changed_flags, | |
3081 | unsigned int *total_flags) | |
3082 | { | |
3083 | struct mwl8k_priv *priv = hw->priv; | |
3084 | ||
3085 | /* | |
3086 | * Hardware sniffer mode is mutually exclusive with STA | |
3087 | * operation, so refuse to enable sniffer mode if a STA | |
3088 | * interface is active. | |
3089 | */ | |
3090 | if (priv->vif != NULL) { | |
3091 | if (net_ratelimit()) | |
3092 | printk(KERN_INFO "%s: not enabling sniffer " | |
3093 | "mode because STA interface is active\n", | |
3094 | wiphy_name(hw->wiphy)); | |
3095 | return 0; | |
3096 | } | |
3097 | ||
3098 | if (!priv->sniffer_enabled) { | |
55489b6e | 3099 | if (mwl8k_cmd_enable_sniffer(hw, 1)) |
a43c49a8 LB |
3100 | return 0; |
3101 | priv->sniffer_enabled = true; | |
3102 | } | |
3103 | ||
3104 | *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | | |
3105 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | | |
3106 | FIF_OTHER_BSS; | |
3107 | ||
3108 | return 1; | |
3109 | } | |
3110 | ||
e6935ea1 LB |
3111 | static void mwl8k_configure_filter(struct ieee80211_hw *hw, |
3112 | unsigned int changed_flags, | |
3113 | unsigned int *total_flags, | |
3114 | u64 multicast) | |
3115 | { | |
3116 | struct mwl8k_priv *priv = hw->priv; | |
a43c49a8 LB |
3117 | struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; |
3118 | ||
c0adae2c LB |
3119 | /* |
3120 | * AP firmware doesn't allow fine-grained control over | |
3121 | * the receive filter. | |
3122 | */ | |
3123 | if (priv->ap_fw) { | |
3124 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; | |
3125 | kfree(cmd); | |
3126 | return; | |
3127 | } | |
3128 | ||
a43c49a8 LB |
3129 | /* |
3130 | * Enable hardware sniffer mode if FIF_CONTROL or | |
3131 | * FIF_OTHER_BSS is requested. | |
3132 | */ | |
3133 | if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && | |
3134 | mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { | |
3135 | kfree(cmd); | |
3136 | return; | |
3137 | } | |
a66098da | 3138 | |
e6935ea1 | 3139 | /* Clear unsupported feature flags */ |
447ced07 | 3140 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; |
a66098da | 3141 | |
90852f7a LB |
3142 | if (mwl8k_fw_lock(hw)) { |
3143 | kfree(cmd); | |
e6935ea1 | 3144 | return; |
90852f7a | 3145 | } |
a66098da | 3146 | |
a43c49a8 | 3147 | if (priv->sniffer_enabled) { |
55489b6e | 3148 | mwl8k_cmd_enable_sniffer(hw, 0); |
a43c49a8 LB |
3149 | priv->sniffer_enabled = false; |
3150 | } | |
3151 | ||
e6935ea1 | 3152 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
77165d88 LB |
3153 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { |
3154 | /* | |
3155 | * Disable the BSS filter. | |
3156 | */ | |
e6935ea1 | 3157 | mwl8k_cmd_set_pre_scan(hw); |
77165d88 | 3158 | } else { |
0a11dfc3 | 3159 | const u8 *bssid; |
a94cc97e | 3160 | |
77165d88 LB |
3161 | /* |
3162 | * Enable the BSS filter. | |
3163 | * | |
3164 | * If there is an active STA interface, use that | |
3165 | * interface's BSSID, otherwise use a dummy one | |
3166 | * (where the OUI part needs to be nonzero for | |
3167 | * the BSSID to be accepted by POST_SCAN). | |
3168 | */ | |
3169 | bssid = "\x01\x00\x00\x00\x00\x00"; | |
a94cc97e | 3170 | if (priv->vif != NULL) |
0a11dfc3 | 3171 | bssid = priv->vif->bss_conf.bssid; |
a94cc97e | 3172 | |
e6935ea1 | 3173 | mwl8k_cmd_set_post_scan(hw, bssid); |
a66098da LB |
3174 | } |
3175 | } | |
3176 | ||
447ced07 LB |
3177 | /* |
3178 | * If FIF_ALLMULTI is being requested, throw away the command | |
3179 | * packet that ->prepare_multicast() built and replace it with | |
3180 | * a command packet that enables reception of all multicast | |
3181 | * packets. | |
3182 | */ | |
3183 | if (*total_flags & FIF_ALLMULTI) { | |
3184 | kfree(cmd); | |
3185 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); | |
3186 | } | |
3187 | ||
3188 | if (cmd != NULL) { | |
3189 | mwl8k_post_cmd(hw, cmd); | |
3190 | kfree(cmd); | |
e6935ea1 | 3191 | } |
a66098da | 3192 | |
e6935ea1 | 3193 | mwl8k_fw_unlock(hw); |
a66098da LB |
3194 | } |
3195 | ||
a66098da LB |
3196 | static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
3197 | { | |
c2c2b12a | 3198 | return mwl8k_cmd_set_rts_threshold(hw, value); |
a66098da LB |
3199 | } |
3200 | ||
bbfd9128 LB |
3201 | struct mwl8k_sta_notify_item |
3202 | { | |
3203 | struct list_head list; | |
3204 | struct ieee80211_vif *vif; | |
3205 | enum sta_notify_cmd cmd; | |
13935e2c | 3206 | struct ieee80211_sta sta; |
bbfd9128 LB |
3207 | }; |
3208 | ||
3209 | static void mwl8k_sta_notify_worker(struct work_struct *work) | |
3210 | { | |
3211 | struct mwl8k_priv *priv = | |
3212 | container_of(work, struct mwl8k_priv, sta_notify_worker); | |
a680400e | 3213 | struct ieee80211_hw *hw = priv->hw; |
bbfd9128 LB |
3214 | |
3215 | spin_lock_bh(&priv->sta_notify_list_lock); | |
3216 | while (!list_empty(&priv->sta_notify_list)) { | |
3217 | struct mwl8k_sta_notify_item *s; | |
bbfd9128 LB |
3218 | |
3219 | s = list_entry(priv->sta_notify_list.next, | |
3220 | struct mwl8k_sta_notify_item, list); | |
3221 | list_del(&s->list); | |
3222 | ||
3223 | spin_unlock_bh(&priv->sta_notify_list_lock); | |
3224 | ||
a680400e LB |
3225 | if (s->cmd == STA_NOTIFY_ADD) { |
3226 | int rc; | |
3227 | ||
13935e2c | 3228 | rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta); |
a680400e LB |
3229 | if (rc >= 0) { |
3230 | struct ieee80211_sta *sta; | |
3231 | ||
3232 | rcu_read_lock(); | |
13935e2c | 3233 | sta = ieee80211_find_sta(s->vif, s->sta.addr); |
a680400e LB |
3234 | if (sta != NULL) |
3235 | MWL8K_STA(sta)->peer_id = rc; | |
3236 | rcu_read_unlock(); | |
3237 | } | |
3238 | } else { | |
13935e2c | 3239 | mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr); |
a680400e | 3240 | } |
bbfd9128 LB |
3241 | |
3242 | kfree(s); | |
3243 | ||
3244 | spin_lock_bh(&priv->sta_notify_list_lock); | |
3245 | } | |
3246 | spin_unlock_bh(&priv->sta_notify_list_lock); | |
3247 | } | |
3248 | ||
3249 | static void | |
3250 | mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3251 | enum sta_notify_cmd cmd, struct ieee80211_sta *sta) | |
3252 | { | |
3253 | struct mwl8k_priv *priv = hw->priv; | |
3254 | struct mwl8k_sta_notify_item *s; | |
3255 | ||
3256 | if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE) | |
3257 | return; | |
3258 | ||
3259 | s = kmalloc(sizeof(*s), GFP_ATOMIC); | |
3260 | if (s != NULL) { | |
3261 | s->vif = vif; | |
3262 | s->cmd = cmd; | |
13935e2c | 3263 | s->sta = *sta; |
bbfd9128 LB |
3264 | |
3265 | spin_lock(&priv->sta_notify_list_lock); | |
3266 | list_add_tail(&s->list, &priv->sta_notify_list); | |
3267 | spin_unlock(&priv->sta_notify_list_lock); | |
3268 | ||
3269 | ieee80211_queue_work(hw, &priv->sta_notify_worker); | |
3270 | } | |
3271 | } | |
3272 | ||
a66098da LB |
3273 | static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3274 | const struct ieee80211_tx_queue_params *params) | |
3275 | { | |
3e4f542c | 3276 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 3277 | int rc; |
a66098da | 3278 | |
3e4f542c LB |
3279 | rc = mwl8k_fw_lock(hw); |
3280 | if (!rc) { | |
3281 | if (!priv->wmm_enabled) | |
55489b6e | 3282 | rc = mwl8k_cmd_set_wmm_mode(hw, 1); |
a66098da | 3283 | |
3e4f542c | 3284 | if (!rc) |
55489b6e LB |
3285 | rc = mwl8k_cmd_set_edca_params(hw, queue, |
3286 | params->cw_min, | |
3287 | params->cw_max, | |
3288 | params->aifs, | |
3289 | params->txop); | |
3e4f542c LB |
3290 | |
3291 | mwl8k_fw_unlock(hw); | |
a66098da | 3292 | } |
3e4f542c | 3293 | |
a66098da LB |
3294 | return rc; |
3295 | } | |
3296 | ||
3297 | static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, | |
3298 | struct ieee80211_tx_queue_stats *stats) | |
3299 | { | |
3300 | struct mwl8k_priv *priv = hw->priv; | |
3301 | struct mwl8k_tx_queue *txq; | |
3302 | int index; | |
3303 | ||
3304 | spin_lock_bh(&priv->tx_lock); | |
3305 | for (index = 0; index < MWL8K_TX_QUEUES; index++) { | |
3306 | txq = priv->txq + index; | |
45eb400d | 3307 | memcpy(&stats[index], &txq->stats, |
a66098da LB |
3308 | sizeof(struct ieee80211_tx_queue_stats)); |
3309 | } | |
3310 | spin_unlock_bh(&priv->tx_lock); | |
a66098da | 3311 | |
954ef509 | 3312 | return 0; |
a66098da LB |
3313 | } |
3314 | ||
3315 | static int mwl8k_get_stats(struct ieee80211_hw *hw, | |
3316 | struct ieee80211_low_level_stats *stats) | |
3317 | { | |
55489b6e | 3318 | return mwl8k_cmd_get_stat(hw, stats); |
a66098da LB |
3319 | } |
3320 | ||
a2292d83 LB |
3321 | static int |
3322 | mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3323 | enum ieee80211_ampdu_mlme_action action, | |
3324 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) | |
3325 | { | |
3326 | switch (action) { | |
3327 | case IEEE80211_AMPDU_RX_START: | |
3328 | case IEEE80211_AMPDU_RX_STOP: | |
3329 | if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION)) | |
3330 | return -ENOTSUPP; | |
3331 | return 0; | |
3332 | default: | |
3333 | return -ENOTSUPP; | |
3334 | } | |
3335 | } | |
3336 | ||
a66098da LB |
3337 | static const struct ieee80211_ops mwl8k_ops = { |
3338 | .tx = mwl8k_tx, | |
3339 | .start = mwl8k_start, | |
3340 | .stop = mwl8k_stop, | |
3341 | .add_interface = mwl8k_add_interface, | |
3342 | .remove_interface = mwl8k_remove_interface, | |
3343 | .config = mwl8k_config, | |
a66098da | 3344 | .bss_info_changed = mwl8k_bss_info_changed, |
3ac64bee | 3345 | .prepare_multicast = mwl8k_prepare_multicast, |
a66098da LB |
3346 | .configure_filter = mwl8k_configure_filter, |
3347 | .set_rts_threshold = mwl8k_set_rts_threshold, | |
bbfd9128 | 3348 | .sta_notify = mwl8k_sta_notify, |
a66098da LB |
3349 | .conf_tx = mwl8k_conf_tx, |
3350 | .get_tx_stats = mwl8k_get_tx_stats, | |
3351 | .get_stats = mwl8k_get_stats, | |
a2292d83 | 3352 | .ampdu_action = mwl8k_ampdu_action, |
a66098da LB |
3353 | }; |
3354 | ||
3355 | static void mwl8k_tx_reclaim_handler(unsigned long data) | |
3356 | { | |
3357 | int i; | |
3358 | struct ieee80211_hw *hw = (struct ieee80211_hw *) data; | |
3359 | struct mwl8k_priv *priv = hw->priv; | |
3360 | ||
3361 | spin_lock_bh(&priv->tx_lock); | |
3362 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3363 | mwl8k_txq_reclaim(hw, i, 0); | |
3364 | ||
88de754a | 3365 | if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { |
ce9e2e1b LB |
3366 | complete(priv->tx_wait); |
3367 | priv->tx_wait = NULL; | |
a66098da LB |
3368 | } |
3369 | spin_unlock_bh(&priv->tx_lock); | |
3370 | } | |
3371 | ||
3372 | static void mwl8k_finalize_join_worker(struct work_struct *work) | |
3373 | { | |
3374 | struct mwl8k_priv *priv = | |
3375 | container_of(work, struct mwl8k_priv, finalize_join_worker); | |
3376 | struct sk_buff *skb = priv->beacon_skb; | |
a66098da | 3377 | |
7dc6a7a7 LB |
3378 | mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, |
3379 | priv->vif->bss_conf.dtim_period); | |
a66098da LB |
3380 | dev_kfree_skb(skb); |
3381 | ||
3382 | priv->beacon_skb = NULL; | |
3383 | } | |
3384 | ||
bcb628d5 | 3385 | enum { |
9e1b17ea LB |
3386 | MWL8363 = 0, |
3387 | MWL8687, | |
bcb628d5 | 3388 | MWL8366, |
6f6d1e9a LB |
3389 | }; |
3390 | ||
bcb628d5 | 3391 | static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { |
9e1b17ea LB |
3392 | [MWL8363] = { |
3393 | .part_name = "88w8363", | |
3394 | .helper_image = "mwl8k/helper_8363.fw", | |
3395 | .fw_image = "mwl8k/fmimage_8363.fw", | |
3396 | }, | |
49eb691c | 3397 | [MWL8687] = { |
bcb628d5 JL |
3398 | .part_name = "88w8687", |
3399 | .helper_image = "mwl8k/helper_8687.fw", | |
3400 | .fw_image = "mwl8k/fmimage_8687.fw", | |
bcb628d5 | 3401 | }, |
49eb691c | 3402 | [MWL8366] = { |
bcb628d5 JL |
3403 | .part_name = "88w8366", |
3404 | .helper_image = "mwl8k/helper_8366.fw", | |
3405 | .fw_image = "mwl8k/fmimage_8366.fw", | |
89a91f4f | 3406 | .ap_rxd_ops = &rxd_8366_ap_ops, |
bcb628d5 | 3407 | }, |
45a390dd LB |
3408 | }; |
3409 | ||
3410 | static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { | |
9e1b17ea LB |
3411 | { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, }, |
3412 | { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, }, | |
bcb628d5 JL |
3413 | { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, |
3414 | { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, | |
3415 | { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, | |
3416 | { }, | |
45a390dd LB |
3417 | }; |
3418 | MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); | |
3419 | ||
a66098da LB |
3420 | static int __devinit mwl8k_probe(struct pci_dev *pdev, |
3421 | const struct pci_device_id *id) | |
3422 | { | |
2aa7b01f | 3423 | static int printed_version = 0; |
a66098da LB |
3424 | struct ieee80211_hw *hw; |
3425 | struct mwl8k_priv *priv; | |
a66098da LB |
3426 | int rc; |
3427 | int i; | |
2aa7b01f LB |
3428 | |
3429 | if (!printed_version) { | |
3430 | printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); | |
3431 | printed_version = 1; | |
3432 | } | |
a66098da | 3433 | |
be695fc4 | 3434 | |
a66098da LB |
3435 | rc = pci_enable_device(pdev); |
3436 | if (rc) { | |
3437 | printk(KERN_ERR "%s: Cannot enable new PCI device\n", | |
3438 | MWL8K_NAME); | |
3439 | return rc; | |
3440 | } | |
3441 | ||
3442 | rc = pci_request_regions(pdev, MWL8K_NAME); | |
3443 | if (rc) { | |
3444 | printk(KERN_ERR "%s: Cannot obtain PCI resources\n", | |
3445 | MWL8K_NAME); | |
3db95e50 | 3446 | goto err_disable_device; |
a66098da LB |
3447 | } |
3448 | ||
3449 | pci_set_master(pdev); | |
3450 | ||
be695fc4 | 3451 | |
a66098da LB |
3452 | hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); |
3453 | if (hw == NULL) { | |
3454 | printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); | |
3455 | rc = -ENOMEM; | |
3456 | goto err_free_reg; | |
3457 | } | |
3458 | ||
be695fc4 LB |
3459 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3460 | pci_set_drvdata(pdev, hw); | |
3461 | ||
a66098da LB |
3462 | priv = hw->priv; |
3463 | priv->hw = hw; | |
3464 | priv->pdev = pdev; | |
bcb628d5 | 3465 | priv->device_info = &mwl8k_info_tbl[id->driver_data]; |
a66098da | 3466 | |
a66098da | 3467 | |
5b9482dd LB |
3468 | priv->sram = pci_iomap(pdev, 0, 0x10000); |
3469 | if (priv->sram == NULL) { | |
3470 | printk(KERN_ERR "%s: Cannot map device SRAM\n", | |
c2c357ce | 3471 | wiphy_name(hw->wiphy)); |
a66098da LB |
3472 | goto err_iounmap; |
3473 | } | |
3474 | ||
5b9482dd LB |
3475 | /* |
3476 | * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. | |
3477 | * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. | |
3478 | */ | |
3479 | priv->regs = pci_iomap(pdev, 1, 0x10000); | |
3480 | if (priv->regs == NULL) { | |
3481 | priv->regs = pci_iomap(pdev, 2, 0x10000); | |
3482 | if (priv->regs == NULL) { | |
3483 | printk(KERN_ERR "%s: Cannot map device registers\n", | |
3484 | wiphy_name(hw->wiphy)); | |
3485 | goto err_iounmap; | |
3486 | } | |
3487 | } | |
3488 | ||
be695fc4 LB |
3489 | |
3490 | /* Reset firmware and hardware */ | |
3491 | mwl8k_hw_reset(priv); | |
3492 | ||
3493 | /* Ask userland hotplug daemon for the device firmware */ | |
3494 | rc = mwl8k_request_firmware(priv); | |
3495 | if (rc) { | |
3496 | printk(KERN_ERR "%s: Firmware files not found\n", | |
3497 | wiphy_name(hw->wiphy)); | |
3498 | goto err_stop_firmware; | |
3499 | } | |
3500 | ||
3501 | /* Load firmware into hardware */ | |
3502 | rc = mwl8k_load_firmware(hw); | |
3503 | if (rc) { | |
3504 | printk(KERN_ERR "%s: Cannot start firmware\n", | |
3505 | wiphy_name(hw->wiphy)); | |
3506 | goto err_stop_firmware; | |
3507 | } | |
3508 | ||
3509 | /* Reclaim memory once firmware is successfully loaded */ | |
3510 | mwl8k_release_firmware(priv); | |
3511 | ||
3512 | ||
91942230 | 3513 | if (priv->ap_fw) { |
89a91f4f | 3514 | priv->rxd_ops = priv->device_info->ap_rxd_ops; |
91942230 LB |
3515 | if (priv->rxd_ops == NULL) { |
3516 | printk(KERN_ERR "%s: Driver does not have AP " | |
3517 | "firmware image support for this hardware\n", | |
3518 | wiphy_name(hw->wiphy)); | |
3519 | goto err_stop_firmware; | |
3520 | } | |
3521 | } else { | |
89a91f4f | 3522 | priv->rxd_ops = &rxd_sta_ops; |
91942230 | 3523 | } |
be695fc4 LB |
3524 | |
3525 | priv->sniffer_enabled = false; | |
3526 | priv->wmm_enabled = false; | |
3527 | priv->pending_tx_pkts = 0; | |
3528 | ||
3529 | ||
a66098da LB |
3530 | memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); |
3531 | priv->band.band = IEEE80211_BAND_2GHZ; | |
3532 | priv->band.channels = priv->channels; | |
3533 | priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); | |
3534 | priv->band.bitrates = priv->rates; | |
3535 | priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); | |
3536 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
3537 | ||
3538 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); | |
3539 | memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); | |
3540 | ||
3541 | /* | |
3542 | * Extra headroom is the size of the required DMA header | |
3543 | * minus the size of the smallest 802.11 frame (CTS frame). | |
3544 | */ | |
3545 | hw->extra_tx_headroom = | |
3546 | sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); | |
3547 | ||
3548 | hw->channel_change_time = 10; | |
3549 | ||
3550 | hw->queues = MWL8K_TX_QUEUES; | |
3551 | ||
a66098da | 3552 | /* Set rssi and noise values to dBm */ |
ce9e2e1b | 3553 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; |
a66098da | 3554 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
a680400e | 3555 | hw->sta_data_size = sizeof(struct mwl8k_sta); |
a66098da LB |
3556 | priv->vif = NULL; |
3557 | ||
3558 | /* Set default radio state and preamble */ | |
c46563b7 | 3559 | priv->radio_on = 0; |
68ce3884 | 3560 | priv->radio_short_preamble = 0; |
a66098da | 3561 | |
bbfd9128 LB |
3562 | /* Station database handling */ |
3563 | INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker); | |
3564 | spin_lock_init(&priv->sta_notify_list_lock); | |
3565 | INIT_LIST_HEAD(&priv->sta_notify_list); | |
3566 | ||
a66098da LB |
3567 | /* Finalize join worker */ |
3568 | INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); | |
3569 | ||
3570 | /* TX reclaim tasklet */ | |
3571 | tasklet_init(&priv->tx_reclaim_task, | |
3572 | mwl8k_tx_reclaim_handler, (unsigned long)hw); | |
3573 | tasklet_disable(&priv->tx_reclaim_task); | |
3574 | ||
a66098da LB |
3575 | /* Power management cookie */ |
3576 | priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); | |
3577 | if (priv->cookie == NULL) | |
be695fc4 | 3578 | goto err_stop_firmware; |
a66098da LB |
3579 | |
3580 | rc = mwl8k_rxq_init(hw, 0); | |
3581 | if (rc) | |
be695fc4 | 3582 | goto err_free_cookie; |
a66098da LB |
3583 | rxq_refill(hw, 0, INT_MAX); |
3584 | ||
618952a7 LB |
3585 | mutex_init(&priv->fw_mutex); |
3586 | priv->fw_mutex_owner = NULL; | |
3587 | priv->fw_mutex_depth = 0; | |
618952a7 LB |
3588 | priv->hostcmd_wait = NULL; |
3589 | ||
a66098da LB |
3590 | spin_lock_init(&priv->tx_lock); |
3591 | ||
88de754a LB |
3592 | priv->tx_wait = NULL; |
3593 | ||
a66098da LB |
3594 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { |
3595 | rc = mwl8k_txq_init(hw, i); | |
3596 | if (rc) | |
3597 | goto err_free_queues; | |
3598 | } | |
3599 | ||
3600 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
c23b5a69 | 3601 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3602 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); |
3603 | iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); | |
3604 | ||
a0607fd3 | 3605 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
3606 | IRQF_SHARED, MWL8K_NAME, hw); |
3607 | if (rc) { | |
3608 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 3609 | wiphy_name(hw->wiphy)); |
a66098da LB |
3610 | goto err_free_queues; |
3611 | } | |
3612 | ||
a66098da LB |
3613 | /* |
3614 | * Temporarily enable interrupts. Initial firmware host | |
c2c2b12a | 3615 | * commands use interrupts and avoid polling. Disable |
a66098da LB |
3616 | * interrupts when done. |
3617 | */ | |
c23b5a69 | 3618 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3619 | |
3620 | /* Get config data, mac addrs etc */ | |
42fba21d LB |
3621 | if (priv->ap_fw) { |
3622 | rc = mwl8k_cmd_get_hw_spec_ap(hw); | |
3623 | if (!rc) | |
3624 | rc = mwl8k_cmd_set_hw_spec(hw); | |
3625 | } else { | |
3626 | rc = mwl8k_cmd_get_hw_spec_sta(hw); | |
89a91f4f LB |
3627 | |
3628 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
42fba21d | 3629 | } |
a66098da | 3630 | if (rc) { |
c2c357ce LB |
3631 | printk(KERN_ERR "%s: Cannot initialise firmware\n", |
3632 | wiphy_name(hw->wiphy)); | |
be695fc4 | 3633 | goto err_free_irq; |
a66098da LB |
3634 | } |
3635 | ||
3636 | /* Turn radio off */ | |
55489b6e | 3637 | rc = mwl8k_cmd_radio_disable(hw); |
a66098da | 3638 | if (rc) { |
c2c357ce | 3639 | printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); |
be695fc4 | 3640 | goto err_free_irq; |
a66098da LB |
3641 | } |
3642 | ||
32060e1b | 3643 | /* Clear MAC address */ |
55489b6e | 3644 | rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b LB |
3645 | if (rc) { |
3646 | printk(KERN_ERR "%s: Cannot clear MAC address\n", | |
3647 | wiphy_name(hw->wiphy)); | |
be695fc4 | 3648 | goto err_free_irq; |
32060e1b LB |
3649 | } |
3650 | ||
a66098da | 3651 | /* Disable interrupts */ |
a66098da | 3652 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3653 | free_irq(priv->pdev->irq, hw); |
3654 | ||
3655 | rc = ieee80211_register_hw(hw); | |
3656 | if (rc) { | |
c2c357ce LB |
3657 | printk(KERN_ERR "%s: Cannot register device\n", |
3658 | wiphy_name(hw->wiphy)); | |
153458ff | 3659 | goto err_free_queues; |
a66098da LB |
3660 | } |
3661 | ||
eae74e65 | 3662 | printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", |
a74b295e | 3663 | wiphy_name(hw->wiphy), priv->device_info->part_name, |
45a390dd | 3664 | priv->hw_rev, hw->wiphy->perm_addr, |
eae74e65 | 3665 | priv->ap_fw ? "AP" : "STA", |
2aa7b01f LB |
3666 | (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, |
3667 | (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); | |
a66098da LB |
3668 | |
3669 | return 0; | |
3670 | ||
a66098da | 3671 | err_free_irq: |
a66098da | 3672 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3673 | free_irq(priv->pdev->irq, hw); |
3674 | ||
3675 | err_free_queues: | |
3676 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3677 | mwl8k_txq_deinit(hw, i); | |
3678 | mwl8k_rxq_deinit(hw, 0); | |
3679 | ||
be695fc4 | 3680 | err_free_cookie: |
a66098da LB |
3681 | if (priv->cookie != NULL) |
3682 | pci_free_consistent(priv->pdev, 4, | |
3683 | priv->cookie, priv->cookie_dma); | |
3684 | ||
be695fc4 LB |
3685 | err_stop_firmware: |
3686 | mwl8k_hw_reset(priv); | |
3687 | mwl8k_release_firmware(priv); | |
3688 | ||
3689 | err_iounmap: | |
a66098da LB |
3690 | if (priv->regs != NULL) |
3691 | pci_iounmap(pdev, priv->regs); | |
3692 | ||
5b9482dd LB |
3693 | if (priv->sram != NULL) |
3694 | pci_iounmap(pdev, priv->sram); | |
3695 | ||
a66098da LB |
3696 | pci_set_drvdata(pdev, NULL); |
3697 | ieee80211_free_hw(hw); | |
3698 | ||
3699 | err_free_reg: | |
3700 | pci_release_regions(pdev); | |
3db95e50 LB |
3701 | |
3702 | err_disable_device: | |
a66098da LB |
3703 | pci_disable_device(pdev); |
3704 | ||
3705 | return rc; | |
3706 | } | |
3707 | ||
230f7af0 | 3708 | static void __devexit mwl8k_shutdown(struct pci_dev *pdev) |
a66098da LB |
3709 | { |
3710 | printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); | |
3711 | } | |
3712 | ||
230f7af0 | 3713 | static void __devexit mwl8k_remove(struct pci_dev *pdev) |
a66098da LB |
3714 | { |
3715 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
3716 | struct mwl8k_priv *priv; | |
3717 | int i; | |
3718 | ||
3719 | if (hw == NULL) | |
3720 | return; | |
3721 | priv = hw->priv; | |
3722 | ||
3723 | ieee80211_stop_queues(hw); | |
3724 | ||
60aa569f LB |
3725 | ieee80211_unregister_hw(hw); |
3726 | ||
a66098da LB |
3727 | /* Remove tx reclaim tasklet */ |
3728 | tasklet_kill(&priv->tx_reclaim_task); | |
3729 | ||
a66098da LB |
3730 | /* Stop hardware */ |
3731 | mwl8k_hw_reset(priv); | |
3732 | ||
3733 | /* Return all skbs to mac80211 */ | |
3734 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3735 | mwl8k_txq_reclaim(hw, i, 1); | |
3736 | ||
a66098da LB |
3737 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
3738 | mwl8k_txq_deinit(hw, i); | |
3739 | ||
3740 | mwl8k_rxq_deinit(hw, 0); | |
3741 | ||
c2c357ce | 3742 | pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); |
a66098da LB |
3743 | |
3744 | pci_iounmap(pdev, priv->regs); | |
5b9482dd | 3745 | pci_iounmap(pdev, priv->sram); |
a66098da LB |
3746 | pci_set_drvdata(pdev, NULL); |
3747 | ieee80211_free_hw(hw); | |
3748 | pci_release_regions(pdev); | |
3749 | pci_disable_device(pdev); | |
3750 | } | |
3751 | ||
3752 | static struct pci_driver mwl8k_driver = { | |
3753 | .name = MWL8K_NAME, | |
45a390dd | 3754 | .id_table = mwl8k_pci_id_table, |
a66098da LB |
3755 | .probe = mwl8k_probe, |
3756 | .remove = __devexit_p(mwl8k_remove), | |
3757 | .shutdown = __devexit_p(mwl8k_shutdown), | |
3758 | }; | |
3759 | ||
3760 | static int __init mwl8k_init(void) | |
3761 | { | |
3762 | return pci_register_driver(&mwl8k_driver); | |
3763 | } | |
3764 | ||
3765 | static void __exit mwl8k_exit(void) | |
3766 | { | |
3767 | pci_unregister_driver(&mwl8k_driver); | |
3768 | } | |
3769 | ||
3770 | module_init(mwl8k_init); | |
3771 | module_exit(mwl8k_exit); | |
c2c357ce LB |
3772 | |
3773 | MODULE_DESCRIPTION(MWL8K_DESC); | |
3774 | MODULE_VERSION(MWL8K_VERSION); | |
3775 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); | |
3776 | MODULE_LICENSE("GPL"); |