]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/wireless/mwl8k.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mwl8k: fix multicast address filter programming
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/completion.h>
20#include <linux/etherdevice.h>
21#include <net/mac80211.h>
22#include <linux/moduleparam.h>
23#include <linux/firmware.h>
24#include <linux/workqueue.h>
25
26#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27#define MWL8K_NAME KBUILD_MODNAME
a145d575 28#define MWL8K_VERSION "0.10"
a66098da 29
a66098da
LB		 30static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
31 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
32 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
33 { }
34};
35MODULE_DEVICE_TABLE(pci, mwl8k_table);
36
a66098da
LB		 37/* Register definitions */
38#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 39#define MWL8K_MODE_STA 0x0000005a
40#define MWL8K_MODE_AP 0x000000a5
a66098da 41#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 42#define MWL8K_FWSTA_READY 0xf0f1f2f4
43#define MWL8K_FWAP_READY 0xf1f2f4a5
44#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 45#define MWL8K_HIU_SCRATCH 0x00000c40
46
47/* Host->device communications */
48#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
49#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
50#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
51#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
52#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 53#define MWL8K_H2A_INT_DUMMY (1 << 20)
54#define MWL8K_H2A_INT_RESET (1 << 15)
55#define MWL8K_H2A_INT_DOORBELL (1 << 1)
56#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 57
58/* Device->host communications */
59#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
60#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
61#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
62#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
63#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 64#define MWL8K_A2H_INT_DUMMY (1 << 20)
65#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
66#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
67#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
68#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
69#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
70#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
71#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
72#define MWL8K_A2H_INT_RX_READY (1 << 1)
73#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 74
75#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
76 MWL8K_A2H_INT_CHNL_SWITCHED | \
77 MWL8K_A2H_INT_QUEUE_EMPTY | \
78 MWL8K_A2H_INT_RADAR_DETECT | \
79 MWL8K_A2H_INT_RADIO_ON | \
80 MWL8K_A2H_INT_RADIO_OFF | \
81 MWL8K_A2H_INT_MAC_EVENT | \
82 MWL8K_A2H_INT_OPC_DONE | \
83 MWL8K_A2H_INT_RX_READY | \
84 MWL8K_A2H_INT_TX_DONE)
85
86/* WME stream classes */
87#define WME_AC_BE 0 /* best effort */
88#define WME_AC_BK 1 /* background */
89#define WME_AC_VI 2 /* video */
90#define WME_AC_VO 3 /* voice */
91
92#define MWL8K_RX_QUEUES 1
93#define MWL8K_TX_QUEUES 4
94
95struct mwl8k_rx_queue {
96 int rx_desc_count;
97
98 /* hw receives here */
99 int rx_head;
100
101 /* refill descs here */
102 int rx_tail;
103
104 struct mwl8k_rx_desc *rx_desc_area;
105 dma_addr_t rx_desc_dma;
106 struct sk_buff **rx_skb;
107};
108
a66098da
LB		 109struct mwl8k_tx_queue {
110 /* hw transmits here */
111 int tx_head;
112
113 /* sw appends here */
114 int tx_tail;
115
116 struct ieee80211_tx_queue_stats tx_stats;
117 struct mwl8k_tx_desc *tx_desc_area;
118 dma_addr_t tx_desc_dma;
76266b2a 119 struct sk_buff **tx_skb;
a66098da
LB		 120};
121
122/* Pointers to the firmware data and meta information about it. */
123struct mwl8k_firmware {
124 /* Microcode */
125 struct firmware *ucode;
126
127 /* Boot helper code */
128 struct firmware *helper;
129};
130
131struct mwl8k_priv {
132 void __iomem *regs;
133 struct ieee80211_hw *hw;
134
135 struct pci_dev *pdev;
a66098da
LB		 136
137 /* firmware files and meta data */
138 struct mwl8k_firmware fw;
139 u32 part_num;
140
618952a7
LB		 141 /* firmware access */
142 struct mutex fw_mutex;
143 struct task_struct *fw_mutex_owner;
144 int fw_mutex_depth;
618952a7
LB		 145 struct completion *hostcmd_wait;
146
a66098da
LB		 147 /* lock held over TX and TX reap */
148 spinlock_t tx_lock;
a66098da 149
88de754a
LB		 150 /* TX quiesce completion, protected by fw_mutex and tx_lock */
151 struct completion *tx_wait;
152
a66098da 153 struct ieee80211_vif *vif;
a66098da
LB		 154
155 struct ieee80211_channel *current_channel;
156
157 /* power management status cookie from firmware */
158 u32 *cookie;
159 dma_addr_t cookie_dma;
160
161 u16 num_mcaddrs;
a66098da 162 u8 hw_rev;
2aa7b01f 163 u32 fw_rev;
a66098da
LB		 164
165 /*
166 * Running count of TX packets in flight, to avoid
167 * iterating over the transmit rings each time.
168 */
169 int pending_tx_pkts;
170
171 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
172 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
173
174 /* PHY parameters */
175 struct ieee80211_supported_band band;
176 struct ieee80211_channel channels[14];
177 struct ieee80211_rate rates[12];
178
c46563b7 179 bool radio_on;
68ce3884 180 bool radio_short_preamble;
0439b1f5 181 bool wmm_enabled;
a66098da 182
a66098da
LB		 183 /* XXX need to convert this to handle multiple interfaces */
184 bool capture_beacon;
d89173f2 185 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 186 struct sk_buff *beacon_skb;
187
188 /*
189 * This FJ worker has to be global as it is scheduled from the
190 * RX handler. At this point we don't know which interface it
191 * belongs to until the list of bssids waiting to complete join
192 * is checked.
193 */
194 struct work_struct finalize_join_worker;
195
196 /* Tasklet to reclaim TX descriptors and buffers after tx */
197 struct tasklet_struct tx_reclaim_task;
198
199 /* Work thread to serialize configuration requests */
200 struct workqueue_struct *config_wq;
a66098da
LB		 201};
202
203/* Per interface specific private data */
204struct mwl8k_vif {
a66098da
LB		 205 /* backpointer to parent config block */
206 struct mwl8k_priv *priv;
207
208 /* BSS config of AP or IBSS from mac80211*/
209 struct ieee80211_bss_conf bss_info;
210
211 /* BSSID of AP or IBSS */
d89173f2
LB		 212 u8 bssid[ETH_ALEN];
213 u8 mac_addr[ETH_ALEN];
a66098da
LB		 214
215 /*
216 * Subset of supported legacy rates.
217 * Intersection of AP and STA supported rates.
218 */
219 struct ieee80211_rate legacy_rates[12];
220
221 /* number of supported legacy rates */
222 u8 legacy_nrates;
223
a66098da
LB		 224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
a66098da
LB		 229};
230
a94cc97e 231#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 232
233static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245};
246
247static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 60, .hw_value = 12, },
252 { .bitrate = 90, .hw_value = 18, },
253 { .bitrate = 110, .hw_value = 22, },
254 { .bitrate = 120, .hw_value = 24, },
255 { .bitrate = 180, .hw_value = 36, },
256 { .bitrate = 240, .hw_value = 48, },
257 { .bitrate = 360, .hw_value = 72, },
258 { .bitrate = 480, .hw_value = 96, },
259 { .bitrate = 540, .hw_value = 108, },
260};
261
a66098da
LB		 262/* Set or get info from Firmware */
263#define MWL8K_CMD_SET 0x0001
264#define MWL8K_CMD_GET 0x0000
265
266/* Firmware command codes */
267#define MWL8K_CMD_CODE_DNLD 0x0001
268#define MWL8K_CMD_GET_HW_SPEC 0x0003
269#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
270#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 271#define MWL8K_CMD_RADIO_CONTROL 0x001c
272#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 273#define MWL8K_CMD_SET_PRE_SCAN 0x0107
274#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 275#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
276#define MWL8K_CMD_SET_AID 0x010d
277#define MWL8K_CMD_SET_RATE 0x0110
278#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
279#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 280#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 281#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
282#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 283#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 284#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 285#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
a66098da 286#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 287#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 288
289static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
290{
291#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
292 snprintf(buf, bufsize, "%s", #x);\
293 return buf;\
294 } while (0)
ce9e2e1b 295 switch (cmd & ~0x8000) {
a66098da
LB		 296 MWL8K_CMDNAME(CODE_DNLD);
297 MWL8K_CMDNAME(GET_HW_SPEC);
298 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
299 MWL8K_CMDNAME(GET_STAT);
300 MWL8K_CMDNAME(RADIO_CONTROL);
301 MWL8K_CMDNAME(RF_TX_POWER);
302 MWL8K_CMDNAME(SET_PRE_SCAN);
303 MWL8K_CMDNAME(SET_POST_SCAN);
304 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 305 MWL8K_CMDNAME(SET_AID);
306 MWL8K_CMDNAME(SET_RATE);
307 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
308 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 309 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 310 MWL8K_CMDNAME(SET_EDCA_PARAMS);
311 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 312 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 313 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 314 MWL8K_CMDNAME(ENABLE_SNIFFER);
a66098da 315 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 316 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 317 default:
318 snprintf(buf, bufsize, "0x%x", cmd);
319 }
320#undef MWL8K_CMDNAME
321
322 return buf;
323}
324
325/* Hardware and firmware reset */
326static void mwl8k_hw_reset(struct mwl8k_priv *priv)
327{
328 iowrite32(MWL8K_H2A_INT_RESET,
329 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
330 iowrite32(MWL8K_H2A_INT_RESET,
331 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
332 msleep(20);
333}
334
335/* Release fw image */
336static void mwl8k_release_fw(struct firmware **fw)
337{
338 if (*fw == NULL)
339 return;
340 release_firmware(*fw);
341 *fw = NULL;
342}
343
344static void mwl8k_release_firmware(struct mwl8k_priv *priv)
345{
346 mwl8k_release_fw(&priv->fw.ucode);
347 mwl8k_release_fw(&priv->fw.helper);
348}
349
350/* Request fw image */
351static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 352 const char *fname, struct firmware **fw)
a66098da
LB		 353{
354 /* release current image */
355 if (*fw != NULL)
356 mwl8k_release_fw(fw);
357
358 return request_firmware((const struct firmware **)fw,
c2c357ce 359 fname, &priv->pdev->dev);
a66098da
LB		 360}
361
362static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
363{
364 u8 filename[64];
365 int rc;
366
367 priv->part_num = part_num;
368
369 snprintf(filename, sizeof(filename),
370 "mwl8k/helper_%u.fw", priv->part_num);
371
372 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
373 if (rc) {
c2c357ce
LB		 374 printk(KERN_ERR "%s: Error requesting helper firmware "
375 "file %s\n", pci_name(priv->pdev), filename);
a66098da
LB		 376 return rc;
377 }
378
379 snprintf(filename, sizeof(filename),
380 "mwl8k/fmimage_%u.fw", priv->part_num);
381
382 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
383 if (rc) {
c2c357ce
LB		 384 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
385 pci_name(priv->pdev), filename);
a66098da
LB		 386 mwl8k_release_fw(&priv->fw.helper);
387 return rc;
388 }
389
390 return 0;
391}
392
393struct mwl8k_cmd_pkt {
394 __le16 code;
395 __le16 length;
396 __le16 seq_num;
397 __le16 result;
398 char payload[0];
399} __attribute__((packed));
400
401/*
402 * Firmware loading.
403 */
404static int
405mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
406{
407 void __iomem *regs = priv->regs;
408 dma_addr_t dma_addr;
a66098da
LB		 409 int loops;
410
411 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
412 if (pci_dma_mapping_error(priv->pdev, dma_addr))
413 return -ENOMEM;
414
415 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
416 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
417 iowrite32(MWL8K_H2A_INT_DOORBELL,
418 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
419 iowrite32(MWL8K_H2A_INT_DUMMY,
420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
421
a66098da
LB		 422 loops = 1000;
423 do {
424 u32 int_code;
425
426 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
427 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
428 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 429 break;
430 }
431
432 udelay(1);
433 } while (--loops);
434
435 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
436
d4b70570 437 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 438}
439
440static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
441 const u8 *data, size_t length)
442{
443 struct mwl8k_cmd_pkt *cmd;
444 int done;
445 int rc = 0;
446
447 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
448 if (cmd == NULL)
449 return -ENOMEM;
450
451 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
452 cmd->seq_num = 0;
453 cmd->result = 0;
454
455 done = 0;
456 while (length) {
457 int block_size = length > 256 ? 256 : length;
458
459 memcpy(cmd->payload, data + done, block_size);
460 cmd->length = cpu_to_le16(block_size);
461
462 rc = mwl8k_send_fw_load_cmd(priv, cmd,
463 sizeof(*cmd) + block_size);
464 if (rc)
465 break;
466
467 done += block_size;
468 length -= block_size;
469 }
470
471 if (!rc) {
472 cmd->length = 0;
473 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
474 }
475
476 kfree(cmd);
477
478 return rc;
479}
480
481static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
482 const u8 *data, size_t length)
483{
484 unsigned char *buffer;
485 int may_continue, rc = 0;
486 u32 done, prev_block_size;
487
488 buffer = kmalloc(1024, GFP_KERNEL);
489 if (buffer == NULL)
490 return -ENOMEM;
491
492 done = 0;
493 prev_block_size = 0;
494 may_continue = 1000;
495 while (may_continue > 0) {
496 u32 block_size;
497
498 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
499 if (block_size & 1) {
500 block_size &= ~1;
501 may_continue--;
502 } else {
503 done += prev_block_size;
504 length -= prev_block_size;
505 }
506
507 if (block_size > 1024 || block_size > length) {
508 rc = -EOVERFLOW;
509 break;
510 }
511
512 if (length == 0) {
513 rc = 0;
514 break;
515 }
516
517 if (block_size == 0) {
518 rc = -EPROTO;
519 may_continue--;
520 udelay(1);
521 continue;
522 }
523
524 prev_block_size = block_size;
525 memcpy(buffer, data + done, block_size);
526
527 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
528 if (rc)
529 break;
530 }
531
532 if (!rc && length != 0)
533 rc = -EREMOTEIO;
534
535 kfree(buffer);
536
537 return rc;
538}
539
c2c357ce 540static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 541{
c2c357ce
LB		 542 struct mwl8k_priv *priv = hw->priv;
543 struct firmware *fw = priv->fw.ucode;
544 int rc;
545 int loops;
546
547 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
548 struct firmware *helper = priv->fw.helper;
a66098da 549
c2c357ce
LB		 550 if (helper == NULL) {
551 printk(KERN_ERR "%s: helper image needed but none "
552 "given\n", pci_name(priv->pdev));
553 return -EINVAL;
554 }
a66098da 555
c2c357ce 556 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 557 if (rc) {
558 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 559 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 560 return rc;
561 }
562 msleep(1);
563
c2c357ce 564 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 565 } else {
c2c357ce 566 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 567 }
568
569 if (rc) {
c2c357ce
LB		 570 printk(KERN_ERR "%s: unable to load firmware image\n",
571 pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
574
575 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
576 msleep(1);
577
578 loops = 200000;
579 do {
580 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
581 == MWL8K_FWSTA_READY)
582 break;
583 udelay(1);
584 } while (--loops);
585
586 return loops ? 0 : -ETIMEDOUT;
587}
588
589
590/*
591 * Defines shared between transmission and reception.
592 */
593/* HT control fields for firmware */
594struct ewc_ht_info {
595 __le16 control1;
596 __le16 control2;
597 __le16 control3;
598} __attribute__((packed));
599
600/* Firmware Station database operations */
601#define MWL8K_STA_DB_ADD_ENTRY 0
602#define MWL8K_STA_DB_MODIFY_ENTRY 1
603#define MWL8K_STA_DB_DEL_ENTRY 2
604#define MWL8K_STA_DB_FLUSH 3
605
606/* Peer Entry flags - used to define the type of the peer node */
607#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da
LB		 608
609#define MWL8K_IEEE_LEGACY_DATA_RATES 12
610#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 611
612struct peer_capability_info {
613 /* Peer type - AP vs. STA. */
614 __u8 peer_type;
615
616 /* Basic 802.11 capabilities from assoc resp. */
617 __le16 basic_caps;
618
619 /* Set if peer supports 802.11n high throughput (HT). */
620 __u8 ht_support;
621
622 /* Valid if HT is supported. */
623 __le16 ht_caps;
624 __u8 extended_ht_caps;
625 struct ewc_ht_info ewc_info;
626
627 /* Legacy rate table. Intersection of our rates and peer rates. */
628 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
629
630 /* HT rate table. Intersection of our rates and peer rates. */
631 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 632 __u8 pad[16];
a66098da
LB		 633
634 /* If set, interoperability mode, no proprietary extensions. */
635 __u8 interop;
636 __u8 pad2;
637 __u8 station_id;
638 __le16 amsdu_enabled;
639} __attribute__((packed));
640
641/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 642static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
643{
644 u16 val_mask = 1 << 4;
645
646 /* End of Service Period Bit 4 */
647 return qos | val_mask;
648}
649
650static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
651{
652 u16 val_mask = 0x3;
653 u8 shift = 5;
654 u16 qos_mask = ~(val_mask << shift);
655
656 /* Ack Policy Bit 5-6 */
657 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
658}
659
660static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
661{
662 u16 val_mask = 1 << 7;
663
664 /* AMSDU present Bit 7 */
665 return qos | val_mask;
666}
667
668static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
669{
670 u16 val_mask = 0xff;
671 u8 shift = 8;
672 u16 qos_mask = ~(val_mask << shift);
673
674 /* Queue Length Bits 8-15 */
675 return (qos & qos_mask) | ((len & val_mask) << shift);
676}
677
678/* DMA header used by firmware and hardware. */
679struct mwl8k_dma_data {
680 __le16 fwlen;
681 struct ieee80211_hdr wh;
682} __attribute__((packed));
683
684/* Routines to add/remove DMA header from skb. */
76266b2a 685static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 686{
76266b2a 687 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 688 void *dst, *src = &tr->wh;
76266b2a 689 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 690 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
691
692 dst = (void *)tr + space;
693 if (dst != src) {
694 memmove(dst, src, hdrlen);
695 skb_pull(skb, space);
696 }
a66098da
LB		 697}
698
76266b2a 699static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 700{
701 struct ieee80211_hdr *wh;
702 u32 hdrlen, pktlen;
703 struct mwl8k_dma_data *tr;
704
705 wh = (struct ieee80211_hdr *)skb->data;
706 hdrlen = ieee80211_hdrlen(wh->frame_control);
707 pktlen = skb->len;
708
709 /*
710 * Copy up/down the 802.11 header; the firmware requires
711 * we present a 2-byte payload length followed by a
712 * 4-address header (w/o QoS), followed (optionally) by
713 * any WEP/ExtIV header (but only filled in for CCMP).
714 */
715 if (hdrlen != sizeof(struct mwl8k_dma_data))
716 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
717
718 tr = (struct mwl8k_dma_data *)skb->data;
719 if (wh != &tr->wh)
720 memmove(&tr->wh, wh, hdrlen);
721
722 /* Clear addr4 */
d89173f2 723 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 724
725 /*
726 * Firmware length is the length of the fully formed "802.11
727 * payload". That is, everything except for the 802.11 header.
728 * This includes all crypto material including the MIC.
729 */
730 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 731}
732
733
734/*
735 * Packet reception.
736 */
a66098da 737#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
a66098da
LB		 738
739struct mwl8k_rx_desc {
740 __le16 pkt_len;
741 __u8 link_quality;
742 __u8 noise_level;
743 __le32 pkt_phys_addr;
744 __le32 next_rx_desc_phys_addr;
745 __le16 qos_control;
746 __le16 rate_info;
747 __le32 pad0[4];
748 __u8 rssi;
749 __u8 channel;
750 __le16 pad1;
751 __u8 rx_ctrl;
752 __u8 rx_status;
753 __u8 pad2[2];
754} __attribute__((packed));
755
756#define MWL8K_RX_DESCS 256
757#define MWL8K_RX_MAXSZ 3800
758
759static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
760{
761 struct mwl8k_priv *priv = hw->priv;
762 struct mwl8k_rx_queue *rxq = priv->rxq + index;
763 int size;
764 int i;
765
766 rxq->rx_desc_count = 0;
767 rxq->rx_head = 0;
768 rxq->rx_tail = 0;
769
770 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
771
772 rxq->rx_desc_area =
773 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
774 if (rxq->rx_desc_area == NULL) {
775 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 776 wiphy_name(hw->wiphy));
a66098da
LB		 777 return -ENOMEM;
778 }
779 memset(rxq->rx_desc_area, 0, size);
780
781 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
782 sizeof(*rxq->rx_skb), GFP_KERNEL);
783 if (rxq->rx_skb == NULL) {
784 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 785 wiphy_name(hw->wiphy));
a66098da
LB		 786 pci_free_consistent(priv->pdev, size,
787 rxq->rx_desc_area, rxq->rx_desc_dma);
788 return -ENOMEM;
789 }
790 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
791
792 for (i = 0; i < MWL8K_RX_DESCS; i++) {
793 struct mwl8k_rx_desc *rx_desc;
794 int nexti;
795
796 rx_desc = rxq->rx_desc_area + i;
797 nexti = (i + 1) % MWL8K_RX_DESCS;
798
799 rx_desc->next_rx_desc_phys_addr =
800 cpu_to_le32(rxq->rx_desc_dma
801 + nexti * sizeof(*rx_desc));
c491bf12 802 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 803 }
804
805 return 0;
806}
807
808static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
809{
810 struct mwl8k_priv *priv = hw->priv;
811 struct mwl8k_rx_queue *rxq = priv->rxq + index;
812 int refilled;
813
814 refilled = 0;
815 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
816 struct sk_buff *skb;
817 int rx;
818
819 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
820 if (skb == NULL)
821 break;
822
823 rxq->rx_desc_count++;
824
825 rx = rxq->rx_tail;
826 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
827
828 rxq->rx_desc_area[rx].pkt_phys_addr =
829 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
830 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
831
832 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
833 rxq->rx_skb[rx] = skb;
834 wmb();
835 rxq->rx_desc_area[rx].rx_ctrl = 0;
836
837 refilled++;
838 }
839
840 return refilled;
841}
842
843/* Must be called only when the card's reception is completely halted */
844static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
845{
846 struct mwl8k_priv *priv = hw->priv;
847 struct mwl8k_rx_queue *rxq = priv->rxq + index;
848 int i;
849
850 for (i = 0; i < MWL8K_RX_DESCS; i++) {
851 if (rxq->rx_skb[i] != NULL) {
852 unsigned long addr;
853
854 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
855 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
856 PCI_DMA_FROMDEVICE);
857 kfree_skb(rxq->rx_skb[i]);
858 rxq->rx_skb[i] = NULL;
859 }
860 }
861
862 kfree(rxq->rx_skb);
863 rxq->rx_skb = NULL;
864
865 pci_free_consistent(priv->pdev,
866 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
867 rxq->rx_desc_area, rxq->rx_desc_dma);
868 rxq->rx_desc_area = NULL;
869}
870
871
872/*
873 * Scan a list of BSSIDs to process for finalize join.
874 * Allows for extension to process multiple BSSIDs.
875 */
876static inline int
877mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
878{
879 return priv->capture_beacon &&
880 ieee80211_is_beacon(wh->frame_control) &&
881 !compare_ether_addr(wh->addr3, priv->capture_bssid);
882}
883
884static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
885 struct sk_buff *skb)
886{
887 priv->capture_beacon = false;
d89173f2 888 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 889
890 /*
891 * Use GFP_ATOMIC as rxq_process is called from
892 * the primary interrupt handler, memory allocation call
893 * must not sleep.
894 */
895 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
896 if (priv->beacon_skb != NULL)
897 queue_work(priv->config_wq,
898 &priv->finalize_join_worker);
899}
900
901static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
902{
903 struct mwl8k_priv *priv = hw->priv;
904 struct mwl8k_rx_queue *rxq = priv->rxq + index;
905 int processed;
906
907 processed = 0;
908 while (rxq->rx_desc_count && limit--) {
909 struct mwl8k_rx_desc *rx_desc;
910 struct sk_buff *skb;
911 struct ieee80211_rx_status status;
912 unsigned long addr;
913 struct ieee80211_hdr *wh;
914
915 rx_desc = rxq->rx_desc_area + rxq->rx_head;
916 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
917 break;
918 rmb();
919
920 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 921 if (skb == NULL)
922 break;
a66098da
LB		 923 rxq->rx_skb[rxq->rx_head] = NULL;
924
925 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
926 rxq->rx_desc_count--;
927
928 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
929 pci_unmap_single(priv->pdev, addr,
930 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
931
932 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
76266b2a 933 mwl8k_remove_dma_header(skb);
a66098da
LB		 934
935 wh = (struct ieee80211_hdr *)skb->data;
936
937 /*
c2c357ce
LB		 938 * Check for a pending join operation. Save a
939 * copy of the beacon and schedule a tasklet to
940 * send a FINALIZE_JOIN command to the firmware.
a66098da
LB		 941 */
942 if (mwl8k_capture_bssid(priv, wh))
943 mwl8k_save_beacon(priv, skb);
944
945 memset(&status, 0, sizeof(status));
946 status.mactime = 0;
947 status.signal = -rx_desc->rssi;
948 status.noise = -rx_desc->noise_level;
949 status.qual = rx_desc->link_quality;
950 status.antenna = 1;
951 status.rate_idx = 1;
952 status.flag = 0;
953 status.band = IEEE80211_BAND_2GHZ;
954 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
f1d58c25
JB		 955 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
956 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 957
958 processed++;
959 }
960
961 return processed;
962}
963
964
965/*
966 * Packet transmission.
967 */
968
969/* Transmit queue assignment. */
970enum {
971 MWL8K_WME_AC_BK = 0, /* background access */
972 MWL8K_WME_AC_BE = 1, /* best effort access */
973 MWL8K_WME_AC_VI = 2, /* video access */
974 MWL8K_WME_AC_VO = 3, /* voice access */
975};
976
977/* Transmit packet ACK policy */
978#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 979#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
980
981#define GET_TXQ(_ac) (\
982 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
983 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
984 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
985 MWL8K_WME_AC_BE)
986
a66098da
LB		 987#define MWL8K_TXD_STATUS_OK 0x00000001
988#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
989#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
990#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 991#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 992
993struct mwl8k_tx_desc {
994 __le32 status;
995 __u8 data_rate;
996 __u8 tx_priority;
997 __le16 qos_control;
998 __le32 pkt_phys_addr;
999 __le16 pkt_len;
d89173f2 1000 __u8 dest_MAC_addr[ETH_ALEN];
a66098da
LB		 1001 __le32 next_tx_desc_phys_addr;
1002 __le32 reserved;
1003 __le16 rate_info;
1004 __u8 peer_id;
1005 __u8 tx_frag_cnt;
1006} __attribute__((packed));
1007
1008#define MWL8K_TX_DESCS 128
1009
1010static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1011{
1012 struct mwl8k_priv *priv = hw->priv;
1013 struct mwl8k_tx_queue *txq = priv->txq + index;
1014 int size;
1015 int i;
1016
ce9e2e1b 1017 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
a66098da
LB		 1018 txq->tx_stats.limit = MWL8K_TX_DESCS;
1019 txq->tx_head = 0;
1020 txq->tx_tail = 0;
1021
1022 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1023
1024 txq->tx_desc_area =
1025 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1026 if (txq->tx_desc_area == NULL) {
1027 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1028 wiphy_name(hw->wiphy));
a66098da
LB		 1029 return -ENOMEM;
1030 }
1031 memset(txq->tx_desc_area, 0, size);
1032
1033 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1034 GFP_KERNEL);
1035 if (txq->tx_skb == NULL) {
1036 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1037 wiphy_name(hw->wiphy));
a66098da
LB		 1038 pci_free_consistent(priv->pdev, size,
1039 txq->tx_desc_area, txq->tx_desc_dma);
1040 return -ENOMEM;
1041 }
1042 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1043
1044 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1045 struct mwl8k_tx_desc *tx_desc;
1046 int nexti;
1047
1048 tx_desc = txq->tx_desc_area + i;
1049 nexti = (i + 1) % MWL8K_TX_DESCS;
1050
1051 tx_desc->status = 0;
1052 tx_desc->next_tx_desc_phys_addr =
1053 cpu_to_le32(txq->tx_desc_dma +
1054 nexti * sizeof(*tx_desc));
1055 }
1056
1057 return 0;
1058}
1059
1060static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1061{
1062 iowrite32(MWL8K_H2A_INT_PPA_READY,
1063 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1064 iowrite32(MWL8K_H2A_INT_DUMMY,
1065 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1066 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1067}
1068
a66098da
LB		 1069struct mwl8k_txq_info {
1070 u32 fw_owned;
1071 u32 drv_owned;
1072 u32 unused;
1073 u32 len;
1074 u32 head;
1075 u32 tail;
1076};
1077
1078static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1079 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1080{
1081 int count, desc, status;
1082 struct mwl8k_tx_queue *txq;
1083 struct mwl8k_tx_desc *tx_desc;
1084 int ndescs = 0;
1085
c3f967d3
LB		 1086 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1087
c3f967d3 1088 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da
LB		 1089 txq = priv->txq + count;
1090 txinfo[count].len = txq->tx_stats.len;
1091 txinfo[count].head = txq->tx_head;
1092 txinfo[count].tail = txq->tx_tail;
1093 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1094 tx_desc = txq->tx_desc_area + desc;
1095 status = le32_to_cpu(tx_desc->status);
1096
1097 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1098 txinfo[count].fw_owned++;
1099 else
1100 txinfo[count].drv_owned++;
1101
1102 if (tx_desc->pkt_len == 0)
1103 txinfo[count].unused++;
1104 }
1105 }
a66098da
LB		 1106
1107 return ndescs;
1108}
1109
618952a7 1110/*
88de754a 1111 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1112 */
950d5b01 1113static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1114{
a66098da 1115 struct mwl8k_priv *priv = hw->priv;
88de754a 1116 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1117 u32 count;
1118 unsigned long timeout;
a66098da
LB		 1119
1120 might_sleep();
1121
a66098da 1122 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1123 count = priv->pending_tx_pkts;
1124 if (count)
1125 priv->tx_wait = &tx_wait;
a66098da
LB		 1126 spin_unlock_bh(&priv->tx_lock);
1127
1128 if (count) {
c3f967d3 1129 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1130 int index;
1131 int newcount;
1132
88de754a 1133 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1134 msecs_to_jiffies(5000));
a66098da
LB		 1135 if (timeout)
1136 return 0;
1137
1138 spin_lock_bh(&priv->tx_lock);
1139 priv->tx_wait = NULL;
88de754a
LB		 1140 newcount = priv->pending_tx_pkts;
1141 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1142 spin_unlock_bh(&priv->tx_lock);
1143
618952a7 1144 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1145 __func__, __LINE__, count, newcount);
a66098da 1146
c3f967d3 1147 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1148 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1149 "DRV:%u U:%u\n",
a66098da
LB		 1150 index,
1151 txinfo[index].len,
1152 txinfo[index].head,
1153 txinfo[index].tail,
1154 txinfo[index].fw_owned,
1155 txinfo[index].drv_owned,
1156 txinfo[index].unused);
ce9e2e1b 1157
a66098da
LB		 1158 return -ETIMEDOUT;
1159 }
1160
1161 return 0;
1162}
1163
c23b5a69
LB		 1164#define MWL8K_TXD_SUCCESS(status) \
1165 ((status) & (MWL8K_TXD_STATUS_OK | \
1166 MWL8K_TXD_STATUS_OK_RETRY | \
1167 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1168
1169static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1170{
1171 struct mwl8k_priv *priv = hw->priv;
1172 struct mwl8k_tx_queue *txq = priv->txq + index;
1173 int wake = 0;
1174
1175 while (txq->tx_stats.len > 0) {
1176 int tx;
a66098da
LB		 1177 struct mwl8k_tx_desc *tx_desc;
1178 unsigned long addr;
ce9e2e1b 1179 int size;
a66098da
LB		 1180 struct sk_buff *skb;
1181 struct ieee80211_tx_info *info;
1182 u32 status;
1183
a66098da
LB		 1184 tx = txq->tx_head;
1185 tx_desc = txq->tx_desc_area + tx;
1186
1187 status = le32_to_cpu(tx_desc->status);
1188
1189 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1190 if (!force)
1191 break;
1192 tx_desc->status &=
1193 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1194 }
1195
1196 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1197 BUG_ON(txq->tx_stats.len == 0);
1198 txq->tx_stats.len--;
1199 priv->pending_tx_pkts--;
1200
1201 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1202 size = le16_to_cpu(tx_desc->pkt_len);
76266b2a
LB		 1203 skb = txq->tx_skb[tx];
1204 txq->tx_skb[tx] = NULL;
a66098da
LB		 1205
1206 BUG_ON(skb == NULL);
1207 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1208
76266b2a 1209 mwl8k_remove_dma_header(skb);
a66098da
LB		 1210
1211 /* Mark descriptor as unused */
1212 tx_desc->pkt_phys_addr = 0;
1213 tx_desc->pkt_len = 0;
1214
a66098da
LB		 1215 info = IEEE80211_SKB_CB(skb);
1216 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1217 if (MWL8K_TXD_SUCCESS(status))
a66098da 1218 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1219
1220 ieee80211_tx_status_irqsafe(hw, skb);
1221
618952a7 1222 wake = 1;
a66098da
LB		 1223 }
1224
618952a7 1225 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1226 ieee80211_wake_queue(hw, index);
1227}
1228
1229/* must be called only when the card's transmit is completely halted */
1230static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1231{
1232 struct mwl8k_priv *priv = hw->priv;
1233 struct mwl8k_tx_queue *txq = priv->txq + index;
1234
1235 mwl8k_txq_reclaim(hw, index, 1);
1236
1237 kfree(txq->tx_skb);
1238 txq->tx_skb = NULL;
1239
1240 pci_free_consistent(priv->pdev,
1241 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1242 txq->tx_desc_area, txq->tx_desc_dma);
1243 txq->tx_desc_area = NULL;
1244}
1245
1246static int
1247mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1248{
1249 struct mwl8k_priv *priv = hw->priv;
1250 struct ieee80211_tx_info *tx_info;
23b33906 1251 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1252 struct ieee80211_hdr *wh;
1253 struct mwl8k_tx_queue *txq;
1254 struct mwl8k_tx_desc *tx;
a66098da 1255 dma_addr_t dma;
23b33906
LB		 1256 u32 txstatus;
1257 u8 txdatarate;
1258 u16 qos;
a66098da 1259
23b33906
LB		 1260 wh = (struct ieee80211_hdr *)skb->data;
1261 if (ieee80211_is_data_qos(wh->frame_control))
1262 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1263 else
1264 qos = 0;
a66098da 1265
76266b2a 1266 mwl8k_add_dma_header(skb);
23b33906 1267 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1268
1269 tx_info = IEEE80211_SKB_CB(skb);
1270 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1271
1272 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1273 u16 seqno = mwl8k_vif->seqno;
23b33906 1274
a66098da
LB		 1275 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1276 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1277 mwl8k_vif->seqno = seqno++ % 4096;
1278 }
1279
23b33906
LB		 1280 /* Setup firmware control bit fields for each frame type. */
1281 txstatus = 0;
1282 txdatarate = 0;
1283 if (ieee80211_is_mgmt(wh->frame_control) ||
1284 ieee80211_is_ctl(wh->frame_control)) {
1285 txdatarate = 0;
1286 qos = mwl8k_qos_setbit_eosp(qos);
1287 /* Set Queue size to unspecified */
1288 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1289 } else if (ieee80211_is_data(wh->frame_control)) {
1290 txdatarate = 1;
1291 if (is_multicast_ether_addr(wh->addr1))
1292 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1293
1294 /* Send pkt in an aggregate if AMPDU frame. */
1295 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1296 qos = mwl8k_qos_setbit_ack(qos,
1297 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1298 else
1299 qos = mwl8k_qos_setbit_ack(qos,
1300 MWL8K_TXD_ACK_POLICY_NORMAL);
1301
1302 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1303 qos = mwl8k_qos_setbit_amsdu(qos);
1304 }
a66098da
LB		 1305
1306 dma = pci_map_single(priv->pdev, skb->data,
1307 skb->len, PCI_DMA_TODEVICE);
1308
1309 if (pci_dma_mapping_error(priv->pdev, dma)) {
1310 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1311 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1312 dev_kfree_skb(skb);
a66098da
LB		 1313 return NETDEV_TX_OK;
1314 }
1315
23b33906 1316 spin_lock_bh(&priv->tx_lock);
a66098da 1317
23b33906 1318 txq = priv->txq + index;
a66098da 1319
23b33906
LB		 1320 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1321 txq->tx_skb[txq->tx_tail] = skb;
a66098da 1322
23b33906
LB		 1323 tx = txq->tx_desc_area + txq->tx_tail;
1324 tx->data_rate = txdatarate;
1325 tx->tx_priority = index;
a66098da 1326 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1327 tx->pkt_phys_addr = cpu_to_le32(dma);
1328 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1329 tx->rate_info = 0;
1330 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1331 wmb();
23b33906
LB		 1332 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1333
1334 txq->tx_stats.count++;
a66098da
LB		 1335 txq->tx_stats.len++;
1336 priv->pending_tx_pkts++;
a66098da 1337
23b33906 1338 txq->tx_tail++;
a66098da
LB		 1339 if (txq->tx_tail == MWL8K_TX_DESCS)
1340 txq->tx_tail = 0;
23b33906 1341
a66098da
LB		 1342 if (txq->tx_head == txq->tx_tail)
1343 ieee80211_stop_queue(hw, index);
1344
23b33906 1345 mwl8k_tx_start(priv);
a66098da
LB		 1346
1347 spin_unlock_bh(&priv->tx_lock);
1348
1349 return NETDEV_TX_OK;
1350}
1351
1352
618952a7
LB		 1353/*
1354 * Firmware access.
1355 *
1356 * We have the following requirements for issuing firmware commands:
1357 * - Some commands require that the packet transmit path is idle when
1358 * the command is issued. (For simplicity, we'll just quiesce the
1359 * transmit path for every command.)
1360 * - There are certain sequences of commands that need to be issued to
1361 * the hardware sequentially, with no other intervening commands.
1362 *
1363 * This leads to an implementation of a "firmware lock" as a mutex that
1364 * can be taken recursively, and which is taken by both the low-level
1365 * command submission function (mwl8k_post_cmd) as well as any users of
1366 * that function that require issuing of an atomic sequence of commands,
1367 * and quiesces the transmit path whenever it's taken.
1368 */
1369static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1370{
1371 struct mwl8k_priv *priv = hw->priv;
1372
1373 if (priv->fw_mutex_owner != current) {
1374 int rc;
1375
1376 mutex_lock(&priv->fw_mutex);
1377 ieee80211_stop_queues(hw);
1378
1379 rc = mwl8k_tx_wait_empty(hw);
1380 if (rc) {
1381 ieee80211_wake_queues(hw);
1382 mutex_unlock(&priv->fw_mutex);
1383
1384 return rc;
1385 }
1386
1387 priv->fw_mutex_owner = current;
1388 }
1389
1390 priv->fw_mutex_depth++;
1391
1392 return 0;
1393}
1394
1395static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1396{
1397 struct mwl8k_priv *priv = hw->priv;
1398
1399 if (!--priv->fw_mutex_depth) {
1400 ieee80211_wake_queues(hw);
1401 priv->fw_mutex_owner = NULL;
1402 mutex_unlock(&priv->fw_mutex);
1403 }
1404}
1405
1406
a66098da
LB		 1407/*
1408 * Command processing.
1409 */
1410
1411/* Timeout firmware commands after 2000ms */
1412#define MWL8K_CMD_TIMEOUT_MS 2000
1413
1414static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1415{
1416 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1417 struct mwl8k_priv *priv = hw->priv;
1418 void __iomem *regs = priv->regs;
1419 dma_addr_t dma_addr;
1420 unsigned int dma_size;
1421 int rc;
a66098da
LB		 1422 unsigned long timeout = 0;
1423 u8 buf[32];
1424
c2c357ce 1425 cmd->result = 0xffff;
a66098da
LB		 1426 dma_size = le16_to_cpu(cmd->length);
1427 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1428 PCI_DMA_BIDIRECTIONAL);
1429 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1430 return -ENOMEM;
1431
618952a7 1432 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1433 if (rc) {
1434 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1435 PCI_DMA_BIDIRECTIONAL);
618952a7 1436 return rc;
39a1e42e 1437 }
a66098da 1438
a66098da
LB		 1439 priv->hostcmd_wait = &cmd_wait;
1440 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1441 iowrite32(MWL8K_H2A_INT_DOORBELL,
1442 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1443 iowrite32(MWL8K_H2A_INT_DUMMY,
1444 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1445
1446 timeout = wait_for_completion_timeout(&cmd_wait,
1447 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1448
618952a7
LB		 1449 priv->hostcmd_wait = NULL;
1450
1451 mwl8k_fw_unlock(hw);
1452
37055bd4
LB		 1453 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1454 PCI_DMA_BIDIRECTIONAL);
1455
a66098da 1456 if (!timeout) {
a66098da 1457 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1458 wiphy_name(hw->wiphy),
a66098da
LB		 1459 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1460 MWL8K_CMD_TIMEOUT_MS);
1461 rc = -ETIMEDOUT;
1462 } else {
ce9e2e1b 1463 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1464 if (rc)
1465 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1466 wiphy_name(hw->wiphy),
a66098da 1467 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1468 le16_to_cpu(cmd->result));
a66098da
LB		 1469 }
1470
a66098da
LB		 1471 return rc;
1472}
1473
1474/*
1475 * GET_HW_SPEC.
1476 */
1477struct mwl8k_cmd_get_hw_spec {
1478 struct mwl8k_cmd_pkt header;
1479 __u8 hw_rev;
1480 __u8 host_interface;
1481 __le16 num_mcaddrs;
d89173f2 1482 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1483 __le16 region_code;
1484 __le32 fw_rev;
1485 __le32 ps_cookie;
1486 __le32 caps;
1487 __u8 mcs_bitmap[16];
1488 __le32 rx_queue_ptr;
1489 __le32 num_tx_queues;
1490 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1491 __le32 caps2;
1492 __le32 num_tx_desc_per_queue;
1493 __le32 total_rx_desc;
1494} __attribute__((packed));
1495
1496static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1497{
1498 struct mwl8k_priv *priv = hw->priv;
1499 struct mwl8k_cmd_get_hw_spec *cmd;
1500 int rc;
1501 int i;
1502
1503 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1504 if (cmd == NULL)
1505 return -ENOMEM;
1506
1507 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1508 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1509
1510 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1511 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1512 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1513 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1514 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1515 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1516 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1517 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1518
1519 rc = mwl8k_post_cmd(hw, &cmd->header);
1520
1521 if (!rc) {
1522 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1523 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1524 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1525 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1526 }
1527
1528 kfree(cmd);
1529 return rc;
1530}
1531
1532/*
1533 * CMD_MAC_MULTICAST_ADR.
1534 */
1535struct mwl8k_cmd_mac_multicast_adr {
1536 struct mwl8k_cmd_pkt header;
1537 __le16 action;
1538 __le16 numaddr;
ce9e2e1b 1539 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1540};
1541
d5e30845
LB		 1542#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1543#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1544#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1545#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1546
e81cd2d6
LB		 1547static struct mwl8k_cmd_pkt *
1548__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1549 int mc_count, struct dev_addr_list *mclist)
a66098da 1550{
e81cd2d6 1551 struct mwl8k_priv *priv = hw->priv;
a66098da 1552 struct mwl8k_cmd_mac_multicast_adr *cmd;
d5e30845 1553 int allmulti;
e81cd2d6 1554 int size;
e81cd2d6 1555
d5e30845
LB		 1556 allmulti = 0;
1557 if (mc_count > priv->num_mcaddrs) {
1558 allmulti = 1;
1559 mc_count = 0;
1560 }
e81cd2d6
LB		 1561
1562 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1563
e81cd2d6 1564 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1565 if (cmd == NULL)
e81cd2d6 1566 return NULL;
a66098da
LB		 1567
1568 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1569 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1570 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1571 MWL8K_ENABLE_RX_BROADCAST);
1572
1573 if (allmulti) {
1574 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1575 } else if (mc_count) {
1576 int i;
1577
1578 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1579 cmd->numaddr = cpu_to_le16(mc_count);
1580 for (i = 0; i < mc_count && mclist; i++) {
1581 if (mclist->da_addrlen != ETH_ALEN) {
1582 kfree(cmd);
1583 return NULL;
1584 }
1585 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1586 mclist = mclist->next;
a66098da 1587 }
a66098da
LB		 1588 }
1589
e81cd2d6 1590 return &cmd->header;
a66098da
LB		 1591}
1592
1593/*
1594 * CMD_802_11_GET_STAT.
1595 */
1596struct mwl8k_cmd_802_11_get_stat {
1597 struct mwl8k_cmd_pkt header;
a66098da
LB		 1598 __le32 stats[64];
1599} __attribute__((packed));
1600
1601#define MWL8K_STAT_ACK_FAILURE 9
1602#define MWL8K_STAT_RTS_FAILURE 12
1603#define MWL8K_STAT_FCS_ERROR 24
1604#define MWL8K_STAT_RTS_SUCCESS 11
1605
1606static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1607 struct ieee80211_low_level_stats *stats)
1608{
1609 struct mwl8k_cmd_802_11_get_stat *cmd;
1610 int rc;
1611
1612 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1613 if (cmd == NULL)
1614 return -ENOMEM;
1615
1616 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1617 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1618
1619 rc = mwl8k_post_cmd(hw, &cmd->header);
1620 if (!rc) {
1621 stats->dot11ACKFailureCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1623 stats->dot11RTSFailureCount =
1624 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1625 stats->dot11FCSErrorCount =
1626 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1627 stats->dot11RTSSuccessCount =
1628 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1629 }
1630 kfree(cmd);
1631
1632 return rc;
1633}
1634
1635/*
1636 * CMD_802_11_RADIO_CONTROL.
1637 */
1638struct mwl8k_cmd_802_11_radio_control {
1639 struct mwl8k_cmd_pkt header;
1640 __le16 action;
1641 __le16 control;
1642 __le16 radio_on;
1643} __attribute__((packed));
1644
c46563b7
LB		 1645static int
1646mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1647{
1648 struct mwl8k_priv *priv = hw->priv;
1649 struct mwl8k_cmd_802_11_radio_control *cmd;
1650 int rc;
1651
c46563b7 1652 if (enable == priv->radio_on && !force)
a66098da
LB		 1653 return 0;
1654
a66098da
LB		 1655 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1656 if (cmd == NULL)
1657 return -ENOMEM;
1658
1659 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1660 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1661 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1662 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1663 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1664
1665 rc = mwl8k_post_cmd(hw, &cmd->header);
1666 kfree(cmd);
1667
1668 if (!rc)
c46563b7 1669 priv->radio_on = enable;
a66098da
LB		 1670
1671 return rc;
1672}
1673
c46563b7
LB		 1674static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1675{
1676 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1677}
1678
1679static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1680{
1681 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1682}
1683
a66098da
LB		 1684static int
1685mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1686{
1687 struct mwl8k_priv *priv;
1688
1689 if (hw == NULL || hw->priv == NULL)
1690 return -EINVAL;
1691 priv = hw->priv;
1692
68ce3884 1693 priv->radio_short_preamble = short_preamble;
a66098da 1694
c46563b7 1695 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1696}
1697
1698/*
1699 * CMD_802_11_RF_TX_POWER.
1700 */
1701#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1702
1703struct mwl8k_cmd_802_11_rf_tx_power {
1704 struct mwl8k_cmd_pkt header;
1705 __le16 action;
1706 __le16 support_level;
1707 __le16 current_level;
1708 __le16 reserved;
1709 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1710} __attribute__((packed));
1711
1712static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1713{
1714 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1715 int rc;
1716
1717 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1718 if (cmd == NULL)
1719 return -ENOMEM;
1720
1721 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1722 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1723 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1724 cmd->support_level = cpu_to_le16(dBm);
1725
1726 rc = mwl8k_post_cmd(hw, &cmd->header);
1727 kfree(cmd);
1728
1729 return rc;
1730}
1731
1732/*
1733 * CMD_SET_PRE_SCAN.
1734 */
1735struct mwl8k_cmd_set_pre_scan {
1736 struct mwl8k_cmd_pkt header;
1737} __attribute__((packed));
1738
1739static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1740{
1741 struct mwl8k_cmd_set_pre_scan *cmd;
1742 int rc;
1743
1744 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1745 if (cmd == NULL)
1746 return -ENOMEM;
1747
1748 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1749 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1750
1751 rc = mwl8k_post_cmd(hw, &cmd->header);
1752 kfree(cmd);
1753
1754 return rc;
1755}
1756
1757/*
1758 * CMD_SET_POST_SCAN.
1759 */
1760struct mwl8k_cmd_set_post_scan {
1761 struct mwl8k_cmd_pkt header;
1762 __le32 isibss;
d89173f2 1763 __u8 bssid[ETH_ALEN];
a66098da
LB		 1764} __attribute__((packed));
1765
1766static int
ce9e2e1b 1767mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1768{
1769 struct mwl8k_cmd_set_post_scan *cmd;
1770 int rc;
1771
1772 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1773 if (cmd == NULL)
1774 return -ENOMEM;
1775
1776 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1777 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1778 cmd->isibss = 0;
d89173f2 1779 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1780
1781 rc = mwl8k_post_cmd(hw, &cmd->header);
1782 kfree(cmd);
1783
1784 return rc;
1785}
1786
1787/*
1788 * CMD_SET_RF_CHANNEL.
1789 */
1790struct mwl8k_cmd_set_rf_channel {
1791 struct mwl8k_cmd_pkt header;
1792 __le16 action;
1793 __u8 current_channel;
1794 __le32 channel_flags;
1795} __attribute__((packed));
1796
1797static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1798 struct ieee80211_channel *channel)
1799{
1800 struct mwl8k_cmd_set_rf_channel *cmd;
1801 int rc;
1802
1803 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1804 if (cmd == NULL)
1805 return -ENOMEM;
1806
1807 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1808 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1809 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1810 cmd->current_channel = channel->hw_value;
1811 if (channel->band == IEEE80211_BAND_2GHZ)
1812 cmd->channel_flags = cpu_to_le32(0x00000081);
1813 else
1814 cmd->channel_flags = cpu_to_le32(0x00000000);
1815
1816 rc = mwl8k_post_cmd(hw, &cmd->header);
1817 kfree(cmd);
1818
1819 return rc;
1820}
1821
1822/*
1823 * CMD_SET_SLOT.
1824 */
1825struct mwl8k_cmd_set_slot {
1826 struct mwl8k_cmd_pkt header;
1827 __le16 action;
1828 __u8 short_slot;
1829} __attribute__((packed));
1830
5539bb51 1831static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 1832{
1833 struct mwl8k_cmd_set_slot *cmd;
1834 int rc;
1835
1836 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1837 if (cmd == NULL)
1838 return -ENOMEM;
1839
1840 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1841 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1842 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 1843 cmd->short_slot = short_slot_time;
a66098da
LB		 1844
1845 rc = mwl8k_post_cmd(hw, &cmd->header);
1846 kfree(cmd);
1847
1848 return rc;
1849}
1850
1851/*
1852 * CMD_MIMO_CONFIG.
1853 */
1854struct mwl8k_cmd_mimo_config {
1855 struct mwl8k_cmd_pkt header;
1856 __le32 action;
1857 __u8 rx_antenna_map;
1858 __u8 tx_antenna_map;
1859} __attribute__((packed));
1860
1861static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1862{
1863 struct mwl8k_cmd_mimo_config *cmd;
1864 int rc;
1865
1866 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1867 if (cmd == NULL)
1868 return -ENOMEM;
1869
1870 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1871 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1872 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1873 cmd->rx_antenna_map = rx;
1874 cmd->tx_antenna_map = tx;
1875
1876 rc = mwl8k_post_cmd(hw, &cmd->header);
1877 kfree(cmd);
1878
1879 return rc;
1880}
1881
1882/*
1883 * CMD_ENABLE_SNIFFER.
1884 */
1885struct mwl8k_cmd_enable_sniffer {
1886 struct mwl8k_cmd_pkt header;
1887 __le32 action;
1888} __attribute__((packed));
1889
1890static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1891{
1892 struct mwl8k_cmd_enable_sniffer *cmd;
1893 int rc;
1894
1895 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1896 if (cmd == NULL)
1897 return -ENOMEM;
1898
1899 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1900 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1901 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1902
1903 rc = mwl8k_post_cmd(hw, &cmd->header);
1904 kfree(cmd);
1905
1906 return rc;
1907}
1908
1909/*
ce9e2e1b 1910 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 1911 */
1912struct mwl8k_cmd_set_rate_adapt_mode {
1913 struct mwl8k_cmd_pkt header;
1914 __le16 action;
1915 __le16 mode;
1916} __attribute__((packed));
1917
1918static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1919{
1920 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1921 int rc;
1922
1923 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1924 if (cmd == NULL)
1925 return -ENOMEM;
1926
1927 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1928 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1929 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1930 cmd->mode = cpu_to_le16(mode);
1931
1932 rc = mwl8k_post_cmd(hw, &cmd->header);
1933 kfree(cmd);
1934
1935 return rc;
1936}
1937
1938/*
1939 * CMD_SET_WMM_MODE.
1940 */
1941struct mwl8k_cmd_set_wmm {
1942 struct mwl8k_cmd_pkt header;
1943 __le16 action;
1944} __attribute__((packed));
1945
1946static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1947{
1948 struct mwl8k_priv *priv = hw->priv;
1949 struct mwl8k_cmd_set_wmm *cmd;
1950 int rc;
1951
1952 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1953 if (cmd == NULL)
1954 return -ENOMEM;
1955
1956 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1957 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 1958 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 1959
1960 rc = mwl8k_post_cmd(hw, &cmd->header);
1961 kfree(cmd);
1962
1963 if (!rc)
0439b1f5 1964 priv->wmm_enabled = enable;
a66098da
LB		 1965
1966 return rc;
1967}
1968
1969/*
1970 * CMD_SET_RTS_THRESHOLD.
1971 */
1972struct mwl8k_cmd_rts_threshold {
1973 struct mwl8k_cmd_pkt header;
1974 __le16 action;
1975 __le16 threshold;
1976} __attribute__((packed));
1977
1978static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 1979 u16 action, u16 threshold)
a66098da
LB		 1980{
1981 struct mwl8k_cmd_rts_threshold *cmd;
1982 int rc;
1983
1984 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1985 if (cmd == NULL)
1986 return -ENOMEM;
1987
1988 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
1989 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1990 cmd->action = cpu_to_le16(action);
733d3067 1991 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 1992
1993 rc = mwl8k_post_cmd(hw, &cmd->header);
1994 kfree(cmd);
1995
1996 return rc;
1997}
1998
1999/*
2000 * CMD_SET_EDCA_PARAMS.
2001 */
2002struct mwl8k_cmd_set_edca_params {
2003 struct mwl8k_cmd_pkt header;
2004
2005 /* See MWL8K_SET_EDCA_XXX below */
2006 __le16 action;
2007
2008 /* TX opportunity in units of 32 us */
2009 __le16 txop;
2010
2011 /* Log exponent of max contention period: 0...15*/
2012 __u8 log_cw_max;
2013
2014 /* Log exponent of min contention period: 0...15 */
2015 __u8 log_cw_min;
2016
2017 /* Adaptive interframe spacing in units of 32us */
2018 __u8 aifs;
2019
2020 /* TX queue to configure */
2021 __u8 txq;
2022} __attribute__((packed));
2023
a66098da
LB		 2024#define MWL8K_SET_EDCA_CW 0x01
2025#define MWL8K_SET_EDCA_TXOP 0x02
2026#define MWL8K_SET_EDCA_AIFS 0x04
2027
2028#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2029 MWL8K_SET_EDCA_TXOP | \
2030 MWL8K_SET_EDCA_AIFS)
2031
2032static int
2033mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2034 __u16 cw_min, __u16 cw_max,
2035 __u8 aifs, __u16 txop)
2036{
2037 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2038 int rc;
2039
2040 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2041 if (cmd == NULL)
2042 return -ENOMEM;
2043
a66098da
LB		 2044 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2045 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2046 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2047 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2048 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2049 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2050 cmd->aifs = aifs;
2051 cmd->txq = qnum;
2052
2053 rc = mwl8k_post_cmd(hw, &cmd->header);
2054 kfree(cmd);
2055
2056 return rc;
2057}
2058
2059/*
2060 * CMD_FINALIZE_JOIN.
2061 */
2062
2063/* FJ beacon buffer size is compiled into the firmware. */
2064#define MWL8K_FJ_BEACON_MAXLEN 128
2065
2066struct mwl8k_cmd_finalize_join {
2067 struct mwl8k_cmd_pkt header;
2068 __le32 sleep_interval; /* Number of beacon periods to sleep */
2069 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2070} __attribute__((packed));
2071
2072static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2073 __u16 framelen, __u16 dtim)
2074{
2075 struct mwl8k_cmd_finalize_join *cmd;
2076 struct ieee80211_mgmt *payload = frame;
2077 u16 hdrlen;
2078 u32 payload_len;
2079 int rc;
2080
2081 if (frame == NULL)
2082 return -EINVAL;
2083
2084 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2085 if (cmd == NULL)
2086 return -ENOMEM;
2087
2088 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2089 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2090 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2091
2092 hdrlen = ieee80211_hdrlen(payload->frame_control);
2093
2094 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2095
2096 /* XXX TBD Might just have to abort and return an error */
2097 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2098 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2099 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2100 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2101
ce9e2e1b
LB		 2102 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2103 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2104
2105 if (payload && payload_len)
2106 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2107
2108 rc = mwl8k_post_cmd(hw, &cmd->header);
2109 kfree(cmd);
2110 return rc;
2111}
2112
2113/*
2114 * CMD_UPDATE_STADB.
2115 */
2116struct mwl8k_cmd_update_sta_db {
2117 struct mwl8k_cmd_pkt header;
2118
2119 /* See STADB_ACTION_TYPE */
2120 __le32 action;
2121
2122 /* Peer MAC address */
d89173f2 2123 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2124
2125 __le32 reserved;
2126
2127 /* Peer info - valid during add/update. */
2128 struct peer_capability_info peer_info;
2129} __attribute__((packed));
2130
2131static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2132 struct ieee80211_vif *vif, __u32 action)
2133{
2134 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2135 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2136 struct mwl8k_cmd_update_sta_db *cmd;
2137 struct peer_capability_info *peer_info;
2138 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2139 int rc;
2140 __u8 count, *rates;
2141
2142 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2143 if (cmd == NULL)
2144 return -ENOMEM;
2145
2146 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2147 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2148
2149 cmd->action = cpu_to_le32(action);
2150 peer_info = &cmd->peer_info;
d89173f2 2151 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2152
2153 switch (action) {
2154 case MWL8K_STA_DB_ADD_ENTRY:
2155 case MWL8K_STA_DB_MODIFY_ENTRY:
2156 /* Build peer_info block */
2157 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2158 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2159 peer_info->interop = 1;
2160 peer_info->amsdu_enabled = 0;
2161
2162 rates = peer_info->legacy_rates;
ce9e2e1b 2163 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2164 rates[count] = bitrates[count].hw_value;
2165
2166 rc = mwl8k_post_cmd(hw, &cmd->header);
2167 if (rc == 0)
2168 mv_vif->peer_id = peer_info->station_id;
2169
2170 break;
2171
2172 case MWL8K_STA_DB_DEL_ENTRY:
2173 case MWL8K_STA_DB_FLUSH:
2174 default:
2175 rc = mwl8k_post_cmd(hw, &cmd->header);
2176 if (rc == 0)
2177 mv_vif->peer_id = 0;
2178 break;
2179 }
2180 kfree(cmd);
2181
2182 return rc;
2183}
2184
2185/*
2186 * CMD_SET_AID.
2187 */
a66098da
LB		 2188#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2189
2190#define MWL8K_FRAME_PROT_DISABLED 0x00
2191#define MWL8K_FRAME_PROT_11G 0x07
2192#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2193#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2194
2195struct mwl8k_cmd_update_set_aid {
2196 struct mwl8k_cmd_pkt header;
2197 __le16 aid;
2198
2199 /* AP's MAC address (BSSID) */
d89173f2 2200 __u8 bssid[ETH_ALEN];
a66098da
LB		 2201 __le16 protection_mode;
2202 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2203} __attribute__((packed));
2204
2205static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2206 struct ieee80211_vif *vif)
2207{
2208 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2209 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2210 struct mwl8k_cmd_update_set_aid *cmd;
2211 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2212 int count;
2213 u16 prot_mode;
2214 int rc;
2215
2216 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2217 if (cmd == NULL)
2218 return -ENOMEM;
2219
2220 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2221 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2222 cmd->aid = cpu_to_le16(info->aid);
2223
d89173f2 2224 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2225
a66098da
LB		 2226 if (info->use_cts_prot) {
2227 prot_mode = MWL8K_FRAME_PROT_11G;
2228 } else {
9ed6bcce 2229 switch (info->ht_operation_mode &
a66098da
LB		 2230 IEEE80211_HT_OP_MODE_PROTECTION) {
2231 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2232 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2233 break;
2234 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2235 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2236 break;
2237 default:
2238 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2239 break;
2240 }
2241 }
a66098da
LB		 2242 cmd->protection_mode = cpu_to_le16(prot_mode);
2243
2244 for (count = 0; count < mv_vif->legacy_nrates; count++)
2245 cmd->supp_rates[count] = bitrates[count].hw_value;
2246
2247 rc = mwl8k_post_cmd(hw, &cmd->header);
2248 kfree(cmd);
2249
2250 return rc;
2251}
2252
2253/*
2254 * CMD_SET_RATE.
2255 */
2256struct mwl8k_cmd_update_rateset {
2257 struct mwl8k_cmd_pkt header;
2258 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2259
2260 /* Bitmap for supported MCS codes. */
2261 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2262 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2263} __attribute__((packed));
2264
2265static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2266 struct ieee80211_vif *vif)
2267{
2268 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2269 struct mwl8k_cmd_update_rateset *cmd;
2270 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2271 int count;
2272 int rc;
2273
2274 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2275 if (cmd == NULL)
2276 return -ENOMEM;
2277
2278 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2279 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2280
2281 for (count = 0; count < mv_vif->legacy_nrates; count++)
2282 cmd->legacy_rates[count] = bitrates[count].hw_value;
2283
2284 rc = mwl8k_post_cmd(hw, &cmd->header);
2285 kfree(cmd);
2286
2287 return rc;
2288}
2289
2290/*
2291 * CMD_USE_FIXED_RATE.
2292 */
2293#define MWL8K_RATE_TABLE_SIZE 8
2294#define MWL8K_UCAST_RATE 0
a66098da
LB		 2295#define MWL8K_USE_AUTO_RATE 0x0002
2296
2297struct mwl8k_rate_entry {
2298 /* Set to 1 if HT rate, 0 if legacy. */
2299 __le32 is_ht_rate;
2300
2301 /* Set to 1 to use retry_count field. */
2302 __le32 enable_retry;
2303
2304 /* Specified legacy rate or MCS. */
2305 __le32 rate;
2306
2307 /* Number of allowed retries. */
2308 __le32 retry_count;
2309} __attribute__((packed));
2310
2311struct mwl8k_rate_table {
2312 /* 1 to allow specified rate and below */
2313 __le32 allow_rate_drop;
2314 __le32 num_rates;
2315 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2316} __attribute__((packed));
2317
2318struct mwl8k_cmd_use_fixed_rate {
2319 struct mwl8k_cmd_pkt header;
2320 __le32 action;
2321 struct mwl8k_rate_table rate_table;
2322
2323 /* Unicast, Broadcast or Multicast */
2324 __le32 rate_type;
2325 __le32 reserved1;
2326 __le32 reserved2;
2327} __attribute__((packed));
2328
2329static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2330 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2331{
2332 struct mwl8k_cmd_use_fixed_rate *cmd;
2333 int count;
2334 int rc;
2335
2336 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2337 if (cmd == NULL)
2338 return -ENOMEM;
2339
2340 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2341 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2342
2343 cmd->action = cpu_to_le32(action);
2344 cmd->rate_type = cpu_to_le32(rate_type);
2345
2346 if (rate_table != NULL) {
c2c357ce
LB		 2347 /*
2348 * Copy over each field manually so that endian
2349 * conversion can be done.
2350 */
a66098da
LB		 2351 cmd->rate_table.allow_rate_drop =
2352 cpu_to_le32(rate_table->allow_rate_drop);
2353 cmd->rate_table.num_rates =
2354 cpu_to_le32(rate_table->num_rates);
2355
2356 for (count = 0; count < rate_table->num_rates; count++) {
2357 struct mwl8k_rate_entry *dst =
2358 &cmd->rate_table.rate_entry[count];
2359 struct mwl8k_rate_entry *src =
2360 &rate_table->rate_entry[count];
2361
2362 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2363 dst->enable_retry = cpu_to_le32(src->enable_retry);
2364 dst->rate = cpu_to_le32(src->rate);
2365 dst->retry_count = cpu_to_le32(src->retry_count);
2366 }
2367 }
2368
2369 rc = mwl8k_post_cmd(hw, &cmd->header);
2370 kfree(cmd);
2371
2372 return rc;
2373}
2374
2375
2376/*
2377 * Interrupt handling.
2378 */
2379static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2380{
2381 struct ieee80211_hw *hw = dev_id;
2382 struct mwl8k_priv *priv = hw->priv;
2383 u32 status;
2384
2385 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2386 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2387
a66098da
LB		 2388 if (!status)
2389 return IRQ_NONE;
2390
2391 if (status & MWL8K_A2H_INT_TX_DONE)
2392 tasklet_schedule(&priv->tx_reclaim_task);
2393
2394 if (status & MWL8K_A2H_INT_RX_READY) {
2395 while (rxq_process(hw, 0, 1))
2396 rxq_refill(hw, 0, 1);
2397 }
2398
2399 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2400 if (priv->hostcmd_wait != NULL)
a66098da 2401 complete(priv->hostcmd_wait);
a66098da
LB		 2402 }
2403
2404 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2405 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2406 priv->radio_on && priv->pending_tx_pkts)
618952a7 2407 mwl8k_tx_start(priv);
a66098da
LB		 2408 }
2409
2410 return IRQ_HANDLED;
2411}
2412
2413
2414/*
2415 * Core driver operations.
2416 */
2417static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2418{
2419 struct mwl8k_priv *priv = hw->priv;
2420 int index = skb_get_queue_mapping(skb);
2421 int rc;
2422
2423 if (priv->current_channel == NULL) {
2424 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2425 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2426 dev_kfree_skb(skb);
2427 return NETDEV_TX_OK;
2428 }
2429
2430 rc = mwl8k_txq_xmit(hw, index, skb);
2431
2432 return rc;
2433}
2434
a66098da
LB		 2435static int mwl8k_start(struct ieee80211_hw *hw)
2436{
a66098da
LB		 2437 struct mwl8k_priv *priv = hw->priv;
2438 int rc;
2439
a66098da
LB		 2440 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2441 IRQF_SHARED, MWL8K_NAME, hw);
2442 if (rc) {
2443 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2444 wiphy_name(hw->wiphy));
2ec610cb 2445 return -EIO;
a66098da
LB		 2446 }
2447
2ec610cb
LB		 2448 /* Enable tx reclaim tasklet */
2449 tasklet_enable(&priv->tx_reclaim_task);
2450
a66098da 2451 /* Enable interrupts */
c23b5a69 2452 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2453
2ec610cb
LB		 2454 rc = mwl8k_fw_lock(hw);
2455 if (!rc) {
2456 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2457
2ec610cb
LB		 2458 if (!rc)
2459 rc = mwl8k_cmd_set_pre_scan(hw);
a66098da 2460
2ec610cb
LB		 2461 if (!rc)
2462 rc = mwl8k_cmd_set_post_scan(hw,
2463 "\x00\x00\x00\x00\x00\x00");
2464
2465 if (!rc)
2466 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2467
2ec610cb
LB		 2468 if (!rc)
2469 rc = mwl8k_set_wmm(hw, 0);
a66098da 2470
2ec610cb
LB		 2471 if (!rc)
2472 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2473
2ec610cb
LB		 2474 mwl8k_fw_unlock(hw);
2475 }
2476
2477 if (rc) {
2478 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2479 free_irq(priv->pdev->irq, hw);
2480 tasklet_disable(&priv->tx_reclaim_task);
2481 }
a66098da
LB		 2482
2483 return rc;
2484}
2485
a66098da
LB		 2486static void mwl8k_stop(struct ieee80211_hw *hw)
2487{
a66098da
LB		 2488 struct mwl8k_priv *priv = hw->priv;
2489 int i;
2490
d3cea0b8 2491 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2492
2493 ieee80211_stop_queues(hw);
2494
a66098da 2495 /* Disable interrupts */
a66098da 2496 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2497 free_irq(priv->pdev->irq, hw);
2498
2499 /* Stop finalize join worker */
2500 cancel_work_sync(&priv->finalize_join_worker);
2501 if (priv->beacon_skb != NULL)
2502 dev_kfree_skb(priv->beacon_skb);
2503
2504 /* Stop tx reclaim tasklet */
2505 tasklet_disable(&priv->tx_reclaim_task);
2506
2507 /* Stop config thread */
2508 flush_workqueue(priv->config_wq);
2509
2510 /* Return all skbs to mac80211 */
2511 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2512 mwl8k_txq_reclaim(hw, i, 1);
2513}
2514
2515static int mwl8k_add_interface(struct ieee80211_hw *hw,
2516 struct ieee80211_if_init_conf *conf)
2517{
2518 struct mwl8k_priv *priv = hw->priv;
2519 struct mwl8k_vif *mwl8k_vif;
2520
2521 /*
2522 * We only support one active interface at a time.
2523 */
2524 if (priv->vif != NULL)
2525 return -EBUSY;
2526
2527 /*
2528 * We only support managed interfaces for now.
2529 */
240e86ef 2530 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2531 return -EINVAL;
2532
2533 /* Clean out driver private area */
2534 mwl8k_vif = MWL8K_VIF(conf->vif);
2535 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2536
2537 /* Save the mac address */
d89173f2 2538 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2539
2540 /* Back pointer to parent config block */
2541 mwl8k_vif->priv = priv;
2542
2543 /* Setup initial PHY parameters */
ce9e2e1b 2544 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2545 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2546 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2547
2548 /* Set Initial sequence number to zero */
2549 mwl8k_vif->seqno = 0;
2550
2551 priv->vif = conf->vif;
2552 priv->current_channel = NULL;
2553
2554 return 0;
2555}
2556
2557static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2558 struct ieee80211_if_init_conf *conf)
2559{
2560 struct mwl8k_priv *priv = hw->priv;
2561
2562 if (priv->vif == NULL)
2563 return;
2564
2565 priv->vif = NULL;
2566}
2567
ee03a932 2568static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2569{
a66098da
LB		 2570 struct ieee80211_conf *conf = &hw->conf;
2571 struct mwl8k_priv *priv = hw->priv;
ee03a932 2572 int rc;
a66098da 2573
7595d67a
LB		 2574 if (conf->flags & IEEE80211_CONF_IDLE) {
2575 mwl8k_cmd_802_11_radio_disable(hw);
2576 priv->current_channel = NULL;
ee03a932 2577 return 0;
7595d67a
LB		 2578 }
2579
ee03a932
LB		 2580 rc = mwl8k_fw_lock(hw);
2581 if (rc)
2582 return rc;
a66098da 2583
ee03a932
LB		 2584 rc = mwl8k_cmd_802_11_radio_enable(hw);
2585 if (rc)
2586 goto out;
a66098da 2587
ee03a932
LB		 2588 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2589 if (rc)
2590 goto out;
2591
2592 priv->current_channel = conf->channel;
a66098da
LB		 2593
2594 if (conf->power_level > 18)
2595 conf->power_level = 18;
ee03a932
LB		 2596 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2597 if (rc)
2598 goto out;
a66098da
LB		 2599
2600 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2601 rc = -EINVAL;
2602
ee03a932
LB		 2603out:
2604 mwl8k_fw_unlock(hw);
a66098da 2605
ee03a932 2606 return rc;
a66098da
LB		 2607}
2608
3a980d0a
LB		 2609static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2610 struct ieee80211_vif *vif,
2611 struct ieee80211_bss_conf *info,
2612 u32 changed)
a66098da 2613{
a66098da
LB		 2614 struct mwl8k_priv *priv = hw->priv;
2615 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 2616 int rc;
2617
2618 if (changed & BSS_CHANGED_BSSID)
2619 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2620
2621 if ((changed & BSS_CHANGED_ASSOC) == 0)
2622 return;
a66098da 2623
a66098da
LB		 2624 priv->capture_beacon = false;
2625
3a980d0a 2626 rc = mwl8k_fw_lock(hw);
942457d6 2627 if (rc)
3a980d0a
LB		 2628 return;
2629
a66098da
LB		 2630 if (info->assoc) {
2631 memcpy(&mwl8k_vif->bss_info, info,
2632 sizeof(struct ieee80211_bss_conf));
2633
2634 /* Install rates */
3a980d0a
LB		 2635 rc = mwl8k_update_rateset(hw, vif);
2636 if (rc)
2637 goto out;
a66098da
LB		 2638
2639 /* Turn on rate adaptation */
3a980d0a
LB		 2640 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2641 MWL8K_UCAST_RATE, NULL);
2642 if (rc)
2643 goto out;
a66098da
LB		 2644
2645 /* Set radio preamble */
3a980d0a
LB		 2646 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2647 if (rc)
2648 goto out;
a66098da
LB		 2649
2650 /* Set slot time */
3a980d0a
LB		 2651 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2652 if (rc)
2653 goto out;
a66098da
LB		 2654
2655 /* Update peer rate info */
3a980d0a
LB		 2656 rc = mwl8k_cmd_update_sta_db(hw, vif,
2657 MWL8K_STA_DB_MODIFY_ENTRY);
2658 if (rc)
2659 goto out;
a66098da
LB		 2660
2661 /* Set AID */
3a980d0a
LB		 2662 rc = mwl8k_cmd_set_aid(hw, vif);
2663 if (rc)
2664 goto out;
a66098da
LB		 2665
2666 /*
2667 * Finalize the join. Tell rx handler to process
2668 * next beacon from our BSSID.
2669 */
d89173f2 2670 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2671 priv->capture_beacon = true;
2672 } else {
3a980d0a 2673 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 2674 memset(&mwl8k_vif->bss_info, 0,
2675 sizeof(struct ieee80211_bss_conf));
d89173f2 2676 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2677 }
2678
3a980d0a
LB		 2679out:
2680 mwl8k_fw_unlock(hw);
a66098da
LB		 2681}
2682
e81cd2d6
LB		 2683static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2684 int mc_count, struct dev_addr_list *mclist)
2685{
2686 struct mwl8k_cmd_pkt *cmd;
2687
2688 cmd = __mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
2689
2690 return (unsigned long)cmd;
2691}
2692
e6935ea1
LB		 2693static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2694 unsigned int changed_flags,
2695 unsigned int *total_flags,
2696 u64 multicast)
2697{
2698 struct mwl8k_priv *priv = hw->priv;
e81cd2d6 2699 struct mwl8k_cmd_pkt *multicast_adr_cmd;
a66098da 2700
e6935ea1
LB		 2701 /* Clear unsupported feature flags */
2702 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
a66098da 2703
e6935ea1
LB		 2704 if (mwl8k_fw_lock(hw))
2705 return;
a66098da 2706
e6935ea1
LB		 2707 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2708 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2709 mwl8k_cmd_set_pre_scan(hw);
a66098da 2710 else {
a94cc97e
LB		 2711 u8 *bssid;
2712
2713 bssid = "\x00\x00\x00\x00\x00\x00";
2714 if (priv->vif != NULL)
2715 bssid = MWL8K_VIF(priv->vif)->bssid;
2716
e6935ea1 2717 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 2718 }
2719 }
2720
e6935ea1
LB		 2721 multicast_adr_cmd = (void *)(unsigned long)multicast;
2722 if (multicast_adr_cmd != NULL) {
2723 mwl8k_post_cmd(hw, multicast_adr_cmd);
2724 kfree(multicast_adr_cmd);
2725 }
a66098da 2726
e6935ea1 2727 mwl8k_fw_unlock(hw);
a66098da
LB		 2728}
2729
a66098da
LB		 2730static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2731{
733d3067 2732 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 2733}
2734
a66098da
LB		 2735static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2736 const struct ieee80211_tx_queue_params *params)
2737{
3e4f542c 2738 struct mwl8k_priv *priv = hw->priv;
a66098da 2739 int rc;
a66098da 2740
3e4f542c
LB		 2741 rc = mwl8k_fw_lock(hw);
2742 if (!rc) {
2743 if (!priv->wmm_enabled)
2744 rc = mwl8k_set_wmm(hw, 1);
a66098da 2745
3e4f542c
LB		 2746 if (!rc)
2747 rc = mwl8k_set_edca_params(hw, queue,
2748 params->cw_min,
2749 params->cw_max,
2750 params->aifs,
2751 params->txop);
2752
2753 mwl8k_fw_unlock(hw);
a66098da 2754 }
3e4f542c 2755
a66098da
LB		 2756 return rc;
2757}
2758
2759static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2760 struct ieee80211_tx_queue_stats *stats)
2761{
2762 struct mwl8k_priv *priv = hw->priv;
2763 struct mwl8k_tx_queue *txq;
2764 int index;
2765
2766 spin_lock_bh(&priv->tx_lock);
2767 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2768 txq = priv->txq + index;
2769 memcpy(&stats[index], &txq->tx_stats,
2770 sizeof(struct ieee80211_tx_queue_stats));
2771 }
2772 spin_unlock_bh(&priv->tx_lock);
a66098da 2773
954ef509 2774 return 0;
a66098da
LB		 2775}
2776
2777static int mwl8k_get_stats(struct ieee80211_hw *hw,
2778 struct ieee80211_low_level_stats *stats)
2779{
954ef509 2780 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 2781}
2782
2783static const struct ieee80211_ops mwl8k_ops = {
2784 .tx = mwl8k_tx,
2785 .start = mwl8k_start,
2786 .stop = mwl8k_stop,
2787 .add_interface = mwl8k_add_interface,
2788 .remove_interface = mwl8k_remove_interface,
2789 .config = mwl8k_config,
a66098da 2790 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 2791 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 2792 .configure_filter = mwl8k_configure_filter,
2793 .set_rts_threshold = mwl8k_set_rts_threshold,
2794 .conf_tx = mwl8k_conf_tx,
2795 .get_tx_stats = mwl8k_get_tx_stats,
2796 .get_stats = mwl8k_get_stats,
2797};
2798
2799static void mwl8k_tx_reclaim_handler(unsigned long data)
2800{
2801 int i;
2802 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2803 struct mwl8k_priv *priv = hw->priv;
2804
2805 spin_lock_bh(&priv->tx_lock);
2806 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2807 mwl8k_txq_reclaim(hw, i, 0);
2808
88de754a 2809 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 2810 complete(priv->tx_wait);
2811 priv->tx_wait = NULL;
a66098da
LB		 2812 }
2813 spin_unlock_bh(&priv->tx_lock);
2814}
2815
2816static void mwl8k_finalize_join_worker(struct work_struct *work)
2817{
2818 struct mwl8k_priv *priv =
2819 container_of(work, struct mwl8k_priv, finalize_join_worker);
2820 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 2821 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 2822
2823 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2824 dev_kfree_skb(skb);
2825
2826 priv->beacon_skb = NULL;
2827}
2828
2829static int __devinit mwl8k_probe(struct pci_dev *pdev,
2830 const struct pci_device_id *id)
2831{
2aa7b01f 2832 static int printed_version = 0;
a66098da
LB		 2833 struct ieee80211_hw *hw;
2834 struct mwl8k_priv *priv;
a66098da
LB		 2835 int rc;
2836 int i;
2aa7b01f
LB		 2837
2838 if (!printed_version) {
2839 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2840 printed_version = 1;
2841 }
a66098da
LB		 2842
2843 rc = pci_enable_device(pdev);
2844 if (rc) {
2845 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2846 MWL8K_NAME);
2847 return rc;
2848 }
2849
2850 rc = pci_request_regions(pdev, MWL8K_NAME);
2851 if (rc) {
2852 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2853 MWL8K_NAME);
2854 return rc;
2855 }
2856
2857 pci_set_master(pdev);
2858
2859 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2860 if (hw == NULL) {
2861 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2862 rc = -ENOMEM;
2863 goto err_free_reg;
2864 }
2865
2866 priv = hw->priv;
2867 priv->hw = hw;
2868 priv->pdev = pdev;
0439b1f5 2869 priv->wmm_enabled = false;
a66098da 2870 priv->pending_tx_pkts = 0;
a66098da 2871
a66098da
LB		 2872 SET_IEEE80211_DEV(hw, &pdev->dev);
2873 pci_set_drvdata(pdev, hw);
2874
2875 priv->regs = pci_iomap(pdev, 1, 0x10000);
2876 if (priv->regs == NULL) {
c2c357ce
LB		 2877 printk(KERN_ERR "%s: Cannot map device memory\n",
2878 wiphy_name(hw->wiphy));
a66098da
LB		 2879 goto err_iounmap;
2880 }
2881
2882 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2883 priv->band.band = IEEE80211_BAND_2GHZ;
2884 priv->band.channels = priv->channels;
2885 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2886 priv->band.bitrates = priv->rates;
2887 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2888 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2889
2890 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2891 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2892
2893 /*
2894 * Extra headroom is the size of the required DMA header
2895 * minus the size of the smallest 802.11 frame (CTS frame).
2896 */
2897 hw->extra_tx_headroom =
2898 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2899
2900 hw->channel_change_time = 10;
2901
2902 hw->queues = MWL8K_TX_QUEUES;
2903
240e86ef 2904 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
a66098da
LB		 2905
2906 /* Set rssi and noise values to dBm */
ce9e2e1b 2907 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 2908 hw->vif_data_size = sizeof(struct mwl8k_vif);
2909 priv->vif = NULL;
2910
2911 /* Set default radio state and preamble */
c46563b7 2912 priv->radio_on = 0;
68ce3884 2913 priv->radio_short_preamble = 0;
a66098da
LB		 2914
2915 /* Finalize join worker */
2916 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2917
2918 /* TX reclaim tasklet */
2919 tasklet_init(&priv->tx_reclaim_task,
2920 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2921 tasklet_disable(&priv->tx_reclaim_task);
2922
2923 /* Config workthread */
2924 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
2925 if (priv->config_wq == NULL)
2926 goto err_iounmap;
2927
2928 /* Power management cookie */
2929 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2930 if (priv->cookie == NULL)
2931 goto err_iounmap;
2932
2933 rc = mwl8k_rxq_init(hw, 0);
2934 if (rc)
2935 goto err_iounmap;
2936 rxq_refill(hw, 0, INT_MAX);
2937
618952a7
LB		 2938 mutex_init(&priv->fw_mutex);
2939 priv->fw_mutex_owner = NULL;
2940 priv->fw_mutex_depth = 0;
618952a7
LB		 2941 priv->hostcmd_wait = NULL;
2942
a66098da
LB		 2943 spin_lock_init(&priv->tx_lock);
2944
88de754a
LB		 2945 priv->tx_wait = NULL;
2946
a66098da
LB		 2947 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2948 rc = mwl8k_txq_init(hw, i);
2949 if (rc)
2950 goto err_free_queues;
2951 }
2952
2953 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 2954 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2955 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
2956 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
2957
2958 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2959 IRQF_SHARED, MWL8K_NAME, hw);
2960 if (rc) {
2961 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2962 wiphy_name(hw->wiphy));
a66098da
LB		 2963 goto err_free_queues;
2964 }
2965
2966 /* Reset firmware and hardware */
2967 mwl8k_hw_reset(priv);
2968
2969 /* Ask userland hotplug daemon for the device firmware */
2970 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
2971 if (rc) {
c2c357ce
LB		 2972 printk(KERN_ERR "%s: Firmware files not found\n",
2973 wiphy_name(hw->wiphy));
a66098da
LB		 2974 goto err_free_irq;
2975 }
2976
2977 /* Load firmware into hardware */
c2c357ce 2978 rc = mwl8k_load_firmware(hw);
a66098da 2979 if (rc) {
c2c357ce
LB		 2980 printk(KERN_ERR "%s: Cannot start firmware\n",
2981 wiphy_name(hw->wiphy));
a66098da
LB		 2982 goto err_stop_firmware;
2983 }
2984
2985 /* Reclaim memory once firmware is successfully loaded */
2986 mwl8k_release_firmware(priv);
2987
2988 /*
2989 * Temporarily enable interrupts. Initial firmware host
2990 * commands use interrupts and avoids polling. Disable
2991 * interrupts when done.
2992 */
c23b5a69 2993 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2994
2995 /* Get config data, mac addrs etc */
2996 rc = mwl8k_cmd_get_hw_spec(hw);
2997 if (rc) {
c2c357ce
LB		 2998 printk(KERN_ERR "%s: Cannot initialise firmware\n",
2999 wiphy_name(hw->wiphy));
a66098da
LB		 3000 goto err_stop_firmware;
3001 }
3002
3003 /* Turn radio off */
c46563b7 3004 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3005 if (rc) {
c2c357ce 3006 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3007 goto err_stop_firmware;
3008 }
3009
3010 /* Disable interrupts */
a66098da 3011 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3012 free_irq(priv->pdev->irq, hw);
3013
3014 rc = ieee80211_register_hw(hw);
3015 if (rc) {
c2c357ce
LB		 3016 printk(KERN_ERR "%s: Cannot register device\n",
3017 wiphy_name(hw->wiphy));
a66098da
LB		 3018 goto err_stop_firmware;
3019 }
3020
2aa7b01f
LB		 3021 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3022 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3023 hw->wiphy->perm_addr,
3024 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3025 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3026
3027 return 0;
3028
3029err_stop_firmware:
3030 mwl8k_hw_reset(priv);
3031 mwl8k_release_firmware(priv);
3032
3033err_free_irq:
a66098da 3034 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3035 free_irq(priv->pdev->irq, hw);
3036
3037err_free_queues:
3038 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3039 mwl8k_txq_deinit(hw, i);
3040 mwl8k_rxq_deinit(hw, 0);
3041
3042err_iounmap:
3043 if (priv->cookie != NULL)
3044 pci_free_consistent(priv->pdev, 4,
3045 priv->cookie, priv->cookie_dma);
3046
3047 if (priv->regs != NULL)
3048 pci_iounmap(pdev, priv->regs);
3049
3050 if (priv->config_wq != NULL)
3051 destroy_workqueue(priv->config_wq);
3052
3053 pci_set_drvdata(pdev, NULL);
3054 ieee80211_free_hw(hw);
3055
3056err_free_reg:
3057 pci_release_regions(pdev);
3058 pci_disable_device(pdev);
3059
3060 return rc;
3061}
3062
230f7af0 3063static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3064{
3065 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3066}
3067
230f7af0 3068static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3069{
3070 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3071 struct mwl8k_priv *priv;
3072 int i;
3073
3074 if (hw == NULL)
3075 return;
3076 priv = hw->priv;
3077
3078 ieee80211_stop_queues(hw);
3079
60aa569f
LB		 3080 ieee80211_unregister_hw(hw);
3081
a66098da
LB		 3082 /* Remove tx reclaim tasklet */
3083 tasklet_kill(&priv->tx_reclaim_task);
3084
3085 /* Stop config thread */
3086 destroy_workqueue(priv->config_wq);
3087
3088 /* Stop hardware */
3089 mwl8k_hw_reset(priv);
3090
3091 /* Return all skbs to mac80211 */
3092 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3093 mwl8k_txq_reclaim(hw, i, 1);
3094
a66098da
LB		 3095 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3096 mwl8k_txq_deinit(hw, i);
3097
3098 mwl8k_rxq_deinit(hw, 0);
3099
c2c357ce 3100 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3101
3102 pci_iounmap(pdev, priv->regs);
3103 pci_set_drvdata(pdev, NULL);
3104 ieee80211_free_hw(hw);
3105 pci_release_regions(pdev);
3106 pci_disable_device(pdev);
3107}
3108
3109static struct pci_driver mwl8k_driver = {
3110 .name = MWL8K_NAME,
3111 .id_table = mwl8k_table,
3112 .probe = mwl8k_probe,
3113 .remove = __devexit_p(mwl8k_remove),
3114 .shutdown = __devexit_p(mwl8k_shutdown),
3115};
3116
3117static int __init mwl8k_init(void)
3118{
3119 return pci_register_driver(&mwl8k_driver);
3120}
3121
3122static void __exit mwl8k_exit(void)
3123{
3124 pci_unregister_driver(&mwl8k_driver);
3125}
3126
3127module_init(mwl8k_init);
3128module_exit(mwl8k_exit);
c2c357ce
LB		 3129
3130MODULE_DESCRIPTION(MWL8K_DESC);
3131MODULE_VERSION(MWL8K_VERSION);
3132MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3133MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror