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p54: more accurate rssi to dBm conversion
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW		 1/*
2 * Common code for mac80211 Prism54 drivers
3 *
4 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
c12abae3 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
eff1a59c 7 *
27df605e
JL		 8 * Based on:
9 * - the islsm (softmac prism54) driver, which is:
10 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
11 * - stlc45xx driver
9483407d 12 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
eff1a59c
MW		 13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/firmware.h>
21#include <linux/etherdevice.h>
22
23#include <net/mac80211.h>
24
25#include "p54.h"
26#include "p54common.h"
27
25900ef0
CL		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
eff1a59c
MW		 31MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32MODULE_DESCRIPTION("Softmac Prism54 common code");
33MODULE_LICENSE("GPL");
34MODULE_ALIAS("prism54common");
35
1b997534 36static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB		 37 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
38 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
39 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
40 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
41 { .bitrate = 60, .hw_value = 4, },
42 { .bitrate = 90, .hw_value = 5, },
43 { .bitrate = 120, .hw_value = 6, },
44 { .bitrate = 180, .hw_value = 7, },
45 { .bitrate = 240, .hw_value = 8, },
46 { .bitrate = 360, .hw_value = 9, },
47 { .bitrate = 480, .hw_value = 10, },
48 { .bitrate = 540, .hw_value = 11, },
49};
50
1b997534 51static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB		 52 { .center_freq = 2412, .hw_value = 1, },
53 { .center_freq = 2417, .hw_value = 2, },
54 { .center_freq = 2422, .hw_value = 3, },
55 { .center_freq = 2427, .hw_value = 4, },
56 { .center_freq = 2432, .hw_value = 5, },
57 { .center_freq = 2437, .hw_value = 6, },
58 { .center_freq = 2442, .hw_value = 7, },
59 { .center_freq = 2447, .hw_value = 8, },
60 { .center_freq = 2452, .hw_value = 9, },
61 { .center_freq = 2457, .hw_value = 10, },
62 { .center_freq = 2462, .hw_value = 11, },
63 { .center_freq = 2467, .hw_value = 12, },
64 { .center_freq = 2472, .hw_value = 13, },
65 { .center_freq = 2484, .hw_value = 14, },
66};
67
c2976ab0 68static struct ieee80211_supported_band band_2GHz = {
1b997534
CL		 69 .channels = p54_bgchannels,
70 .n_channels = ARRAY_SIZE(p54_bgchannels),
71 .bitrates = p54_bgrates,
72 .n_bitrates = ARRAY_SIZE(p54_bgrates),
73};
74
75static struct ieee80211_rate p54_arates[] = {
76 { .bitrate = 60, .hw_value = 4, },
77 { .bitrate = 90, .hw_value = 5, },
78 { .bitrate = 120, .hw_value = 6, },
79 { .bitrate = 180, .hw_value = 7, },
80 { .bitrate = 240, .hw_value = 8, },
81 { .bitrate = 360, .hw_value = 9, },
82 { .bitrate = 480, .hw_value = 10, },
83 { .bitrate = 540, .hw_value = 11, },
84};
85
86static struct ieee80211_channel p54_achannels[] = {
87 { .center_freq = 4920 },
88 { .center_freq = 4940 },
89 { .center_freq = 4960 },
90 { .center_freq = 4980 },
91 { .center_freq = 5040 },
92 { .center_freq = 5060 },
93 { .center_freq = 5080 },
94 { .center_freq = 5170 },
95 { .center_freq = 5180 },
96 { .center_freq = 5190 },
97 { .center_freq = 5200 },
98 { .center_freq = 5210 },
99 { .center_freq = 5220 },
100 { .center_freq = 5230 },
101 { .center_freq = 5240 },
102 { .center_freq = 5260 },
103 { .center_freq = 5280 },
104 { .center_freq = 5300 },
105 { .center_freq = 5320 },
106 { .center_freq = 5500 },
107 { .center_freq = 5520 },
108 { .center_freq = 5540 },
109 { .center_freq = 5560 },
110 { .center_freq = 5580 },
111 { .center_freq = 5600 },
112 { .center_freq = 5620 },
113 { .center_freq = 5640 },
114 { .center_freq = 5660 },
115 { .center_freq = 5680 },
116 { .center_freq = 5700 },
117 { .center_freq = 5745 },
118 { .center_freq = 5765 },
119 { .center_freq = 5785 },
120 { .center_freq = 5805 },
121 { .center_freq = 5825 },
122};
123
124static struct ieee80211_supported_band band_5GHz = {
125 .channels = p54_achannels,
126 .n_channels = ARRAY_SIZE(p54_achannels),
127 .bitrates = p54_arates,
128 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB		 129};
130
4e416a6f 131int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW		 132{
133 struct p54_common *priv = dev->priv;
134 struct bootrec_exp_if *exp_if;
135 struct bootrec *bootrec;
136 u32 *data = (u32 *)fw->data;
137 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
138 u8 *fw_version = NULL;
139 size_t len;
140 int i;
141
142 if (priv->rx_start)
4e416a6f 143 return 0;
eff1a59c
MW		 144
145 while (data < end_data && *data)
146 data++;
147
148 while (data < end_data && !*data)
149 data++;
150
151 bootrec = (struct bootrec *) data;
152
153 while (bootrec->data <= end_data &&
154 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
155 u32 code = le32_to_cpu(bootrec->code);
156 switch (code) {
157 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF		 158 priv->fw_interface = be32_to_cpup((__be32 *)
159 bootrec->data);
2b80848e 160 switch (priv->fw_interface) {
eff1a59c 161 case FW_LM86:
02e37ba1
CL		 162 case FW_LM20:
163 case FW_LM87: {
164 char *iftype = (char *)bootrec->data;
165 printk(KERN_INFO "%s: p54 detected a LM%c%c "
166 "firmware\n",
167 wiphy_name(dev->wiphy),
168 iftype[2], iftype[3]);
eff1a59c 169 break;
02e37ba1
CL		 170 }
171 case FW_FMAC:
eff1a59c 172 default:
02e37ba1
CL		 173 printk(KERN_ERR "%s: unsupported firmware\n",
174 wiphy_name(dev->wiphy));
175 return -ENODEV;
eff1a59c
MW		 176 }
177 break;
178 case BR_CODE_COMPONENT_VERSION:
179 /* 24 bytes should be enough for all firmwares */
180 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
181 fw_version = (unsigned char*)bootrec->data;
182 break;
4e416a6f
CL		 183 case BR_CODE_DESCR: {
184 struct bootrec_desc *desc =
185 (struct bootrec_desc *)bootrec->data;
186 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 187 /* FIXME add sanity checking */
4e416a6f
CL		 188 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
189 priv->headroom = desc->headroom;
190 priv->tailroom = desc->tailroom;
25900ef0
CL		 191 priv->privacy_caps = desc->privacy_caps;
192 priv->rx_keycache_size = desc->rx_keycache_size;
1f1c0e33 193 if (le32_to_cpu(bootrec->len) == 11)
2e20cc39 194 priv->rx_mtu = le16_to_cpu(desc->rx_mtu);
4e416a6f
CL		 195 else
196 priv->rx_mtu = (size_t)
197 0x620 - priv->tx_hdr_len;
eff1a59c 198 break;
4e416a6f 199 }
eff1a59c
MW		 200 case BR_CODE_EXPOSED_IF:
201 exp_if = (struct bootrec_exp_if *) bootrec->data;
202 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 203 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 204 priv->fw_var = le16_to_cpu(exp_if[i].variant);
205 break;
206 case BR_CODE_DEPENDENT_IF:
207 break;
208 case BR_CODE_END_OF_BRA:
209 case LEGACY_BR_CODE_END_OF_BRA:
210 end_data = NULL;
211 break;
212 default:
213 break;
214 }
215 bootrec = (struct bootrec *)&bootrec->data[len];
216 }
217
218 if (fw_version)
02e37ba1
CL		 219 printk(KERN_INFO "%s: FW rev %s - Softmac protocol %x.%x\n",
220 wiphy_name(dev->wiphy), fw_version,
221 priv->fw_var >> 8, priv->fw_var & 0xff);
eff1a59c 222
9a8675d7 223 if (priv->fw_var < 0x500)
02e37ba1 224 printk(KERN_INFO "%s: you are using an obsolete firmware. "
9a8675d7 225 "visit http://wireless.kernel.org/en/users/Drivers/p54 "
02e37ba1
CL		 226 "and grab one for \"kernel >= 2.6.28\"!\n",
227 wiphy_name(dev->wiphy));
9a8675d7 228
eff1a59c
MW		 229 if (priv->fw_var >= 0x300) {
230 /* Firmware supports QoS, use it! */
9e7f3f8e
CL		 231 priv->tx_stats[4].limit = 3; /* AC_VO */
232 priv->tx_stats[5].limit = 4; /* AC_VI */
233 priv->tx_stats[6].limit = 3; /* AC_BE */
234 priv->tx_stats[7].limit = 2; /* AC_BK */
eff1a59c
MW		 235 dev->queues = 4;
236 }
4e416a6f 237
25900ef0
CL		 238 if (!modparam_nohwcrypt)
239 printk(KERN_INFO "%s: cryptographic accelerator "
240 "WEP:%s, TKIP:%s, CCMP:%s\n",
241 wiphy_name(dev->wiphy),
242 (priv->privacy_caps & BR_DESC_PRIV_CAP_WEP) ? "YES" :
243 "no", (priv->privacy_caps & (BR_DESC_PRIV_CAP_TKIP |
244 BR_DESC_PRIV_CAP_MICHAEL)) ? "YES" : "no",
245 (priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP) ?
246 "YES" : "no");
247
4e416a6f 248 return 0;
eff1a59c
MW		 249}
250EXPORT_SYMBOL_GPL(p54_parse_firmware);
251
154e3af1
CL		 252static int p54_convert_rev0(struct ieee80211_hw *dev,
253 struct pda_pa_curve_data *curve_data)
eff1a59c
MW		 254{
255 struct p54_common *priv = dev->priv;
154e3af1
CL		 256 struct p54_pa_curve_data_sample *dst;
257 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 258 size_t cd_len = sizeof(*curve_data) +
154e3af1 259 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW		 260 curve_data->channels;
261 unsigned int i, j;
262 void *source, *target;
263
264 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
265 if (!priv->curve_data)
266 return -ENOMEM;
267
268 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
269 source = curve_data->data;
270 target = priv->curve_data->data;
271 for (i = 0; i < curve_data->channels; i++) {
272 __le16 *freq = source;
273 source += sizeof(__le16);
274 *((__le16 *)target) = *freq;
275 target += sizeof(__le16);
276 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL		 277 dst = target;
278 src = source;
eff1a59c 279
154e3af1
CL		 280 dst->rf_power = src->rf_power;
281 dst->pa_detector = src->pa_detector;
282 dst->data_64qam = src->pcv;
eff1a59c
MW		 283 /* "invent" the points for the other modulations */
284#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL		 285 dst->data_16qam = SUB(src->pcv, 12);
286 dst->data_qpsk = SUB(dst->data_16qam, 12);
287 dst->data_bpsk = SUB(dst->data_qpsk, 12);
288 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 289#undef SUB
154e3af1
CL		 290 target += sizeof(*dst);
291 source += sizeof(*src);
eff1a59c
MW		 292 }
293 }
294
295 return 0;
296}
297
154e3af1
CL		 298static int p54_convert_rev1(struct ieee80211_hw *dev,
299 struct pda_pa_curve_data *curve_data)
300{
301 struct p54_common *priv = dev->priv;
302 struct p54_pa_curve_data_sample *dst;
303 struct pda_pa_curve_data_sample_rev1 *src;
304 size_t cd_len = sizeof(*curve_data) +
305 (curve_data->points_per_channel*sizeof(*dst) + 2) *
306 curve_data->channels;
307 unsigned int i, j;
308 void *source, *target;
309
310 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
311 if (!priv->curve_data)
312 return -ENOMEM;
313
314 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
315 source = curve_data->data;
316 target = priv->curve_data->data;
317 for (i = 0; i < curve_data->channels; i++) {
318 __le16 *freq = source;
319 source += sizeof(__le16);
320 *((__le16 *)target) = *freq;
321 target += sizeof(__le16);
322 for (j = 0; j < curve_data->points_per_channel; j++) {
323 memcpy(target, source, sizeof(*src));
324
325 target += sizeof(*dst);
326 source += sizeof(*src);
327 }
328 source++;
329 }
330
331 return 0;
332}
333
4cc683c9
CL		 334static const char *p54_rf_chips[] = { "NULL", "Duette3", "Duette2",
335 "Frisbee", "Xbow", "Longbow", "NULL", "NULL" };
1b997534 336static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 337
69ba3e5d
CL		 338static void p54_parse_rssical(struct ieee80211_hw *dev, void *data, int len,
339 u16 type)
340{
341 struct p54_common *priv = dev->priv;
342 int offset = (type == PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED) ? 2 : 0;
343 int entry_size = sizeof(struct pda_rssi_cal_entry) + offset;
344 int num_entries = (type == PDR_RSSI_LINEAR_APPROXIMATION) ? 1 : 2;
345 int i;
346
347 if (len != (entry_size * num_entries)) {
348 printk(KERN_ERR "%s: unknown rssi calibration data packing "
349 " type:(%x) len:%d.\n",
350 wiphy_name(dev->wiphy), type, len);
351
352 print_hex_dump_bytes("rssical:", DUMP_PREFIX_NONE,
353 data, len);
354
355 printk(KERN_ERR "%s: please report this issue.\n",
356 wiphy_name(dev->wiphy));
357 return;
358 }
359
360 for (i = 0; i < num_entries; i++) {
361 struct pda_rssi_cal_entry *cal = data +
362 (offset + i * entry_size);
363 priv->rssical_db[i].mul = (s16) le16_to_cpu(cal->mul);
364 priv->rssical_db[i].add = (s16) le16_to_cpu(cal->add);
365 }
366}
367
1f1c0e33 368static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW		 369{
370 struct p54_common *priv = dev->priv;
371 struct eeprom_pda_wrap *wrap = NULL;
372 struct pda_entry *entry;
eff1a59c
MW		 373 unsigned int data_len, entry_len;
374 void *tmp;
375 int err;
c2f2d3a0 376 u8 *end = (u8 *)eeprom + len;
f2c2e255 377 u16 synth = 0;
eff1a59c
MW		 378
379 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 380 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB		 381
382 /* verify that at least the entry length/code fits */
383 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW		 384 entry_len = le16_to_cpu(entry->len);
385 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB		 386
387 /* abort if entry exceeds whole structure */
388 if ((u8 *)entry + sizeof(*entry) + data_len > end)
389 break;
390
eff1a59c
MW		 391 switch (le16_to_cpu(entry->code)) {
392 case PDR_MAC_ADDRESS:
393 SET_IEEE80211_PERM_ADDR(dev, entry->data);
394 break;
395 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
396 if (data_len < 2) {
397 err = -EINVAL;
398 goto err;
399 }
400
401 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
402 err = -EINVAL;
403 goto err;
404 }
405
406 priv->output_limit = kmalloc(entry->data[1] *
407 sizeof(*priv->output_limit), GFP_KERNEL);
408
409 if (!priv->output_limit) {
410 err = -ENOMEM;
411 goto err;
412 }
413
414 memcpy(priv->output_limit, &entry->data[2],
415 entry->data[1]*sizeof(*priv->output_limit));
416 priv->output_limit_len = entry->data[1];
417 break;
154e3af1
CL		 418 case PDR_PRISM_PA_CAL_CURVE_DATA: {
419 struct pda_pa_curve_data *curve_data =
420 (struct pda_pa_curve_data *)entry->data;
421 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW		 422 err = -EINVAL;
423 goto err;
424 }
425
154e3af1
CL		 426 switch (curve_data->cal_method_rev) {
427 case 0:
428 err = p54_convert_rev0(dev, curve_data);
429 break;
430 case 1:
431 err = p54_convert_rev1(dev, curve_data);
432 break;
433 default:
02e37ba1 434 printk(KERN_ERR "%s: unknown curve data "
154e3af1 435 "revision %d\n",
02e37ba1 436 wiphy_name(dev->wiphy),
154e3af1
CL		 437 curve_data->cal_method_rev);
438 err = -ENODEV;
439 break;
eff1a59c 440 }
154e3af1
CL		 441 if (err)
442 goto err;
eff1a59c 443
154e3af1 444 }
eff1a59c
MW		 445 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
446 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
447 if (!priv->iq_autocal) {
448 err = -ENOMEM;
449 goto err;
450 }
451
452 memcpy(priv->iq_autocal, entry->data, data_len);
453 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
454 break;
455 case PDR_INTERFACE_LIST:
456 tmp = entry->data;
457 while ((u8 *)tmp < entry->data + data_len) {
458 struct bootrec_exp_if *exp_if = tmp;
4cc683c9
CL		 459 if (le16_to_cpu(exp_if->if_id) == 0xf)
460 synth = le16_to_cpu(exp_if->variant);
eff1a59c
MW		 461 tmp += sizeof(struct bootrec_exp_if);
462 }
463 break;
464 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
465 priv->version = *(u8 *)(entry->data + 1);
466 break;
69ba3e5d
CL		 467 case PDR_RSSI_LINEAR_APPROXIMATION:
468 case PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND:
469 case PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED:
470 p54_parse_rssical(dev, entry->data, data_len,
471 le16_to_cpu(entry->code));
472 break;
eff1a59c 473 case PDR_END:
c2f2d3a0
JB		 474 /* make it overrun */
475 entry_len = len;
eff1a59c 476 break;
c8034c44
PR		 477 case PDR_MANUFACTURING_PART_NUMBER:
478 case PDR_PDA_VERSION:
479 case PDR_NIC_SERIAL_NUMBER:
480 case PDR_REGULATORY_DOMAIN_LIST:
481 case PDR_TEMPERATURE_TYPE:
482 case PDR_PRISM_PCI_IDENTIFIER:
483 case PDR_COUNTRY_INFORMATION:
484 case PDR_OEM_NAME:
485 case PDR_PRODUCT_NAME:
486 case PDR_UTF8_OEM_NAME:
487 case PDR_UTF8_PRODUCT_NAME:
488 case PDR_COUNTRY_LIST:
489 case PDR_DEFAULT_COUNTRY:
490 case PDR_ANTENNA_GAIN:
491 case PDR_PRISM_INDIGO_PA_CALIBRATION_DATA:
c8034c44 492 case PDR_REGULATORY_POWER_LIMITS:
c8034c44
PR		 493 case PDR_RADIATED_TRANSMISSION_CORRECTION:
494 case PDR_PRISM_TX_IQ_CALIBRATION:
495 case PDR_BASEBAND_REGISTERS:
496 case PDR_PER_CHANNEL_BASEBAND_REGISTERS:
497 break;
58e30739 498 default:
02e37ba1
CL		 499 printk(KERN_INFO "%s: unknown eeprom code : 0x%x\n",
500 wiphy_name(dev->wiphy),
58e30739
FF		 501 le16_to_cpu(entry->code));
502 break;
eff1a59c
MW		 503 }
504
505 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW		 506 }
507
f2c2e255
CL		 508 if (!synth || !priv->iq_autocal || !priv->output_limit ||
509 !priv->curve_data) {
02e37ba1
CL		 510 printk(KERN_ERR "%s: not all required entries found in eeprom!\n",
511 wiphy_name(dev->wiphy));
eff1a59c
MW		 512 err = -EINVAL;
513 goto err;
514 }
515
9e7f3f8e 516 priv->rxhw = synth & PDR_SYNTH_FRONTEND_MASK;
4cc683c9 517 if (priv->rxhw == 4)
1b997534 518 p54_init_xbow_synth(dev);
9e7f3f8e 519 if (!(synth & PDR_SYNTH_24_GHZ_DISABLED))
1b997534 520 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
9e7f3f8e 521 if (!(synth & PDR_SYNTH_5_GHZ_DISABLED))
4cc683c9 522 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
7cb77072
CL		 523
524 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
525 u8 perm_addr[ETH_ALEN];
526
527 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
528 wiphy_name(dev->wiphy));
529 random_ether_addr(perm_addr);
530 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
531 }
532
e174961c 533 printk(KERN_INFO "%s: hwaddr %pM, MAC:isl38%02x RF:%s\n",
7cb77072 534 wiphy_name(dev->wiphy),
e174961c 535 dev->wiphy->perm_addr,
7cb77072
CL		 536 priv->version, p54_rf_chips[priv->rxhw]);
537
eff1a59c
MW		 538 return 0;
539
540 err:
541 if (priv->iq_autocal) {
542 kfree(priv->iq_autocal);
543 priv->iq_autocal = NULL;
544 }
545
546 if (priv->output_limit) {
547 kfree(priv->output_limit);
548 priv->output_limit = NULL;
549 }
550
551 if (priv->curve_data) {
552 kfree(priv->curve_data);
553 priv->curve_data = NULL;
554 }
555
02e37ba1
CL		 556 printk(KERN_ERR "%s: eeprom parse failed!\n",
557 wiphy_name(dev->wiphy));
eff1a59c
MW		 558 return err;
559}
eff1a59c 560
cc6de669
CL		 561static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
562{
69ba3e5d
CL		 563 struct p54_common *priv = dev->priv;
564 int band = dev->conf.channel->band;
565
566 return ((rssi * priv->rssical_db[band].mul) / 64 +
567 priv->rssical_db[band].add) / 4;
cc6de669
CL		 568}
569
19c19d54 570static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 571{
a0db663f 572 struct p54_common *priv = dev->priv;
27df605e 573 struct p54_rx_data *hdr = (struct p54_rx_data *) skb->data;
eff1a59c
MW		 574 struct ieee80211_rx_status rx_status = {0};
575 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 576 size_t header_len = sizeof(*hdr);
a0db663f 577 u32 tsf32;
eff1a59c 578
59651e89
CL		 579 /*
580 * If the device is in a unspecified state we have to
581 * ignore all data frames. Else we could end up with a
582 * nasty crash.
583 */
584 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
585 return 0;
586
27df605e 587 if (!(hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_IN_FCS_GOOD))) {
78d57eb2
CL		 588 if (priv->filter_flags & FIF_FCSFAIL)
589 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
590 else
591 return 0;
592 }
593
25900ef0
CL		 594 if (hdr->decrypt_status == P54_DECRYPT_OK)
595 rx_status.flag |= RX_FLAG_DECRYPTED;
596 if ((hdr->decrypt_status == P54_DECRYPT_FAIL_MICHAEL) ||
597 (hdr->decrypt_status == P54_DECRYPT_FAIL_TKIP))
598 rx_status.flag |= RX_FLAG_MMIC_ERROR;
599
cc6de669
CL		 600 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
601 rx_status.noise = priv->noise;
8318d78a 602 /* XX correct? */
18d72605 603 rx_status.qual = (100 * hdr->rssi) / 127;
ffed7858
CL		 604 if (hdr->rate & 0x10)
605 rx_status.flag |= RX_FLAG_SHORTPRE;
cf3e74c2
CL		 606 rx_status.rate_idx = (dev->conf.channel->band == IEEE80211_BAND_2GHZ ?
607 hdr->rate : (hdr->rate - 4)) & 0xf;
eff1a59c 608 rx_status.freq = freq;
cf3e74c2 609 rx_status.band = dev->conf.channel->band;
eff1a59c 610 rx_status.antenna = hdr->antenna;
a0db663f
CL		 611
612 tsf32 = le32_to_cpu(hdr->tsf32);
613 if (tsf32 < priv->tsf_low32)
614 priv->tsf_high32++;
615 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
616 priv->tsf_low32 = tsf32;
617
03bffc13 618 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 619
27df605e 620 if (hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
19c19d54
CL		 621 header_len += hdr->align[0];
622
623 skb_pull(skb, header_len);
eff1a59c
MW		 624 skb_trim(skb, le16_to_cpu(hdr->len));
625
626 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54 627
54fdb040
CL		 628 queue_delayed_work(dev->workqueue, &priv->work,
629 msecs_to_jiffies(P54_STATISTICS_UPDATE));
630
19c19d54 631 return -1;
eff1a59c
MW		 632}
633
634static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
635{
636 struct p54_common *priv = dev->priv;
637 int i;
638
b92f30d6
CL		 639 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
640 return ;
641
eff1a59c 642 for (i = 0; i < dev->queues; i++)
84df3ed3 643 if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit)
eff1a59c
MW		 644 ieee80211_wake_queue(dev, i);
645}
646
b92f30d6
CL		 647void p54_free_skb(struct ieee80211_hw *dev, struct sk_buff *skb)
648{
649 struct p54_common *priv = dev->priv;
650 struct ieee80211_tx_info *info;
651 struct memrecord *range;
652 unsigned long flags;
653 u32 freed = 0, last_addr = priv->rx_start;
654
ffed7858 655 if (unlikely(!skb || !dev || !skb_queue_len(&priv->tx_queue)))
b92f30d6
CL		 656 return;
657
59651e89
CL		 658 /*
659 * don't try to free an already unlinked skb
660 */
661 if (unlikely((!skb->next) || (!skb->prev)))
662 return;
663
b92f30d6
CL		 664 spin_lock_irqsave(&priv->tx_queue.lock, flags);
665 info = IEEE80211_SKB_CB(skb);
666 range = (void *)info->rate_driver_data;
667 if (skb->prev != (struct sk_buff *)&priv->tx_queue) {
668 struct ieee80211_tx_info *ni;
669 struct memrecord *mr;
670
671 ni = IEEE80211_SKB_CB(skb->prev);
672 mr = (struct memrecord *)ni->rate_driver_data;
673 last_addr = mr->end_addr;
674 }
675 if (skb->next != (struct sk_buff *)&priv->tx_queue) {
676 struct ieee80211_tx_info *ni;
677 struct memrecord *mr;
678
679 ni = IEEE80211_SKB_CB(skb->next);
680 mr = (struct memrecord *)ni->rate_driver_data;
681 freed = mr->start_addr - last_addr;
682 } else
683 freed = priv->rx_end - last_addr;
684 __skb_unlink(skb, &priv->tx_queue);
685 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
686 kfree_skb(skb);
687
27df605e 688 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
b92f30d6
CL		 689 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
690 p54_wake_free_queues(dev);
691}
692EXPORT_SYMBOL_GPL(p54_free_skb);
693
54fdb040
CL		 694static struct sk_buff *p54_find_tx_entry(struct ieee80211_hw *dev,
695 __le32 req_id)
696{
697 struct p54_common *priv = dev->priv;
698 struct sk_buff *entry = priv->tx_queue.next;
699 unsigned long flags;
700
701 spin_lock_irqsave(&priv->tx_queue.lock, flags);
702 while (entry != (struct sk_buff *)&priv->tx_queue) {
703 struct p54_hdr *hdr = (struct p54_hdr *) entry->data;
704
705 if (hdr->req_id == req_id) {
706 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
707 return entry;
708 }
709 entry = entry->next;
710 }
711 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
712 return NULL;
713}
714
eff1a59c
MW		 715static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
716{
717 struct p54_common *priv = dev->priv;
27df605e
JL		 718 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
719 struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data;
eff1a59c 720 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
4e416a6f 721 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
eff1a59c
MW		 722 struct memrecord *range = NULL;
723 u32 freed = 0;
724 u32 last_addr = priv->rx_start;
031d10ee 725 unsigned long flags;
c12abae3 726 int count, idx;
eff1a59c 727
031d10ee 728 spin_lock_irqsave(&priv->tx_queue.lock, flags);
eff1a59c 729 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f 730 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
27df605e
JL		 731 struct p54_hdr *entry_hdr;
732 struct p54_tx_data *entry_data;
9de5776f 733 int pad = 0;
eff1a59c 734
9de5776f
CL		 735 range = (void *)info->rate_driver_data;
736 if (range->start_addr != addr) {
737 last_addr = range->end_addr;
738 entry = entry->next;
739 continue;
740 }
552fe53f 741
9de5776f
CL		 742 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
743 struct ieee80211_tx_info *ni;
744 struct memrecord *mr;
eff1a59c 745
9de5776f
CL		 746 ni = IEEE80211_SKB_CB(entry->next);
747 mr = (struct memrecord *)ni->rate_driver_data;
748 freed = mr->start_addr - last_addr;
749 } else
750 freed = priv->rx_end - last_addr;
751
752 last_addr = range->end_addr;
753 __skb_unlink(entry, &priv->tx_queue);
754 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
755
c772a08b
CL		 756 entry_hdr = (struct p54_hdr *) entry->data;
757 entry_data = (struct p54_tx_data *) entry_hdr->data;
758 priv->tx_stats[entry_data->hw_queue].len--;
ee370ced 759 priv->stats.dot11ACKFailureCount += payload->tries - 1;
c772a08b 760
e5ea92a7
CL		 761 if (unlikely(entry == priv->cached_beacon)) {
762 kfree_skb(entry);
763 priv->cached_beacon = NULL;
764 goto out;
765 }
766
9de5776f
CL		 767 /*
768 * Clear manually, ieee80211_tx_info_clear_status would
769 * clear the counts too and we need them.
770 */
771 memset(&info->status.ampdu_ack_len, 0,
772 sizeof(struct ieee80211_tx_info) -
773 offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
774 BUILD_BUG_ON(offsetof(struct ieee80211_tx_info,
775 status.ampdu_ack_len) != 23);
776
27df605e 777 if (entry_hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
9de5776f
CL		 778 pad = entry_data->align[0];
779
780 /* walk through the rates array and adjust the counts */
27df605e 781 count = payload->tries;
9de5776f
CL		 782 for (idx = 0; idx < 4; idx++) {
783 if (count >= info->status.rates[idx].count) {
784 count -= info->status.rates[idx].count;
785 } else if (count > 0) {
786 info->status.rates[idx].count = count;
787 count = 0;
788 } else {
789 info->status.rates[idx].idx = -1;
790 info->status.rates[idx].count = 0;
eff1a59c 791 }
9de5776f 792 }
c12abae3 793
9de5776f
CL		 794 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
795 (!payload->status))
796 info->flags |= IEEE80211_TX_STAT_ACK;
9e7f3f8e 797 if (payload->status & P54_TX_PSM_CANCELLED)
9de5776f
CL		 798 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
799 info->status.ack_signal = p54_rssi_to_dbm(dev,
27df605e 800 (int)payload->ack_rssi);
9de5776f
CL		 801 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
802 ieee80211_tx_status_irqsafe(dev, entry);
803 goto out;
eff1a59c 804 }
031d10ee 805 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 806
031d10ee 807out:
27df605e 808 if (freed >= priv->headroom + sizeof(struct p54_hdr) + 48 +
9de5776f 809 IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
eff1a59c
MW		 810 p54_wake_free_queues(dev);
811}
812
7cb77072
CL		 813static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
814 struct sk_buff *skb)
815{
27df605e 816 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
7cb77072
CL		 817 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
818 struct p54_common *priv = dev->priv;
819
820 if (!priv->eeprom)
821 return ;
822
64c354dd
CL		 823 if (priv->fw_var >= 0x509) {
824 memcpy(priv->eeprom, eeprom->v2.data,
825 le16_to_cpu(eeprom->v2.len));
826 } else {
827 memcpy(priv->eeprom, eeprom->v1.data,
828 le16_to_cpu(eeprom->v1.len));
829 }
7cb77072
CL		 830
831 complete(&priv->eeprom_comp);
832}
833
cc6de669
CL		 834static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
835{
836 struct p54_common *priv = dev->priv;
27df605e 837 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
cc6de669 838 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
54fdb040
CL		 839 u32 tsf32;
840
841 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
842 return ;
cc6de669 843
54fdb040 844 tsf32 = le32_to_cpu(stats->tsf32);
cc6de669
CL		 845 if (tsf32 < priv->tsf_low32)
846 priv->tsf_high32++;
847 priv->tsf_low32 = tsf32;
848
849 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
850 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
851 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
852
853 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
cc6de669 854
54fdb040 855 p54_free_skb(dev, p54_find_tx_entry(dev, hdr->req_id));
cc6de669
CL		 856}
857
e5ea92a7
CL		 858static void p54_rx_trap(struct ieee80211_hw *dev, struct sk_buff *skb)
859{
860 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
861 struct p54_trap *trap = (struct p54_trap *) hdr->data;
862 u16 event = le16_to_cpu(trap->event);
863 u16 freq = le16_to_cpu(trap->frequency);
864
865 switch (event) {
866 case P54_TRAP_BEACON_TX:
867 break;
868 case P54_TRAP_RADAR:
869 printk(KERN_INFO "%s: radar (freq:%d MHz)\n",
870 wiphy_name(dev->wiphy), freq);
871 break;
872 case P54_TRAP_NO_BEACON:
873 break;
874 case P54_TRAP_SCAN:
875 break;
876 case P54_TRAP_TBTT:
877 break;
878 case P54_TRAP_TIMER:
879 break;
880 default:
881 printk(KERN_INFO "%s: received event:%x freq:%d\n",
882 wiphy_name(dev->wiphy), event, freq);
883 break;
884 }
885}
886
19c19d54 887static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 888{
27df605e 889 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
eff1a59c
MW		 890
891 switch (le16_to_cpu(hdr->type)) {
892 case P54_CONTROL_TYPE_TXDONE:
893 p54_rx_frame_sent(dev, skb);
894 break;
e5ea92a7
CL		 895 case P54_CONTROL_TYPE_TRAP:
896 p54_rx_trap(dev, skb);
897 break;
eff1a59c
MW		 898 case P54_CONTROL_TYPE_BBP:
899 break;
cc6de669
CL		 900 case P54_CONTROL_TYPE_STAT_READBACK:
901 p54_rx_stats(dev, skb);
902 break;
7cb77072
CL		 903 case P54_CONTROL_TYPE_EEPROM_READBACK:
904 p54_rx_eeprom_readback(dev, skb);
905 break;
eff1a59c
MW		 906 default:
907 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
908 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
909 break;
910 }
19c19d54
CL		 911
912 return 0;
eff1a59c
MW		 913}
914
915/* returns zero if skb can be reused */
916int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
917{
9e7f3f8e 918 u16 type = le16_to_cpu(*((__le16 *)skb->data));
19c19d54 919
9e7f3f8e 920 if (type & P54_HDR_FLAG_CONTROL)
19c19d54
CL		 921 return p54_rx_control(dev, skb);
922 else
923 return p54_rx_data(dev, skb);
eff1a59c
MW		 924}
925EXPORT_SYMBOL_GPL(p54_rx);
926
927/*
928 * So, the firmware is somewhat stupid and doesn't know what places in its
929 * memory incoming data should go to. By poking around in the firmware, we
930 * can find some unused memory to upload our packets to. However, data that we
931 * want the card to TX needs to stay intact until the card has told us that
932 * it is done with it. This function finds empty places we can upload to and
933 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
934 * allocated areas.
935 */
b92f30d6 936static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
27df605e 937 struct p54_hdr *data, u32 len)
eff1a59c
MW		 938{
939 struct p54_common *priv = dev->priv;
940 struct sk_buff *entry = priv->tx_queue.next;
941 struct sk_buff *target_skb = NULL;
b92f30d6
CL		 942 struct ieee80211_tx_info *info;
943 struct memrecord *range;
eff1a59c
MW		 944 u32 last_addr = priv->rx_start;
945 u32 largest_hole = 0;
946 u32 target_addr = priv->rx_start;
947 unsigned long flags;
948 unsigned int left;
4e416a6f 949 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c 950
b92f30d6
CL		 951 if (!skb)
952 return -EINVAL;
953
eff1a59c 954 spin_lock_irqsave(&priv->tx_queue.lock, flags);
39ca5bb7 955
eff1a59c 956 left = skb_queue_len(&priv->tx_queue);
39ca5bb7
CL		 957 if (unlikely(left >= 28)) {
958 /*
959 * The tx_queue is nearly full!
960 * We have throttle normal data traffic, because we must
961 * have a few spare slots for control frames left.
962 */
963 ieee80211_stop_queues(dev);
54fdb040
CL		 964 queue_delayed_work(dev->workqueue, &priv->work,
965 msecs_to_jiffies(P54_TX_TIMEOUT));
39ca5bb7
CL		 966
967 if (unlikely(left == 32)) {
968 /*
969 * The tx_queue is now really full.
970 *
971 * TODO: check if the device has crashed and reset it.
972 */
973 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
974 return -ENOSPC;
975 }
976 }
977
eff1a59c
MW		 978 while (left--) {
979 u32 hole_size;
b92f30d6
CL		 980 info = IEEE80211_SKB_CB(entry);
981 range = (void *)info->rate_driver_data;
eff1a59c
MW		 982 hole_size = range->start_addr - last_addr;
983 if (!target_skb && hole_size >= len) {
984 target_skb = entry->prev;
985 hole_size -= len;
986 target_addr = last_addr;
987 }
988 largest_hole = max(largest_hole, hole_size);
989 last_addr = range->end_addr;
990 entry = entry->next;
991 }
992 if (!target_skb && priv->rx_end - last_addr >= len) {
993 target_skb = priv->tx_queue.prev;
994 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
995 if (!skb_queue_empty(&priv->tx_queue)) {
b92f30d6
CL		 996 info = IEEE80211_SKB_CB(target_skb);
997 range = (void *)info->rate_driver_data;
eff1a59c
MW		 998 target_addr = range->end_addr;
999 }
1000 } else
1001 largest_hole = max(largest_hole, priv->rx_end - last_addr);
1002
b92f30d6
CL		 1003 if (!target_skb) {
1004 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1005 ieee80211_stop_queues(dev);
39ca5bb7 1006 return -ENOSPC;
eff1a59c 1007 }
b92f30d6
CL		 1008
1009 info = IEEE80211_SKB_CB(skb);
1010 range = (void *)info->rate_driver_data;
1011 range->start_addr = target_addr;
1012 range->end_addr = target_addr + len;
1013 __skb_queue_after(&priv->tx_queue, target_skb, skb);
eff1a59c
MW		 1014 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1015
27df605e 1016 if (largest_hole < priv->headroom + sizeof(struct p54_hdr) +
b92f30d6
CL		 1017 48 + IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
1018 ieee80211_stop_queues(dev);
1019
4e416a6f 1020 data->req_id = cpu_to_le32(target_addr + priv->headroom);
b92f30d6
CL		 1021 return 0;
1022}
1023
1024static struct sk_buff *p54_alloc_skb(struct ieee80211_hw *dev,
1025 u16 hdr_flags, u16 len, u16 type, gfp_t memflags)
1026{
1027 struct p54_common *priv = dev->priv;
27df605e 1028 struct p54_hdr *hdr;
b92f30d6
CL		 1029 struct sk_buff *skb;
1030
1031 skb = __dev_alloc_skb(len + priv->tx_hdr_len, memflags);
1032 if (!skb)
1033 return NULL;
1034 skb_reserve(skb, priv->tx_hdr_len);
1035
27df605e
JL		 1036 hdr = (struct p54_hdr *) skb_put(skb, sizeof(*hdr));
1037 hdr->flags = cpu_to_le16(hdr_flags);
b92f30d6
CL		 1038 hdr->len = cpu_to_le16(len - sizeof(*hdr));
1039 hdr->type = cpu_to_le16(type);
27df605e 1040 hdr->tries = hdr->rts_tries = 0;
b92f30d6
CL		 1041
1042 if (unlikely(p54_assign_address(dev, skb, hdr, len))) {
1043 kfree_skb(skb);
1044 return NULL;
1045 }
1046 return skb;
eff1a59c
MW		 1047}
1048
7cb77072
CL		 1049int p54_read_eeprom(struct ieee80211_hw *dev)
1050{
1051 struct p54_common *priv = dev->priv;
27df605e 1052 struct p54_hdr *hdr = NULL;
7cb77072 1053 struct p54_eeprom_lm86 *eeprom_hdr;
b92f30d6 1054 struct sk_buff *skb;
64c354dd 1055 size_t eeprom_size = 0x2020, offset = 0, blocksize, maxblocksize;
7cb77072
CL		 1056 int ret = -ENOMEM;
1057 void *eeprom = NULL;
1058
64c354dd
CL		 1059 maxblocksize = EEPROM_READBACK_LEN;
1060 if (priv->fw_var >= 0x509)
1061 maxblocksize -= 0xc;
1062 else
1063 maxblocksize -= 0x4;
1064
1065 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL, sizeof(*hdr) +
1066 sizeof(*eeprom_hdr) + maxblocksize,
b92f30d6
CL		 1067 P54_CONTROL_TYPE_EEPROM_READBACK, GFP_KERNEL);
1068 if (!skb)
7cb77072 1069 goto free;
7cb77072
CL		 1070 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
1071 if (!priv->eeprom)
1072 goto free;
7cb77072
CL		 1073 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
1074 if (!eeprom)
1075 goto free;
1076
b92f30d6 1077 eeprom_hdr = (struct p54_eeprom_lm86 *) skb_put(skb,
64c354dd 1078 sizeof(*eeprom_hdr) + maxblocksize);
7cb77072
CL		 1079
1080 while (eeprom_size) {
64c354dd
CL		 1081 blocksize = min(eeprom_size, maxblocksize);
1082 if (priv->fw_var < 0x509) {
1083 eeprom_hdr->v1.offset = cpu_to_le16(offset);
1084 eeprom_hdr->v1.len = cpu_to_le16(blocksize);
1085 } else {
1086 eeprom_hdr->v2.offset = cpu_to_le32(offset);
1087 eeprom_hdr->v2.len = cpu_to_le16(blocksize);
1088 eeprom_hdr->v2.magic2 = 0xf;
1089 memcpy(eeprom_hdr->v2.magic, (const char *)"LOCK", 4);
1090 }
b92f30d6 1091 priv->tx(dev, skb, 0);
7cb77072
CL		 1092
1093 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
1094 printk(KERN_ERR "%s: device does not respond!\n",
1095 wiphy_name(dev->wiphy));
1096 ret = -EBUSY;
1097 goto free;
1098 }
1099
1100 memcpy(eeprom + offset, priv->eeprom, blocksize);
1101 offset += blocksize;
1102 eeprom_size -= blocksize;
1103 }
1104
1105 ret = p54_parse_eeprom(dev, eeprom, offset);
1106free:
1107 kfree(priv->eeprom);
1108 priv->eeprom = NULL;
b92f30d6 1109 p54_free_skb(dev, skb);
7cb77072
CL		 1110 kfree(eeprom);
1111
1112 return ret;
1113}
1114EXPORT_SYMBOL_GPL(p54_read_eeprom);
1115
e5ea92a7
CL		 1116static int p54_set_tim(struct ieee80211_hw *dev, struct ieee80211_sta *sta,
1117 bool set)
1118{
1119 struct p54_common *priv = dev->priv;
1120 struct sk_buff *skb;
1121 struct p54_tim *tim;
1122
1123 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1124 sizeof(struct p54_hdr) + sizeof(*tim),
1125 P54_CONTROL_TYPE_TIM, GFP_KERNEL);
1126 if (!skb)
1127 return -ENOMEM;
1128
1129 tim = (struct p54_tim *) skb_put(skb, sizeof(*tim));
1130 tim->count = 1;
1131 tim->entry[0] = cpu_to_le16(set ? (sta->aid | 0x8000) : sta->aid);
1132 priv->tx(dev, skb, 1);
1133 return 0;
1134}
1135
1136static int p54_sta_unlock(struct ieee80211_hw *dev, u8 *addr)
1137{
1138 struct p54_common *priv = dev->priv;
1139 struct sk_buff *skb;
1140 struct p54_sta_unlock *sta;
1141
1142 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1143 sizeof(struct p54_hdr) + sizeof(*sta),
1144 P54_CONTROL_TYPE_PSM_STA_UNLOCK, GFP_ATOMIC);
1145 if (!skb)
1146 return -ENOMEM;
1147
1148 sta = (struct p54_sta_unlock *)skb_put(skb, sizeof(*sta));
1149 memcpy(sta->addr, addr, ETH_ALEN);
1150 priv->tx(dev, skb, 1);
1151 return 0;
1152}
1153
c772a08b
CL		 1154static void p54_sta_notify(struct ieee80211_hw *dev, struct ieee80211_vif *vif,
1155 enum sta_notify_cmd notify_cmd,
1156 struct ieee80211_sta *sta)
1157{
1158 switch (notify_cmd) {
1159 case STA_NOTIFY_ADD:
1160 case STA_NOTIFY_REMOVE:
1161 /*
1162 * Notify the firmware that we don't want or we don't
1163 * need to buffer frames for this station anymore.
1164 */
1165
89fad578
CL		 1166 p54_sta_unlock(dev, sta->addr);
1167 break;
1168 case STA_NOTIFY_AWAKE:
1169 /* update the firmware's filter table */
c772a08b
CL		 1170 p54_sta_unlock(dev, sta->addr);
1171 break;
1172 default:
1173 break;
1174 }
1175}
1176
e5ea92a7
CL		 1177static int p54_tx_cancel(struct ieee80211_hw *dev, struct sk_buff *entry)
1178{
1179 struct p54_common *priv = dev->priv;
1180 struct sk_buff *skb;
1181 struct p54_hdr *hdr;
1182 struct p54_txcancel *cancel;
1183
1184 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET,
1185 sizeof(struct p54_hdr) + sizeof(*cancel),
1186 P54_CONTROL_TYPE_TXCANCEL, GFP_ATOMIC);
1187 if (!skb)
1188 return -ENOMEM;
1189
1190 hdr = (void *)entry->data;
1191 cancel = (struct p54_txcancel *)skb_put(skb, sizeof(*cancel));
1192 cancel->req_id = hdr->req_id;
1193 priv->tx(dev, skb, 1);
1194 return 0;
1195}
1196
94585b09
CL		 1197static int p54_tx_fill(struct ieee80211_hw *dev, struct sk_buff *skb,
1198 struct ieee80211_tx_info *info, u8 *queue, size_t *extra_len,
1199 u16 *flags, u16 *aid)
1200{
1201 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1202 struct p54_common *priv = dev->priv;
1203 int ret = 0;
1204
1205 if (unlikely(ieee80211_is_mgmt(hdr->frame_control))) {
1206 if (ieee80211_is_beacon(hdr->frame_control)) {
1207 *aid = 0;
1208 *queue = 0;
1209 *extra_len = IEEE80211_MAX_TIM_LEN;
1210 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP;
1211 return 0;
1212 } else if (ieee80211_is_probe_resp(hdr->frame_control)) {
1213 *aid = 0;
1214 *queue = 2;
1215 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP |
1216 P54_HDR_FLAG_DATA_OUT_NOCANCEL;
1217 return 0;
1218 } else {
1219 *queue = 2;
1220 ret = 0;
1221 }
1222 } else {
1223 *queue += 4;
1224 ret = 1;
1225 }
1226
1227 switch (priv->mode) {
1228 case NL80211_IFTYPE_STATION:
1229 *aid = 1;
1230 break;
1231 case NL80211_IFTYPE_AP:
1232 case NL80211_IFTYPE_ADHOC:
d131bb59 1233 case NL80211_IFTYPE_MESH_POINT:
94585b09
CL		 1234 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1235 *aid = 0;
1236 *queue = 3;
1237 return 0;
1238 }
1239 if (info->control.sta)
1240 *aid = info->control.sta->aid;
1241 else
c772a08b 1242 *flags |= P54_HDR_FLAG_DATA_OUT_NOCANCEL;
94585b09
CL		 1243 }
1244 return ret;
1245}
1246
25900ef0
CL		 1247static u8 p54_convert_algo(enum ieee80211_key_alg alg)
1248{
1249 switch (alg) {
1250 case ALG_WEP:
1251 return P54_CRYPTO_WEP;
1252 case ALG_TKIP:
1253 return P54_CRYPTO_TKIPMICHAEL;
1254 case ALG_CCMP:
1255 return P54_CRYPTO_AESCCMP;
1256 default:
1257 return 0;
1258 }
1259}
1260
e039fa4a 1261static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 1262{
e039fa4a 1263 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9e7f3f8e 1264 struct ieee80211_tx_queue_stats *current_queue = NULL;
eff1a59c 1265 struct p54_common *priv = dev->priv;
27df605e
JL		 1266 struct p54_hdr *hdr;
1267 struct p54_tx_data *txhdr;
db4186cf 1268 size_t padding, len, tim_len = 0;
c772a08b 1269 int i, j, ridx, ret;
94585b09 1270 u16 hdr_flags = 0, aid = 0;
25900ef0 1271 u8 rate, queue, crypt_offset = 0;
aaa15535 1272 u8 cts_rate = 0x20;
e6a9854b 1273 u8 rc_flags;
c12abae3
JB		 1274 u8 calculated_tries[4];
1275 u8 nrates = 0, nremaining = 8;
eff1a59c 1276
94585b09
CL		 1277 queue = skb_get_queue_mapping(skb);
1278
c772a08b
CL		 1279 ret = p54_tx_fill(dev, skb, info, &queue, &tim_len, &hdr_flags, &aid);
1280 current_queue = &priv->tx_stats[queue];
1281 if (unlikely((current_queue->len > current_queue->limit) && ret))
1282 return NETDEV_TX_BUSY;
1283 current_queue->len++;
1284 current_queue->count++;
1285 if ((current_queue->len == current_queue->limit) && ret)
1286 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW		 1287
1288 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
1289 len = skb->len;
1290
25900ef0
CL		 1291 if (info->control.hw_key) {
1292 crypt_offset = ieee80211_get_hdrlen_from_skb(skb);
1293 if (info->control.hw_key->alg == ALG_TKIP) {
1294 u8 *iv = (u8 *)(skb->data + crypt_offset);
1295 /*
1296 * The firmware excepts that the IV has to have
1297 * this special format
1298 */
1299 iv[1] = iv[0];
1300 iv[0] = iv[2];
1301 iv[2] = 0;
1302 }
1303 }
1304
27df605e
JL		 1305 txhdr = (struct p54_tx_data *) skb_push(skb, sizeof(*txhdr) + padding);
1306 hdr = (struct p54_hdr *) skb_push(skb, sizeof(*hdr));
eff1a59c
MW		 1307
1308 if (padding)
9e7f3f8e 1309 hdr_flags |= P54_HDR_FLAG_DATA_ALIGN;
94585b09 1310 hdr->type = cpu_to_le16(aid);
27df605e 1311 hdr->rts_tries = info->control.rates[0].count;
c12abae3
JB		 1312
1313 /*
1314 * we register the rates in perfect order, and
1315 * RTS/CTS won't happen on 5 GHz
1316 */
1317 cts_rate = info->control.rts_cts_rate_idx;
1318
1319 memset(&txhdr->rateset, 0, sizeof(txhdr->rateset));
1320
1321 /* see how many rates got used */
1322 for (i = 0; i < 4; i++) {
1323 if (info->control.rates[i].idx < 0)
1324 break;
1325 nrates++;
1326 }
1327
1328 /* limit tries to 8/nrates per rate */
1329 for (i = 0; i < nrates; i++) {
1330 /*
1331 * The magic expression here is equivalent to 8/nrates for
1332 * all values that matter, but avoids division and jumps.
1333 * Note that nrates can only take the values 1 through 4.
1334 */
1335 calculated_tries[i] = min_t(int, ((15 >> nrates) | 1) + 1,
1336 info->control.rates[i].count);
1337 nremaining -= calculated_tries[i];
aaa15535 1338 }
c12abae3
JB		 1339
1340 /* if there are tries left, distribute from back to front */
1341 for (i = nrates - 1; nremaining > 0 && i >= 0; i--) {
1342 int tmp = info->control.rates[i].count - calculated_tries[i];
1343
1344 if (tmp <= 0)
1345 continue;
1346 /* RC requested more tries at this rate */
1347
1348 tmp = min_t(int, tmp, nremaining);
1349 calculated_tries[i] += tmp;
1350 nremaining -= tmp;
aaa15535 1351 }
c12abae3
JB		 1352
1353 ridx = 0;
1354 for (i = 0; i < nrates && ridx < 8; i++) {
1355 /* we register the rates in perfect order */
1356 rate = info->control.rates[i].idx;
1357 if (info->band == IEEE80211_BAND_5GHZ)
1358 rate += 4;
1359
1360 /* store the count we actually calculated for TX status */
1361 info->control.rates[i].count = calculated_tries[i];
1362
1363 rc_flags = info->control.rates[i].flags;
1364 if (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) {
1365 rate |= 0x10;
1366 cts_rate |= 0x10;
1367 }
1368 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1369 rate |= 0x40;
1370 else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1371 rate |= 0x20;
1372 for (j = 0; j < calculated_tries[i] && ridx < 8; j++) {
1373 txhdr->rateset[ridx] = rate;
1374 ridx++;
1375 }
1376 }
9e7f3f8e
CL		 1377
1378 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
1379 hdr_flags |= P54_HDR_FLAG_DATA_OUT_SEQNR;
1380
1381 /* TODO: enable bursting */
1382 hdr->flags = cpu_to_le16(hdr_flags);
27df605e 1383 hdr->tries = ridx;
27df605e 1384 txhdr->rts_rate_idx = 0;
25900ef0
CL		 1385 if (info->control.hw_key) {
1386 crypt_offset += info->control.hw_key->iv_len;
1387 txhdr->key_type = p54_convert_algo(info->control.hw_key->alg);
1388 txhdr->key_len = min((u8)16, info->control.hw_key->keylen);
1389 memcpy(txhdr->key, info->control.hw_key->key, txhdr->key_len);
1390 if (info->control.hw_key->alg == ALG_TKIP) {
1391 if (unlikely(skb_tailroom(skb) < 12))
1392 goto err;
1393 /* reserve space for the MIC key */
1394 len += 8;
1395 memcpy(skb_put(skb, 8), &(info->control.hw_key->key
1396 [NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY]), 8);
1397 }
1398 /* reserve some space for ICV */
1399 len += info->control.hw_key->icv_len;
1400 } else {
1401 txhdr->key_type = 0;
1402 txhdr->key_len = 0;
1403 }
1404 txhdr->crypt_offset = crypt_offset;
94585b09 1405 txhdr->hw_queue = queue;
ffed7858
CL		 1406 if (current_queue)
1407 txhdr->backlog = current_queue->len;
1408 else
1409 txhdr->backlog = 0;
27df605e 1410 memset(txhdr->durations, 0, sizeof(txhdr->durations));
aaa15535 1411 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 1412 2 : info->antenna_sel_tx - 1;
09adf284 1413 txhdr->output_power = priv->output_power;
27df605e 1414 txhdr->cts_rate = cts_rate;
eff1a59c
MW		 1415 if (padding)
1416 txhdr->align[0] = padding;
1417
25900ef0 1418 hdr->len = cpu_to_le16(len);
e039fa4a 1419 /* modifies skb->cb and with it info, so must be last! */
25900ef0
CL		 1420 if (unlikely(p54_assign_address(dev, skb, hdr, skb->len + tim_len)))
1421 goto err;
b92f30d6 1422 priv->tx(dev, skb, 0);
54fdb040
CL		 1423
1424 queue_delayed_work(dev->workqueue, &priv->work,
1425 msecs_to_jiffies(P54_TX_FRAME_LIFETIME));
1426
eff1a59c 1427 return 0;
25900ef0
CL		 1428
1429 err:
1430 skb_pull(skb, sizeof(*hdr) + sizeof(*txhdr) + padding);
1431 if (current_queue) {
1432 current_queue->len--;
1433 current_queue->count--;
1434 }
1435 return NETDEV_TX_BUSY;
eff1a59c
MW		 1436}
1437
b2023ddc 1438static int p54_setup_mac(struct ieee80211_hw *dev)
eff1a59c
MW		 1439{
1440 struct p54_common *priv = dev->priv;
b92f30d6 1441 struct sk_buff *skb;
5e73444e 1442 struct p54_setup_mac *setup;
b2023ddc 1443 u16 mode;
eff1a59c 1444
27df605e
JL		 1445 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*setup) +
1446 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SETUP,
b92f30d6
CL		 1447 GFP_ATOMIC);
1448 if (!skb)
1449 return -ENOMEM;
eff1a59c 1450
5e73444e 1451 setup = (struct p54_setup_mac *) skb_put(skb, sizeof(*setup));
b2023ddc
CL		 1452 if (dev->conf.radio_enabled) {
1453 switch (priv->mode) {
1454 case NL80211_IFTYPE_STATION:
1455 mode = P54_FILTER_TYPE_STATION;
1456 break;
1457 case NL80211_IFTYPE_AP:
1458 mode = P54_FILTER_TYPE_AP;
1459 break;
1460 case NL80211_IFTYPE_ADHOC:
1461 case NL80211_IFTYPE_MESH_POINT:
1462 mode = P54_FILTER_TYPE_IBSS;
1463 break;
1464 default:
1465 mode = P54_FILTER_TYPE_NONE;
1466 break;
1467 }
1468 if (priv->filter_flags & FIF_PROMISC_IN_BSS)
1469 mode |= P54_FILTER_TYPE_TRANSPARENT;
1470 } else
1471 mode = P54_FILTER_TYPE_RX_DISABLED;
1472
5e73444e
CL		 1473 setup->mac_mode = cpu_to_le16(mode);
1474 memcpy(setup->mac_addr, priv->mac_addr, ETH_ALEN);
b2023ddc
CL		 1475 memcpy(setup->bssid, priv->bssid, ETH_ALEN);
1476 setup->rx_antenna = 2; /* automatic */
9483407d 1477 setup->rx_align = 0;
19c19d54 1478 if (priv->fw_var < 0x500) {
ced09574 1479 setup->v1.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
9483407d 1480 memset(setup->v1.rts_rates, 0, 8);
5e73444e
CL		 1481 setup->v1.rx_addr = cpu_to_le32(priv->rx_end);
1482 setup->v1.max_rx = cpu_to_le16(priv->rx_mtu);
1483 setup->v1.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1484 setup->v1.wakeup_timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1485 setup->v1.unalloc0 = cpu_to_le16(0);
19c19d54 1486 } else {
5e73444e
CL		 1487 setup->v2.rx_addr = cpu_to_le32(priv->rx_end);
1488 setup->v2.max_rx = cpu_to_le16(priv->rx_mtu);
1489 setup->v2.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1490 setup->v2.timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1491 setup->v2.truncate = cpu_to_le16(48896);
ced09574 1492 setup->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
5e73444e
CL		 1493 setup->v2.sbss_offset = 0;
1494 setup->v2.mcast_window = 0;
1495 setup->v2.rx_rssi_threshold = 0;
1496 setup->v2.rx_ed_threshold = 0;
1497 setup->v2.ref_clock = cpu_to_le32(644245094);
1498 setup->v2.lpf_bandwidth = cpu_to_le16(65535);
1499 setup->v2.osc_start_delay = cpu_to_le16(65535);
19c19d54 1500 }
b92f30d6 1501 priv->tx(dev, skb, 1);
eff1a59c
MW		 1502 return 0;
1503}
1504
69ba3e5d 1505static int p54_scan(struct ieee80211_hw *dev, u16 mode, u16 dwell)
eff1a59c
MW		 1506{
1507 struct p54_common *priv = dev->priv;
b92f30d6 1508 struct sk_buff *skb;
27df605e 1509 struct p54_scan *chan;
eff1a59c 1510 unsigned int i;
eff1a59c 1511 void *entry;
69ba3e5d
CL		 1512 __le16 freq = cpu_to_le16(dev->conf.channel->center_freq);
1513 int band = dev->conf.channel->band;
eff1a59c 1514
27df605e
JL		 1515 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*chan) +
1516 sizeof(struct p54_hdr), P54_CONTROL_TYPE_SCAN,
1517 GFP_ATOMIC);
b92f30d6 1518 if (!skb)
eff1a59c
MW		 1519 return -ENOMEM;
1520
27df605e 1521 chan = (struct p54_scan *) skb_put(skb, sizeof(*chan));
b92f30d6 1522 memset(chan->padding1, 0, sizeof(chan->padding1));
b2023ddc
CL		 1523 chan->mode = cpu_to_le16(mode);
1524 chan->dwell = cpu_to_le16(dwell);
eff1a59c
MW		 1525
1526 for (i = 0; i < priv->iq_autocal_len; i++) {
1527 if (priv->iq_autocal[i].freq != freq)
1528 continue;
1529
1530 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
1531 sizeof(*priv->iq_autocal));
1532 break;
1533 }
1534 if (i == priv->iq_autocal_len)
1535 goto err;
1536
1537 for (i = 0; i < priv->output_limit_len; i++) {
1538 if (priv->output_limit[i].freq != freq)
1539 continue;
1540
1541 chan->val_barker = 0x38;
154e3af1
CL		 1542 chan->val_bpsk = chan->dup_bpsk =
1543 priv->output_limit[i].val_bpsk;
1544 chan->val_qpsk = chan->dup_qpsk =
1545 priv->output_limit[i].val_qpsk;
1546 chan->val_16qam = chan->dup_16qam =
1547 priv->output_limit[i].val_16qam;
1548 chan->val_64qam = chan->dup_64qam =
1549 priv->output_limit[i].val_64qam;
eff1a59c
MW		 1550 break;
1551 }
1552 if (i == priv->output_limit_len)
1553 goto err;
1554
eff1a59c
MW		 1555 entry = priv->curve_data->data;
1556 for (i = 0; i < priv->curve_data->channels; i++) {
1557 if (*((__le16 *)entry) != freq) {
1558 entry += sizeof(__le16);
154e3af1
CL		 1559 entry += sizeof(struct p54_pa_curve_data_sample) *
1560 priv->curve_data->points_per_channel;
eff1a59c
MW		 1561 continue;
1562 }
1563
1564 entry += sizeof(__le16);
9483407d
C		 1565 chan->pa_points_per_curve = 8;
1566 memset(chan->curve_data, 0, sizeof(*chan->curve_data));
1567 memcpy(chan->curve_data, entry,
1568 sizeof(struct p54_pa_curve_data_sample) *
1569 min((u8)8, priv->curve_data->points_per_channel));
eff1a59c
MW		 1570 break;
1571 }
1572
19c19d54 1573 if (priv->fw_var < 0x500) {
69ba3e5d
CL		 1574 chan->v1_rssi.mul = cpu_to_le16(priv->rssical_db[band].mul);
1575 chan->v1_rssi.add = cpu_to_le16(priv->rssical_db[band].add);
19c19d54 1576 } else {
69ba3e5d
CL		 1577 chan->v2.rssi.mul = cpu_to_le16(priv->rssical_db[band].mul);
1578 chan->v2.rssi.add = cpu_to_le16(priv->rssical_db[band].add);
ced09574 1579 chan->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
27df605e 1580 memset(chan->v2.rts_rates, 0, 8);
19c19d54 1581 }
b92f30d6 1582 priv->tx(dev, skb, 1);
eff1a59c
MW		 1583 return 0;
1584
1585 err:
1586 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
b92f30d6 1587 kfree_skb(skb);
eff1a59c
MW		 1588 return -EINVAL;
1589}
1590
1591static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
1592{
1593 struct p54_common *priv = dev->priv;
b92f30d6 1594 struct sk_buff *skb;
27df605e 1595 struct p54_led *led;
eff1a59c 1596
27df605e
JL		 1597 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*led) +
1598 sizeof(struct p54_hdr), P54_CONTROL_TYPE_LED,
1599 GFP_ATOMIC);
b92f30d6 1600 if (!skb)
eff1a59c
MW		 1601 return -ENOMEM;
1602
27df605e 1603 led = (struct p54_led *)skb_put(skb, sizeof(*led));
eff1a59c
MW		 1604 led->mode = cpu_to_le16(mode);
1605 led->led_permanent = cpu_to_le16(link);
1606 led->led_temporary = cpu_to_le16(act);
1607 led->duration = cpu_to_le16(1000);
b92f30d6 1608 priv->tx(dev, skb, 1);
eff1a59c
MW		 1609 return 0;
1610}
1611
3330d7be 1612#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 1613do { \
1614 queue.aifs = cpu_to_le16(ai_fs); \
1615 queue.cwmin = cpu_to_le16(cw_min); \
1616 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1617 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 1618} while(0)
1619
0fdd7c5d 1620static int p54_set_edcf(struct ieee80211_hw *dev)
eff1a59c
MW		 1621{
1622 struct p54_common *priv = dev->priv;
b92f30d6 1623 struct sk_buff *skb;
0fdd7c5d 1624 struct p54_edcf *edcf;
eff1a59c 1625
27df605e
JL		 1626 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*edcf) +
1627 sizeof(struct p54_hdr), P54_CONTROL_TYPE_DCFINIT,
1628 GFP_ATOMIC);
b92f30d6 1629 if (!skb)
0fdd7c5d
CL		 1630 return -ENOMEM;
1631
b92f30d6 1632 edcf = (struct p54_edcf *)skb_put(skb, sizeof(*edcf));
40333e4f 1633 if (priv->use_short_slot) {
0fdd7c5d
CL		 1634 edcf->slottime = 9;
1635 edcf->sifs = 0x10;
1636 edcf->eofpad = 0x00;
eff1a59c 1637 } else {
0fdd7c5d
CL		 1638 edcf->slottime = 20;
1639 edcf->sifs = 0x0a;
1640 edcf->eofpad = 0x06;
eff1a59c 1641 }
eff1a59c 1642 /* (see prism54/isl_oid.h for further details) */
0fdd7c5d
CL		 1643 edcf->frameburst = cpu_to_le16(0);
1644 edcf->round_trip_delay = cpu_to_le16(0);
9483407d 1645 edcf->flags = 0;
0fdd7c5d
CL		 1646 memset(edcf->mapping, 0, sizeof(edcf->mapping));
1647 memcpy(edcf->queue, priv->qos_params, sizeof(edcf->queue));
b92f30d6 1648 priv->tx(dev, skb, 1);
0fdd7c5d 1649 return 0;
eff1a59c
MW		 1650}
1651
e5ea92a7
CL		 1652static int p54_beacon_tim(struct sk_buff *skb)
1653{
1654 /*
1655 * the good excuse for this mess is ... the firmware.
1656 * The dummy TIM MUST be at the end of the beacon frame,
1657 * because it'll be overwritten!
1658 */
1659
1660 struct ieee80211_mgmt *mgmt = (void *)skb->data;
1661 u8 *pos, *end;
1662
02e37ba1 1663 if (skb->len <= sizeof(mgmt))
e5ea92a7 1664 return -EINVAL;
e5ea92a7
CL		 1665
1666 pos = (u8 *)mgmt->u.beacon.variable;
1667 end = skb->data + skb->len;
1668 while (pos < end) {
02e37ba1 1669 if (pos + 2 + pos[1] > end)
e5ea92a7 1670 return -EINVAL;
e5ea92a7
CL		 1671
1672 if (pos[0] == WLAN_EID_TIM) {
1673 u8 dtim_len = pos[1];
1674 u8 dtim_period = pos[3];
1675 u8 *next = pos + 2 + dtim_len;
1676
02e37ba1 1677 if (dtim_len < 3)
e5ea92a7 1678 return -EINVAL;
02e37ba1 1679
e5ea92a7
CL		 1680 memmove(pos, next, end - next);
1681
1682 if (dtim_len > 3)
1683 skb_trim(skb, skb->len - (dtim_len - 3));
1684
1685 pos = end - (dtim_len + 2);
1686
1687 /* add the dummy at the end */
1688 pos[0] = WLAN_EID_TIM;
1689 pos[1] = 3;
1690 pos[2] = 0;
1691 pos[3] = dtim_period;
1692 pos[4] = 0;
1693 return 0;
1694 }
1695 pos += 2 + pos[1];
1696 }
1697 return 0;
1698}
1699
1700static int p54_beacon_update(struct ieee80211_hw *dev,
1701 struct ieee80211_vif *vif)
1702{
1703 struct p54_common *priv = dev->priv;
1704 struct sk_buff *beacon;
1705 int ret;
1706
1707 if (priv->cached_beacon) {
1708 p54_tx_cancel(dev, priv->cached_beacon);
1709 /* wait for the last beacon the be freed */
1710 msleep(10);
1711 }
1712
1713 beacon = ieee80211_beacon_get(dev, vif);
1714 if (!beacon)
1715 return -ENOMEM;
1716 ret = p54_beacon_tim(beacon);
1717 if (ret)
1718 return ret;
1719 ret = p54_tx(dev, beacon);
1720 if (ret)
1721 return ret;
1722 priv->cached_beacon = beacon;
1723 priv->tsf_high32 = 0;
1724 priv->tsf_low32 = 0;
1725
1726 return 0;
1727}
1728
0f1be978
CL		 1729static int p54_start(struct ieee80211_hw *dev)
1730{
1731 struct p54_common *priv = dev->priv;
1732 int err;
cc6de669 1733
9e7f3f8e 1734 mutex_lock(&priv->conf_mutex);
4150c572 1735 err = priv->open(dev);
40db0b22
CL		 1736 if (err)
1737 goto out;
0fdd7c5d
CL		 1738 P54_SET_QUEUE(priv->qos_params[0], 0x0002, 0x0003, 0x0007, 47);
1739 P54_SET_QUEUE(priv->qos_params[1], 0x0002, 0x0007, 0x000f, 94);
1740 P54_SET_QUEUE(priv->qos_params[2], 0x0003, 0x000f, 0x03ff, 0);
1741 P54_SET_QUEUE(priv->qos_params[3], 0x0007, 0x000f, 0x03ff, 0);
1742 err = p54_set_edcf(dev);
40db0b22
CL		 1743 if (err)
1744 goto out;
b2023ddc
CL		 1745
1746 memset(priv->bssid, ~0, ETH_ALEN);
40db0b22 1747 priv->mode = NL80211_IFTYPE_MONITOR;
b2023ddc
CL		 1748 err = p54_setup_mac(dev);
1749 if (err) {
1750 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1751 goto out;
1752 }
4150c572 1753
54fdb040
CL		 1754 queue_delayed_work(dev->workqueue, &priv->work, 0);
1755
40db0b22 1756out:
9e7f3f8e 1757 mutex_unlock(&priv->conf_mutex);
4150c572
JB		 1758 return err;
1759}
1760
1761static void p54_stop(struct ieee80211_hw *dev)
1762{
1763 struct p54_common *priv = dev->priv;
1764 struct sk_buff *skb;
cc6de669 1765
9e7f3f8e 1766 mutex_lock(&priv->conf_mutex);
59651e89 1767 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
54fdb040 1768 cancel_delayed_work_sync(&priv->work);
e5ea92a7
CL		 1769 if (priv->cached_beacon)
1770 p54_tx_cancel(dev, priv->cached_beacon);
1771
59651e89 1772 priv->stop(dev);
e039fa4a 1773 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 1774 kfree_skb(skb);
e5ea92a7 1775 priv->cached_beacon = NULL;
a0db663f 1776 priv->tsf_high32 = priv->tsf_low32 = 0;
9e7f3f8e 1777 mutex_unlock(&priv->conf_mutex);
4150c572
JB		 1778}
1779
eff1a59c
MW		 1780static int p54_add_interface(struct ieee80211_hw *dev,
1781 struct ieee80211_if_init_conf *conf)
1782{
1783 struct p54_common *priv = dev->priv;
eff1a59c 1784
9e7f3f8e
CL		 1785 mutex_lock(&priv->conf_mutex);
1786 if (priv->mode != NL80211_IFTYPE_MONITOR) {
1787 mutex_unlock(&priv->conf_mutex);
4150c572 1788 return -EOPNOTSUPP;
9e7f3f8e 1789 }
eff1a59c
MW		 1790
1791 switch (conf->type) {
05c914fe 1792 case NL80211_IFTYPE_STATION:
e5ea92a7
CL		 1793 case NL80211_IFTYPE_ADHOC:
1794 case NL80211_IFTYPE_AP:
d131bb59 1795 case NL80211_IFTYPE_MESH_POINT:
eff1a59c
MW		 1796 priv->mode = conf->type;
1797 break;
1798 default:
9e7f3f8e 1799 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1800 return -EOPNOTSUPP;
1801 }
1802
4150c572 1803 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
b2023ddc 1804 p54_setup_mac(dev);
eff1a59c 1805 p54_set_leds(dev, 1, 0, 0);
9e7f3f8e 1806 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1807 return 0;
1808}
1809
1810static void p54_remove_interface(struct ieee80211_hw *dev,
1811 struct ieee80211_if_init_conf *conf)
1812{
1813 struct p54_common *priv = dev->priv;
9e7f3f8e
CL		 1814
1815 mutex_lock(&priv->conf_mutex);
e5ea92a7
CL		 1816 if (priv->cached_beacon)
1817 p54_tx_cancel(dev, priv->cached_beacon);
05c914fe 1818 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1819 memset(priv->mac_addr, 0, ETH_ALEN);
b2023ddc
CL		 1820 memset(priv->bssid, 0, ETH_ALEN);
1821 p54_setup_mac(dev);
9e7f3f8e 1822 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1823}
1824
e8975581 1825static int p54_config(struct ieee80211_hw *dev, u32 changed)
eff1a59c
MW		 1826{
1827 int ret;
6041e2a0 1828 struct p54_common *priv = dev->priv;
e8975581 1829 struct ieee80211_conf *conf = &dev->conf;
eff1a59c 1830
6041e2a0 1831 mutex_lock(&priv->conf_mutex);
b2023ddc
CL		 1832 if (changed & IEEE80211_CONF_CHANGE_POWER)
1833 priv->output_power = conf->power_level << 2;
1834 if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
1835 ret = p54_setup_mac(dev);
1836 if (ret)
1837 goto out;
1838 }
1839 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
69ba3e5d 1840 ret = p54_scan(dev, P54_SCAN_EXIT, 0);
b2023ddc
CL		 1841 if (ret)
1842 goto out;
1843 }
1844
1845out:
6041e2a0 1846 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 1847 return ret;
1848}
1849
32bfd35d
JB		 1850static int p54_config_interface(struct ieee80211_hw *dev,
1851 struct ieee80211_vif *vif,
eff1a59c
MW		 1852 struct ieee80211_if_conf *conf)
1853{
1854 struct p54_common *priv = dev->priv;
e5ea92a7 1855 int ret = 0;
eff1a59c 1856
6041e2a0 1857 mutex_lock(&priv->conf_mutex);
b2023ddc
CL		 1858 if (conf->changed & IEEE80211_IFCC_BSSID) {
1859 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1860 ret = p54_setup_mac(dev);
e5ea92a7
CL		 1861 if (ret)
1862 goto out;
b2023ddc
CL		 1863 }
1864
1865 if (conf->changed & IEEE80211_IFCC_BEACON) {
69ba3e5d 1866 ret = p54_scan(dev, P54_SCAN_EXIT, 0);
e5ea92a7
CL		 1867 if (ret)
1868 goto out;
b2023ddc 1869 ret = p54_setup_mac(dev);
e5ea92a7
CL		 1870 if (ret)
1871 goto out;
b2023ddc
CL		 1872 ret = p54_beacon_update(dev, vif);
1873 if (ret)
1874 goto out;
1875 ret = p54_set_edcf(dev);
e5ea92a7
CL		 1876 if (ret)
1877 goto out;
e5ea92a7 1878 }
b2023ddc
CL		 1879
1880 ret = p54_set_leds(dev, 1, !is_multicast_ether_addr(priv->bssid), 0);
1881
e5ea92a7 1882out:
6041e2a0 1883 mutex_unlock(&priv->conf_mutex);
e5ea92a7 1884 return ret;
eff1a59c
MW		 1885}
1886
4150c572
JB		 1887static void p54_configure_filter(struct ieee80211_hw *dev,
1888 unsigned int changed_flags,
1889 unsigned int *total_flags,
1890 int mc_count, struct dev_mc_list *mclist)
1891{
1892 struct p54_common *priv = dev->priv;
1893
b2023ddc
CL		 1894 *total_flags &= FIF_PROMISC_IN_BSS |
1895 (*total_flags & FIF_PROMISC_IN_BSS) ?
1896 FIF_FCSFAIL : 0;
78d57eb2
CL		 1897
1898 priv->filter_flags = *total_flags;
4150c572 1899
b2023ddc
CL		 1900 if (changed_flags & FIF_PROMISC_IN_BSS)
1901 p54_setup_mac(dev);
4150c572
JB		 1902}
1903
e100bb64 1904static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW		 1905 const struct ieee80211_tx_queue_params *params)
1906{
1907 struct p54_common *priv = dev->priv;
9e7f3f8e 1908 int ret;
eff1a59c 1909
9e7f3f8e 1910 mutex_lock(&priv->conf_mutex);
3df5ee60 1911 if ((params) && !(queue > 4)) {
0fdd7c5d 1912 P54_SET_QUEUE(priv->qos_params[queue], params->aifs,
3330d7be 1913 params->cw_min, params->cw_max, params->txop);
b50563a6 1914 ret = p54_set_edcf(dev);
eff1a59c 1915 } else
9e7f3f8e 1916 ret = -EINVAL;
9e7f3f8e
CL		 1917 mutex_unlock(&priv->conf_mutex);
1918 return ret;
eff1a59c
MW		 1919}
1920
1b997534
CL		 1921static int p54_init_xbow_synth(struct ieee80211_hw *dev)
1922{
1923 struct p54_common *priv = dev->priv;
b92f30d6 1924 struct sk_buff *skb;
27df605e 1925 struct p54_xbow_synth *xbow;
1b997534 1926
27df605e
JL		 1927 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*xbow) +
1928 sizeof(struct p54_hdr),
1929 P54_CONTROL_TYPE_XBOW_SYNTH_CFG,
b92f30d6
CL		 1930 GFP_KERNEL);
1931 if (!skb)
1b997534
CL		 1932 return -ENOMEM;
1933
27df605e 1934 xbow = (struct p54_xbow_synth *)skb_put(skb, sizeof(*xbow));
1b997534
CL		 1935 xbow->magic1 = cpu_to_le16(0x1);
1936 xbow->magic2 = cpu_to_le16(0x2);
1937 xbow->freq = cpu_to_le16(5390);
b92f30d6
CL		 1938 memset(xbow->padding, 0, sizeof(xbow->padding));
1939 priv->tx(dev, skb, 1);
1b997534
CL		 1940 return 0;
1941}
1942
54fdb040 1943static void p54_work(struct work_struct *work)
cc6de669 1944{
54fdb040
CL		 1945 struct p54_common *priv = container_of(work, struct p54_common,
1946 work.work);
1947 struct ieee80211_hw *dev = priv->hw;
1948 struct sk_buff *skb;
1949
1950 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
1951 return ;
1952
1953 /*
1954 * TODO: walk through tx_queue and do the following tasks
1955 * 1. initiate bursts.
1956 * 2. cancel stuck frames / reset the device if necessary.
1957 */
cc6de669 1958
54fdb040
CL		 1959 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL, sizeof(struct p54_hdr) +
1960 sizeof(struct p54_statistics),
1961 P54_CONTROL_TYPE_STAT_READBACK, GFP_KERNEL);
1962 if (!skb)
1963 return ;
cc6de669 1964
54fdb040 1965 priv->tx(dev, skb, 0);
cc6de669
CL		 1966}
1967
eff1a59c
MW		 1968static int p54_get_stats(struct ieee80211_hw *dev,
1969 struct ieee80211_low_level_stats *stats)
1970{
cc6de669
CL		 1971 struct p54_common *priv = dev->priv;
1972
cc6de669 1973 memcpy(stats, &priv->stats, sizeof(*stats));
eff1a59c
MW		 1974 return 0;
1975}
1976
1977static int p54_get_tx_stats(struct ieee80211_hw *dev,
1978 struct ieee80211_tx_queue_stats *stats)
1979{
1980 struct p54_common *priv = dev->priv;
eff1a59c 1981
84df3ed3 1982 memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues);
eff1a59c
MW		 1983
1984 return 0;
1985}
1986
40333e4f
CL		 1987static void p54_bss_info_changed(struct ieee80211_hw *dev,
1988 struct ieee80211_vif *vif,
1989 struct ieee80211_bss_conf *info,
1990 u32 changed)
1991{
1992 struct p54_common *priv = dev->priv;
1993
1994 if (changed & BSS_CHANGED_ERP_SLOT) {
1995 priv->use_short_slot = info->use_short_slot;
0fdd7c5d 1996 p54_set_edcf(dev);
40333e4f 1997 }
ced09574
CL		 1998 if (changed & BSS_CHANGED_BASIC_RATES) {
1999 if (dev->conf.channel->band == IEEE80211_BAND_5GHZ)
2000 priv->basic_rate_mask = (info->basic_rates << 4);
2001 else
2002 priv->basic_rate_mask = info->basic_rates;
b2023ddc 2003 p54_setup_mac(dev);
ced09574 2004 if (priv->fw_var >= 0x500)
69ba3e5d 2005 p54_scan(dev, P54_SCAN_EXIT, 0);
ced09574
CL		 2006 }
2007 if (changed & BSS_CHANGED_ASSOC) {
2008 if (info->assoc) {
2009 priv->aid = info->aid;
2010 priv->wakeup_timer = info->beacon_int *
2011 info->dtim_period * 5;
b2023ddc 2012 p54_setup_mac(dev);
ced09574
CL		 2013 }
2014 }
2015
40333e4f
CL		 2016}
2017
25900ef0
CL		 2018static int p54_set_key(struct ieee80211_hw *dev, enum set_key_cmd cmd,
2019 const u8 *local_address, const u8 *address,
2020 struct ieee80211_key_conf *key)
2021{
2022 struct p54_common *priv = dev->priv;
2023 struct sk_buff *skb;
2024 struct p54_keycache *rxkey;
2025 u8 algo = 0;
2026
2027 if (modparam_nohwcrypt)
2028 return -EOPNOTSUPP;
2029
2030 if (cmd == DISABLE_KEY)
2031 algo = 0;
2032 else {
2033 switch (key->alg) {
2034 case ALG_TKIP:
2035 if (!(priv->privacy_caps & (BR_DESC_PRIV_CAP_MICHAEL |
2036 BR_DESC_PRIV_CAP_TKIP)))
2037 return -EOPNOTSUPP;
2038 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2039 algo = P54_CRYPTO_TKIPMICHAEL;
2040 break;
2041 case ALG_WEP:
2042 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_WEP))
2043 return -EOPNOTSUPP;
2044 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2045 algo = P54_CRYPTO_WEP;
2046 break;
2047 case ALG_CCMP:
2048 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP))
2049 return -EOPNOTSUPP;
2050 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2051 algo = P54_CRYPTO_AESCCMP;
2052 break;
2053 default:
2054 return -EINVAL;
2055 }
2056 }
2057
2058 if (key->keyidx > priv->rx_keycache_size) {
2059 /*
2060 * The device supports the choosen algorithm, but the firmware
2061 * does not provide enough key slots to store all of them.
2062 * So, incoming frames have to be decoded by the mac80211 stack,
2063 * but we can still offload encryption for outgoing frames.
2064 */
2065
2066 return 0;
2067 }
2068
2069 mutex_lock(&priv->conf_mutex);
2070 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*rxkey) +
2071 sizeof(struct p54_hdr), P54_CONTROL_TYPE_RX_KEYCACHE,
2072 GFP_ATOMIC);
2073 if (!skb) {
2074 mutex_unlock(&priv->conf_mutex);
2075 return -ENOMEM;
2076 }
2077
2078 /* TODO: some devices have 4 more free slots for rx keys */
2079 rxkey = (struct p54_keycache *)skb_put(skb, sizeof(*rxkey));
2080 rxkey->entry = key->keyidx;
2081 rxkey->key_id = key->keyidx;
2082 rxkey->key_type = algo;
2083 if (address)
2084 memcpy(rxkey->mac, address, ETH_ALEN);
2085 else
2086 memset(rxkey->mac, ~0, ETH_ALEN);
2087 if (key->alg != ALG_TKIP) {
2088 rxkey->key_len = min((u8)16, key->keylen);
2089 memcpy(rxkey->key, key->key, rxkey->key_len);
2090 } else {
2091 rxkey->key_len = 24;
2092 memcpy(rxkey->key, key->key, 16);
2093 memcpy(&(rxkey->key[16]), &(key->key
2094 [NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]), 8);
2095 }
2096
2097 priv->tx(dev, skb, 1);
2098 mutex_unlock(&priv->conf_mutex);
2099 return 0;
2100}
2101
eff1a59c
MW		 2102static const struct ieee80211_ops p54_ops = {
2103 .tx = p54_tx,
4150c572
JB		 2104 .start = p54_start,
2105 .stop = p54_stop,
eff1a59c
MW		 2106 .add_interface = p54_add_interface,
2107 .remove_interface = p54_remove_interface,
e5ea92a7 2108 .set_tim = p54_set_tim,
c772a08b 2109 .sta_notify = p54_sta_notify,
25900ef0 2110 .set_key = p54_set_key,
eff1a59c
MW		 2111 .config = p54_config,
2112 .config_interface = p54_config_interface,
40333e4f 2113 .bss_info_changed = p54_bss_info_changed,
4150c572 2114 .configure_filter = p54_configure_filter,
eff1a59c
MW		 2115 .conf_tx = p54_conf_tx,
2116 .get_stats = p54_get_stats,
2117 .get_tx_stats = p54_get_tx_stats
2118};
2119
2120struct ieee80211_hw *p54_init_common(size_t priv_data_len)
2121{
2122 struct ieee80211_hw *dev;
2123 struct p54_common *priv;
eff1a59c
MW		 2124
2125 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
2126 if (!dev)
2127 return NULL;
2128
2129 priv = dev->priv;
54fdb040 2130 priv->hw = dev;
05c914fe 2131 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
ced09574 2132 priv->basic_rate_mask = 0x15f;
eff1a59c 2133 skb_queue_head_init(&priv->tx_queue);
94585b09 2134 dev->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669
CL		 2135 IEEE80211_HW_SIGNAL_DBM |
2136 IEEE80211_HW_NOISE_DBM;
f59ac048 2137
d131bb59
CL		 2138 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2139 BIT(NL80211_IFTYPE_ADHOC) |
2140 BIT(NL80211_IFTYPE_AP) |
2141 BIT(NL80211_IFTYPE_MESH_POINT);
f59ac048 2142
eff1a59c 2143 dev->channel_change_time = 1000; /* TODO: find actual value */
9e7f3f8e
CL		 2144 priv->tx_stats[0].limit = 1; /* Beacon queue */
2145 priv->tx_stats[1].limit = 1; /* Probe queue for HW scan */
2146 priv->tx_stats[2].limit = 3; /* queue for MLMEs */
2147 priv->tx_stats[3].limit = 3; /* Broadcast / MC queue */
2148 priv->tx_stats[4].limit = 5; /* Data */
eff1a59c 2149 dev->queues = 1;
cc6de669 2150 priv->noise = -94;
c12abae3
JB		 2151 /*
2152 * We support at most 8 tries no matter which rate they're at,
2153 * we cannot support max_rates * max_rate_tries as we set it
2154 * here, but setting it correctly to 4/2 or so would limit us
2155 * artificially if the RC algorithm wants just two rates, so
2156 * let's say 4/7, we'll redistribute it at TX time, see the
2157 * comments there.
2158 */
2159 dev->max_rates = 4;
2160 dev->max_rate_tries = 7;
27df605e
JL		 2161 dev->extra_tx_headroom = sizeof(struct p54_hdr) + 4 +
2162 sizeof(struct p54_tx_data);
eff1a59c 2163
6041e2a0 2164 mutex_init(&priv->conf_mutex);
7cb77072 2165 init_completion(&priv->eeprom_comp);
54fdb040 2166 INIT_DELAYED_WORK(&priv->work, p54_work);
eff1a59c 2167
eff1a59c
MW		 2168 return dev;
2169}
2170EXPORT_SYMBOL_GPL(p54_init_common);
2171
2172void p54_free_common(struct ieee80211_hw *dev)
2173{
2174 struct p54_common *priv = dev->priv;
2175 kfree(priv->iq_autocal);
2176 kfree(priv->output_limit);
2177 kfree(priv->curve_data);
eff1a59c
MW		 2178}
2179EXPORT_SYMBOL_GPL(p54_free_common);
2180
2181static int __init p54_init(void)
2182{
2183 return 0;
2184}
2185
2186static void __exit p54_exit(void)
2187{
2188}
2189
2190module_init(p54_init);
2191module_exit(p54_exit);
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