[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / p54 / p54pci.c


/*
 * Linux device driver for PCI based Prism54
 *
 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
 *
 * Based on the islsm (softmac prism54) driver, which is:
 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <net/mac80211.h>

#include "p54.h"
#include "lmac.h"
#include "p54pci.h"

MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
MODULE_DESCRIPTION("Prism54 PCI wireless driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("prism54pci");
MODULE_FIRMWARE("isl3886pci");

static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3890) },
	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	{ PCI_DEVICE(0x10b7, 0x6001) },
	/* Intersil PRISM Indigo Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3877) },
	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3886) },
	/* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
	{ PCI_DEVICE(0x1260, 0xffff) },
	{ },
};

MODULE_DEVICE_TABLE(pci, p54p_table);

static int p54p_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	__le32 reg;
	int err;
	__le32 *data;
	u32 remains, left, device_addr;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();

	/* wait for the firmware to reset properly */
	mdelay(10);

	err = p54_parse_firmware(dev, priv->firmware);
	if (err)
		return err;

	if (priv->common.fw_interface != FW_LM86) {
		dev_err(&priv->pdev->dev, "wrong firmware, "
			"please get a LM86(PCI) firmware a try again.\n");
		return -EINVAL;
	}

	data = (__le32 *) priv->firmware->data;
	remains = priv->firmware->size;
	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	while (remains) {
		u32 i = 0;
		left = min((u32)0x1000, remains);
		P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
		P54P_READ(int_enable);

		device_addr += 0x1000;
		while (i < left) {
			P54P_WRITE(direct_mem_win[i], *data++);
			i += sizeof(u32);
		}

		remains -= left;
		P54P_READ(int_enable);
	}

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	/* wait for the firmware to boot properly */
	mdelay(100);

	return 0;
}

static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf, u32 index)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	u32 limit, idx, i;

	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
	limit = idx;
	limit -= index;
	limit = ring_limit - limit;

	i = idx % ring_limit;
	while (limit-- > 1) {
		struct p54p_desc *desc = &ring[i];

		if (!desc->host_addr) {
			struct sk_buff *skb;
			dma_addr_t mapping;
			skb = dev_alloc_skb(priv->common.rx_mtu + 32);
			if (!skb)
				break;

			mapping = pci_map_single(priv->pdev,
						 skb_tail_pointer(skb),
						 priv->common.rx_mtu + 32,
						 PCI_DMA_FROMDEVICE);

			if (pci_dma_mapping_error(priv->pdev, mapping)) {
				dev_kfree_skb_any(skb);
				dev_err(&priv->pdev->dev,
					"RX DMA Mapping error\n");
				break;
			}

			desc->host_addr = cpu_to_le32(mapping);
			desc->device_addr = 0;	// FIXME: necessary?
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
			desc->flags = 0;
			rx_buf[i] = skb;
		}

		i++;
		idx++;
		i %= ring_limit;
	}

	wmb();
	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
}

static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	idx %= ring_limit;
	while (i != idx) {
		u16 len;
		struct sk_buff *skb;
		dma_addr_t dma_addr;
		desc = &ring[i];
		len = le16_to_cpu(desc->len);
		skb = rx_buf[i];

		if (!skb) {
			i++;
			i %= ring_limit;
			continue;
		}

		if (unlikely(len > priv->common.rx_mtu)) {
			if (net_ratelimit())
				dev_err(&priv->pdev->dev, "rx'd frame size "
					"exceeds length threshold.\n");

			len = priv->common.rx_mtu;
		}
		dma_addr = le32_to_cpu(desc->host_addr);
		pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
			priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
		skb_put(skb, len);

		if (p54_rx(dev, skb)) {
			pci_unmap_single(priv->pdev, dma_addr,
				priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
			rx_buf[i] = NULL;
			desc->host_addr = cpu_to_le32(0);
		} else {
			skb_trim(skb, 0);
			pci_dma_sync_single_for_device(priv->pdev, dma_addr,
				priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
		}

		i++;
		i %= ring_limit;
	}

	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
}

static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **tx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	struct sk_buff *skb;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	idx %= ring_limit;

	while (i != idx) {
		desc = &ring[i];

		skb = tx_buf[i];
		tx_buf[i] = NULL;

		pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
				 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);

		desc->host_addr = 0;
		desc->device_addr = 0;
		desc->len = 0;
		desc->flags = 0;

		if (skb && FREE_AFTER_TX(skb))
			p54_free_skb(dev, skb);

		i++;
		i %= ring_limit;
	}
}

static void p54p_tasklet(unsigned long dev_id)
{
	struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;

	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
			   ARRAY_SIZE(ring_control->tx_mgmt),
			   priv->tx_buf_mgmt);

	p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
			   ARRAY_SIZE(ring_control->tx_data),
			   priv->tx_buf_data);

	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
		ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);

	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
		ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);

	wmb();
	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
}

static irqreturn_t p54p_interrupt(int irq, void *dev_id)
{
	struct ieee80211_hw *dev = dev_id;
	struct p54p_priv *priv = dev->priv;
	__le32 reg;

	reg = P54P_READ(int_ident);
	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
		goto out;
	}
	P54P_WRITE(int_ack, reg);

	reg &= P54P_READ(int_enable);

	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
		tasklet_schedule(&priv->tasklet);
	else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
		complete(&priv->boot_comp);

out:
	return reg ? IRQ_HANDLED : IRQ_NONE;
}

static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	unsigned long flags;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	dma_addr_t mapping;
	u32 device_idx, idx, i;

	spin_lock_irqsave(&priv->lock, flags);
	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	idx = le32_to_cpu(ring_control->host_idx[1]);
	i = idx % ARRAY_SIZE(ring_control->tx_data);

	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
				 PCI_DMA_TODEVICE);
	if (pci_dma_mapping_error(priv->pdev, mapping)) {
		spin_unlock_irqrestore(&priv->lock, flags);
		p54_free_skb(dev, skb);
		dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
		return ;
	}
	priv->tx_buf_data[i] = skb;

	desc = &ring_control->tx_data[i];
	desc->host_addr = cpu_to_le32(mapping);
	desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
	desc->len = cpu_to_le16(skb->len);
	desc->flags = 0;

	wmb();
	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
	spin_unlock_irqrestore(&priv->lock, flags);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
}

static void p54p_stop(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	unsigned int i;
	struct p54p_desc *desc;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	free_irq(priv->pdev->irq, dev);

	tasklet_kill(&priv->tasklet);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
		desc = &ring_control->rx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_data[i]);
		priv->rx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
		desc = &ring_control->rx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_mgmt[i]);
		priv->rx_buf_mgmt[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
		desc = &ring_control->tx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		p54_free_skb(dev, priv->tx_buf_data[i]);
		priv->tx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
		desc = &ring_control->tx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		p54_free_skb(dev, priv->tx_buf_mgmt[i]);
		priv->tx_buf_mgmt[i] = NULL;
	}

	memset(ring_control, 0, sizeof(*ring_control));
}

static int p54p_open(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	int err;

	init_completion(&priv->boot_comp);
	err = request_irq(priv->pdev->irq, p54p_interrupt,
			  IRQF_SHARED, "p54pci", dev);
	if (err) {
		dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
		return err;
	}

	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	err = p54p_upload_firmware(dev);
	if (err) {
		free_irq(priv->pdev->irq, dev);
		return err;
	}
	priv->rx_idx_data = priv->tx_idx_data = 0;
	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;

	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
		ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);

	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
		ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);

	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	P54P_READ(ring_control_base);
	wmb();
	udelay(10);

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	P54P_READ(dev_int);

	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
		wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
		p54p_stop(dev);
		return -ETIMEDOUT;
	}

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
	wmb();
	udelay(10);

	return 0;
}

static int __devinit p54p_probe(struct pci_dev *pdev,
				const struct pci_device_id *id)
{
	struct p54p_priv *priv;
	struct ieee80211_hw *dev;
	unsigned long mem_addr, mem_len;
	int err;

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Cannot enable new PCI device\n");
		return err;
	}

	mem_addr = pci_resource_start(pdev, 0);
	mem_len = pci_resource_len(pdev, 0);
	if (mem_len < sizeof(struct p54p_csr)) {
		dev_err(&pdev->dev, "Too short PCI resources\n");
		goto err_disable_dev;
	}

	err = pci_request_regions(pdev, "p54pci");
	if (err) {
		dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
		goto err_disable_dev;
	}

	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
	    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
		dev_err(&pdev->dev, "No suitable DMA available\n");
		goto err_free_reg;
	}

	pci_set_master(pdev);
	pci_try_set_mwi(pdev);

	pci_write_config_byte(pdev, 0x40, 0);
	pci_write_config_byte(pdev, 0x41, 0);

	dev = p54_init_common(sizeof(*priv));
	if (!dev) {
		dev_err(&pdev->dev, "ieee80211 alloc failed\n");
		err = -ENOMEM;
		goto err_free_reg;
	}

	priv = dev->priv;
	priv->pdev = pdev;

	SET_IEEE80211_DEV(dev, &pdev->dev);
	pci_set_drvdata(pdev, dev);

	priv->map = ioremap(mem_addr, mem_len);
	if (!priv->map) {
		dev_err(&pdev->dev, "Cannot map device memory\n");
		err = -ENOMEM;
		goto err_free_dev;
	}

	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
						  &priv->ring_control_dma);
	if (!priv->ring_control) {
		dev_err(&pdev->dev, "Cannot allocate rings\n");
		err = -ENOMEM;
		goto err_iounmap;
	}
	priv->common.open = p54p_open;
	priv->common.stop = p54p_stop;
	priv->common.tx = p54p_tx;

	spin_lock_init(&priv->lock);
	tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);

	err = request_firmware(&priv->firmware, "isl3886pci",
			       &priv->pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
		err = request_firmware(&priv->firmware, "isl3886",
				       &priv->pdev->dev);
		if (err)
			goto err_free_common;
	}

	err = p54p_open(dev);
	if (err)
		goto err_free_common;
	err = p54_read_eeprom(dev);
	p54p_stop(dev);
	if (err)
		goto err_free_common;

	err = p54_register_common(dev, &pdev->dev);
	if (err)
		goto err_free_common;

	return 0;

 err_free_common:
	release_firmware(priv->firmware);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);

 err_iounmap:
	iounmap(priv->map);

 err_free_dev:
	pci_set_drvdata(pdev, NULL);
	p54_free_common(dev);

 err_free_reg:
	pci_release_regions(pdev);
 err_disable_dev:
	pci_disable_device(pdev);
	return err;
}

static void __devexit p54p_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv;

	if (!dev)
		return;

	p54_unregister_common(dev);
	priv = dev->priv;
	release_firmware(priv->firmware);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);
	iounmap(priv->map);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	p54_free_common(dev);
}

#ifdef CONFIG_PM
static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		ieee80211_stop_queues(dev);
		p54p_stop(dev);
	}

	pci_save_state(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	return 0;
}

static int p54p_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		p54p_open(dev);
		ieee80211_wake_queues(dev);
	}

	return 0;
}
#endif /* CONFIG_PM */

static struct pci_driver p54p_driver = {
	.name		= "p54pci",
	.id_table	= p54p_table,
	.probe		= p54p_probe,
	.remove		= __devexit_p(p54p_remove),
#ifdef CONFIG_PM
	.suspend	= p54p_suspend,
	.resume		= p54p_resume,
#endif /* CONFIG_PM */
};

static int __init p54p_init(void)
{
	return pci_register_driver(&p54p_driver);
}

static void __exit p54p_exit(void)
{
	pci_unregister_driver(&p54p_driver);
}

module_init(p54p_init);
module_exit(p54p_exit);
Commit	Line	Data
eff1a59c MW	1
	2	/*
	3	* Linux device driver for PCI based Prism54
	4	*
	5	* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
7262d593	6	* Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
eff1a59c MW	7	*
	8	* Based on the islsm (softmac prism54) driver, which is:
	9	* Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/pci.h>
5a0e3ad6	18	#include <linux/slab.h>
eff1a59c MW	19	#include <linux/firmware.h>
	20	#include <linux/etherdevice.h>
	21	#include <linux/delay.h>
	22	#include <linux/completion.h>
	23	#include <net/mac80211.h>
	24
	25	#include "p54.h"
d8c92107	26	#include "lmac.h"
eff1a59c MW	27	#include "p54pci.h"
	28
	29	MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
	30	MODULE_DESCRIPTION("Prism54 PCI wireless driver");
	31	MODULE_LICENSE("GPL");
	32	MODULE_ALIAS("prism54pci");
9a8675d7	33	MODULE_FIRMWARE("isl3886pci");
eff1a59c	34
a3aa1884	35	static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
eff1a59c MW	36	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	37	{ PCI_DEVICE(0x1260, 0x3890) },
	38	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	39	{ PCI_DEVICE(0x10b7, 0x6001) },
	40	/* Intersil PRISM Indigo Wireless LAN adapter */
	41	{ PCI_DEVICE(0x1260, 0x3877) },
	42	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	43	{ PCI_DEVICE(0x1260, 0x3886) },
50900f16 JA	44	/* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
50900f16 JA	45	{ PCI_DEVICE(0x1260, 0xffff) },
90f4dd0f	46	{ },
eff1a59c MW	47	};
	48
	49	MODULE_DEVICE_TABLE(pci, p54p_table);
	50
	51	static int p54p_upload_firmware(struct ieee80211_hw *dev)
	52	{
	53	struct p54p_priv *priv = dev->priv;
eff1a59c MW	54	__le32 reg;
eff1a59c MW	55	int err;
8160c031	56	__le32 *data;
eff1a59c MW	57	u32 remains, left, device_addr;
eff1a59c MW	58
8160c031	59	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	60	P54P_READ(int_enable);
	61	udelay(10);
	62
	63	reg = P54P_READ(ctrl_stat);
	64	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	65	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	66	P54P_WRITE(ctrl_stat, reg);
	67	P54P_READ(ctrl_stat);
	68	udelay(10);
	69
	70	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	71	P54P_WRITE(ctrl_stat, reg);
	72	wmb();
	73	udelay(10);
	74
	75	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	76	P54P_WRITE(ctrl_stat, reg);
	77	wmb();
	78
40db0b22 CL	79	/* wait for the firmware to reset properly */
40db0b22 CL	80	mdelay(10);
eff1a59c	81
40db0b22 CL	82	err = p54_parse_firmware(dev, priv->firmware);
40db0b22 CL	83	if (err)
4e416a6f	84	return err;
eff1a59c	85
e365f160 CL	86	if (priv->common.fw_interface != FW_LM86) {
	87	dev_err(&priv->pdev->dev, "wrong firmware, "
	88	"please get a LM86(PCI) firmware a try again.\n");
	89	return -EINVAL;
	90	}
	91
40db0b22 CL	92	data = (__le32 *) priv->firmware->data;
40db0b22 CL	93	remains = priv->firmware->size;
eff1a59c MW	94	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	95	while (remains) {
	96	u32 i = 0;
	97	left = min((u32)0x1000, remains);
	98	P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
	99	P54P_READ(int_enable);
	100
	101	device_addr += 0x1000;
	102	while (i < left) {
	103	P54P_WRITE(direct_mem_win[i], *data++);
	104	i += sizeof(u32);
	105	}
	106
	107	remains -= left;
	108	P54P_READ(int_enable);
	109	}
	110
eff1a59c MW	111	reg = P54P_READ(ctrl_stat);
	112	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	113	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	114	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	115	P54P_WRITE(ctrl_stat, reg);
	116	P54P_READ(ctrl_stat);
	117	udelay(10);
	118
	119	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	120	P54P_WRITE(ctrl_stat, reg);
	121	wmb();
	122	udelay(10);
	123
	124	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	125	P54P_WRITE(ctrl_stat, reg);
	126	wmb();
	127	udelay(10);
	128
7cb77072	129	/* wait for the firmware to boot properly */
eff1a59c	130	mdelay(100);
eff1a59c	131
7cb77072	132	return 0;
eff1a59c MW	133	}
eff1a59c MW	134
7262d593 CL	135	static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
7262d593 CL	136	int ring_index, struct p54p_desc *ring, u32 ring_limit,
5988f385	137	struct sk_buff **rx_buf, u32 index)
eff1a59c MW	138	{
eff1a59c MW	139	struct p54p_priv *priv = dev->priv;
eb76bf29	140	struct p54p_ring_control *ring_control = priv->ring_control;
7262d593	141	u32 limit, idx, i;
eff1a59c	142
7262d593 CL	143	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
7262d593 CL	144	limit = idx;
103823db	145	limit -= index;
7262d593	146	limit = ring_limit - limit;
eff1a59c	147
7262d593	148	i = idx % ring_limit;
eff1a59c	149	while (limit-- > 1) {
7262d593	150	struct p54p_desc *desc = &ring[i];
eff1a59c MW	151
	152	if (!desc->host_addr) {
	153	struct sk_buff *skb;
	154	dma_addr_t mapping;
4e416a6f	155	skb = dev_alloc_skb(priv->common.rx_mtu + 32);
eff1a59c MW	156	if (!skb)
	157	break;
	158
	159	mapping = pci_map_single(priv->pdev,
	160	skb_tail_pointer(skb),
4e416a6f	161	priv->common.rx_mtu + 32,
eff1a59c	162	PCI_DMA_FROMDEVICE);
288c8ce8 CL	163
	164	if (pci_dma_mapping_error(priv->pdev, mapping)) {
	165	dev_kfree_skb_any(skb);
	166	dev_err(&priv->pdev->dev,
	167	"RX DMA Mapping error\n");
	168	break;
	169	}
	170
eff1a59c MW	171	desc->host_addr = cpu_to_le32(mapping);
eff1a59c MW	172	desc->device_addr = 0; // FIXME: necessary?
4e416a6f	173	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
eff1a59c	174	desc->flags = 0;
7262d593	175	rx_buf[i] = skb;
eff1a59c MW	176	}
eff1a59c MW	177
7262d593	178	i++;
eff1a59c	179	idx++;
7262d593	180	i %= ring_limit;
eff1a59c MW	181	}
	182
	183	wmb();
7262d593 CL	184	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
	185	}
	186
	187	static void p54p_check_rx_ring(struct ieee80211_hw dev, u32 index,
	188	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	189	struct sk_buff **rx_buf)
	190	{
	191	struct p54p_priv *priv = dev->priv;
	192	struct p54p_ring_control *ring_control = priv->ring_control;
	193	struct p54p_desc *desc;
	194	u32 idx, i;
	195
	196	i = (*index) % ring_limit;
	197	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	198	idx %= ring_limit;
	199	while (i != idx) {
	200	u16 len;
	201	struct sk_buff *skb;
0bf719df	202	dma_addr_t dma_addr;
7262d593 CL	203	desc = &ring[i];
	204	len = le16_to_cpu(desc->len);
	205	skb = rx_buf[i];
	206
0c25970d CL	207	if (!skb) {
	208	i++;
	209	i %= ring_limit;
7262d593	210	continue;
0c25970d	211	}
f5300e04 CL	212
	213	if (unlikely(len > priv->common.rx_mtu)) {
	214	if (net_ratelimit())
	215	dev_err(&priv->pdev->dev, "rx'd frame size "
	216	"exceeds length threshold.\n");
	217
	218	len = priv->common.rx_mtu;
	219	}
0bf719df CL	220	dma_addr = le32_to_cpu(desc->host_addr);
	221	pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
	222	priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
7262d593 CL	223	skb_put(skb, len);
	224
	225	if (p54_rx(dev, skb)) {
0bf719df CL	226	pci_unmap_single(priv->pdev, dma_addr,
0bf719df CL	227	priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
7262d593	228	rx_buf[i] = NULL;
0bf719df	229	desc->host_addr = cpu_to_le32(0);
7262d593 CL	230	} else {
7262d593 CL	231	skb_trim(skb, 0);
0bf719df CL	232	pci_dma_sync_single_for_device(priv->pdev, dma_addr,
0bf719df CL	233	priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
4e416a6f	234	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
7262d593 CL	235	}
	236
	237	i++;
	238	i %= ring_limit;
	239	}
	240
5988f385	241	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
7262d593 CL	242	}
7262d593 CL	243
7262d593 CL	244	static void p54p_check_tx_ring(struct ieee80211_hw dev, u32 index,
7262d593 CL	245	int ring_index, struct p54p_desc *ring, u32 ring_limit,
d713804c	246	struct sk_buff **tx_buf)
7262d593 CL	247	{
	248	struct p54p_priv *priv = dev->priv;
	249	struct p54p_ring_control *ring_control = priv->ring_control;
	250	struct p54p_desc *desc;
d713804c	251	struct sk_buff *skb;
7262d593 CL	252	u32 idx, i;
	253
	254	i = (*index) % ring_limit;
0250ecec	255	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
7262d593 CL	256	idx %= ring_limit;
	257
	258	while (i != idx) {
	259	desc = &ring[i];
d713804c CL	260
d713804c CL	261	skb = tx_buf[i];
7262d593 CL	262	tx_buf[i] = NULL;
	263
	264	pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
	265	le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
	266
	267	desc->host_addr = 0;
	268	desc->device_addr = 0;
	269	desc->len = 0;
	270	desc->flags = 0;
	271
b92f7d30	272	if (skb && FREE_AFTER_TX(skb))
d713804c	273	p54_free_skb(dev, skb);
d713804c	274
7262d593 CL	275	i++;
	276	i %= ring_limit;
	277	}
	278	}
	279
d713804c	280	static void p54p_tasklet(unsigned long dev_id)
7262d593 CL	281	{
	282	struct ieee80211_hw dev = (struct ieee80211_hw )dev_id;
	283	struct p54p_priv *priv = dev->priv;
	284	struct p54p_ring_control *ring_control = priv->ring_control;
	285
d4cde88c HG	286	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
	287	ARRAY_SIZE(ring_control->tx_mgmt),
	288	priv->tx_buf_mgmt);
	289
	290	p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
	291	ARRAY_SIZE(ring_control->tx_data),
	292	priv->tx_buf_data);
	293
7262d593 CL	294	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
	295	ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
	296
	297	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
	298	ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
	299
	300	wmb();
	301	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
eff1a59c MW	302	}
	303
	304	static irqreturn_t p54p_interrupt(int irq, void *dev_id)
	305	{
	306	struct ieee80211_hw *dev = dev_id;
	307	struct p54p_priv *priv = dev->priv;
	308	__le32 reg;
	309
eff1a59c	310	reg = P54P_READ(int_ident);
8160c031	311	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
d713804c	312	goto out;
eff1a59c	313	}
eff1a59c MW	314	P54P_WRITE(int_ack, reg);
	315
	316	reg &= P54P_READ(int_enable);
	317
d713804c CL	318	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
	319	tasklet_schedule(&priv->tasklet);
	320	else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
eff1a59c MW	321	complete(&priv->boot_comp);
eff1a59c MW	322
d713804c	323	out:
eff1a59c MW	324	return reg ? IRQ_HANDLED : IRQ_NONE;
	325	}
	326
0a5ec96a	327	static void p54p_tx(struct ieee80211_hw dev, struct sk_buff skb)
eff1a59c	328	{
b92f7d30	329	unsigned long flags;
eff1a59c	330	struct p54p_priv *priv = dev->priv;
eb76bf29	331	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	332	struct p54p_desc *desc;
	333	dma_addr_t mapping;
	334	u32 device_idx, idx, i;
	335
	336	spin_lock_irqsave(&priv->lock, flags);
eb76bf29 DT	337	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	338	idx = le32_to_cpu(ring_control->host_idx[1]);
	339	i = idx % ARRAY_SIZE(ring_control->tx_data);
eff1a59c	340
b92f30d6 CL	341	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
b92f30d6 CL	342	PCI_DMA_TODEVICE);
288c8ce8 CL	343	if (pci_dma_mapping_error(priv->pdev, mapping)) {
	344	spin_unlock_irqrestore(&priv->lock, flags);
	345	p54_free_skb(dev, skb);
	346	dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
	347	return ;
	348	}
	349	priv->tx_buf_data[i] = skb;
	350
eb76bf29	351	desc = &ring_control->tx_data[i];
eff1a59c	352	desc->host_addr = cpu_to_le32(mapping);
27df605e	353	desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
b92f30d6	354	desc->len = cpu_to_le16(skb->len);
eff1a59c MW	355	desc->flags = 0;
	356
	357	wmb();
eb76bf29	358	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
eff1a59c MW	359	spin_unlock_irqrestore(&priv->lock, flags);
	360
	361	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	362	P54P_READ(dev_int);
eff1a59c MW	363	}
eff1a59c MW	364
eff1a59c MW	365	static void p54p_stop(struct ieee80211_hw *dev)
	366	{
	367	struct p54p_priv *priv = dev->priv;
eb76bf29	368	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	369	unsigned int i;
	370	struct p54p_desc *desc;
	371
8160c031	372	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	373	P54P_READ(int_enable);
	374	udelay(10);
	375
	376	free_irq(priv->pdev->irq, dev);
	377
b92f7d30 CL	378	tasklet_kill(&priv->tasklet);
b92f7d30 CL	379
eff1a59c MW	380	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
eff1a59c MW	381
7262d593	382	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
eb76bf29	383	desc = &ring_control->rx_data[i];
eff1a59c	384	if (desc->host_addr)
7262d593 CL	385	pci_unmap_single(priv->pdev,
7262d593 CL	386	le32_to_cpu(desc->host_addr),
4e416a6f CL	387	priv->common.rx_mtu + 32,
4e416a6f CL	388	PCI_DMA_FROMDEVICE);
7262d593 CL	389	kfree_skb(priv->rx_buf_data[i]);
7262d593 CL	390	priv->rx_buf_data[i] = NULL;
eff1a59c MW	391	}
eff1a59c MW	392
7262d593 CL	393	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
	394	desc = &ring_control->rx_mgmt[i];
	395	if (desc->host_addr)
	396	pci_unmap_single(priv->pdev,
	397	le32_to_cpu(desc->host_addr),
4e416a6f CL	398	priv->common.rx_mtu + 32,
4e416a6f CL	399	PCI_DMA_FROMDEVICE);
7262d593 CL	400	kfree_skb(priv->rx_buf_mgmt[i]);
	401	priv->rx_buf_mgmt[i] = NULL;
	402	}
	403
	404	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
eb76bf29	405	desc = &ring_control->tx_data[i];
eff1a59c	406	if (desc->host_addr)
7262d593 CL	407	pci_unmap_single(priv->pdev,
	408	le32_to_cpu(desc->host_addr),
	409	le16_to_cpu(desc->len),
	410	PCI_DMA_TODEVICE);
	411
b92f30d6	412	p54_free_skb(dev, priv->tx_buf_data[i]);
7262d593 CL	413	priv->tx_buf_data[i] = NULL;
	414	}
	415
	416	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
	417	desc = &ring_control->tx_mgmt[i];
	418	if (desc->host_addr)
	419	pci_unmap_single(priv->pdev,
	420	le32_to_cpu(desc->host_addr),
	421	le16_to_cpu(desc->len),
	422	PCI_DMA_TODEVICE);
eff1a59c	423
b92f30d6	424	p54_free_skb(dev, priv->tx_buf_mgmt[i]);
7262d593	425	priv->tx_buf_mgmt[i] = NULL;
eff1a59c MW	426	}
eff1a59c MW	427
7262d593	428	memset(ring_control, 0, sizeof(*ring_control));
eff1a59c MW	429	}
eff1a59c MW	430
35961627 CL	431	static int p54p_open(struct ieee80211_hw *dev)
	432	{
	433	struct p54p_priv *priv = dev->priv;
	434	int err;
	435
	436	init_completion(&priv->boot_comp);
8fbd90b0	437	err = request_irq(priv->pdev->irq, p54p_interrupt,
35961627 CL	438	IRQF_SHARED, "p54pci", dev);
35961627 CL	439	if (err) {
ad5e72ee	440	dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
35961627 CL	441	return err;
	442	}
	443
	444	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	445	err = p54p_upload_firmware(dev);
	446	if (err) {
	447	free_irq(priv->pdev->irq, dev);
	448	return err;
	449	}
	450	priv->rx_idx_data = priv->tx_idx_data = 0;
	451	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
	452
	453	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
5988f385	454	ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
35961627 CL	455
35961627 CL	456	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
5988f385	457	ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
35961627 CL	458
	459	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	460	P54P_READ(ring_control_base);
	461	wmb();
	462	udelay(10);
	463
	464	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	465	P54P_READ(int_enable);
	466	wmb();
	467	udelay(10);
	468
	469	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	470	P54P_READ(dev_int);
	471
	472	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
5db55844	473	wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
35961627 CL	474	p54p_stop(dev);
	475	return -ETIMEDOUT;
	476	}
	477
	478	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	479	P54P_READ(int_enable);
	480	wmb();
	481	udelay(10);
	482
	483	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	484	P54P_READ(dev_int);
	485	wmb();
	486	udelay(10);
	487
	488	return 0;
	489	}
	490
eff1a59c MW	491	static int __devinit p54p_probe(struct pci_dev *pdev,
	492	const struct pci_device_id *id)
	493	{
	494	struct p54p_priv *priv;
	495	struct ieee80211_hw *dev;
	496	unsigned long mem_addr, mem_len;
	497	int err;
eff1a59c MW	498
	499	err = pci_enable_device(pdev);
	500	if (err) {
ad5e72ee	501	dev_err(&pdev->dev, "Cannot enable new PCI device\n");
eff1a59c MW	502	return err;
	503	}
	504
	505	mem_addr = pci_resource_start(pdev, 0);
	506	mem_len = pci_resource_len(pdev, 0);
	507	if (mem_len < sizeof(struct p54p_csr)) {
ad5e72ee	508	dev_err(&pdev->dev, "Too short PCI resources\n");
40db0b22	509	goto err_disable_dev;
eff1a59c MW	510	}
eff1a59c MW	511
32ddf071	512	err = pci_request_regions(pdev, "p54pci");
eff1a59c	513	if (err) {
ad5e72ee	514	dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
40db0b22	515	goto err_disable_dev;
eff1a59c MW	516	}
eff1a59c MW	517
e930438c YH	518	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) \|\|
e930438c YH	519	pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
ad5e72ee	520	dev_err(&pdev->dev, "No suitable DMA available\n");
eff1a59c MW	521	goto err_free_reg;
	522	}
	523
	524	pci_set_master(pdev);
	525	pci_try_set_mwi(pdev);
	526
	527	pci_write_config_byte(pdev, 0x40, 0);
	528	pci_write_config_byte(pdev, 0x41, 0);
	529
	530	dev = p54_init_common(sizeof(*priv));
	531	if (!dev) {
ad5e72ee	532	dev_err(&pdev->dev, "ieee80211 alloc failed\n");
eff1a59c MW	533	err = -ENOMEM;
	534	goto err_free_reg;
	535	}
	536
	537	priv = dev->priv;
	538	priv->pdev = pdev;
	539
	540	SET_IEEE80211_DEV(dev, &pdev->dev);
	541	pci_set_drvdata(pdev, dev);
	542
	543	priv->map = ioremap(mem_addr, mem_len);
	544	if (!priv->map) {
ad5e72ee CL	545	dev_err(&pdev->dev, "Cannot map device memory\n");
ad5e72ee CL	546	err = -ENOMEM;
eff1a59c MW	547	goto err_free_dev;
	548	}
	549
	550	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
	551	&priv->ring_control_dma);
	552	if (!priv->ring_control) {
ad5e72ee	553	dev_err(&pdev->dev, "Cannot allocate rings\n");
eff1a59c MW	554	err = -ENOMEM;
	555	goto err_iounmap;
	556	}
eff1a59c MW	557	priv->common.open = p54p_open;
	558	priv->common.stop = p54p_stop;
	559	priv->common.tx = p54p_tx;
	560
	561	spin_lock_init(&priv->lock);
d713804c	562	tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
eff1a59c	563
40db0b22 CL	564	err = request_firmware(&priv->firmware, "isl3886pci",
	565	&priv->pdev->dev);
	566	if (err) {
ad5e72ee	567	dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
40db0b22 CL	568	err = request_firmware(&priv->firmware, "isl3886",
	569	&priv->pdev->dev);
	570	if (err)
	571	goto err_free_common;
	572	}
	573
35961627 CL	574	err = p54p_open(dev);
	575	if (err)
	576	goto err_free_common;
7cb77072 CL	577	err = p54_read_eeprom(dev);
	578	p54p_stop(dev);
	579	if (err)
35961627	580	goto err_free_common;
7cb77072	581
2ac71072 CL	582	err = p54_register_common(dev, &pdev->dev);
2ac71072 CL	583	if (err)
eff1a59c	584	goto err_free_common;
eff1a59c	585
eff1a59c MW	586	return 0;
	587
	588	err_free_common:
40db0b22	589	release_firmware(priv->firmware);
eff1a59c MW	590	pci_free_consistent(pdev, sizeof(*priv->ring_control),
	591	priv->ring_control, priv->ring_control_dma);
	592
	593	err_iounmap:
	594	iounmap(priv->map);
	595
	596	err_free_dev:
	597	pci_set_drvdata(pdev, NULL);
d8c92107	598	p54_free_common(dev);
eff1a59c MW	599
	600	err_free_reg:
	601	pci_release_regions(pdev);
40db0b22	602	err_disable_dev:
eff1a59c MW	603	pci_disable_device(pdev);
	604	return err;
	605	}
	606
	607	static void __devexit p54p_remove(struct pci_dev *pdev)
	608	{
	609	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	610	struct p54p_priv *priv;
	611
	612	if (!dev)
	613	return;
	614
d8c92107	615	p54_unregister_common(dev);
eff1a59c	616	priv = dev->priv;
40db0b22	617	release_firmware(priv->firmware);
eff1a59c MW	618	pci_free_consistent(pdev, sizeof(*priv->ring_control),
eff1a59c MW	619	priv->ring_control, priv->ring_control_dma);
eff1a59c MW	620	iounmap(priv->map);
	621	pci_release_regions(pdev);
	622	pci_disable_device(pdev);
d8c92107	623	p54_free_common(dev);
eff1a59c MW	624	}
	625
	626	#ifdef CONFIG_PM
	627	static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
	628	{
	629	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	630	struct p54p_priv *priv = dev->priv;
	631
05c914fe	632	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c MW	633	ieee80211_stop_queues(dev);
	634	p54p_stop(dev);
	635	}
	636
	637	pci_save_state(pdev);
	638	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	639	return 0;
	640	}
	641
	642	static int p54p_resume(struct pci_dev *pdev)
	643	{
	644	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	645	struct p54p_priv *priv = dev->priv;
	646
	647	pci_set_power_state(pdev, PCI_D0);
	648	pci_restore_state(pdev);
	649
05c914fe	650	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c	651	p54p_open(dev);
36d6825b	652	ieee80211_wake_queues(dev);
eff1a59c MW	653	}
	654
	655	return 0;
	656	}
	657	#endif /* CONFIG_PM */
	658
	659	static struct pci_driver p54p_driver = {
32ddf071	660	.name = "p54pci",
eff1a59c MW	661	.id_table = p54p_table,
	662	.probe = p54p_probe,
	663	.remove = __devexit_p(p54p_remove),
	664	#ifdef CONFIG_PM
	665	.suspend = p54p_suspend,
	666	.resume = p54p_resume,
	667	#endif /* CONFIG_PM */
	668	};
	669
	670	static int __init p54p_init(void)
	671	{
	672	return pci_register_driver(&p54p_driver);
	673	}
	674
	675	static void __exit p54p_exit(void)
	676	{
	677	pci_unregister_driver(&p54p_driver);
	678	}
	679
	680	module_init(p54p_init);
	681	module_exit(p54p_exit);