[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / p54 / p54spi.c

/*
 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
 * Copyright 2008       Johannes Berg <johannes@sipsolutions.net>
 *
 * This driver is a port from stlc45xx:
 *	Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/etherdevice.h>
#include <linux/gpio.h>

#include "p54spi.h"
#include "p54spi_eeprom.h"
#include "p54.h"

#include "p54common.h"

MODULE_FIRMWARE("3826.arm");
MODULE_ALIAS("stlc45xx");

/*
 * gpios should be handled in board files and provided via platform data,
 * but because it's currently impossible for p54spi to have a header file
 * in include/linux, let's use module paramaters for now
 */

static int p54spi_gpio_power = 97;
module_param(p54spi_gpio_power, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");

static int p54spi_gpio_irq = 87;
module_param(p54spi_gpio_irq, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");

static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
			      void *buf, size_t len)
{
	struct spi_transfer t[2];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = len;
	spi_message_add_tail(&t[1], &m);

	spi_sync(priv->spi, &m);
}


static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
			     const void *buf, size_t len)
{
	struct spi_transfer t[3];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].tx_buf = buf;
	t[1].len = len;
	spi_message_add_tail(&t[1], &m);

	if (len % 2) {
		__le16 last_word;
		last_word = cpu_to_le16(((u8 *)buf)[len - 1]);

		t[2].tx_buf = &last_word;
		t[2].len = sizeof(last_word);
		spi_message_add_tail(&t[2], &m);
	}

	spi_sync(priv->spi, &m);
}

static u16 p54spi_read16(struct p54s_priv *priv, u8 addr)
{
	__le16 val;

	p54spi_spi_read(priv, addr, &val, sizeof(val));

	return le16_to_cpu(val);
}

static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
{
	__le32 val;

	p54spi_spi_read(priv, addr, &val, sizeof(val));

	return le32_to_cpu(val);
}

static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

struct p54spi_spi_reg {
	u16 address;		/* __le16 ? */
	u16 length;
	char *name;
};

static const struct p54spi_spi_reg p54spi_registers_array[] =
{
	{ SPI_ADRS_ARM_INTERRUPTS,	32, "ARM_INT     " },
	{ SPI_ADRS_ARM_INT_EN,		32, "ARM_INT_ENA " },
	{ SPI_ADRS_HOST_INTERRUPTS,	32, "HOST_INT    " },
	{ SPI_ADRS_HOST_INT_EN,		32, "HOST_INT_ENA" },
	{ SPI_ADRS_HOST_INT_ACK,	32, "HOST_INT_ACK" },
	{ SPI_ADRS_GEN_PURP_1,		32, "GP1_COMM    " },
	{ SPI_ADRS_GEN_PURP_2,		32, "GP2_COMM    " },
	{ SPI_ADRS_DEV_CTRL_STAT,	32, "DEV_CTRL_STA" },
	{ SPI_ADRS_DMA_DATA,		16, "DMA_DATA    " },
	{ SPI_ADRS_DMA_WRITE_CTRL,	16, "DMA_WR_CTRL " },
	{ SPI_ADRS_DMA_WRITE_LEN,	16, "DMA_WR_LEN  " },
	{ SPI_ADRS_DMA_WRITE_BASE,	32, "DMA_WR_BASE " },
	{ SPI_ADRS_DMA_READ_CTRL,	16, "DMA_RD_CTRL " },
	{ SPI_ADRS_DMA_READ_LEN,	16, "DMA_RD_LEN  " },
	{ SPI_ADRS_DMA_WRITE_BASE,	32, "DMA_RD_BASE " }
};

static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
{
	int i;

	for (i = 0; i < 2000; i++) {
		__le32 buffer = p54spi_read32(priv, reg);
		if ((buffer & bits) == bits)
			return 1;

		msleep(0);
	}
	return 0;
}

static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
				const void *buf, size_t len)
{
	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
		       cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));

	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
			     cpu_to_le32(HOST_ALLOWED))) {
		dev_err(&priv->spi->dev, "spi_write_dma not allowed "
			"to DMA write.\n");
		return -EAGAIN;
	}

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	return 0;
}

static int p54spi_request_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	int ret;

	/* FIXME: should driver use it's own struct device? */
	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);

	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
		return ret;
	}

	ret = p54_parse_firmware(dev, priv->firmware);
	if (ret) {
		release_firmware(priv->firmware);
		return ret;
	}

	return 0;
}

static int p54spi_request_eeprom(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	const struct firmware *eeprom;
	int ret;

	/*
	 * allow users to customize their eeprom.
	 */

	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	if (ret < 0) {
		dev_info(&priv->spi->dev, "loading default eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
				       sizeof(p54spi_eeprom));
	} else {
		dev_info(&priv->spi->dev, "loading user eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) eeprom->data,
				       (int)eeprom->size);
		release_firmware(eeprom);
	}
	return ret;
}

static int p54spi_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long fw_len, _fw_len;
	unsigned int offset = 0;
	int err = 0;
	u8 *fw;

	fw_len = priv->firmware->size;
	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	if (!fw)
		return -ENOMEM;

	/* stop the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	while (fw_len > 0) {
		_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);

		err = p54spi_spi_write_dma(priv, cpu_to_le32(
					   ISL38XX_DEV_FIRMWARE_ADDR + offset),
					   (fw + offset), _fw_len);
		if (err < 0)
			goto out;

		fw_len -= _fw_len;
		offset += _fw_len;
	}

	BUG_ON(fw_len != 0);

	/* enable host interrupts */
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
		       cpu_to_le32(SPI_HOST_INTS_DEFAULT));

	/* boot the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_RAM_BOOT));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
	msleep(TARGET_BOOT_SLEEP);

out:
	kfree(fw);
	return err;
}

static void p54spi_power_off(struct p54s_priv *priv)
{
	disable_irq(gpio_to_irq(p54spi_gpio_irq));
	gpio_set_value(p54spi_gpio_power, 0);
}

static void p54spi_power_on(struct p54s_priv *priv)
{
	gpio_set_value(p54spi_gpio_power, 1);
	enable_irq(gpio_to_irq(p54spi_gpio_irq));

	/*
	 * need to wait a while before device can be accessed, the lenght
	 * is just a guess
	 */
	msleep(10);
}

static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
}

static void p54spi_wakeup(struct p54s_priv *priv)
{
	/* wake the chip */
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_WAKEUP));

	/* And wait for the READY interrupt */
	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     cpu_to_le32(SPI_HOST_INT_READY))) {
		dev_err(&priv->spi->dev, "INT_READY timeout\n");
		goto out;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_READY);

out:
	return;
}

static inline void p54spi_sleep(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_SLEEP));
}

static void p54spi_int_ready(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
		       SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));

	switch (priv->fw_state) {
	case FW_STATE_BOOTING:
		priv->fw_state = FW_STATE_READY;
		complete(&priv->fw_comp);
		break;
	case FW_STATE_RESETTING:
		priv->fw_state = FW_STATE_READY;
		/* TODO: reinitialize state */
		break;
	default:
		break;
	}
}

static int p54spi_rx(struct p54s_priv *priv)
{
	struct sk_buff *skb;
	u16 len;

	p54spi_wakeup(priv);

	/* dummy read to flush SPI DMA controller bug */
	p54spi_read16(priv, SPI_ADRS_GEN_PURP_1);

	len = p54spi_read16(priv, SPI_ADRS_DMA_DATA);

	if (len == 0) {
		dev_err(&priv->spi->dev, "rx request of zero bytes");
		return 0;
	}


	/* Firmware may insert up to 4 padding bytes after the lmac header,
	 * but it does not amend the size of SPI data transfer.
	 * Such packets has correct data size in header, thus referencing
	 * past the end of allocated skb. Reserve extra 4 bytes for this case */
	skb = dev_alloc_skb(len + 4);
	if (!skb) {
		dev_err(&priv->spi->dev, "could not alloc skb");
		return 0;
	}

	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, skb_put(skb, len), len);
	p54spi_sleep(priv);
	/* Put additional bytes to compensate for the possible
	 * alignment-caused truncation */
	skb_put(skb, 4);

	if (p54_rx(priv->hw, skb) == 0)
		dev_kfree_skb(skb);

	return 0;
}


static irqreturn_t p54spi_interrupt(int irq, void *config)
{
	struct spi_device *spi = config;
	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);

	queue_work(priv->hw->workqueue, &priv->work);

	return IRQ_HANDLED;
}

static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
{
	struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
	int ret = 0;

	p54spi_wakeup(priv);

	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	if (ret < 0)
		goto out;

	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     cpu_to_le32(SPI_HOST_INT_WR_READY))) {
		dev_err(&priv->spi->dev, "WR_READY timeout\n");
		ret = -1;
		goto out;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
	p54spi_sleep(priv);

	if (FREE_AFTER_TX(skb))
		p54_free_skb(priv->hw, skb);
out:
	return ret;
}

static int p54spi_wq_tx(struct p54s_priv *priv)
{
	struct p54s_tx_info *entry;
	struct sk_buff *skb;
	struct ieee80211_tx_info *info;
	struct p54_tx_info *minfo;
	struct p54s_tx_info *dinfo;
	unsigned long flags;
	int ret = 0;

	spin_lock_irqsave(&priv->tx_lock, flags);

	while (!list_empty(&priv->tx_pending)) {
		entry = list_entry(priv->tx_pending.next,
				   struct p54s_tx_info, tx_list);

		list_del_init(&entry->tx_list);

		spin_unlock_irqrestore(&priv->tx_lock, flags);

		dinfo = container_of((void *) entry, struct p54s_tx_info,
				     tx_list);
		minfo = container_of((void *) dinfo, struct p54_tx_info,
				     data);
		info = container_of((void *) minfo, struct ieee80211_tx_info,
				    rate_driver_data);
		skb = container_of((void *) info, struct sk_buff, cb);

		ret = p54spi_tx_frame(priv, skb);

		if (ret < 0) {
			p54_free_skb(priv->hw, skb);
			return ret;
		}

		spin_lock_irqsave(&priv->tx_lock, flags);
	}
	spin_unlock_irqrestore(&priv->tx_lock, flags);
	return ret;
}

static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	struct p54s_priv *priv = dev->priv;
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
	struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
	unsigned long flags;

	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));

	spin_lock_irqsave(&priv->tx_lock, flags);
	list_add_tail(&di->tx_list, &priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	queue_work(priv->hw->workqueue, &priv->work);
}

static void p54spi_work(struct work_struct *work)
{
	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	u32 ints;
	int ret;

	mutex_lock(&priv->mutex);

	if (priv->fw_state == FW_STATE_OFF &&
	    priv->fw_state == FW_STATE_RESET)
		goto out;

	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);

	if (ints & SPI_HOST_INT_READY) {
		p54spi_int_ready(priv);
		p54spi_int_ack(priv, SPI_HOST_INT_READY);
	}

	if (priv->fw_state != FW_STATE_READY)
		goto out;

	if (ints & SPI_HOST_INT_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}
	if (ints & SPI_HOST_INT_SW_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}

	ret = p54spi_wq_tx(priv);
	if (ret < 0)
		goto out;

	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);

out:
	mutex_unlock(&priv->mutex);
}

static int p54spi_op_start(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long timeout;
	int ret = 0;

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		goto out;
	}

	priv->fw_state = FW_STATE_BOOTING;

	p54spi_power_on(priv);

	ret = p54spi_upload_firmware(dev);
	if (ret < 0) {
		p54spi_power_off(priv);
		goto out_unlock;
	}

	mutex_unlock(&priv->mutex);

	timeout = msecs_to_jiffies(2000);
	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
							    timeout);
	if (!timeout) {
		dev_err(&priv->spi->dev, "firmware boot failed");
		p54spi_power_off(priv);
		ret = -1;
		goto out;
	}

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		p54spi_power_off(priv);
		goto out;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

out_unlock:
	mutex_unlock(&priv->mutex);

out:
	return ret;
}

static void p54spi_op_stop(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long flags;

	if (mutex_lock_interruptible(&priv->mutex)) {
		/* FIXME: how to handle this error? */
		return;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

	cancel_work_sync(&priv->work);

	p54spi_power_off(priv);
	spin_lock_irqsave(&priv->tx_lock, flags);
	INIT_LIST_HEAD(&priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	priv->fw_state = FW_STATE_OFF;
	mutex_unlock(&priv->mutex);
}

static int __devinit p54spi_probe(struct spi_device *spi)
{
	struct p54s_priv *priv = NULL;
	struct ieee80211_hw *hw;
	int ret = -EINVAL;

	hw = p54_init_common(sizeof(*priv));
	if (!hw) {
		dev_err(&priv->spi->dev, "could not alloc ieee80211_hw");
		return -ENOMEM;
	}

	priv = hw->priv;
	priv->hw = hw;
	dev_set_drvdata(&spi->dev, priv);
	priv->spi = spi;

	spi->bits_per_word = 16;
	spi->max_speed_hz = 24000000;

	ret = spi_setup(spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "spi_setup failed");
		goto err_free_common;
	}

	ret = gpio_request(p54spi_gpio_power, "p54spi power");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
		goto err_free_common;
	}

	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
		goto err_free_common;
	}

	gpio_direction_output(p54spi_gpio_power, 0);
	gpio_direction_input(p54spi_gpio_irq);

	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
			  p54spi_interrupt, IRQF_DISABLED, "p54spi",
			  priv->spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_irq() failed");
		goto err_free_common;
	}

	set_irq_type(gpio_to_irq(p54spi_gpio_irq),
		     IRQ_TYPE_EDGE_RISING);

	disable_irq(gpio_to_irq(p54spi_gpio_irq));

	INIT_WORK(&priv->work, p54spi_work);
	init_completion(&priv->fw_comp);
	INIT_LIST_HEAD(&priv->tx_pending);
	mutex_init(&priv->mutex);
	SET_IEEE80211_DEV(hw, &spi->dev);
	priv->common.open = p54spi_op_start;
	priv->common.stop = p54spi_op_stop;
	priv->common.tx = p54spi_op_tx;

	ret = p54spi_request_firmware(hw);
	if (ret < 0)
		goto err_free_common;

	ret = p54spi_request_eeprom(hw);
	if (ret)
		goto err_free_common;

	ret = p54_register_common(hw, &priv->spi->dev);
	if (ret)
		goto err_free_common;

	return 0;

err_free_common:
	p54_free_common(priv->hw);
	return ret;
}

static int __devexit p54spi_remove(struct spi_device *spi)
{
	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);

	ieee80211_unregister_hw(priv->hw);

	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);

	gpio_free(p54spi_gpio_power);
	gpio_free(p54spi_gpio_irq);
	release_firmware(priv->firmware);

	mutex_destroy(&priv->mutex);

	p54_free_common(priv->hw);
	ieee80211_free_hw(priv->hw);

	return 0;
}


static struct spi_driver p54spi_driver = {
	.driver = {
		/* use cx3110x name because board-n800.c uses that for the
		 * SPI port */
		.name		= "cx3110x",
		.bus		= &spi_bus_type,
		.owner		= THIS_MODULE,
	},

	.probe		= p54spi_probe,
	.remove		= __devexit_p(p54spi_remove),
};

static int __init p54spi_init(void)
{
	int ret;

	ret = spi_register_driver(&p54spi_driver);
	if (ret < 0) {
		printk(KERN_ERR "failed to register SPI driver: %d", ret);
		goto out;
	}

out:
	return ret;
}

static void __exit p54spi_exit(void)
{
	spi_unregister_driver(&p54spi_driver);
}

module_init(p54spi_init);
module_exit(p54spi_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
Commit	Line	Data
cd8d3d32 CL	1	/*
	2	* Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
	3	* Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
	4	*
	5	* This driver is a port from stlc45xx:
	6	* Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/firmware.h>
	27	#include <linux/delay.h>
	28	#include <linux/irq.h>
	29	#include <linux/spi/spi.h>
	30	#include <linux/etherdevice.h>
	31	#include <linux/gpio.h>
	32
	33	#include "p54spi.h"
	34	#include "p54spi_eeprom.h"
	35	#include "p54.h"
	36
	37	#include "p54common.h"
	38
	39	MODULE_FIRMWARE("3826.arm");
	40	MODULE_ALIAS("stlc45xx");
	41
a2116993 CL	42	/*
	43	* gpios should be handled in board files and provided via platform data,
	44	* but because it's currently impossible for p54spi to have a header file
	45	* in include/linux, let's use module paramaters for now
	46	*/
	47
	48	static int p54spi_gpio_power = 97;
	49	module_param(p54spi_gpio_power, int, 0444);
	50	MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
	51
	52	static int p54spi_gpio_irq = 87;
	53	module_param(p54spi_gpio_irq, int, 0444);
	54	MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
	55
cd8d3d32 CL	56	static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
	57	void *buf, size_t len)
	58	{
	59	struct spi_transfer t[2];
	60	struct spi_message m;
	61	__le16 addr;
	62
	63	/* We first push the address */
	64	addr = cpu_to_le16(address << 8 \| SPI_ADRS_READ_BIT_15);
	65
	66	spi_message_init(&m);
	67	memset(t, 0, sizeof(t));
	68
	69	t[0].tx_buf = &addr;
	70	t[0].len = sizeof(addr);
	71	spi_message_add_tail(&t[0], &m);
	72
	73	t[1].rx_buf = buf;
	74	t[1].len = len;
	75	spi_message_add_tail(&t[1], &m);
	76
	77	spi_sync(priv->spi, &m);
	78	}
	79
	80
	81	static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
	82	const void *buf, size_t len)
	83	{
	84	struct spi_transfer t[3];
	85	struct spi_message m;
	86	__le16 addr;
	87
	88	/* We first push the address */
	89	addr = cpu_to_le16(address << 8);
	90
	91	spi_message_init(&m);
	92	memset(t, 0, sizeof(t));
	93
	94	t[0].tx_buf = &addr;
	95	t[0].len = sizeof(addr);
	96	spi_message_add_tail(&t[0], &m);
	97
	98	t[1].tx_buf = buf;
	99	t[1].len = len;
	100	spi_message_add_tail(&t[1], &m);
	101
	102	if (len % 2) {
	103	__le16 last_word;
	104	last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
	105
	106	t[2].tx_buf = &last_word;
	107	t[2].len = sizeof(last_word);
	108	spi_message_add_tail(&t[2], &m);
	109	}
	110
	111	spi_sync(priv->spi, &m);
	112	}
	113
	114	static u16 p54spi_read16(struct p54s_priv *priv, u8 addr)
	115	{
	116	__le16 val;
	117
	118	p54spi_spi_read(priv, addr, &val, sizeof(val));
	119
120	return le16_to_cpu(val);
121	}
122
123	static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
124	{
125	__le32 val;
126
127	p54spi_spi_read(priv, addr, &val, sizeof(val));
128
129	return le32_to_cpu(val);
130	}
131
132	static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
133	{
134	p54spi_spi_write(priv, addr, &val, sizeof(val));
135	}
136
137	static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
138	{
139	p54spi_spi_write(priv, addr, &val, sizeof(val));
140	}
141
142	struct p54spi_spi_reg {
143	u16 address; /* __le16 ? */
144	u16 length;
145	char *name;
146	};
147
148	static const struct p54spi_spi_reg p54spi_registers_array[] =
149	{
150	{ SPI_ADRS_ARM_INTERRUPTS, 32, "ARM_INT " },
151	{ SPI_ADRS_ARM_INT_EN, 32, "ARM_INT_ENA " },
152	{ SPI_ADRS_HOST_INTERRUPTS, 32, "HOST_INT " },
153	{ SPI_ADRS_HOST_INT_EN, 32, "HOST_INT_ENA" },
154	{ SPI_ADRS_HOST_INT_ACK, 32, "HOST_INT_ACK" },
155	{ SPI_ADRS_GEN_PURP_1, 32, "GP1_COMM " },
156	{ SPI_ADRS_GEN_PURP_2, 32, "GP2_COMM " },
157	{ SPI_ADRS_DEV_CTRL_STAT, 32, "DEV_CTRL_STA" },
158	{ SPI_ADRS_DMA_DATA, 16, "DMA_DATA " },
159	{ SPI_ADRS_DMA_WRITE_CTRL, 16, "DMA_WR_CTRL " },
160	{ SPI_ADRS_DMA_WRITE_LEN, 16, "DMA_WR_LEN " },
161	{ SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_WR_BASE " },
162	{ SPI_ADRS_DMA_READ_CTRL, 16, "DMA_RD_CTRL " },
163	{ SPI_ADRS_DMA_READ_LEN, 16, "DMA_RD_LEN " },
164	{ SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_RD_BASE " }
165	};
166
167	static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
168	{
169	int i;
cd8d3d32 CL	170
cd8d3d32 CL	171	for (i = 0; i < 2000; i++) {
87cbfd06	172	__le32 buffer = p54spi_read32(priv, reg);
f74d0f5c	173	if ((buffer & bits) == bits)
cd8d3d32 CL	174	return 1;
cd8d3d32 CL	175
87cbfd06	176	msleep(0);
cd8d3d32 CL	177	}
	178	return 0;
	179	}
	180
4f5cab96 MF	181	static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
	182	const void *buf, size_t len)
	183	{
	184	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
	185	cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
	186
87cbfd06 MF	187	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
87cbfd06 MF	188	cpu_to_le32(HOST_ALLOWED))) {
4f5cab96	189	dev_err(&priv->spi->dev, "spi_write_dma not allowed "
87cbfd06	190	"to DMA write.\n");
4f5cab96 MF	191	return -EAGAIN;
	192	}
	193
	194	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	195	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	196	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	197	return 0;
	198	}
	199
cd8d3d32 CL	200	static int p54spi_request_firmware(struct ieee80211_hw *dev)
	201	{
	202	struct p54s_priv *priv = dev->priv;
	203	int ret;
	204
	205	/* FIXME: should driver use it's own struct device? */
	206	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
	207
	208	if (ret < 0) {
	209	dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
	210	return ret;
	211	}
	212
	213	ret = p54_parse_firmware(dev, priv->firmware);
	214	if (ret) {
	215	release_firmware(priv->firmware);
	216	return ret;
	217	}
	218
	219	return 0;
	220	}
	221
	222	static int p54spi_request_eeprom(struct ieee80211_hw *dev)
	223	{
	224	struct p54s_priv *priv = dev->priv;
	225	const struct firmware *eeprom;
	226	int ret;
	227
	228	/*
	229	* allow users to customize their eeprom.
	230	*/
	231
	232	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	233	if (ret < 0) {
	234	dev_info(&priv->spi->dev, "loading default eeprom...\n");
	235	ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
	236	sizeof(p54spi_eeprom));
	237	} else {
	238	dev_info(&priv->spi->dev, "loading user eeprom...\n");
	239	ret = p54_parse_eeprom(dev, (void *) eeprom->data,
	240	(int)eeprom->size);
	241	release_firmware(eeprom);
	242	}
	243	return ret;
	244	}
	245
	246	static int p54spi_upload_firmware(struct ieee80211_hw *dev)
	247	{
	248	struct p54s_priv *priv = dev->priv;
5e3af1d2 MF	249	unsigned long fw_len, _fw_len;
	250	unsigned int offset = 0;
	251	int err = 0;
	252	u8 *fw;
	253
	254	fw_len = priv->firmware->size;
	255	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	256	if (!fw)
	257	return -ENOMEM;
cd8d3d32 CL	258
	259	/* stop the device */
	260	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	261	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	262	SPI_CTRL_STAT_START_HALTED));
	263
	264	msleep(TARGET_BOOT_SLEEP);
	265
	266	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	267	SPI_CTRL_STAT_HOST_OVERRIDE \|
	268	SPI_CTRL_STAT_START_HALTED));
	269
	270	msleep(TARGET_BOOT_SLEEP);
	271
cd8d3d32 CL	272	while (fw_len > 0) {
	273	_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
	274
4f5cab96 MF	275	err = p54spi_spi_write_dma(priv, cpu_to_le32(
	276	ISL38XX_DEV_FIRMWARE_ADDR + offset),
	277	(fw + offset), _fw_len);
	278	if (err < 0)
5e3af1d2	279	goto out;
cd8d3d32 CL	280
cd8d3d32 CL	281	fw_len -= _fw_len;
5e3af1d2	282	offset += _fw_len;
cd8d3d32 CL	283	}
	284
	285	BUG_ON(fw_len != 0);
	286
	287	/* enable host interrupts */
	288	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
	289	cpu_to_le32(SPI_HOST_INTS_DEFAULT));
	290
	291	/* boot the device */
	292	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	293	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	294	SPI_CTRL_STAT_RAM_BOOT));
	295
	296	msleep(TARGET_BOOT_SLEEP);
	297
	298	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	299	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_RAM_BOOT));
	300	msleep(TARGET_BOOT_SLEEP);
5e3af1d2 MF	301
	302	out:
	303	kfree(fw);
	304	return err;
cd8d3d32 CL	305	}
	306
	307	static void p54spi_power_off(struct p54s_priv *priv)
	308	{
a2116993 CL	309	disable_irq(gpio_to_irq(p54spi_gpio_irq));
a2116993 CL	310	gpio_set_value(p54spi_gpio_power, 0);
cd8d3d32 CL	311	}
	312
	313	static void p54spi_power_on(struct p54s_priv *priv)
	314	{
a2116993 CL	315	gpio_set_value(p54spi_gpio_power, 1);
a2116993 CL	316	enable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	317
	318	/*
	319	* need to wait a while before device can be accessed, the lenght
	320	* is just a guess
	321	*/
	322	msleep(10);
	323	}
	324
	325	static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
	326	{
	327	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
	328	}
	329
	330	static void p54spi_wakeup(struct p54s_priv *priv)
	331	{
cd8d3d32 CL	332	/* wake the chip */
	333	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	334	cpu_to_le32(SPI_TARGET_INT_WAKEUP));
	335
	336	/* And wait for the READY interrupt */
87cbfd06 MF	337	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
	338	cpu_to_le32(SPI_HOST_INT_READY))) {
	339	dev_err(&priv->spi->dev, "INT_READY timeout\n");
	340	goto out;
cd8d3d32 CL	341	}
	342
	343	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	344
	345	out:
	346	return;
	347	}
	348
	349	static inline void p54spi_sleep(struct p54s_priv *priv)
	350	{
	351	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	352	cpu_to_le32(SPI_TARGET_INT_SLEEP));
	353	}
	354
	355	static void p54spi_int_ready(struct p54s_priv *priv)
	356	{
	357	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
	358	SPI_HOST_INT_UPDATE \| SPI_HOST_INT_SW_UPDATE));
	359
	360	switch (priv->fw_state) {
	361	case FW_STATE_BOOTING:
	362	priv->fw_state = FW_STATE_READY;
	363	complete(&priv->fw_comp);
	364	break;
	365	case FW_STATE_RESETTING:
	366	priv->fw_state = FW_STATE_READY;
	367	/* TODO: reinitialize state */
	368	break;
	369	default:
	370	break;
	371	}
	372	}
	373
	374	static int p54spi_rx(struct p54s_priv *priv)
	375	{
	376	struct sk_buff *skb;
	377	u16 len;
	378
	379	p54spi_wakeup(priv);
	380
	381	/* dummy read to flush SPI DMA controller bug */
	382	p54spi_read16(priv, SPI_ADRS_GEN_PURP_1);
	383
	384	len = p54spi_read16(priv, SPI_ADRS_DMA_DATA);
	385
	386	if (len == 0) {
	387	dev_err(&priv->spi->dev, "rx request of zero bytes");
	388	return 0;
	389	}
	390
9f201a87 MF	391
	392	/* Firmware may insert up to 4 padding bytes after the lmac header,
	393	* but it does not amend the size of SPI data transfer.
	394	* Such packets has correct data size in header, thus referencing
	395	* past the end of allocated skb. Reserve extra 4 bytes for this case */
	396	skb = dev_alloc_skb(len + 4);
cd8d3d32 CL	397	if (!skb) {
	398	dev_err(&priv->spi->dev, "could not alloc skb");
	399	return 0;
	400	}
	401
	402	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, skb_put(skb, len), len);
	403	p54spi_sleep(priv);
9f201a87 MF	404	/* Put additional bytes to compensate for the possible
	405	* alignment-caused truncation */
	406	skb_put(skb, 4);
cd8d3d32 CL	407
	408	if (p54_rx(priv->hw, skb) == 0)
	409	dev_kfree_skb(skb);
	410
	411	return 0;
	412	}
	413
	414
	415	static irqreturn_t p54spi_interrupt(int irq, void *config)
	416	{
	417	struct spi_device *spi = config;
	418	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
	419
	420	queue_work(priv->hw->workqueue, &priv->work);
	421
	422	return IRQ_HANDLED;
	423	}
	424
	425	static int p54spi_tx_frame(struct p54s_priv priv, struct sk_buff skb)
	426	{
	427	struct p54_hdr hdr = (struct p54_hdr ) skb->data;
cd8d3d32	428	int ret = 0;
cd8d3d32 CL	429
	430	p54spi_wakeup(priv);
	431
4f5cab96 MF	432	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	433	if (ret < 0)
	434	goto out;
cd8d3d32	435
87cbfd06 MF	436	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
	437	cpu_to_le32(SPI_HOST_INT_WR_READY))) {
	438	dev_err(&priv->spi->dev, "WR_READY timeout\n");
	439	ret = -1;
	440	goto out;
cd8d3d32 CL	441	}
	442
	443	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
	444	p54spi_sleep(priv);
	445
cd8d3d32 CL	446	if (FREE_AFTER_TX(skb))
cd8d3d32 CL	447	p54_free_skb(priv->hw, skb);
4f5cab96	448	out:
cd8d3d32 CL	449	return ret;
	450	}
	451
	452	static int p54spi_wq_tx(struct p54s_priv *priv)
	453	{
	454	struct p54s_tx_info *entry;
	455	struct sk_buff *skb;
	456	struct ieee80211_tx_info *info;
	457	struct p54_tx_info *minfo;
	458	struct p54s_tx_info *dinfo;
731c6531	459	unsigned long flags;
cd8d3d32 CL	460	int ret = 0;
cd8d3d32 CL	461
731c6531	462	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32 CL	463
	464	while (!list_empty(&priv->tx_pending)) {
	465	entry = list_entry(priv->tx_pending.next,
	466	struct p54s_tx_info, tx_list);
	467
	468	list_del_init(&entry->tx_list);
	469
731c6531	470	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	471
	472	dinfo = container_of((void *) entry, struct p54s_tx_info,
	473	tx_list);
	474	minfo = container_of((void *) dinfo, struct p54_tx_info,
	475	data);
	476	info = container_of((void *) minfo, struct ieee80211_tx_info,
	477	rate_driver_data);
	478	skb = container_of((void *) info, struct sk_buff, cb);
	479
	480	ret = p54spi_tx_frame(priv, skb);
	481
cd8d3d32 CL	482	if (ret < 0) {
cd8d3d32 CL	483	p54_free_skb(priv->hw, skb);
731c6531	484	return ret;
cd8d3d32	485	}
cd8d3d32	486
731c6531 CL	487	spin_lock_irqsave(&priv->tx_lock, flags);
	488	}
	489	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	490	return ret;
	491	}
	492
	493	static void p54spi_op_tx(struct ieee80211_hw dev, struct sk_buff skb)
	494	{
	495	struct p54s_priv *priv = dev->priv;
	496	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	497	struct p54_tx_info mi = (struct p54_tx_info ) info->rate_driver_data;
	498	struct p54s_tx_info di = (struct p54s_tx_info ) mi->data;
731c6531	499	unsigned long flags;
cd8d3d32 CL	500
	501	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
	502
731c6531	503	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	504	list_add_tail(&di->tx_list, &priv->tx_pending);
731c6531	505	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	506
	507	queue_work(priv->hw->workqueue, &priv->work);
	508	}
	509
	510	static void p54spi_work(struct work_struct *work)
	511	{
	512	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	513	u32 ints;
	514	int ret;
	515
	516	mutex_lock(&priv->mutex);
	517
	518	if (priv->fw_state == FW_STATE_OFF &&
	519	priv->fw_state == FW_STATE_RESET)
	520	goto out;
	521
	522	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
	523
	524	if (ints & SPI_HOST_INT_READY) {
	525	p54spi_int_ready(priv);
	526	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	527	}
	528
	529	if (priv->fw_state != FW_STATE_READY)
	530	goto out;
	531
	532	if (ints & SPI_HOST_INT_UPDATE) {
	533	p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
	534	ret = p54spi_rx(priv);
	535	if (ret < 0)
	536	goto out;
	537	}
	538	if (ints & SPI_HOST_INT_SW_UPDATE) {
	539	p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
	540	ret = p54spi_rx(priv);
	541	if (ret < 0)
	542	goto out;
	543	}
	544
	545	ret = p54spi_wq_tx(priv);
	546	if (ret < 0)
	547	goto out;
	548
	549	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
	550
	551	out:
	552	mutex_unlock(&priv->mutex);
	553	}
	554
	555	static int p54spi_op_start(struct ieee80211_hw *dev)
	556	{
	557	struct p54s_priv *priv = dev->priv;
	558	unsigned long timeout;
	559	int ret = 0;
	560
	561	if (mutex_lock_interruptible(&priv->mutex)) {
	562	ret = -EINTR;
	563	goto out;
	564	}
	565
	566	priv->fw_state = FW_STATE_BOOTING;
	567
	568	p54spi_power_on(priv);
	569
570	ret = p54spi_upload_firmware(dev);
571	if (ret < 0) {
572	p54spi_power_off(priv);
573	goto out_unlock;
574	}
575
576	mutex_unlock(&priv->mutex);
577
578	timeout = msecs_to_jiffies(2000);
579	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
580	timeout);
581	if (!timeout) {
582	dev_err(&priv->spi->dev, "firmware boot failed");
583	p54spi_power_off(priv);
584	ret = -1;
585	goto out;
586	}
587
588	if (mutex_lock_interruptible(&priv->mutex)) {
589	ret = -EINTR;
590	p54spi_power_off(priv);
591	goto out;
592	}
593
594	WARN_ON(priv->fw_state != FW_STATE_READY);
595
596	out_unlock:
597	mutex_unlock(&priv->mutex);
598
599	out:
600	return ret;
601	}
602
603	static void p54spi_op_stop(struct ieee80211_hw *dev)
604	{
605	struct p54s_priv *priv = dev->priv;
731c6531	606	unsigned long flags;
cd8d3d32 CL	607
	608	if (mutex_lock_interruptible(&priv->mutex)) {
	609	/* FIXME: how to handle this error? */
	610	return;
	611	}
	612
	613	WARN_ON(priv->fw_state != FW_STATE_READY);
	614
	615	cancel_work_sync(&priv->work);
	616
	617	p54spi_power_off(priv);
731c6531	618	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	619	INIT_LIST_HEAD(&priv->tx_pending);
731c6531	620	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	621
	622	priv->fw_state = FW_STATE_OFF;
	623	mutex_unlock(&priv->mutex);
	624	}
	625
	626	static int __devinit p54spi_probe(struct spi_device *spi)
	627	{
	628	struct p54s_priv *priv = NULL;
	629	struct ieee80211_hw *hw;
	630	int ret = -EINVAL;
	631
	632	hw = p54_init_common(sizeof(*priv));
	633	if (!hw) {
	634	dev_err(&priv->spi->dev, "could not alloc ieee80211_hw");
	635	return -ENOMEM;
	636	}
	637
	638	priv = hw->priv;
	639	priv->hw = hw;
	640	dev_set_drvdata(&spi->dev, priv);
	641	priv->spi = spi;
	642
cd8d3d32 CL	643	spi->bits_per_word = 16;
	644	spi->max_speed_hz = 24000000;
	645
	646	ret = spi_setup(spi);
	647	if (ret < 0) {
	648	dev_err(&priv->spi->dev, "spi_setup failed");
	649	goto err_free_common;
	650	}
	651
a2116993	652	ret = gpio_request(p54spi_gpio_power, "p54spi power");
cd8d3d32 CL	653	if (ret < 0) {
	654	dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
	655	goto err_free_common;
	656	}
	657
a2116993	658	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
cd8d3d32 CL	659	if (ret < 0) {
	660	dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
	661	goto err_free_common;
	662	}
	663
a2116993 CL	664	gpio_direction_output(p54spi_gpio_power, 0);
a2116993 CL	665	gpio_direction_input(p54spi_gpio_irq);
cd8d3d32	666
a2116993	667	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
cd8d3d32 CL	668	p54spi_interrupt, IRQF_DISABLED, "p54spi",
	669	priv->spi);
	670	if (ret < 0) {
	671	dev_err(&priv->spi->dev, "request_irq() failed");
	672	goto err_free_common;
	673	}
	674
a2116993	675	set_irq_type(gpio_to_irq(p54spi_gpio_irq),
cd8d3d32 CL	676	IRQ_TYPE_EDGE_RISING);
cd8d3d32 CL	677
a2116993	678	disable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	679
	680	INIT_WORK(&priv->work, p54spi_work);
	681	init_completion(&priv->fw_comp);
	682	INIT_LIST_HEAD(&priv->tx_pending);
	683	mutex_init(&priv->mutex);
	684	SET_IEEE80211_DEV(hw, &spi->dev);
	685	priv->common.open = p54spi_op_start;
	686	priv->common.stop = p54spi_op_stop;
	687	priv->common.tx = p54spi_op_tx;
	688
	689	ret = p54spi_request_firmware(hw);
	690	if (ret < 0)
	691	goto err_free_common;
	692
	693	ret = p54spi_request_eeprom(hw);
	694	if (ret)
	695	goto err_free_common;
	696
2ac71072 CL	697	ret = p54_register_common(hw, &priv->spi->dev);
2ac71072 CL	698	if (ret)
cd8d3d32	699	goto err_free_common;
cd8d3d32	700
cd8d3d32 CL	701	return 0;
	702
	703	err_free_common:
	704	p54_free_common(priv->hw);
	705	return ret;
	706	}
	707
	708	static int __devexit p54spi_remove(struct spi_device *spi)
	709	{
	710	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
	711
	712	ieee80211_unregister_hw(priv->hw);
	713
a2116993	714	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
cd8d3d32	715
a2116993 CL	716	gpio_free(p54spi_gpio_power);
a2116993 CL	717	gpio_free(p54spi_gpio_irq);
cd8d3d32 CL	718	release_firmware(priv->firmware);
	719
	720	mutex_destroy(&priv->mutex);
	721
	722	p54_free_common(priv->hw);
	723	ieee80211_free_hw(priv->hw);
	724
	725	return 0;
	726	}
	727
	728
	729	static struct spi_driver p54spi_driver = {
	730	.driver = {
	731	/* use cx3110x name because board-n800.c uses that for the
	732	* SPI port */
	733	.name = "cx3110x",
	734	.bus = &spi_bus_type,
	735	.owner = THIS_MODULE,
	736	},
	737
	738	.probe = p54spi_probe,
	739	.remove = __devexit_p(p54spi_remove),
	740	};
	741
	742	static int __init p54spi_init(void)
	743	{
	744	int ret;
	745
	746	ret = spi_register_driver(&p54spi_driver);
	747	if (ret < 0) {
	748	printk(KERN_ERR "failed to register SPI driver: %d", ret);
	749	goto out;
	750	}
	751
	752	out:
	753	return ret;
	754	}
	755
	756	static void __exit p54spi_exit(void)
	757	{
	758	spi_unregister_driver(&p54spi_driver);
	759	}
	760
	761	module_init(p54spi_init);
	762	module_exit(p54spi_exit);
	763
	764	MODULE_LICENSE("GPL");
	765	MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");