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mac80211: give burst time in txop rather than 0.1msec units
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / p54common.c
CommitLineData
eff1a59c
MW		 1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
8318d78a
JB		 30static struct ieee80211_rate p54_rates[] = {
31 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
32 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
33 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
34 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
35 { .bitrate = 60, .hw_value = 4, },
36 { .bitrate = 90, .hw_value = 5, },
37 { .bitrate = 120, .hw_value = 6, },
38 { .bitrate = 180, .hw_value = 7, },
39 { .bitrate = 240, .hw_value = 8, },
40 { .bitrate = 360, .hw_value = 9, },
41 { .bitrate = 480, .hw_value = 10, },
42 { .bitrate = 540, .hw_value = 11, },
43};
44
45static struct ieee80211_channel p54_channels[] = {
46 { .center_freq = 2412, .hw_value = 1, },
47 { .center_freq = 2417, .hw_value = 2, },
48 { .center_freq = 2422, .hw_value = 3, },
49 { .center_freq = 2427, .hw_value = 4, },
50 { .center_freq = 2432, .hw_value = 5, },
51 { .center_freq = 2437, .hw_value = 6, },
52 { .center_freq = 2442, .hw_value = 7, },
53 { .center_freq = 2447, .hw_value = 8, },
54 { .center_freq = 2452, .hw_value = 9, },
55 { .center_freq = 2457, .hw_value = 10, },
56 { .center_freq = 2462, .hw_value = 11, },
57 { .center_freq = 2467, .hw_value = 12, },
58 { .center_freq = 2472, .hw_value = 13, },
59 { .center_freq = 2484, .hw_value = 14, },
60};
61
62struct ieee80211_supported_band band_2GHz = {
63 .channels = p54_channels,
64 .n_channels = ARRAY_SIZE(p54_channels),
65 .bitrates = p54_rates,
66 .n_bitrates = ARRAY_SIZE(p54_rates),
67};
68
69
eff1a59c
MW		 70void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
71{
72 struct p54_common *priv = dev->priv;
73 struct bootrec_exp_if *exp_if;
74 struct bootrec *bootrec;
75 u32 *data = (u32 *)fw->data;
76 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
77 u8 *fw_version = NULL;
78 size_t len;
79 int i;
80
81 if (priv->rx_start)
82 return;
83
84 while (data < end_data && *data)
85 data++;
86
87 while (data < end_data && !*data)
88 data++;
89
90 bootrec = (struct bootrec *) data;
91
92 while (bootrec->data <= end_data &&
93 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
94 u32 code = le32_to_cpu(bootrec->code);
95 switch (code) {
96 case BR_CODE_COMPONENT_ID:
dc73c623 97 switch (be32_to_cpu(*(__be32 *)bootrec->data)) {
eff1a59c
MW		 98 case FW_FMAC:
99 printk(KERN_INFO "p54: FreeMAC firmware\n");
100 break;
101 case FW_LM20:
102 printk(KERN_INFO "p54: LM20 firmware\n");
103 break;
104 case FW_LM86:
105 printk(KERN_INFO "p54: LM86 firmware\n");
106 break;
107 case FW_LM87:
108 printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n");
109 break;
110 default:
111 printk(KERN_INFO "p54: unknown firmware\n");
112 break;
113 }
114 break;
115 case BR_CODE_COMPONENT_VERSION:
116 /* 24 bytes should be enough for all firmwares */
117 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
118 fw_version = (unsigned char*)bootrec->data;
119 break;
120 case BR_CODE_DESCR:
dc73c623 121 priv->rx_start = le32_to_cpu(((__le32 *)bootrec->data)[1]);
eff1a59c 122 /* FIXME add sanity checking */
dc73c623 123 priv->rx_end = le32_to_cpu(((__le32 *)bootrec->data)[2]) - 0x3500;
eff1a59c
MW		 124 break;
125 case BR_CODE_EXPOSED_IF:
126 exp_if = (struct bootrec_exp_if *) bootrec->data;
127 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 128 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 129 priv->fw_var = le16_to_cpu(exp_if[i].variant);
130 break;
131 case BR_CODE_DEPENDENT_IF:
132 break;
133 case BR_CODE_END_OF_BRA:
134 case LEGACY_BR_CODE_END_OF_BRA:
135 end_data = NULL;
136 break;
137 default:
138 break;
139 }
140 bootrec = (struct bootrec *)&bootrec->data[len];
141 }
142
143 if (fw_version)
144 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
145 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
146
147 if (priv->fw_var >= 0x300) {
148 /* Firmware supports QoS, use it! */
149 priv->tx_stats.data[0].limit = 3;
150 priv->tx_stats.data[1].limit = 4;
151 priv->tx_stats.data[2].limit = 3;
152 priv->tx_stats.data[3].limit = 1;
153 dev->queues = 4;
154 }
155}
156EXPORT_SYMBOL_GPL(p54_parse_firmware);
157
158static int p54_convert_rev0_to_rev1(struct ieee80211_hw *dev,
159 struct pda_pa_curve_data *curve_data)
160{
161 struct p54_common *priv = dev->priv;
162 struct pda_pa_curve_data_sample_rev1 *rev1;
163 struct pda_pa_curve_data_sample_rev0 *rev0;
164 size_t cd_len = sizeof(*curve_data) +
165 (curve_data->points_per_channel*sizeof(*rev1) + 2) *
166 curve_data->channels;
167 unsigned int i, j;
168 void *source, *target;
169
170 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
171 if (!priv->curve_data)
172 return -ENOMEM;
173
174 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
175 source = curve_data->data;
176 target = priv->curve_data->data;
177 for (i = 0; i < curve_data->channels; i++) {
178 __le16 *freq = source;
179 source += sizeof(__le16);
180 *((__le16 *)target) = *freq;
181 target += sizeof(__le16);
182 for (j = 0; j < curve_data->points_per_channel; j++) {
183 rev1 = target;
184 rev0 = source;
185
186 rev1->rf_power = rev0->rf_power;
187 rev1->pa_detector = rev0->pa_detector;
188 rev1->data_64qam = rev0->pcv;
189 /* "invent" the points for the other modulations */
190#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
191 rev1->data_16qam = SUB(rev0->pcv, 12);
192 rev1->data_qpsk = SUB(rev1->data_16qam, 12);
193 rev1->data_bpsk = SUB(rev1->data_qpsk, 12);
194 rev1->data_barker= SUB(rev1->data_bpsk, 14);
195#undef SUB
196 target += sizeof(*rev1);
197 source += sizeof(*rev0);
198 }
199 }
200
201 return 0;
202}
203
204int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
205{
206 struct p54_common *priv = dev->priv;
207 struct eeprom_pda_wrap *wrap = NULL;
208 struct pda_entry *entry;
209 int i = 0;
210 unsigned int data_len, entry_len;
211 void *tmp;
212 int err;
213
214 wrap = (struct eeprom_pda_wrap *) eeprom;
215 entry = (void *)wrap->data + wrap->len;
216 i += 2;
217 i += le16_to_cpu(entry->len)*2;
218 while (i < len) {
219 entry_len = le16_to_cpu(entry->len);
220 data_len = ((entry_len - 1) << 1);
221 switch (le16_to_cpu(entry->code)) {
222 case PDR_MAC_ADDRESS:
223 SET_IEEE80211_PERM_ADDR(dev, entry->data);
224 break;
225 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
226 if (data_len < 2) {
227 err = -EINVAL;
228 goto err;
229 }
230
231 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
232 err = -EINVAL;
233 goto err;
234 }
235
236 priv->output_limit = kmalloc(entry->data[1] *
237 sizeof(*priv->output_limit), GFP_KERNEL);
238
239 if (!priv->output_limit) {
240 err = -ENOMEM;
241 goto err;
242 }
243
244 memcpy(priv->output_limit, &entry->data[2],
245 entry->data[1]*sizeof(*priv->output_limit));
246 priv->output_limit_len = entry->data[1];
247 break;
248 case PDR_PRISM_PA_CAL_CURVE_DATA:
249 if (data_len < sizeof(struct pda_pa_curve_data)) {
250 err = -EINVAL;
251 goto err;
252 }
253
254 if (((struct pda_pa_curve_data *)entry->data)->cal_method_rev) {
255 priv->curve_data = kmalloc(data_len, GFP_KERNEL);
256 if (!priv->curve_data) {
257 err = -ENOMEM;
258 goto err;
259 }
260
261 memcpy(priv->curve_data, entry->data, data_len);
262 } else {
263 err = p54_convert_rev0_to_rev1(dev, (struct pda_pa_curve_data *)entry->data);
264 if (err)
265 goto err;
266 }
267
268 break;
269 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
270 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
271 if (!priv->iq_autocal) {
272 err = -ENOMEM;
273 goto err;
274 }
275
276 memcpy(priv->iq_autocal, entry->data, data_len);
277 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
278 break;
279 case PDR_INTERFACE_LIST:
280 tmp = entry->data;
281 while ((u8 *)tmp < entry->data + data_len) {
282 struct bootrec_exp_if *exp_if = tmp;
283 if (le16_to_cpu(exp_if->if_id) == 0xF)
284 priv->rxhw = exp_if->variant & cpu_to_le16(0x07);
285 tmp += sizeof(struct bootrec_exp_if);
286 }
287 break;
288 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
289 priv->version = *(u8 *)(entry->data + 1);
290 break;
291 case PDR_END:
292 i = len;
293 break;
294 }
295
296 entry = (void *)entry + (entry_len + 1)*2;
297 i += 2;
298 i += entry_len*2;
299 }
300
301 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
302 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
303 err = -EINVAL;
304 goto err;
305 }
306
307 return 0;
308
309 err:
310 if (priv->iq_autocal) {
311 kfree(priv->iq_autocal);
312 priv->iq_autocal = NULL;
313 }
314
315 if (priv->output_limit) {
316 kfree(priv->output_limit);
317 priv->output_limit = NULL;
318 }
319
320 if (priv->curve_data) {
321 kfree(priv->curve_data);
322 priv->curve_data = NULL;
323 }
324
325 printk(KERN_ERR "p54: eeprom parse failed!\n");
326 return err;
327}
328EXPORT_SYMBOL_GPL(p54_parse_eeprom);
329
330void p54_fill_eeprom_readback(struct p54_control_hdr *hdr)
331{
332 struct p54_eeprom_lm86 *eeprom_hdr;
333
334 hdr->magic1 = cpu_to_le16(0x8000);
335 hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000);
336 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
337 hdr->retry1 = hdr->retry2 = 0;
338 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
339 eeprom_hdr->offset = 0x0;
340 eeprom_hdr->len = cpu_to_le16(0x2000);
341}
342EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback);
343
344static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
345{
346 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
347 struct ieee80211_rx_status rx_status = {0};
348 u16 freq = le16_to_cpu(hdr->freq);
349
350 rx_status.ssi = hdr->rssi;
8318d78a
JB		 351 /* XX correct? */
352 rx_status.rate_idx = hdr->rate & 0xf;
eff1a59c 353 rx_status.freq = freq;
8318d78a 354 rx_status.band = IEEE80211_BAND_2GHZ;
eff1a59c
MW		 355 rx_status.antenna = hdr->antenna;
356 rx_status.mactime = le64_to_cpu(hdr->timestamp);
03bffc13 357 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c
MW		 358
359 skb_pull(skb, sizeof(*hdr));
360 skb_trim(skb, le16_to_cpu(hdr->len));
361
362 ieee80211_rx_irqsafe(dev, skb, &rx_status);
363}
364
365static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
366{
367 struct p54_common *priv = dev->priv;
368 int i;
369
370 /* ieee80211_start_queues is great if all queues are really empty.
371 * But, what if some are full? */
372
373 for (i = 0; i < dev->queues; i++)
374 if (priv->tx_stats.data[i].len < priv->tx_stats.data[i].limit)
375 ieee80211_wake_queue(dev, i);
376}
377
378static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
379{
380 struct p54_common *priv = dev->priv;
381 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
382 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
383 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
384 u32 addr = le32_to_cpu(hdr->req_id) - 0x70;
385 struct memrecord *range = NULL;
386 u32 freed = 0;
387 u32 last_addr = priv->rx_start;
388
389 while (entry != (struct sk_buff *)&priv->tx_queue) {
390 range = (struct memrecord *)&entry->cb;
391 if (range->start_addr == addr) {
392 struct ieee80211_tx_status status = {{0}};
393 struct p54_control_hdr *entry_hdr;
394 struct p54_tx_control_allocdata *entry_data;
395 int pad = 0;
396
397 if (entry->next != (struct sk_buff *)&priv->tx_queue)
398 freed = ((struct memrecord *)&entry->next->cb)->start_addr - last_addr;
399 else
400 freed = priv->rx_end - last_addr;
401
402 last_addr = range->end_addr;
403 __skb_unlink(entry, &priv->tx_queue);
404 if (!range->control) {
405 kfree_skb(entry);
406 break;
407 }
408 memcpy(&status.control, range->control,
409 sizeof(status.control));
410 kfree(range->control);
411 priv->tx_stats.data[status.control.queue].len--;
412
413 entry_hdr = (struct p54_control_hdr *) entry->data;
414 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
415 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
416 pad = entry_data->align[0];
417
f59d9782 418 if (!(status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
eff1a59c
MW		 419 if (!(payload->status & 0x01))
420 status.flags |= IEEE80211_TX_STATUS_ACK;
421 else
422 status.excessive_retries = 1;
423 }
424 status.retry_count = payload->retries - 1;
425 status.ack_signal = le16_to_cpu(payload->ack_rssi);
426 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
427 ieee80211_tx_status_irqsafe(dev, entry, &status);
428 break;
429 } else
430 last_addr = range->end_addr;
431 entry = entry->next;
432 }
433
434 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
435 sizeof(struct p54_control_hdr))
436 p54_wake_free_queues(dev);
437}
438
439static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
440{
441 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
442
443 switch (le16_to_cpu(hdr->type)) {
444 case P54_CONTROL_TYPE_TXDONE:
445 p54_rx_frame_sent(dev, skb);
446 break;
447 case P54_CONTROL_TYPE_BBP:
448 break;
449 default:
450 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
451 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
452 break;
453 }
454}
455
456/* returns zero if skb can be reused */
457int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
458{
459 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
460 switch (type) {
461 case 0x00:
462 case 0x01:
463 p54_rx_data(dev, skb);
464 return -1;
465 case 0x4d:
466 /* TODO: do something better... but then again, I've never seen this happen */
467 printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n",
468 wiphy_name(dev->wiphy));
469 break;
470 case 0x80:
471 p54_rx_control(dev, skb);
472 break;
473 default:
474 printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n",
475 wiphy_name(dev->wiphy), type);
476 break;
477 }
478 return 0;
479}
480EXPORT_SYMBOL_GPL(p54_rx);
481
482/*
483 * So, the firmware is somewhat stupid and doesn't know what places in its
484 * memory incoming data should go to. By poking around in the firmware, we
485 * can find some unused memory to upload our packets to. However, data that we
486 * want the card to TX needs to stay intact until the card has told us that
487 * it is done with it. This function finds empty places we can upload to and
488 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
489 * allocated areas.
490 */
491static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
492 struct p54_control_hdr *data, u32 len,
493 struct ieee80211_tx_control *control)
494{
495 struct p54_common *priv = dev->priv;
496 struct sk_buff *entry = priv->tx_queue.next;
497 struct sk_buff *target_skb = NULL;
498 struct memrecord *range;
499 u32 last_addr = priv->rx_start;
500 u32 largest_hole = 0;
501 u32 target_addr = priv->rx_start;
502 unsigned long flags;
503 unsigned int left;
504 len = (len + 0x170 + 3) & ~0x3; /* 0x70 headroom, 0x100 tailroom */
505
506 spin_lock_irqsave(&priv->tx_queue.lock, flags);
507 left = skb_queue_len(&priv->tx_queue);
508 while (left--) {
509 u32 hole_size;
510 range = (struct memrecord *)&entry->cb;
511 hole_size = range->start_addr - last_addr;
512 if (!target_skb && hole_size >= len) {
513 target_skb = entry->prev;
514 hole_size -= len;
515 target_addr = last_addr;
516 }
517 largest_hole = max(largest_hole, hole_size);
518 last_addr = range->end_addr;
519 entry = entry->next;
520 }
521 if (!target_skb && priv->rx_end - last_addr >= len) {
522 target_skb = priv->tx_queue.prev;
523 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
524 if (!skb_queue_empty(&priv->tx_queue)) {
525 range = (struct memrecord *)&target_skb->cb;
526 target_addr = range->end_addr;
527 }
528 } else
529 largest_hole = max(largest_hole, priv->rx_end - last_addr);
530
531 if (skb) {
532 range = (struct memrecord *)&skb->cb;
533 range->start_addr = target_addr;
534 range->end_addr = target_addr + len;
535 range->control = control;
536 __skb_queue_after(&priv->tx_queue, target_skb, skb);
537 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
538 sizeof(struct p54_control_hdr))
539 ieee80211_stop_queues(dev);
540 }
541 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
542
543 data->req_id = cpu_to_le32(target_addr + 0x70);
544}
545
546static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
547 struct ieee80211_tx_control *control)
548{
549 struct ieee80211_tx_queue_stats_data *current_queue;
550 struct p54_common *priv = dev->priv;
551 struct p54_control_hdr *hdr;
552 struct p54_tx_control_allocdata *txhdr;
553 struct ieee80211_tx_control *control_copy;
554 size_t padding, len;
555 u8 rate;
556
557 current_queue = &priv->tx_stats.data[control->queue];
558 if (unlikely(current_queue->len > current_queue->limit))
559 return NETDEV_TX_BUSY;
560 current_queue->len++;
561 current_queue->count++;
562 if (current_queue->len == current_queue->limit)
563 ieee80211_stop_queue(dev, control->queue);
564
565 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
566 len = skb->len;
567
568 control_copy = kmalloc(sizeof(*control), GFP_ATOMIC);
569 if (control_copy)
570 memcpy(control_copy, control, sizeof(*control));
571
572 txhdr = (struct p54_tx_control_allocdata *)
573 skb_push(skb, sizeof(*txhdr) + padding);
574 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
575
576 if (padding)
577 hdr->magic1 = cpu_to_le16(0x4010);
578 else
579 hdr->magic1 = cpu_to_le16(0x0010);
580 hdr->len = cpu_to_le16(len);
581 hdr->type = (control->flags & IEEE80211_TXCTL_NO_ACK) ? 0 : cpu_to_le16(1);
582 hdr->retry1 = hdr->retry2 = control->retry_limit;
583 p54_assign_address(dev, skb, hdr, skb->len, control_copy);
584
585 memset(txhdr->wep_key, 0x0, 16);
586 txhdr->padding = 0;
587 txhdr->padding2 = 0;
588
589 /* TODO: add support for alternate retry TX rates */
8318d78a
JB		 590 rate = control->tx_rate->hw_value;
591 if (control->flags & IEEE80211_TXCTL_SHORT_PREAMBLE)
592 rate |= 0x10;
eff1a59c
MW		 593 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
594 rate |= 0x40;
595 else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
596 rate |= 0x20;
597 memset(txhdr->rateset, rate, 8);
598 txhdr->wep_key_present = 0;
599 txhdr->wep_key_len = 0;
600 txhdr->frame_type = cpu_to_le32(control->queue + 4);
601 txhdr->magic4 = 0;
602 txhdr->antenna = (control->antenna_sel_tx == 0) ?
603 2 : control->antenna_sel_tx - 1;
604 txhdr->output_power = 0x7f; // HW Maximum
605 txhdr->magic5 = (control->flags & IEEE80211_TXCTL_NO_ACK) ?
606 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23));
607 if (padding)
608 txhdr->align[0] = padding;
609
610 priv->tx(dev, hdr, skb->len, 0);
611 return 0;
612}
613
614static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
615 const u8 *dst, const u8 *src, u8 antenna,
616 u32 magic3, u32 magic8, u32 magic9)
617{
618 struct p54_common *priv = dev->priv;
619 struct p54_control_hdr *hdr;
620 struct p54_tx_control_filter *filter;
621
622 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
ba8007ce 623 priv->tx_hdr_len, GFP_ATOMIC);
eff1a59c
MW		 624 if (!hdr)
625 return -ENOMEM;
626
627 hdr = (void *)hdr + priv->tx_hdr_len;
628
629 filter = (struct p54_tx_control_filter *) hdr->data;
630 hdr->magic1 = cpu_to_le16(0x8001);
631 hdr->len = cpu_to_le16(sizeof(*filter));
632 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter), NULL);
633 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
634
635 filter->filter_type = cpu_to_le16(filter_type);
636 memcpy(filter->dst, dst, ETH_ALEN);
637 if (!src)
638 memset(filter->src, ~0, ETH_ALEN);
639 else
640 memcpy(filter->src, src, ETH_ALEN);
641 filter->antenna = antenna;
642 filter->magic3 = cpu_to_le32(magic3);
643 filter->rx_addr = cpu_to_le32(priv->rx_end);
644 filter->max_rx = cpu_to_le16(0x0620); /* FIXME: for usb ver 1.. maybe */
645 filter->rxhw = priv->rxhw;
646 filter->magic8 = cpu_to_le16(magic8);
647 filter->magic9 = cpu_to_le16(magic9);
648
649 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1);
650 return 0;
651}
652
653static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
654{
655 struct p54_common *priv = dev->priv;
656 struct p54_control_hdr *hdr;
657 struct p54_tx_control_channel *chan;
658 unsigned int i;
659 size_t payload_len = sizeof(*chan) + sizeof(u32)*2 +
660 sizeof(*chan->curve_data) *
661 priv->curve_data->points_per_channel;
662 void *entry;
663
664 hdr = kzalloc(sizeof(*hdr) + payload_len +
665 priv->tx_hdr_len, GFP_KERNEL);
666 if (!hdr)
667 return -ENOMEM;
668
669 hdr = (void *)hdr + priv->tx_hdr_len;
670
671 chan = (struct p54_tx_control_channel *) hdr->data;
672
673 hdr->magic1 = cpu_to_le16(0x8001);
674 hdr->len = cpu_to_le16(sizeof(*chan));
675 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
676 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len, NULL);
677
678 chan->magic1 = cpu_to_le16(0x1);
679 chan->magic2 = cpu_to_le16(0x0);
680
681 for (i = 0; i < priv->iq_autocal_len; i++) {
682 if (priv->iq_autocal[i].freq != freq)
683 continue;
684
685 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
686 sizeof(*priv->iq_autocal));
687 break;
688 }
689 if (i == priv->iq_autocal_len)
690 goto err;
691
692 for (i = 0; i < priv->output_limit_len; i++) {
693 if (priv->output_limit[i].freq != freq)
694 continue;
695
696 chan->val_barker = 0x38;
697 chan->val_bpsk = priv->output_limit[i].val_bpsk;
698 chan->val_qpsk = priv->output_limit[i].val_qpsk;
699 chan->val_16qam = priv->output_limit[i].val_16qam;
700 chan->val_64qam = priv->output_limit[i].val_64qam;
701 break;
702 }
703 if (i == priv->output_limit_len)
704 goto err;
705
706 chan->pa_points_per_curve = priv->curve_data->points_per_channel;
707
708 entry = priv->curve_data->data;
709 for (i = 0; i < priv->curve_data->channels; i++) {
710 if (*((__le16 *)entry) != freq) {
711 entry += sizeof(__le16);
712 entry += sizeof(struct pda_pa_curve_data_sample_rev1) *
713 chan->pa_points_per_curve;
714 continue;
715 }
716
717 entry += sizeof(__le16);
718 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
719 chan->pa_points_per_curve);
720 break;
721 }
722
723 memcpy(hdr->data + payload_len - 4, &chan->val_bpsk, 4);
724
725 priv->tx(dev, hdr, sizeof(*hdr) + payload_len, 1);
726 return 0;
727
728 err:
729 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
730 kfree(hdr);
731 return -EINVAL;
732}
733
734static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
735{
736 struct p54_common *priv = dev->priv;
737 struct p54_control_hdr *hdr;
738 struct p54_tx_control_led *led;
739
740 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
741 priv->tx_hdr_len, GFP_KERNEL);
742 if (!hdr)
743 return -ENOMEM;
744
745 hdr = (void *)hdr + priv->tx_hdr_len;
746 hdr->magic1 = cpu_to_le16(0x8001);
747 hdr->len = cpu_to_le16(sizeof(*led));
748 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
749 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led), NULL);
750
751 led = (struct p54_tx_control_led *) hdr->data;
752 led->mode = cpu_to_le16(mode);
753 led->led_permanent = cpu_to_le16(link);
754 led->led_temporary = cpu_to_le16(act);
755 led->duration = cpu_to_le16(1000);
756
757 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
758
759 return 0;
760}
761
3330d7be 762#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 763do { \
764 queue.aifs = cpu_to_le16(ai_fs); \
765 queue.cwmin = cpu_to_le16(cw_min); \
766 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 767 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 768} while(0)
769
770static void p54_init_vdcf(struct ieee80211_hw *dev)
771{
772 struct p54_common *priv = dev->priv;
773 struct p54_control_hdr *hdr;
774 struct p54_tx_control_vdcf *vdcf;
775
776 /* all USB V1 adapters need a extra headroom */
777 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
778 hdr->magic1 = cpu_to_le16(0x8001);
779 hdr->len = cpu_to_le16(sizeof(*vdcf));
780 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
781 hdr->req_id = cpu_to_le32(priv->rx_start);
782
783 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
784
3330d7be
JB		 785 /*
786 * FIXME: The default values in the spec (IEEE 802.11
787 * 7.3.2.19 Table 37) are 47, 94, 0, 0, why use
788 * 47, 94, 63, 0 here? Also, the default AIFS
789 * values (second parameter) are 2, 2, 3, 7...
790 */
791 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47);
792 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94);
793 P54_SET_QUEUE(vdcf->queue[2], 0x0002, 0x000f, 0x03ff, 63);
794 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0);
eff1a59c
MW		 795}
796
797static void p54_set_vdcf(struct ieee80211_hw *dev)
798{
799 struct p54_common *priv = dev->priv;
800 struct p54_control_hdr *hdr;
801 struct p54_tx_control_vdcf *vdcf;
802
803 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
804
805 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf), NULL);
806
807 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
808
809 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
810 vdcf->slottime = 9;
811 vdcf->magic1 = 0x00;
812 vdcf->magic2 = 0x10;
813 } else {
814 vdcf->slottime = 20;
815 vdcf->magic1 = 0x0a;
816 vdcf->magic2 = 0x06;
817 }
818
819 /* (see prism54/isl_oid.h for further details) */
820 vdcf->frameburst = cpu_to_le16(0);
821
822 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
823}
824
4150c572
JB		 825static int p54_start(struct ieee80211_hw *dev)
826{
827 struct p54_common *priv = dev->priv;
828 int err;
829
830 err = priv->open(dev);
831 if (!err)
832 priv->mode = IEEE80211_IF_TYPE_MNTR;
833
834 return err;
835}
836
837static void p54_stop(struct ieee80211_hw *dev)
838{
839 struct p54_common *priv = dev->priv;
840 struct sk_buff *skb;
841 while ((skb = skb_dequeue(&priv->tx_queue))) {
842 struct memrecord *range = (struct memrecord *)&skb->cb;
843 if (range->control)
844 kfree(range->control);
845 kfree_skb(skb);
846 }
847 priv->stop(dev);
a2897552 848 priv->mode = IEEE80211_IF_TYPE_INVALID;
4150c572
JB		 849}
850
eff1a59c
MW		 851static int p54_add_interface(struct ieee80211_hw *dev,
852 struct ieee80211_if_init_conf *conf)
853{
854 struct p54_common *priv = dev->priv;
eff1a59c 855
4150c572
JB		 856 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
857 return -EOPNOTSUPP;
eff1a59c
MW		 858
859 switch (conf->type) {
860 case IEEE80211_IF_TYPE_STA:
861 priv->mode = conf->type;
862 break;
863 default:
864 return -EOPNOTSUPP;
865 }
866
4150c572 867 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c
MW		 868
869 p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642);
870 p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642);
eff1a59c
MW		 871
872 switch (conf->type) {
873 case IEEE80211_IF_TYPE_STA:
874 p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0);
875 break;
4150c572
JB		 876 default:
877 BUG(); /* impossible */
878 break;
eff1a59c
MW		 879 }
880
881 p54_set_leds(dev, 1, 0, 0);
882
883 return 0;
884}
885
886static void p54_remove_interface(struct ieee80211_hw *dev,
887 struct ieee80211_if_init_conf *conf)
888{
889 struct p54_common *priv = dev->priv;
4150c572
JB		 890 priv->mode = IEEE80211_IF_TYPE_MNTR;
891 memset(priv->mac_addr, 0, ETH_ALEN);
892 p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0);
eff1a59c
MW		 893}
894
895static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
896{
897 int ret;
898
8318d78a 899 ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq));
eff1a59c
MW		 900 p54_set_vdcf(dev);
901 return ret;
902}
903
32bfd35d
JB		 904static int p54_config_interface(struct ieee80211_hw *dev,
905 struct ieee80211_vif *vif,
eff1a59c
MW		 906 struct ieee80211_if_conf *conf)
907{
908 struct p54_common *priv = dev->priv;
909
910 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642);
911 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0);
912 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 913 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
eff1a59c
MW		 914 return 0;
915}
916
4150c572
JB		 917static void p54_configure_filter(struct ieee80211_hw *dev,
918 unsigned int changed_flags,
919 unsigned int *total_flags,
920 int mc_count, struct dev_mc_list *mclist)
921{
922 struct p54_common *priv = dev->priv;
923
924 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
925
926 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
927 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
928 p54_set_filter(dev, 0, priv->mac_addr,
929 NULL, 2, 0, 0, 0);
930 else
931 p54_set_filter(dev, 0, priv->mac_addr,
932 priv->bssid, 2, 0, 0, 0);
933 }
934}
935
eff1a59c
MW		 936static int p54_conf_tx(struct ieee80211_hw *dev, int queue,
937 const struct ieee80211_tx_queue_params *params)
938{
939 struct p54_common *priv = dev->priv;
940 struct p54_tx_control_vdcf *vdcf;
941
942 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
943 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
944
945 if ((params) && !((queue < 0) || (queue > 4))) {
946 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
3330d7be 947 params->cw_min, params->cw_max, params->txop);
eff1a59c
MW		 948 } else
949 return -EINVAL;
950
951 p54_set_vdcf(dev);
952
953 return 0;
954}
955
956static int p54_get_stats(struct ieee80211_hw *dev,
957 struct ieee80211_low_level_stats *stats)
958{
959 /* TODO */
960 return 0;
961}
962
963static int p54_get_tx_stats(struct ieee80211_hw *dev,
964 struct ieee80211_tx_queue_stats *stats)
965{
966 struct p54_common *priv = dev->priv;
967 unsigned int i;
968
969 for (i = 0; i < dev->queues; i++)
970 memcpy(&stats->data[i], &priv->tx_stats.data[i],
971 sizeof(stats->data[i]));
972
973 return 0;
974}
975
976static const struct ieee80211_ops p54_ops = {
977 .tx = p54_tx,
4150c572
JB		 978 .start = p54_start,
979 .stop = p54_stop,
eff1a59c
MW		 980 .add_interface = p54_add_interface,
981 .remove_interface = p54_remove_interface,
982 .config = p54_config,
983 .config_interface = p54_config_interface,
4150c572 984 .configure_filter = p54_configure_filter,
eff1a59c
MW		 985 .conf_tx = p54_conf_tx,
986 .get_stats = p54_get_stats,
987 .get_tx_stats = p54_get_tx_stats
988};
989
990struct ieee80211_hw *p54_init_common(size_t priv_data_len)
991{
992 struct ieee80211_hw *dev;
993 struct p54_common *priv;
eff1a59c
MW		 994
995 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
996 if (!dev)
997 return NULL;
998
999 priv = dev->priv;
a2897552 1000 priv->mode = IEEE80211_IF_TYPE_INVALID;
eff1a59c 1001 skb_queue_head_init(&priv->tx_queue);
8318d78a 1002 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
eff1a59c
MW		 1003 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
1004 IEEE80211_HW_RX_INCLUDES_FCS;
1005 dev->channel_change_time = 1000; /* TODO: find actual value */
1006 dev->max_rssi = 127;
1007
1008 priv->tx_stats.data[0].limit = 5;
1009 dev->queues = 1;
1010
1011 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
1012 sizeof(struct p54_tx_control_allocdata);
1013
1014 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) +
1015 priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL);
1016
1017 if (!priv->cached_vdcf) {
1018 ieee80211_free_hw(dev);
1019 return NULL;
1020 }
1021
1022 p54_init_vdcf(dev);
1023
eff1a59c
MW		 1024 return dev;
1025}
1026EXPORT_SYMBOL_GPL(p54_init_common);
1027
1028void p54_free_common(struct ieee80211_hw *dev)
1029{
1030 struct p54_common *priv = dev->priv;
1031 kfree(priv->iq_autocal);
1032 kfree(priv->output_limit);
1033 kfree(priv->curve_data);
1034 kfree(priv->cached_vdcf);
1035}
1036EXPORT_SYMBOL_GPL(p54_free_common);
1037
1038static int __init p54_init(void)
1039{
1040 return 0;
1041}
1042
1043static void __exit p54_exit(void)
1044{
1045}
1046
1047module_init(p54_init);
1048module_exit(p54_exit);
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