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rt2x00: convert rt2x00usb_register_read return type
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ralink / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
41977e86
RY		 62#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
64 (__reg))
89297425
BZ		 65#define WAIT_FOR_RF(__dev, __reg) \
66 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
67#define WAIT_FOR_MCU(__dev, __reg) \
68 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
69 H2M_MAILBOX_CSR_OWNER, (__reg))
70
baff8006
HS		 71static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72{
73 /* check for rt2872 on SoC */
74 if (!rt2x00_is_soc(rt2x00dev) ||
75 !rt2x00_rt(rt2x00dev, RT2872))
76 return false;
77
78 /* we know for sure that these rf chipsets are used on rt305x boards */
79 if (rt2x00_rf(rt2x00dev, RF3020) ||
80 rt2x00_rf(rt2x00dev, RF3021) ||
81 rt2x00_rf(rt2x00dev, RF3022))
82 return true;
83
ec9c4989 84 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 85 return false;
86}
87
fcf51541
BZ		 88static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
89 const unsigned int word, const u8 value)
89297425
BZ		 90{
91 u32 reg;
92
93 mutex_lock(&rt2x00dev->csr_mutex);
94
95 /*
96 * Wait until the BBP becomes available, afterwards we
97 * can safely write the new data into the register.
98 */
99 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
100 reg = 0;
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 105 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 106
107 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
108 }
109
110 mutex_unlock(&rt2x00dev->csr_mutex);
111}
89297425 112
fcf51541
BZ		 113static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
114 const unsigned int word, u8 *value)
89297425
BZ		 115{
116 u32 reg;
117
118 mutex_lock(&rt2x00dev->csr_mutex);
119
120 /*
121 * Wait until the BBP becomes available, afterwards we
122 * can safely write the read request into the register.
123 * After the data has been written, we wait until hardware
124 * returns the correct value, if at any time the register
125 * doesn't become available in time, reg will be 0xffffffff
126 * which means we return 0xff to the caller.
127 */
128 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
129 reg = 0;
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 133 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 134
135 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136
137 WAIT_FOR_BBP(rt2x00dev, &reg);
138 }
139
140 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141
142 mutex_unlock(&rt2x00dev->csr_mutex);
143}
89297425 144
fcf51541
BZ		 145static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
146 const unsigned int word, const u8 value)
89297425
BZ		 147{
148 u32 reg;
149
150 mutex_lock(&rt2x00dev->csr_mutex);
151
152 /*
153 * Wait until the RFCSR becomes available, afterwards we
154 * can safely write the new data into the register.
155 */
41977e86
RY		 156 switch (rt2x00dev->chip.rt) {
157 case RT6352:
158 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
159 reg = 0;
160 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
161 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
162 word);
163 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
164 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
165
166 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
167 }
168 break;
89297425 169
41977e86
RY		 170 default:
171 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
172 reg = 0;
173 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
174 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
175 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
176 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
177
178 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
179 }
180 break;
89297425
BZ		 181 }
182
183 mutex_unlock(&rt2x00dev->csr_mutex);
184}
89297425 185
41977e86
RY		 186static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
187 const unsigned int reg, const u8 value)
188{
189 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
190}
191
192static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
193 const unsigned int reg, const u8 value)
194{
195 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
196 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
197}
198
199static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
200 const unsigned int reg, const u8 value)
201{
202 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
203 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
204}
205
16d571bb
AB		 206static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
207 const unsigned int word)
89297425
BZ		 208{
209 u32 reg;
16d571bb 210 u8 value;
89297425
BZ		 211
212 mutex_lock(&rt2x00dev->csr_mutex);
213
214 /*
215 * Wait until the RFCSR becomes available, afterwards we
216 * can safely write the read request into the register.
217 * After the data has been written, we wait until hardware
218 * returns the correct value, if at any time the register
219 * doesn't become available in time, reg will be 0xffffffff
220 * which means we return 0xff to the caller.
221 */
41977e86
RY		 222 switch (rt2x00dev->chip.rt) {
223 case RT6352:
224 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
225 reg = 0;
226 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
227 word);
228 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
229 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
89297425 230
41977e86 231 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
89297425 232
41977e86
RY		 233 WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
234 }
89297425 235
16d571bb 236 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
41977e86
RY		 237 break;
238
239 default:
240 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
241 reg = 0;
242 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
243 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
244 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
245
246 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
247
248 WAIT_FOR_RFCSR(rt2x00dev, &reg);
249 }
250
16d571bb 251 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
41977e86
RY		 252 break;
253 }
89297425
BZ		 254
255 mutex_unlock(&rt2x00dev->csr_mutex);
16d571bb
AB		 256
257 return value;
89297425 258}
89297425 259
16d571bb
AB		 260static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
261 const unsigned int reg)
41977e86 262{
16d571bb 263 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
41977e86
RY		 264}
265
fcf51541
BZ		 266static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
267 const unsigned int word, const u32 value)
89297425
BZ		 268{
269 u32 reg;
270
271 mutex_lock(&rt2x00dev->csr_mutex);
272
273 /*
274 * Wait until the RF becomes available, afterwards we
275 * can safely write the new data into the register.
276 */
277 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
278 reg = 0;
279 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
280 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
281 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
282 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
283
284 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
285 rt2x00_rf_write(rt2x00dev, word, value);
286 }
287
288 mutex_unlock(&rt2x00dev->csr_mutex);
289}
89297425 290
379448fe
GJ		 291static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
292 [EEPROM_CHIP_ID] = 0x0000,
293 [EEPROM_VERSION] = 0x0001,
294 [EEPROM_MAC_ADDR_0] = 0x0002,
295 [EEPROM_MAC_ADDR_1] = 0x0003,
296 [EEPROM_MAC_ADDR_2] = 0x0004,
297 [EEPROM_NIC_CONF0] = 0x001a,
298 [EEPROM_NIC_CONF1] = 0x001b,
299 [EEPROM_FREQ] = 0x001d,
300 [EEPROM_LED_AG_CONF] = 0x001e,
301 [EEPROM_LED_ACT_CONF] = 0x001f,
302 [EEPROM_LED_POLARITY] = 0x0020,
303 [EEPROM_NIC_CONF2] = 0x0021,
304 [EEPROM_LNA] = 0x0022,
305 [EEPROM_RSSI_BG] = 0x0023,
306 [EEPROM_RSSI_BG2] = 0x0024,
307 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
308 [EEPROM_RSSI_A] = 0x0025,
309 [EEPROM_RSSI_A2] = 0x0026,
310 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
311 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
312 [EEPROM_TXPOWER_DELTA] = 0x0028,
313 [EEPROM_TXPOWER_BG1] = 0x0029,
314 [EEPROM_TXPOWER_BG2] = 0x0030,
315 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
316 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
317 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
318 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
319 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
320 [EEPROM_TXPOWER_A1] = 0x003c,
321 [EEPROM_TXPOWER_A2] = 0x0053,
41977e86 322 [EEPROM_TXPOWER_INIT] = 0x0068,
379448fe
GJ		 323 [EEPROM_TSSI_BOUND_A1] = 0x006a,
324 [EEPROM_TSSI_BOUND_A2] = 0x006b,
325 [EEPROM_TSSI_BOUND_A3] = 0x006c,
326 [EEPROM_TSSI_BOUND_A4] = 0x006d,
327 [EEPROM_TSSI_BOUND_A5] = 0x006e,
328 [EEPROM_TXPOWER_BYRATE] = 0x006f,
329 [EEPROM_BBP_START] = 0x0078,
330};
331
fa31d157
GJ		 332static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
333 [EEPROM_CHIP_ID] = 0x0000,
334 [EEPROM_VERSION] = 0x0001,
335 [EEPROM_MAC_ADDR_0] = 0x0002,
336 [EEPROM_MAC_ADDR_1] = 0x0003,
337 [EEPROM_MAC_ADDR_2] = 0x0004,
338 [EEPROM_NIC_CONF0] = 0x001a,
339 [EEPROM_NIC_CONF1] = 0x001b,
340 [EEPROM_NIC_CONF2] = 0x001c,
341 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
342 [EEPROM_FREQ] = 0x0022,
343 [EEPROM_LED_AG_CONF] = 0x0023,
344 [EEPROM_LED_ACT_CONF] = 0x0024,
345 [EEPROM_LED_POLARITY] = 0x0025,
346 [EEPROM_LNA] = 0x0026,
347 [EEPROM_EXT_LNA2] = 0x0027,
348 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 349 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 350 [EEPROM_RSSI_A] = 0x002a,
351 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 352 [EEPROM_TXPOWER_BG1] = 0x0030,
353 [EEPROM_TXPOWER_BG2] = 0x0037,
354 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
355 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
356 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
357 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
358 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
359 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
360 [EEPROM_TXPOWER_A1] = 0x004b,
361 [EEPROM_TXPOWER_A2] = 0x0065,
362 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
363 [EEPROM_TSSI_BOUND_A1] = 0x009a,
364 [EEPROM_TSSI_BOUND_A2] = 0x009b,
365 [EEPROM_TSSI_BOUND_A3] = 0x009c,
366 [EEPROM_TSSI_BOUND_A4] = 0x009d,
367 [EEPROM_TSSI_BOUND_A5] = 0x009e,
368 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
369};
370
379448fe
GJ		 371static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
372 const enum rt2800_eeprom_word word)
373{
374 const unsigned int *map;
375 unsigned int index;
376
377 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
378 "%s: invalid EEPROM word %d\n",
379 wiphy_name(rt2x00dev->hw->wiphy), word))
380 return 0;
381
fa31d157
GJ		 382 if (rt2x00_rt(rt2x00dev, RT3593))
383 map = rt2800_eeprom_map_ext;
384 else
385 map = rt2800_eeprom_map;
386
379448fe
GJ		 387 index = map[word];
388
389 /* Index 0 is valid only for EEPROM_CHIP_ID.
390 * Otherwise it means that the offset of the
391 * given word is not initialized in the map,
392 * or that the field is not usable on the
393 * actual chipset.
394 */
395 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
396 "%s: invalid access of EEPROM word %d\n",
397 wiphy_name(rt2x00dev->hw->wiphy), word);
398
399 return index;
400}
401
3e38d3da
GJ		 402static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
403 const enum rt2800_eeprom_word word)
404{
379448fe
GJ		 405 unsigned int index;
406
407 index = rt2800_eeprom_word_index(rt2x00dev, word);
408 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 409}
410
411static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
412 const enum rt2800_eeprom_word word, u16 *data)
413{
379448fe
GJ		 414 unsigned int index;
415
416 index = rt2800_eeprom_word_index(rt2x00dev, word);
417 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 418}
419
420static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
421 const enum rt2800_eeprom_word word, u16 data)
422{
379448fe
GJ		 423 unsigned int index;
424
425 index = rt2800_eeprom_word_index(rt2x00dev, word);
426 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 427}
428
022138ca
GJ		 429static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
430 const enum rt2800_eeprom_word array,
431 unsigned int offset,
432 u16 *data)
433{
379448fe
GJ		 434 unsigned int index;
435
436 index = rt2800_eeprom_word_index(rt2x00dev, array);
437 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 438}
439
16ebd608
WH		 440static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
441{
442 u32 reg;
443 int i, count;
444
445 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
16ebd608
WH		 446 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
447 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
448 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
449 rt2x00_set_field32(&reg, WLAN_EN, 1);
450 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
451
452 udelay(REGISTER_BUSY_DELAY);
453
454 count = 0;
455 do {
456 /*
457 * Check PLL_LD & XTAL_RDY.
458 */
459 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
460 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
461 if (rt2x00_get_field32(reg, PLL_LD) &&
462 rt2x00_get_field32(reg, XTAL_RDY))
463 break;
464 udelay(REGISTER_BUSY_DELAY);
465 }
466
467 if (i >= REGISTER_BUSY_COUNT) {
468
469 if (count >= 10)
470 return -EIO;
471
472 rt2800_register_write(rt2x00dev, 0x58, 0x018);
473 udelay(REGISTER_BUSY_DELAY);
474 rt2800_register_write(rt2x00dev, 0x58, 0x418);
475 udelay(REGISTER_BUSY_DELAY);
476 rt2800_register_write(rt2x00dev, 0x58, 0x618);
477 udelay(REGISTER_BUSY_DELAY);
478 count++;
479 } else {
480 count = 0;
481 }
482
483 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
484 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
485 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
486 rt2x00_set_field32(&reg, WLAN_RESET, 1);
487 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
488 udelay(10);
489 rt2x00_set_field32(&reg, WLAN_RESET, 0);
490 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
491 udelay(10);
492 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
493 } while (count != 0);
494
495 return 0;
496}
497
89297425
BZ		 498void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
499 const u8 command, const u8 token,
500 const u8 arg0, const u8 arg1)
501{
502 u32 reg;
503
ee303e54 504 /*
cea90e55 505 * SOC devices don't support MCU requests.
ee303e54 506 */
cea90e55 507 if (rt2x00_is_soc(rt2x00dev))
ee303e54 508 return;
89297425
BZ		 509
510 mutex_lock(&rt2x00dev->csr_mutex);
511
512 /*
513 * Wait until the MCU becomes available, afterwards we
514 * can safely write the new data into the register.
515 */
516 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
517 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
518 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
519 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
520 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
521 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
522
523 reg = 0;
524 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
525 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
526 }
527
528 mutex_unlock(&rt2x00dev->csr_mutex);
529}
530EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 531
5ffddc49
ID		 532int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
533{
534 unsigned int i = 0;
535 u32 reg;
536
537 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
538 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
539 if (reg && reg != ~0)
540 return 0;
541 msleep(1);
542 }
543
ec9c4989 544 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 545 return -EBUSY;
546}
547EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
548
67a4c1e2
GW		 549int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
550{
551 unsigned int i;
552 u32 reg;
553
08e53100
HS		 554 /*
555 * Some devices are really slow to respond here. Wait a whole second
556 * before timing out.
557 */
67a4c1e2
GW		 558 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
559 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
560 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
561 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
562 return 0;
563
08e53100 564 msleep(10);
67a4c1e2
GW		 565 }
566
ec9c4989 567 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 568 return -EACCES;
569}
570EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
571
f7b395e9
JK		 572void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
573{
574 u32 reg;
575
576 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
577 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
578 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
579 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
580 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
581 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
582 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
583}
584EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
585
ae1b1c5d
GJ		 586void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
587 unsigned short *txwi_size,
588 unsigned short *rxwi_size)
589{
590 switch (rt2x00dev->chip.rt) {
591 case RT3593:
592 *txwi_size = TXWI_DESC_SIZE_4WORDS;
593 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
594 break;
595
596 case RT5592:
41977e86 597 case RT6352:
ae1b1c5d
GJ		 598 *txwi_size = TXWI_DESC_SIZE_5WORDS;
599 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
600 break;
601
602 default:
603 *txwi_size = TXWI_DESC_SIZE_4WORDS;
604 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
605 break;
606 }
607}
608EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
609
f31c9a8c
ID		 610static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
611{
612 u16 fw_crc;
613 u16 crc;
614
615 /*
616 * The last 2 bytes in the firmware array are the crc checksum itself,
617 * this means that we should never pass those 2 bytes to the crc
618 * algorithm.
619 */
620 fw_crc = (data[len - 2] << 8 | data[len - 1]);
621
622 /*
623 * Use the crc ccitt algorithm.
624 * This will return the same value as the legacy driver which
625 * used bit ordering reversion on the both the firmware bytes
626 * before input input as well as on the final output.
627 * Obviously using crc ccitt directly is much more efficient.
628 */
629 crc = crc_ccitt(~0, data, len - 2);
630
631 /*
632 * There is a small difference between the crc-itu-t + bitrev and
633 * the crc-ccitt crc calculation. In the latter method the 2 bytes
634 * will be swapped, use swab16 to convert the crc to the correct
635 * value.
636 */
637 crc = swab16(crc);
638
639 return fw_crc == crc;
640}
641
642int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
643 const u8 *data, const size_t len)
644{
645 size_t offset = 0;
646 size_t fw_len;
647 bool multiple;
648
649 /*
650 * PCI(e) & SOC devices require firmware with a length
651 * of 8kb. USB devices require firmware files with a length
652 * of 4kb. Certain USB chipsets however require different firmware,
653 * which Ralink only provides attached to the original firmware
654 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 655 * which is a multiple of 4kb. The firmware for rt3290 chip also
656 * have a length which is a multiple of 4kb.
f31c9a8c 657 */
a89534ed 658 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 659 fw_len = 4096;
a89534ed 660 else
f31c9a8c 661 fw_len = 8192;
f31c9a8c 662
a89534ed 663 multiple = true;
f31c9a8c
ID		 664 /*
665 * Validate the firmware length
666 */
667 if (len != fw_len && (!multiple || (len % fw_len) != 0))
668 return FW_BAD_LENGTH;
669
670 /*
671 * Check if the chipset requires one of the upper parts
672 * of the firmware.
673 */
674 if (rt2x00_is_usb(rt2x00dev) &&
675 !rt2x00_rt(rt2x00dev, RT2860) &&
676 !rt2x00_rt(rt2x00dev, RT2872) &&
677 !rt2x00_rt(rt2x00dev, RT3070) &&
678 ((len / fw_len) == 1))
679 return FW_BAD_VERSION;
680
681 /*
682 * 8kb firmware files must be checked as if it were
683 * 2 separate firmware files.
684 */
685 while (offset < len) {
686 if (!rt2800_check_firmware_crc(data + offset, fw_len))
687 return FW_BAD_CRC;
688
689 offset += fw_len;
690 }
691
692 return FW_OK;
693}
694EXPORT_SYMBOL_GPL(rt2800_check_firmware);
695
696int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
697 const u8 *data, const size_t len)
698{
699 unsigned int i;
700 u32 reg;
16ebd608
WH		 701 int retval;
702
703 if (rt2x00_rt(rt2x00dev, RT3290)) {
704 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
705 if (retval)
706 return -EBUSY;
707 }
f31c9a8c
ID		 708
709 /*
b9eca242
ID		 710 * If driver doesn't wake up firmware here,
711 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 712 */
b9eca242 713 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 714
f31c9a8c
ID		 715 /*
716 * Wait for stable hardware.
717 */
5ffddc49 718 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 719 return -EBUSY;
f31c9a8c 720
adde5882 721 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 722 if (rt2x00_rt(rt2x00dev, RT3290) ||
723 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 724 rt2x00_rt(rt2x00dev, RT5390) ||
725 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 726 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
727 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
728 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
729 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
730 }
f31c9a8c 731 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 732 }
f31c9a8c 733
b7e1d225
JK		 734 rt2800_disable_wpdma(rt2x00dev);
735
f31c9a8c
ID		 736 /*
737 * Write firmware to the device.
738 */
739 rt2800_drv_write_firmware(rt2x00dev, data, len);
740
741 /*
742 * Wait for device to stabilize.
743 */
744 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
745 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
746 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
747 break;
748 msleep(1);
749 }
750
751 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 752 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 753 return -EBUSY;
754 }
755
4ed1dd2a
SG		 756 /*
757 * Disable DMA, will be reenabled later when enabling
758 * the radio.
759 */
f7b395e9 760 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 761
f31c9a8c
ID		 762 /*
763 * Initialize firmware.
764 */
765 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
766 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 767 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 768 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 769 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
770 }
f31c9a8c
ID		 771 msleep(1);
772
773 return 0;
774}
775EXPORT_SYMBOL_GPL(rt2800_load_firmware);
776
0c5879bc
ID		 777void rt2800_write_tx_data(struct queue_entry *entry,
778 struct txentry_desc *txdesc)
59679b91 779{
0c5879bc 780 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 781 u32 word;
557985ae 782 int i;
59679b91
GW		 783
784 /*
785 * Initialize TX Info descriptor
786 */
787 rt2x00_desc_read(txwi, 0, &word);
788 rt2x00_set_field32(&word, TXWI_W0_FRAG,
789 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 790 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
791 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 792 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
793 rt2x00_set_field32(&word, TXWI_W0_TS,
794 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
795 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
796 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 797 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
798 txdesc->u.ht.mpdu_density);
799 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
800 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 801 rt2x00_set_field32(&word, TXWI_W0_BW,
802 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
803 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
804 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 805 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 806 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
807 rt2x00_desc_write(txwi, 0, word);
808
809 rt2x00_desc_read(txwi, 1, &word);
810 rt2x00_set_field32(&word, TXWI_W1_ACK,
811 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
812 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
813 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 814 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 815 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
816 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 817 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 818 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
819 txdesc->length);
2b23cdaa 820 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 821 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 822 rt2x00_desc_write(txwi, 1, word);
823
824 /*
557985ae
SG		 825 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
826 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 827 * When TXD_W3_WIV is set to 1 it will use the IV data
828 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
829 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 830 *
831 * Nulify all remaining words as well, we don't know how to program them.
59679b91 832 */
557985ae
SG		 833 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
834 _rt2x00_desc_write(txwi, i, 0);
59679b91 835}
0c5879bc 836EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 837
ff6133be 838static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 839{
7fc41755
LT		 840 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
841 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
842 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 843 u16 eeprom;
844 u8 offset0;
845 u8 offset1;
846 u8 offset2;
847
57fbcce3 848 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 849 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 850 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
851 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 852 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 853 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
854 } else {
3e38d3da 855 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 856 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
857 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 858 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 859 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
860 }
861
862 /*
863 * Convert the value from the descriptor into the RSSI value
864 * If the value in the descriptor is 0, it is considered invalid
865 * and the default (extremely low) rssi value is assumed
866 */
867 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
868 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
869 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
870
871 /*
872 * mac80211 only accepts a single RSSI value. Calculating the
873 * average doesn't deliver a fair answer either since -60:-60 would
874 * be considered equally good as -50:-70 while the second is the one
875 * which gives less energy...
876 */
877 rssi0 = max(rssi0, rssi1);
7fc41755 878 return (int)max(rssi0, rssi2);
74861922
ID		 879}
880
881void rt2800_process_rxwi(struct queue_entry *entry,
882 struct rxdone_entry_desc *rxdesc)
883{
884 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 885 u32 word;
886
887 rt2x00_desc_read(rxwi, 0, &word);
888
889 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
890 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
891
892 rt2x00_desc_read(rxwi, 1, &word);
893
894 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
7fdd69c5 895 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2de64dd2
GW		 896
897 if (rt2x00_get_field32(word, RXWI_W1_BW))
da6a4352 898 rxdesc->bw = RATE_INFO_BW_40;
2de64dd2
GW		 899
900 /*
901 * Detect RX rate, always use MCS as signal type.
902 */
903 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
904 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
905 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
906
907 /*
908 * Mask of 0x8 bit to remove the short preamble flag.
909 */
910 if (rxdesc->rate_mode == RATE_MODE_CCK)
911 rxdesc->signal &= ~0x8;
912
913 rt2x00_desc_read(rxwi, 2, &word);
914
74861922
ID		 915 /*
916 * Convert descriptor AGC value to RSSI value.
917 */
918 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 919 /*
920 * Remove RXWI descriptor from start of the buffer.
921 */
922 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 923}
924EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
925
9d7a7a4d
SG		 926static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
927 u32 status, enum nl80211_band band)
928{
929 u8 flags = 0;
930 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
931
932 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
933 case RATE_MODE_HT_GREENFIELD:
934 flags |= IEEE80211_TX_RC_GREEN_FIELD;
935 /* fall through */
936 case RATE_MODE_HT_MIX:
937 flags |= IEEE80211_TX_RC_MCS;
938 break;
939 case RATE_MODE_OFDM:
940 if (band == NL80211_BAND_2GHZ)
941 idx += 4;
942 break;
943 case RATE_MODE_CCK:
944 if (idx >= 8)
945 idx -= 8;
946 break;
947 }
948
949 if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
950 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
951
952 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
953 flags |= IEEE80211_TX_RC_SHORT_GI;
954
955 skbdesc->tx_rate_idx = idx;
956 skbdesc->tx_rate_flags = flags;
957}
958
293dff78
SG		 959void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
960 bool match)
14433331
HS		 961{
962 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
a13d985f 963 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
b34793ee 964 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 965 struct txdone_entry_desc txdesc;
966 u32 word;
967 u16 mcs, real_mcs;
293dff78 968 int aggr, ampdu, wcid, ack_req;
14433331
HS		 969
970 /*
971 * Obtain the status about this packet.
972 */
973 txdesc.flags = 0;
14433331 974 rt2x00_desc_read(txwi, 0, &word);
b34793ee 975
14433331 976 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 977 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
978
14433331 979 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee 980 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
a13d985f 981 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
293dff78 982 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
b34793ee
HS		 983
984 /*
985 * If a frame was meant to be sent as a single non-aggregated MPDU
986 * but ended up in an aggregate the used tx rate doesn't correlate
987 * with the one specified in the TXWI as the whole aggregate is sent
988 * with the same rate.
989 *
990 * For example: two frames are sent to rt2x00, the first one sets
991 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
992 * and requests MCS15. If the hw aggregates both frames into one
993 * AMDPU the tx status for both frames will contain MCS7 although
994 * the frame was sent successfully.
995 *
996 * Hence, replace the requested rate with the real tx rate to not
997 * confuse the rate control algortihm by providing clearly wrong
998 * data.
293dff78
SG		 999 *
1000 * FIXME: if we do not find matching entry, we tell that frame was
1001 * posted without any retries. We need to find a way to fix that
1002 * and provide retry count.
1003 */
1004 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
9d7a7a4d 1005 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
b34793ee
HS		 1006 mcs = real_mcs;
1007 }
14433331 1008
f16d2db7
HS		 1009 if (aggr == 1 || ampdu == 1)
1010 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1011
293dff78
SG		 1012 if (!ack_req)
1013 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1014
14433331
HS		 1015 /*
1016 * Ralink has a retry mechanism using a global fallback
1017 * table. We setup this fallback table to try the immediate
1018 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1019 * always contains the MCS used for the last transmission, be
1020 * it successful or not.
1021 */
1022 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1023 /*
1024 * Transmission succeeded. The number of retries is
1025 * mcs - real_mcs
1026 */
1027 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1028 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1029 } else {
1030 /*
1031 * Transmission failed. The number of retries is
1032 * always 7 in this case (for a total number of 8
1033 * frames sent).
1034 */
1035 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1036 txdesc.retry = rt2x00dev->long_retry;
1037 }
1038
1039 /*
1040 * the frame was retried at least once
1041 * -> hw used fallback rates
1042 */
1043 if (txdesc.retry)
1044 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1045
293dff78
SG		 1046 if (!match) {
1047 /* RCU assures non-null sta will not be freed by mac80211. */
1048 rcu_read_lock();
1049 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1050 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1051 else
1052 skbdesc->sta = NULL;
1053 rt2x00lib_txdone_nomatch(entry, &txdesc);
1054 rcu_read_unlock();
1055 } else {
1056 rt2x00lib_txdone(entry, &txdesc);
1057 }
14433331
HS		 1058}
1059EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1060
21c6af6b
GJ		 1061static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1062 unsigned int index)
1063{
1064 return HW_BEACON_BASE(index);
1065}
1066
634b8059
GJ		 1067static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1068 unsigned int index)
1069{
1070 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1071}
1072
ba08910e
SG		 1073static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1074{
1075 struct data_queue *queue = rt2x00dev->bcn;
1076 struct queue_entry *entry;
1077 int i, bcn_num = 0;
1078 u64 off, reg = 0;
1079 u32 bssid_dw1;
1080
1081 /*
1082 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1083 */
1084 for (i = 0; i < queue->limit; i++) {
1085 entry = &queue->entries[i];
1086 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1087 continue;
1088 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1089 reg |= off << (8 * bcn_num);
1090 bcn_num++;
1091 }
1092
ba08910e
SG		 1093 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1094 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1095
1096 /*
1097 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1098 */
1099 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
1100 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1101 bcn_num > 0 ? bcn_num - 1 : 0);
1102 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1103}
1104
f0194b2d
GW		 1105void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1106{
1107 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1108 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1109 unsigned int beacon_base;
739fd940 1110 unsigned int padding_len;
d76dfc61 1111 u32 orig_reg, reg;
f0bda571 1112 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 1113
1114 /*
1115 * Disable beaconing while we are reloading the beacon data,
1116 * otherwise we might be sending out invalid data.
1117 */
1118 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 1119 orig_reg = reg;
f0194b2d
GW		 1120 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1121 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1122
1123 /*
1124 * Add space for the TXWI in front of the skb.
1125 */
f0bda571 1126 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1127
1128 /*
1129 * Register descriptor details in skb frame descriptor.
1130 */
1131 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1132 skbdesc->desc = entry->skb->data;
f0bda571 1133 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1134
1135 /*
1136 * Add the TXWI for the beacon to the skb.
1137 */
0c5879bc 1138 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1139
1140 /*
1141 * Dump beacon to userspace through debugfs.
1142 */
2ceb8137 1143 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
f0194b2d
GW		 1144
1145 /*
739fd940 1146 * Write entire beacon with TXWI and padding to register.
f0194b2d 1147 */
739fd940 1148 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1149 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1150 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1151 /* skb freed by skb_pad() on failure */
1152 entry->skb = NULL;
1153 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1154 return;
1155 }
1156
21c6af6b
GJ		 1157 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1158
739fd940
WK		 1159 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1160 entry->skb->len + padding_len);
ba08910e
SG		 1161 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1162
1163 /*
1164 * Change global beacons settings.
1165 */
1166 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1167
1168 /*
bc0df75a 1169 * Restore beaconing state.
f0194b2d 1170 */
bc0df75a 1171 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1172
1173 /*
1174 * Clean up beacon skb.
1175 */
1176 dev_kfree_skb_any(entry->skb);
1177 entry->skb = NULL;
1178}
50e888ea 1179EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1180
69cf36a4 1181static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1182 unsigned int index)
fdb87251
HS		 1183{
1184 int i;
0879f875 1185 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1186 unsigned int beacon_base;
1187
21c6af6b 1188 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1189
1190 /*
1191 * For the Beacon base registers we only need to clear
1192 * the whole TXWI which (when set to 0) will invalidate
1193 * the entire beacon.
1194 */
f0bda571 1195 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1196 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1197}
1198
69cf36a4
HS		 1199void rt2800_clear_beacon(struct queue_entry *entry)
1200{
1201 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1202 u32 orig_reg, reg;
69cf36a4
HS		 1203
1204 /*
1205 * Disable beaconing while we are reloading the beacon data,
1206 * otherwise we might be sending out invalid data.
1207 */
bc0df75a
SG		 1208 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1209 reg = orig_reg;
69cf36a4
HS		 1210 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1211 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1212
1213 /*
1214 * Clear beacon.
1215 */
77f7c0f3 1216 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1217 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1218
ba08910e
SG		 1219 /*
1220 * Change global beacons settings.
1221 */
1222 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1223 /*
bc0df75a 1224 * Restore beaconing state.
69cf36a4 1225 */
bc0df75a 1226 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1227}
1228EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1229
f4450616 1230#ifdef CONFIG_RT2X00_LIB_DEBUGFS
6b81745e
AB		 1231static u8 _rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
1232{
1233 u8 value;
1234
1235 rt2800_bbp_read(rt2x00dev, word, &value);
1236
1237 return value;
1238}
1239
f4450616
BZ		 1240const struct rt2x00debug rt2800_rt2x00debug = {
1241 .owner = THIS_MODULE,
1242 .csr = {
6b81745e 1243 .read = _rt2800_register_read,
f4450616
BZ		 1244 .write = rt2800_register_write,
1245 .flags = RT2X00DEBUGFS_OFFSET,
1246 .word_base = CSR_REG_BASE,
1247 .word_size = sizeof(u32),
1248 .word_count = CSR_REG_SIZE / sizeof(u32),
1249 },
1250 .eeprom = {
3e38d3da
GJ		 1251 /* NOTE: The local EEPROM access functions can't
1252 * be used here, use the generic versions instead.
1253 */
6b81745e 1254 .read = _rt2x00_eeprom_read,
f4450616
BZ		 1255 .write = rt2x00_eeprom_write,
1256 .word_base = EEPROM_BASE,
1257 .word_size = sizeof(u16),
1258 .word_count = EEPROM_SIZE / sizeof(u16),
1259 },
1260 .bbp = {
6b81745e 1261 .read = _rt2800_bbp_read,
f4450616
BZ		 1262 .write = rt2800_bbp_write,
1263 .word_base = BBP_BASE,
1264 .word_size = sizeof(u8),
1265 .word_count = BBP_SIZE / sizeof(u8),
1266 },
1267 .rf = {
aea8baa1 1268 .read = rt2x00_rf_read,
f4450616
BZ		 1269 .write = rt2800_rf_write,
1270 .word_base = RF_BASE,
1271 .word_size = sizeof(u32),
1272 .word_count = RF_SIZE / sizeof(u32),
1273 },
f2bd7f16 1274 .rfcsr = {
16d571bb 1275 .read = rt2800_rfcsr_read,
f2bd7f16
AA		 1276 .write = rt2800_rfcsr_write,
1277 .word_base = RFCSR_BASE,
1278 .word_size = sizeof(u8),
1279 .word_count = RFCSR_SIZE / sizeof(u8),
1280 },
f4450616
BZ		 1281};
1282EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1283#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1284
1285int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1286{
1287 u32 reg;
1288
a89534ed
WH		 1289 if (rt2x00_rt(rt2x00dev, RT3290)) {
1290 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1291 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1292 } else {
99bdf51a
GW		 1293 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1294 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1295 }
f4450616
BZ		 1296}
1297EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1298
1299#ifdef CONFIG_RT2X00_LIB_LEDS
1300static void rt2800_brightness_set(struct led_classdev *led_cdev,
1301 enum led_brightness brightness)
1302{
1303 struct rt2x00_led *led =
1304 container_of(led_cdev, struct rt2x00_led, led_dev);
1305 unsigned int enabled = brightness != LED_OFF;
1306 unsigned int bg_mode =
57fbcce3 1307 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
f4450616
BZ		 1308 unsigned int polarity =
1309 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1310 EEPROM_FREQ_LED_POLARITY);
1311 unsigned int ledmode =
1312 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1313 EEPROM_FREQ_LED_MODE);
44704e5d 1314 u32 reg;
f4450616 1315
44704e5d
LE		 1316 /* Check for SoC (SOC devices don't support MCU requests) */
1317 if (rt2x00_is_soc(led->rt2x00dev)) {
1318 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1319
1320 /* Set LED Polarity */
1321 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1322
1323 /* Set LED Mode */
1324 if (led->type == LED_TYPE_RADIO) {
1325 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1326 enabled ? 3 : 0);
1327 } else if (led->type == LED_TYPE_ASSOC) {
1328 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1329 enabled ? 3 : 0);
1330 } else if (led->type == LED_TYPE_QUALITY) {
1331 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1332 enabled ? 3 : 0);
1333 }
1334
1335 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1336
1337 } else {
1338 if (led->type == LED_TYPE_RADIO) {
1339 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1340 enabled ? 0x20 : 0);
1341 } else if (led->type == LED_TYPE_ASSOC) {
1342 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1343 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1344 } else if (led->type == LED_TYPE_QUALITY) {
1345 /*
1346 * The brightness is divided into 6 levels (0 - 5),
1347 * The specs tell us the following levels:
1348 * 0, 1 ,3, 7, 15, 31
1349 * to determine the level in a simple way we can simply
1350 * work with bitshifting:
1351 * (1 << level) - 1
1352 */
1353 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1354 (1 << brightness / (LED_FULL / 6)) - 1,
1355 polarity);
1356 }
f4450616
BZ		 1357 }
1358}
1359
b3579d6a 1360static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1361 struct rt2x00_led *led, enum led_type type)
1362{
1363 led->rt2x00dev = rt2x00dev;
1364 led->type = type;
1365 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1366 led->flags = LED_INITIALIZED;
1367}
f4450616
BZ		 1368#endif /* CONFIG_RT2X00_LIB_LEDS */
1369
1370/*
1371 * Configuration handlers.
1372 */
a2b1328a
HS		 1373static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1374 const u8 *address,
1375 int wcid)
f4450616
BZ		 1376{
1377 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1378 u32 offset;
1379
1380 offset = MAC_WCID_ENTRY(wcid);
1381
1382 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1383 if (address)
1384 memcpy(wcid_entry.mac, address, ETH_ALEN);
1385
1386 rt2800_register_multiwrite(rt2x00dev, offset,
1387 &wcid_entry, sizeof(wcid_entry));
1388}
1389
1390static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1391{
1392 u32 offset;
1393 offset = MAC_WCID_ATTR_ENTRY(wcid);
1394 rt2800_register_write(rt2x00dev, offset, 0);
1395}
1396
1397static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1398 int wcid, u32 bssidx)
1399{
1400 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1401 u32 reg;
1402
1403 /*
1404 * The BSS Idx numbers is split in a main value of 3 bits,
1405 * and a extended field for adding one additional bit to the value.
1406 */
1407 rt2800_register_read(rt2x00dev, offset, &reg);
1408 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1409 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1410 (bssidx & 0x8) >> 3);
1411 rt2800_register_write(rt2x00dev, offset, reg);
1412}
1413
1414static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1415 struct rt2x00lib_crypto *crypto,
1416 struct ieee80211_key_conf *key)
1417{
f4450616
BZ		 1418 struct mac_iveiv_entry iveiv_entry;
1419 u32 offset;
1420 u32 reg;
1421
1422 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1423
e4a0ab34
ID		 1424 if (crypto->cmd == SET_KEY) {
1425 rt2800_register_read(rt2x00dev, offset, &reg);
1426 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1427 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1428 /*
1429 * Both the cipher as the BSS Idx numbers are split in a main
1430 * value of 3 bits, and a extended field for adding one additional
1431 * bit to the value.
1432 */
1433 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1434 (crypto->cipher & 0x7));
1435 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1436 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1437 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1438 rt2800_register_write(rt2x00dev, offset, reg);
1439 } else {
a2b1328a
HS		 1440 /* Delete the cipher without touching the bssidx */
1441 rt2800_register_read(rt2x00dev, offset, &reg);
1442 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1443 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1444 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1445 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1446 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1447 }
f4450616
BZ		 1448
1449 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1450
1451 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1452 if ((crypto->cipher == CIPHER_TKIP) ||
1453 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1454 (crypto->cipher == CIPHER_AES))
1455 iveiv_entry.iv[3] |= 0x20;
1456 iveiv_entry.iv[3] |= key->keyidx << 6;
1457 rt2800_register_multiwrite(rt2x00dev, offset,
1458 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1459}
1460
1461int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1462 struct rt2x00lib_crypto *crypto,
1463 struct ieee80211_key_conf *key)
1464{
1465 struct hw_key_entry key_entry;
1466 struct rt2x00_field32 field;
1467 u32 offset;
1468 u32 reg;
1469
1470 if (crypto->cmd == SET_KEY) {
1471 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1472
1473 memcpy(key_entry.key, crypto->key,
1474 sizeof(key_entry.key));
1475 memcpy(key_entry.tx_mic, crypto->tx_mic,
1476 sizeof(key_entry.tx_mic));
1477 memcpy(key_entry.rx_mic, crypto->rx_mic,
1478 sizeof(key_entry.rx_mic));
1479
1480 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1481 rt2800_register_multiwrite(rt2x00dev, offset,
1482 &key_entry, sizeof(key_entry));
1483 }
1484
1485 /*
1486 * The cipher types are stored over multiple registers
1487 * starting with SHARED_KEY_MODE_BASE each word will have
1488 * 32 bits and contains the cipher types for 2 bssidx each.
1489 * Using the correct defines correctly will cause overhead,
1490 * so just calculate the correct offset.
1491 */
1492 field.bit_offset = 4 * (key->hw_key_idx % 8);
1493 field.bit_mask = 0x7 << field.bit_offset;
1494
1495 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1496
1497 rt2800_register_read(rt2x00dev, offset, &reg);
1498 rt2x00_set_field32(&reg, field,
1499 (crypto->cmd == SET_KEY) * crypto->cipher);
1500 rt2800_register_write(rt2x00dev, offset, reg);
1501
1502 /*
1503 * Update WCID information
1504 */
a2b1328a
HS		 1505 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1506 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1507 crypto->bssidx);
1508 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1509
1510 return 0;
1511}
1512EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1513
1514int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1515 struct rt2x00lib_crypto *crypto,
1516 struct ieee80211_key_conf *key)
1517{
1518 struct hw_key_entry key_entry;
1519 u32 offset;
1520
1521 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1522 /*
1523 * Allow key configuration only for STAs that are
1524 * known by the hw.
1525 */
ed8e0ed5 1526 if (crypto->wcid > WCID_END)
f4450616 1527 return -ENOSPC;
a2b1328a 1528 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1529
1530 memcpy(key_entry.key, crypto->key,
1531 sizeof(key_entry.key));
1532 memcpy(key_entry.tx_mic, crypto->tx_mic,
1533 sizeof(key_entry.tx_mic));
1534 memcpy(key_entry.rx_mic, crypto->rx_mic,
1535 sizeof(key_entry.rx_mic));
1536
1537 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1538 rt2800_register_multiwrite(rt2x00dev, offset,
1539 &key_entry, sizeof(key_entry));
1540 }
1541
1542 /*
1543 * Update WCID information
1544 */
a2b1328a 1545 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1546
1547 return 0;
1548}
1549EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1550
8f03a7c6
SG		 1551static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1552{
1553 u8 i, max_psdu;
1554 u32 reg;
1555 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1556
1557 for (i = 0; i < 3; i++)
1558 if (drv_data->ampdu_factor_cnt[i] > 0)
1559 break;
1560
1561 max_psdu = min(drv_data->max_psdu, i);
1562
1563 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1564 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1565 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1566}
1567
a2b1328a
HS		 1568int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1569 struct ieee80211_sta *sta)
1570{
1571 int wcid;
1572 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
ed8e0ed5 1573 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
a2b1328a 1574
8f03a7c6
SG		 1575 /*
1576 * Limit global maximum TX AMPDU length to smallest value of all
1577 * connected stations. In AP mode this can be suboptimal, but we
1578 * do not have a choice if some connected STA is not capable to
1579 * receive the same amount of data like the others.
1580 */
1581 if (sta->ht_cap.ht_supported) {
1582 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1583 rt2800_set_max_psdu_len(rt2x00dev);
1584 }
1585
a2b1328a 1586 /*
ed8e0ed5
SG		 1587 * Search for the first free WCID entry and return the corresponding
1588 * index.
a2b1328a 1589 */
ed8e0ed5 1590 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
a2b1328a
HS		 1591
1592 /*
1593 * Store selected wcid even if it is invalid so that we can
1594 * later decide if the STA is uploaded into the hw.
1595 */
1596 sta_priv->wcid = wcid;
1597
1598 /*
1599 * No space left in the device, however, we can still communicate
1600 * with the STA -> No error.
1601 */
ed8e0ed5 1602 if (wcid > WCID_END)
a2b1328a
HS		 1603 return 0;
1604
ed8e0ed5 1605 __set_bit(wcid - WCID_START, drv_data->sta_ids);
a13d985f 1606 drv_data->wcid_to_sta[wcid - WCID_START] = sta;
ed8e0ed5 1607
a2b1328a
HS		 1608 /*
1609 * Clean up WCID attributes and write STA address to the device.
1610 */
1611 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1612 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1613 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1614 rt2x00lib_get_bssidx(rt2x00dev, vif));
1615 return 0;
1616}
1617EXPORT_SYMBOL_GPL(rt2800_sta_add);
1618
8f03a7c6 1619int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta)
a2b1328a 1620{
ed8e0ed5 1621 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8f03a7c6
SG		 1622 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1623 int wcid = sta_priv->wcid;
1624
1625 if (sta->ht_cap.ht_supported) {
1626 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1627 rt2800_set_max_psdu_len(rt2x00dev);
1628 }
ed8e0ed5
SG		 1629
1630 if (wcid > WCID_END)
1631 return 0;
a2b1328a
HS		 1632 /*
1633 * Remove WCID entry, no need to clean the attributes as they will
1634 * get renewed when the WCID is reused.
1635 */
1636 rt2800_config_wcid(rt2x00dev, NULL, wcid);
a13d985f 1637 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
ed8e0ed5 1638 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
a2b1328a
HS		 1639
1640 return 0;
1641}
1642EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1643
f4450616
BZ		 1644void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1645 const unsigned int filter_flags)
1646{
1647 u32 reg;
1648
1649 /*
1650 * Start configuration steps.
1651 * Note that the version error will always be dropped
1652 * and broadcast frames will always be accepted since
1653 * there is no filter for it at this time.
1654 */
1655 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1656 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1657 !(filter_flags & FIF_FCSFAIL));
1658 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1659 !(filter_flags & FIF_PLCPFAIL));
262c741e
EC		 1660 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1661 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
f4450616
BZ		 1662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1663 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1664 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1665 !(filter_flags & FIF_ALLMULTI));
1666 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1667 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1668 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1669 !(filter_flags & FIF_CONTROL));
1670 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1671 !(filter_flags & FIF_CONTROL));
1672 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1673 !(filter_flags & FIF_CONTROL));
1674 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1675 !(filter_flags & FIF_CONTROL));
1676 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1677 !(filter_flags & FIF_CONTROL));
1678 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1679 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1680 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1681 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1682 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1683 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1684 !(filter_flags & FIF_CONTROL));
1685 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1686}
1687EXPORT_SYMBOL_GPL(rt2800_config_filter);
1688
1689void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1690 struct rt2x00intf_conf *conf, const unsigned int flags)
1691{
f4450616 1692 u32 reg;
fa8b4b22 1693 bool update_bssid = false;
f4450616
BZ		 1694
1695 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1696 /*
1697 * Enable synchronisation.
1698 */
1699 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1700 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1701 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1702
1703 if (conf->sync == TSF_SYNC_AP_NONE) {
1704 /*
1705 * Tune beacon queue transmit parameters for AP mode
1706 */
1707 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1708 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1709 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1710 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1711 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1712 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1713 } else {
1714 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1715 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1716 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1717 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1718 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1719 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1720 }
f4450616
BZ		 1721 }
1722
1723 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1724 if (flags & CONFIG_UPDATE_TYPE &&
1725 conf->sync == TSF_SYNC_AP_NONE) {
1726 /*
1727 * The BSSID register has to be set to our own mac
1728 * address in AP mode.
1729 */
1730 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1731 update_bssid = true;
1732 }
1733
c600c826
ID		 1734 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1735 reg = le32_to_cpu(conf->mac[1]);
1736 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1737 conf->mac[1] = cpu_to_le32(reg);
1738 }
f4450616
BZ		 1739
1740 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1741 conf->mac, sizeof(conf->mac));
1742 }
1743
fa8b4b22 1744 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1745 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1746 reg = le32_to_cpu(conf->bssid[1]);
1747 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1748 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1749 conf->bssid[1] = cpu_to_le32(reg);
1750 }
f4450616
BZ		 1751
1752 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1753 conf->bssid, sizeof(conf->bssid));
1754 }
1755}
1756EXPORT_SYMBOL_GPL(rt2800_config_intf);
1757
87c1915d
HS		 1758static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1759 struct rt2x00lib_erp *erp)
1760{
1761 bool any_sta_nongf = !!(erp->ht_opmode &
1762 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1763 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1764 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1765 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1766 u32 reg;
1767
1768 /* default protection rate for HT20: OFDM 24M */
1769 mm20_rate = gf20_rate = 0x4004;
1770
1771 /* default protection rate for HT40: duplicate OFDM 24M */
1772 mm40_rate = gf40_rate = 0x4084;
1773
1774 switch (protection) {
1775 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1776 /*
1777 * All STAs in this BSS are HT20/40 but there might be
1778 * STAs not supporting greenfield mode.
1779 * => Disable protection for HT transmissions.
1780 */
1781 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1782
1783 break;
1784 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1785 /*
1786 * All STAs in this BSS are HT20 or HT20/40 but there
1787 * might be STAs not supporting greenfield mode.
1788 * => Protect all HT40 transmissions.
1789 */
1790 mm20_mode = gf20_mode = 0;
6c40063d 1791 mm40_mode = gf40_mode = 1;
87c1915d
HS		 1792
1793 break;
1794 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1795 /*
1796 * Nonmember protection:
1797 * According to 802.11n we _should_ protect all
1798 * HT transmissions (but we don't have to).
1799 *
1800 * But if cts_protection is enabled we _shall_ protect
1801 * all HT transmissions using a CCK rate.
1802 *
1803 * And if any station is non GF we _shall_ protect
1804 * GF transmissions.
1805 *
1806 * We decide to protect everything
1807 * -> fall through to mixed mode.
1808 */
1809 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1810 /*
1811 * Legacy STAs are present
1812 * => Protect all HT transmissions.
1813 */
6c40063d 1814 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
87c1915d
HS		 1815
1816 /*
1817 * If erp protection is needed we have to protect HT
1818 * transmissions with CCK 11M long preamble.
1819 */
1820 if (erp->cts_protection) {
1821 /* don't duplicate RTS/CTS in CCK mode */
1822 mm20_rate = mm40_rate = 0x0003;
1823 gf20_rate = gf40_rate = 0x0003;
1824 }
1825 break;
6403eab1 1826 }
87c1915d
HS		 1827
1828 /* check for STAs not supporting greenfield mode */
1829 if (any_sta_nongf)
6c40063d 1830 gf20_mode = gf40_mode = 1;
87c1915d
HS		 1831
1832 /* Update HT protection config */
1833 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1834 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1835 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1836 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1837
1838 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1839 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1840 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1841 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1842
1843 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1844 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1845 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1846 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1847
1848 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1849 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1850 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1851 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1852}
1853
02044643
HS		 1854void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1855 u32 changed)
f4450616
BZ		 1856{
1857 u32 reg;
1858
02044643
HS		 1859 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1860 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
02044643
HS		 1861 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1862 !!erp->short_preamble);
1863 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1864 }
f4450616 1865
02044643
HS		 1866 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1867 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1868 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1869 erp->cts_protection ? 2 : 0);
1870 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1871 }
f4450616 1872
02044643
HS		 1873 if (changed & BSS_CHANGED_BASIC_RATES) {
1874 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
770e4b73 1875 0xff0 | erp->basic_rates);
02044643
HS		 1876 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1877 }
f4450616 1878
02044643
HS		 1879 if (changed & BSS_CHANGED_ERP_SLOT) {
1880 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1881 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1882 erp->slot_time);
1883 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1884
02044643
HS		 1885 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1886 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1887 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1888 }
f4450616 1889
02044643
HS		 1890 if (changed & BSS_CHANGED_BEACON_INT) {
1891 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1892 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1893 erp->beacon_int * 16);
1894 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1895 }
87c1915d
HS		 1896
1897 if (changed & BSS_CHANGED_HT)
1898 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1899}
1900EXPORT_SYMBOL_GPL(rt2800_config_erp);
1901
872834df
GW		 1902static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1903{
1904 u32 reg;
1905 u16 eeprom;
1906 u8 led_ctrl, led_g_mode, led_r_mode;
1907
1908 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
57fbcce3 1909 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
872834df
GW		 1910 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1911 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1912 } else {
1913 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1914 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1915 }
1916 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1917
1918 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1919 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1920 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1921 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1922 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1923 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1924 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1925 if (led_ctrl == 0 || led_ctrl > 0x40) {
1926 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1927 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1928 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1929 } else {
1930 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1931 (led_g_mode << 2) | led_r_mode, 1);
1932 }
1933 }
1934}
1935
d96aa640
RJH		 1936static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1937 enum antenna ant)
1938{
1939 u32 reg;
1940 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1941 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1942
1943 if (rt2x00_is_pci(rt2x00dev)) {
1944 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1945 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1946 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1947 } else if (rt2x00_is_usb(rt2x00dev))
1948 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1949 eesk_pin, 0);
1950
99bdf51a
GW		 1951 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1952 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1953 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1954 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1955}
1956
f4450616
BZ		 1957void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1958{
1959 u8 r1;
1960 u8 r3;
d96aa640 1961 u16 eeprom;
f4450616
BZ		 1962
1963 rt2800_bbp_read(rt2x00dev, 1, &r1);
1964 rt2800_bbp_read(rt2x00dev, 3, &r3);
1965
872834df 1966 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1967 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1968 rt2800_config_3572bt_ant(rt2x00dev);
1969
f4450616
BZ		 1970 /*
1971 * Configure the TX antenna.
1972 */
d96aa640 1973 switch (ant->tx_chain_num) {
f4450616
BZ		 1974 case 1:
1975 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1976 break;
1977 case 2:
872834df 1978 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1979 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1980 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1981 else
1982 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1983 break;
1984 case 3:
4788ac1e 1985 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1986 break;
1987 }
1988
1989 /*
1990 * Configure the RX antenna.
1991 */
d96aa640 1992 switch (ant->rx_chain_num) {
f4450616 1993 case 1:
d96aa640
RJH		 1994 if (rt2x00_rt(rt2x00dev, RT3070) ||
1995 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1996 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1997 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1998 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1999 EEPROM_NIC_CONF1, &eeprom);
2000 if (rt2x00_get_field16(eeprom,
2001 EEPROM_NIC_CONF1_ANT_DIVERSITY))
2002 rt2800_set_ant_diversity(rt2x00dev,
2003 rt2x00dev->default_ant.rx);
2004 }
f4450616
BZ		 2005 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2006 break;
2007 case 2:
872834df 2008 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 2009 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2010 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2011 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
57fbcce3 2012 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
872834df
GW		 2013 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2014 } else {
2015 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2016 }
f4450616
BZ		 2017 break;
2018 case 3:
2019 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2020 break;
2021 }
2022
2023 rt2800_bbp_write(rt2x00dev, 3, r3);
2024 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 2025
2026 if (rt2x00_rt(rt2x00dev, RT3593)) {
2027 if (ant->rx_chain_num == 1)
2028 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2029 else
2030 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2031 }
f4450616
BZ		 2032}
2033EXPORT_SYMBOL_GPL(rt2800_config_ant);
2034
2035static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2036 struct rt2x00lib_conf *libconf)
2037{
2038 u16 eeprom;
2039 short lna_gain;
2040
2041 if (libconf->rf.channel <= 14) {
3e38d3da 2042 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 2043 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2044 } else if (libconf->rf.channel <= 64) {
3e38d3da 2045 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 2046 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2047 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 2048 if (rt2x00_rt(rt2x00dev, RT3593)) {
2049 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
2050 lna_gain = rt2x00_get_field16(eeprom,
2051 EEPROM_EXT_LNA2_A1);
2052 } else {
2053 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
2054 lna_gain = rt2x00_get_field16(eeprom,
2055 EEPROM_RSSI_BG2_LNA_A1);
2056 }
f4450616 2057 } else {
f36bb0ca
GJ		 2058 if (rt2x00_rt(rt2x00dev, RT3593)) {
2059 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
2060 lna_gain = rt2x00_get_field16(eeprom,
2061 EEPROM_EXT_LNA2_A2);
2062 } else {
2063 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
2064 lna_gain = rt2x00_get_field16(eeprom,
2065 EEPROM_RSSI_A2_LNA_A2);
2066 }
f4450616
BZ		 2067 }
2068
2069 rt2x00dev->lna_gain = lna_gain;
2070}
2071
5c4412e0
DG		 2072static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2073{
2074 return clk_get_rate(rt2x00dev->clk) == 20000000;
2075}
2076
3f1b8739
GJ		 2077#define FREQ_OFFSET_BOUND 0x5f
2078
88452541 2079static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
3f1b8739
GJ		 2080{
2081 u8 freq_offset, prev_freq_offset;
2082 u8 rfcsr, prev_rfcsr;
2083
2084 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2085 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2086
16d571bb 2087 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3f1b8739
GJ		 2088 prev_rfcsr = rfcsr;
2089
2090 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2091 if (rfcsr == prev_rfcsr)
2092 return;
2093
2094 if (rt2x00_is_usb(rt2x00dev)) {
2095 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2096 freq_offset, prev_rfcsr);
2097 return;
2098 }
2099
2100 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2101 while (prev_freq_offset != freq_offset) {
2102 if (prev_freq_offset < freq_offset)
2103 prev_freq_offset++;
2104 else
2105 prev_freq_offset--;
2106
2107 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2108 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2109
2110 usleep_range(1000, 1500);
2111 }
2112}
2113
06855ef4
GW		 2114static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2115 struct ieee80211_conf *conf,
2116 struct rf_channel *rf,
2117 struct channel_info *info)
f4450616
BZ		 2118{
2119 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2120
d96aa640 2121 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 2122 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2123
d96aa640 2124 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 2125 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2126 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 2127 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 2128 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2129
2130 if (rf->channel > 14) {
2131 /*
2132 * When TX power is below 0, we should increase it by 7 to
25985edc 2133 * make it a positive value (Minimum value is -7).
f4450616
BZ		 2134 * However this means that values between 0 and 7 have
2135 * double meaning, and we should set a 7DBm boost flag.
2136 */
2137 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 2138 (info->default_power1 >= 0));
f4450616 2139
8d1331b3
ID		 2140 if (info->default_power1 < 0)
2141 info->default_power1 += 7;
f4450616 2142
8d1331b3 2143 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 2144
2145 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 2146 (info->default_power2 >= 0));
f4450616 2147
8d1331b3
ID		 2148 if (info->default_power2 < 0)
2149 info->default_power2 += 7;
f4450616 2150
8d1331b3 2151 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 2152 } else {
8d1331b3
ID		 2153 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2154 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 2155 }
2156
2157 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2158
2159 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2160 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2161 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2162 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2163
2164 udelay(200);
2165
2166 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2167 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2168 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2169 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2170
2171 udelay(200);
2172
2173 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2174 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2175 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2176 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2177}
2178
06855ef4
GW		 2179static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2180 struct ieee80211_conf *conf,
2181 struct rf_channel *rf,
2182 struct channel_info *info)
f4450616 2183{
3a1c0128 2184 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2185 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2186
2187 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab 2188
16d571bb 2189 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
7f4666ab
SG		 2190 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2191 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616 2192
16d571bb 2193 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
fab799c3 2194 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2195 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2196
16d571bb 2197 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
8d1331b3 2198 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2199 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2200
16d571bb 2201 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
8d1331b3 2202 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2203 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197 2204
16d571bb 2205 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
e3bab197 2206 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2207 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2208 rt2x00dev->default_ant.rx_chain_num <= 1);
2209 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2210 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2211 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2212 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2213 rt2x00dev->default_ant.tx_chain_num <= 1);
2214 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2215 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2216 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2217
16d571bb 2218 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
f4450616
BZ		 2219 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2220 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2221
f1f12f98
SG		 2222 if (rt2x00_rt(rt2x00dev, RT3390)) {
2223 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2224 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2225 } else {
3a1c0128
GW		 2226 if (conf_is_ht40(conf)) {
2227 calib_tx = drv_data->calibration_bw40;
2228 calib_rx = drv_data->calibration_bw40;
2229 } else {
2230 calib_tx = drv_data->calibration_bw20;
2231 calib_rx = drv_data->calibration_bw20;
2232 }
f1f12f98
SG		 2233 }
2234
16d571bb 2235 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
f1f12f98
SG		 2236 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2237 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2238
16d571bb 2239 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
f1f12f98
SG		 2240 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2241 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2242
16d571bb 2243 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
f4450616 2244 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2245 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643 2246
16d571bb 2247 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3e0c7643
SG		 2248 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2249 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
31369c32
SG		 2250
2251 usleep_range(1000, 1500);
2252
3e0c7643
SG		 2253 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2254 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2255}
2256
872834df
GW		 2257static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2258 struct ieee80211_conf *conf,
2259 struct rf_channel *rf,
2260 struct channel_info *info)
2261{
3a1c0128 2262 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2263 u8 rfcsr;
2264 u32 reg;
2265
2266 if (rf->channel <= 14) {
5d137dff
GW		 2267 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2268 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2269 } else {
2270 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2271 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2272 }
2273
2274 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2275 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2276
16d571bb 2277 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
872834df
GW		 2278 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2279 if (rf->channel <= 14)
2280 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2281 else
2282 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2283 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2284
16d571bb 2285 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
872834df
GW		 2286 if (rf->channel <= 14)
2287 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2288 else
2289 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2290 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2291
16d571bb 2292 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
872834df
GW		 2293 if (rf->channel <= 14) {
2294 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2295 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2296 info->default_power1);
872834df
GW		 2297 } else {
2298 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2299 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2300 (info->default_power1 & 0x3) |
2301 ((info->default_power1 & 0xC) << 1));
2302 }
2303 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2304
16d571bb 2305 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
872834df
GW		 2306 if (rf->channel <= 14) {
2307 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2308 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2309 info->default_power2);
872834df
GW		 2310 } else {
2311 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2312 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2313 (info->default_power2 & 0x3) |
2314 ((info->default_power2 & 0xC) << 1));
2315 }
2316 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2317
16d571bb 2318 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
872834df
GW		 2319 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2320 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2321 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2322 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2323 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2324 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2325 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2326 if (rf->channel <= 14) {
2327 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2328 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2329 }
2330 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2331 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2332 } else {
2333 switch (rt2x00dev->default_ant.tx_chain_num) {
2334 case 1:
2335 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2336 case 2:
2337 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2338 break;
2339 }
2340
2341 switch (rt2x00dev->default_ant.rx_chain_num) {
2342 case 1:
2343 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2344 case 2:
2345 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2346 break;
2347 }
2348 }
2349 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2350
16d571bb 2351 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
872834df
GW		 2352 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2353 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2354
3a1c0128
GW		 2355 if (conf_is_ht40(conf)) {
2356 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2357 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2358 } else {
2359 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2360 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2361 }
872834df
GW		 2362
2363 if (rf->channel <= 14) {
2364 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2365 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2366 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2367 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2368 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2369 rfcsr = 0x4c;
2370 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2371 drv_data->txmixer_gain_24g);
2372 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2373 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2374 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2375 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2376 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2377 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2378 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2379 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2380 } else {
16d571bb 2381 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
58b8ae14
GW		 2382 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2383 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2384 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2385 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2386 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2387 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2388 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2389 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2390 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2391 rfcsr = 0x7a;
2392 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2393 drv_data->txmixer_gain_5g);
2394 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2395 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2396 if (rf->channel <= 64) {
2397 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2398 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2399 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2400 } else if (rf->channel <= 128) {
2401 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2402 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2403 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2404 } else {
2405 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2406 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2407 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2408 }
2409 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2410 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2411 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2412 }
2413
99bdf51a
GW		 2414 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2415 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2416 if (rf->channel <= 14)
99bdf51a 2417 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2418 else
99bdf51a
GW		 2419 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2420 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df 2421
16d571bb 2422 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
872834df
GW		 2423 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2424 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2425}
60687ba7 2426
f42b0465
GJ		 2427static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2428 struct ieee80211_conf *conf,
2429 struct rf_channel *rf,
2430 struct channel_info *info)
2431{
2432 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2433 u8 txrx_agc_fc;
2434 u8 txrx_h20m;
2435 u8 rfcsr;
2436 u8 bbp;
2437 const bool txbf_enabled = false; /* TODO */
2438
2439 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2440 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2441 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2442 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2443 rt2800_bbp_write(rt2x00dev, 109, bbp);
2444
2445 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2446 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2447 rt2800_bbp_write(rt2x00dev, 110, bbp);
2448
2449 if (rf->channel <= 14) {
2450 /* Restore BBP 25 & 26 for 2.4 GHz */
2451 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2452 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2453 } else {
2454 /* Hard code BBP 25 & 26 for 5GHz */
2455
2456 /* Enable IQ Phase correction */
2457 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2458 /* Setup IQ Phase correction value */
2459 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2460 }
2461
2462 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2463 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2464
16d571bb 2465 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
f42b0465
GJ		 2466 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2467 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2468
16d571bb 2469 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
f42b0465
GJ		 2470 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2471 if (rf->channel <= 14)
2472 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2473 else
2474 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2475 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2476
16d571bb 2477 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
f42b0465
GJ		 2478 if (rf->channel <= 14) {
2479 rfcsr = 0;
2480 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2481 info->default_power1 & 0x1f);
2482 } else {
2483 if (rt2x00_is_usb(rt2x00dev))
2484 rfcsr = 0x40;
2485
2486 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2487 ((info->default_power1 & 0x18) << 1) |
2488 (info->default_power1 & 7));
2489 }
2490 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2491
16d571bb 2492 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
f42b0465
GJ		 2493 if (rf->channel <= 14) {
2494 rfcsr = 0;
2495 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2496 info->default_power2 & 0x1f);
2497 } else {
2498 if (rt2x00_is_usb(rt2x00dev))
2499 rfcsr = 0x40;
2500
2501 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2502 ((info->default_power2 & 0x18) << 1) |
2503 (info->default_power2 & 7));
2504 }
2505 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2506
16d571bb 2507 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
f42b0465
GJ		 2508 if (rf->channel <= 14) {
2509 rfcsr = 0;
2510 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2511 info->default_power3 & 0x1f);
2512 } else {
2513 if (rt2x00_is_usb(rt2x00dev))
2514 rfcsr = 0x40;
2515
2516 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2517 ((info->default_power3 & 0x18) << 1) |
2518 (info->default_power3 & 7));
2519 }
2520 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2521
16d571bb 2522 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
f42b0465
GJ		 2523 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2524 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2525 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2526 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2527 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2528 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2529 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2530 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2531
2532 switch (rt2x00dev->default_ant.tx_chain_num) {
2533 case 3:
2534 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2535 /* fallthrough */
2536 case 2:
2537 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2538 /* fallthrough */
2539 case 1:
2540 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2541 break;
2542 }
2543
2544 switch (rt2x00dev->default_ant.rx_chain_num) {
2545 case 3:
2546 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2547 /* fallthrough */
2548 case 2:
2549 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2550 /* fallthrough */
2551 case 1:
2552 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2553 break;
2554 }
2555 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2556
88452541 2557 rt2800_freq_cal_mode1(rt2x00dev);
f42b0465
GJ		 2558
2559 if (conf_is_ht40(conf)) {
2560 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2561 RFCSR24_TX_AGC_FC);
2562 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2563 RFCSR24_TX_H20M);
2564 } else {
2565 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2566 RFCSR24_TX_AGC_FC);
2567 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2568 RFCSR24_TX_H20M);
2569 }
2570
2571 /* NOTE: the reference driver does not writes the new value
2572 * back to RFCSR 32
2573 */
16d571bb 2574 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
f42b0465
GJ		 2575 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2576
2577 if (rf->channel <= 14)
2578 rfcsr = 0xa0;
2579 else
2580 rfcsr = 0x80;
2581 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2582
16d571bb 2583 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
f42b0465
GJ		 2584 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2585 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2586 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2587
2588 /* Band selection */
16d571bb 2589 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
f42b0465
GJ		 2590 if (rf->channel <= 14)
2591 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2592 else
2593 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2594 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2595
16d571bb 2596 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
f42b0465
GJ		 2597 if (rf->channel <= 14)
2598 rfcsr = 0x3c;
2599 else
2600 rfcsr = 0x20;
2601 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2602
16d571bb 2603 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
f42b0465
GJ		 2604 if (rf->channel <= 14)
2605 rfcsr = 0x1a;
2606 else
2607 rfcsr = 0x12;
2608 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2609
16d571bb 2610 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
f42b0465
GJ		 2611 if (rf->channel >= 1 && rf->channel <= 14)
2612 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2613 else if (rf->channel >= 36 && rf->channel <= 64)
2614 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2615 else if (rf->channel >= 100 && rf->channel <= 128)
2616 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2617 else
2618 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2619 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2620
16d571bb 2621 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
f42b0465
GJ		 2622 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2623 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2624
2625 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2626
2627 if (rf->channel <= 14) {
2628 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2629 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2630 } else {
2631 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2632 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2633 }
2634
16d571bb 2635 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
f42b0465
GJ		 2636 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2637 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2638
16d571bb 2639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
f42b0465
GJ		 2640 if (rf->channel <= 14) {
2641 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2642 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2643 } else {
2644 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2645 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2646 }
2647 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2648
16d571bb 2649 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
f42b0465
GJ		 2650 if (rf->channel <= 14)
2651 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2652 else
2653 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2654
2655 if (txbf_enabled)
2656 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2657
2658 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2659
16d571bb 2660 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
f42b0465
GJ		 2661 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2662 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2663
16d571bb 2664 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
f42b0465
GJ		 2665 if (rf->channel <= 14)
2666 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2667 else
2668 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2669 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2670
2671 if (rf->channel <= 14) {
2672 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2673 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2674 } else {
2675 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2676 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2677 }
2678
2679 /* Initiate VCO calibration */
16d571bb 2680 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
f42b0465
GJ		 2681 if (rf->channel <= 14) {
2682 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2683 } else {
2684 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2685 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2686 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2687 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2688 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2689 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2690 }
2691 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2692
2693 if (rf->channel >= 1 && rf->channel <= 14) {
2694 rfcsr = 0x23;
2695 if (txbf_enabled)
2696 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2697 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2698
2699 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2700 } else if (rf->channel >= 36 && rf->channel <= 64) {
2701 rfcsr = 0x36;
2702 if (txbf_enabled)
2703 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2704 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2705
2706 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2707 } else if (rf->channel >= 100 && rf->channel <= 128) {
2708 rfcsr = 0x32;
2709 if (txbf_enabled)
2710 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2711 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2712
2713 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2714 } else {
2715 rfcsr = 0x30;
2716 if (txbf_enabled)
2717 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2718 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2719
2720 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2721 }
2722}
2723
7573cb5b 2724#define POWER_BOUND 0x27
8f821098 2725#define POWER_BOUND_5G 0x2b
0c9e5fb9 2726
a89534ed
WH		 2727static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2728 struct ieee80211_conf *conf,
2729 struct rf_channel *rf,
2730 struct channel_info *info)
2731{
2732 u8 rfcsr;
2733
2734 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2735 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
16d571bb 2736 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
a89534ed
WH		 2737 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2738 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2739
16d571bb 2740 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
7573cb5b
SG		 2741 if (info->default_power1 > POWER_BOUND)
2742 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2743 else
2744 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2745 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2746
88452541 2747 rt2800_freq_cal_mode1(rt2x00dev);
a89534ed
WH		 2748
2749 if (rf->channel <= 14) {
2750 if (rf->channel == 6)
2751 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2752 else
2753 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2754
2755 if (rf->channel >= 1 && rf->channel <= 6)
2756 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2757 else if (rf->channel >= 7 && rf->channel <= 11)
2758 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2759 else if (rf->channel >= 12 && rf->channel <= 14)
2760 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2761 }
2762}
2763
03839951
DG		 2764static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2765 struct ieee80211_conf *conf,
2766 struct rf_channel *rf,
2767 struct channel_info *info)
2768{
2769 u8 rfcsr;
2770
2771 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2772 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2773
2774 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2775 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2776 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2777
2778 if (info->default_power1 > POWER_BOUND)
2779 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2780 else
2781 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2782
2783 if (info->default_power2 > POWER_BOUND)
2784 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2785 else
2786 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2787
88452541 2788 rt2800_freq_cal_mode1(rt2x00dev);
03839951 2789
16d571bb 2790 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
03839951
DG		 2791 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2792 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2793
2794 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2795 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2796 else
2797 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2798
2799 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2800 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2801 else
2802 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2803
2804 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2805 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2806
2807 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2808
2809 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2810}
2811
60687ba7 2812static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2813 struct ieee80211_conf *conf,
2814 struct rf_channel *rf,
2815 struct channel_info *info)
2816{
2817 u8 rfcsr;
adde5882
GJ		 2818
2819 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2820 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
16d571bb 2821 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
adde5882
GJ		 2822 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2823 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2824
16d571bb 2825 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
7573cb5b
SG		 2826 if (info->default_power1 > POWER_BOUND)
2827 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2828 else
2829 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2830 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2831
cff3d1f0 2832 if (rt2x00_rt(rt2x00dev, RT5392)) {
16d571bb 2833 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
6264995f 2834 if (info->default_power2 > POWER_BOUND)
7573cb5b 2835 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2836 else
2837 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2838 info->default_power2);
2839 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2840 }
2841
16d571bb 2842 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
cff3d1f0
ZL		 2843 if (rt2x00_rt(rt2x00dev, RT5392)) {
2844 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2845 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2846 }
adde5882
GJ		 2847 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2848 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2849 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2850 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2851 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2852
88452541 2853 rt2800_freq_cal_mode1(rt2x00dev);
adde5882 2854
adde5882
GJ		 2855 if (rf->channel <= 14) {
2856 int idx = rf->channel-1;
2857
c429dfef 2858 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2859 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2860 /* r55/r59 value array of channel 1~14 */
2861 static const char r55_bt_rev[] = {0x83, 0x83,
2862 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2863 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2864 static const char r59_bt_rev[] = {0x0e, 0x0e,
2865 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2866 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2867
2868 rt2800_rfcsr_write(rt2x00dev, 55,
2869 r55_bt_rev[idx]);
2870 rt2800_rfcsr_write(rt2x00dev, 59,
2871 r59_bt_rev[idx]);
2872 } else {
2873 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2874 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2875 0x88, 0x88, 0x86, 0x85, 0x84};
2876
2877 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2878 }
2879 } else {
2880 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2881 static const char r55_nonbt_rev[] = {0x23, 0x23,
2882 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2883 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2884 static const char r59_nonbt_rev[] = {0x07, 0x07,
2885 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2886 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2887
2888 rt2800_rfcsr_write(rt2x00dev, 55,
2889 r55_nonbt_rev[idx]);
2890 rt2800_rfcsr_write(rt2x00dev, 59,
2891 r59_nonbt_rev[idx]);
2ed71884 2892 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
41977e86
RY		 2893 rt2x00_rt(rt2x00dev, RT5392) ||
2894 rt2x00_rt(rt2x00dev, RT6352)) {
adde5882
GJ		 2895 static const char r59_non_bt[] = {0x8f, 0x8f,
2896 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2897 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2898
98e71f44
SV		 2899 rt2800_rfcsr_write(rt2x00dev, 59,
2900 r59_non_bt[idx]);
2901 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
2902 static const char r59_non_bt[] = {0x0b, 0x0b,
2903 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
2904 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
2905
adde5882
GJ		 2906 rt2800_rfcsr_write(rt2x00dev, 59,
2907 r59_non_bt[idx]);
2908 }
2909 }
2910 }
60687ba7
RST		 2911}
2912
8f821098
SG		 2913static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2914 struct ieee80211_conf *conf,
2915 struct rf_channel *rf,
2916 struct channel_info *info)
2917{
2918 u8 rfcsr, ep_reg;
d5ae7a6b 2919 u32 reg;
8f821098
SG		 2920 int power_bound;
2921
2922 /* TODO */
2923 const bool is_11b = false;
2924 const bool is_type_ep = false;
2925
d5ae7a6b
SG		 2926 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2927 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2928 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2929 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2930
2931 /* Order of values on rf_channel entry: N, K, mod, R */
2932 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2933
16d571bb 2934 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
8f821098
SG		 2935 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2936 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2937 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2938 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2939
16d571bb 2940 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
8f821098
SG		 2941 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2942 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2943 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2944
2945 if (rf->channel <= 14) {
2946 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2947 /* FIXME: RF11 owerwrite ? */
2948 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2949 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2950 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2951 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2952 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2953 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2954 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2955 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2956 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2957 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2958 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2959 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2960 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2961 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2962 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2963 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2964 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2965 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2966 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2967 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2968 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2969 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2970 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2971 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2972 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2973 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2974 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2975 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2976
2977 /* TODO RF27 <- tssi */
2978
2979 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2980 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2981 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2982
2983 if (is_11b) {
2984 /* CCK */
2985 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2986 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2987 if (is_type_ep)
2988 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2989 else
2990 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2991 } else {
2992 /* OFDM */
2993 if (is_type_ep)
2994 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2995 else
2996 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2997 }
2998
2999 power_bound = POWER_BOUND;
3000 ep_reg = 0x2;
3001 } else {
3002 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3003 /* FIMXE: RF11 overwrite */
3004 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3005 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3006 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3007 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3008 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3009 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3010 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3011 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3012 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3013 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3014 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3015 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3016 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3017 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3018
3019 /* TODO RF27 <- tssi */
3020
3021 if (rf->channel >= 36 && rf->channel <= 64) {
3022
3023 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3024 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3025 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3026 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3027 if (rf->channel <= 50)
3028 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3029 else if (rf->channel >= 52)
3030 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3031 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3032 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3033 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3034 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3035 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3036 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3037 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3038 if (rf->channel <= 50) {
3039 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3040 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3041 } else if (rf->channel >= 52) {
3042 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3043 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3044 }
3045
3046 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3047 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3048 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3049
3050 } else if (rf->channel >= 100 && rf->channel <= 165) {
3051
3052 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3053 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3054 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3055 if (rf->channel <= 153) {
3056 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3057 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3058 } else if (rf->channel >= 155) {
3059 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3060 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3061 }
3062 if (rf->channel <= 138) {
3063 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3064 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3065 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3066 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3067 } else if (rf->channel >= 140) {
3068 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3069 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3070 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3071 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3072 }
3073 if (rf->channel <= 124)
3074 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3075 else if (rf->channel >= 126)
3076 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3077 if (rf->channel <= 138)
3078 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3079 else if (rf->channel >= 140)
3080 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3081 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3082 if (rf->channel <= 138)
3083 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3084 else if (rf->channel >= 140)
3085 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3086 if (rf->channel <= 128)
3087 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3088 else if (rf->channel >= 130)
3089 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3090 if (rf->channel <= 116)
3091 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3092 else if (rf->channel >= 118)
3093 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3094 if (rf->channel <= 138)
3095 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3096 else if (rf->channel >= 140)
3097 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3098 if (rf->channel <= 116)
3099 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3100 else if (rf->channel >= 118)
3101 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3102 }
3103
3104 power_bound = POWER_BOUND_5G;
3105 ep_reg = 0x3;
3106 }
3107
16d571bb 3108 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
8f821098
SG		 3109 if (info->default_power1 > power_bound)
3110 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3111 else
3112 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3113 if (is_type_ep)
3114 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3115 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3116
16d571bb 3117 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
0847beb2 3118 if (info->default_power2 > power_bound)
8f821098
SG		 3119 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3120 else
3121 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3122 if (is_type_ep)
3123 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3124 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3125
16d571bb 3126 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8f821098
SG		 3127 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3128 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3129
3130 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3131 rt2x00dev->default_ant.tx_chain_num >= 1);
3132 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3133 rt2x00dev->default_ant.tx_chain_num == 2);
3134 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3135
3136 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3137 rt2x00dev->default_ant.rx_chain_num >= 1);
3138 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3139 rt2x00dev->default_ant.rx_chain_num == 2);
3140 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3141
3142 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3143 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3144
3145 if (conf_is_ht40(conf))
3146 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3147 else
3148 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3149
3150 if (!is_11b) {
3151 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3152 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3153 }
3154
3155 /* TODO proper frequency adjustment */
88452541 3156 rt2800_freq_cal_mode1(rt2x00dev);
8f821098
SG		 3157
3158 /* TODO merge with others */
16d571bb 3159 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
8f821098
SG		 3160 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3161 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 3162
3163 /* BBP settings */
3164 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3165 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3166 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3167
3168 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3169 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3170 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3171 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3172
3173 /* GLRT band configuration */
3174 rt2800_bbp_write(rt2x00dev, 195, 128);
3175 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3176 rt2800_bbp_write(rt2x00dev, 195, 129);
3177 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3178 rt2800_bbp_write(rt2x00dev, 195, 130);
3179 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3180 rt2800_bbp_write(rt2x00dev, 195, 131);
3181 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3182 rt2800_bbp_write(rt2x00dev, 195, 133);
3183 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3184 rt2800_bbp_write(rt2x00dev, 195, 124);
3185 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3186}
3187
41977e86
RY		 3188static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3189 struct ieee80211_conf *conf,
3190 struct rf_channel *rf,
3191 struct channel_info *info)
3192{
3193 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3194 u8 rx_agc_fc, tx_agc_fc;
3195 u8 rfcsr;
3196
3197 /* Frequeny plan setting */
3198 /* Rdiv setting (set 0x03 if Xtal==20)
3199 * R13[1:0]
3200 */
16d571bb 3201 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
41977e86
RY		 3202 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3203 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3204 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3205
3206 /* N setting
3207 * R20[7:0] in rf->rf1
3208 * R21[0] always 0
3209 */
16d571bb 3210 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
41977e86
RY		 3211 rfcsr = (rf->rf1 & 0x00ff);
3212 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3213
16d571bb 3214 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
41977e86
RY		 3215 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3216 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3217
3218 /* K setting (always 0)
3219 * R16[3:0] (RF PLL freq selection)
3220 */
16d571bb 3221 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
41977e86
RY		 3222 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3223 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3224
3225 /* D setting (always 0)
3226 * R22[2:0] (D=15, R22[2:0]=<111>)
3227 */
16d571bb 3228 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
41977e86
RY		 3229 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3230 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3231
3232 /* Ksd setting
3233 * Ksd: R17<7:0> in rf->rf2
3234 * R18<7:0> in rf->rf3
3235 * R19<1:0> in rf->rf4
3236 */
16d571bb 3237 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
41977e86
RY		 3238 rfcsr = rf->rf2;
3239 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3240
16d571bb 3241 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
41977e86
RY		 3242 rfcsr = rf->rf3;
3243 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3244
16d571bb 3245 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
41977e86
RY		 3246 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3247 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3248
3249 /* Default: XO=20MHz , SDM mode */
16d571bb 3250 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
41977e86
RY		 3251 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3252 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3253
16d571bb 3254 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
41977e86
RY		 3255 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3256 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3257
16d571bb 3258 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
41977e86
RY		 3259 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3260 rt2x00dev->default_ant.tx_chain_num != 1);
3261 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3262
16d571bb 3263 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
41977e86
RY		 3264 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3265 rt2x00dev->default_ant.tx_chain_num != 1);
3266 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3267 rt2x00dev->default_ant.rx_chain_num != 1);
3268 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3269
16d571bb 3270 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
41977e86
RY		 3271 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3272 rt2x00dev->default_ant.tx_chain_num != 1);
3273 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3274
3275 /* RF for DC Cal BW */
3276 if (conf_is_ht40(conf)) {
3277 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3278 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3279 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3280 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3281 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3282 } else {
3283 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3284 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3285 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3286 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3287 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3288 }
3289
3290 if (conf_is_ht40(conf)) {
3291 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3292 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3293 } else {
3294 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3295 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3296 }
3297
16d571bb 3298 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
41977e86
RY		 3299 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3300 conf_is_ht40(conf) && (rf->channel == 11));
3301 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3302
3303 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3304 if (conf_is_ht40(conf)) {
3305 rx_agc_fc = drv_data->rx_calibration_bw40;
3306 tx_agc_fc = drv_data->tx_calibration_bw40;
3307 } else {
3308 rx_agc_fc = drv_data->rx_calibration_bw20;
3309 tx_agc_fc = drv_data->tx_calibration_bw20;
3310 }
16d571bb 3311 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
41977e86
RY		 3312 rfcsr &= (~0x3F);
3313 rfcsr |= rx_agc_fc;
3314 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
16d571bb 3315 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
41977e86
RY		 3316 rfcsr &= (~0x3F);
3317 rfcsr |= rx_agc_fc;
3318 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
16d571bb 3319 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
41977e86
RY		 3320 rfcsr &= (~0x3F);
3321 rfcsr |= rx_agc_fc;
3322 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
16d571bb 3323 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
41977e86
RY		 3324 rfcsr &= (~0x3F);
3325 rfcsr |= rx_agc_fc;
3326 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3327
16d571bb 3328 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
41977e86
RY		 3329 rfcsr &= (~0x3F);
3330 rfcsr |= tx_agc_fc;
3331 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
16d571bb 3332 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
41977e86
RY		 3333 rfcsr &= (~0x3F);
3334 rfcsr |= tx_agc_fc;
3335 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
16d571bb 3336 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
41977e86
RY		 3337 rfcsr &= (~0x3F);
3338 rfcsr |= tx_agc_fc;
3339 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
16d571bb 3340 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
41977e86
RY		 3341 rfcsr &= (~0x3F);
3342 rfcsr |= tx_agc_fc;
3343 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3344 }
3345}
3346
3347static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3348 struct ieee80211_channel *chan,
3349 int power_level) {
3350 u16 eeprom, target_power, max_power;
3351 u32 mac_sys_ctrl, mac_status;
3352 u32 reg;
3353 u8 bbp;
3354 int i;
3355
3356 /* hardware unit is 0.5dBm, limited to 23.5dBm */
3357 power_level *= 2;
3358 if (power_level > 0x2f)
3359 power_level = 0x2f;
3360
3361 max_power = chan->max_power * 2;
3362 if (max_power > 0x2f)
3363 max_power = 0x2f;
3364
3365 rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, &reg);
3366 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3367 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3368 rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3369 rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3370
3371 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3372 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3373 /* init base power by eeprom target power */
3374 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_INIT,
3375 &target_power);
3376 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3377 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3378 }
3379 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3380
3381 rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
3382 rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3383 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3384
3385 /* Save MAC SYS CTRL registers */
3386 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
3387 /* Disable Tx/Rx */
3388 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3389 /* Check MAC Tx/Rx idle */
3390 for (i = 0; i < 10000; i++) {
3391 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG,
3392 &mac_status);
3393 if (mac_status & 0x3)
3394 usleep_range(50, 200);
3395 else
3396 break;
3397 }
3398
3399 if (i == 10000)
3400 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3401
3402 if (chan->center_freq > 2457) {
3403 rt2800_bbp_read(rt2x00dev, 30, &bbp);
3404 bbp = 0x40;
3405 rt2800_bbp_write(rt2x00dev, 30, bbp);
3406 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3407 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3408 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3409 else
3410 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3411 } else {
3412 rt2800_bbp_read(rt2x00dev, 30, &bbp);
3413 bbp = 0x1f;
3414 rt2800_bbp_write(rt2x00dev, 30, bbp);
3415 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3416 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3417 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3418 else
3419 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3420 }
3421 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
2031bada
DG		 3422
3423 rt2800_vco_calibration(rt2x00dev);
41977e86
RY		 3424}
3425
5bc2dd06
SG		 3426static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3427 const unsigned int word,
3428 const u8 value)
3429{
3430 u8 chain, reg;
3431
3432 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3433 rt2800_bbp_read(rt2x00dev, 27, &reg);
3434 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3435 rt2800_bbp_write(rt2x00dev, 27, reg);
3436
3437 rt2800_bbp_write(rt2x00dev, word, value);
3438 }
3439}
3440
8756130b
SG		 3441static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3442{
3443 u8 cal;
3444
415e3f2f 3445 /* TX0 IQ Gain */
8756130b 3446 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3447 if (channel <= 14)
3448 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3449 else if (channel >= 36 && channel <= 64)
3450 cal = rt2x00_eeprom_byte(rt2x00dev,
3451 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3452 else if (channel >= 100 && channel <= 138)
3453 cal = rt2x00_eeprom_byte(rt2x00dev,
3454 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3455 else if (channel >= 140 && channel <= 165)
3456 cal = rt2x00_eeprom_byte(rt2x00dev,
3457 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3458 else
3459 cal = 0;
8756130b
SG		 3460 rt2800_bbp_write(rt2x00dev, 159, cal);
3461
415e3f2f 3462 /* TX0 IQ Phase */
8756130b 3463 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3464 if (channel <= 14)
3465 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3466 else if (channel >= 36 && channel <= 64)
3467 cal = rt2x00_eeprom_byte(rt2x00dev,
3468 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3469 else if (channel >= 100 && channel <= 138)
3470 cal = rt2x00_eeprom_byte(rt2x00dev,
3471 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3472 else if (channel >= 140 && channel <= 165)
3473 cal = rt2x00_eeprom_byte(rt2x00dev,
3474 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3475 else
3476 cal = 0;
8756130b
SG		 3477 rt2800_bbp_write(rt2x00dev, 159, cal);
3478
415e3f2f 3479 /* TX1 IQ Gain */
8756130b 3480 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3481 if (channel <= 14)
3482 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3483 else if (channel >= 36 && channel <= 64)
3484 cal = rt2x00_eeprom_byte(rt2x00dev,
3485 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3486 else if (channel >= 100 && channel <= 138)
3487 cal = rt2x00_eeprom_byte(rt2x00dev,
3488 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3489 else if (channel >= 140 && channel <= 165)
3490 cal = rt2x00_eeprom_byte(rt2x00dev,
3491 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3492 else
3493 cal = 0;
8756130b
SG		 3494 rt2800_bbp_write(rt2x00dev, 159, cal);
3495
415e3f2f 3496 /* TX1 IQ Phase */
8756130b 3497 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3498 if (channel <= 14)
3499 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3500 else if (channel >= 36 && channel <= 64)
3501 cal = rt2x00_eeprom_byte(rt2x00dev,
3502 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3503 else if (channel >= 100 && channel <= 138)
3504 cal = rt2x00_eeprom_byte(rt2x00dev,
3505 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3506 else if (channel >= 140 && channel <= 165)
3507 cal = rt2x00_eeprom_byte(rt2x00dev,
3508 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3509 else
3510 cal = 0;
8756130b
SG		 3511 rt2800_bbp_write(rt2x00dev, 159, cal);
3512
415e3f2f
SG		 3513 /* FIXME: possible RX0, RX1 callibration ? */
3514
8756130b
SG		 3515 /* RF IQ compensation control */
3516 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3517 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3518 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3519
3520 /* RF IQ imbalance compensation control */
3521 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3522 cal = rt2x00_eeprom_byte(rt2x00dev,
3523 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3524 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3525}
3526
97aa03f1
GJ		 3527static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3528 unsigned int channel,
3529 char txpower)
3530{
fc739cfe
GJ		 3531 if (rt2x00_rt(rt2x00dev, RT3593))
3532 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3533
97aa03f1
GJ		 3534 if (channel <= 14)
3535 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3536
3537 if (rt2x00_rt(rt2x00dev, RT3593))
3538 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3539 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3540 else
3541 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3542}
3543
f4450616
BZ		 3544static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3545 struct ieee80211_conf *conf,
3546 struct rf_channel *rf,
3547 struct channel_info *info)
3548{
3549 u32 reg;
41977e86 3550 u32 tx_pin;
a89534ed 3551 u8 bbp, rfcsr;
f4450616 3552
97aa03f1
GJ		 3553 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3554 info->default_power1);
3555 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3556 info->default_power2);
c0a14369
GJ		 3557 if (rt2x00dev->default_ant.tx_chain_num > 2)
3558 info->default_power3 =
3559 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3560 info->default_power3);
46323e11 3561
5aa57015
GW		 3562 switch (rt2x00dev->chip.rf) {
3563 case RF2020:
3564 case RF3020:
3565 case RF3021:
3566 case RF3022:
3567 case RF3320:
06855ef4 3568 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3569 break;
3570 case RF3052:
872834df 3571 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3572 break;
f42b0465
GJ		 3573 case RF3053:
3574 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3575 break;
a89534ed
WH		 3576 case RF3290:
3577 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3578 break;
03839951
DG		 3579 case RF3322:
3580 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3581 break;
3b9b74ba 3582 case RF3070:
98e71f44 3583 case RF5350:
ccf91bd6 3584 case RF5360:
ac0372ab 3585 case RF5362:
5aa57015 3586 case RF5370:
2ed71884 3587 case RF5372:
5aa57015 3588 case RF5390:
cff3d1f0 3589 case RF5392:
adde5882 3590 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3591 break;
8f821098
SG		 3592 case RF5592:
3593 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3594 break;
41977e86
RY		 3595 case RF7620:
3596 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
3597 break;
5aa57015 3598 default:
06855ef4 3599 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3600 }
f4450616 3601
3b9b74ba
SG		 3602 if (rt2x00_rf(rt2x00dev, RF3070) ||
3603 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3604 rt2x00_rf(rt2x00dev, RF3322) ||
98e71f44 3605 rt2x00_rf(rt2x00dev, RF5350) ||
a89534ed 3606 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3607 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3608 rt2x00_rf(rt2x00dev, RF5370) ||
3609 rt2x00_rf(rt2x00dev, RF5372) ||
3610 rt2x00_rf(rt2x00dev, RF5390) ||
3611 rt2x00_rf(rt2x00dev, RF5392)) {
16d571bb 3612 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
e974f3ac
SV		 3613 if (rt2x00_rf(rt2x00dev, RF3322)) {
3614 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
3615 conf_is_ht40(conf));
3616 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
3617 conf_is_ht40(conf));
3618 } else {
3619 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
3620 conf_is_ht40(conf));
3621 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
3622 conf_is_ht40(conf));
3623 }
a89534ed
WH		 3624 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3625
16d571bb 3626 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
d6d82020 3627 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3628 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3629 }
3630
f4450616
BZ		 3631 /*
3632 * Change BBP settings
3633 */
dab38e7d 3634
03839951 3635 if (rt2x00_rt(rt2x00dev, RT3352)) {
dab38e7d
DG		 3636 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3637 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3638 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3639
03839951 3640 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3641 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3642 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3643 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
dab38e7d
DG		 3644 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3645 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
f42b0465
GJ		 3646 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3647 if (rf->channel > 14) {
3648 /* Disable CCK Packet detection on 5GHz */
3649 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3650 } else {
3651 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3652 }
3653
3654 if (conf_is_ht40(conf))
3655 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3656 else
3657 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3658
3659 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3660 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3661 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3662 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3663 } else {
3664 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3665 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3666 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3667 rt2800_bbp_write(rt2x00dev, 86, 0);
3668 }
f4450616
BZ		 3669
3670 if (rf->channel <= 14) {
2ed71884 3671 if (!rt2x00_rt(rt2x00dev, RT5390) &&
41977e86
RY		 3672 !rt2x00_rt(rt2x00dev, RT5392) &&
3673 !rt2x00_rt(rt2x00dev, RT6352)) {
c429dfef 3674 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3675 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3676 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3677 } else {
f42b0465
GJ		 3678 if (rt2x00_rt(rt2x00dev, RT3593))
3679 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3680 else
3681 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3682 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3683 }
f42b0465
GJ		 3684 if (rt2x00_rt(rt2x00dev, RT3593))
3685 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3686 }
f42b0465 3687
f4450616 3688 } else {
872834df
GW		 3689 if (rt2x00_rt(rt2x00dev, RT3572))
3690 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3691 else if (rt2x00_rt(rt2x00dev, RT3593))
3692 rt2800_bbp_write(rt2x00dev, 82, 0x82);
41977e86 3693 else if (!rt2x00_rt(rt2x00dev, RT6352))
872834df 3694 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3695
f42b0465
GJ		 3696 if (rt2x00_rt(rt2x00dev, RT3593))
3697 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3698
c429dfef 3699 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3700 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3701 else
3702 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3703 }
3704
3705 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3706 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3707 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3708 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3709 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3710
872834df
GW		 3711 if (rt2x00_rt(rt2x00dev, RT3572))
3712 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3713
41977e86 3714 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
f4450616 3715
bb16d488
GJ		 3716 switch (rt2x00dev->default_ant.tx_chain_num) {
3717 case 3:
3718 /* Turn on tertiary PAs */
3719 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3720 rf->channel > 14);
3721 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3722 rf->channel <= 14);
3723 /* fall-through */
3724 case 2:
3725 /* Turn on secondary PAs */
65f31b5e
GW		 3726 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3727 rf->channel > 14);
3728 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3729 rf->channel <= 14);
bb16d488
GJ		 3730 /* fall-through */
3731 case 1:
3732 /* Turn on primary PAs */
3733 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3734 rf->channel > 14);
c429dfef 3735 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3736 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3737 else
3738 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3739 rf->channel <= 14);
3740 break;
f4450616
BZ		 3741 }
3742
bb16d488
GJ		 3743 switch (rt2x00dev->default_ant.rx_chain_num) {
3744 case 3:
3745 /* Turn on tertiary LNAs */
3746 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3747 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3748 /* fall-through */
3749 case 2:
3750 /* Turn on secondary LNAs */
f4450616
BZ		 3751 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3752 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3753 /* fall-through */
3754 case 1:
3755 /* Turn on primary LNAs */
3756 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3757 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3758 break;
f4450616
BZ		 3759 }
3760
f4450616
BZ		 3761 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3762 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
41977e86 3763 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
f4450616
BZ		 3764
3765 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3766
733aec6a 3767 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3768 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3769
733aec6a
GJ		 3770 /* AGC init */
3771 if (rf->channel <= 14)
3772 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3773 else
3774 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3775
3776 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3777 }
3778
f42b0465 3779 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3780 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3781
60751001
GJ		 3782 /* Band selection */
3783 if (rt2x00_is_usb(rt2x00dev) ||
3784 rt2x00_is_pcie(rt2x00dev)) {
3785 /* GPIO #8 controls all paths */
f42b0465
GJ		 3786 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3787 if (rf->channel <= 14)
3788 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3789 else
3790 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3791 }
f42b0465 3792
60751001
GJ		 3793 /* LNA PE control. */
3794 if (rt2x00_is_usb(rt2x00dev)) {
3795 /* GPIO #4 controls PE0 and PE1,
3796 * GPIO #7 controls PE2
3797 */
f42b0465
GJ		 3798 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3799 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3800
f42b0465
GJ		 3801 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3802 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3803 } else if (rt2x00_is_pcie(rt2x00dev)) {
3804 /* GPIO #4 controls PE0, PE1 and PE2 */
3805 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3806 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3807 }
3808
60751001
GJ		 3809 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3810
f42b0465
GJ		 3811 /* AGC init */
3812 if (rf->channel <= 14)
3813 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3814 else
3815 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3816
3817 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3818
3819 usleep_range(1000, 1500);
3820 }
3821
41977e86 3822 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
225a644a
DG		 3823 reg = 0x10;
3824 if (!conf_is_ht40(conf)) {
3825 if (rt2x00_rt(rt2x00dev, RT6352) &&
3826 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3827 reg |= 0x5;
3828 } else {
3829 reg |= 0xa;
3830 }
3831 }
6803141b 3832 rt2800_bbp_write(rt2x00dev, 195, 141);
225a644a 3833 rt2800_bbp_write(rt2x00dev, 196, reg);
6803141b 3834
8ba0ebf3 3835 /* AGC init */
225a644a
DG		 3836 if (rt2x00_rt(rt2x00dev, RT6352))
3837 reg = 0x04;
3838 else
3839 reg = rf->channel <= 14 ? 0x1c : 0x24;
3840
3841 reg += 2 * rt2x00dev->lna_gain;
8ba0ebf3
SG		 3842 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3843
8756130b 3844 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3845 }
3846
f4450616
BZ		 3847 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3848 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3849 rt2800_bbp_write(rt2x00dev, 4, bbp);
3850
3851 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3852 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3853 rt2800_bbp_write(rt2x00dev, 3, bbp);
3854
8d0c9b65 3855 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3856 if (conf_is_ht40(conf)) {
3857 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3858 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3859 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3860 } else {
3861 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3862 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3863 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3864 }
3865 }
3866
31369c32 3867 usleep_range(1000, 1500);
977206d7
HS		 3868
3869 /*
3870 * Clear channel statistic counters
3871 */
3872 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3873 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3874 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3875
3876 /*
3877 * Clear update flag
3878 */
98e71f44
SV		 3879 if (rt2x00_rt(rt2x00dev, RT3352) ||
3880 rt2x00_rt(rt2x00dev, RT5350)) {
03839951
DG		 3881 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3882 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3883 rt2800_bbp_write(rt2x00dev, 49, bbp);
3884 }
f4450616
BZ		 3885}
3886
9e33a355
HS		 3887static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3888{
3889 u8 tssi_bounds[9];
3890 u8 current_tssi;
3891 u16 eeprom;
3892 u8 step;
3893 int i;
3894
6e956da2
SG		 3895 /*
3896 * First check if temperature compensation is supported.
3897 */
3898 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3899 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3900 return 0;
3901
9e33a355
HS		 3902 /*
3903 * Read TSSI boundaries for temperature compensation from
3904 * the EEPROM.
3905 *
3906 * Array idx 0 1 2 3 4 5 6 7 8
3907 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3908 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3909 */
57fbcce3 3910 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 3911 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3912 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3913 EEPROM_TSSI_BOUND_BG1_MINUS4);
3914 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3915 EEPROM_TSSI_BOUND_BG1_MINUS3);
3916
3e38d3da 3917 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3918 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3919 EEPROM_TSSI_BOUND_BG2_MINUS2);
3920 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3921 EEPROM_TSSI_BOUND_BG2_MINUS1);
3922
3e38d3da 3923 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3924 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3925 EEPROM_TSSI_BOUND_BG3_REF);
3926 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3927 EEPROM_TSSI_BOUND_BG3_PLUS1);
3928
3e38d3da 3929 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3930 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3931 EEPROM_TSSI_BOUND_BG4_PLUS2);
3932 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3933 EEPROM_TSSI_BOUND_BG4_PLUS3);
3934
3e38d3da 3935 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3936 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3937 EEPROM_TSSI_BOUND_BG5_PLUS4);
3938
3939 step = rt2x00_get_field16(eeprom,
3940 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3941 } else {
3e38d3da 3942 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3943 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3944 EEPROM_TSSI_BOUND_A1_MINUS4);
3945 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3946 EEPROM_TSSI_BOUND_A1_MINUS3);
3947
3e38d3da 3948 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3949 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3950 EEPROM_TSSI_BOUND_A2_MINUS2);
3951 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3952 EEPROM_TSSI_BOUND_A2_MINUS1);
3953
3e38d3da 3954 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3955 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3956 EEPROM_TSSI_BOUND_A3_REF);
3957 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3958 EEPROM_TSSI_BOUND_A3_PLUS1);
3959
3e38d3da 3960 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3961 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3962 EEPROM_TSSI_BOUND_A4_PLUS2);
3963 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3964 EEPROM_TSSI_BOUND_A4_PLUS3);
3965
3e38d3da 3966 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3967 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3968 EEPROM_TSSI_BOUND_A5_PLUS4);
3969
3970 step = rt2x00_get_field16(eeprom,
3971 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3972 }
3973
3974 /*
3975 * Check if temperature compensation is supported.
3976 */
bf7e1abe 3977 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3978 return 0;
3979
3980 /*
3981 * Read current TSSI (BBP 49).
3982 */
3983 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3984
3985 /*
3986 * Compare TSSI value (BBP49) with the compensation boundaries
3987 * from the EEPROM and increase or decrease tx power.
3988 */
3989 for (i = 0; i <= 3; i++) {
3990 if (current_tssi > tssi_bounds[i])
3991 break;
3992 }
3993
3994 if (i == 4) {
3995 for (i = 8; i >= 5; i--) {
3996 if (current_tssi < tssi_bounds[i])
3997 break;
3998 }
3999 }
4000
4001 return (i - 4) * step;
4002}
4003
e90c54b2 4004static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
57fbcce3 4005 enum nl80211_band band)
e90c54b2
RJH		 4006{
4007 u16 eeprom;
4008 u8 comp_en;
4009 u8 comp_type;
75faae8b 4010 int comp_value = 0;
e90c54b2 4011
3e38d3da 4012 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 4013
75faae8b
HS		 4014 /*
4015 * HT40 compensation not required.
4016 */
4017 if (eeprom == 0xffff ||
4018 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 4019 return 0;
4020
57fbcce3 4021 if (band == NL80211_BAND_2GHZ) {
e90c54b2
RJH		 4022 comp_en = rt2x00_get_field16(eeprom,
4023 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4024 if (comp_en) {
4025 comp_type = rt2x00_get_field16(eeprom,
4026 EEPROM_TXPOWER_DELTA_TYPE_2G);
4027 comp_value = rt2x00_get_field16(eeprom,
4028 EEPROM_TXPOWER_DELTA_VALUE_2G);
4029 if (!comp_type)
4030 comp_value = -comp_value;
4031 }
4032 } else {
4033 comp_en = rt2x00_get_field16(eeprom,
4034 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4035 if (comp_en) {
4036 comp_type = rt2x00_get_field16(eeprom,
4037 EEPROM_TXPOWER_DELTA_TYPE_5G);
4038 comp_value = rt2x00_get_field16(eeprom,
4039 EEPROM_TXPOWER_DELTA_VALUE_5G);
4040 if (!comp_type)
4041 comp_value = -comp_value;
4042 }
4043 }
4044
4045 return comp_value;
4046}
4047
1e4cf249
SG		 4048static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4049 int power_level, int max_power)
4050{
4051 int delta;
4052
c429dfef 4053 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 4054 return 0;
4055
4056 /*
4057 * XXX: We don't know the maximum transmit power of our hardware since
4058 * the EEPROM doesn't expose it. We only know that we are calibrated
4059 * to 100% tx power.
4060 *
4061 * Hence, we assume the regulatory limit that cfg80211 calulated for
4062 * the current channel is our maximum and if we are requested to lower
4063 * the value we just reduce our tx power accordingly.
4064 */
4065 delta = power_level - max_power;
4066 return min(delta, 0);
4067}
4068
fa71a160 4069static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
57fbcce3 4070 enum nl80211_band band, int power_level,
fa71a160 4071 u8 txpower, int delta)
e90c54b2 4072{
e90c54b2
RJH		 4073 u16 eeprom;
4074 u8 criterion;
4075 u8 eirp_txpower;
4076 u8 eirp_txpower_criterion;
4077 u8 reg_limit;
e90c54b2 4078
34542ff5
GJ		 4079 if (rt2x00_rt(rt2x00dev, RT3593))
4080 return min_t(u8, txpower, 0xc);
4081
c429dfef 4082 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 4083 /*
4084 * Check if eirp txpower exceed txpower_limit.
4085 * We use OFDM 6M as criterion and its eirp txpower
4086 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4087 * .11b data rate need add additional 4dbm
4088 * when calculating eirp txpower.
4089 */
022138ca
GJ		 4090 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4091 1, &eeprom);
d9bceaeb
SG		 4092 criterion = rt2x00_get_field16(eeprom,
4093 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 4094
3e38d3da 4095 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 4096 &eeprom);
e90c54b2 4097
57fbcce3 4098 if (band == NL80211_BAND_2GHZ)
e90c54b2
RJH		 4099 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4100 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4101 else
4102 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4103 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4104
4105 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 4106 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 4107
4108 reg_limit = (eirp_txpower > power_level) ?
4109 (eirp_txpower - power_level) : 0;
4110 } else
4111 reg_limit = 0;
4112
19f3fa24
SG		 4113 txpower = max(0, txpower + delta - reg_limit);
4114 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 4115}
4116
34542ff5
GJ		 4117
4118enum {
4119 TX_PWR_CFG_0_IDX,
4120 TX_PWR_CFG_1_IDX,
4121 TX_PWR_CFG_2_IDX,
4122 TX_PWR_CFG_3_IDX,
4123 TX_PWR_CFG_4_IDX,
4124 TX_PWR_CFG_5_IDX,
4125 TX_PWR_CFG_6_IDX,
4126 TX_PWR_CFG_7_IDX,
4127 TX_PWR_CFG_8_IDX,
4128 TX_PWR_CFG_9_IDX,
4129 TX_PWR_CFG_0_EXT_IDX,
4130 TX_PWR_CFG_1_EXT_IDX,
4131 TX_PWR_CFG_2_EXT_IDX,
4132 TX_PWR_CFG_3_EXT_IDX,
4133 TX_PWR_CFG_4_EXT_IDX,
4134 TX_PWR_CFG_IDX_COUNT,
4135};
4136
4137static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4138 struct ieee80211_channel *chan,
4139 int power_level)
4140{
4141 u8 txpower;
4142 u16 eeprom;
4143 u32 regs[TX_PWR_CFG_IDX_COUNT];
4144 unsigned int offset;
57fbcce3 4145 enum nl80211_band band = chan->band;
34542ff5
GJ		 4146 int delta;
4147 int i;
4148
4149 memset(regs, '\0', sizeof(regs));
4150
4151 /* TODO: adapt TX power reduction from the rt28xx code */
4152
4153 /* calculate temperature compensation delta */
4154 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4155
57fbcce3 4156 if (band == NL80211_BAND_5GHZ)
34542ff5
GJ		 4157 offset = 16;
4158 else
4159 offset = 0;
4160
4161 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4162 offset += 8;
4163
4164 /* read the next four txpower values */
4165 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4166 offset, &eeprom);
4167
4168 /* CCK 1MBS,2MBS */
4169 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4170 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4171 txpower, delta);
4172 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4173 TX_PWR_CFG_0_CCK1_CH0, txpower);
4174 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4175 TX_PWR_CFG_0_CCK1_CH1, txpower);
4176 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4177 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4178
4179 /* CCK 5.5MBS,11MBS */
4180 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4181 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4182 txpower, delta);
4183 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4184 TX_PWR_CFG_0_CCK5_CH0, txpower);
4185 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4186 TX_PWR_CFG_0_CCK5_CH1, txpower);
4187 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4188 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4189
4190 /* OFDM 6MBS,9MBS */
4191 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4192 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4193 txpower, delta);
4194 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4195 TX_PWR_CFG_0_OFDM6_CH0, txpower);
4196 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4197 TX_PWR_CFG_0_OFDM6_CH1, txpower);
4198 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4199 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4200
4201 /* OFDM 12MBS,18MBS */
4202 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4203 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4204 txpower, delta);
4205 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4206 TX_PWR_CFG_0_OFDM12_CH0, txpower);
4207 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4208 TX_PWR_CFG_0_OFDM12_CH1, txpower);
4209 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4210 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4211
4212 /* read the next four txpower values */
4213 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4214 offset + 1, &eeprom);
4215
4216 /* OFDM 24MBS,36MBS */
4217 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4218 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4219 txpower, delta);
4220 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4221 TX_PWR_CFG_1_OFDM24_CH0, txpower);
4222 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4223 TX_PWR_CFG_1_OFDM24_CH1, txpower);
4224 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4225 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4226
4227 /* OFDM 48MBS */
4228 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4229 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4230 txpower, delta);
4231 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4232 TX_PWR_CFG_1_OFDM48_CH0, txpower);
4233 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4234 TX_PWR_CFG_1_OFDM48_CH1, txpower);
4235 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4236 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4237
4238 /* OFDM 54MBS */
4239 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4240 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4241 txpower, delta);
4242 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4243 TX_PWR_CFG_7_OFDM54_CH0, txpower);
4244 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4245 TX_PWR_CFG_7_OFDM54_CH1, txpower);
4246 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4247 TX_PWR_CFG_7_OFDM54_CH2, txpower);
4248
4249 /* read the next four txpower values */
4250 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4251 offset + 2, &eeprom);
4252
4253 /* MCS 0,1 */
4254 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4255 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4256 txpower, delta);
4257 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4258 TX_PWR_CFG_1_MCS0_CH0, txpower);
4259 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4260 TX_PWR_CFG_1_MCS0_CH1, txpower);
4261 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4262 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4263
4264 /* MCS 2,3 */
4265 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4266 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4267 txpower, delta);
4268 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4269 TX_PWR_CFG_1_MCS2_CH0, txpower);
4270 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4271 TX_PWR_CFG_1_MCS2_CH1, txpower);
4272 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4273 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4274
4275 /* MCS 4,5 */
4276 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4277 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4278 txpower, delta);
4279 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4280 TX_PWR_CFG_2_MCS4_CH0, txpower);
4281 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4282 TX_PWR_CFG_2_MCS4_CH1, txpower);
4283 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4284 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4285
4286 /* MCS 6 */
4287 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4288 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4289 txpower, delta);
4290 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4291 TX_PWR_CFG_2_MCS6_CH0, txpower);
4292 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4293 TX_PWR_CFG_2_MCS6_CH1, txpower);
4294 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4295 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4296
4297 /* read the next four txpower values */
4298 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4299 offset + 3, &eeprom);
4300
4301 /* MCS 7 */
4302 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4303 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4304 txpower, delta);
4305 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4306 TX_PWR_CFG_7_MCS7_CH0, txpower);
4307 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4308 TX_PWR_CFG_7_MCS7_CH1, txpower);
4309 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4310 TX_PWR_CFG_7_MCS7_CH2, txpower);
4311
4312 /* MCS 8,9 */
4313 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4314 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4315 txpower, delta);
4316 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4317 TX_PWR_CFG_2_MCS8_CH0, txpower);
4318 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4319 TX_PWR_CFG_2_MCS8_CH1, txpower);
4320 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4321 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4322
4323 /* MCS 10,11 */
4324 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4325 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4326 txpower, delta);
4327 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4328 TX_PWR_CFG_2_MCS10_CH0, txpower);
4329 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4330 TX_PWR_CFG_2_MCS10_CH1, txpower);
4331 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4332 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4333
4334 /* MCS 12,13 */
4335 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4336 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4337 txpower, delta);
4338 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4339 TX_PWR_CFG_3_MCS12_CH0, txpower);
4340 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4341 TX_PWR_CFG_3_MCS12_CH1, txpower);
4342 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4343 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4344
4345 /* read the next four txpower values */
4346 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4347 offset + 4, &eeprom);
4348
4349 /* MCS 14 */
4350 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4351 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4352 txpower, delta);
4353 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4354 TX_PWR_CFG_3_MCS14_CH0, txpower);
4355 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4356 TX_PWR_CFG_3_MCS14_CH1, txpower);
4357 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4358 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4359
4360 /* MCS 15 */
4361 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4362 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4363 txpower, delta);
4364 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4365 TX_PWR_CFG_8_MCS15_CH0, txpower);
4366 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4367 TX_PWR_CFG_8_MCS15_CH1, txpower);
4368 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4369 TX_PWR_CFG_8_MCS15_CH2, txpower);
4370
4371 /* MCS 16,17 */
4372 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4373 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4374 txpower, delta);
4375 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4376 TX_PWR_CFG_5_MCS16_CH0, txpower);
4377 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4378 TX_PWR_CFG_5_MCS16_CH1, txpower);
4379 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4380 TX_PWR_CFG_5_MCS16_CH2, txpower);
4381
4382 /* MCS 18,19 */
4383 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4384 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4385 txpower, delta);
4386 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4387 TX_PWR_CFG_5_MCS18_CH0, txpower);
4388 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4389 TX_PWR_CFG_5_MCS18_CH1, txpower);
4390 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4391 TX_PWR_CFG_5_MCS18_CH2, txpower);
4392
4393 /* read the next four txpower values */
4394 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4395 offset + 5, &eeprom);
4396
4397 /* MCS 20,21 */
4398 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4399 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4400 txpower, delta);
4401 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4402 TX_PWR_CFG_6_MCS20_CH0, txpower);
4403 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4404 TX_PWR_CFG_6_MCS20_CH1, txpower);
4405 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4406 TX_PWR_CFG_6_MCS20_CH2, txpower);
4407
4408 /* MCS 22 */
4409 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4410 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4411 txpower, delta);
4412 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4413 TX_PWR_CFG_6_MCS22_CH0, txpower);
4414 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4415 TX_PWR_CFG_6_MCS22_CH1, txpower);
4416 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4417 TX_PWR_CFG_6_MCS22_CH2, txpower);
4418
4419 /* MCS 23 */
4420 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4421 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4422 txpower, delta);
4423 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4424 TX_PWR_CFG_8_MCS23_CH0, txpower);
4425 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4426 TX_PWR_CFG_8_MCS23_CH1, txpower);
4427 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4428 TX_PWR_CFG_8_MCS23_CH2, txpower);
4429
4430 /* read the next four txpower values */
4431 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4432 offset + 6, &eeprom);
4433
4434 /* STBC, MCS 0,1 */
4435 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4436 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4437 txpower, delta);
4438 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4439 TX_PWR_CFG_3_STBC0_CH0, txpower);
4440 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4441 TX_PWR_CFG_3_STBC0_CH1, txpower);
4442 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4443 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4444
4445 /* STBC, MCS 2,3 */
4446 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4447 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4448 txpower, delta);
4449 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4450 TX_PWR_CFG_3_STBC2_CH0, txpower);
4451 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4452 TX_PWR_CFG_3_STBC2_CH1, txpower);
4453 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4454 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4455
4456 /* STBC, MCS 4,5 */
4457 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4458 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4459 txpower, delta);
4460 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4461 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4462 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4463 txpower);
4464
4465 /* STBC, MCS 6 */
4466 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4467 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4468 txpower, delta);
4469 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4470 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4471 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4472 txpower);
4473
4474 /* read the next four txpower values */
4475 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4476 offset + 7, &eeprom);
4477
4478 /* STBC, MCS 7 */
4479 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4480 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4481 txpower, delta);
4482 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4483 TX_PWR_CFG_9_STBC7_CH0, txpower);
4484 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4485 TX_PWR_CFG_9_STBC7_CH1, txpower);
4486 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4487 TX_PWR_CFG_9_STBC7_CH2, txpower);
4488
4489 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4490 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4491 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4492 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4493 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4494 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4495 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4496 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4497 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4498 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4499
4500 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4501 regs[TX_PWR_CFG_0_EXT_IDX]);
4502 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4503 regs[TX_PWR_CFG_1_EXT_IDX]);
4504 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4505 regs[TX_PWR_CFG_2_EXT_IDX]);
4506 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4507 regs[TX_PWR_CFG_3_EXT_IDX]);
4508 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4509 regs[TX_PWR_CFG_4_EXT_IDX]);
4510
4511 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4512 rt2x00_dbg(rt2x00dev,
4513 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
57fbcce3 4514 (band == NL80211_BAND_5GHZ) ? '5' : '2',
34542ff5
GJ		 4515 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4516 '4' : '2',
4517 (i > TX_PWR_CFG_9_IDX) ?
4518 (i - TX_PWR_CFG_9_IDX - 1) : i,
4519 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4520 (unsigned long) regs[i]);
4521}
4522
41977e86
RY		 4523static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4524 struct ieee80211_channel *chan,
4525 int power_level)
4526{
4527 u32 reg, pwreg;
4528 u16 eeprom;
4529 u32 data, gdata;
4530 u8 t, i;
4531 enum nl80211_band band = chan->band;
4532 int delta;
4533
4534 /* Warn user if bw_comp is set in EEPROM */
4535 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4536
4537 if (delta)
4538 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4539 delta);
4540
4541 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4542 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4543 * driver does as well, though it looks kinda wrong.
4544 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4545 * the hardware has a problem handling 0x20, and as the code initially
4546 * used a fixed offset between HT20 and HT40 rates they had to work-
4547 * around that issue and most likely just forgot about it later on.
4548 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4549 * however, the corresponding EEPROM value is not respected by the
4550 * vendor driver, so maybe this is rather being taken care of the
4551 * TXALC and the driver doesn't need to handle it...?
4552 * Though this is all very awkward, just do as they did, as that's what
4553 * board vendors expected when they populated the EEPROM...
4554 */
4555 for (i = 0; i < 5; i++) {
4556 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4557 i * 2, &eeprom);
4558
4559 data = eeprom;
4560
4561 t = eeprom & 0x3f;
4562 if (t == 32)
4563 t++;
4564
4565 gdata = t;
4566
4567 t = (eeprom & 0x3f00) >> 8;
4568 if (t == 32)
4569 t++;
4570
4571 gdata |= (t << 8);
4572
4573 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4574 (i * 2) + 1, &eeprom);
4575
4576 t = eeprom & 0x3f;
4577 if (t == 32)
4578 t++;
4579
4580 gdata |= (t << 16);
4581
4582 t = (eeprom & 0x3f00) >> 8;
4583 if (t == 32)
4584 t++;
4585
4586 gdata |= (t << 24);
4587 data |= (eeprom << 16);
4588
4589 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
4590 /* HT20 */
4591 if (data != 0xffffffff)
4592 rt2800_register_write(rt2x00dev,
4593 TX_PWR_CFG_0 + (i * 4),
4594 data);
4595 } else {
4596 /* HT40 */
4597 if (gdata != 0xffffffff)
4598 rt2800_register_write(rt2x00dev,
4599 TX_PWR_CFG_0 + (i * 4),
4600 gdata);
4601 }
4602 }
4603
4604 /* Aparently Ralink ran out of space in the BYRATE calibration section
4605 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
4606 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
4607 * power-offsets more space would be needed. Ralink decided to keep the
4608 * EEPROM layout untouched and rather have some shared values covering
4609 * multiple bitrates.
4610 * Populate the registers not covered by the EEPROM in the same way the
4611 * vendor driver does.
4612 */
4613
4614 /* For OFDM 54MBS use value from OFDM 48MBS */
4615 pwreg = 0;
4616 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
4617 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
4618 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
4619
4620 /* For MCS 7 use value from MCS 6 */
4621 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
4622 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
4623 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
4624 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
4625
4626 /* For MCS 15 use value from MCS 14 */
4627 pwreg = 0;
4628 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
4629 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
4630 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
4631 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
4632
4633 /* For STBC MCS 7 use value from STBC MCS 6 */
4634 pwreg = 0;
4635 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
4636 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
4637 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
4638 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
4639
4640 rt2800_config_alc(rt2x00dev, chan, power_level);
4641
4642 /* TODO: temperature compensation code! */
4643}
4644
7a66205a
SG		 4645/*
4646 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4647 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4648 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4649 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4650 * Reference per rate transmit power values are located in the EEPROM at
4651 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4652 * current conditions (i.e. band, bandwidth, temperature, user settings).
4653 */
34542ff5
GJ		 4654static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4655 struct ieee80211_channel *chan,
4656 int power_level)
f4450616 4657{
cee2c731 4658 u8 txpower, r1;
5e846004 4659 u16 eeprom;
cee2c731
SG		 4660 u32 reg, offset;
4661 int i, is_rate_b, delta, power_ctrl;
57fbcce3 4662 enum nl80211_band band = chan->band;
2af242e1
HS		 4663
4664 /*
7a66205a
SG		 4665 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4666 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4667 */
4668 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4669
9e33a355 4670 /*
7a66205a
SG		 4671 * Calculate temperature compensation. Depends on measurement of current
4672 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4673 * to temperature or maybe other factors) is smaller or bigger than
4674 * expected. We adjust it, based on TSSI reference and boundaries values
4675 * provided in EEPROM.
9e33a355 4676 */
87dd2d76
SG		 4677 switch (rt2x00dev->chip.rt) {
4678 case RT2860:
4679 case RT2872:
4680 case RT2883:
4681 case RT3070:
4682 case RT3071:
4683 case RT3090:
4684 case RT3572:
4685 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4686 break;
4687 default:
4688 /* TODO: temperature compensation code for other chips. */
4689 break;
4690 }
f4450616 4691
1e4cf249 4692 /*
7a66205a
SG		 4693 * Decrease power according to user settings, on devices with unknown
4694 * maximum tx power. For other devices we take user power_level into
4695 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4696 */
4697 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4698 chan->max_power);
4699
5e846004 4700 /*
cee2c731
SG		 4701 * BBP_R1 controls TX power for all rates, it allow to set the following
4702 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4703 *
4704 * TODO: we do not use +6 dBm option to do not increase power beyond
4705 * regulatory limit, however this could be utilized for devices with
4706 * CAPABILITY_POWER_LIMIT.
8c8d2017 4707 */
87dd2d76
SG		 4708 if (delta <= -12) {
4709 power_ctrl = 2;
4710 delta += 12;
4711 } else if (delta <= -6) {
4712 power_ctrl = 1;
4713 delta += 6;
4714 } else {
4715 power_ctrl = 0;
cee2c731 4716 }
87dd2d76
SG		 4717 rt2800_bbp_read(rt2x00dev, 1, &r1);
4718 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4719 rt2800_bbp_write(rt2x00dev, 1, r1);
8c8d2017 4720
5e846004
HS		 4721 offset = TX_PWR_CFG_0;
4722
4723 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4724 /* just to be safe */
4725 if (offset > TX_PWR_CFG_4)
4726 break;
4727
4728 rt2800_register_read(rt2x00dev, offset, &reg);
4729
4730 /* read the next four txpower values */
022138ca
GJ		 4731 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4732 i, &eeprom);
5e846004 4733
e90c54b2
RJH		 4734 is_rate_b = i ? 0 : 1;
4735 /*
4736 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4737 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4738 * TX_PWR_CFG_4: unknown
4739 */
5e846004
HS		 4740 txpower = rt2x00_get_field16(eeprom,
4741 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4742 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4743 power_level, txpower, delta);
e90c54b2 4744 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4745
e90c54b2
RJH		 4746 /*
4747 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4748 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4749 * TX_PWR_CFG_4: unknown
4750 */
5e846004
HS		 4751 txpower = rt2x00_get_field16(eeprom,
4752 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4753 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4754 power_level, txpower, delta);
e90c54b2 4755 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4756
e90c54b2
RJH		 4757 /*
4758 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4759 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4760 * TX_PWR_CFG_4: unknown
4761 */
5e846004
HS		 4762 txpower = rt2x00_get_field16(eeprom,
4763 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4764 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4765 power_level, txpower, delta);
e90c54b2 4766 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4767
e90c54b2
RJH		 4768 /*
4769 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4770 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4771 * TX_PWR_CFG_4: unknown
4772 */
5e846004
HS		 4773 txpower = rt2x00_get_field16(eeprom,
4774 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4775 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4776 power_level, txpower, delta);
e90c54b2 4777 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4778
4779 /* read the next four txpower values */
022138ca
GJ		 4780 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4781 i + 1, &eeprom);
5e846004 4782
e90c54b2
RJH		 4783 is_rate_b = 0;
4784 /*
4785 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4786 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4787 * TX_PWR_CFG_4: unknown
4788 */
5e846004
HS		 4789 txpower = rt2x00_get_field16(eeprom,
4790 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4791 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4792 power_level, txpower, delta);
e90c54b2 4793 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4794
e90c54b2
RJH		 4795 /*
4796 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4797 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4798 * TX_PWR_CFG_4: unknown
4799 */
5e846004
HS		 4800 txpower = rt2x00_get_field16(eeprom,
4801 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4802 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4803 power_level, txpower, delta);
e90c54b2 4804 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4805
e90c54b2
RJH		 4806 /*
4807 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4808 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4809 * TX_PWR_CFG_4: unknown
4810 */
5e846004
HS		 4811 txpower = rt2x00_get_field16(eeprom,
4812 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4813 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4814 power_level, txpower, delta);
e90c54b2 4815 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4816
e90c54b2
RJH		 4817 /*
4818 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4819 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4820 * TX_PWR_CFG_4: unknown
4821 */
5e846004
HS		 4822 txpower = rt2x00_get_field16(eeprom,
4823 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4824 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4825 power_level, txpower, delta);
e90c54b2 4826 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4827
4828 rt2800_register_write(rt2x00dev, offset, reg);
4829
4830 /* next TX_PWR_CFG register */
4831 offset += 4;
4832 }
f4450616
BZ		 4833}
4834
34542ff5
GJ		 4835static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4836 struct ieee80211_channel *chan,
4837 int power_level)
4838{
4839 if (rt2x00_rt(rt2x00dev, RT3593))
4840 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
41977e86
RY		 4841 else if (rt2x00_rt(rt2x00dev, RT6352))
4842 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
34542ff5
GJ		 4843 else
4844 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4845}
4846
9e33a355
HS		 4847void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4848{
675a0b04 4849 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4850 rt2x00dev->tx_power);
4851}
4852EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4853
2e9c43dd
JL		 4854void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4855{
4856 u32 tx_pin;
4857 u8 rfcsr;
41977e86 4858 unsigned long min_sleep = 0;
2e9c43dd
JL		 4859
4860 /*
4861 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4862 * designed to be controlled in oscillation frequency by a voltage
4863 * input. Maybe the temperature will affect the frequency of
4864 * oscillation to be shifted. The VCO calibration will be called
4865 * periodically to adjust the frequency to be precision.
4866 */
4867
4868 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4869 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4870 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4871
4872 switch (rt2x00dev->chip.rf) {
4873 case RF2020:
4874 case RF3020:
4875 case RF3021:
4876 case RF3022:
4877 case RF3320:
4878 case RF3052:
16d571bb 4879 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2e9c43dd
JL		 4880 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4881 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4882 break;
1095df07 4883 case RF3053:
3b9b74ba 4884 case RF3070:
a89534ed 4885 case RF3290:
98e71f44 4886 case RF5350:
ccf91bd6 4887 case RF5360:
ac0372ab 4888 case RF5362:
2e9c43dd
JL		 4889 case RF5370:
4890 case RF5372:
4891 case RF5390:
cff3d1f0 4892 case RF5392:
24d42ef3 4893 case RF5592:
16d571bb 4894 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
d6d82020 4895 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd 4896 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
41977e86
RY		 4897 min_sleep = 1000;
4898 break;
4899 case RF7620:
4900 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
4901 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
16d571bb 4902 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
41977e86
RY		 4903 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
4904 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
4905 min_sleep = 2000;
2e9c43dd
JL		 4906 break;
4907 default:
bc007705
SG		 4908 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
4909 rt2x00dev->chip.rf);
2e9c43dd
JL		 4910 return;
4911 }
4912
41977e86
RY		 4913 if (min_sleep > 0)
4914 usleep_range(min_sleep, min_sleep * 2);
2e9c43dd
JL		 4915
4916 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4917 if (rt2x00dev->rf_channel <= 14) {
4918 switch (rt2x00dev->default_ant.tx_chain_num) {
4919 case 3:
4920 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4921 /* fall through */
4922 case 2:
4923 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4924 /* fall through */
4925 case 1:
4926 default:
4927 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4928 break;
4929 }
4930 } else {
4931 switch (rt2x00dev->default_ant.tx_chain_num) {
4932 case 3:
4933 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4934 /* fall through */
4935 case 2:
4936 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4937 /* fall through */
4938 case 1:
4939 default:
4940 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4941 break;
4942 }
4943 }
4944 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4945
41977e86 4946 if (rt2x00_rt(rt2x00dev, RT6352)) {
4bd96b5d 4947 if (rt2x00dev->default_ant.rx_chain_num == 1) {
41977e86
RY		 4948 rt2800_bbp_write(rt2x00dev, 91, 0x07);
4949 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
4950 rt2800_bbp_write(rt2x00dev, 195, 128);
4951 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
4952 rt2800_bbp_write(rt2x00dev, 195, 170);
4953 rt2800_bbp_write(rt2x00dev, 196, 0x12);
4954 rt2800_bbp_write(rt2x00dev, 195, 171);
4955 rt2800_bbp_write(rt2x00dev, 196, 0x10);
4956 } else {
4957 rt2800_bbp_write(rt2x00dev, 91, 0x06);
4958 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
4959 rt2800_bbp_write(rt2x00dev, 195, 128);
4960 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
4961 rt2800_bbp_write(rt2x00dev, 195, 170);
4962 rt2800_bbp_write(rt2x00dev, 196, 0x30);
4963 rt2800_bbp_write(rt2x00dev, 195, 171);
4964 rt2800_bbp_write(rt2x00dev, 196, 0x30);
4965 }
4966
4967 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4bd96b5d
TP		 4968 rt2800_bbp_write(rt2x00dev, 75, 0x68);
4969 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
41977e86
RY		 4970 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
4971 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
4972 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
4973 }
4974
4975 /* On 11A, We should delay and wait RF/BBP to be stable
4976 * and the appropriate time should be 1000 micro seconds
4977 * 2005/06/05 - On 11G, we also need this delay time.
4978 * Otherwise it's difficult to pass the WHQL.
4979 */
4980 usleep_range(1000, 1500);
4981 }
2e9c43dd
JL		 4982}
4983EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4984
f4450616
BZ		 4985static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4986 struct rt2x00lib_conf *libconf)
4987{
4988 u32 reg;
4989
4990 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4991 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4992 libconf->conf->short_frame_max_tx_count);
4993 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4994 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4995 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4996}
4997
4998static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4999 struct rt2x00lib_conf *libconf)
5000{
5001 enum dev_state state =
5002 (libconf->conf->flags & IEEE80211_CONF_PS) ?
5003 STATE_SLEEP : STATE_AWAKE;
5004 u32 reg;
5005
5006 if (state == STATE_SLEEP) {
5007 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5008
5009 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
5010 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5011 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5012 libconf->conf->listen_interval - 1);
5013 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5014 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5015
5016 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5017 } else {
f4450616
BZ		 5018 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
5019 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5020 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5021 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5022 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 5023
5024 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 5025 }
5026}
5027
5028void rt2800_config(struct rt2x00_dev *rt2x00dev,
5029 struct rt2x00lib_conf *libconf,
5030 const unsigned int flags)
5031{
5032 /* Always recalculate LNA gain before changing configuration */
5033 rt2800_config_lna_gain(rt2x00dev, libconf);
5034
e90c54b2 5035 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 5036 rt2800_config_channel(rt2x00dev, libconf->conf,
5037 &libconf->rf, &libconf->channel);
675a0b04 5038 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 5039 libconf->conf->power_level);
e90c54b2 5040 }
f4450616 5041 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 5042 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 5043 libconf->conf->power_level);
f4450616
BZ		 5044 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5045 rt2800_config_retry_limit(rt2x00dev, libconf);
5046 if (flags & IEEE80211_CONF_CHANGE_PS)
5047 rt2800_config_ps(rt2x00dev, libconf);
5048}
5049EXPORT_SYMBOL_GPL(rt2800_config);
5050
5051/*
5052 * Link tuning
5053 */
5054void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5055{
5056 u32 reg;
5057
5058 /*
5059 * Update FCS error count from register.
5060 */
5061 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5062 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5063}
5064EXPORT_SYMBOL_GPL(rt2800_link_stats);
5065
5066static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5067{
8c6728b0
GW		 5068 u8 vgc;
5069
57fbcce3 5070 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
d5385bfc 5071 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 5072 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 5073 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 5074 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 5075 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 5076 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 5077 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 5078 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e 5079 rt2x00_rt(rt2x00dev, RT5392) ||
41977e86
RY		 5080 rt2x00_rt(rt2x00dev, RT5592) ||
5081 rt2x00_rt(rt2x00dev, RT6352))
8c6728b0
GW		 5082 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5083 else
5084 vgc = 0x2e + rt2x00dev->lna_gain;
5085 } else { /* 5GHZ band */
733aec6a 5086 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 5087 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 5088 else if (rt2x00_rt(rt2x00dev, RT5592))
5089 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 5090 else {
5091 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5092 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5093 else
5094 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5095 }
f4450616
BZ		 5096 }
5097
8c6728b0 5098 return vgc;
f4450616
BZ		 5099}
5100
5101static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5102 struct link_qual *qual, u8 vgc_level)
5103{
5104 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 5105 if (rt2x00_rt(rt2x00dev, RT3572) ||
5106 rt2x00_rt(rt2x00dev, RT3593)) {
5107 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5108 vgc_level);
5109 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 5110 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5111 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 5112 } else {
3d81535e 5113 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 5114 }
5115
f4450616
BZ		 5116 qual->vgc_level = vgc_level;
5117 qual->vgc_level_reg = vgc_level;
5118 }
5119}
5120
5121void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5122{
5123 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5124}
5125EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5126
5127void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5128 const u32 count)
5129{
3d81535e
SG		 5130 u8 vgc;
5131
8d0c9b65 5132 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 5133 return;
e25aa82a
GJ		 5134
5135 /* When RSSI is better than a certain threshold, increase VGC
5136 * with a chip specific value in order to improve the balance
5137 * between sensibility and noise isolation.
f4450616 5138 */
3d81535e
SG		 5139
5140 vgc = rt2800_get_default_vgc(rt2x00dev);
5141
e25aa82a
GJ		 5142 switch (rt2x00dev->chip.rt) {
5143 case RT3572:
5144 case RT3593:
5145 if (qual->rssi > -65) {
57fbcce3 5146 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
e25aa82a
GJ		 5147 vgc += 0x20;
5148 else
5149 vgc += 0x10;
5150 }
5151 break;
5152
5153 case RT5592:
0beb1bbf
GJ		 5154 if (qual->rssi > -65)
5155 vgc += 0x20;
e25aa82a
GJ		 5156 break;
5157
5158 default:
0beb1bbf
GJ		 5159 if (qual->rssi > -80)
5160 vgc += 0x10;
e25aa82a 5161 break;
0beb1bbf 5162 }
3d81535e
SG		 5163
5164 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 5165}
5166EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 5167
5168/*
5169 * Initialization functions.
5170 */
b9a07ae9 5171static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541 5172{
8f03a7c6 5173 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541 5174 u32 reg;
d5385bfc 5175 u16 eeprom;
fcf51541 5176 unsigned int i;
e3a896b9 5177 int ret;
fcf51541 5178
f7b395e9 5179 rt2800_disable_wpdma(rt2x00dev);
a9dce149 5180
e3a896b9
GW		 5181 ret = rt2800_drv_init_registers(rt2x00dev);
5182 if (ret)
5183 return ret;
fcf51541 5184
fcf51541
BZ		 5185 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5186 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5187
5188 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5189
5190 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 5191 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 5192 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5193 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5194 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5195 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5196 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5197 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5198
a9dce149
GW		 5199 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5200
5201 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
5202 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5203 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5204 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5205
a89534ed
WH		 5206 if (rt2x00_rt(rt2x00dev, RT3290)) {
5207 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
5208 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5209 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5210 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5211 }
5212
5213 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
5214 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5215 rt2x00_set_field32(&reg, LDO0_EN, 1);
5216 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5217 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5218 }
5219
5220 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
5221 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5222 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5223 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5224 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5225
5226 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
5227 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5228 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5229
5230 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
5231 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5232 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5233 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5234 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5235 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5236
5237 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
5238 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5239 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5240 }
5241
64522957 5242 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 5243 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 5244 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 5245 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 5246
5247 if (rt2x00_rt(rt2x00dev, RT3290))
5248 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5249 0x00000404);
5250 else
5251 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5252 0x00000400);
5253
fcf51541 5254 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 5255 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 5256 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5257 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 5258 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5259 &eeprom);
38c8a566 5260 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 5261 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5262 0x0000002c);
5263 else
5264 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5265 0x0000000f);
5266 } else {
5267 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5268 }
d5385bfc 5269 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 5270 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 5271
5272 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5273 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5274 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5275 } else {
5276 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5277 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5278 }
c295a81d
HS		 5279 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5280 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5281 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 5282 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 5283 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5284 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5285 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5286 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 5287 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5288 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5289 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 5290 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5291 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5292 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5293 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5294 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5295 &eeprom);
5296 if (rt2x00_get_field16(eeprom,
5297 EEPROM_NIC_CONF1_DAC_TEST))
5298 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5299 0x0000001f);
5300 else
5301 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5302 0x0000000f);
5303 } else {
5304 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5305 0x00000000);
5306 }
2ed71884 5307 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
41977e86
RY		 5308 rt2x00_rt(rt2x00dev, RT5392) ||
5309 rt2x00_rt(rt2x00dev, RT6352)) {
adde5882
GJ		 5310 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5311 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5312 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
231aeca1
SG		 5313 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5314 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5315 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5316 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
98e71f44
SV		 5317 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5318 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
41977e86
RY		 5319 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5320 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5321 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5322 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5323 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5324 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5325 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
5326 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5327 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5328 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5329 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5330 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5331 0x3630363A);
5332 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5333 0x3630363A);
5334 rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, &reg);
5335 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5336 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
fcf51541
BZ		 5337 } else {
5338 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5339 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5340 }
5341
5342 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
5343 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5344 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5345 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5346 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5347 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5348 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5349 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5350 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5351 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5352
5353 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
5354 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 5355 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 5356 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5357 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5358
5359 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
5360 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
66ecec02
SG		 5361 if (rt2x00_is_usb(rt2x00dev)) {
5362 drv_data->max_psdu = 3;
5363 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5364 rt2x00_rt(rt2x00dev, RT2883) ||
5365 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
8f03a7c6 5366 drv_data->max_psdu = 2;
8f03a7c6
SG		 5367 } else {
5368 drv_data->max_psdu = 1;
8f03a7c6 5369 }
66ecec02 5370 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
a51b8969
SG		 5371 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5372 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
fcf51541
BZ		 5373 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5374
a9dce149
GW		 5375 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
5376 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5377 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5378 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5379 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5380 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5381 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5382 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5383 rt2800_register_write(rt2x00dev, LED_CFG, reg);
5384
fcf51541
BZ		 5385 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5386
a9dce149 5387 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
01d97ef4
SG		 5388 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5389 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
a9dce149
GW		 5390 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5391 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5392 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5393 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5394 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5395
fcf51541
BZ		 5396 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
5397 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 5398 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
be82de9d 5399 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
fcf51541 5400 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
be82de9d 5401 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
fcf51541
BZ		 5402 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5403 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5404 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5405
5406 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 5407 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 5408 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 5409 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 5410 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5411 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5412 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 5413 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 5414 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 5415 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5416 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 5417 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5418
5419 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 5420 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 5421 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 5422 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 5423 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5424 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5425 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 5426 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 5427 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 5428 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5429 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 5430 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5431
5432 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5433 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 5434 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5435 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5436 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5437 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5438 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5439 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5440 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5441 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 5442 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5443 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5444
5445 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5446 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 5447 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5448 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5449 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5450 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5451 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5452 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5453 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5454 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 5455 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5456 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5457
5458 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5459 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 5460 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5461 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5462 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5463 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5464 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5465 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5466 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5467 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 5468 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5469 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5470
5471 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5472 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 5473 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 5474 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 5475 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 5476 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5477 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5478 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5479 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5480 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 5481 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 5482 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5483
cea90e55 5484 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 5485 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5486
5487 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5488 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5489 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5490 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5491 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5492 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5493 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5494 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5495 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5496 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5497 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5498 }
5499
961621ab
HS		 5500 /*
5501 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5502 * although it is reserved.
5503 */
5504 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
5505 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5506 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5507 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5508 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5509 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5510 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5511 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5512 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5513 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5514 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5515 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5516
7641328d
SG		 5517 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5518 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 5519
5520 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
e4019e7f 5521 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
fcf51541
BZ		 5522 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
5523 IEEE80211_MAX_RTS_THRESHOLD);
e4019e7f 5524 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
fcf51541
BZ		 5525 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5526
5527 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 5528
a21c2ab4
HS		 5529 /*
5530 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
5531 * time should be set to 16. However, the original Ralink driver uses
5532 * 16 for both and indeed using a value of 10 for CCK SIFS results in
5533 * connection problems with 11g + CTS protection. Hence, use the same
5534 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
5535 */
a9dce149 5536 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 5537 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
5538 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 5539 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5540 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
5541 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5542 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5543
fcf51541
BZ		 5544 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5545
5546 /*
5547 * ASIC will keep garbage value after boot, clear encryption keys.
5548 */
5549 for (i = 0; i < 4; i++)
5550 rt2800_register_write(rt2x00dev,
5551 SHARED_KEY_MODE_ENTRY(i), 0);
5552
5553 for (i = 0; i < 256; i++) {
d7d259d3
HS		 5554 rt2800_config_wcid(rt2x00dev, NULL, i);
5555 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 5556 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
5557 }
5558
5559 /*
5560 * Clear all beacons
fcf51541 5561 */
77f7c0f3
GJ		 5562 for (i = 0; i < 8; i++)
5563 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 5564
cea90e55 5565 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 5566 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
5567 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
5568 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 5569 } else if (rt2x00_is_pcie(rt2x00dev)) {
5570 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
5571 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
5572 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 5573 }
5574
5575 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
5576 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
5577 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
5578 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
5579 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
5580 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
5581 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
5582 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
5583 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
5584 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5585
5586 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
5587 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
5588 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
5589 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
5590 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
5591 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
5592 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
5593 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
5594 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
5595 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5596
5597 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
5598 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5599 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5600 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
5601 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
5602 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
5603 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
5604 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
5605 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
5606 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5607
5608 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
5609 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
5610 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
5611 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
5612 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
5613 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5614
47ee3eb1
HS		 5615 /*
5616 * Do not force the BA window size, we use the TXWI to set it
5617 */
5618 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
5619 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
5620 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5621 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5622
fcf51541
BZ		 5623 /*
5624 * We must clear the error counters.
5625 * These registers are cleared on read,
5626 * so we may pass a useless variable to store the value.
5627 */
5628 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5629 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
5630 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
5631 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
5632 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
5633 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
5634
9f926fb5
HS		 5635 /*
5636 * Setup leadtime for pre tbtt interrupt to 6ms
5637 */
5638 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
5639 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5640 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5641
977206d7
HS		 5642 /*
5643 * Set up channel statistics timer
5644 */
5645 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
5646 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5647 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5648 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5649 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5650 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5651 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5652
fcf51541
BZ		 5653 return 0;
5654}
fcf51541
BZ		 5655
5656static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5657{
5658 unsigned int i;
5659 u32 reg;
5660
5661 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5662 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5663 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5664 return 0;
5665
5666 udelay(REGISTER_BUSY_DELAY);
5667 }
5668
ec9c4989 5669 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5670 return -EACCES;
5671}
5672
5673static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5674{
5675 unsigned int i;
5676 u8 value;
5677
5678 /*
5679 * BBP was enabled after firmware was loaded,
5680 * but we need to reactivate it now.
5681 */
5682 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5683 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5684 msleep(1);
5685
5686 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5687 rt2800_bbp_read(rt2x00dev, 0, &value);
5688 if ((value != 0xff) && (value != 0x00))
5689 return 0;
5690 udelay(REGISTER_BUSY_DELAY);
5691 }
5692
ec9c4989 5693 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5694 return -EACCES;
5695}
5696
a7bbbe5c
SG		 5697static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5698{
5699 u8 value;
5700
5701 rt2800_bbp_read(rt2x00dev, 4, &value);
5702 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5703 rt2800_bbp_write(rt2x00dev, 4, value);
5704}
5705
c2675487
SG		 5706static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5707{
5708 rt2800_bbp_write(rt2x00dev, 142, 1);
5709 rt2800_bbp_write(rt2x00dev, 143, 57);
5710}
5711
a7bbbe5c
SG		 5712static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5713{
5714 const u8 glrt_table[] = {
5715 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5716 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5717 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5718 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5719 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5720 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5721 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5722 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5723 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5724 };
5725 int i;
5726
5727 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5728 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5729 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5730 }
5731};
5732
624708b8 5733static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5734{
5735 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5736 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5737 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5738 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5739 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5740 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5741 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5742 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5743 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5744 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5745 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5746 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5747 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5748 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5749 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5750 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5751}
5752
5df1ff3a
SG		 5753static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5754{
5755 u16 eeprom;
5756 u8 value;
5757
5758 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5759 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5760 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5761 value |= 0x20;
5762 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5763 value &= ~0x02;
5764 rt2800_bbp_write(rt2x00dev, 138, value);
5765}
5766
dae62957
SG		 5767static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5768{
b2f8e0bd 5769 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5770
5771 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5772 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5773
5774 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5775 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5776
5777 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5778
5779 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5780 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5781
5782 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5783
5784 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5785
5786 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5787
5788 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5789
5790 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5791
5792 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5793
5794 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5795
5796 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5797
5798 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5799}
5800
39ab3e8b
SG		 5801static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5802{
e379de12
SG		 5803 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5804 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5805
5806 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5807 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5808 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5809 } else {
5810 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5811 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5812 }
8d97be38
SG		 5813
5814 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5815
5816 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5817
5818 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5819
5820 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5821
5822 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5823 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5824 else
5825 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5826
5827 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5828
5829 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5830
5831 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5832
5833 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5834
5835 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5836
5837 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5838}
5839
5840static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5841{
e379de12
SG		 5842 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5843 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5844
5845 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5846 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5847
5848 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5849
5850 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5851 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5852 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5853
5854 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5855
5856 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5857
5858 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5859
5860 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5861
5862 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5863
5864 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5865
5866 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5867 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5868 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5869 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5870 else
5871 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5872
5873 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5874
5875 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5876
5877 if (rt2x00_rt(rt2x00dev, RT3071) ||
5878 rt2x00_rt(rt2x00dev, RT3090))
5879 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5880}
5881
5882static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5883{
6addb24e
SG		 5884 u8 value;
5885
c3223573 5886 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5887
5888 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5889
5890 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5891 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5892
5893 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5894
5895 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5896 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5897 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5898 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5899
5900 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5901
5902 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5903
5904 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5905 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5906 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5907 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5908
5909 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5910
5911 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5912
5913 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5914
5915 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5916
5917 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5918
5919 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5920
5921 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5922
5923 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5924
5925 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5926
5927 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5928
5929 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5930
5931 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5932 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5933 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5934 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5935 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5936 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5937 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5938 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5939 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5940 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5941
5942 rt2800_bbp_read(rt2x00dev, 47, &value);
5943 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5944 rt2800_bbp_write(rt2x00dev, 47, value);
5945
5946 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5947 rt2800_bbp_read(rt2x00dev, 3, &value);
5948 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5949 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5950 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5951}
5952
5953static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5954{
29f3a58b
SG		 5955 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5956 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5957
5958 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5959
5960 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5961
5962 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5963 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5964
5965 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5966
5967 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5968 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5969 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5970 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5971
5972 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5973
5974 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5975
5976 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5977 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5978 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5979
5980 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414 5981
98e71f44
SV		 5982 if (rt2x00_rt(rt2x00dev, RT5350)) {
5983 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5984 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5985 } else {
5986 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5987 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5988 }
aef9f38b
SG		 5989
5990 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5991
5992 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5993
5994 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5995
5996 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5997
5998 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5999
6000 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118 6001
98e71f44
SV		 6002 if (rt2x00_rt(rt2x00dev, RT5350)) {
6003 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6004 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6005 } else {
6006 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6007 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6008 }
46b90d32
SG		 6009
6010 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 6011
6012 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 6013
6014 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6015 /* Set ITxBF timeout to 0x9c40=1000msec */
6016 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6017 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6018 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6019 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6020 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6021 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6022 /* Reprogram the inband interface to put right values in RXWI */
6023 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6024 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6025 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6026 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6027 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6028 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6029 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6030 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6031
6032 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
98e71f44
SV		 6033
6034 if (rt2x00_rt(rt2x00dev, RT5350)) {
6035 /* Antenna Software OFDM */
6036 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6037 /* Antenna Software CCK */
6038 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6039 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6040 /* Clear previously selected antenna */
6041 rt2800_bbp_write(rt2x00dev, 154, 0);
6042 }
39ab3e8b
SG		 6043}
6044
6045static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6046{
e379de12
SG		 6047 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6048 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 6049
6050 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6051 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 6052
6053 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 6054
6055 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6056 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6057 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 6058
6059 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 6060
6061 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 6062
6063 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 6064
6065 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 6066
6067 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 6068
6069 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 6070
6071 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6072 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6073 else
6074 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 6075
6076 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 6077
6078 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 6079
6080 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 6081}
6082
6083static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6084{
b2f8e0bd 6085 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 6086
6087 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6088 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 6089
6090 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6091 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 6092
6093 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 6094
6095 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6096 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6097 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 6098
6099 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 6100
6101 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 6102
6103 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 6104
6105 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 6106
6107 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 6108
6109 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 6110
6111 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 6112
6113 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 6114
6115 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 6116
6117 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 6118}
6119
b189a181
GJ		 6120static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6121{
6122 rt2800_init_bbp_early(rt2x00dev);
6123
6124 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6125 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6126 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6127 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6128
6129 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6130
6131 /* Enable DC filter */
6132 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6133 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6134}
6135
39ab3e8b
SG		 6136static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6137{
32ef8f49
SG		 6138 int ant, div_mode;
6139 u16 eeprom;
6140 u8 value;
6141
c3223573 6142 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 6143
6144 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 6145
6146 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6147 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 6148
6149 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 6150
58422191 6151 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 6152 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6153 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6154 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6155
6156 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 6157
58422191
SG		 6158 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6159
43f535e2
SG		 6160 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6161 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6162 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 6163
6164 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 6165
6166 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 6167
6168 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 6169
6170 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 6171
6172 if (rt2x00_rt(rt2x00dev, RT5392))
6173 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 6174
6175 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 6176
6177 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 6178
6179 if (rt2x00_rt(rt2x00dev, RT5392)) {
6180 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6181 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6182 }
672d1188
SG		 6183
6184 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 6185
6186 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 6187
6188 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 6189
6190 if (rt2x00_rt(rt2x00dev, RT5390))
6191 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6192 else if (rt2x00_rt(rt2x00dev, RT5392))
6193 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6194 else
6195 WARN_ON(1);
f2b6777c
SG		 6196
6197 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 6198
6199 if (rt2x00_rt(rt2x00dev, RT5392)) {
6200 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6201 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6202 }
5df1ff3a
SG		 6203
6204 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 6205
3e38d3da 6206 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 6207 div_mode = rt2x00_get_field16(eeprom,
6208 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6209 ant = (div_mode == 3) ? 1 : 0;
6210
6211 /* check if this is a Bluetooth combo card */
c429dfef 6212 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 6213 u32 reg;
6214
6215 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6216 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6217 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6218 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6219 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6220 if (ant == 0)
6221 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6222 else if (ant == 1)
6223 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6224 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6225 }
6226
6227 /* This chip has hardware antenna diversity*/
6228 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6229 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6230 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6231 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6232 }
6233
6234 rt2800_bbp_read(rt2x00dev, 152, &value);
6235 if (ant == 0)
6236 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6237 else
6238 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6239 rt2800_bbp_write(rt2x00dev, 152, value);
6240
6241 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 6242}
6243
a7bbbe5c
SG		 6244static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6245{
6246 int ant, div_mode;
6247 u16 eeprom;
6248 u8 value;
6249
624708b8 6250 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 6251
a7bbbe5c
SG		 6252 rt2800_bbp_read(rt2x00dev, 105, &value);
6253 rt2x00_set_field8(&value, BBP105_MLD,
6254 rt2x00dev->default_ant.rx_chain_num == 2);
6255 rt2800_bbp_write(rt2x00dev, 105, value);
6256
6257 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6258
6259 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6260 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6261 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6262 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6263 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6264 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6265 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6266 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6267 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6268 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6269 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6270 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6271 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6272 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6273 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6274 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6275 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6276 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6277 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6278 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6279 /* FIXME BBP105 owerwrite */
6280 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6281 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6282 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6283 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6284 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6285 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6286
6287 /* Initialize GLRT (Generalized Likehood Radio Test) */
6288 rt2800_init_bbp_5592_glrt(rt2x00dev);
6289
6290 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6291
3e38d3da 6292 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 6293 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6294 ant = (div_mode == 3) ? 1 : 0;
6295 rt2800_bbp_read(rt2x00dev, 152, &value);
6296 if (ant == 0) {
6297 /* Main antenna */
6298 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6299 } else {
6300 /* Auxiliary antenna */
6301 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6302 }
6303 rt2800_bbp_write(rt2x00dev, 152, value);
6304
6305 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6306 rt2800_bbp_read(rt2x00dev, 254, &value);
6307 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6308 rt2800_bbp_write(rt2x00dev, 254, value);
6309 }
6310
c2675487
SG		 6311 rt2800_init_freq_calibration(rt2x00dev);
6312
a7bbbe5c 6313 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 6314 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6315 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 6316}
6317
41977e86
RY		 6318static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6319 const u8 reg, const u8 value)
6320{
6321 rt2800_bbp_write(rt2x00dev, 195, reg);
6322 rt2800_bbp_write(rt2x00dev, 196, value);
6323}
6324
6325static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6326 const u8 reg, const u8 value)
6327{
6328 rt2800_bbp_write(rt2x00dev, 158, reg);
6329 rt2800_bbp_write(rt2x00dev, 159, value);
6330}
6331
6332static void rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev,
6333 const u8 reg, u8 *value)
6334{
6335 rt2800_bbp_write(rt2x00dev, 158, reg);
6336 rt2800_bbp_read(rt2x00dev, 159, value);
6337}
6338
6339static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6340{
6341 u8 bbp;
6342
6343 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6344 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6345 rt2x00_set_field8(&bbp, BBP105_MLD,
6346 rt2x00dev->default_ant.rx_chain_num == 2);
6347 rt2800_bbp_write(rt2x00dev, 105, bbp);
6348
6349 /* Avoid data loss and CRC errors */
6350 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6351
6352 /* Fix I/Q swap issue */
6353 rt2800_bbp_read(rt2x00dev, 1, &bbp);
6354 bbp |= 0x04;
6355 rt2800_bbp_write(rt2x00dev, 1, bbp);
6356
6357 /* BBP for G band */
6358 rt2800_bbp_write(rt2x00dev, 3, 0x08);
6359 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6360 rt2800_bbp_write(rt2x00dev, 6, 0x08);
6361 rt2800_bbp_write(rt2x00dev, 14, 0x09);
6362 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6363 rt2800_bbp_write(rt2x00dev, 16, 0x01);
6364 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6365 rt2800_bbp_write(rt2x00dev, 21, 0x00);
6366 rt2800_bbp_write(rt2x00dev, 22, 0x00);
6367 rt2800_bbp_write(rt2x00dev, 27, 0x00);
6368 rt2800_bbp_write(rt2x00dev, 28, 0x00);
6369 rt2800_bbp_write(rt2x00dev, 30, 0x00);
6370 rt2800_bbp_write(rt2x00dev, 31, 0x48);
6371 rt2800_bbp_write(rt2x00dev, 47, 0x40);
6372 rt2800_bbp_write(rt2x00dev, 62, 0x00);
6373 rt2800_bbp_write(rt2x00dev, 63, 0x00);
6374 rt2800_bbp_write(rt2x00dev, 64, 0x00);
6375 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6376 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6377 rt2800_bbp_write(rt2x00dev, 67, 0x20);
6378 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6379 rt2800_bbp_write(rt2x00dev, 69, 0x10);
6380 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6381 rt2800_bbp_write(rt2x00dev, 73, 0x18);
6382 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6383 rt2800_bbp_write(rt2x00dev, 75, 0x60);
6384 rt2800_bbp_write(rt2x00dev, 76, 0x44);
6385 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6386 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6387 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6388 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6389 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6390 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6391 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6392 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6393 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6394 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6395 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6396 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6397 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6398 rt2800_bbp_write(rt2x00dev, 96, 0x00);
6399 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6400 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6401 /* FIXME BBP105 owerwrite */
6402 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6403 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6404 rt2800_bbp_write(rt2x00dev, 109, 0x00);
6405 rt2800_bbp_write(rt2x00dev, 134, 0x10);
6406 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6407 rt2800_bbp_write(rt2x00dev, 137, 0x04);
6408 rt2800_bbp_write(rt2x00dev, 142, 0x30);
6409 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6410 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6411 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6412 rt2800_bbp_write(rt2x00dev, 162, 0x77);
6413 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6414 rt2800_bbp_write(rt2x00dev, 164, 0x00);
6415 rt2800_bbp_write(rt2x00dev, 165, 0x00);
6416 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6417 rt2800_bbp_write(rt2x00dev, 187, 0x00);
6418 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6419 rt2800_bbp_write(rt2x00dev, 186, 0x00);
6420 rt2800_bbp_write(rt2x00dev, 187, 0x01);
6421 rt2800_bbp_write(rt2x00dev, 188, 0x00);
6422 rt2800_bbp_write(rt2x00dev, 189, 0x00);
6423
6424 rt2800_bbp_write(rt2x00dev, 91, 0x06);
6425 rt2800_bbp_write(rt2x00dev, 92, 0x04);
6426 rt2800_bbp_write(rt2x00dev, 93, 0x54);
6427 rt2800_bbp_write(rt2x00dev, 99, 0x50);
6428 rt2800_bbp_write(rt2x00dev, 148, 0x84);
6429 rt2800_bbp_write(rt2x00dev, 167, 0x80);
6430 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6431 rt2800_bbp_write(rt2x00dev, 106, 0x13);
6432
6433 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6434 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6435 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6436 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6437 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6438 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6439 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6440 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6441 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6442 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6443 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6444 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6445 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6446 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6447 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6448 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6449 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6450 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6451 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6452 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6453 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6454 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6455 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6456 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6457 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6458 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6459 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6460 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6461 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6462 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6463 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6464 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6465 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6466 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6467 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6468 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6469 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6470 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6471 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6472 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6473 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6474 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6475 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6476 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6477 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6478 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6479 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6480 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6481 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6482 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6483 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6484 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6485 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6486 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6487 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6488 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
6489 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
6490 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
6491 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
6492 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
6493 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
6494 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
6495 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
6496 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
6497 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
6498 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
6499 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
6500 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
6501 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
6502 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
6503 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
6504 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
6505 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
6506 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
6507 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
6508 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
6509 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
6510 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
6511 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
6512 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
6513 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
6514 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
6515 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
6516 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
6517
6518 /* BBP for G band DCOC function */
6519 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
6520 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
6521 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
6522 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
6523 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
6524 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
6525 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
6526 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
6527 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
6528 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
6529 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
6530 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
6531 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
6532 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
6533 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
6534 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
6535 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
6536 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
6537 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
6538 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
6539
6540 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6541}
6542
a1ef5039 6543static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 6544{
6545 unsigned int i;
6546 u16 eeprom;
6547 u8 reg_id;
6548 u8 value;
6549
dae62957
SG		 6550 if (rt2800_is_305x_soc(rt2x00dev))
6551 rt2800_init_bbp_305x_soc(rt2x00dev);
6552
39ab3e8b
SG		 6553 switch (rt2x00dev->chip.rt) {
6554 case RT2860:
6555 case RT2872:
6556 case RT2883:
6557 rt2800_init_bbp_28xx(rt2x00dev);
6558 break;
6559 case RT3070:
6560 case RT3071:
6561 case RT3090:
6562 rt2800_init_bbp_30xx(rt2x00dev);
6563 break;
6564 case RT3290:
6565 rt2800_init_bbp_3290(rt2x00dev);
6566 break;
6567 case RT3352:
98e71f44 6568 case RT5350:
39ab3e8b
SG		 6569 rt2800_init_bbp_3352(rt2x00dev);
6570 break;
6571 case RT3390:
6572 rt2800_init_bbp_3390(rt2x00dev);
6573 break;
6574 case RT3572:
6575 rt2800_init_bbp_3572(rt2x00dev);
6576 break;
b189a181
GJ		 6577 case RT3593:
6578 rt2800_init_bbp_3593(rt2x00dev);
6579 return;
39ab3e8b
SG		 6580 case RT5390:
6581 case RT5392:
6582 rt2800_init_bbp_53xx(rt2x00dev);
6583 break;
6584 case RT5592:
a7bbbe5c 6585 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 6586 return;
41977e86
RY		 6587 case RT6352:
6588 rt2800_init_bbp_6352(rt2x00dev);
6589 break;
a7bbbe5c
SG		 6590 }
6591
fcf51541 6592 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 6593 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
6594 &eeprom);
fcf51541
BZ		 6595
6596 if (eeprom != 0xffff && eeprom != 0x0000) {
6597 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6598 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6599 rt2800_bbp_write(rt2x00dev, reg_id, value);
6600 }
6601 }
fcf51541 6602}
fcf51541 6603
d9517f2f
SG		 6604static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
6605{
6606 u32 reg;
6607
6608 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
6609 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
6610 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
6611}
6612
c5b3c350
SG		 6613static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
6614 u8 filter_target)
fcf51541
BZ		 6615{
6616 unsigned int i;
6617 u8 bbp;
6618 u8 rfcsr;
6619 u8 passband;
6620 u8 stopband;
6621 u8 overtuned = 0;
c5b3c350 6622 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 6623
6624 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6625
6626 rt2800_bbp_read(rt2x00dev, 4, &bbp);
6627 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
6628 rt2800_bbp_write(rt2x00dev, 4, bbp);
6629
16d571bb 6630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
80d184e6
RJH		 6631 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
6632 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
6633
16d571bb 6634 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
fcf51541
BZ		 6635 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
6636 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6637
6638 /*
6639 * Set power & frequency of passband test tone
6640 */
6641 rt2800_bbp_write(rt2x00dev, 24, 0);
6642
6643 for (i = 0; i < 100; i++) {
6644 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6645 msleep(1);
6646
6647 rt2800_bbp_read(rt2x00dev, 55, &passband);
6648 if (passband)
6649 break;
6650 }
6651
6652 /*
6653 * Set power & frequency of stopband test tone
6654 */
6655 rt2800_bbp_write(rt2x00dev, 24, 0x06);
6656
6657 for (i = 0; i < 100; i++) {
6658 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6659 msleep(1);
6660
6661 rt2800_bbp_read(rt2x00dev, 55, &stopband);
6662
6663 if ((passband - stopband) <= filter_target) {
6664 rfcsr24++;
6665 overtuned += ((passband - stopband) == filter_target);
6666 } else
6667 break;
6668
6669 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6670 }
6671
6672 rfcsr24 -= !!overtuned;
6673
6674 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6675 return rfcsr24;
6676}
6677
ce94ede9
SG		 6678static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
6679 const unsigned int rf_reg)
6680{
6681 u8 rfcsr;
6682
16d571bb 6683 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
ce94ede9
SG		 6684 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
6685 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6686 msleep(1);
6687 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
6688 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6689}
6690
c5b3c350
SG		 6691static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
6692{
6693 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6694 u8 filter_tgt_bw20;
6695 u8 filter_tgt_bw40;
6696 u8 rfcsr, bbp;
6697
6698 /*
6699 * TODO: sync filter_tgt values with vendor driver
6700 */
6701 if (rt2x00_rt(rt2x00dev, RT3070)) {
6702 filter_tgt_bw20 = 0x16;
6703 filter_tgt_bw40 = 0x19;
6704 } else {
6705 filter_tgt_bw20 = 0x13;
6706 filter_tgt_bw40 = 0x15;
6707 }
6708
6709 drv_data->calibration_bw20 =
6710 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
6711 drv_data->calibration_bw40 =
6712 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
6713
6714 /*
6715 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
6716 */
6717 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6718 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6719
6720 /*
6721 * Set back to initial state
6722 */
6723 rt2800_bbp_write(rt2x00dev, 24, 0);
6724
16d571bb 6725 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
c5b3c350
SG		 6726 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
6727 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6728
6729 /*
6730 * Set BBP back to BW20
6731 */
6732 rt2800_bbp_read(rt2x00dev, 4, &bbp);
6733 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
6734 rt2800_bbp_write(rt2x00dev, 4, bbp);
6735}
6736
da8064c2
SG		 6737static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
6738{
6739 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6740 u8 min_gain, rfcsr, bbp;
6741 u16 eeprom;
6742
16d571bb 6743 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
da8064c2
SG		 6744
6745 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
6746 if (rt2x00_rt(rt2x00dev, RT3070) ||
6747 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6748 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
6749 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 6750 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 6751 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
6752 }
6753
6754 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
6755 if (drv_data->txmixer_gain_24g >= min_gain) {
6756 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
6757 drv_data->txmixer_gain_24g);
6758 }
6759
6760 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
6761
6762 if (rt2x00_rt(rt2x00dev, RT3090)) {
6763 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6764 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 6765 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 6766 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6767 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
6768 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6769 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
6770 rt2800_bbp_write(rt2x00dev, 138, bbp);
6771 }
6772
6773 if (rt2x00_rt(rt2x00dev, RT3070)) {
16d571bb 6774 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
da8064c2
SG		 6775 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
6776 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
6777 else
6778 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
6779 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
6780 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
6781 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
6782 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
6783 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6784 rt2x00_rt(rt2x00dev, RT3090) ||
6785 rt2x00_rt(rt2x00dev, RT3390)) {
16d571bb 6786 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
da8064c2
SG		 6787 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6788 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
6789 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
6790 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
6791 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
6792 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6793
16d571bb 6794 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
da8064c2
SG		 6795 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
6796 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
6797
16d571bb 6798 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
da8064c2
SG		 6799 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
6800 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
6801
16d571bb 6802 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
da8064c2
SG		 6803 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
6804 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
6805 }
6806}
6807
ab7078ac
GJ		 6808static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
6809{
6810 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6811 u8 rfcsr;
6812 u8 tx_gain;
6813
16d571bb 6814 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
ab7078ac
GJ		 6815 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
6816 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
6817
16d571bb 6818 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
ab7078ac
GJ		 6819 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
6820 RFCSR17_TXMIXER_GAIN);
6821 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
6822 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
6823
16d571bb 6824 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
ab7078ac
GJ		 6825 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
6826 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
6827
16d571bb 6828 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
ab7078ac
GJ		 6829 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
6830 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
6831
16d571bb 6832 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
ab7078ac
GJ		 6833 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6834 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
6835 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6836
16d571bb 6837 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
ab7078ac
GJ		 6838 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
6839 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
6840
6841 /* TODO: enable stream mode */
6842}
6843
f7df8fe5
SG		 6844static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
6845{
6846 u8 reg;
6847 u16 eeprom;
6848
6849 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
6850 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 6851 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 6852 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6853 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
6854 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6855 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
6856 rt2800_bbp_write(rt2x00dev, 138, reg);
6857
16d571bb 6858 reg = rt2800_rfcsr_read(rt2x00dev, 38);
f7df8fe5
SG		 6859 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
6860 rt2800_rfcsr_write(rt2x00dev, 38, reg);
6861
16d571bb 6862 reg = rt2800_rfcsr_read(rt2x00dev, 39);
f7df8fe5
SG		 6863 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
6864 rt2800_rfcsr_write(rt2x00dev, 39, reg);
6865
6866 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6867
16d571bb 6868 reg = rt2800_rfcsr_read(rt2x00dev, 30);
f7df8fe5
SG		 6869 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
6870 rt2800_rfcsr_write(rt2x00dev, 30, reg);
6871}
6872
d5374ef1
SG		 6873static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
6874{
ce94ede9
SG		 6875 rt2800_rf_init_calibration(rt2x00dev, 30);
6876
d5374ef1
SG		 6877 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
6878 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
6879 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
6880 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
6881 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6882 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6883 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6884 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
6885 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6886 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6887 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6888 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6889 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6890 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6891 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6892 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6893 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6894 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6895 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6896 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6897 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6898 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6899 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6900 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6901 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6902 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6903 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6904 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6905 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6906 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6907 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6908 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6909}
6910
6911static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6912{
c9a221b2
SG		 6913 u8 rfcsr;
6914 u16 eeprom;
6915 u32 reg;
6916
ce94ede9
SG		 6917 /* XXX vendor driver do this only for 3070 */
6918 rt2800_rf_init_calibration(rt2x00dev, 30);
6919
d5374ef1
SG		 6920 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6921 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6922 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6923 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6924 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6925 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6926 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6927 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6928 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6929 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6930 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6931 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6932 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6933 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6934 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6935 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6936 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6937 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6938 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6939
6940 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6941 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6942 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6943 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6944 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6945 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6946 rt2x00_rt(rt2x00dev, RT3090)) {
6947 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6948
16d571bb 6949 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
c9a221b2
SG		 6950 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6951 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6952
6953 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6954 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6955 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6956 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6957 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6958 &eeprom);
c9a221b2
SG		 6959 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6960 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6961 else
6962 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6963 }
6964 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6965
6966 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6967 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6968 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6969 }
c5b3c350
SG		 6970
6971 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6972
6973 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6974 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6975 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6976 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6977
6978 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6979 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6980}
6981
6982static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6983{
f9cdcbb1
SG		 6984 u8 rfcsr;
6985
ce94ede9
SG		 6986 rt2800_rf_init_calibration(rt2x00dev, 2);
6987
d5374ef1
SG		 6988 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6989 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6990 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6991 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6992 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6993 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6994 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6995 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6996 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6997 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6998 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6999 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7000 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7001 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7002 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7003 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7004 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7005 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7006 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7007 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7008 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7009 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7010 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7011 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7012 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7013 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7014 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7015 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7016 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7017 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7018 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7019 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7020 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7021 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7022 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7023 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7024 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7025 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7026 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7027 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7028 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7029 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7030 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7031 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7032 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7033 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1 7034
16d571bb 7035 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
f9cdcbb1
SG		 7036 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7037 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 7038
7039 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7040 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7041}
7042
7043static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7044{
1f242a3d 7045 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
dab38e7d 7046 &rt2x00dev->cap_flags);
1f242a3d 7047 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
dab38e7d
DG		 7048 &rt2x00dev->cap_flags);
7049 u8 rfcsr;
7050
ce94ede9
SG		 7051 rt2800_rf_init_calibration(rt2x00dev, 30);
7052
d5374ef1
SG		 7053 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7054 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7055 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7056 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7057 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7058 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7059 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7060 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7061 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7062 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7063 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7064 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7065 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7066 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7067 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7068 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7069 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7070 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7071 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7072 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7073 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7074 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7075 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7076 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7077 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7078 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7079 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7080 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7081 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7082 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7083 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7084 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7085 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
dab38e7d 7086 rfcsr = 0x01;
1f242a3d 7087 if (tx0_ext_pa)
dab38e7d 7088 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
1f242a3d 7089 if (tx1_ext_pa)
dab38e7d
DG		 7090 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7091 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
d5374ef1
SG		 7092 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7093 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7094 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7095 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7096 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7097 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
dab38e7d 7098 rfcsr = 0x52;
1f242a3d 7099 if (!tx0_ext_pa) {
dab38e7d
DG		 7100 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7101 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7102 }
7103 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7104 rfcsr = 0x52;
1f242a3d 7105 if (!tx1_ext_pa) {
dab38e7d
DG		 7106 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7107 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7108 }
7109 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
d5374ef1
SG		 7110 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7111 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7112 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7113 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7114 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7115 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7116 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
dab38e7d 7117 rfcsr = 0x2d;
1f242a3d 7118 if (tx0_ext_pa)
dab38e7d 7119 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
1f242a3d 7120 if (tx1_ext_pa)
dab38e7d
DG		 7121 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7122 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
1f242a3d
DG		 7123 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7124 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7125 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7126 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7127 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7128 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7129 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7130 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
d5374ef1
SG		 7131 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7132 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7133 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7134 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7135 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 7136
7137 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 7138 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7139 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7140}
7141
7142static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7143{
2971e66f
SG		 7144 u32 reg;
7145
ce94ede9
SG		 7146 rt2800_rf_init_calibration(rt2x00dev, 30);
7147
d5374ef1
SG		 7148 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7149 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7150 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7151 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7152 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7153 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7154 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7155 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7156 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7157 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7158 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7159 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7160 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7161 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7162 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7163 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7164 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7165 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7166 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7167 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7168 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7169 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7170 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7171 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7172 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7173 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7174 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7175 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7176 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7177 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7178 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7179 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 7180
7181 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
7182 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7183 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 7184
7185 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 7186
7187 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7188 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 7189
7190 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7191 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7192}
7193
7194static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7195{
87d91db9
SG		 7196 u8 rfcsr;
7197 u32 reg;
7198
ce94ede9
SG		 7199 rt2800_rf_init_calibration(rt2x00dev, 30);
7200
d5374ef1
SG		 7201 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7202 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7203 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7204 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7205 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7206 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7207 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7208 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7209 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7210 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7211 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7212 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7213 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7214 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7215 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7216 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7217 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7218 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7219 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7220 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7221 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7222 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7223 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7224 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7225 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7226 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7227 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7228 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7229 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7230 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7231 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9 7232
16d571bb 7233 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
87d91db9
SG		 7234 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7235 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7236
7237 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7238 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7239 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7240 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7241 msleep(1);
7242 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7243 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7244 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7245 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 7246
7247 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 7248 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 7249 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 7250}
7251
d63f7e8c
GJ		 7252static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7253{
7254 u8 bbp;
7255 bool txbf_enabled = false; /* FIXME */
7256
7257 rt2800_bbp_read(rt2x00dev, 105, &bbp);
7258 if (rt2x00dev->default_ant.rx_chain_num == 1)
7259 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7260 else
7261 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7262 rt2800_bbp_write(rt2x00dev, 105, bbp);
7263
7264 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7265
7266 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7267 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7268 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7269 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7270 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7271 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7272 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7273 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7274
7275 if (txbf_enabled)
7276 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7277 else
7278 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7279
7280 /* SNR mapping */
7281 rt2800_bbp_write(rt2x00dev, 142, 6);
7282 rt2800_bbp_write(rt2x00dev, 143, 160);
7283 rt2800_bbp_write(rt2x00dev, 142, 7);
7284 rt2800_bbp_write(rt2x00dev, 143, 161);
7285 rt2800_bbp_write(rt2x00dev, 142, 8);
7286 rt2800_bbp_write(rt2x00dev, 143, 162);
7287
7288 /* ADC/DAC control */
7289 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7290
7291 /* RX AGC energy lower bound in log2 */
7292 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7293
7294 /* FIXME: BBP 105 owerwrite? */
7295 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 7296
d63f7e8c
GJ		 7297}
7298
ab7078ac
GJ		 7299static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7300{
7301 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7302 u32 reg;
7303 u8 rfcsr;
7304
7305 /* Disable GPIO #4 and #7 function for LAN PE control */
7306 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
7307 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7308 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7309 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7310
7311 /* Initialize default register values */
7312 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7313 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7314 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7315 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7316 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7317 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7318 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7319 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7320 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7321 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7322 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7323 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7324 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7325 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7326 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7327 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7328 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7329 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7330 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7331 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7332 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7333 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7334 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7335 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7336 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7337 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7338 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7339 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7340 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7341 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7342 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7343 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7344
7345 /* Initiate calibration */
7346 /* TODO: use rt2800_rf_init_calibration ? */
16d571bb 7347 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
ab7078ac
GJ		 7348 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7349 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7350
88452541 7351 rt2800_freq_cal_mode1(rt2x00dev);
ab7078ac 7352
16d571bb 7353 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
ab7078ac
GJ		 7354 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7355 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7356
7357 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7358 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7359 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7360 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7361 usleep_range(1000, 1500);
7362 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
7363 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7364 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7365
7366 /* Set initial values for RX filter calibration */
7367 drv_data->calibration_bw20 = 0x1f;
7368 drv_data->calibration_bw40 = 0x2f;
7369
7370 /* Save BBP 25 & 26 values for later use in channel switching */
7371 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
7372 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
7373
7374 rt2800_led_open_drain_enable(rt2x00dev);
7375 rt2800_normal_mode_setup_3593(rt2x00dev);
7376
d63f7e8c 7377 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 7378
7379 /* TODO: enable stream mode support */
7380}
7381
98e71f44
SV		 7382static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7383{
7384 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7385 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7386 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7387 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7388 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7389 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7390 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7391 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7392 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7393 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7394 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7395 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7396 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7397 if (rt2800_clk_is_20mhz(rt2x00dev))
7398 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7399 else
7400 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7401 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7402 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7403 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7404 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7405 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7406 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7407 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7408 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7409 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7410 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7411 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7412 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7413 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7414 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7415 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7416 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7417 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7418 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7419 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7420 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7421 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7422 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7423 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7424 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7425 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7426 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7427 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7428 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7429 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7430 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7431 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7432 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7433 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7434 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7435 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7436 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7437 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7438 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7439 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7440 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7441 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7442 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7443 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7444 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7445 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7446 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7447 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7448 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7449 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7450}
7451
d5374ef1
SG		 7452static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
7453{
ce94ede9
SG		 7454 rt2800_rf_init_calibration(rt2x00dev, 2);
7455
d5374ef1
SG		 7456 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7457 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7458 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7459 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7460 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7461 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7462 else
7463 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7464 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7465 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7466 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 7467 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 7468 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7469 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7470 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7471 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7472 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7473 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7474
7475 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7476 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7477 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7478 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7479 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 7480 if (rt2x00_is_usb(rt2x00dev) &&
7481 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 7482 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7483 else
7484 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
7485 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7486 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7487 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7488 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7489
7122e660 7490 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 7491 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7492 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7493 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7494 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7495 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7496 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7497 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7498 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7499 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7500
c8520bcb 7501 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 7502 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7503 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
7504 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
7505 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7506 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7507 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7508 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7509 else
7510 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
7511 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7512 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7513 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7514
7515 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7516 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7517 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7518 else
7519 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
7520 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7521 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 7522 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7523 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
7524 else
7525 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 7526 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7527 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 7528 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 7529
7530 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 7531 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
7532 if (rt2x00_is_usb(rt2x00dev))
7533 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7534 else
7535 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
7536 } else {
7537 if (rt2x00_is_usb(rt2x00dev))
7538 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
7539 else
7540 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
7541 }
d5374ef1
SG		 7542 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7543 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 7544
7545 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 7546
7547 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 7548}
7549
7550static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
7551{
ce94ede9
SG		 7552 rt2800_rf_init_calibration(rt2x00dev, 2);
7553
d5374ef1 7554 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 7555 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7556 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7557 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7558 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7559 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7560 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7561 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7562 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7563 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7564 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7565 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7566 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7567 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
7568 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7569 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
7570 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7571 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
7572 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
7573 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7574 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7575 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7576 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7577 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7578 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7579 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7580 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
7581 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7582 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7583 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7584 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7585 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7586 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
7587 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7588 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
7589 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7590 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7591 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7592 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7593 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7594 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7595 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
7596 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7597 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7598 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
7599 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
7600 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
7601 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
7602 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7603 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7604 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
7605 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7606 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7607 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
7608 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7609 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
7610 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
7611 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 7612
7613 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 7614
7615 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 7616}
7617
0c9e5fb9
SG		 7618static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
7619{
ce94ede9
SG		 7620 rt2800_rf_init_calibration(rt2x00dev, 30);
7621
0c9e5fb9
SG		 7622 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
7623 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 7624 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7625 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
7626 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7627 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7628 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7629 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7630 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7631 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
7632 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
7633 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
7634 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7635 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7636 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7637 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7638 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7639 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7640 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
7641 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
7642 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7643
7644 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7645 msleep(1);
7646
88452541 7647 rt2800_freq_cal_mode1(rt2x00dev);
c630ccf1 7648
c630ccf1
SG		 7649 /* Enable DC filter */
7650 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7651 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7652
f7df8fe5 7653 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 7654
7655 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
7656 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 7657
7658 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 7659}
7660
41977e86
RY		 7661static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
7662 bool set_bw, bool is_ht40)
7663{
7664 u8 bbp_val;
7665
7666 rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
7667 bbp_val |= 0x1;
7668 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7669 usleep_range(100, 200);
7670
7671 if (set_bw) {
7672 rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
7673 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
7674 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7675 usleep_range(100, 200);
7676 }
7677
7678 rt2800_bbp_read(rt2x00dev, 21, &bbp_val);
7679 bbp_val &= (~0x1);
7680 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7681 usleep_range(100, 200);
7682}
7683
7684static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
7685{
7686 u8 rf_val;
7687
7688 if (btxcal)
7689 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
7690 else
7691 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
7692
7693 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
7694
16d571bb 7695 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
41977e86
RY		 7696 rf_val |= 0x80;
7697 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
7698
7699 if (btxcal) {
7700 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
7701 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
7702 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
16d571bb 7703 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
41977e86
RY		 7704 rf_val &= (~0x3F);
7705 rf_val |= 0x3F;
7706 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
16d571bb 7707 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
41977e86
RY		 7708 rf_val &= (~0x3F);
7709 rf_val |= 0x3F;
7710 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7711 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
7712 } else {
7713 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
7714 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
7715 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
16d571bb 7716 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
41977e86
RY		 7717 rf_val &= (~0x3F);
7718 rf_val |= 0x34;
7719 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
16d571bb 7720 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
41977e86
RY		 7721 rf_val &= (~0x3F);
7722 rf_val |= 0x34;
7723 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7724 }
7725
7726 return 0;
7727}
7728
7729static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
7730{
7731 unsigned int cnt;
7732 u8 bbp_val;
7733 char cal_val;
7734
7735 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
7736
7737 cnt = 0;
7738 do {
7739 usleep_range(500, 2000);
7740 rt2800_bbp_read(rt2x00dev, 159, &bbp_val);
7741 if (bbp_val == 0x02 || cnt == 20)
7742 break;
7743
7744 cnt++;
7745 } while (cnt < 20);
7746
7747 rt2800_bbp_dcoc_read(rt2x00dev, 0x39, &bbp_val);
7748 cal_val = bbp_val & 0x7F;
7749 if (cal_val >= 0x40)
7750 cal_val -= 128;
7751
7752 return cal_val;
7753}
7754
7755static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
7756 bool btxcal)
7757{
7758 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7759 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
7760 u8 filter_target;
7761 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
7762 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
7763 int loop = 0, is_ht40, cnt;
7764 u8 bbp_val, rf_val;
7765 char cal_r32_init, cal_r32_val, cal_diff;
7766 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
7767 u8 saverfb5r06, saverfb5r07;
7768 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
7769 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
7770 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
7771 u8 saverfb5r58, saverfb5r59;
7772 u8 savebbp159r0, savebbp159r2, savebbpr23;
7773 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
7774
7775 /* Save MAC registers */
7776 rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0);
7777 rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0);
7778
7779 /* save BBP registers */
7780 rt2800_bbp_read(rt2x00dev, 23, &savebbpr23);
7781
7782 rt2800_bbp_dcoc_read(rt2x00dev, 0, &savebbp159r0);
7783 rt2800_bbp_dcoc_read(rt2x00dev, 2, &savebbp159r2);
7784
7785 /* Save RF registers */
16d571bb
AB		 7786 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7787 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7788 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7789 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7790 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
7791 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7792 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7793 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7794 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7795 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
7796 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
7797 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
7798
7799 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
7800 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
7801 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
7802 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
7803 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
7804 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
7805 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
7806 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
7807 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
7808 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
7809
7810 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7811 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7812
7813 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
41977e86
RY		 7814 rf_val |= 0x3;
7815 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7816
16d571bb 7817 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
41977e86
RY		 7818 rf_val |= 0x1;
7819 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
7820
7821 cnt = 0;
7822 do {
7823 usleep_range(500, 2000);
16d571bb 7824 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
41977e86
RY		 7825 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
7826 break;
7827 cnt++;
7828 } while (cnt < 40);
7829
16d571bb 7830 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
41977e86
RY		 7831 rf_val &= (~0x3);
7832 rf_val |= 0x1;
7833 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7834
7835 /* I-3 */
7836 rt2800_bbp_read(rt2x00dev, 23, &bbp_val);
7837 bbp_val &= (~0x1F);
7838 bbp_val |= 0x10;
7839 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
7840
7841 do {
7842 /* I-4,5,6,7,8,9 */
7843 if (loop == 0) {
7844 is_ht40 = false;
7845
7846 if (btxcal)
7847 filter_target = tx_filter_target_20m;
7848 else
7849 filter_target = rx_filter_target_20m;
7850 } else {
7851 is_ht40 = true;
7852
7853 if (btxcal)
7854 filter_target = tx_filter_target_40m;
7855 else
7856 filter_target = rx_filter_target_40m;
7857 }
7858
16d571bb 7859 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
41977e86
RY		 7860 rf_val &= (~0x04);
7861 if (loop == 1)
7862 rf_val |= 0x4;
7863
7864 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
7865
7866 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
7867
7868 rt2800_rf_lp_config(rt2x00dev, btxcal);
7869 if (btxcal) {
7870 tx_agc_fc = 0;
16d571bb 7871 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
41977e86
RY		 7872 rf_val &= (~0x7F);
7873 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
16d571bb 7874 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
41977e86
RY		 7875 rf_val &= (~0x7F);
7876 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7877 } else {
7878 rx_agc_fc = 0;
16d571bb 7879 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
41977e86
RY		 7880 rf_val &= (~0x7F);
7881 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
16d571bb 7882 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
41977e86
RY		 7883 rf_val &= (~0x7F);
7884 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7885 }
7886
7887 usleep_range(1000, 2000);
7888
7889 rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
7890 bbp_val &= (~0x6);
7891 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7892
7893 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7894
7895 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7896
7897 rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val);
7898 bbp_val |= 0x6;
7899 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7900do_cal:
7901 if (btxcal) {
16d571bb 7902 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
41977e86
RY		 7903 rf_val &= (~0x7F);
7904 rf_val |= tx_agc_fc;
7905 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
16d571bb 7906 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
41977e86
RY		 7907 rf_val &= (~0x7F);
7908 rf_val |= tx_agc_fc;
7909 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7910 } else {
16d571bb 7911 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
41977e86
RY		 7912 rf_val &= (~0x7F);
7913 rf_val |= rx_agc_fc;
7914 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
16d571bb 7915 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
41977e86
RY		 7916 rf_val &= (~0x7F);
7917 rf_val |= rx_agc_fc;
7918 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7919 }
7920
7921 usleep_range(500, 1000);
7922
7923 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7924
7925 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7926
7927 cal_diff = cal_r32_init - cal_r32_val;
7928
7929 if (btxcal)
7930 cmm_agc_fc = tx_agc_fc;
7931 else
7932 cmm_agc_fc = rx_agc_fc;
7933
7934 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
7935 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
7936 if (btxcal)
7937 tx_agc_fc = 0;
7938 else
7939 rx_agc_fc = 0;
7940 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
7941 if (btxcal)
7942 tx_agc_fc++;
7943 else
7944 rx_agc_fc++;
7945 goto do_cal;
7946 }
7947
7948 if (btxcal) {
7949 if (loop == 0)
7950 drv_data->tx_calibration_bw20 = tx_agc_fc;
7951 else
7952 drv_data->tx_calibration_bw40 = tx_agc_fc;
7953 } else {
7954 if (loop == 0)
7955 drv_data->rx_calibration_bw20 = rx_agc_fc;
7956 else
7957 drv_data->rx_calibration_bw40 = rx_agc_fc;
7958 }
7959
7960 loop++;
7961 } while (loop <= 1);
7962
7963 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
7964 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
7965 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
7966 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
7967 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
7968 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
7969 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
7970 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
7971 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
7972 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
7973 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
7974 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
7975
7976 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
7977 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
7978 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
7979 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
7980 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
7981 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
7982 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
7983 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
7984 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
7985 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
7986
7987 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
7988 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
7989
7990 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
7991
7992 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
7993 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
7994
7995 rt2800_bbp_read(rt2x00dev, 4, &bbp_val);
7996 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
7997 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
7998 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7999
8000 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8001 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8002}
8003
8004static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8005{
8006 /* Initialize RF central register to default value */
8007 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8008 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8009 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8010 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8011 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8012 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8013 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8014 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8015 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8016 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8017 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8018 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8019 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8020 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8021 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8022 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8023 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8024 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8025 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8026 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8027 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8028 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8029 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8030 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8031 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8032 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8033 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8034 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8035 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8036 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8037 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8038 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8039 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8040 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8041 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8042 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8043 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8044 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8045 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8046 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8047 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8048 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8049 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8050 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8051
8052 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8053 if (rt2800_clk_is_20mhz(rt2x00dev))
8054 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8055 else
8056 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8057 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8058 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8059 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8060 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8061 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8062 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8063 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8064 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8065 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8066 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8067 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8068 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8069 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8070 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8071 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8072 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8073
8074 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8075 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8076 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8077
8078 /* Initialize RF channel register to default value */
8079 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8080 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8081 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8082 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8083 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8084 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8085 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8086 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8087 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8088 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8089 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8090 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8091 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8092 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8093 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8094 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8095 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8096 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8097 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8098 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8099 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8100 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8101 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8102 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8103 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8104 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8105 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8106 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8107 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8108 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8109 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8110 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8111 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8112 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8113 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8114 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8115 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8116 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8117 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8118 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8119 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8120 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8121 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8122 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8123 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8124 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8125 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8126 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8127 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8128 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8129 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8130 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8131 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8132 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8133 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8134 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8135 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8136 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8137 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8138 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8139
8140 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8141
8142 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8143 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8144 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8145 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8146 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8147 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8148 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8149 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8150 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8151 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8152 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8153 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8154 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8155 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8156 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8157 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8158 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8159 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
a0597834
TP		 8160 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8161 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
41977e86 8162 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
a0597834
TP		 8163 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8164 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
41977e86
RY		 8165 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8166 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8167 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8168 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8169 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8170 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8171 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8172
8173 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8174 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8175 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8176 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8177 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8178 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8179 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8180 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8181 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8182
8183 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8184 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8185 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8186 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8187 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8188 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8189
8190 /* Initialize RF channel register for DRQFN */
8191 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8192 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8193 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8194 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8195 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8196 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8197 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8198 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8199
8200 /* Initialize RF DC calibration register to default value */
8201 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8202 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8203 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8204 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8205 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8206 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8207 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8208 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8209 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8210 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8211 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8212 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8213 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8214 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8215 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8216 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8217 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8218 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8219 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8220 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8221 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8222 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8223 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8224 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8225 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8226 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8227 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8228 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8229 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8230 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8231 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8232 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8233 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8234 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8235 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8236 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8237 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8238 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8239 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8240 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8241 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8242 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8243 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8244 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8245 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8246 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8247 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8248 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8249 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8250 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8251 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8252 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8253 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8254 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8255 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8256 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8257 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8258 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8259 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8260
8261 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8262 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8263 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8264
8265 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8266 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8267
8268 rt2800_bw_filter_calibration(rt2x00dev, true);
8269 rt2800_bw_filter_calibration(rt2x00dev, false);
8270}
8271
074f2529 8272static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 8273{
d5374ef1
SG		 8274 if (rt2800_is_305x_soc(rt2x00dev)) {
8275 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 8276 return;
d5374ef1
SG		 8277 }
8278
8279 switch (rt2x00dev->chip.rt) {
8280 case RT3070:
8281 case RT3071:
8282 case RT3090:
8283 rt2800_init_rfcsr_30xx(rt2x00dev);
8284 break;
8285 case RT3290:
8286 rt2800_init_rfcsr_3290(rt2x00dev);
8287 break;
8288 case RT3352:
8289 rt2800_init_rfcsr_3352(rt2x00dev);
8290 break;
8291 case RT3390:
8292 rt2800_init_rfcsr_3390(rt2x00dev);
8293 break;
8294 case RT3572:
8295 rt2800_init_rfcsr_3572(rt2x00dev);
8296 break;
ab7078ac
GJ		 8297 case RT3593:
8298 rt2800_init_rfcsr_3593(rt2x00dev);
8299 break;
98e71f44
SV		 8300 case RT5350:
8301 rt2800_init_rfcsr_5350(rt2x00dev);
8302 break;
d5374ef1
SG		 8303 case RT5390:
8304 rt2800_init_rfcsr_5390(rt2x00dev);
8305 break;
8306 case RT5392:
8307 rt2800_init_rfcsr_5392(rt2x00dev);
8308 break;
0c9e5fb9
SG		 8309 case RT5592:
8310 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 8311 break;
41977e86
RY		 8312 case RT6352:
8313 rt2800_init_rfcsr_6352(rt2x00dev);
8314 break;
8cdd15e0 8315 }
fcf51541 8316}
b9a07ae9
ID		 8317
8318int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8319{
8320 u32 reg;
8321 u16 word;
8322
8323 /*
61edc7fa 8324 * Initialize MAC registers.
b9a07ae9
ID		 8325 */
8326 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 8327 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 8328 return -EIO;
8329
61edc7fa
SG		 8330 /*
8331 * Wait BBP/RF to wake up.
8332 */
f4e1a4d3
SG		 8333 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8334 return -EIO;
8335
b9a07ae9 8336 /*
61edc7fa 8337 * Send signal during boot time to initialize firmware.
b9a07ae9 8338 */
c630ccf1
SG		 8339 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8340 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 8341 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 8342 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 8343 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 8344 msleep(1);
8345
61edc7fa
SG		 8346 /*
8347 * Make sure BBP is up and running.
8348 */
f4e1a4d3 8349 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 8350 return -EIO;
b9a07ae9 8351
61edc7fa
SG		 8352 /*
8353 * Initialize BBP/RF registers.
8354 */
a1ef5039 8355 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 8356 rt2800_init_rfcsr(rt2x00dev);
8357
b9a07ae9
ID		 8358 if (rt2x00_is_usb(rt2x00dev) &&
8359 (rt2x00_rt(rt2x00dev, RT3070) ||
8360 rt2x00_rt(rt2x00dev, RT3071) ||
8361 rt2x00_rt(rt2x00dev, RT3572))) {
8362 udelay(200);
8363 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
8364 udelay(10);
8365 }
8366
8367 /*
8368 * Enable RX.
8369 */
8370 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
8371 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8372 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8373 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8374
8375 udelay(50);
8376
8377 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
8378 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
8379 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
b9a07ae9
ID		 8380 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
8381 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
8382
8383 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
8384 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8385 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
8386 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8387
8388 /*
8389 * Initialize LED control
8390 */
3e38d3da 8391 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 8392 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 8393 word & 0xff, (word >> 8) & 0xff);
8394
3e38d3da 8395 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 8396 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 8397 word & 0xff, (word >> 8) & 0xff);
8398
3e38d3da 8399 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 8400 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 8401 word & 0xff, (word >> 8) & 0xff);
8402
8403 return 0;
8404}
8405EXPORT_SYMBOL_GPL(rt2800_enable_radio);
8406
8407void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
8408{
8409 u32 reg;
8410
f7b395e9 8411 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 8412
8413 /* Wait for DMA, ignore error */
8414 rt2800_wait_wpdma_ready(rt2x00dev);
8415
8416 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
8417 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
8418 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8419 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 8420}
8421EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 8422
30e84034
BZ		 8423int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
8424{
8425 u32 reg;
a89534ed 8426 u16 efuse_ctrl_reg;
30e84034 8427
a89534ed
WH		 8428 if (rt2x00_rt(rt2x00dev, RT3290))
8429 efuse_ctrl_reg = EFUSE_CTRL_3290;
8430 else
8431 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 8432
a89534ed 8433 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 8434 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
8435}
8436EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
8437
8438static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
8439{
8440 u32 reg;
a89534ed
WH		 8441 u16 efuse_ctrl_reg;
8442 u16 efuse_data0_reg;
8443 u16 efuse_data1_reg;
8444 u16 efuse_data2_reg;
8445 u16 efuse_data3_reg;
8446
8447 if (rt2x00_rt(rt2x00dev, RT3290)) {
8448 efuse_ctrl_reg = EFUSE_CTRL_3290;
8449 efuse_data0_reg = EFUSE_DATA0_3290;
8450 efuse_data1_reg = EFUSE_DATA1_3290;
8451 efuse_data2_reg = EFUSE_DATA2_3290;
8452 efuse_data3_reg = EFUSE_DATA3_3290;
8453 } else {
8454 efuse_ctrl_reg = EFUSE_CTRL;
8455 efuse_data0_reg = EFUSE_DATA0;
8456 efuse_data1_reg = EFUSE_DATA1;
8457 efuse_data2_reg = EFUSE_DATA2;
8458 efuse_data3_reg = EFUSE_DATA3;
8459 }
31a4cf1f
GW		 8460 mutex_lock(&rt2x00dev->csr_mutex);
8461
a89534ed 8462 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 8463 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
8464 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
8465 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 8466 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 8467
8468 /* Wait until the EEPROM has been loaded */
a89534ed 8469 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 8470 /* Apparently the data is read from end to start */
a89534ed 8471 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 8472 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 8473 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 8474 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 8475 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 8476 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 8477 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 8478 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 8479 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 8480
8481 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 8482}
8483
a02308e9 8484int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 8485{
8486 unsigned int i;
8487
8488 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
8489 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 8490
8491 return 0;
30e84034
BZ		 8492}
8493EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
8494
a3f1625d
GJ		 8495static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
8496{
8497 u16 word;
8498
6316c786
GJ		 8499 if (rt2x00_rt(rt2x00dev, RT3593))
8500 return 0;
8501
a3f1625d
GJ		 8502 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
8503 if ((word & 0x00ff) != 0x00ff)
8504 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
8505
8506 return 0;
8507}
8508
8509static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
8510{
8511 u16 word;
8512
6316c786
GJ		 8513 if (rt2x00_rt(rt2x00dev, RT3593))
8514 return 0;
8515
a3f1625d
GJ		 8516 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
8517 if ((word & 0x00ff) != 0x00ff)
8518 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
8519
8520 return 0;
8521}
8522
ad417a53 8523static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 8524{
77c06c2c 8525 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 8526 u16 word;
8527 u8 *mac;
8528 u8 default_lna_gain;
a02308e9 8529 int retval;
38bd7b8a 8530
ad417a53
GW		 8531 /*
8532 * Read the EEPROM.
8533 */
a02308e9
GJ		 8534 retval = rt2800_read_eeprom(rt2x00dev);
8535 if (retval)
8536 return retval;
ad417a53 8537
38bd7b8a
BZ		 8538 /*
8539 * Start validation of the data that has been read.
8540 */
3e38d3da 8541 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9766cb70 8542 rt2x00lib_set_mac_address(rt2x00dev, mac);
38bd7b8a 8543
3e38d3da 8544 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 8545 if (word == 0xffff) {
38c8a566
RJH		 8546 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8547 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
8548 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 8549 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 8550 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 8551 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 8552 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 8553 /*
8554 * There is a max of 2 RX streams for RT28x0 series
8555 */
38c8a566
RJH		 8556 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
8557 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 8558 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 8559 }
8560
3e38d3da 8561 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 8562 if (word == 0xffff) {
38c8a566
RJH		 8563 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
8564 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
8565 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
8566 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
8567 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
8568 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
8569 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
8570 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
8571 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
8572 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
8573 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
8574 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
8575 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
8576 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
8577 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 8578 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 8579 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 8580 }
8581
3e38d3da 8582 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 8583 if ((word & 0x00ff) == 0x00ff) {
8584 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 8585 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 8586 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 8587 }
8588 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 8589 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
8590 LED_MODE_TXRX_ACTIVITY);
8591 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 8592 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8593 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
8594 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
8595 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 8596 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 8597 }
8598
8599 /*
8600 * During the LNA validation we are going to use
8601 * lna0 as correct value. Note that EEPROM_LNA
8602 * is never validated.
8603 */
3e38d3da 8604 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 8605 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
8606
3e38d3da 8607 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 8608 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
8609 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
8610 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
8611 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 8612 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 8613
a3f1625d 8614 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 8615
3e38d3da 8616 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 8617 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
8618 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 8619 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8620 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
8621 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
8622 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
8623 default_lna_gain);
8624 }
3e38d3da 8625 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 8626
a3f1625d 8627 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 8628
3e38d3da 8629 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 8630 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
8631 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
8632 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
8633 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 8634 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 8635
3e38d3da 8636 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 8637 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
8638 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 8639 if (!rt2x00_rt(rt2x00dev, RT3593)) {
8640 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
8641 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
8642 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
8643 default_lna_gain);
8644 }
3e38d3da 8645 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 8646
f36bb0ca
GJ		 8647 if (rt2x00_rt(rt2x00dev, RT3593)) {
8648 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
8649 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
8650 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
8651 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8652 default_lna_gain);
8653 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
8654 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
8655 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8656 default_lna_gain);
8657 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
8658 }
8659
38bd7b8a
BZ		 8660 return 0;
8661}
38bd7b8a 8662
ad417a53 8663static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 8664{
38bd7b8a
BZ		 8665 u16 value;
8666 u16 eeprom;
86868b26 8667 u16 rf;
38bd7b8a 8668
86868b26
GJ		 8669 /*
8670 * Read EEPROM word for configuration.
8671 */
3e38d3da 8672 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 8673
8674 /*
8675 * Identify RF chipset by EEPROM value
8676 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
8677 * RT53xx: defined in "EEPROM_CHIP_ID" field
8678 */
8679 if (rt2x00_rt(rt2x00dev, RT3290) ||
8680 rt2x00_rt(rt2x00dev, RT5390) ||
41977e86
RY		 8681 rt2x00_rt(rt2x00dev, RT5392) ||
8682 rt2x00_rt(rt2x00dev, RT6352))
3e38d3da 8683 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
b8c2db58
FF		 8684 else if (rt2x00_rt(rt2x00dev, RT3352))
8685 rf = RF3322;
98e71f44
SV		 8686 else if (rt2x00_rt(rt2x00dev, RT5350))
8687 rf = RF5350;
86868b26
GJ		 8688 else
8689 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
8690
8691 switch (rf) {
d331eb51
LF		 8692 case RF2820:
8693 case RF2850:
8694 case RF2720:
8695 case RF2750:
8696 case RF3020:
8697 case RF2020:
8698 case RF3021:
8699 case RF3022:
8700 case RF3052:
0f5af26a 8701 case RF3053:
3b9b74ba 8702 case RF3070:
a89534ed 8703 case RF3290:
d331eb51 8704 case RF3320:
03839951 8705 case RF3322:
98e71f44 8706 case RF5350:
ccf91bd6 8707 case RF5360:
ac0372ab 8708 case RF5362:
d331eb51 8709 case RF5370:
2ed71884 8710 case RF5372:
d331eb51 8711 case RF5390:
cff3d1f0 8712 case RF5392:
b8863f8b 8713 case RF5592:
41977e86 8714 case RF7620:
d331eb51
LF		 8715 break;
8716 default:
ec9c4989
JP		 8717 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
8718 rf);
38bd7b8a
BZ		 8719 return -ENODEV;
8720 }
8721
86868b26
GJ		 8722 rt2x00_set_rf(rt2x00dev, rf);
8723
38bd7b8a
BZ		 8724 /*
8725 * Identify default antenna configuration.
8726 */
d96aa640 8727 rt2x00dev->default_ant.tx_chain_num =
38c8a566 8728 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 8729 rt2x00dev->default_ant.rx_chain_num =
38c8a566 8730 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 8731
3e38d3da 8732 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 8733
8734 if (rt2x00_rt(rt2x00dev, RT3070) ||
8735 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 8736 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 8737 rt2x00_rt(rt2x00dev, RT3390)) {
8738 value = rt2x00_get_field16(eeprom,
8739 EEPROM_NIC_CONF1_ANT_DIVERSITY);
8740 switch (value) {
8741 case 0:
8742 case 1:
8743 case 2:
8744 rt2x00dev->default_ant.tx = ANTENNA_A;
8745 rt2x00dev->default_ant.rx = ANTENNA_A;
8746 break;
8747 case 3:
8748 rt2x00dev->default_ant.tx = ANTENNA_A;
8749 rt2x00dev->default_ant.rx = ANTENNA_B;
8750 break;
8751 }
8752 } else {
8753 rt2x00dev->default_ant.tx = ANTENNA_A;
8754 rt2x00dev->default_ant.rx = ANTENNA_A;
8755 }
8756
0586a11b
AA		 8757 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
8758 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
8759 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
8760 }
8761
38bd7b8a 8762 /*
9328fdac 8763 * Determine external LNA informations.
38bd7b8a 8764 */
38c8a566 8765 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 8766 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 8767 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 8768 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 8769
8770 /*
8771 * Detect if this device has an hardware controlled radio.
8772 */
38c8a566 8773 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 8774 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 8775
fdbc7b0a
GW		 8776 /*
8777 * Detect if this device has Bluetooth co-existence.
8778 */
dab38e7d
DG		 8779 if (!rt2x00_rt(rt2x00dev, RT3352) &&
8780 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
fdbc7b0a
GW		 8781 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
8782
9328fdac
GW		 8783 /*
8784 * Read frequency offset and RF programming sequence.
8785 */
3e38d3da 8786 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 8787 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
8788
38bd7b8a
BZ		 8789 /*
8790 * Store led settings, for correct led behaviour.
8791 */
8792#ifdef CONFIG_RT2X00_LIB_LEDS
8793 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
8794 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
8795 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
8796
9328fdac 8797 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 8798#endif /* CONFIG_RT2X00_LIB_LEDS */
8799
e90c54b2
RJH		 8800 /*
8801 * Check if support EIRP tx power limit feature.
8802 */
3e38d3da 8803 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 8804
8805 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
8806 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 8807 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 8808
dab38e7d
DG		 8809 /*
8810 * Detect if device uses internal or external PA
8811 */
8812 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
8813
8814 if (rt2x00_rt(rt2x00dev, RT3352)) {
1f242a3d 8815 if (rt2x00_get_field16(eeprom,
dab38e7d 8816 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
1f242a3d 8817 __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
dab38e7d 8818 &rt2x00dev->cap_flags);
1f242a3d 8819 if (rt2x00_get_field16(eeprom,
dab38e7d 8820 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
1f242a3d 8821 __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
dab38e7d
DG		 8822 &rt2x00dev->cap_flags);
8823 }
8824
38bd7b8a
BZ		 8825 return 0;
8826}
38bd7b8a 8827
4da2933f 8828/*
55f9321a 8829 * RF value list for rt28xx
4da2933f
BZ		 8830 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
8831 */
8832static const struct rf_channel rf_vals[] = {
8833 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
8834 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
8835 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
8836 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
8837 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
8838 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
8839 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
8840 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
8841 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
8842 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
8843 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
8844 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
8845 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
8846 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
8847
8848 /* 802.11 UNI / HyperLan 2 */
8849 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
8850 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
8851 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
8852 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
8853 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
8854 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
8855 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
8856 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
8857 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
8858 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
8859 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
8860 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
8861
8862 /* 802.11 HyperLan 2 */
8863 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
8864 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
8865 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
8866 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
8867 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
8868 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
8869 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
8870 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
8871 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
8872 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
8873 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
8874 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
8875 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
8876 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
8877 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
8878 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
8879
8880 /* 802.11 UNII */
8881 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
8882 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
8883 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
8884 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
8885 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
8886 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
8887 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
8888 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
8889 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
8890 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
8891 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
8892
8893 /* 802.11 Japan */
8894 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
8895 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
8896 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
8897 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
8898 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
8899 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
8900 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
8901};
8902
8903/*
55f9321a 8904 * RF value list for rt3xxx
b6b561c3 8905 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 8906 */
55f9321a 8907static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 8908 {1, 241, 2, 2 },
8909 {2, 241, 2, 7 },
8910 {3, 242, 2, 2 },
8911 {4, 242, 2, 7 },
8912 {5, 243, 2, 2 },
8913 {6, 243, 2, 7 },
8914 {7, 244, 2, 2 },
8915 {8, 244, 2, 7 },
8916 {9, 245, 2, 2 },
8917 {10, 245, 2, 7 },
8918 {11, 246, 2, 2 },
8919 {12, 246, 2, 7 },
8920 {13, 247, 2, 2 },
8921 {14, 248, 2, 4 },
55f9321a
ID		 8922
8923 /* 802.11 UNI / HyperLan 2 */
8924 {36, 0x56, 0, 4},
8925 {38, 0x56, 0, 6},
8926 {40, 0x56, 0, 8},
8927 {44, 0x57, 0, 0},
8928 {46, 0x57, 0, 2},
8929 {48, 0x57, 0, 4},
8930 {52, 0x57, 0, 8},
8931 {54, 0x57, 0, 10},
8932 {56, 0x58, 0, 0},
8933 {60, 0x58, 0, 4},
8934 {62, 0x58, 0, 6},
8935 {64, 0x58, 0, 8},
8936
8937 /* 802.11 HyperLan 2 */
8938 {100, 0x5b, 0, 8},
8939 {102, 0x5b, 0, 10},
8940 {104, 0x5c, 0, 0},
8941 {108, 0x5c, 0, 4},
8942 {110, 0x5c, 0, 6},
8943 {112, 0x5c, 0, 8},
8944 {116, 0x5d, 0, 0},
8945 {118, 0x5d, 0, 2},
8946 {120, 0x5d, 0, 4},
8947 {124, 0x5d, 0, 8},
8948 {126, 0x5d, 0, 10},
8949 {128, 0x5e, 0, 0},
8950 {132, 0x5e, 0, 4},
8951 {134, 0x5e, 0, 6},
8952 {136, 0x5e, 0, 8},
8953 {140, 0x5f, 0, 0},
8954
8955 /* 802.11 UNII */
8956 {149, 0x5f, 0, 9},
8957 {151, 0x5f, 0, 11},
8958 {153, 0x60, 0, 1},
8959 {157, 0x60, 0, 5},
8960 {159, 0x60, 0, 7},
8961 {161, 0x60, 0, 9},
8962 {165, 0x61, 0, 1},
8963 {167, 0x61, 0, 3},
8964 {169, 0x61, 0, 5},
8965 {171, 0x61, 0, 7},
8966 {173, 0x61, 0, 9},
4da2933f
BZ		 8967};
8968
5c4412e0
DG		 8969/*
8970 * RF value list for rt3xxx with Xtal20MHz
8971 * Supports: 2.4 GHz (all) (RF3322)
8972 */
8973static const struct rf_channel rf_vals_3x_xtal20[] = {
8974 {1, 0xE2, 2, 0x14},
8975 {2, 0xE3, 2, 0x14},
8976 {3, 0xE4, 2, 0x14},
8977 {4, 0xE5, 2, 0x14},
8978 {5, 0xE6, 2, 0x14},
8979 {6, 0xE7, 2, 0x14},
8980 {7, 0xE8, 2, 0x14},
8981 {8, 0xE9, 2, 0x14},
8982 {9, 0xEA, 2, 0x14},
8983 {10, 0xEB, 2, 0x14},
8984 {11, 0xEC, 2, 0x14},
8985 {12, 0xED, 2, 0x14},
8986 {13, 0xEE, 2, 0x14},
8987 {14, 0xF0, 2, 0x18},
8988};
8989
7848b231
SG		 8990static const struct rf_channel rf_vals_5592_xtal20[] = {
8991 /* Channel, N, K, mod, R */
8992 {1, 482, 4, 10, 3},
8993 {2, 483, 4, 10, 3},
8994 {3, 484, 4, 10, 3},
8995 {4, 485, 4, 10, 3},
8996 {5, 486, 4, 10, 3},
8997 {6, 487, 4, 10, 3},
8998 {7, 488, 4, 10, 3},
8999 {8, 489, 4, 10, 3},
9000 {9, 490, 4, 10, 3},
9001 {10, 491, 4, 10, 3},
9002 {11, 492, 4, 10, 3},
9003 {12, 493, 4, 10, 3},
9004 {13, 494, 4, 10, 3},
9005 {14, 496, 8, 10, 3},
9006 {36, 172, 8, 12, 1},
9007 {38, 173, 0, 12, 1},
9008 {40, 173, 4, 12, 1},
9009 {42, 173, 8, 12, 1},
9010 {44, 174, 0, 12, 1},
9011 {46, 174, 4, 12, 1},
9012 {48, 174, 8, 12, 1},
9013 {50, 175, 0, 12, 1},
9014 {52, 175, 4, 12, 1},
9015 {54, 175, 8, 12, 1},
9016 {56, 176, 0, 12, 1},
9017 {58, 176, 4, 12, 1},
9018 {60, 176, 8, 12, 1},
9019 {62, 177, 0, 12, 1},
9020 {64, 177, 4, 12, 1},
9021 {100, 183, 4, 12, 1},
9022 {102, 183, 8, 12, 1},
9023 {104, 184, 0, 12, 1},
9024 {106, 184, 4, 12, 1},
9025 {108, 184, 8, 12, 1},
9026 {110, 185, 0, 12, 1},
9027 {112, 185, 4, 12, 1},
9028 {114, 185, 8, 12, 1},
9029 {116, 186, 0, 12, 1},
9030 {118, 186, 4, 12, 1},
9031 {120, 186, 8, 12, 1},
9032 {122, 187, 0, 12, 1},
9033 {124, 187, 4, 12, 1},
9034 {126, 187, 8, 12, 1},
9035 {128, 188, 0, 12, 1},
9036 {130, 188, 4, 12, 1},
9037 {132, 188, 8, 12, 1},
9038 {134, 189, 0, 12, 1},
9039 {136, 189, 4, 12, 1},
9040 {138, 189, 8, 12, 1},
9041 {140, 190, 0, 12, 1},
9042 {149, 191, 6, 12, 1},
9043 {151, 191, 10, 12, 1},
9044 {153, 192, 2, 12, 1},
9045 {155, 192, 6, 12, 1},
9046 {157, 192, 10, 12, 1},
9047 {159, 193, 2, 12, 1},
9048 {161, 193, 6, 12, 1},
9049 {165, 194, 2, 12, 1},
9050 {184, 164, 0, 12, 1},
9051 {188, 164, 4, 12, 1},
9052 {192, 165, 8, 12, 1},
9053 {196, 166, 0, 12, 1},
9054};
9055
9056static const struct rf_channel rf_vals_5592_xtal40[] = {
9057 /* Channel, N, K, mod, R */
9058 {1, 241, 2, 10, 3},
9059 {2, 241, 7, 10, 3},
9060 {3, 242, 2, 10, 3},
9061 {4, 242, 7, 10, 3},
9062 {5, 243, 2, 10, 3},
9063 {6, 243, 7, 10, 3},
9064 {7, 244, 2, 10, 3},
9065 {8, 244, 7, 10, 3},
9066 {9, 245, 2, 10, 3},
9067 {10, 245, 7, 10, 3},
9068 {11, 246, 2, 10, 3},
9069 {12, 246, 7, 10, 3},
9070 {13, 247, 2, 10, 3},
9071 {14, 248, 4, 10, 3},
9072 {36, 86, 4, 12, 1},
9073 {38, 86, 6, 12, 1},
9074 {40, 86, 8, 12, 1},
9075 {42, 86, 10, 12, 1},
9076 {44, 87, 0, 12, 1},
9077 {46, 87, 2, 12, 1},
9078 {48, 87, 4, 12, 1},
9079 {50, 87, 6, 12, 1},
9080 {52, 87, 8, 12, 1},
9081 {54, 87, 10, 12, 1},
9082 {56, 88, 0, 12, 1},
9083 {58, 88, 2, 12, 1},
9084 {60, 88, 4, 12, 1},
9085 {62, 88, 6, 12, 1},
9086 {64, 88, 8, 12, 1},
9087 {100, 91, 8, 12, 1},
9088 {102, 91, 10, 12, 1},
9089 {104, 92, 0, 12, 1},
9090 {106, 92, 2, 12, 1},
9091 {108, 92, 4, 12, 1},
9092 {110, 92, 6, 12, 1},
9093 {112, 92, 8, 12, 1},
9094 {114, 92, 10, 12, 1},
9095 {116, 93, 0, 12, 1},
9096 {118, 93, 2, 12, 1},
9097 {120, 93, 4, 12, 1},
9098 {122, 93, 6, 12, 1},
9099 {124, 93, 8, 12, 1},
9100 {126, 93, 10, 12, 1},
9101 {128, 94, 0, 12, 1},
9102 {130, 94, 2, 12, 1},
9103 {132, 94, 4, 12, 1},
9104 {134, 94, 6, 12, 1},
9105 {136, 94, 8, 12, 1},
9106 {138, 94, 10, 12, 1},
9107 {140, 95, 0, 12, 1},
9108 {149, 95, 9, 12, 1},
9109 {151, 95, 11, 12, 1},
9110 {153, 96, 1, 12, 1},
9111 {155, 96, 3, 12, 1},
9112 {157, 96, 5, 12, 1},
9113 {159, 96, 7, 12, 1},
9114 {161, 96, 9, 12, 1},
9115 {165, 97, 1, 12, 1},
9116 {184, 82, 0, 12, 1},
9117 {188, 82, 4, 12, 1},
9118 {192, 82, 8, 12, 1},
9119 {196, 83, 0, 12, 1},
9120};
9121
41977e86
RY		 9122static const struct rf_channel rf_vals_7620[] = {
9123 {1, 0x50, 0x99, 0x99, 1},
9124 {2, 0x50, 0x44, 0x44, 2},
9125 {3, 0x50, 0xEE, 0xEE, 2},
9126 {4, 0x50, 0x99, 0x99, 3},
9127 {5, 0x51, 0x44, 0x44, 0},
9128 {6, 0x51, 0xEE, 0xEE, 0},
9129 {7, 0x51, 0x99, 0x99, 1},
9130 {8, 0x51, 0x44, 0x44, 2},
9131 {9, 0x51, 0xEE, 0xEE, 2},
9132 {10, 0x51, 0x99, 0x99, 3},
9133 {11, 0x52, 0x44, 0x44, 0},
9134 {12, 0x52, 0xEE, 0xEE, 0},
9135 {13, 0x52, 0x99, 0x99, 1},
9136 {14, 0x52, 0x33, 0x33, 3},
9137};
9138
ad417a53 9139static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 9140{
4da2933f
BZ		 9141 struct hw_mode_spec *spec = &rt2x00dev->spec;
9142 struct channel_info *info;
8d1331b3
ID		 9143 char *default_power1;
9144 char *default_power2;
c0a14369 9145 char *default_power3;
cea5b03d 9146 unsigned int i, tx_chains, rx_chains;
7848b231 9147 u32 reg;
4da2933f 9148
93b6bd26 9149 /*
58e33a21 9150 * Disable powersaving as default.
93b6bd26 9151 */
58e33a21 9152 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 9153
01d97ef4
SG		 9154 /*
9155 * Change default retry settings to values corresponding more closely
9156 * to rate[0].count setting of minstrel rate control algorithm.
9157 */
9158 rt2x00dev->hw->wiphy->retry_short = 2;
9159 rt2x00dev->hw->wiphy->retry_long = 2;
9160
4da2933f
BZ		 9161 /*
9162 * Initialize all hw fields.
9163 */
30686bf7
JB		 9164 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9165 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9166 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9167 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9168 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9d4f09b8 9169
5a5b6ed6
HS		 9170 /*
9171 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9172 * unless we are capable of sending the buffered frames out after the
9173 * DTIM transmission using rt2x00lib_beacondone. This will send out
9174 * multicast and broadcast traffic immediately instead of buffering it
9175 * infinitly and thus dropping it after some time.
9176 */
9177 if (!rt2x00_is_usb(rt2x00dev))
30686bf7 9178 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
4da2933f 9179
2557654d
CYY		 9180 /* Set MFP if HW crypto is disabled. */
9181 if (rt2800_hwcrypt_disabled(rt2x00dev))
9182 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9183
4da2933f
BZ		 9184 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9185 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 9186 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 9187 EEPROM_MAC_ADDR_0));
9188
3f2bee24
HS		 9189 /*
9190 * As rt2800 has a global fallback table we cannot specify
9191 * more then one tx rate per frame but since the hw will
9192 * try several rates (based on the fallback table) we should
ba3b9e5e 9193 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 9194 * we are going to try. Otherwise mac80211 will truncate our
9195 * reported tx rates and the rc algortihm will end up with
9196 * incorrect data.
9197 */
ba3b9e5e
HS		 9198 rt2x00dev->hw->max_rates = 1;
9199 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 9200 rt2x00dev->hw->max_rate_tries = 1;
9201
4da2933f
BZ		 9202 /*
9203 * Initialize hw_mode information.
9204 */
4da2933f
BZ		 9205 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9206
4a32c36d
GJ		 9207 switch (rt2x00dev->chip.rf) {
9208 case RF2720:
9209 case RF2820:
4da2933f
BZ		 9210 spec->num_channels = 14;
9211 spec->channels = rf_vals;
4a32c36d
GJ		 9212 break;
9213
9214 case RF2750:
9215 case RF2850:
4da2933f
BZ		 9216 spec->num_channels = ARRAY_SIZE(rf_vals);
9217 spec->channels = rf_vals;
4a32c36d
GJ		 9218 break;
9219
9220 case RF2020:
9221 case RF3020:
9222 case RF3021:
9223 case RF3022:
9224 case RF3070:
9225 case RF3290:
9226 case RF3320:
9227 case RF3322:
98e71f44 9228 case RF5350:
4a32c36d 9229 case RF5360:
ac0372ab 9230 case RF5362:
4a32c36d
GJ		 9231 case RF5370:
9232 case RF5372:
9233 case RF5390:
9234 case RF5392:
55f9321a 9235 spec->num_channels = 14;
5c4412e0
DG		 9236 if (rt2800_clk_is_20mhz(rt2x00dev))
9237 spec->channels = rf_vals_3x_xtal20;
9238 else
9239 spec->channels = rf_vals_3x;
4a32c36d
GJ		 9240 break;
9241
41977e86
RY		 9242 case RF7620:
9243 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9244 spec->channels = rf_vals_7620;
9245 break;
9246
4a32c36d
GJ		 9247 case RF3052:
9248 case RF3053:
55f9321a
ID		 9249 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9250 spec->channels = rf_vals_3x;
4a32c36d 9251 break;
7848b231 9252
4a32c36d 9253 case RF5592:
7848b231
SG		 9254 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
9255 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9256 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9257 spec->channels = rf_vals_5592_xtal40;
9258 } else {
9259 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9260 spec->channels = rf_vals_5592_xtal20;
9261 }
4a32c36d 9262 break;
4da2933f
BZ		 9263 }
9264
53216d6a
SG		 9265 if (WARN_ON_ONCE(!spec->channels))
9266 return -ENODEV;
9267
53c5a099
GJ		 9268 spec->supported_bands = SUPPORT_BAND_2GHZ;
9269 if (spec->num_channels > 14)
9270 spec->supported_bands |= SUPPORT_BAND_5GHZ;
9271
4da2933f
BZ		 9272 /*
9273 * Initialize HT information.
9274 */
5122d898 9275 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 9276 spec->ht.ht_supported = true;
9277 else
9278 spec->ht.ht_supported = false;
9279
4da2933f 9280 spec->ht.cap =
06443e46 9281 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 9282 IEEE80211_HT_CAP_GRN_FLD |
9283 IEEE80211_HT_CAP_SGI_20 |
aa674631 9284 IEEE80211_HT_CAP_SGI_40;
22cabaa6 9285
cea5b03d
SG		 9286 tx_chains = rt2x00dev->default_ant.tx_chain_num;
9287 rx_chains = rt2x00dev->default_ant.rx_chain_num;
9288
9289 if (tx_chains >= 2)
22cabaa6
HS		 9290 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
9291
cea5b03d 9292 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 9293
a08b9819 9294 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
4da2933f 9295 spec->ht.ampdu_density = 4;
cea5b03d
SG		 9296 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9297 if (tx_chains != rx_chains) {
9298 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
9299 spec->ht.mcs.tx_params |=
9300 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
9301 }
4da2933f 9302
cea5b03d 9303 switch (rx_chains) {
4da2933f
BZ		 9304 case 3:
9305 spec->ht.mcs.rx_mask[2] = 0xff;
9306 case 2:
9307 spec->ht.mcs.rx_mask[1] = 0xff;
9308 case 1:
9309 spec->ht.mcs.rx_mask[0] = 0xff;
9310 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
9311 break;
9312 }
9313
9314 /*
9315 * Create channel information array
9316 */
baeb2ffa 9317 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 9318 if (!info)
9319 return -ENOMEM;
9320
9321 spec->channels_info = info;
9322
3e38d3da
GJ		 9323 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
9324 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 9325
c0a14369
GJ		 9326 if (rt2x00dev->default_ant.tx_chain_num > 2)
9327 default_power3 = rt2800_eeprom_addr(rt2x00dev,
9328 EEPROM_EXT_TXPOWER_BG3);
9329 else
9330 default_power3 = NULL;
9331
4da2933f 9332 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 9333 info[i].default_power1 = default_power1[i];
9334 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 9335 if (default_power3)
9336 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 9337 }
9338
9339 if (spec->num_channels > 14) {
3e38d3da
GJ		 9340 default_power1 = rt2800_eeprom_addr(rt2x00dev,
9341 EEPROM_TXPOWER_A1);
9342 default_power2 = rt2800_eeprom_addr(rt2x00dev,
9343 EEPROM_TXPOWER_A2);
4da2933f 9344
c0a14369
GJ		 9345 if (rt2x00dev->default_ant.tx_chain_num > 2)
9346 default_power3 =
9347 rt2800_eeprom_addr(rt2x00dev,
9348 EEPROM_EXT_TXPOWER_A3);
9349 else
9350 default_power3 = NULL;
9351
4da2933f 9352 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 9353 info[i].default_power1 = default_power1[i - 14];
9354 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 9355 if (default_power3)
9356 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 9357 }
9358 }
9359
2e9c43dd
JL		 9360 switch (rt2x00dev->chip.rf) {
9361 case RF2020:
9362 case RF3020:
9363 case RF3021:
9364 case RF3022:
9365 case RF3320:
9366 case RF3052:
1095df07 9367 case RF3053:
3b9b74ba 9368 case RF3070:
a89534ed 9369 case RF3290:
98e71f44 9370 case RF5350:
ccf91bd6 9371 case RF5360:
ac0372ab 9372 case RF5362:
2e9c43dd
JL		 9373 case RF5370:
9374 case RF5372:
9375 case RF5390:
cff3d1f0 9376 case RF5392:
24d42ef3 9377 case RF5592:
41977e86 9378 case RF7620:
2e9c43dd
JL		 9379 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
9380 break;
9381 }
9382
4da2933f
BZ		 9383 return 0;
9384}
ad417a53 9385
cbafb601
GJ		 9386static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
9387{
9388 u32 reg;
9389 u32 rt;
9390 u32 rev;
9391
9392 if (rt2x00_rt(rt2x00dev, RT3290))
9393 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
9394 else
9395 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
9396
9397 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
9398 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
9399
9400 switch (rt) {
9401 case RT2860:
9402 case RT2872:
9403 case RT2883:
9404 case RT3070:
9405 case RT3071:
9406 case RT3090:
9407 case RT3290:
9408 case RT3352:
9409 case RT3390:
9410 case RT3572:
2dc2bd2f 9411 case RT3593:
98e71f44 9412 case RT5350:
cbafb601
GJ		 9413 case RT5390:
9414 case RT5392:
9415 case RT5592:
9416 break;
9417 default:
ec9c4989
JP		 9418 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
9419 rt, rev);
cbafb601
GJ		 9420 return -ENODEV;
9421 }
9422
41977e86
RY		 9423 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
9424 rt = RT6352;
9425
cbafb601
GJ		 9426 rt2x00_set_rt(rt2x00dev, rt, rev);
9427
9428 return 0;
9429}
9430
ad417a53
GW		 9431int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
9432{
9433 int retval;
9434 u32 reg;
9435
cbafb601
GJ		 9436 retval = rt2800_probe_rt(rt2x00dev);
9437 if (retval)
9438 return retval;
9439
ad417a53
GW		 9440 /*
9441 * Allocate eeprom data.
9442 */
9443 retval = rt2800_validate_eeprom(rt2x00dev);
9444 if (retval)
9445 return retval;
9446
9447 retval = rt2800_init_eeprom(rt2x00dev);
9448 if (retval)
9449 return retval;
9450
9451 /*
9452 * Enable rfkill polling by setting GPIO direction of the
9453 * rfkill switch GPIO pin correctly.
9454 */
9455 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
9456 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
9457 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
9458
9459 /*
9460 * Initialize hw specifications.
9461 */
9462 retval = rt2800_probe_hw_mode(rt2x00dev);
9463 if (retval)
9464 return retval;
9465
9466 /*
9467 * Set device capabilities.
9468 */
9469 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
9470 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
9471 if (!rt2x00_is_usb(rt2x00dev))
9472 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9473
9474 /*
9475 * Set device requirements.
9476 */
9477 if (!rt2x00_is_soc(rt2x00dev))
9478 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
9479 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
9480 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
9481 if (!rt2800_hwcrypt_disabled(rt2x00dev))
9482 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
9483 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
9484 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
9485 if (rt2x00_is_usb(rt2x00dev))
9486 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
9487 else {
9488 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
9489 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
9490 }
9491
9492 /*
9493 * Set the rssi offset.
9494 */
9495 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
9496
9497 return 0;
9498}
9499EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 9500
2ce33995
BZ		 9501/*
9502 * IEEE80211 stack callback functions.
9503 */
9352c19f
JB		 9504void rt2800_get_key_seq(struct ieee80211_hw *hw,
9505 struct ieee80211_key_conf *key,
9506 struct ieee80211_key_seq *seq)
2ce33995
BZ		 9507{
9508 struct rt2x00_dev *rt2x00dev = hw->priv;
9509 struct mac_iveiv_entry iveiv_entry;
9510 u32 offset;
9511
9352c19f
JB		 9512 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
9513 return;
9514
9515 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
2ce33995
BZ		 9516 rt2800_register_multiread(rt2x00dev, offset,
9517 &iveiv_entry, sizeof(iveiv_entry));
9518
9352c19f
JB		 9519 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
9520 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
2ce33995 9521}
9352c19f 9522EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
2ce33995 9523
e783619e 9524int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 9525{
9526 struct rt2x00_dev *rt2x00dev = hw->priv;
9527 u32 reg;
9528 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
9529
9530 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
9531 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
9532 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
9533
9534 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
9535 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
9536 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
9537
9538 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
9539 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9540 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
9541
9542 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
9543 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
9544 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
9545
9546 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
9547 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
9548 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
9549
9550 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
9551 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
9552 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
9553
9554 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
9555 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
9556 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
9557
9558 return 0;
9559}
e783619e 9560EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 9561
8a3a3c85
EP		 9562int rt2800_conf_tx(struct ieee80211_hw *hw,
9563 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 9564 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 9565{
9566 struct rt2x00_dev *rt2x00dev = hw->priv;
9567 struct data_queue *queue;
9568 struct rt2x00_field32 field;
9569 int retval;
9570 u32 reg;
9571 u32 offset;
9572
9573 /*
9574 * First pass the configuration through rt2x00lib, that will
9575 * update the queue settings and validate the input. After that
9576 * we are free to update the registers based on the value
9577 * in the queue parameter.
9578 */
8a3a3c85 9579 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 9580 if (retval)
9581 return retval;
9582
9583 /*
9584 * We only need to perform additional register initialization
9585 * for WMM queues/
9586 */
9587 if (queue_idx >= 4)
9588 return 0;
9589
11f818e0 9590 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 9591
9592 /* Update WMM TXOP register */
9593 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
9594 field.bit_offset = (queue_idx & 1) * 16;
9595 field.bit_mask = 0xffff << field.bit_offset;
9596
9597 rt2800_register_read(rt2x00dev, offset, &reg);
9598 rt2x00_set_field32(&reg, field, queue->txop);
9599 rt2800_register_write(rt2x00dev, offset, reg);
9600
9601 /* Update WMM registers */
9602 field.bit_offset = queue_idx * 4;
9603 field.bit_mask = 0xf << field.bit_offset;
9604
9605 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
9606 rt2x00_set_field32(&reg, field, queue->aifs);
9607 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
9608
9609 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
9610 rt2x00_set_field32(&reg, field, queue->cw_min);
9611 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
9612
9613 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
9614 rt2x00_set_field32(&reg, field, queue->cw_max);
9615 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
9616
9617 /* Update EDCA registers */
9618 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
9619
9620 rt2800_register_read(rt2x00dev, offset, &reg);
9621 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
9622 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
9623 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
9624 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9625 rt2800_register_write(rt2x00dev, offset, reg);
9626
9627 return 0;
9628}
e783619e 9629EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 9630
37a41b4a 9631u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 9632{
9633 struct rt2x00_dev *rt2x00dev = hw->priv;
9634 u64 tsf;
9635 u32 reg;
9636
9637 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
9638 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9639 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
9640 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
9641
9642 return tsf;
9643}
e783619e 9644EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 9645
e783619e 9646int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 9647 struct ieee80211_ampdu_params *params)
1df90809 9648{
50ea05ef
SS		 9649 struct ieee80211_sta *sta = params->sta;
9650 enum ieee80211_ampdu_mlme_action action = params->action;
9651 u16 tid = params->tid;
af35323d 9652 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 9653 int ret = 0;
9654
af35323d
HS		 9655 /*
9656 * Don't allow aggregation for stations the hardware isn't aware
9657 * of because tx status reports for frames to an unknown station
ed8e0ed5
SG		 9658 * always contain wcid=WCID_END+1 and thus we can't distinguish
9659 * between multiple stations which leads to unwanted situations
9660 * when the hw reorders frames due to aggregation.
af35323d 9661 */
ed8e0ed5 9662 if (sta_priv->wcid > WCID_END)
af35323d
HS		 9663 return 1;
9664
1df90809
HS		 9665 switch (action) {
9666 case IEEE80211_AMPDU_RX_START:
9667 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 9668 /*
9669 * The hw itself takes care of setting up BlockAck mechanisms.
9670 * So, we only have to allow mac80211 to nagotiate a BlockAck
9671 * agreement. Once that is done, the hw will BlockAck incoming
9672 * AMPDUs without further setup.
9673 */
1df90809
HS		 9674 break;
9675 case IEEE80211_AMPDU_TX_START:
9676 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9677 break;
18b559d5
JB		 9678 case IEEE80211_AMPDU_TX_STOP_CONT:
9679 case IEEE80211_AMPDU_TX_STOP_FLUSH:
9680 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 9681 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9682 break;
9683 case IEEE80211_AMPDU_TX_OPERATIONAL:
9684 break;
9685 default:
ec9c4989
JP		 9686 rt2x00_warn((struct rt2x00_dev *)hw->priv,
9687 "Unknown AMPDU action\n");
1df90809
HS		 9688 }
9689
9690 return ret;
9691}
e783619e 9692EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 9693
977206d7
HS		 9694int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
9695 struct survey_info *survey)
9696{
9697 struct rt2x00_dev *rt2x00dev = hw->priv;
9698 struct ieee80211_conf *conf = &hw->conf;
9699 u32 idle, busy, busy_ext;
9700
9701 if (idx != 0)
9702 return -ENOENT;
9703
675a0b04 9704 survey->channel = conf->chandef.chan;
977206d7
HS		 9705
9706 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
9707 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
9708 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
9709
9710 if (idle || busy) {
4ed20beb
JB		 9711 survey->filled = SURVEY_INFO_TIME |
9712 SURVEY_INFO_TIME_BUSY |
9713 SURVEY_INFO_TIME_EXT_BUSY;
977206d7 9714
4ed20beb
JB		 9715 survey->time = (idle + busy) / 1000;
9716 survey->time_busy = busy / 1000;
9717 survey->time_ext_busy = busy_ext / 1000;
977206d7
HS		 9718 }
9719
9931df26
HS		 9720 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
9721 survey->filled |= SURVEY_INFO_IN_USE;
9722
977206d7
HS		 9723 return 0;
9724
9725}
9726EXPORT_SYMBOL_GPL(rt2800_get_survey);
9727
a5ea2f02
ID		 9728MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
9729MODULE_VERSION(DRV_VERSION);
9730MODULE_DESCRIPTION("Ralink RT2800 library");
9731MODULE_LICENSE("GPL");
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