]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/wireless/ralink/rt2x00/rt2800lib.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2800: rename adjust_freq_offset function
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ralink / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
ec9c4989 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
89297425 109
fcf51541
BZ		 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
89297425
BZ		 112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
89297425 141
fcf51541
BZ		 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
89297425
BZ		 144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
89297425 165
fcf51541
BZ		 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
89297425
BZ		 168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
89297425 196
fcf51541
BZ		 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
89297425
BZ		 199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
89297425 221
379448fe
GJ		 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
fa31d157
GJ		 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 279 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
379448fe
GJ		 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
fa31d157
GJ		 312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
379448fe
GJ		 317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
3e38d3da
GJ		 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
379448fe
GJ		 335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
379448fe
GJ		 344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
379448fe
GJ		 353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 357}
358
022138ca
GJ		 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
379448fe
GJ		 364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 368}
369
16ebd608
WH		 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(&reg, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(&reg, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(&reg, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
89297425
BZ		 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
ee303e54 437 /*
cea90e55 438 * SOC devices don't support MCU requests.
ee303e54 439 */
cea90e55 440 if (rt2x00_is_soc(rt2x00dev))
ee303e54 441 return;
89297425
BZ		 442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 464
5ffddc49
ID		 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
ec9c4989 477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
67a4c1e2
GW		 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
08e53100
HS		 487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
67a4c1e2
GW		 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
08e53100 497 msleep(10);
67a4c1e2
GW		 498 }
499
ec9c4989 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
f7b395e9
JK		 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
ae1b1c5d
GJ		 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
f31c9a8c
ID		 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
f31c9a8c 589 */
a89534ed 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 591 fw_len = 4096;
a89534ed 592 else
f31c9a8c 593 fw_len = 8192;
f31c9a8c 594
a89534ed 595 multiple = true;
f31c9a8c
ID		 596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
16ebd608
WH		 633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
f31c9a8c
ID		 640
641 /*
b9eca242
ID		 642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 644 */
b9eca242 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 646
f31c9a8c
ID		 647 /*
648 * Wait for stable hardware.
649 */
5ffddc49 650 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 651 return -EBUSY;
f31c9a8c 652
adde5882 653 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
f31c9a8c 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 664 }
f31c9a8c 665
b7e1d225
JK		 666 rt2800_disable_wpdma(rt2x00dev);
667
f31c9a8c
ID		 668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 685 return -EBUSY;
686 }
687
4ed1dd2a
SG		 688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
f7b395e9 692 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 693
f31c9a8c
ID		 694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 699 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
f31c9a8c
ID		 703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
0c5879bc
ID		 709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
59679b91 711{
0c5879bc 712 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 713 u32 word;
557985ae 714 int i;
59679b91
GW		 715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 749 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
2b23cdaa 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
557985ae
SG		 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 762 *
763 * Nulify all remaining words as well, we don't know how to program them.
59679b91 764 */
557985ae
SG		 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
59679b91 767}
0c5879bc 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 769
ff6133be 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 771{
7fc41755
LT		 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
57fbcce3 780 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
3e38d3da 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
7fc41755 810 return (int)max(rssi0, rssi2);
74861922
ID		 811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
74861922
ID		 847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
31937c42 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
b34793ee 865 int aggr, ampdu;
14433331
HS		 866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
14433331 871 rt2x00_desc_read(txwi, 0, &word);
b34793ee 872
14433331 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
14433331 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
5356d963 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
14433331 899
f16d2db7
HS		 900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
14433331
HS		 903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
21c6af6b
GJ		 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
634b8059
GJ		 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
ba08910e
SG		 950static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
951{
952 struct data_queue *queue = rt2x00dev->bcn;
953 struct queue_entry *entry;
954 int i, bcn_num = 0;
955 u64 off, reg = 0;
956 u32 bssid_dw1;
957
958 /*
959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
960 */
961 for (i = 0; i < queue->limit; i++) {
962 entry = &queue->entries[i];
963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
964 continue;
965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
966 reg |= off << (8 * bcn_num);
967 bcn_num++;
968 }
969
970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
971
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
974
975 /*
976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
977 */
978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
980 bcn_num > 0 ? bcn_num - 1 : 0);
981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
982}
983
f0194b2d
GW		 984void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
985{
986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
988 unsigned int beacon_base;
739fd940 989 unsigned int padding_len;
d76dfc61 990 u32 orig_reg, reg;
f0bda571 991 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 992
993 /*
994 * Disable beaconing while we are reloading the beacon data,
995 * otherwise we might be sending out invalid data.
996 */
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 998 orig_reg = reg;
f0194b2d
GW		 999 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002 /*
1003 * Add space for the TXWI in front of the skb.
1004 */
f0bda571 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1006
1007 /*
1008 * Register descriptor details in skb frame descriptor.
1009 */
1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011 skbdesc->desc = entry->skb->data;
f0bda571 1012 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1013
1014 /*
1015 * Add the TXWI for the beacon to the skb.
1016 */
0c5879bc 1017 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1018
1019 /*
1020 * Dump beacon to userspace through debugfs.
1021 */
1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024 /*
739fd940 1025 * Write entire beacon with TXWI and padding to register.
f0194b2d 1026 */
739fd940 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1028 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1030 /* skb freed by skb_pad() on failure */
1031 entry->skb = NULL;
1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033 return;
1034 }
1035
21c6af6b
GJ		 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
739fd940
WK		 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039 entry->skb->len + padding_len);
ba08910e
SG		 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042 /*
1043 * Change global beacons settings.
1044 */
1045 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1046
1047 /*
bc0df75a 1048 * Restore beaconing state.
f0194b2d 1049 */
bc0df75a 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1051
1052 /*
1053 * Clean up beacon skb.
1054 */
1055 dev_kfree_skb_any(entry->skb);
1056 entry->skb = NULL;
1057}
50e888ea 1058EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1059
69cf36a4 1060static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1061 unsigned int index)
fdb87251
HS		 1062{
1063 int i;
0879f875 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1065 unsigned int beacon_base;
1066
21c6af6b 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1068
1069 /*
1070 * For the Beacon base registers we only need to clear
1071 * the whole TXWI which (when set to 0) will invalidate
1072 * the entire beacon.
1073 */
f0bda571 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076}
1077
69cf36a4
HS		 1078void rt2800_clear_beacon(struct queue_entry *entry)
1079{
1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1081 u32 orig_reg, reg;
69cf36a4
HS		 1082
1083 /*
1084 * Disable beaconing while we are reloading the beacon data,
1085 * otherwise we might be sending out invalid data.
1086 */
bc0df75a
SG		 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088 reg = orig_reg;
69cf36a4
HS		 1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092 /*
1093 * Clear beacon.
1094 */
77f7c0f3 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1097
ba08910e
SG		 1098 /*
1099 * Change global beacons settings.
1100 */
1101 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1102 /*
bc0df75a 1103 * Restore beaconing state.
69cf36a4 1104 */
bc0df75a 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1106}
1107EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
f4450616
BZ		 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110const struct rt2x00debug rt2800_rt2x00debug = {
1111 .owner = THIS_MODULE,
1112 .csr = {
1113 .read = rt2800_register_read,
1114 .write = rt2800_register_write,
1115 .flags = RT2X00DEBUGFS_OFFSET,
1116 .word_base = CSR_REG_BASE,
1117 .word_size = sizeof(u32),
1118 .word_count = CSR_REG_SIZE / sizeof(u32),
1119 },
1120 .eeprom = {
3e38d3da
GJ		 1121 /* NOTE: The local EEPROM access functions can't
1122 * be used here, use the generic versions instead.
1123 */
f4450616
BZ		 1124 .read = rt2x00_eeprom_read,
1125 .write = rt2x00_eeprom_write,
1126 .word_base = EEPROM_BASE,
1127 .word_size = sizeof(u16),
1128 .word_count = EEPROM_SIZE / sizeof(u16),
1129 },
1130 .bbp = {
1131 .read = rt2800_bbp_read,
1132 .write = rt2800_bbp_write,
1133 .word_base = BBP_BASE,
1134 .word_size = sizeof(u8),
1135 .word_count = BBP_SIZE / sizeof(u8),
1136 },
1137 .rf = {
1138 .read = rt2x00_rf_read,
1139 .write = rt2800_rf_write,
1140 .word_base = RF_BASE,
1141 .word_size = sizeof(u32),
1142 .word_count = RF_SIZE / sizeof(u32),
1143 },
f2bd7f16
AA		 1144 .rfcsr = {
1145 .read = rt2800_rfcsr_read,
1146 .write = rt2800_rfcsr_write,
1147 .word_base = RFCSR_BASE,
1148 .word_size = sizeof(u8),
1149 .word_count = RFCSR_SIZE / sizeof(u8),
1150 },
f4450616
BZ		 1151};
1152EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156{
1157 u32 reg;
1158
a89534ed
WH		 1159 if (rt2x00_rt(rt2x00dev, RT3290)) {
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162 } else {
99bdf51a
GW		 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1165 }
f4450616
BZ		 1166}
1167EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169#ifdef CONFIG_RT2X00_LIB_LEDS
1170static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171 enum led_brightness brightness)
1172{
1173 struct rt2x00_led *led =
1174 container_of(led_cdev, struct rt2x00_led, led_dev);
1175 unsigned int enabled = brightness != LED_OFF;
1176 unsigned int bg_mode =
57fbcce3 1177 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
f4450616
BZ		 1178 unsigned int polarity =
1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180 EEPROM_FREQ_LED_POLARITY);
1181 unsigned int ledmode =
1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183 EEPROM_FREQ_LED_MODE);
44704e5d 1184 u32 reg;
f4450616 1185
44704e5d
LE		 1186 /* Check for SoC (SOC devices don't support MCU requests) */
1187 if (rt2x00_is_soc(led->rt2x00dev)) {
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190 /* Set LED Polarity */
1191 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193 /* Set LED Mode */
1194 if (led->type == LED_TYPE_RADIO) {
1195 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196 enabled ? 3 : 0);
1197 } else if (led->type == LED_TYPE_ASSOC) {
1198 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199 enabled ? 3 : 0);
1200 } else if (led->type == LED_TYPE_QUALITY) {
1201 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202 enabled ? 3 : 0);
1203 }
1204
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207 } else {
1208 if (led->type == LED_TYPE_RADIO) {
1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210 enabled ? 0x20 : 0);
1211 } else if (led->type == LED_TYPE_ASSOC) {
1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214 } else if (led->type == LED_TYPE_QUALITY) {
1215 /*
1216 * The brightness is divided into 6 levels (0 - 5),
1217 * The specs tell us the following levels:
1218 * 0, 1 ,3, 7, 15, 31
1219 * to determine the level in a simple way we can simply
1220 * work with bitshifting:
1221 * (1 << level) - 1
1222 */
1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224 (1 << brightness / (LED_FULL / 6)) - 1,
1225 polarity);
1226 }
f4450616
BZ		 1227 }
1228}
1229
b3579d6a 1230static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1231 struct rt2x00_led *led, enum led_type type)
1232{
1233 led->rt2x00dev = rt2x00dev;
1234 led->type = type;
1235 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1236 led->flags = LED_INITIALIZED;
1237}
f4450616
BZ		 1238#endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240/*
1241 * Configuration handlers.
1242 */
a2b1328a
HS		 1243static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244 const u8 *address,
1245 int wcid)
f4450616
BZ		 1246{
1247 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1248 u32 offset;
1249
1250 offset = MAC_WCID_ENTRY(wcid);
1251
1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253 if (address)
1254 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256 rt2800_register_multiwrite(rt2x00dev, offset,
1257 &wcid_entry, sizeof(wcid_entry));
1258}
1259
1260static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261{
1262 u32 offset;
1263 offset = MAC_WCID_ATTR_ENTRY(wcid);
1264 rt2800_register_write(rt2x00dev, offset, 0);
1265}
1266
1267static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268 int wcid, u32 bssidx)
1269{
1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271 u32 reg;
1272
1273 /*
1274 * The BSS Idx numbers is split in a main value of 3 bits,
1275 * and a extended field for adding one additional bit to the value.
1276 */
1277 rt2800_register_read(rt2x00dev, offset, &reg);
1278 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280 (bssidx & 0x8) >> 3);
1281 rt2800_register_write(rt2x00dev, offset, reg);
1282}
1283
1284static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_crypto *crypto,
1286 struct ieee80211_key_conf *key)
1287{
f4450616
BZ		 1288 struct mac_iveiv_entry iveiv_entry;
1289 u32 offset;
1290 u32 reg;
1291
1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
e4a0ab34
ID		 1294 if (crypto->cmd == SET_KEY) {
1295 rt2800_register_read(rt2x00dev, offset, &reg);
1296 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298 /*
1299 * Both the cipher as the BSS Idx numbers are split in a main
1300 * value of 3 bits, and a extended field for adding one additional
1301 * bit to the value.
1302 */
1303 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304 (crypto->cipher & 0x7));
1305 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1307 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308 rt2800_register_write(rt2x00dev, offset, reg);
1309 } else {
a2b1328a
HS		 1310 /* Delete the cipher without touching the bssidx */
1311 rt2800_register_read(rt2x00dev, offset, &reg);
1312 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1317 }
f4450616
BZ		 1318
1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322 if ((crypto->cipher == CIPHER_TKIP) ||
1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324 (crypto->cipher == CIPHER_AES))
1325 iveiv_entry.iv[3] |= 0x20;
1326 iveiv_entry.iv[3] |= key->keyidx << 6;
1327 rt2800_register_multiwrite(rt2x00dev, offset,
1328 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1329}
1330
1331int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332 struct rt2x00lib_crypto *crypto,
1333 struct ieee80211_key_conf *key)
1334{
1335 struct hw_key_entry key_entry;
1336 struct rt2x00_field32 field;
1337 u32 offset;
1338 u32 reg;
1339
1340 if (crypto->cmd == SET_KEY) {
1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343 memcpy(key_entry.key, crypto->key,
1344 sizeof(key_entry.key));
1345 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346 sizeof(key_entry.tx_mic));
1347 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348 sizeof(key_entry.rx_mic));
1349
1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351 rt2800_register_multiwrite(rt2x00dev, offset,
1352 &key_entry, sizeof(key_entry));
1353 }
1354
1355 /*
1356 * The cipher types are stored over multiple registers
1357 * starting with SHARED_KEY_MODE_BASE each word will have
1358 * 32 bits and contains the cipher types for 2 bssidx each.
1359 * Using the correct defines correctly will cause overhead,
1360 * so just calculate the correct offset.
1361 */
1362 field.bit_offset = 4 * (key->hw_key_idx % 8);
1363 field.bit_mask = 0x7 << field.bit_offset;
1364
1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367 rt2800_register_read(rt2x00dev, offset, &reg);
1368 rt2x00_set_field32(&reg, field,
1369 (crypto->cmd == SET_KEY) * crypto->cipher);
1370 rt2800_register_write(rt2x00dev, offset, reg);
1371
1372 /*
1373 * Update WCID information
1374 */
a2b1328a
HS		 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377 crypto->bssidx);
1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1379
1380 return 0;
1381}
1382EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
1384int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1385 struct rt2x00lib_crypto *crypto,
1386 struct ieee80211_key_conf *key)
1387{
1388 struct hw_key_entry key_entry;
1389 u32 offset;
1390
1391 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1392 /*
1393 * Allow key configuration only for STAs that are
1394 * known by the hw.
1395 */
ed8e0ed5 1396 if (crypto->wcid > WCID_END)
f4450616 1397 return -ENOSPC;
a2b1328a 1398 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1399
1400 memcpy(key_entry.key, crypto->key,
1401 sizeof(key_entry.key));
1402 memcpy(key_entry.tx_mic, crypto->tx_mic,
1403 sizeof(key_entry.tx_mic));
1404 memcpy(key_entry.rx_mic, crypto->rx_mic,
1405 sizeof(key_entry.rx_mic));
1406
1407 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1408 rt2800_register_multiwrite(rt2x00dev, offset,
1409 &key_entry, sizeof(key_entry));
1410 }
1411
1412 /*
1413 * Update WCID information
1414 */
a2b1328a 1415 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1416
1417 return 0;
1418}
1419EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1420
8f03a7c6
SG		 1421static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1422{
1423 u8 i, max_psdu;
1424 u32 reg;
1425 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1426
1427 for (i = 0; i < 3; i++)
1428 if (drv_data->ampdu_factor_cnt[i] > 0)
1429 break;
1430
1431 max_psdu = min(drv_data->max_psdu, i);
1432
1433 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1434 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1435 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1436}
1437
a2b1328a
HS		 1438int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1439 struct ieee80211_sta *sta)
1440{
1441 int wcid;
1442 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
ed8e0ed5 1443 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
a2b1328a 1444
8f03a7c6
SG		 1445 /*
1446 * Limit global maximum TX AMPDU length to smallest value of all
1447 * connected stations. In AP mode this can be suboptimal, but we
1448 * do not have a choice if some connected STA is not capable to
1449 * receive the same amount of data like the others.
1450 */
1451 if (sta->ht_cap.ht_supported) {
1452 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1453 rt2800_set_max_psdu_len(rt2x00dev);
1454 }
1455
a2b1328a 1456 /*
ed8e0ed5
SG		 1457 * Search for the first free WCID entry and return the corresponding
1458 * index.
a2b1328a 1459 */
ed8e0ed5 1460 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
a2b1328a
HS		 1461
1462 /*
1463 * Store selected wcid even if it is invalid so that we can
1464 * later decide if the STA is uploaded into the hw.
1465 */
1466 sta_priv->wcid = wcid;
1467
1468 /*
1469 * No space left in the device, however, we can still communicate
1470 * with the STA -> No error.
1471 */
ed8e0ed5 1472 if (wcid > WCID_END)
a2b1328a
HS		 1473 return 0;
1474
ed8e0ed5
SG		 1475 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1476
a2b1328a
HS		 1477 /*
1478 * Clean up WCID attributes and write STA address to the device.
1479 */
1480 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1481 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1482 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1483 rt2x00lib_get_bssidx(rt2x00dev, vif));
1484 return 0;
1485}
1486EXPORT_SYMBOL_GPL(rt2800_sta_add);
1487
8f03a7c6 1488int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta)
a2b1328a 1489{
ed8e0ed5 1490 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8f03a7c6
SG		 1491 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1492 int wcid = sta_priv->wcid;
1493
1494 if (sta->ht_cap.ht_supported) {
1495 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1496 rt2800_set_max_psdu_len(rt2x00dev);
1497 }
ed8e0ed5
SG		 1498
1499 if (wcid > WCID_END)
1500 return 0;
a2b1328a
HS		 1501 /*
1502 * Remove WCID entry, no need to clean the attributes as they will
1503 * get renewed when the WCID is reused.
1504 */
1505 rt2800_config_wcid(rt2x00dev, NULL, wcid);
ed8e0ed5 1506 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
a2b1328a
HS		 1507
1508 return 0;
1509}
1510EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1511
f4450616
BZ		 1512void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1513 const unsigned int filter_flags)
1514{
1515 u32 reg;
1516
1517 /*
1518 * Start configuration steps.
1519 * Note that the version error will always be dropped
1520 * and broadcast frames will always be accepted since
1521 * there is no filter for it at this time.
1522 */
1523 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1525 !(filter_flags & FIF_FCSFAIL));
1526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1527 !(filter_flags & FIF_PLCPFAIL));
262c741e
EC		 1528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1529 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
f4450616
BZ		 1530 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1531 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1532 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1533 !(filter_flags & FIF_ALLMULTI));
1534 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1535 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1536 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1537 !(filter_flags & FIF_CONTROL));
1538 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1539 !(filter_flags & FIF_CONTROL));
1540 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1541 !(filter_flags & FIF_CONTROL));
1542 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1543 !(filter_flags & FIF_CONTROL));
1544 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1545 !(filter_flags & FIF_CONTROL));
1546 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1547 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1548 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1549 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1550 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1551 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1552 !(filter_flags & FIF_CONTROL));
1553 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1554}
1555EXPORT_SYMBOL_GPL(rt2800_config_filter);
1556
1557void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1558 struct rt2x00intf_conf *conf, const unsigned int flags)
1559{
f4450616 1560 u32 reg;
fa8b4b22 1561 bool update_bssid = false;
f4450616
BZ		 1562
1563 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1564 /*
1565 * Enable synchronisation.
1566 */
1567 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1568 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1569 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1570
1571 if (conf->sync == TSF_SYNC_AP_NONE) {
1572 /*
1573 * Tune beacon queue transmit parameters for AP mode
1574 */
1575 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1576 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1577 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1578 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1579 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1580 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1581 } else {
1582 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1583 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1584 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1585 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1586 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1587 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1588 }
f4450616
BZ		 1589 }
1590
1591 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1592 if (flags & CONFIG_UPDATE_TYPE &&
1593 conf->sync == TSF_SYNC_AP_NONE) {
1594 /*
1595 * The BSSID register has to be set to our own mac
1596 * address in AP mode.
1597 */
1598 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1599 update_bssid = true;
1600 }
1601
c600c826
ID		 1602 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1603 reg = le32_to_cpu(conf->mac[1]);
1604 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1605 conf->mac[1] = cpu_to_le32(reg);
1606 }
f4450616
BZ		 1607
1608 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1609 conf->mac, sizeof(conf->mac));
1610 }
1611
fa8b4b22 1612 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1613 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1614 reg = le32_to_cpu(conf->bssid[1]);
1615 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1616 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1617 conf->bssid[1] = cpu_to_le32(reg);
1618 }
f4450616
BZ		 1619
1620 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1621 conf->bssid, sizeof(conf->bssid));
1622 }
1623}
1624EXPORT_SYMBOL_GPL(rt2800_config_intf);
1625
87c1915d
HS		 1626static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1627 struct rt2x00lib_erp *erp)
1628{
1629 bool any_sta_nongf = !!(erp->ht_opmode &
1630 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1631 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1632 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1633 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1634 u32 reg;
1635
1636 /* default protection rate for HT20: OFDM 24M */
1637 mm20_rate = gf20_rate = 0x4004;
1638
1639 /* default protection rate for HT40: duplicate OFDM 24M */
1640 mm40_rate = gf40_rate = 0x4084;
1641
1642 switch (protection) {
1643 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1644 /*
1645 * All STAs in this BSS are HT20/40 but there might be
1646 * STAs not supporting greenfield mode.
1647 * => Disable protection for HT transmissions.
1648 */
1649 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1650
1651 break;
1652 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1653 /*
1654 * All STAs in this BSS are HT20 or HT20/40 but there
1655 * might be STAs not supporting greenfield mode.
1656 * => Protect all HT40 transmissions.
1657 */
1658 mm20_mode = gf20_mode = 0;
6c40063d 1659 mm40_mode = gf40_mode = 1;
87c1915d
HS		 1660
1661 break;
1662 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1663 /*
1664 * Nonmember protection:
1665 * According to 802.11n we _should_ protect all
1666 * HT transmissions (but we don't have to).
1667 *
1668 * But if cts_protection is enabled we _shall_ protect
1669 * all HT transmissions using a CCK rate.
1670 *
1671 * And if any station is non GF we _shall_ protect
1672 * GF transmissions.
1673 *
1674 * We decide to protect everything
1675 * -> fall through to mixed mode.
1676 */
1677 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1678 /*
1679 * Legacy STAs are present
1680 * => Protect all HT transmissions.
1681 */
6c40063d 1682 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
87c1915d
HS		 1683
1684 /*
1685 * If erp protection is needed we have to protect HT
1686 * transmissions with CCK 11M long preamble.
1687 */
1688 if (erp->cts_protection) {
1689 /* don't duplicate RTS/CTS in CCK mode */
1690 mm20_rate = mm40_rate = 0x0003;
1691 gf20_rate = gf40_rate = 0x0003;
1692 }
1693 break;
6403eab1 1694 }
87c1915d
HS		 1695
1696 /* check for STAs not supporting greenfield mode */
1697 if (any_sta_nongf)
6c40063d 1698 gf20_mode = gf40_mode = 1;
87c1915d
HS		 1699
1700 /* Update HT protection config */
1701 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1702 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1703 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1704 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1705
1706 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1707 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1708 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1709 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1710
1711 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1712 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1713 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1714 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1715
1716 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1717 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1718 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1719 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1720}
1721
02044643
HS		 1722void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1723 u32 changed)
f4450616
BZ		 1724{
1725 u32 reg;
1726
02044643
HS		 1727 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1728 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
02044643
HS		 1729 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1730 !!erp->short_preamble);
1731 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1732 }
f4450616 1733
02044643
HS		 1734 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1735 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1736 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1737 erp->cts_protection ? 2 : 0);
1738 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1739 }
f4450616 1740
02044643
HS		 1741 if (changed & BSS_CHANGED_BASIC_RATES) {
1742 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
770e4b73 1743 0xff0 | erp->basic_rates);
02044643
HS		 1744 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1745 }
f4450616 1746
02044643
HS		 1747 if (changed & BSS_CHANGED_ERP_SLOT) {
1748 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1749 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1750 erp->slot_time);
1751 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1752
02044643
HS		 1753 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1754 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1755 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1756 }
f4450616 1757
02044643
HS		 1758 if (changed & BSS_CHANGED_BEACON_INT) {
1759 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1760 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1761 erp->beacon_int * 16);
1762 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1763 }
87c1915d
HS		 1764
1765 if (changed & BSS_CHANGED_HT)
1766 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1767}
1768EXPORT_SYMBOL_GPL(rt2800_config_erp);
1769
872834df
GW		 1770static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1771{
1772 u32 reg;
1773 u16 eeprom;
1774 u8 led_ctrl, led_g_mode, led_r_mode;
1775
1776 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
57fbcce3 1777 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
872834df
GW		 1778 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1779 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1780 } else {
1781 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1782 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1783 }
1784 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1785
1786 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1787 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1788 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1789 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1790 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1791 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1792 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1793 if (led_ctrl == 0 || led_ctrl > 0x40) {
1794 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1795 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1796 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1797 } else {
1798 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1799 (led_g_mode << 2) | led_r_mode, 1);
1800 }
1801 }
1802}
1803
d96aa640
RJH		 1804static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1805 enum antenna ant)
1806{
1807 u32 reg;
1808 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1809 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1810
1811 if (rt2x00_is_pci(rt2x00dev)) {
1812 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1813 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1814 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1815 } else if (rt2x00_is_usb(rt2x00dev))
1816 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1817 eesk_pin, 0);
1818
99bdf51a
GW		 1819 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1820 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1821 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1822 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1823}
1824
f4450616
BZ		 1825void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1826{
1827 u8 r1;
1828 u8 r3;
d96aa640 1829 u16 eeprom;
f4450616
BZ		 1830
1831 rt2800_bbp_read(rt2x00dev, 1, &r1);
1832 rt2800_bbp_read(rt2x00dev, 3, &r3);
1833
872834df 1834 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1835 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1836 rt2800_config_3572bt_ant(rt2x00dev);
1837
f4450616
BZ		 1838 /*
1839 * Configure the TX antenna.
1840 */
d96aa640 1841 switch (ant->tx_chain_num) {
f4450616
BZ		 1842 case 1:
1843 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1844 break;
1845 case 2:
872834df 1846 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1847 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1848 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1849 else
1850 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1851 break;
1852 case 3:
4788ac1e 1853 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1854 break;
1855 }
1856
1857 /*
1858 * Configure the RX antenna.
1859 */
d96aa640 1860 switch (ant->rx_chain_num) {
f4450616 1861 case 1:
d96aa640
RJH		 1862 if (rt2x00_rt(rt2x00dev, RT3070) ||
1863 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1864 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1865 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1866 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1867 EEPROM_NIC_CONF1, &eeprom);
1868 if (rt2x00_get_field16(eeprom,
1869 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1870 rt2800_set_ant_diversity(rt2x00dev,
1871 rt2x00dev->default_ant.rx);
1872 }
f4450616
BZ		 1873 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1874 break;
1875 case 2:
872834df 1876 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1877 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1878 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1879 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
57fbcce3 1880 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
872834df
GW		 1881 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1882 } else {
1883 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1884 }
f4450616
BZ		 1885 break;
1886 case 3:
1887 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1888 break;
1889 }
1890
1891 rt2800_bbp_write(rt2x00dev, 3, r3);
1892 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1893
1894 if (rt2x00_rt(rt2x00dev, RT3593)) {
1895 if (ant->rx_chain_num == 1)
1896 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1897 else
1898 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1899 }
f4450616
BZ		 1900}
1901EXPORT_SYMBOL_GPL(rt2800_config_ant);
1902
1903static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1904 struct rt2x00lib_conf *libconf)
1905{
1906 u16 eeprom;
1907 short lna_gain;
1908
1909 if (libconf->rf.channel <= 14) {
3e38d3da 1910 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1911 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1912 } else if (libconf->rf.channel <= 64) {
3e38d3da 1913 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1914 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1915 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1916 if (rt2x00_rt(rt2x00dev, RT3593)) {
1917 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1918 lna_gain = rt2x00_get_field16(eeprom,
1919 EEPROM_EXT_LNA2_A1);
1920 } else {
1921 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1922 lna_gain = rt2x00_get_field16(eeprom,
1923 EEPROM_RSSI_BG2_LNA_A1);
1924 }
f4450616 1925 } else {
f36bb0ca
GJ		 1926 if (rt2x00_rt(rt2x00dev, RT3593)) {
1927 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1928 lna_gain = rt2x00_get_field16(eeprom,
1929 EEPROM_EXT_LNA2_A2);
1930 } else {
1931 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1932 lna_gain = rt2x00_get_field16(eeprom,
1933 EEPROM_RSSI_A2_LNA_A2);
1934 }
f4450616
BZ		 1935 }
1936
1937 rt2x00dev->lna_gain = lna_gain;
1938}
1939
3f1b8739
GJ		 1940#define FREQ_OFFSET_BOUND 0x5f
1941
88452541 1942static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
3f1b8739
GJ		 1943{
1944 u8 freq_offset, prev_freq_offset;
1945 u8 rfcsr, prev_rfcsr;
1946
1947 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1948 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1949
1950 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1951 prev_rfcsr = rfcsr;
1952
1953 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1954 if (rfcsr == prev_rfcsr)
1955 return;
1956
1957 if (rt2x00_is_usb(rt2x00dev)) {
1958 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1959 freq_offset, prev_rfcsr);
1960 return;
1961 }
1962
1963 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1964 while (prev_freq_offset != freq_offset) {
1965 if (prev_freq_offset < freq_offset)
1966 prev_freq_offset++;
1967 else
1968 prev_freq_offset--;
1969
1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1971 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1972
1973 usleep_range(1000, 1500);
1974 }
1975}
1976
06855ef4
GW		 1977static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1978 struct ieee80211_conf *conf,
1979 struct rf_channel *rf,
1980 struct channel_info *info)
f4450616
BZ		 1981{
1982 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1983
d96aa640 1984 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1985 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1986
d96aa640 1987 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1988 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1989 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1990 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1991 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1992
1993 if (rf->channel > 14) {
1994 /*
1995 * When TX power is below 0, we should increase it by 7 to
25985edc 1996 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1997 * However this means that values between 0 and 7 have
1998 * double meaning, and we should set a 7DBm boost flag.
1999 */
2000 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 2001 (info->default_power1 >= 0));
f4450616 2002
8d1331b3
ID		 2003 if (info->default_power1 < 0)
2004 info->default_power1 += 7;
f4450616 2005
8d1331b3 2006 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 2007
2008 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 2009 (info->default_power2 >= 0));
f4450616 2010
8d1331b3
ID		 2011 if (info->default_power2 < 0)
2012 info->default_power2 += 7;
f4450616 2013
8d1331b3 2014 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 2015 } else {
8d1331b3
ID		 2016 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2017 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 2018 }
2019
2020 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2021
2022 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2023 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2024 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2025 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2026
2027 udelay(200);
2028
2029 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2030 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2031 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2032 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2033
2034 udelay(200);
2035
2036 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2037 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2038 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2039 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2040}
2041
06855ef4
GW		 2042static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2043 struct ieee80211_conf *conf,
2044 struct rf_channel *rf,
2045 struct channel_info *info)
f4450616 2046{
3a1c0128 2047 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2048 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2049
2050 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2051
2052 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2053 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2054 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2055
2056 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2057 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2058 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2059
2060 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2061 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2062 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2063
5a673964 2064 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2065 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2066 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2067
2068 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2069 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2070 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2071 rt2x00dev->default_ant.rx_chain_num <= 1);
2072 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2073 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2074 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2075 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2076 rt2x00dev->default_ant.tx_chain_num <= 1);
2077 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2078 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2079 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2080
f4450616
BZ		 2081 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2082 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2083 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2084
f1f12f98
SG		 2085 if (rt2x00_rt(rt2x00dev, RT3390)) {
2086 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2087 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2088 } else {
3a1c0128
GW		 2089 if (conf_is_ht40(conf)) {
2090 calib_tx = drv_data->calibration_bw40;
2091 calib_rx = drv_data->calibration_bw40;
2092 } else {
2093 calib_tx = drv_data->calibration_bw20;
2094 calib_rx = drv_data->calibration_bw20;
2095 }
f1f12f98
SG		 2096 }
2097
2098 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2099 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2100 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2101
2102 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2103 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2104 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2105
71976907 2106 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2107 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2108 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2109
2110 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2111 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2112 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2113 msleep(1);
2114 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2115 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2116}
2117
872834df
GW		 2118static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2119 struct ieee80211_conf *conf,
2120 struct rf_channel *rf,
2121 struct channel_info *info)
2122{
3a1c0128 2123 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2124 u8 rfcsr;
2125 u32 reg;
2126
2127 if (rf->channel <= 14) {
5d137dff
GW		 2128 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2129 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2130 } else {
2131 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2132 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2133 }
2134
2135 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2136 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2137
2138 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2139 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2140 if (rf->channel <= 14)
2141 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2142 else
2143 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2144 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2145
2146 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2147 if (rf->channel <= 14)
2148 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2149 else
2150 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2151 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2152
2153 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2154 if (rf->channel <= 14) {
2155 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2156 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2157 info->default_power1);
872834df
GW		 2158 } else {
2159 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2160 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2161 (info->default_power1 & 0x3) |
2162 ((info->default_power1 & 0xC) << 1));
2163 }
2164 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2165
2166 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2167 if (rf->channel <= 14) {
2168 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2169 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2170 info->default_power2);
872834df
GW		 2171 } else {
2172 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2173 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2174 (info->default_power2 & 0x3) |
2175 ((info->default_power2 & 0xC) << 1));
2176 }
2177 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2178
2179 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2180 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2181 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2182 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2183 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2184 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2185 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2186 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2187 if (rf->channel <= 14) {
2188 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2189 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2190 }
2191 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2192 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2193 } else {
2194 switch (rt2x00dev->default_ant.tx_chain_num) {
2195 case 1:
2196 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2197 case 2:
2198 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2199 break;
2200 }
2201
2202 switch (rt2x00dev->default_ant.rx_chain_num) {
2203 case 1:
2204 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2205 case 2:
2206 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2207 break;
2208 }
2209 }
2210 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2211
2212 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2213 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2214 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2215
3a1c0128
GW		 2216 if (conf_is_ht40(conf)) {
2217 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2218 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2219 } else {
2220 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2221 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2222 }
872834df
GW		 2223
2224 if (rf->channel <= 14) {
2225 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2226 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2227 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2228 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2229 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2230 rfcsr = 0x4c;
2231 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2232 drv_data->txmixer_gain_24g);
2233 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2234 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2235 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2236 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2237 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2238 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2239 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2240 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2241 } else {
58b8ae14
GW		 2242 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2243 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2244 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2245 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2246 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2247 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2248 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2249 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2250 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2251 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2252 rfcsr = 0x7a;
2253 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2254 drv_data->txmixer_gain_5g);
2255 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2256 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2257 if (rf->channel <= 64) {
2258 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2259 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2260 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2261 } else if (rf->channel <= 128) {
2262 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2263 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2264 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2265 } else {
2266 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2267 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2268 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2269 }
2270 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2271 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2272 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2273 }
2274
99bdf51a
GW		 2275 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2276 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2277 if (rf->channel <= 14)
99bdf51a 2278 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2279 else
99bdf51a
GW		 2280 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2281 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2282
2283 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2284 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2285 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2286}
60687ba7 2287
f42b0465
GJ		 2288static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2289 struct ieee80211_conf *conf,
2290 struct rf_channel *rf,
2291 struct channel_info *info)
2292{
2293 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2294 u8 txrx_agc_fc;
2295 u8 txrx_h20m;
2296 u8 rfcsr;
2297 u8 bbp;
2298 const bool txbf_enabled = false; /* TODO */
2299
2300 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2301 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2302 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2303 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2304 rt2800_bbp_write(rt2x00dev, 109, bbp);
2305
2306 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2307 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2308 rt2800_bbp_write(rt2x00dev, 110, bbp);
2309
2310 if (rf->channel <= 14) {
2311 /* Restore BBP 25 & 26 for 2.4 GHz */
2312 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2313 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2314 } else {
2315 /* Hard code BBP 25 & 26 for 5GHz */
2316
2317 /* Enable IQ Phase correction */
2318 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2319 /* Setup IQ Phase correction value */
2320 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2321 }
2322
2323 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2324 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2325
2326 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2327 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2328 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2329
2330 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2331 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2332 if (rf->channel <= 14)
2333 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2334 else
2335 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2336 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2337
2338 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2339 if (rf->channel <= 14) {
2340 rfcsr = 0;
2341 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2342 info->default_power1 & 0x1f);
2343 } else {
2344 if (rt2x00_is_usb(rt2x00dev))
2345 rfcsr = 0x40;
2346
2347 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2348 ((info->default_power1 & 0x18) << 1) |
2349 (info->default_power1 & 7));
2350 }
2351 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2352
2353 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2354 if (rf->channel <= 14) {
2355 rfcsr = 0;
2356 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2357 info->default_power2 & 0x1f);
2358 } else {
2359 if (rt2x00_is_usb(rt2x00dev))
2360 rfcsr = 0x40;
2361
2362 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2363 ((info->default_power2 & 0x18) << 1) |
2364 (info->default_power2 & 7));
2365 }
2366 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2367
2368 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2369 if (rf->channel <= 14) {
2370 rfcsr = 0;
2371 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2372 info->default_power3 & 0x1f);
2373 } else {
2374 if (rt2x00_is_usb(rt2x00dev))
2375 rfcsr = 0x40;
2376
2377 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2378 ((info->default_power3 & 0x18) << 1) |
2379 (info->default_power3 & 7));
2380 }
2381 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2382
2383 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2384 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2385 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2386 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2387 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2388 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2389 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2390 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2391 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2392
2393 switch (rt2x00dev->default_ant.tx_chain_num) {
2394 case 3:
2395 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2396 /* fallthrough */
2397 case 2:
2398 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2399 /* fallthrough */
2400 case 1:
2401 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2402 break;
2403 }
2404
2405 switch (rt2x00dev->default_ant.rx_chain_num) {
2406 case 3:
2407 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2408 /* fallthrough */
2409 case 2:
2410 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2411 /* fallthrough */
2412 case 1:
2413 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2414 break;
2415 }
2416 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2417
88452541 2418 rt2800_freq_cal_mode1(rt2x00dev);
f42b0465
GJ		 2419
2420 if (conf_is_ht40(conf)) {
2421 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2422 RFCSR24_TX_AGC_FC);
2423 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2424 RFCSR24_TX_H20M);
2425 } else {
2426 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2427 RFCSR24_TX_AGC_FC);
2428 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2429 RFCSR24_TX_H20M);
2430 }
2431
2432 /* NOTE: the reference driver does not writes the new value
2433 * back to RFCSR 32
2434 */
2435 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2436 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2437
2438 if (rf->channel <= 14)
2439 rfcsr = 0xa0;
2440 else
2441 rfcsr = 0x80;
2442 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2443
2444 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2445 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2446 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2447 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2448
2449 /* Band selection */
2450 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2451 if (rf->channel <= 14)
2452 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2453 else
2454 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2455 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2456
2457 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2458 if (rf->channel <= 14)
2459 rfcsr = 0x3c;
2460 else
2461 rfcsr = 0x20;
2462 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2463
2464 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2465 if (rf->channel <= 14)
2466 rfcsr = 0x1a;
2467 else
2468 rfcsr = 0x12;
2469 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2470
2471 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2472 if (rf->channel >= 1 && rf->channel <= 14)
2473 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2474 else if (rf->channel >= 36 && rf->channel <= 64)
2475 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2476 else if (rf->channel >= 100 && rf->channel <= 128)
2477 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2478 else
2479 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2480 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2481
2482 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2483 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2484 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2485
2486 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2487
2488 if (rf->channel <= 14) {
2489 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2490 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2491 } else {
2492 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2493 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2494 }
2495
2496 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2497 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2498 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2499
2500 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2501 if (rf->channel <= 14) {
2502 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2503 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2504 } else {
2505 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2506 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2507 }
2508 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2509
2510 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2511 if (rf->channel <= 14)
2512 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2513 else
2514 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2515
2516 if (txbf_enabled)
2517 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2518
2519 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2520
2521 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2522 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2523 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2524
2525 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2526 if (rf->channel <= 14)
2527 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2528 else
2529 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2530 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2531
2532 if (rf->channel <= 14) {
2533 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2534 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2535 } else {
2536 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2537 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2538 }
2539
2540 /* Initiate VCO calibration */
2541 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2542 if (rf->channel <= 14) {
2543 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2544 } else {
2545 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2546 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2547 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2548 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2549 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2550 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2551 }
2552 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2553
2554 if (rf->channel >= 1 && rf->channel <= 14) {
2555 rfcsr = 0x23;
2556 if (txbf_enabled)
2557 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2558 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2559
2560 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2561 } else if (rf->channel >= 36 && rf->channel <= 64) {
2562 rfcsr = 0x36;
2563 if (txbf_enabled)
2564 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2565 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2566
2567 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2568 } else if (rf->channel >= 100 && rf->channel <= 128) {
2569 rfcsr = 0x32;
2570 if (txbf_enabled)
2571 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2572 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2573
2574 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2575 } else {
2576 rfcsr = 0x30;
2577 if (txbf_enabled)
2578 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2579 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2580
2581 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2582 }
2583}
2584
7573cb5b 2585#define POWER_BOUND 0x27
8f821098 2586#define POWER_BOUND_5G 0x2b
0c9e5fb9 2587
a89534ed
WH		 2588static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2589 struct ieee80211_conf *conf,
2590 struct rf_channel *rf,
2591 struct channel_info *info)
2592{
2593 u8 rfcsr;
2594
2595 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2596 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2597 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2598 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2599 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2600
2601 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2602 if (info->default_power1 > POWER_BOUND)
2603 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2604 else
2605 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2606 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2607
88452541 2608 rt2800_freq_cal_mode1(rt2x00dev);
a89534ed
WH		 2609
2610 if (rf->channel <= 14) {
2611 if (rf->channel == 6)
2612 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2613 else
2614 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2615
2616 if (rf->channel >= 1 && rf->channel <= 6)
2617 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2618 else if (rf->channel >= 7 && rf->channel <= 11)
2619 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2620 else if (rf->channel >= 12 && rf->channel <= 14)
2621 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2622 }
2623}
2624
03839951
DG		 2625static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2626 struct ieee80211_conf *conf,
2627 struct rf_channel *rf,
2628 struct channel_info *info)
2629{
2630 u8 rfcsr;
2631
2632 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2633 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2634
2635 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2636 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2637 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2638
2639 if (info->default_power1 > POWER_BOUND)
2640 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2641 else
2642 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2643
2644 if (info->default_power2 > POWER_BOUND)
2645 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2646 else
2647 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2648
88452541 2649 rt2800_freq_cal_mode1(rt2x00dev);
03839951
DG		 2650
2651 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2652 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2653 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2654
2655 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2656 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2657 else
2658 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2659
2660 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2661 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2662 else
2663 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2664
2665 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2666 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2667
2668 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2669
2670 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2671}
2672
60687ba7 2673static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2674 struct ieee80211_conf *conf,
2675 struct rf_channel *rf,
2676 struct channel_info *info)
2677{
2678 u8 rfcsr;
adde5882
GJ		 2679
2680 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2681 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2682 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2683 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2684 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2685
2686 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2687 if (info->default_power1 > POWER_BOUND)
2688 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2689 else
2690 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2691 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2692
cff3d1f0
ZL		 2693 if (rt2x00_rt(rt2x00dev, RT5392)) {
2694 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2695 if (info->default_power2 > POWER_BOUND)
7573cb5b 2696 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2697 else
2698 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2699 info->default_power2);
2700 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2701 }
2702
adde5882 2703 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2704 if (rt2x00_rt(rt2x00dev, RT5392)) {
2705 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2706 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2707 }
adde5882
GJ		 2708 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2709 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2710 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2711 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2712 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2713
88452541 2714 rt2800_freq_cal_mode1(rt2x00dev);
adde5882 2715
adde5882
GJ		 2716 if (rf->channel <= 14) {
2717 int idx = rf->channel-1;
2718
c429dfef 2719 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2720 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2721 /* r55/r59 value array of channel 1~14 */
2722 static const char r55_bt_rev[] = {0x83, 0x83,
2723 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2724 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2725 static const char r59_bt_rev[] = {0x0e, 0x0e,
2726 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2727 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2728
2729 rt2800_rfcsr_write(rt2x00dev, 55,
2730 r55_bt_rev[idx]);
2731 rt2800_rfcsr_write(rt2x00dev, 59,
2732 r59_bt_rev[idx]);
2733 } else {
2734 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2735 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2736 0x88, 0x88, 0x86, 0x85, 0x84};
2737
2738 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2739 }
2740 } else {
2741 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2742 static const char r55_nonbt_rev[] = {0x23, 0x23,
2743 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2744 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2745 static const char r59_nonbt_rev[] = {0x07, 0x07,
2746 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2747 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2748
2749 rt2800_rfcsr_write(rt2x00dev, 55,
2750 r55_nonbt_rev[idx]);
2751 rt2800_rfcsr_write(rt2x00dev, 59,
2752 r59_nonbt_rev[idx]);
2ed71884 2753 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2754 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2755 static const char r59_non_bt[] = {0x8f, 0x8f,
2756 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2757 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2758
2759 rt2800_rfcsr_write(rt2x00dev, 59,
2760 r59_non_bt[idx]);
2761 }
2762 }
2763 }
60687ba7
RST		 2764}
2765
8f821098
SG		 2766static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2767 struct ieee80211_conf *conf,
2768 struct rf_channel *rf,
2769 struct channel_info *info)
2770{
2771 u8 rfcsr, ep_reg;
d5ae7a6b 2772 u32 reg;
8f821098
SG		 2773 int power_bound;
2774
2775 /* TODO */
2776 const bool is_11b = false;
2777 const bool is_type_ep = false;
2778
d5ae7a6b
SG		 2779 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2780 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2781 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2782 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2783
2784 /* Order of values on rf_channel entry: N, K, mod, R */
2785 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2786
2787 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2788 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2789 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2790 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2791 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2792
2793 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2794 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2795 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2796 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2797
2798 if (rf->channel <= 14) {
2799 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2800 /* FIXME: RF11 owerwrite ? */
2801 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2802 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2803 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2804 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2805 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2806 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2807 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2808 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2809 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2810 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2811 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2812 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2813 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2814 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2815 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2816 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2817 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2818 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2819 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2820 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2821 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2822 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2823 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2824 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2825 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2826 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2827 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2828 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2829
2830 /* TODO RF27 <- tssi */
2831
2832 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2833 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2834 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2835
2836 if (is_11b) {
2837 /* CCK */
2838 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2839 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2840 if (is_type_ep)
2841 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2842 else
2843 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2844 } else {
2845 /* OFDM */
2846 if (is_type_ep)
2847 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2848 else
2849 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2850 }
2851
2852 power_bound = POWER_BOUND;
2853 ep_reg = 0x2;
2854 } else {
2855 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2856 /* FIMXE: RF11 overwrite */
2857 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2858 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2859 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2860 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2861 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2862 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2863 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2864 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2865 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2866 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2867 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2868 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2869 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2870 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2871
2872 /* TODO RF27 <- tssi */
2873
2874 if (rf->channel >= 36 && rf->channel <= 64) {
2875
2876 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2877 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2878 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2879 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2880 if (rf->channel <= 50)
2881 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2882 else if (rf->channel >= 52)
2883 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2884 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2885 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2886 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2887 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2888 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2889 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2890 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2891 if (rf->channel <= 50) {
2892 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2893 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2894 } else if (rf->channel >= 52) {
2895 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2896 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2897 }
2898
2899 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2900 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2901 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2902
2903 } else if (rf->channel >= 100 && rf->channel <= 165) {
2904
2905 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2906 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2907 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2908 if (rf->channel <= 153) {
2909 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2910 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2911 } else if (rf->channel >= 155) {
2912 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2913 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2914 }
2915 if (rf->channel <= 138) {
2916 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2917 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2918 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2919 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2920 } else if (rf->channel >= 140) {
2921 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2922 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2923 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2924 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2925 }
2926 if (rf->channel <= 124)
2927 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2928 else if (rf->channel >= 126)
2929 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2930 if (rf->channel <= 138)
2931 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2932 else if (rf->channel >= 140)
2933 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2934 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2935 if (rf->channel <= 138)
2936 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2937 else if (rf->channel >= 140)
2938 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2939 if (rf->channel <= 128)
2940 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2941 else if (rf->channel >= 130)
2942 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2943 if (rf->channel <= 116)
2944 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2945 else if (rf->channel >= 118)
2946 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2947 if (rf->channel <= 138)
2948 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2949 else if (rf->channel >= 140)
2950 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2951 if (rf->channel <= 116)
2952 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2953 else if (rf->channel >= 118)
2954 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2955 }
2956
2957 power_bound = POWER_BOUND_5G;
2958 ep_reg = 0x3;
2959 }
2960
2961 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2962 if (info->default_power1 > power_bound)
2963 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2964 else
2965 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2966 if (is_type_ep)
2967 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2968 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2969
2970 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2971 if (info->default_power2 > power_bound)
8f821098
SG		 2972 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2973 else
2974 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2975 if (is_type_ep)
2976 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2977 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2978
2979 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2980 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2981 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2982
2983 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2984 rt2x00dev->default_ant.tx_chain_num >= 1);
2985 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2986 rt2x00dev->default_ant.tx_chain_num == 2);
2987 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2988
2989 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2990 rt2x00dev->default_ant.rx_chain_num >= 1);
2991 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2992 rt2x00dev->default_ant.rx_chain_num == 2);
2993 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2994
2995 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2996 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2997
2998 if (conf_is_ht40(conf))
2999 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3000 else
3001 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3002
3003 if (!is_11b) {
3004 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3005 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3006 }
3007
3008 /* TODO proper frequency adjustment */
88452541 3009 rt2800_freq_cal_mode1(rt2x00dev);
8f821098
SG		 3010
3011 /* TODO merge with others */
3012 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3013 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3014 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 3015
3016 /* BBP settings */
3017 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3018 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3019 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3020
3021 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3022 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3023 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3024 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3025
3026 /* GLRT band configuration */
3027 rt2800_bbp_write(rt2x00dev, 195, 128);
3028 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3029 rt2800_bbp_write(rt2x00dev, 195, 129);
3030 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3031 rt2800_bbp_write(rt2x00dev, 195, 130);
3032 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3033 rt2800_bbp_write(rt2x00dev, 195, 131);
3034 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3035 rt2800_bbp_write(rt2x00dev, 195, 133);
3036 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3037 rt2800_bbp_write(rt2x00dev, 195, 124);
3038 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3039}
3040
5bc2dd06
SG		 3041static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3042 const unsigned int word,
3043 const u8 value)
3044{
3045 u8 chain, reg;
3046
3047 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3048 rt2800_bbp_read(rt2x00dev, 27, &reg);
3049 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3050 rt2800_bbp_write(rt2x00dev, 27, reg);
3051
3052 rt2800_bbp_write(rt2x00dev, word, value);
3053 }
3054}
3055
8756130b
SG		 3056static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3057{
3058 u8 cal;
3059
415e3f2f 3060 /* TX0 IQ Gain */
8756130b 3061 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3062 if (channel <= 14)
3063 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3064 else if (channel >= 36 && channel <= 64)
3065 cal = rt2x00_eeprom_byte(rt2x00dev,
3066 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3067 else if (channel >= 100 && channel <= 138)
3068 cal = rt2x00_eeprom_byte(rt2x00dev,
3069 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3070 else if (channel >= 140 && channel <= 165)
3071 cal = rt2x00_eeprom_byte(rt2x00dev,
3072 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3073 else
3074 cal = 0;
8756130b
SG		 3075 rt2800_bbp_write(rt2x00dev, 159, cal);
3076
415e3f2f 3077 /* TX0 IQ Phase */
8756130b 3078 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3079 if (channel <= 14)
3080 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3081 else if (channel >= 36 && channel <= 64)
3082 cal = rt2x00_eeprom_byte(rt2x00dev,
3083 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3084 else if (channel >= 100 && channel <= 138)
3085 cal = rt2x00_eeprom_byte(rt2x00dev,
3086 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3087 else if (channel >= 140 && channel <= 165)
3088 cal = rt2x00_eeprom_byte(rt2x00dev,
3089 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3090 else
3091 cal = 0;
8756130b
SG		 3092 rt2800_bbp_write(rt2x00dev, 159, cal);
3093
415e3f2f 3094 /* TX1 IQ Gain */
8756130b 3095 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3096 if (channel <= 14)
3097 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3098 else if (channel >= 36 && channel <= 64)
3099 cal = rt2x00_eeprom_byte(rt2x00dev,
3100 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3101 else if (channel >= 100 && channel <= 138)
3102 cal = rt2x00_eeprom_byte(rt2x00dev,
3103 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3104 else if (channel >= 140 && channel <= 165)
3105 cal = rt2x00_eeprom_byte(rt2x00dev,
3106 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3107 else
3108 cal = 0;
8756130b
SG		 3109 rt2800_bbp_write(rt2x00dev, 159, cal);
3110
415e3f2f 3111 /* TX1 IQ Phase */
8756130b 3112 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3113 if (channel <= 14)
3114 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3115 else if (channel >= 36 && channel <= 64)
3116 cal = rt2x00_eeprom_byte(rt2x00dev,
3117 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3118 else if (channel >= 100 && channel <= 138)
3119 cal = rt2x00_eeprom_byte(rt2x00dev,
3120 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3121 else if (channel >= 140 && channel <= 165)
3122 cal = rt2x00_eeprom_byte(rt2x00dev,
3123 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3124 else
3125 cal = 0;
8756130b
SG		 3126 rt2800_bbp_write(rt2x00dev, 159, cal);
3127
415e3f2f
SG		 3128 /* FIXME: possible RX0, RX1 callibration ? */
3129
8756130b
SG		 3130 /* RF IQ compensation control */
3131 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3132 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3133 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3134
3135 /* RF IQ imbalance compensation control */
3136 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3137 cal = rt2x00_eeprom_byte(rt2x00dev,
3138 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3139 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3140}
3141
97aa03f1
GJ		 3142static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3143 unsigned int channel,
3144 char txpower)
3145{
fc739cfe
GJ		 3146 if (rt2x00_rt(rt2x00dev, RT3593))
3147 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3148
97aa03f1
GJ		 3149 if (channel <= 14)
3150 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3151
3152 if (rt2x00_rt(rt2x00dev, RT3593))
3153 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3154 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3155 else
3156 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3157}
3158
f4450616
BZ		 3159static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3160 struct ieee80211_conf *conf,
3161 struct rf_channel *rf,
3162 struct channel_info *info)
3163{
3164 u32 reg;
3165 unsigned int tx_pin;
a89534ed 3166 u8 bbp, rfcsr;
f4450616 3167
97aa03f1
GJ		 3168 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3169 info->default_power1);
3170 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3171 info->default_power2);
c0a14369
GJ		 3172 if (rt2x00dev->default_ant.tx_chain_num > 2)
3173 info->default_power3 =
3174 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3175 info->default_power3);
46323e11 3176
5aa57015
GW		 3177 switch (rt2x00dev->chip.rf) {
3178 case RF2020:
3179 case RF3020:
3180 case RF3021:
3181 case RF3022:
3182 case RF3320:
06855ef4 3183 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3184 break;
3185 case RF3052:
872834df 3186 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3187 break;
f42b0465
GJ		 3188 case RF3053:
3189 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3190 break;
a89534ed
WH		 3191 case RF3290:
3192 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3193 break;
03839951
DG		 3194 case RF3322:
3195 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3196 break;
3b9b74ba 3197 case RF3070:
ccf91bd6 3198 case RF5360:
ac0372ab 3199 case RF5362:
5aa57015 3200 case RF5370:
2ed71884 3201 case RF5372:
5aa57015 3202 case RF5390:
cff3d1f0 3203 case RF5392:
adde5882 3204 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3205 break;
8f821098
SG		 3206 case RF5592:
3207 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3208 break;
5aa57015 3209 default:
06855ef4 3210 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3211 }
f4450616 3212
3b9b74ba
SG		 3213 if (rt2x00_rf(rt2x00dev, RF3070) ||
3214 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3215 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed 3216 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3217 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3218 rt2x00_rf(rt2x00dev, RF5370) ||
3219 rt2x00_rf(rt2x00dev, RF5372) ||
3220 rt2x00_rf(rt2x00dev, RF5390) ||
3221 rt2x00_rf(rt2x00dev, RF5392)) {
3222 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3223 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3224 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3225 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3226
3227 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3228 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3229 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3230 }
3231
f4450616
BZ		 3232 /*
3233 * Change BBP settings
3234 */
03839951
DG		 3235 if (rt2x00_rt(rt2x00dev, RT3352)) {
3236 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3237 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3238 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3239 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3240 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3241 if (rf->channel > 14) {
3242 /* Disable CCK Packet detection on 5GHz */
3243 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3244 } else {
3245 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3246 }
3247
3248 if (conf_is_ht40(conf))
3249 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3250 else
3251 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3252
3253 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3254 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3255 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3256 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3257 } else {
3258 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3259 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3260 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3261 rt2800_bbp_write(rt2x00dev, 86, 0);
3262 }
f4450616
BZ		 3263
3264 if (rf->channel <= 14) {
2ed71884 3265 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3266 !rt2x00_rt(rt2x00dev, RT5392)) {
c429dfef 3267 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3268 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3269 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3270 } else {
f42b0465
GJ		 3271 if (rt2x00_rt(rt2x00dev, RT3593))
3272 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3273 else
3274 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3275 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3276 }
f42b0465
GJ		 3277 if (rt2x00_rt(rt2x00dev, RT3593))
3278 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3279 }
f42b0465 3280
f4450616 3281 } else {
872834df
GW		 3282 if (rt2x00_rt(rt2x00dev, RT3572))
3283 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3284 else if (rt2x00_rt(rt2x00dev, RT3593))
3285 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3286 else
3287 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3288
f42b0465
GJ		 3289 if (rt2x00_rt(rt2x00dev, RT3593))
3290 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3291
c429dfef 3292 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3293 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3294 else
3295 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3296 }
3297
3298 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3299 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3300 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3301 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3302 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3303
872834df
GW		 3304 if (rt2x00_rt(rt2x00dev, RT3572))
3305 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3306
f4450616
BZ		 3307 tx_pin = 0;
3308
bb16d488
GJ		 3309 switch (rt2x00dev->default_ant.tx_chain_num) {
3310 case 3:
3311 /* Turn on tertiary PAs */
3312 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3313 rf->channel > 14);
3314 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3315 rf->channel <= 14);
3316 /* fall-through */
3317 case 2:
3318 /* Turn on secondary PAs */
65f31b5e
GW		 3319 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3320 rf->channel > 14);
3321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3322 rf->channel <= 14);
bb16d488
GJ		 3323 /* fall-through */
3324 case 1:
3325 /* Turn on primary PAs */
3326 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3327 rf->channel > 14);
c429dfef 3328 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3330 else
3331 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3332 rf->channel <= 14);
3333 break;
f4450616
BZ		 3334 }
3335
bb16d488
GJ		 3336 switch (rt2x00dev->default_ant.rx_chain_num) {
3337 case 3:
3338 /* Turn on tertiary LNAs */
3339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3340 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3341 /* fall-through */
3342 case 2:
3343 /* Turn on secondary LNAs */
f4450616
BZ		 3344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3345 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3346 /* fall-through */
3347 case 1:
3348 /* Turn on primary LNAs */
3349 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3350 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3351 break;
f4450616
BZ		 3352 }
3353
f4450616
BZ		 3354 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3355 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3356
3357 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3358
733aec6a 3359 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3360 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3361
733aec6a
GJ		 3362 /* AGC init */
3363 if (rf->channel <= 14)
3364 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3365 else
3366 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3367
3368 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3369 }
3370
f42b0465 3371 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3372 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3373
60751001
GJ		 3374 /* Band selection */
3375 if (rt2x00_is_usb(rt2x00dev) ||
3376 rt2x00_is_pcie(rt2x00dev)) {
3377 /* GPIO #8 controls all paths */
f42b0465
GJ		 3378 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3379 if (rf->channel <= 14)
3380 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3381 else
3382 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3383 }
f42b0465 3384
60751001
GJ		 3385 /* LNA PE control. */
3386 if (rt2x00_is_usb(rt2x00dev)) {
3387 /* GPIO #4 controls PE0 and PE1,
3388 * GPIO #7 controls PE2
3389 */
f42b0465
GJ		 3390 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3391 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3392
f42b0465
GJ		 3393 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3394 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3395 } else if (rt2x00_is_pcie(rt2x00dev)) {
3396 /* GPIO #4 controls PE0, PE1 and PE2 */
3397 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3398 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3399 }
3400
60751001
GJ		 3401 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3402
f42b0465
GJ		 3403 /* AGC init */
3404 if (rf->channel <= 14)
3405 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3406 else
3407 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3408
3409 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3410
3411 usleep_range(1000, 1500);
3412 }
3413
6803141b
SG		 3414 if (rt2x00_rt(rt2x00dev, RT5592)) {
3415 rt2800_bbp_write(rt2x00dev, 195, 141);
3416 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3417
8ba0ebf3
SG		 3418 /* AGC init */
3419 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3420 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3421
8756130b 3422 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3423 }
3424
f4450616
BZ		 3425 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3426 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3427 rt2800_bbp_write(rt2x00dev, 4, bbp);
3428
3429 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3430 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3431 rt2800_bbp_write(rt2x00dev, 3, bbp);
3432
8d0c9b65 3433 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3434 if (conf_is_ht40(conf)) {
3435 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3436 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3437 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3438 } else {
3439 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3440 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3441 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3442 }
3443 }
3444
3445 msleep(1);
977206d7
HS		 3446
3447 /*
3448 * Clear channel statistic counters
3449 */
3450 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3451 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3452 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3453
3454 /*
3455 * Clear update flag
3456 */
3457 if (rt2x00_rt(rt2x00dev, RT3352)) {
3458 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3459 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3460 rt2800_bbp_write(rt2x00dev, 49, bbp);
3461 }
f4450616
BZ		 3462}
3463
9e33a355
HS		 3464static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3465{
3466 u8 tssi_bounds[9];
3467 u8 current_tssi;
3468 u16 eeprom;
3469 u8 step;
3470 int i;
3471
6e956da2
SG		 3472 /*
3473 * First check if temperature compensation is supported.
3474 */
3475 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3476 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3477 return 0;
3478
9e33a355
HS		 3479 /*
3480 * Read TSSI boundaries for temperature compensation from
3481 * the EEPROM.
3482 *
3483 * Array idx 0 1 2 3 4 5 6 7 8
3484 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3485 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3486 */
57fbcce3 3487 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 3488 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3489 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3490 EEPROM_TSSI_BOUND_BG1_MINUS4);
3491 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3492 EEPROM_TSSI_BOUND_BG1_MINUS3);
3493
3e38d3da 3494 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3495 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3496 EEPROM_TSSI_BOUND_BG2_MINUS2);
3497 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3498 EEPROM_TSSI_BOUND_BG2_MINUS1);
3499
3e38d3da 3500 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3501 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3502 EEPROM_TSSI_BOUND_BG3_REF);
3503 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3504 EEPROM_TSSI_BOUND_BG3_PLUS1);
3505
3e38d3da 3506 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3507 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3508 EEPROM_TSSI_BOUND_BG4_PLUS2);
3509 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3510 EEPROM_TSSI_BOUND_BG4_PLUS3);
3511
3e38d3da 3512 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3513 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3514 EEPROM_TSSI_BOUND_BG5_PLUS4);
3515
3516 step = rt2x00_get_field16(eeprom,
3517 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3518 } else {
3e38d3da 3519 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3520 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3521 EEPROM_TSSI_BOUND_A1_MINUS4);
3522 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3523 EEPROM_TSSI_BOUND_A1_MINUS3);
3524
3e38d3da 3525 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3526 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3527 EEPROM_TSSI_BOUND_A2_MINUS2);
3528 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3529 EEPROM_TSSI_BOUND_A2_MINUS1);
3530
3e38d3da 3531 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3532 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3533 EEPROM_TSSI_BOUND_A3_REF);
3534 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3535 EEPROM_TSSI_BOUND_A3_PLUS1);
3536
3e38d3da 3537 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3538 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3539 EEPROM_TSSI_BOUND_A4_PLUS2);
3540 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3541 EEPROM_TSSI_BOUND_A4_PLUS3);
3542
3e38d3da 3543 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3544 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3545 EEPROM_TSSI_BOUND_A5_PLUS4);
3546
3547 step = rt2x00_get_field16(eeprom,
3548 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3549 }
3550
3551 /*
3552 * Check if temperature compensation is supported.
3553 */
bf7e1abe 3554 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3555 return 0;
3556
3557 /*
3558 * Read current TSSI (BBP 49).
3559 */
3560 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3561
3562 /*
3563 * Compare TSSI value (BBP49) with the compensation boundaries
3564 * from the EEPROM and increase or decrease tx power.
3565 */
3566 for (i = 0; i <= 3; i++) {
3567 if (current_tssi > tssi_bounds[i])
3568 break;
3569 }
3570
3571 if (i == 4) {
3572 for (i = 8; i >= 5; i--) {
3573 if (current_tssi < tssi_bounds[i])
3574 break;
3575 }
3576 }
3577
3578 return (i - 4) * step;
3579}
3580
e90c54b2 3581static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
57fbcce3 3582 enum nl80211_band band)
e90c54b2
RJH		 3583{
3584 u16 eeprom;
3585 u8 comp_en;
3586 u8 comp_type;
75faae8b 3587 int comp_value = 0;
e90c54b2 3588
3e38d3da 3589 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3590
75faae8b
HS		 3591 /*
3592 * HT40 compensation not required.
3593 */
3594 if (eeprom == 0xffff ||
3595 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3596 return 0;
3597
57fbcce3 3598 if (band == NL80211_BAND_2GHZ) {
e90c54b2
RJH		 3599 comp_en = rt2x00_get_field16(eeprom,
3600 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3601 if (comp_en) {
3602 comp_type = rt2x00_get_field16(eeprom,
3603 EEPROM_TXPOWER_DELTA_TYPE_2G);
3604 comp_value = rt2x00_get_field16(eeprom,
3605 EEPROM_TXPOWER_DELTA_VALUE_2G);
3606 if (!comp_type)
3607 comp_value = -comp_value;
3608 }
3609 } else {
3610 comp_en = rt2x00_get_field16(eeprom,
3611 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3612 if (comp_en) {
3613 comp_type = rt2x00_get_field16(eeprom,
3614 EEPROM_TXPOWER_DELTA_TYPE_5G);
3615 comp_value = rt2x00_get_field16(eeprom,
3616 EEPROM_TXPOWER_DELTA_VALUE_5G);
3617 if (!comp_type)
3618 comp_value = -comp_value;
3619 }
3620 }
3621
3622 return comp_value;
3623}
3624
1e4cf249
SG		 3625static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3626 int power_level, int max_power)
3627{
3628 int delta;
3629
c429dfef 3630 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 3631 return 0;
3632
3633 /*
3634 * XXX: We don't know the maximum transmit power of our hardware since
3635 * the EEPROM doesn't expose it. We only know that we are calibrated
3636 * to 100% tx power.
3637 *
3638 * Hence, we assume the regulatory limit that cfg80211 calulated for
3639 * the current channel is our maximum and if we are requested to lower
3640 * the value we just reduce our tx power accordingly.
3641 */
3642 delta = power_level - max_power;
3643 return min(delta, 0);
3644}
3645
fa71a160 3646static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
57fbcce3 3647 enum nl80211_band band, int power_level,
fa71a160 3648 u8 txpower, int delta)
e90c54b2 3649{
e90c54b2
RJH		 3650 u16 eeprom;
3651 u8 criterion;
3652 u8 eirp_txpower;
3653 u8 eirp_txpower_criterion;
3654 u8 reg_limit;
e90c54b2 3655
34542ff5
GJ		 3656 if (rt2x00_rt(rt2x00dev, RT3593))
3657 return min_t(u8, txpower, 0xc);
3658
c429dfef 3659 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 3660 /*
3661 * Check if eirp txpower exceed txpower_limit.
3662 * We use OFDM 6M as criterion and its eirp txpower
3663 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3664 * .11b data rate need add additional 4dbm
3665 * when calculating eirp txpower.
3666 */
022138ca
GJ		 3667 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3668 1, &eeprom);
d9bceaeb
SG		 3669 criterion = rt2x00_get_field16(eeprom,
3670 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3671
3e38d3da 3672 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3673 &eeprom);
e90c54b2 3674
57fbcce3 3675 if (band == NL80211_BAND_2GHZ)
e90c54b2
RJH		 3676 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3677 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3678 else
3679 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3680 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3681
3682 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3683 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3684
3685 reg_limit = (eirp_txpower > power_level) ?
3686 (eirp_txpower - power_level) : 0;
3687 } else
3688 reg_limit = 0;
3689
19f3fa24
SG		 3690 txpower = max(0, txpower + delta - reg_limit);
3691 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3692}
3693
34542ff5
GJ		 3694
3695enum {
3696 TX_PWR_CFG_0_IDX,
3697 TX_PWR_CFG_1_IDX,
3698 TX_PWR_CFG_2_IDX,
3699 TX_PWR_CFG_3_IDX,
3700 TX_PWR_CFG_4_IDX,
3701 TX_PWR_CFG_5_IDX,
3702 TX_PWR_CFG_6_IDX,
3703 TX_PWR_CFG_7_IDX,
3704 TX_PWR_CFG_8_IDX,
3705 TX_PWR_CFG_9_IDX,
3706 TX_PWR_CFG_0_EXT_IDX,
3707 TX_PWR_CFG_1_EXT_IDX,
3708 TX_PWR_CFG_2_EXT_IDX,
3709 TX_PWR_CFG_3_EXT_IDX,
3710 TX_PWR_CFG_4_EXT_IDX,
3711 TX_PWR_CFG_IDX_COUNT,
3712};
3713
3714static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3715 struct ieee80211_channel *chan,
3716 int power_level)
3717{
3718 u8 txpower;
3719 u16 eeprom;
3720 u32 regs[TX_PWR_CFG_IDX_COUNT];
3721 unsigned int offset;
57fbcce3 3722 enum nl80211_band band = chan->band;
34542ff5
GJ		 3723 int delta;
3724 int i;
3725
3726 memset(regs, '\0', sizeof(regs));
3727
3728 /* TODO: adapt TX power reduction from the rt28xx code */
3729
3730 /* calculate temperature compensation delta */
3731 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3732
57fbcce3 3733 if (band == NL80211_BAND_5GHZ)
34542ff5
GJ		 3734 offset = 16;
3735 else
3736 offset = 0;
3737
3738 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3739 offset += 8;
3740
3741 /* read the next four txpower values */
3742 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3743 offset, &eeprom);
3744
3745 /* CCK 1MBS,2MBS */
3746 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3747 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3748 txpower, delta);
3749 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3750 TX_PWR_CFG_0_CCK1_CH0, txpower);
3751 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3752 TX_PWR_CFG_0_CCK1_CH1, txpower);
3753 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3754 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3755
3756 /* CCK 5.5MBS,11MBS */
3757 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3758 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3759 txpower, delta);
3760 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3761 TX_PWR_CFG_0_CCK5_CH0, txpower);
3762 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3763 TX_PWR_CFG_0_CCK5_CH1, txpower);
3764 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3765 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3766
3767 /* OFDM 6MBS,9MBS */
3768 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3769 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3770 txpower, delta);
3771 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3772 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3773 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3774 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3775 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3776 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3777
3778 /* OFDM 12MBS,18MBS */
3779 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3780 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3781 txpower, delta);
3782 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3783 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3784 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3785 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3786 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3787 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3788
3789 /* read the next four txpower values */
3790 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3791 offset + 1, &eeprom);
3792
3793 /* OFDM 24MBS,36MBS */
3794 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3795 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3796 txpower, delta);
3797 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3798 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3799 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3800 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3801 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3802 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3803
3804 /* OFDM 48MBS */
3805 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3806 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3807 txpower, delta);
3808 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3809 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3810 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3811 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3812 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3813 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3814
3815 /* OFDM 54MBS */
3816 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3817 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3818 txpower, delta);
3819 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3820 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3821 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3822 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3823 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3824 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3825
3826 /* read the next four txpower values */
3827 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3828 offset + 2, &eeprom);
3829
3830 /* MCS 0,1 */
3831 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3833 txpower, delta);
3834 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3835 TX_PWR_CFG_1_MCS0_CH0, txpower);
3836 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3837 TX_PWR_CFG_1_MCS0_CH1, txpower);
3838 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3839 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3840
3841 /* MCS 2,3 */
3842 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3843 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3844 txpower, delta);
3845 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3846 TX_PWR_CFG_1_MCS2_CH0, txpower);
3847 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3848 TX_PWR_CFG_1_MCS2_CH1, txpower);
3849 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3850 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3851
3852 /* MCS 4,5 */
3853 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3854 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3855 txpower, delta);
3856 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3857 TX_PWR_CFG_2_MCS4_CH0, txpower);
3858 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3859 TX_PWR_CFG_2_MCS4_CH1, txpower);
3860 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3861 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3862
3863 /* MCS 6 */
3864 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3865 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3866 txpower, delta);
3867 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3868 TX_PWR_CFG_2_MCS6_CH0, txpower);
3869 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3870 TX_PWR_CFG_2_MCS6_CH1, txpower);
3871 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3872 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3873
3874 /* read the next four txpower values */
3875 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3876 offset + 3, &eeprom);
3877
3878 /* MCS 7 */
3879 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3880 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3881 txpower, delta);
3882 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3883 TX_PWR_CFG_7_MCS7_CH0, txpower);
3884 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3885 TX_PWR_CFG_7_MCS7_CH1, txpower);
3886 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3887 TX_PWR_CFG_7_MCS7_CH2, txpower);
3888
3889 /* MCS 8,9 */
3890 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3891 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3892 txpower, delta);
3893 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3894 TX_PWR_CFG_2_MCS8_CH0, txpower);
3895 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3896 TX_PWR_CFG_2_MCS8_CH1, txpower);
3897 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3898 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3899
3900 /* MCS 10,11 */
3901 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3902 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3903 txpower, delta);
3904 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3905 TX_PWR_CFG_2_MCS10_CH0, txpower);
3906 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3907 TX_PWR_CFG_2_MCS10_CH1, txpower);
3908 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3909 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3910
3911 /* MCS 12,13 */
3912 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3913 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3914 txpower, delta);
3915 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3916 TX_PWR_CFG_3_MCS12_CH0, txpower);
3917 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3918 TX_PWR_CFG_3_MCS12_CH1, txpower);
3919 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3920 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3921
3922 /* read the next four txpower values */
3923 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3924 offset + 4, &eeprom);
3925
3926 /* MCS 14 */
3927 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3928 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3929 txpower, delta);
3930 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3931 TX_PWR_CFG_3_MCS14_CH0, txpower);
3932 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3933 TX_PWR_CFG_3_MCS14_CH1, txpower);
3934 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3935 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3936
3937 /* MCS 15 */
3938 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3939 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3940 txpower, delta);
3941 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3942 TX_PWR_CFG_8_MCS15_CH0, txpower);
3943 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3944 TX_PWR_CFG_8_MCS15_CH1, txpower);
3945 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3946 TX_PWR_CFG_8_MCS15_CH2, txpower);
3947
3948 /* MCS 16,17 */
3949 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3950 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3951 txpower, delta);
3952 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3953 TX_PWR_CFG_5_MCS16_CH0, txpower);
3954 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3955 TX_PWR_CFG_5_MCS16_CH1, txpower);
3956 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3957 TX_PWR_CFG_5_MCS16_CH2, txpower);
3958
3959 /* MCS 18,19 */
3960 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3961 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3962 txpower, delta);
3963 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3964 TX_PWR_CFG_5_MCS18_CH0, txpower);
3965 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3966 TX_PWR_CFG_5_MCS18_CH1, txpower);
3967 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3968 TX_PWR_CFG_5_MCS18_CH2, txpower);
3969
3970 /* read the next four txpower values */
3971 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3972 offset + 5, &eeprom);
3973
3974 /* MCS 20,21 */
3975 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3976 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3977 txpower, delta);
3978 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3979 TX_PWR_CFG_6_MCS20_CH0, txpower);
3980 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3981 TX_PWR_CFG_6_MCS20_CH1, txpower);
3982 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3983 TX_PWR_CFG_6_MCS20_CH2, txpower);
3984
3985 /* MCS 22 */
3986 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3987 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3988 txpower, delta);
3989 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3990 TX_PWR_CFG_6_MCS22_CH0, txpower);
3991 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3992 TX_PWR_CFG_6_MCS22_CH1, txpower);
3993 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3994 TX_PWR_CFG_6_MCS22_CH2, txpower);
3995
3996 /* MCS 23 */
3997 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3998 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3999 txpower, delta);
4000 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4001 TX_PWR_CFG_8_MCS23_CH0, txpower);
4002 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4003 TX_PWR_CFG_8_MCS23_CH1, txpower);
4004 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4005 TX_PWR_CFG_8_MCS23_CH2, txpower);
4006
4007 /* read the next four txpower values */
4008 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4009 offset + 6, &eeprom);
4010
4011 /* STBC, MCS 0,1 */
4012 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4013 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4014 txpower, delta);
4015 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4016 TX_PWR_CFG_3_STBC0_CH0, txpower);
4017 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4018 TX_PWR_CFG_3_STBC0_CH1, txpower);
4019 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4020 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4021
4022 /* STBC, MCS 2,3 */
4023 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4024 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4025 txpower, delta);
4026 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4027 TX_PWR_CFG_3_STBC2_CH0, txpower);
4028 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4029 TX_PWR_CFG_3_STBC2_CH1, txpower);
4030 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4031 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4032
4033 /* STBC, MCS 4,5 */
4034 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4035 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4036 txpower, delta);
4037 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4038 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4039 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4040 txpower);
4041
4042 /* STBC, MCS 6 */
4043 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4044 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4045 txpower, delta);
4046 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4047 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4048 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4049 txpower);
4050
4051 /* read the next four txpower values */
4052 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4053 offset + 7, &eeprom);
4054
4055 /* STBC, MCS 7 */
4056 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4057 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4058 txpower, delta);
4059 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4060 TX_PWR_CFG_9_STBC7_CH0, txpower);
4061 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4062 TX_PWR_CFG_9_STBC7_CH1, txpower);
4063 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4064 TX_PWR_CFG_9_STBC7_CH2, txpower);
4065
4066 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4067 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4068 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4069 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4070 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4071 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4072 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4073 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4074 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4075 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4076
4077 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4078 regs[TX_PWR_CFG_0_EXT_IDX]);
4079 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4080 regs[TX_PWR_CFG_1_EXT_IDX]);
4081 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4082 regs[TX_PWR_CFG_2_EXT_IDX]);
4083 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4084 regs[TX_PWR_CFG_3_EXT_IDX]);
4085 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4086 regs[TX_PWR_CFG_4_EXT_IDX]);
4087
4088 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4089 rt2x00_dbg(rt2x00dev,
4090 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
57fbcce3 4091 (band == NL80211_BAND_5GHZ) ? '5' : '2',
34542ff5
GJ		 4092 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4093 '4' : '2',
4094 (i > TX_PWR_CFG_9_IDX) ?
4095 (i - TX_PWR_CFG_9_IDX - 1) : i,
4096 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4097 (unsigned long) regs[i]);
4098}
4099
7a66205a
SG		 4100/*
4101 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4102 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4103 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4104 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4105 * Reference per rate transmit power values are located in the EEPROM at
4106 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4107 * current conditions (i.e. band, bandwidth, temperature, user settings).
4108 */
34542ff5
GJ		 4109static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4110 struct ieee80211_channel *chan,
4111 int power_level)
f4450616 4112{
cee2c731 4113 u8 txpower, r1;
5e846004 4114 u16 eeprom;
cee2c731
SG		 4115 u32 reg, offset;
4116 int i, is_rate_b, delta, power_ctrl;
57fbcce3 4117 enum nl80211_band band = chan->band;
2af242e1
HS		 4118
4119 /*
7a66205a
SG		 4120 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4121 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4122 */
4123 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4124
9e33a355 4125 /*
7a66205a
SG		 4126 * Calculate temperature compensation. Depends on measurement of current
4127 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4128 * to temperature or maybe other factors) is smaller or bigger than
4129 * expected. We adjust it, based on TSSI reference and boundaries values
4130 * provided in EEPROM.
9e33a355 4131 */
87dd2d76
SG		 4132 switch (rt2x00dev->chip.rt) {
4133 case RT2860:
4134 case RT2872:
4135 case RT2883:
4136 case RT3070:
4137 case RT3071:
4138 case RT3090:
4139 case RT3572:
4140 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4141 break;
4142 default:
4143 /* TODO: temperature compensation code for other chips. */
4144 break;
4145 }
f4450616 4146
1e4cf249 4147 /*
7a66205a
SG		 4148 * Decrease power according to user settings, on devices with unknown
4149 * maximum tx power. For other devices we take user power_level into
4150 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4151 */
4152 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4153 chan->max_power);
4154
5e846004 4155 /*
cee2c731
SG		 4156 * BBP_R1 controls TX power for all rates, it allow to set the following
4157 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4158 *
4159 * TODO: we do not use +6 dBm option to do not increase power beyond
4160 * regulatory limit, however this could be utilized for devices with
4161 * CAPABILITY_POWER_LIMIT.
8c8d2017 4162 */
87dd2d76
SG		 4163 if (delta <= -12) {
4164 power_ctrl = 2;
4165 delta += 12;
4166 } else if (delta <= -6) {
4167 power_ctrl = 1;
4168 delta += 6;
4169 } else {
4170 power_ctrl = 0;
cee2c731 4171 }
87dd2d76
SG		 4172 rt2800_bbp_read(rt2x00dev, 1, &r1);
4173 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4174 rt2800_bbp_write(rt2x00dev, 1, r1);
8c8d2017 4175
5e846004
HS		 4176 offset = TX_PWR_CFG_0;
4177
4178 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4179 /* just to be safe */
4180 if (offset > TX_PWR_CFG_4)
4181 break;
4182
4183 rt2800_register_read(rt2x00dev, offset, &reg);
4184
4185 /* read the next four txpower values */
022138ca
GJ		 4186 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4187 i, &eeprom);
5e846004 4188
e90c54b2
RJH		 4189 is_rate_b = i ? 0 : 1;
4190 /*
4191 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4192 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4193 * TX_PWR_CFG_4: unknown
4194 */
5e846004
HS		 4195 txpower = rt2x00_get_field16(eeprom,
4196 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4197 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4198 power_level, txpower, delta);
e90c54b2 4199 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4200
e90c54b2
RJH		 4201 /*
4202 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4203 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4204 * TX_PWR_CFG_4: unknown
4205 */
5e846004
HS		 4206 txpower = rt2x00_get_field16(eeprom,
4207 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4208 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4209 power_level, txpower, delta);
e90c54b2 4210 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4211
e90c54b2
RJH		 4212 /*
4213 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4214 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4215 * TX_PWR_CFG_4: unknown
4216 */
5e846004
HS		 4217 txpower = rt2x00_get_field16(eeprom,
4218 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4219 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4220 power_level, txpower, delta);
e90c54b2 4221 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4222
e90c54b2
RJH		 4223 /*
4224 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4225 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4226 * TX_PWR_CFG_4: unknown
4227 */
5e846004
HS		 4228 txpower = rt2x00_get_field16(eeprom,
4229 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4230 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4231 power_level, txpower, delta);
e90c54b2 4232 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4233
4234 /* read the next four txpower values */
022138ca
GJ		 4235 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4236 i + 1, &eeprom);
5e846004 4237
e90c54b2
RJH		 4238 is_rate_b = 0;
4239 /*
4240 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4241 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4242 * TX_PWR_CFG_4: unknown
4243 */
5e846004
HS		 4244 txpower = rt2x00_get_field16(eeprom,
4245 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4246 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4247 power_level, txpower, delta);
e90c54b2 4248 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4249
e90c54b2
RJH		 4250 /*
4251 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4252 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4253 * TX_PWR_CFG_4: unknown
4254 */
5e846004
HS		 4255 txpower = rt2x00_get_field16(eeprom,
4256 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4257 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4258 power_level, txpower, delta);
e90c54b2 4259 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4260
e90c54b2
RJH		 4261 /*
4262 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4263 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4264 * TX_PWR_CFG_4: unknown
4265 */
5e846004
HS		 4266 txpower = rt2x00_get_field16(eeprom,
4267 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4268 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4269 power_level, txpower, delta);
e90c54b2 4270 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4271
e90c54b2
RJH		 4272 /*
4273 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4274 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4275 * TX_PWR_CFG_4: unknown
4276 */
5e846004
HS		 4277 txpower = rt2x00_get_field16(eeprom,
4278 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4279 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4280 power_level, txpower, delta);
e90c54b2 4281 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4282
4283 rt2800_register_write(rt2x00dev, offset, reg);
4284
4285 /* next TX_PWR_CFG register */
4286 offset += 4;
4287 }
f4450616
BZ		 4288}
4289
34542ff5
GJ		 4290static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4291 struct ieee80211_channel *chan,
4292 int power_level)
4293{
4294 if (rt2x00_rt(rt2x00dev, RT3593))
4295 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4296 else
4297 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4298}
4299
9e33a355
HS		 4300void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4301{
675a0b04 4302 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4303 rt2x00dev->tx_power);
4304}
4305EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4306
2e9c43dd
JL		 4307void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4308{
4309 u32 tx_pin;
4310 u8 rfcsr;
4311
4312 /*
4313 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4314 * designed to be controlled in oscillation frequency by a voltage
4315 * input. Maybe the temperature will affect the frequency of
4316 * oscillation to be shifted. The VCO calibration will be called
4317 * periodically to adjust the frequency to be precision.
4318 */
4319
4320 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4321 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4322 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4323
4324 switch (rt2x00dev->chip.rf) {
4325 case RF2020:
4326 case RF3020:
4327 case RF3021:
4328 case RF3022:
4329 case RF3320:
4330 case RF3052:
4331 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4332 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4333 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4334 break;
1095df07 4335 case RF3053:
3b9b74ba 4336 case RF3070:
a89534ed 4337 case RF3290:
ccf91bd6 4338 case RF5360:
ac0372ab 4339 case RF5362:
2e9c43dd
JL		 4340 case RF5370:
4341 case RF5372:
4342 case RF5390:
cff3d1f0 4343 case RF5392:
2e9c43dd 4344 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4345 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4346 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4347 break;
4348 default:
4349 return;
4350 }
4351
4352 mdelay(1);
4353
4354 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4355 if (rt2x00dev->rf_channel <= 14) {
4356 switch (rt2x00dev->default_ant.tx_chain_num) {
4357 case 3:
4358 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4359 /* fall through */
4360 case 2:
4361 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4362 /* fall through */
4363 case 1:
4364 default:
4365 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4366 break;
4367 }
4368 } else {
4369 switch (rt2x00dev->default_ant.tx_chain_num) {
4370 case 3:
4371 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4372 /* fall through */
4373 case 2:
4374 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4375 /* fall through */
4376 case 1:
4377 default:
4378 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4379 break;
4380 }
4381 }
4382 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4383
4384}
4385EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4386
f4450616
BZ		 4387static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4388 struct rt2x00lib_conf *libconf)
4389{
4390 u32 reg;
4391
4392 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4393 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4394 libconf->conf->short_frame_max_tx_count);
4395 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4396 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4397 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4398}
4399
4400static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4401 struct rt2x00lib_conf *libconf)
4402{
4403 enum dev_state state =
4404 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4405 STATE_SLEEP : STATE_AWAKE;
4406 u32 reg;
4407
4408 if (state == STATE_SLEEP) {
4409 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4410
4411 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4412 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4413 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4414 libconf->conf->listen_interval - 1);
4415 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4416 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4417
4418 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4419 } else {
f4450616
BZ		 4420 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4421 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4422 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4423 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4424 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4425
4426 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4427 }
4428}
4429
4430void rt2800_config(struct rt2x00_dev *rt2x00dev,
4431 struct rt2x00lib_conf *libconf,
4432 const unsigned int flags)
4433{
4434 /* Always recalculate LNA gain before changing configuration */
4435 rt2800_config_lna_gain(rt2x00dev, libconf);
4436
e90c54b2 4437 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4438 rt2800_config_channel(rt2x00dev, libconf->conf,
4439 &libconf->rf, &libconf->channel);
675a0b04 4440 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4441 libconf->conf->power_level);
e90c54b2 4442 }
f4450616 4443 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4444 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4445 libconf->conf->power_level);
f4450616
BZ		 4446 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4447 rt2800_config_retry_limit(rt2x00dev, libconf);
4448 if (flags & IEEE80211_CONF_CHANGE_PS)
4449 rt2800_config_ps(rt2x00dev, libconf);
4450}
4451EXPORT_SYMBOL_GPL(rt2800_config);
4452
4453/*
4454 * Link tuning
4455 */
4456void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4457{
4458 u32 reg;
4459
4460 /*
4461 * Update FCS error count from register.
4462 */
4463 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4464 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4465}
4466EXPORT_SYMBOL_GPL(rt2800_link_stats);
4467
4468static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4469{
8c6728b0
GW		 4470 u8 vgc;
4471
57fbcce3 4472 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
d5385bfc 4473 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4474 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4475 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4476 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4477 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4478 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 4479 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 4480 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4481 rt2x00_rt(rt2x00dev, RT5392) ||
4482 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4483 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4484 else
4485 vgc = 0x2e + rt2x00dev->lna_gain;
4486 } else { /* 5GHZ band */
733aec6a 4487 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 4488 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4489 else if (rt2x00_rt(rt2x00dev, RT5592))
4490 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4491 else {
4492 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4493 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4494 else
4495 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4496 }
f4450616
BZ		 4497 }
4498
8c6728b0 4499 return vgc;
f4450616
BZ		 4500}
4501
4502static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4503 struct link_qual *qual, u8 vgc_level)
4504{
4505 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 4506 if (rt2x00_rt(rt2x00dev, RT3572) ||
4507 rt2x00_rt(rt2x00dev, RT3593)) {
4508 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4509 vgc_level);
4510 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 4511 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4512 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 4513 } else {
3d81535e 4514 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 4515 }
4516
f4450616
BZ		 4517 qual->vgc_level = vgc_level;
4518 qual->vgc_level_reg = vgc_level;
4519 }
4520}
4521
4522void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4523{
4524 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4525}
4526EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4527
4528void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4529 const u32 count)
4530{
3d81535e
SG		 4531 u8 vgc;
4532
8d0c9b65 4533 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4534 return;
e25aa82a
GJ		 4535
4536 /* When RSSI is better than a certain threshold, increase VGC
4537 * with a chip specific value in order to improve the balance
4538 * between sensibility and noise isolation.
f4450616 4539 */
3d81535e
SG		 4540
4541 vgc = rt2800_get_default_vgc(rt2x00dev);
4542
e25aa82a
GJ		 4543 switch (rt2x00dev->chip.rt) {
4544 case RT3572:
4545 case RT3593:
4546 if (qual->rssi > -65) {
57fbcce3 4547 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
e25aa82a
GJ		 4548 vgc += 0x20;
4549 else
4550 vgc += 0x10;
4551 }
4552 break;
4553
4554 case RT5592:
0beb1bbf
GJ		 4555 if (qual->rssi > -65)
4556 vgc += 0x20;
e25aa82a
GJ		 4557 break;
4558
4559 default:
0beb1bbf
GJ		 4560 if (qual->rssi > -80)
4561 vgc += 0x10;
e25aa82a 4562 break;
0beb1bbf 4563 }
3d81535e
SG		 4564
4565 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4566}
4567EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4568
4569/*
4570 * Initialization functions.
4571 */
b9a07ae9 4572static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541 4573{
8f03a7c6 4574 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541 4575 u32 reg;
d5385bfc 4576 u16 eeprom;
fcf51541 4577 unsigned int i;
e3a896b9 4578 int ret;
fcf51541 4579
f7b395e9 4580 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4581
e3a896b9
GW		 4582 ret = rt2800_drv_init_registers(rt2x00dev);
4583 if (ret)
4584 return ret;
fcf51541 4585
fcf51541
BZ		 4586 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4587 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4588
4589 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4590
4591 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4592 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4593 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4594 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4595 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4596 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4597 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4598 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4599
a9dce149
GW		 4600 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4601
4602 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4603 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4604 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4605 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4606
a89534ed
WH		 4607 if (rt2x00_rt(rt2x00dev, RT3290)) {
4608 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4609 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4610 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4611 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4612 }
4613
4614 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4615 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4616 rt2x00_set_field32(&reg, LDO0_EN, 1);
4617 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4618 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4619 }
4620
4621 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4622 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4623 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4624 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4625 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4626
4627 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4628 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4629 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4630
4631 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4632 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4633 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4634 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4635 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4636 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4637
4638 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4639 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4640 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4641 }
4642
64522957 4643 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4644 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4645 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4646 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4647
4648 if (rt2x00_rt(rt2x00dev, RT3290))
4649 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4650 0x00000404);
4651 else
4652 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4653 0x00000400);
4654
fcf51541 4655 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4656 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4657 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4658 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4659 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4660 &eeprom);
38c8a566 4661 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4662 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4663 0x0000002c);
4664 else
4665 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4666 0x0000000f);
4667 } else {
4668 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4669 }
d5385bfc 4670 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4671 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4672
4673 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4674 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4675 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4676 } else {
4677 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4678 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4679 }
c295a81d
HS		 4680 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4681 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4682 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4683 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4684 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4685 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4686 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4687 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4688 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4689 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4690 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4691 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4692 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4693 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4694 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4695 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4696 &eeprom);
4697 if (rt2x00_get_field16(eeprom,
4698 EEPROM_NIC_CONF1_DAC_TEST))
4699 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4700 0x0000001f);
4701 else
4702 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4703 0x0000000f);
4704 } else {
4705 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4706 0x00000000);
4707 }
2ed71884 4708 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
231aeca1 4709 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4710 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4711 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4712 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
231aeca1
SG		 4713 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
4714 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4715 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4716 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4717 } else {
4718 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4719 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4720 }
4721
4722 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4723 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4724 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4725 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4726 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4727 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4728 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4729 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4730 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4731 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4732
4733 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4734 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4735 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4736 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4737 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4738
4739 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4740 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4741 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4742 rt2x00_rt(rt2x00dev, RT2883) ||
8f03a7c6
SG		 4743 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
4744 drv_data->max_psdu = 2;
fcf51541 4745 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
8f03a7c6
SG		 4746 } else {
4747 drv_data->max_psdu = 1;
fcf51541 4748 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
8f03a7c6 4749 }
a51b8969
SG		 4750 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
4751 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
fcf51541
BZ		 4752 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4753
a9dce149
GW		 4754 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4755 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4756 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4757 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4758 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4759 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4760 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4761 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4762 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4763
fcf51541
BZ		 4764 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4765
a9dce149
GW		 4766 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4767 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4768 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4769 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4770 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4771 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4772 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4773 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4774
fcf51541
BZ		 4775 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4776 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4777 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
be82de9d 4778 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
fcf51541 4779 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
be82de9d 4780 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
fcf51541
BZ		 4781 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4782 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4783 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4784
4785 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4786 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4787 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4788 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4789 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4790 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4791 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4792 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4793 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4794 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4795 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4796 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4797
4798 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4799 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4800 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4801 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4802 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4803 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4804 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4805 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4806 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4807 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4808 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4809 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4810
4811 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4812 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 4813 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4814 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4815 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4816 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4817 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4818 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4819 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4820 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4821 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4822 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4823
4824 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4825 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 4826 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4827 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4828 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4829 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4830 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4831 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4832 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4833 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4834 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4835 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4836
4837 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4838 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 4839 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4840 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4841 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4842 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4843 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4844 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4845 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4846 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4847 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4848 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4849
4850 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4851 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 4852 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4853 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4854 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4855 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4856 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4857 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4858 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4859 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4860 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4861 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4862
cea90e55 4863 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4864 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4865
4866 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4867 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4868 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4869 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4870 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4871 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4872 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4873 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4874 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4875 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4876 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4877 }
4878
961621ab
HS		 4879 /*
4880 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4881 * although it is reserved.
4882 */
4883 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4884 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4885 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4886 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4887 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4888 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4889 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4890 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4891 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4892 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4893 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4894 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4895
7641328d
SG		 4896 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4897 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4898
4899 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4900 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4901 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4902 IEEE80211_MAX_RTS_THRESHOLD);
4903 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4904 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4905
4906 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4907
a21c2ab4
HS		 4908 /*
4909 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4910 * time should be set to 16. However, the original Ralink driver uses
4911 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4912 * connection problems with 11g + CTS protection. Hence, use the same
4913 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4914 */
a9dce149 4915 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4916 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4917 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4918 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4919 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4920 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4921 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4922
fcf51541
BZ		 4923 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4924
4925 /*
4926 * ASIC will keep garbage value after boot, clear encryption keys.
4927 */
4928 for (i = 0; i < 4; i++)
4929 rt2800_register_write(rt2x00dev,
4930 SHARED_KEY_MODE_ENTRY(i), 0);
4931
4932 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4933 rt2800_config_wcid(rt2x00dev, NULL, i);
4934 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4935 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4936 }
4937
4938 /*
4939 * Clear all beacons
fcf51541 4940 */
77f7c0f3
GJ		 4941 for (i = 0; i < 8; i++)
4942 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4943
cea90e55 4944 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4945 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4946 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4947 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4948 } else if (rt2x00_is_pcie(rt2x00dev)) {
4949 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4950 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4951 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4952 }
4953
4954 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4955 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4956 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4957 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4958 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4959 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4960 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4961 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4962 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4963 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4964
4965 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4966 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4967 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4968 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4969 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4970 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4971 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4972 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4973 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4974 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4975
4976 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4977 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4978 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4979 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4980 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4981 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4982 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4983 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4984 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4985 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4986
4987 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4988 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4989 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4990 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4991 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4992 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4993
47ee3eb1
HS		 4994 /*
4995 * Do not force the BA window size, we use the TXWI to set it
4996 */
4997 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4998 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4999 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5000 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5001
fcf51541
BZ		 5002 /*
5003 * We must clear the error counters.
5004 * These registers are cleared on read,
5005 * so we may pass a useless variable to store the value.
5006 */
5007 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5008 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
5009 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
5010 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
5011 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
5012 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
5013
9f926fb5
HS		 5014 /*
5015 * Setup leadtime for pre tbtt interrupt to 6ms
5016 */
5017 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
5018 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5019 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5020
977206d7
HS		 5021 /*
5022 * Set up channel statistics timer
5023 */
5024 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
5025 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5026 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5027 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5028 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5029 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5030 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5031
fcf51541
BZ		 5032 return 0;
5033}
fcf51541
BZ		 5034
5035static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5036{
5037 unsigned int i;
5038 u32 reg;
5039
5040 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5041 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5042 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5043 return 0;
5044
5045 udelay(REGISTER_BUSY_DELAY);
5046 }
5047
ec9c4989 5048 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5049 return -EACCES;
5050}
5051
5052static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5053{
5054 unsigned int i;
5055 u8 value;
5056
5057 /*
5058 * BBP was enabled after firmware was loaded,
5059 * but we need to reactivate it now.
5060 */
5061 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5062 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5063 msleep(1);
5064
5065 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5066 rt2800_bbp_read(rt2x00dev, 0, &value);
5067 if ((value != 0xff) && (value != 0x00))
5068 return 0;
5069 udelay(REGISTER_BUSY_DELAY);
5070 }
5071
ec9c4989 5072 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5073 return -EACCES;
5074}
5075
a7bbbe5c
SG		 5076static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5077{
5078 u8 value;
5079
5080 rt2800_bbp_read(rt2x00dev, 4, &value);
5081 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5082 rt2800_bbp_write(rt2x00dev, 4, value);
5083}
5084
c2675487
SG		 5085static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5086{
5087 rt2800_bbp_write(rt2x00dev, 142, 1);
5088 rt2800_bbp_write(rt2x00dev, 143, 57);
5089}
5090
a7bbbe5c
SG		 5091static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5092{
5093 const u8 glrt_table[] = {
5094 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5095 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5096 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5097 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5098 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5099 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5101 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5102 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5103 };
5104 int i;
5105
5106 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5107 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5108 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5109 }
5110};
5111
624708b8 5112static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5113{
5114 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5115 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5116 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5117 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5118 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5119 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5120 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5121 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5122 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5123 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5124 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5125 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5126 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5127 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5128 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5129 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5130}
5131
5df1ff3a
SG		 5132static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5133{
5134 u16 eeprom;
5135 u8 value;
5136
5137 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5138 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5139 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5140 value |= 0x20;
5141 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5142 value &= ~0x02;
5143 rt2800_bbp_write(rt2x00dev, 138, value);
5144}
5145
dae62957
SG		 5146static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5147{
b2f8e0bd 5148 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5149
5150 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5151 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5152
5153 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5154 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5155
5156 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5157
5158 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5159 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5160
5161 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5162
5163 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5164
5165 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5166
5167 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5168
5169 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5170
5171 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5172
5173 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5174
5175 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5176
5177 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5178}
5179
39ab3e8b
SG		 5180static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5181{
e379de12
SG		 5182 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5183 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5184
5185 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5186 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5187 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5188 } else {
5189 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5190 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5191 }
8d97be38
SG		 5192
5193 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5194
5195 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5196
5197 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5198
5199 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5200
5201 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5202 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5203 else
5204 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5205
5206 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5207
5208 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5209
5210 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5211
5212 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5213
5214 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5215
5216 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5217}
5218
5219static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5220{
e379de12
SG		 5221 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5222 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5223
5224 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5225 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5226
5227 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5228
5229 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5230 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5231 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5232
5233 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5234
5235 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5236
5237 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5238
5239 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5240
5241 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5242
5243 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5244
5245 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5246 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5247 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5248 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5249 else
5250 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5251
5252 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5253
5254 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5255
5256 if (rt2x00_rt(rt2x00dev, RT3071) ||
5257 rt2x00_rt(rt2x00dev, RT3090))
5258 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5259}
5260
5261static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5262{
6addb24e
SG		 5263 u8 value;
5264
c3223573 5265 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5266
5267 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5268
5269 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5270 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5271
5272 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5273
5274 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5275 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5276 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5277 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5278
5279 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5280
5281 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5282
5283 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5284 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5285 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5286 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5287
5288 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5289
5290 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5291
5292 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5293
5294 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5295
5296 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5297
5298 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5299
5300 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5301
5302 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5303
5304 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5305
5306 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5307
5308 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5309
5310 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5311 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5312 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5313 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5314 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5315 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5316 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5317 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5318 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5319 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5320
5321 rt2800_bbp_read(rt2x00dev, 47, &value);
5322 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5323 rt2800_bbp_write(rt2x00dev, 47, value);
5324
5325 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5326 rt2800_bbp_read(rt2x00dev, 3, &value);
5327 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5328 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5329 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5330}
5331
5332static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5333{
29f3a58b
SG		 5334 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5335 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5336
5337 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5338
5339 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5340
5341 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5342 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5343
5344 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5345
5346 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5347 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5348 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5349 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5350
5351 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5352
5353 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5354
5355 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5356 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5357 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5358
5359 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5360
5361 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5362
5363 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5364
5365 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5366
5367 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5368
5369 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5370
5371 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5372
5373 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5374
5375 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5376
5377 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5378
5379 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5380
5381 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5382
5383 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5384
5385 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5386 /* Set ITxBF timeout to 0x9c40=1000msec */
5387 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5388 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5389 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5390 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5391 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5392 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5393 /* Reprogram the inband interface to put right values in RXWI */
5394 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5395 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5396 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5397 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5398 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5399 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5400 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5401 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5402
5403 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5404}
5405
5406static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5407{
e379de12
SG		 5408 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5409 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5410
5411 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5412 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5413
5414 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5415
5416 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5417 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5418 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5419
5420 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5421
5422 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5423
5424 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5425
5426 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5427
5428 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5429
5430 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5431
5432 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5433 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5434 else
5435 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5436
5437 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5438
5439 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5440
5441 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5442}
5443
5444static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5445{
b2f8e0bd 5446 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5447
5448 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5449 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5450
5451 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5452 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5453
5454 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5455
5456 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5457 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5458 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5459
5460 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5461
5462 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5463
5464 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5465
5466 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5467
5468 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5469
5470 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5471
5472 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5473
5474 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5475
5476 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5477
5478 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5479}
5480
b189a181
GJ		 5481static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5482{
5483 rt2800_init_bbp_early(rt2x00dev);
5484
5485 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5486 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5487 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5488 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5489
5490 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5491
5492 /* Enable DC filter */
5493 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5494 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5495}
5496
39ab3e8b
SG		 5497static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5498{
32ef8f49
SG		 5499 int ant, div_mode;
5500 u16 eeprom;
5501 u8 value;
5502
c3223573 5503 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5504
5505 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5506
5507 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5508 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5509
5510 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 5511
58422191 5512 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 5513 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5514 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5515 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5516
5517 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 5518
58422191
SG		 5519 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5520
43f535e2
SG		 5521 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5522 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5523 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5524
5525 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5526
5527 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5528
5529 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5530
5531 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5532
5533 if (rt2x00_rt(rt2x00dev, RT5392))
5534 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5535
5536 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5537
5538 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5539
5540 if (rt2x00_rt(rt2x00dev, RT5392)) {
5541 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5542 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5543 }
672d1188
SG		 5544
5545 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5546
5547 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5548
5549 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5550
5551 if (rt2x00_rt(rt2x00dev, RT5390))
5552 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5553 else if (rt2x00_rt(rt2x00dev, RT5392))
5554 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5555 else
5556 WARN_ON(1);
f2b6777c
SG		 5557
5558 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5559
5560 if (rt2x00_rt(rt2x00dev, RT5392)) {
5561 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5562 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5563 }
5df1ff3a
SG		 5564
5565 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5566
3e38d3da 5567 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5568 div_mode = rt2x00_get_field16(eeprom,
5569 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5570 ant = (div_mode == 3) ? 1 : 0;
5571
5572 /* check if this is a Bluetooth combo card */
c429dfef 5573 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 5574 u32 reg;
5575
5576 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5577 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5578 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5579 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5580 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5581 if (ant == 0)
5582 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5583 else if (ant == 1)
5584 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5585 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5586 }
5587
5588 /* This chip has hardware antenna diversity*/
5589 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5590 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5591 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5592 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5593 }
5594
5595 rt2800_bbp_read(rt2x00dev, 152, &value);
5596 if (ant == 0)
5597 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5598 else
5599 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5600 rt2800_bbp_write(rt2x00dev, 152, value);
5601
5602 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5603}
5604
a7bbbe5c
SG		 5605static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5606{
5607 int ant, div_mode;
5608 u16 eeprom;
5609 u8 value;
5610
624708b8 5611 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5612
a7bbbe5c
SG		 5613 rt2800_bbp_read(rt2x00dev, 105, &value);
5614 rt2x00_set_field8(&value, BBP105_MLD,
5615 rt2x00dev->default_ant.rx_chain_num == 2);
5616 rt2800_bbp_write(rt2x00dev, 105, value);
5617
5618 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5619
5620 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5621 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5622 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5623 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5624 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5625 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5626 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5627 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5628 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5629 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5630 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5631 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5632 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5633 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5634 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5635 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5636 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5637 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5638 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5639 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5640 /* FIXME BBP105 owerwrite */
5641 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5642 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5643 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5644 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5645 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5646 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5647
5648 /* Initialize GLRT (Generalized Likehood Radio Test) */
5649 rt2800_init_bbp_5592_glrt(rt2x00dev);
5650
5651 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5652
3e38d3da 5653 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5654 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5655 ant = (div_mode == 3) ? 1 : 0;
5656 rt2800_bbp_read(rt2x00dev, 152, &value);
5657 if (ant == 0) {
5658 /* Main antenna */
5659 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5660 } else {
5661 /* Auxiliary antenna */
5662 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5663 }
5664 rt2800_bbp_write(rt2x00dev, 152, value);
5665
5666 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5667 rt2800_bbp_read(rt2x00dev, 254, &value);
5668 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5669 rt2800_bbp_write(rt2x00dev, 254, value);
5670 }
5671
c2675487
SG		 5672 rt2800_init_freq_calibration(rt2x00dev);
5673
a7bbbe5c 5674 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5675 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5676 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5677}
5678
a1ef5039 5679static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5680{
5681 unsigned int i;
5682 u16 eeprom;
5683 u8 reg_id;
5684 u8 value;
5685
dae62957
SG		 5686 if (rt2800_is_305x_soc(rt2x00dev))
5687 rt2800_init_bbp_305x_soc(rt2x00dev);
5688
39ab3e8b
SG		 5689 switch (rt2x00dev->chip.rt) {
5690 case RT2860:
5691 case RT2872:
5692 case RT2883:
5693 rt2800_init_bbp_28xx(rt2x00dev);
5694 break;
5695 case RT3070:
5696 case RT3071:
5697 case RT3090:
5698 rt2800_init_bbp_30xx(rt2x00dev);
5699 break;
5700 case RT3290:
5701 rt2800_init_bbp_3290(rt2x00dev);
5702 break;
5703 case RT3352:
5704 rt2800_init_bbp_3352(rt2x00dev);
5705 break;
5706 case RT3390:
5707 rt2800_init_bbp_3390(rt2x00dev);
5708 break;
5709 case RT3572:
5710 rt2800_init_bbp_3572(rt2x00dev);
5711 break;
b189a181
GJ		 5712 case RT3593:
5713 rt2800_init_bbp_3593(rt2x00dev);
5714 return;
39ab3e8b
SG		 5715 case RT5390:
5716 case RT5392:
5717 rt2800_init_bbp_53xx(rt2x00dev);
5718 break;
5719 case RT5592:
a7bbbe5c 5720 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5721 return;
a7bbbe5c
SG		 5722 }
5723
fcf51541 5724 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5725 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5726 &eeprom);
fcf51541
BZ		 5727
5728 if (eeprom != 0xffff && eeprom != 0x0000) {
5729 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5730 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5731 rt2800_bbp_write(rt2x00dev, reg_id, value);
5732 }
5733 }
fcf51541 5734}
fcf51541 5735
d9517f2f
SG		 5736static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5737{
5738 u32 reg;
5739
5740 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5741 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5742 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5743}
5744
c5b3c350
SG		 5745static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5746 u8 filter_target)
fcf51541
BZ		 5747{
5748 unsigned int i;
5749 u8 bbp;
5750 u8 rfcsr;
5751 u8 passband;
5752 u8 stopband;
5753 u8 overtuned = 0;
c5b3c350 5754 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5755
5756 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5757
5758 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5759 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5760 rt2800_bbp_write(rt2x00dev, 4, bbp);
5761
80d184e6
RJH		 5762 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5763 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5764 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5765
fcf51541
BZ		 5766 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5767 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5768 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5769
5770 /*
5771 * Set power & frequency of passband test tone
5772 */
5773 rt2800_bbp_write(rt2x00dev, 24, 0);
5774
5775 for (i = 0; i < 100; i++) {
5776 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5777 msleep(1);
5778
5779 rt2800_bbp_read(rt2x00dev, 55, &passband);
5780 if (passband)
5781 break;
5782 }
5783
5784 /*
5785 * Set power & frequency of stopband test tone
5786 */
5787 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5788
5789 for (i = 0; i < 100; i++) {
5790 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5791 msleep(1);
5792
5793 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5794
5795 if ((passband - stopband) <= filter_target) {
5796 rfcsr24++;
5797 overtuned += ((passband - stopband) == filter_target);
5798 } else
5799 break;
5800
5801 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5802 }
5803
5804 rfcsr24 -= !!overtuned;
5805
5806 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5807 return rfcsr24;
5808}
5809
ce94ede9
SG		 5810static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5811 const unsigned int rf_reg)
5812{
5813 u8 rfcsr;
5814
5815 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5816 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5817 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5818 msleep(1);
5819 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5820 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5821}
5822
c5b3c350
SG		 5823static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5824{
5825 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5826 u8 filter_tgt_bw20;
5827 u8 filter_tgt_bw40;
5828 u8 rfcsr, bbp;
5829
5830 /*
5831 * TODO: sync filter_tgt values with vendor driver
5832 */
5833 if (rt2x00_rt(rt2x00dev, RT3070)) {
5834 filter_tgt_bw20 = 0x16;
5835 filter_tgt_bw40 = 0x19;
5836 } else {
5837 filter_tgt_bw20 = 0x13;
5838 filter_tgt_bw40 = 0x15;
5839 }
5840
5841 drv_data->calibration_bw20 =
5842 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5843 drv_data->calibration_bw40 =
5844 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5845
5846 /*
5847 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5848 */
5849 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5850 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5851
5852 /*
5853 * Set back to initial state
5854 */
5855 rt2800_bbp_write(rt2x00dev, 24, 0);
5856
5857 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5858 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5859 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5860
5861 /*
5862 * Set BBP back to BW20
5863 */
5864 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5865 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5866 rt2800_bbp_write(rt2x00dev, 4, bbp);
5867}
5868
da8064c2
SG		 5869static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5870{
5871 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5872 u8 min_gain, rfcsr, bbp;
5873 u16 eeprom;
5874
5875 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5876
5877 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5878 if (rt2x00_rt(rt2x00dev, RT3070) ||
5879 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5880 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5881 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 5882 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 5883 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5884 }
5885
5886 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5887 if (drv_data->txmixer_gain_24g >= min_gain) {
5888 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5889 drv_data->txmixer_gain_24g);
5890 }
5891
5892 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5893
5894 if (rt2x00_rt(rt2x00dev, RT3090)) {
5895 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5896 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5897 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5898 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5899 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5900 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5901 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5902 rt2800_bbp_write(rt2x00dev, 138, bbp);
5903 }
5904
5905 if (rt2x00_rt(rt2x00dev, RT3070)) {
5906 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5907 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5908 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5909 else
5910 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5911 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5912 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5913 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5914 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5915 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5916 rt2x00_rt(rt2x00dev, RT3090) ||
5917 rt2x00_rt(rt2x00dev, RT3390)) {
5918 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5919 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5920 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5921 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5922 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5923 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5924 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5925
5926 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5927 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5928 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5929
5930 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5931 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5932 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5933
5934 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5935 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5936 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5937 }
5938}
5939
ab7078ac
GJ		 5940static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5941{
5942 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5943 u8 rfcsr;
5944 u8 tx_gain;
5945
5946 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5947 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5948 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5949
5950 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5951 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5952 RFCSR17_TXMIXER_GAIN);
5953 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5954 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5955
5956 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5957 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5958 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5959
5960 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5961 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5962 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5963
5964 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5965 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5966 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5967 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5968
5969 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5970 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5971 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5972
5973 /* TODO: enable stream mode */
5974}
5975
f7df8fe5
SG		 5976static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5977{
5978 u8 reg;
5979 u16 eeprom;
5980
5981 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5982 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5983 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5984 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5985 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5986 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5987 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5988 rt2800_bbp_write(rt2x00dev, 138, reg);
5989
5990 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5991 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5992 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5993
5994 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5995 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5996 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5997
5998 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5999
6000 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
6001 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
6002 rt2800_rfcsr_write(rt2x00dev, 30, reg);
6003}
6004
d5374ef1
SG		 6005static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
6006{
ce94ede9
SG		 6007 rt2800_rf_init_calibration(rt2x00dev, 30);
6008
d5374ef1
SG		 6009 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
6010 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
6011 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
6012 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
6013 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6014 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6015 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6016 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
6017 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6018 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6019 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6020 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6021 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6022 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6023 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6024 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6025 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6026 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6027 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6028 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6029 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6030 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6031 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6032 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6033 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6034 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6035 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6036 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6037 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6038 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6039 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6040 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6041}
6042
6043static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6044{
c9a221b2
SG		 6045 u8 rfcsr;
6046 u16 eeprom;
6047 u32 reg;
6048
ce94ede9
SG		 6049 /* XXX vendor driver do this only for 3070 */
6050 rt2800_rf_init_calibration(rt2x00dev, 30);
6051
d5374ef1
SG		 6052 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6053 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6054 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6055 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6056 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6057 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6058 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6059 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6060 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6061 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6062 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6063 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6064 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6065 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6066 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6067 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6068 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6069 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6070 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6071
6072 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6073 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6074 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6075 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6076 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6077 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6078 rt2x00_rt(rt2x00dev, RT3090)) {
6079 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6080
6081 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6082 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6083 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6084
6085 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6086 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6087 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6088 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6089 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6090 &eeprom);
c9a221b2
SG		 6091 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6092 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6093 else
6094 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6095 }
6096 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6097
6098 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6099 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6100 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6101 }
c5b3c350
SG		 6102
6103 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6104
6105 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6106 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6107 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6108 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6109
6110 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6111 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6112}
6113
6114static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6115{
f9cdcbb1
SG		 6116 u8 rfcsr;
6117
ce94ede9
SG		 6118 rt2800_rf_init_calibration(rt2x00dev, 2);
6119
d5374ef1
SG		 6120 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6121 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6122 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6123 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6124 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6125 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6126 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6127 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6128 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6129 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6130 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6131 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6132 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6133 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6134 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6135 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6136 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6137 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6138 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6139 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6140 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6141 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6142 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6143 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6144 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6145 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6146 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6147 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6148 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6149 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6150 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6151 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6152 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6153 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6154 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6155 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6156 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6157 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6158 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6159 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6160 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6161 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6162 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6163 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6164 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6165 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6166
6167 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6168 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6169 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6170
6171 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6172 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6173}
6174
6175static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6176{
ce94ede9
SG		 6177 rt2800_rf_init_calibration(rt2x00dev, 30);
6178
d5374ef1
SG		 6179 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6180 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6181 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6182 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6183 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6184 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6185 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6186 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6187 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6188 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6189 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6190 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6191 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6192 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6193 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6194 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6195 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6196 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6197 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6198 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6199 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6200 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6201 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6202 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6203 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6204 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6205 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6206 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6207 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6208 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6209 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6210 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6211 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6212 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6213 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6214 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6215 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6216 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6217 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6218 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6219 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6220 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6221 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6222 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6223 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6224 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6225 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6226 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6227 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6228 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6229 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6230 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6231 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6232 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6233 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6234 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6235 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6236 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6237 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6238 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6239 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6240 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6241 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6242
6243 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6244 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6245 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6246}
6247
6248static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6249{
2971e66f
SG		 6250 u32 reg;
6251
ce94ede9
SG		 6252 rt2800_rf_init_calibration(rt2x00dev, 30);
6253
d5374ef1
SG		 6254 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6255 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6256 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6257 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6258 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6259 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6260 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6261 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6262 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6263 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6264 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6265 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6266 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6267 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6268 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6269 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6270 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6271 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6272 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6273 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6274 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6275 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6276 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6277 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6278 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6279 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6280 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6281 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6282 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6283 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6284 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6285 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6286
6287 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6288 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6289 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6290
6291 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6292
6293 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6294 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6295
6296 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6297 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6298}
6299
6300static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6301{
87d91db9
SG		 6302 u8 rfcsr;
6303 u32 reg;
6304
ce94ede9
SG		 6305 rt2800_rf_init_calibration(rt2x00dev, 30);
6306
d5374ef1
SG		 6307 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6308 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6309 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6310 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6311 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6312 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6313 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6314 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6315 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6316 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6317 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6318 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6319 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6320 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6321 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6322 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6323 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6324 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6325 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6326 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6327 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6328 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6329 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6330 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6331 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6332 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6333 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6334 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6335 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6336 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6337 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6338
6339 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6340 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6341 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6342
6343 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6344 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6345 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6346 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6347 msleep(1);
6348 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6349 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6350 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6351 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6352
6353 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6354 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6355 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6356}
6357
d63f7e8c
GJ		 6358static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6359{
6360 u8 bbp;
6361 bool txbf_enabled = false; /* FIXME */
6362
6363 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6364 if (rt2x00dev->default_ant.rx_chain_num == 1)
6365 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6366 else
6367 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6368 rt2800_bbp_write(rt2x00dev, 105, bbp);
6369
6370 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6371
6372 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6373 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6374 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6375 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6376 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6377 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6378 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6379 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6380
6381 if (txbf_enabled)
6382 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6383 else
6384 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6385
6386 /* SNR mapping */
6387 rt2800_bbp_write(rt2x00dev, 142, 6);
6388 rt2800_bbp_write(rt2x00dev, 143, 160);
6389 rt2800_bbp_write(rt2x00dev, 142, 7);
6390 rt2800_bbp_write(rt2x00dev, 143, 161);
6391 rt2800_bbp_write(rt2x00dev, 142, 8);
6392 rt2800_bbp_write(rt2x00dev, 143, 162);
6393
6394 /* ADC/DAC control */
6395 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6396
6397 /* RX AGC energy lower bound in log2 */
6398 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6399
6400 /* FIXME: BBP 105 owerwrite? */
6401 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6402
d63f7e8c
GJ		 6403}
6404
ab7078ac
GJ		 6405static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6406{
6407 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6408 u32 reg;
6409 u8 rfcsr;
6410
6411 /* Disable GPIO #4 and #7 function for LAN PE control */
6412 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6413 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6414 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6415 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6416
6417 /* Initialize default register values */
6418 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6419 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6420 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6421 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6422 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6423 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6424 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6425 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6426 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6427 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6428 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6429 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6430 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6431 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6432 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6433 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6434 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6435 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6436 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6437 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6438 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6439 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6440 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6441 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6442 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6443 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6444 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6445 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6446 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6447 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6448 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6449 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6450
6451 /* Initiate calibration */
6452 /* TODO: use rt2800_rf_init_calibration ? */
6453 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6454 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6455 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6456
88452541 6457 rt2800_freq_cal_mode1(rt2x00dev);
ab7078ac
GJ		 6458
6459 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6460 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6461 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6462
6463 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6464 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6465 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6466 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6467 usleep_range(1000, 1500);
6468 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6469 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6470 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6471
6472 /* Set initial values for RX filter calibration */
6473 drv_data->calibration_bw20 = 0x1f;
6474 drv_data->calibration_bw40 = 0x2f;
6475
6476 /* Save BBP 25 & 26 values for later use in channel switching */
6477 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6478 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6479
6480 rt2800_led_open_drain_enable(rt2x00dev);
6481 rt2800_normal_mode_setup_3593(rt2x00dev);
6482
d63f7e8c 6483 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6484
6485 /* TODO: enable stream mode support */
6486}
6487
d5374ef1
SG		 6488static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6489{
ce94ede9
SG		 6490 rt2800_rf_init_calibration(rt2x00dev, 2);
6491
d5374ef1
SG		 6492 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6493 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6494 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6495 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6496 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6497 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6498 else
6499 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6500 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6501 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6502 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 6503 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 6504 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6505 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6506 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6507 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6508 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6509 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6510
6511 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6512 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6513 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6514 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6515 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 6516 if (rt2x00_is_usb(rt2x00dev) &&
6517 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 6518 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6519 else
6520 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6521 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6522 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6523 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6524 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6525
7122e660 6526 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 6527 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6528 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6529 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6530 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6531 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6532 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6533 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6534 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6535 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6536
c8520bcb 6537 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 6538 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6539 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6540 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6541 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6542 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6543 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6544 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6545 else
6546 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6547 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6548 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6549 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6550
6551 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6552 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6553 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6554 else
6555 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6556 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6557 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 6558 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6559 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6560 else
6561 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 6562 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6563 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 6564 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 6565
6566 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 6567 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6568 if (rt2x00_is_usb(rt2x00dev))
6569 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6570 else
6571 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6572 } else {
6573 if (rt2x00_is_usb(rt2x00dev))
6574 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6575 else
6576 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6577 }
d5374ef1
SG		 6578 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6579 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6580
6581 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6582
6583 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6584}
6585
6586static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6587{
ce94ede9
SG		 6588 rt2800_rf_init_calibration(rt2x00dev, 2);
6589
d5374ef1 6590 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 6591 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6592 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6593 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6594 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6595 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6596 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6597 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6598 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6599 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6600 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6601 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6602 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6603 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6604 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6605 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6606 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6607 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6608 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6609 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6610 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6611 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6612 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6613 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6614 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6615 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6616 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6617 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6618 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6619 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6620 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6621 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6622 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6623 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6624 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6625 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6626 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6627 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6628 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6629 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6630 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6631 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6632 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6633 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6634 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6635 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6636 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6637 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6638 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6639 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6640 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6641 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6642 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6643 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6644 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6645 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6646 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6647 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6648
6649 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6650
6651 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6652}
6653
0c9e5fb9
SG		 6654static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6655{
ce94ede9
SG		 6656 rt2800_rf_init_calibration(rt2x00dev, 30);
6657
0c9e5fb9
SG		 6658 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6659 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 6660 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6661 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6662 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6663 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6664 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6665 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6666 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6667 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6668 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6669 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6670 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6671 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6672 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6673 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6674 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6675 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6676 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6677 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6678 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6679
6680 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6681 msleep(1);
6682
88452541 6683 rt2800_freq_cal_mode1(rt2x00dev);
c630ccf1 6684
c630ccf1
SG		 6685 /* Enable DC filter */
6686 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6687 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6688
f7df8fe5 6689 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6690
6691 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6692 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6693
6694 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6695}
6696
074f2529 6697static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6698{
d5374ef1
SG		 6699 if (rt2800_is_305x_soc(rt2x00dev)) {
6700 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6701 return;
d5374ef1
SG		 6702 }
6703
6704 switch (rt2x00dev->chip.rt) {
6705 case RT3070:
6706 case RT3071:
6707 case RT3090:
6708 rt2800_init_rfcsr_30xx(rt2x00dev);
6709 break;
6710 case RT3290:
6711 rt2800_init_rfcsr_3290(rt2x00dev);
6712 break;
6713 case RT3352:
6714 rt2800_init_rfcsr_3352(rt2x00dev);
6715 break;
6716 case RT3390:
6717 rt2800_init_rfcsr_3390(rt2x00dev);
6718 break;
6719 case RT3572:
6720 rt2800_init_rfcsr_3572(rt2x00dev);
6721 break;
ab7078ac
GJ		 6722 case RT3593:
6723 rt2800_init_rfcsr_3593(rt2x00dev);
6724 break;
d5374ef1
SG		 6725 case RT5390:
6726 rt2800_init_rfcsr_5390(rt2x00dev);
6727 break;
6728 case RT5392:
6729 rt2800_init_rfcsr_5392(rt2x00dev);
6730 break;
0c9e5fb9
SG		 6731 case RT5592:
6732 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6733 break;
8cdd15e0 6734 }
fcf51541 6735}
b9a07ae9
ID		 6736
6737int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6738{
6739 u32 reg;
6740 u16 word;
6741
6742 /*
61edc7fa 6743 * Initialize MAC registers.
b9a07ae9
ID		 6744 */
6745 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6746 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6747 return -EIO;
6748
61edc7fa
SG		 6749 /*
6750 * Wait BBP/RF to wake up.
6751 */
f4e1a4d3
SG		 6752 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6753 return -EIO;
6754
b9a07ae9 6755 /*
61edc7fa 6756 * Send signal during boot time to initialize firmware.
b9a07ae9 6757 */
c630ccf1
SG		 6758 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6759 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 6760 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 6761 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 6762 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 6763 msleep(1);
6764
61edc7fa
SG		 6765 /*
6766 * Make sure BBP is up and running.
6767 */
f4e1a4d3 6768 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6769 return -EIO;
b9a07ae9 6770
61edc7fa
SG		 6771 /*
6772 * Initialize BBP/RF registers.
6773 */
a1ef5039 6774 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6775 rt2800_init_rfcsr(rt2x00dev);
6776
b9a07ae9
ID		 6777 if (rt2x00_is_usb(rt2x00dev) &&
6778 (rt2x00_rt(rt2x00dev, RT3070) ||
6779 rt2x00_rt(rt2x00dev, RT3071) ||
6780 rt2x00_rt(rt2x00dev, RT3572))) {
6781 udelay(200);
6782 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6783 udelay(10);
6784 }
6785
6786 /*
6787 * Enable RX.
6788 */
6789 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6790 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6791 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6792 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6793
6794 udelay(50);
6795
6796 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6797 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6798 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
b9a07ae9
ID		 6799 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6800 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6801
6802 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6803 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6804 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6805 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6806
6807 /*
6808 * Initialize LED control
6809 */
3e38d3da 6810 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6811 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6812 word & 0xff, (word >> 8) & 0xff);
6813
3e38d3da 6814 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6815 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6816 word & 0xff, (word >> 8) & 0xff);
6817
3e38d3da 6818 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6819 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6820 word & 0xff, (word >> 8) & 0xff);
6821
6822 return 0;
6823}
6824EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6825
6826void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6827{
6828 u32 reg;
6829
f7b395e9 6830 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6831
6832 /* Wait for DMA, ignore error */
6833 rt2800_wait_wpdma_ready(rt2x00dev);
6834
6835 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6836 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6837 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6838 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6839}
6840EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6841
30e84034
BZ		 6842int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6843{
6844 u32 reg;
a89534ed 6845 u16 efuse_ctrl_reg;
30e84034 6846
a89534ed
WH		 6847 if (rt2x00_rt(rt2x00dev, RT3290))
6848 efuse_ctrl_reg = EFUSE_CTRL_3290;
6849 else
6850 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6851
a89534ed 6852 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6853 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6854}
6855EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6856
6857static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6858{
6859 u32 reg;
a89534ed
WH		 6860 u16 efuse_ctrl_reg;
6861 u16 efuse_data0_reg;
6862 u16 efuse_data1_reg;
6863 u16 efuse_data2_reg;
6864 u16 efuse_data3_reg;
6865
6866 if (rt2x00_rt(rt2x00dev, RT3290)) {
6867 efuse_ctrl_reg = EFUSE_CTRL_3290;
6868 efuse_data0_reg = EFUSE_DATA0_3290;
6869 efuse_data1_reg = EFUSE_DATA1_3290;
6870 efuse_data2_reg = EFUSE_DATA2_3290;
6871 efuse_data3_reg = EFUSE_DATA3_3290;
6872 } else {
6873 efuse_ctrl_reg = EFUSE_CTRL;
6874 efuse_data0_reg = EFUSE_DATA0;
6875 efuse_data1_reg = EFUSE_DATA1;
6876 efuse_data2_reg = EFUSE_DATA2;
6877 efuse_data3_reg = EFUSE_DATA3;
6878 }
31a4cf1f
GW		 6879 mutex_lock(&rt2x00dev->csr_mutex);
6880
a89534ed 6881 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6882 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6883 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6884 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6885 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6886
6887 /* Wait until the EEPROM has been loaded */
a89534ed 6888 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6889 /* Apparently the data is read from end to start */
a89534ed 6890 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6891 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6892 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6893 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6894 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6895 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6896 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6897 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6898 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6899
6900 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6901}
6902
a02308e9 6903int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6904{
6905 unsigned int i;
6906
6907 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6908 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6909
6910 return 0;
30e84034
BZ		 6911}
6912EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6913
a3f1625d
GJ		 6914static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6915{
6916 u16 word;
6917
6316c786
GJ		 6918 if (rt2x00_rt(rt2x00dev, RT3593))
6919 return 0;
6920
a3f1625d
GJ		 6921 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6922 if ((word & 0x00ff) != 0x00ff)
6923 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6924
6925 return 0;
6926}
6927
6928static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6929{
6930 u16 word;
6931
6316c786
GJ		 6932 if (rt2x00_rt(rt2x00dev, RT3593))
6933 return 0;
6934
a3f1625d
GJ		 6935 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6936 if ((word & 0x00ff) != 0x00ff)
6937 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6938
6939 return 0;
6940}
6941
ad417a53 6942static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6943{
77c06c2c 6944 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6945 u16 word;
6946 u8 *mac;
6947 u8 default_lna_gain;
a02308e9 6948 int retval;
38bd7b8a 6949
ad417a53
GW		 6950 /*
6951 * Read the EEPROM.
6952 */
a02308e9
GJ		 6953 retval = rt2800_read_eeprom(rt2x00dev);
6954 if (retval)
6955 return retval;
ad417a53 6956
38bd7b8a
BZ		 6957 /*
6958 * Start validation of the data that has been read.
6959 */
3e38d3da 6960 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9766cb70 6961 rt2x00lib_set_mac_address(rt2x00dev, mac);
38bd7b8a 6962
3e38d3da 6963 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6964 if (word == 0xffff) {
38c8a566
RJH		 6965 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6966 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6967 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6968 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6969 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6970 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6971 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6972 /*
6973 * There is a max of 2 RX streams for RT28x0 series
6974 */
38c8a566
RJH		 6975 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6976 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6977 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6978 }
6979
3e38d3da 6980 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6981 if (word == 0xffff) {
38c8a566
RJH		 6982 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6983 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6984 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6985 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6986 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6987 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6988 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6989 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6990 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6991 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6992 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6993 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6994 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6995 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6996 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6997 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6998 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6999 }
7000
3e38d3da 7001 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 7002 if ((word & 0x00ff) == 0x00ff) {
7003 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 7004 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 7005 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 7006 }
7007 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 7008 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
7009 LED_MODE_TXRX_ACTIVITY);
7010 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 7011 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
7012 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
7013 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
7014 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 7015 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 7016 }
7017
7018 /*
7019 * During the LNA validation we are going to use
7020 * lna0 as correct value. Note that EEPROM_LNA
7021 * is never validated.
7022 */
3e38d3da 7023 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 7024 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
7025
3e38d3da 7026 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 7027 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
7028 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
7029 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
7030 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 7031 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 7032
a3f1625d 7033 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 7034
3e38d3da 7035 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 7036 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
7037 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 7038 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7039 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7040 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7041 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7042 default_lna_gain);
7043 }
3e38d3da 7044 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 7045
a3f1625d 7046 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 7047
3e38d3da 7048 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 7049 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7050 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7051 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7052 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 7053 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 7054
3e38d3da 7055 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 7056 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7057 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 7058 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7059 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7060 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7061 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7062 default_lna_gain);
7063 }
3e38d3da 7064 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 7065
f36bb0ca
GJ		 7066 if (rt2x00_rt(rt2x00dev, RT3593)) {
7067 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7068 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7069 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7070 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7071 default_lna_gain);
7072 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7073 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7074 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7075 default_lna_gain);
7076 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7077 }
7078
38bd7b8a
BZ		 7079 return 0;
7080}
38bd7b8a 7081
ad417a53 7082static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 7083{
38bd7b8a
BZ		 7084 u16 value;
7085 u16 eeprom;
86868b26 7086 u16 rf;
38bd7b8a 7087
86868b26
GJ		 7088 /*
7089 * Read EEPROM word for configuration.
7090 */
3e38d3da 7091 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 7092
7093 /*
7094 * Identify RF chipset by EEPROM value
7095 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7096 * RT53xx: defined in "EEPROM_CHIP_ID" field
7097 */
7098 if (rt2x00_rt(rt2x00dev, RT3290) ||
7099 rt2x00_rt(rt2x00dev, RT5390) ||
7100 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7101 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7102 else
7103 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7104
7105 switch (rf) {
d331eb51
LF		 7106 case RF2820:
7107 case RF2850:
7108 case RF2720:
7109 case RF2750:
7110 case RF3020:
7111 case RF2020:
7112 case RF3021:
7113 case RF3022:
7114 case RF3052:
0f5af26a 7115 case RF3053:
3b9b74ba 7116 case RF3070:
a89534ed 7117 case RF3290:
d331eb51 7118 case RF3320:
03839951 7119 case RF3322:
ccf91bd6 7120 case RF5360:
ac0372ab 7121 case RF5362:
d331eb51 7122 case RF5370:
2ed71884 7123 case RF5372:
d331eb51 7124 case RF5390:
cff3d1f0 7125 case RF5392:
b8863f8b 7126 case RF5592:
d331eb51
LF		 7127 break;
7128 default:
ec9c4989
JP		 7129 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7130 rf);
38bd7b8a
BZ		 7131 return -ENODEV;
7132 }
7133
86868b26
GJ		 7134 rt2x00_set_rf(rt2x00dev, rf);
7135
38bd7b8a
BZ		 7136 /*
7137 * Identify default antenna configuration.
7138 */
d96aa640 7139 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7140 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7141 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7142 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7143
3e38d3da 7144 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7145
7146 if (rt2x00_rt(rt2x00dev, RT3070) ||
7147 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7148 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7149 rt2x00_rt(rt2x00dev, RT3390)) {
7150 value = rt2x00_get_field16(eeprom,
7151 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7152 switch (value) {
7153 case 0:
7154 case 1:
7155 case 2:
7156 rt2x00dev->default_ant.tx = ANTENNA_A;
7157 rt2x00dev->default_ant.rx = ANTENNA_A;
7158 break;
7159 case 3:
7160 rt2x00dev->default_ant.tx = ANTENNA_A;
7161 rt2x00dev->default_ant.rx = ANTENNA_B;
7162 break;
7163 }
7164 } else {
7165 rt2x00dev->default_ant.tx = ANTENNA_A;
7166 rt2x00dev->default_ant.rx = ANTENNA_A;
7167 }
7168
0586a11b
AA		 7169 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7170 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7171 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7172 }
7173
38bd7b8a 7174 /*
9328fdac 7175 * Determine external LNA informations.
38bd7b8a 7176 */
38c8a566 7177 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7178 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7179 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7180 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7181
7182 /*
7183 * Detect if this device has an hardware controlled radio.
7184 */
38c8a566 7185 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7186 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7187
fdbc7b0a
GW		 7188 /*
7189 * Detect if this device has Bluetooth co-existence.
7190 */
7191 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7192 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7193
9328fdac
GW		 7194 /*
7195 * Read frequency offset and RF programming sequence.
7196 */
3e38d3da 7197 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7198 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7199
38bd7b8a
BZ		 7200 /*
7201 * Store led settings, for correct led behaviour.
7202 */
7203#ifdef CONFIG_RT2X00_LIB_LEDS
7204 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7205 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7206 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7207
9328fdac 7208 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7209#endif /* CONFIG_RT2X00_LIB_LEDS */
7210
e90c54b2
RJH		 7211 /*
7212 * Check if support EIRP tx power limit feature.
7213 */
3e38d3da 7214 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7215
7216 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7217 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7218 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7219
38bd7b8a
BZ		 7220 return 0;
7221}
38bd7b8a 7222
4da2933f 7223/*
55f9321a 7224 * RF value list for rt28xx
4da2933f
BZ		 7225 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7226 */
7227static const struct rf_channel rf_vals[] = {
7228 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7229 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7230 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7231 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7232 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7233 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7234 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7235 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7236 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7237 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7238 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7239 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7240 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7241 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7242
7243 /* 802.11 UNI / HyperLan 2 */
7244 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7245 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7246 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7247 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7248 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7249 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7250 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7251 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7252 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7253 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7254 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7255 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7256
7257 /* 802.11 HyperLan 2 */
7258 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7259 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7260 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7261 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7262 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7263 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7264 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7265 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7266 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7267 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7268 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7269 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7270 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7271 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7272 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7273 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7274
7275 /* 802.11 UNII */
7276 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7277 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7278 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7279 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7280 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7281 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7282 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7283 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7284 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7285 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7286 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7287
7288 /* 802.11 Japan */
7289 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7290 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7291 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7292 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7293 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7294 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7295 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7296};
7297
7298/*
55f9321a 7299 * RF value list for rt3xxx
b6b561c3 7300 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 7301 */
55f9321a 7302static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7303 {1, 241, 2, 2 },
7304 {2, 241, 2, 7 },
7305 {3, 242, 2, 2 },
7306 {4, 242, 2, 7 },
7307 {5, 243, 2, 2 },
7308 {6, 243, 2, 7 },
7309 {7, 244, 2, 2 },
7310 {8, 244, 2, 7 },
7311 {9, 245, 2, 2 },
7312 {10, 245, 2, 7 },
7313 {11, 246, 2, 2 },
7314 {12, 246, 2, 7 },
7315 {13, 247, 2, 2 },
7316 {14, 248, 2, 4 },
55f9321a
ID		 7317
7318 /* 802.11 UNI / HyperLan 2 */
7319 {36, 0x56, 0, 4},
7320 {38, 0x56, 0, 6},
7321 {40, 0x56, 0, 8},
7322 {44, 0x57, 0, 0},
7323 {46, 0x57, 0, 2},
7324 {48, 0x57, 0, 4},
7325 {52, 0x57, 0, 8},
7326 {54, 0x57, 0, 10},
7327 {56, 0x58, 0, 0},
7328 {60, 0x58, 0, 4},
7329 {62, 0x58, 0, 6},
7330 {64, 0x58, 0, 8},
7331
7332 /* 802.11 HyperLan 2 */
7333 {100, 0x5b, 0, 8},
7334 {102, 0x5b, 0, 10},
7335 {104, 0x5c, 0, 0},
7336 {108, 0x5c, 0, 4},
7337 {110, 0x5c, 0, 6},
7338 {112, 0x5c, 0, 8},
7339 {116, 0x5d, 0, 0},
7340 {118, 0x5d, 0, 2},
7341 {120, 0x5d, 0, 4},
7342 {124, 0x5d, 0, 8},
7343 {126, 0x5d, 0, 10},
7344 {128, 0x5e, 0, 0},
7345 {132, 0x5e, 0, 4},
7346 {134, 0x5e, 0, 6},
7347 {136, 0x5e, 0, 8},
7348 {140, 0x5f, 0, 0},
7349
7350 /* 802.11 UNII */
7351 {149, 0x5f, 0, 9},
7352 {151, 0x5f, 0, 11},
7353 {153, 0x60, 0, 1},
7354 {157, 0x60, 0, 5},
7355 {159, 0x60, 0, 7},
7356 {161, 0x60, 0, 9},
7357 {165, 0x61, 0, 1},
7358 {167, 0x61, 0, 3},
7359 {169, 0x61, 0, 5},
7360 {171, 0x61, 0, 7},
7361 {173, 0x61, 0, 9},
4da2933f
BZ		 7362};
7363
7848b231
SG		 7364static const struct rf_channel rf_vals_5592_xtal20[] = {
7365 /* Channel, N, K, mod, R */
7366 {1, 482, 4, 10, 3},
7367 {2, 483, 4, 10, 3},
7368 {3, 484, 4, 10, 3},
7369 {4, 485, 4, 10, 3},
7370 {5, 486, 4, 10, 3},
7371 {6, 487, 4, 10, 3},
7372 {7, 488, 4, 10, 3},
7373 {8, 489, 4, 10, 3},
7374 {9, 490, 4, 10, 3},
7375 {10, 491, 4, 10, 3},
7376 {11, 492, 4, 10, 3},
7377 {12, 493, 4, 10, 3},
7378 {13, 494, 4, 10, 3},
7379 {14, 496, 8, 10, 3},
7380 {36, 172, 8, 12, 1},
7381 {38, 173, 0, 12, 1},
7382 {40, 173, 4, 12, 1},
7383 {42, 173, 8, 12, 1},
7384 {44, 174, 0, 12, 1},
7385 {46, 174, 4, 12, 1},
7386 {48, 174, 8, 12, 1},
7387 {50, 175, 0, 12, 1},
7388 {52, 175, 4, 12, 1},
7389 {54, 175, 8, 12, 1},
7390 {56, 176, 0, 12, 1},
7391 {58, 176, 4, 12, 1},
7392 {60, 176, 8, 12, 1},
7393 {62, 177, 0, 12, 1},
7394 {64, 177, 4, 12, 1},
7395 {100, 183, 4, 12, 1},
7396 {102, 183, 8, 12, 1},
7397 {104, 184, 0, 12, 1},
7398 {106, 184, 4, 12, 1},
7399 {108, 184, 8, 12, 1},
7400 {110, 185, 0, 12, 1},
7401 {112, 185, 4, 12, 1},
7402 {114, 185, 8, 12, 1},
7403 {116, 186, 0, 12, 1},
7404 {118, 186, 4, 12, 1},
7405 {120, 186, 8, 12, 1},
7406 {122, 187, 0, 12, 1},
7407 {124, 187, 4, 12, 1},
7408 {126, 187, 8, 12, 1},
7409 {128, 188, 0, 12, 1},
7410 {130, 188, 4, 12, 1},
7411 {132, 188, 8, 12, 1},
7412 {134, 189, 0, 12, 1},
7413 {136, 189, 4, 12, 1},
7414 {138, 189, 8, 12, 1},
7415 {140, 190, 0, 12, 1},
7416 {149, 191, 6, 12, 1},
7417 {151, 191, 10, 12, 1},
7418 {153, 192, 2, 12, 1},
7419 {155, 192, 6, 12, 1},
7420 {157, 192, 10, 12, 1},
7421 {159, 193, 2, 12, 1},
7422 {161, 193, 6, 12, 1},
7423 {165, 194, 2, 12, 1},
7424 {184, 164, 0, 12, 1},
7425 {188, 164, 4, 12, 1},
7426 {192, 165, 8, 12, 1},
7427 {196, 166, 0, 12, 1},
7428};
7429
7430static const struct rf_channel rf_vals_5592_xtal40[] = {
7431 /* Channel, N, K, mod, R */
7432 {1, 241, 2, 10, 3},
7433 {2, 241, 7, 10, 3},
7434 {3, 242, 2, 10, 3},
7435 {4, 242, 7, 10, 3},
7436 {5, 243, 2, 10, 3},
7437 {6, 243, 7, 10, 3},
7438 {7, 244, 2, 10, 3},
7439 {8, 244, 7, 10, 3},
7440 {9, 245, 2, 10, 3},
7441 {10, 245, 7, 10, 3},
7442 {11, 246, 2, 10, 3},
7443 {12, 246, 7, 10, 3},
7444 {13, 247, 2, 10, 3},
7445 {14, 248, 4, 10, 3},
7446 {36, 86, 4, 12, 1},
7447 {38, 86, 6, 12, 1},
7448 {40, 86, 8, 12, 1},
7449 {42, 86, 10, 12, 1},
7450 {44, 87, 0, 12, 1},
7451 {46, 87, 2, 12, 1},
7452 {48, 87, 4, 12, 1},
7453 {50, 87, 6, 12, 1},
7454 {52, 87, 8, 12, 1},
7455 {54, 87, 10, 12, 1},
7456 {56, 88, 0, 12, 1},
7457 {58, 88, 2, 12, 1},
7458 {60, 88, 4, 12, 1},
7459 {62, 88, 6, 12, 1},
7460 {64, 88, 8, 12, 1},
7461 {100, 91, 8, 12, 1},
7462 {102, 91, 10, 12, 1},
7463 {104, 92, 0, 12, 1},
7464 {106, 92, 2, 12, 1},
7465 {108, 92, 4, 12, 1},
7466 {110, 92, 6, 12, 1},
7467 {112, 92, 8, 12, 1},
7468 {114, 92, 10, 12, 1},
7469 {116, 93, 0, 12, 1},
7470 {118, 93, 2, 12, 1},
7471 {120, 93, 4, 12, 1},
7472 {122, 93, 6, 12, 1},
7473 {124, 93, 8, 12, 1},
7474 {126, 93, 10, 12, 1},
7475 {128, 94, 0, 12, 1},
7476 {130, 94, 2, 12, 1},
7477 {132, 94, 4, 12, 1},
7478 {134, 94, 6, 12, 1},
7479 {136, 94, 8, 12, 1},
7480 {138, 94, 10, 12, 1},
7481 {140, 95, 0, 12, 1},
7482 {149, 95, 9, 12, 1},
7483 {151, 95, 11, 12, 1},
7484 {153, 96, 1, 12, 1},
7485 {155, 96, 3, 12, 1},
7486 {157, 96, 5, 12, 1},
7487 {159, 96, 7, 12, 1},
7488 {161, 96, 9, 12, 1},
7489 {165, 97, 1, 12, 1},
7490 {184, 82, 0, 12, 1},
7491 {188, 82, 4, 12, 1},
7492 {192, 82, 8, 12, 1},
7493 {196, 83, 0, 12, 1},
7494};
7495
ad417a53 7496static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7497{
4da2933f
BZ		 7498 struct hw_mode_spec *spec = &rt2x00dev->spec;
7499 struct channel_info *info;
8d1331b3
ID		 7500 char *default_power1;
7501 char *default_power2;
c0a14369 7502 char *default_power3;
cea5b03d 7503 unsigned int i, tx_chains, rx_chains;
7848b231 7504 u32 reg;
4da2933f 7505
93b6bd26 7506 /*
58e33a21 7507 * Disable powersaving as default.
93b6bd26 7508 */
58e33a21 7509 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 7510
4da2933f
BZ		 7511 /*
7512 * Initialize all hw fields.
7513 */
30686bf7
JB		 7514 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
7515 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
7516 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
7517 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
7518 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9d4f09b8 7519
5a5b6ed6
HS		 7520 /*
7521 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7522 * unless we are capable of sending the buffered frames out after the
7523 * DTIM transmission using rt2x00lib_beacondone. This will send out
7524 * multicast and broadcast traffic immediately instead of buffering it
7525 * infinitly and thus dropping it after some time.
7526 */
7527 if (!rt2x00_is_usb(rt2x00dev))
30686bf7 7528 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
4da2933f 7529
2557654d
CYY		 7530 /* Set MFP if HW crypto is disabled. */
7531 if (rt2800_hwcrypt_disabled(rt2x00dev))
7532 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
7533
4da2933f
BZ		 7534 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7535 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7536 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7537 EEPROM_MAC_ADDR_0));
7538
3f2bee24
HS		 7539 /*
7540 * As rt2800 has a global fallback table we cannot specify
7541 * more then one tx rate per frame but since the hw will
7542 * try several rates (based on the fallback table) we should
ba3b9e5e 7543 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7544 * we are going to try. Otherwise mac80211 will truncate our
7545 * reported tx rates and the rc algortihm will end up with
7546 * incorrect data.
7547 */
ba3b9e5e
HS		 7548 rt2x00dev->hw->max_rates = 1;
7549 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7550 rt2x00dev->hw->max_rate_tries = 1;
7551
4da2933f
BZ		 7552 /*
7553 * Initialize hw_mode information.
7554 */
4da2933f
BZ		 7555 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7556
4a32c36d
GJ		 7557 switch (rt2x00dev->chip.rf) {
7558 case RF2720:
7559 case RF2820:
4da2933f
BZ		 7560 spec->num_channels = 14;
7561 spec->channels = rf_vals;
4a32c36d
GJ		 7562 break;
7563
7564 case RF2750:
7565 case RF2850:
4da2933f
BZ		 7566 spec->num_channels = ARRAY_SIZE(rf_vals);
7567 spec->channels = rf_vals;
4a32c36d
GJ		 7568 break;
7569
7570 case RF2020:
7571 case RF3020:
7572 case RF3021:
7573 case RF3022:
7574 case RF3070:
7575 case RF3290:
7576 case RF3320:
7577 case RF3322:
7578 case RF5360:
ac0372ab 7579 case RF5362:
4a32c36d
GJ		 7580 case RF5370:
7581 case RF5372:
7582 case RF5390:
7583 case RF5392:
55f9321a
ID		 7584 spec->num_channels = 14;
7585 spec->channels = rf_vals_3x;
4a32c36d
GJ		 7586 break;
7587
7588 case RF3052:
7589 case RF3053:
55f9321a
ID		 7590 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7591 spec->channels = rf_vals_3x;
4a32c36d 7592 break;
7848b231 7593
4a32c36d 7594 case RF5592:
7848b231
SG		 7595 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7596 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7597 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7598 spec->channels = rf_vals_5592_xtal40;
7599 } else {
7600 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7601 spec->channels = rf_vals_5592_xtal20;
7602 }
4a32c36d 7603 break;
4da2933f
BZ		 7604 }
7605
53216d6a
SG		 7606 if (WARN_ON_ONCE(!spec->channels))
7607 return -ENODEV;
7608
53c5a099
GJ		 7609 spec->supported_bands = SUPPORT_BAND_2GHZ;
7610 if (spec->num_channels > 14)
7611 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7612
4da2933f
BZ		 7613 /*
7614 * Initialize HT information.
7615 */
5122d898 7616 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7617 spec->ht.ht_supported = true;
7618 else
7619 spec->ht.ht_supported = false;
7620
4da2933f 7621 spec->ht.cap =
06443e46 7622 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7623 IEEE80211_HT_CAP_GRN_FLD |
7624 IEEE80211_HT_CAP_SGI_20 |
aa674631 7625 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7626
cea5b03d
SG		 7627 tx_chains = rt2x00dev->default_ant.tx_chain_num;
7628 rx_chains = rt2x00dev->default_ant.rx_chain_num;
7629
7630 if (tx_chains >= 2)
22cabaa6
HS		 7631 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7632
cea5b03d 7633 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 7634
a08b9819 7635 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
4da2933f 7636 spec->ht.ampdu_density = 4;
cea5b03d
SG		 7637 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7638 if (tx_chains != rx_chains) {
7639 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
7640 spec->ht.mcs.tx_params |=
7641 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
7642 }
4da2933f 7643
cea5b03d 7644 switch (rx_chains) {
4da2933f
BZ		 7645 case 3:
7646 spec->ht.mcs.rx_mask[2] = 0xff;
7647 case 2:
7648 spec->ht.mcs.rx_mask[1] = 0xff;
7649 case 1:
7650 spec->ht.mcs.rx_mask[0] = 0xff;
7651 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7652 break;
7653 }
7654
7655 /*
7656 * Create channel information array
7657 */
baeb2ffa 7658 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7659 if (!info)
7660 return -ENOMEM;
7661
7662 spec->channels_info = info;
7663
3e38d3da
GJ		 7664 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7665 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7666
c0a14369
GJ		 7667 if (rt2x00dev->default_ant.tx_chain_num > 2)
7668 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7669 EEPROM_EXT_TXPOWER_BG3);
7670 else
7671 default_power3 = NULL;
7672
4da2933f 7673 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7674 info[i].default_power1 = default_power1[i];
7675 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7676 if (default_power3)
7677 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7678 }
7679
7680 if (spec->num_channels > 14) {
3e38d3da
GJ		 7681 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7682 EEPROM_TXPOWER_A1);
7683 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7684 EEPROM_TXPOWER_A2);
4da2933f 7685
c0a14369
GJ		 7686 if (rt2x00dev->default_ant.tx_chain_num > 2)
7687 default_power3 =
7688 rt2800_eeprom_addr(rt2x00dev,
7689 EEPROM_EXT_TXPOWER_A3);
7690 else
7691 default_power3 = NULL;
7692
4da2933f 7693 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7694 info[i].default_power1 = default_power1[i - 14];
7695 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7696 if (default_power3)
7697 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7698 }
7699 }
7700
2e9c43dd
JL		 7701 switch (rt2x00dev->chip.rf) {
7702 case RF2020:
7703 case RF3020:
7704 case RF3021:
7705 case RF3022:
7706 case RF3320:
7707 case RF3052:
1095df07 7708 case RF3053:
3b9b74ba 7709 case RF3070:
a89534ed 7710 case RF3290:
ccf91bd6 7711 case RF5360:
ac0372ab 7712 case RF5362:
2e9c43dd
JL		 7713 case RF5370:
7714 case RF5372:
7715 case RF5390:
cff3d1f0 7716 case RF5392:
2e9c43dd
JL		 7717 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7718 break;
7719 }
7720
4da2933f
BZ		 7721 return 0;
7722}
ad417a53 7723
cbafb601
GJ		 7724static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7725{
7726 u32 reg;
7727 u32 rt;
7728 u32 rev;
7729
7730 if (rt2x00_rt(rt2x00dev, RT3290))
7731 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7732 else
7733 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7734
7735 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7736 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7737
7738 switch (rt) {
7739 case RT2860:
7740 case RT2872:
7741 case RT2883:
7742 case RT3070:
7743 case RT3071:
7744 case RT3090:
7745 case RT3290:
7746 case RT3352:
7747 case RT3390:
7748 case RT3572:
2dc2bd2f 7749 case RT3593:
cbafb601
GJ		 7750 case RT5390:
7751 case RT5392:
7752 case RT5592:
7753 break;
7754 default:
ec9c4989
JP		 7755 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7756 rt, rev);
cbafb601
GJ		 7757 return -ENODEV;
7758 }
7759
7760 rt2x00_set_rt(rt2x00dev, rt, rev);
7761
7762 return 0;
7763}
7764
ad417a53
GW		 7765int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7766{
7767 int retval;
7768 u32 reg;
7769
cbafb601
GJ		 7770 retval = rt2800_probe_rt(rt2x00dev);
7771 if (retval)
7772 return retval;
7773
ad417a53
GW		 7774 /*
7775 * Allocate eeprom data.
7776 */
7777 retval = rt2800_validate_eeprom(rt2x00dev);
7778 if (retval)
7779 return retval;
7780
7781 retval = rt2800_init_eeprom(rt2x00dev);
7782 if (retval)
7783 return retval;
7784
7785 /*
7786 * Enable rfkill polling by setting GPIO direction of the
7787 * rfkill switch GPIO pin correctly.
7788 */
7789 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7790 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7791 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7792
7793 /*
7794 * Initialize hw specifications.
7795 */
7796 retval = rt2800_probe_hw_mode(rt2x00dev);
7797 if (retval)
7798 return retval;
7799
7800 /*
7801 * Set device capabilities.
7802 */
7803 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7804 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7805 if (!rt2x00_is_usb(rt2x00dev))
7806 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7807
7808 /*
7809 * Set device requirements.
7810 */
7811 if (!rt2x00_is_soc(rt2x00dev))
7812 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7813 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7814 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7815 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7816 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7817 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7818 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7819 if (rt2x00_is_usb(rt2x00dev))
7820 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7821 else {
7822 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7823 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7824 }
7825
7826 /*
7827 * Set the rssi offset.
7828 */
7829 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7830
7831 return 0;
7832}
7833EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7834
2ce33995
BZ		 7835/*
7836 * IEEE80211 stack callback functions.
7837 */
9352c19f
JB		 7838void rt2800_get_key_seq(struct ieee80211_hw *hw,
7839 struct ieee80211_key_conf *key,
7840 struct ieee80211_key_seq *seq)
2ce33995
BZ		 7841{
7842 struct rt2x00_dev *rt2x00dev = hw->priv;
7843 struct mac_iveiv_entry iveiv_entry;
7844 u32 offset;
7845
9352c19f
JB		 7846 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
7847 return;
7848
7849 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
2ce33995
BZ		 7850 rt2800_register_multiread(rt2x00dev, offset,
7851 &iveiv_entry, sizeof(iveiv_entry));
7852
9352c19f
JB		 7853 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
7854 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
2ce33995 7855}
9352c19f 7856EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
2ce33995 7857
e783619e 7858int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7859{
7860 struct rt2x00_dev *rt2x00dev = hw->priv;
7861 u32 reg;
7862 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7863
7864 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7865 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7866 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7867
7868 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7869 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7870 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7871
7872 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7873 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7874 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7875
7876 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7877 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7878 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7879
7880 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7881 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7882 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7883
7884 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7885 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7886 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7887
7888 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7889 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7890 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7891
7892 return 0;
7893}
e783619e 7894EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7895
8a3a3c85
EP		 7896int rt2800_conf_tx(struct ieee80211_hw *hw,
7897 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7898 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7899{
7900 struct rt2x00_dev *rt2x00dev = hw->priv;
7901 struct data_queue *queue;
7902 struct rt2x00_field32 field;
7903 int retval;
7904 u32 reg;
7905 u32 offset;
7906
7907 /*
7908 * First pass the configuration through rt2x00lib, that will
7909 * update the queue settings and validate the input. After that
7910 * we are free to update the registers based on the value
7911 * in the queue parameter.
7912 */
8a3a3c85 7913 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7914 if (retval)
7915 return retval;
7916
7917 /*
7918 * We only need to perform additional register initialization
7919 * for WMM queues/
7920 */
7921 if (queue_idx >= 4)
7922 return 0;
7923
11f818e0 7924 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7925
7926 /* Update WMM TXOP register */
7927 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7928 field.bit_offset = (queue_idx & 1) * 16;
7929 field.bit_mask = 0xffff << field.bit_offset;
7930
7931 rt2800_register_read(rt2x00dev, offset, &reg);
7932 rt2x00_set_field32(&reg, field, queue->txop);
7933 rt2800_register_write(rt2x00dev, offset, reg);
7934
7935 /* Update WMM registers */
7936 field.bit_offset = queue_idx * 4;
7937 field.bit_mask = 0xf << field.bit_offset;
7938
7939 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7940 rt2x00_set_field32(&reg, field, queue->aifs);
7941 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7942
7943 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7944 rt2x00_set_field32(&reg, field, queue->cw_min);
7945 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7946
7947 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7948 rt2x00_set_field32(&reg, field, queue->cw_max);
7949 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7950
7951 /* Update EDCA registers */
7952 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7953
7954 rt2800_register_read(rt2x00dev, offset, &reg);
7955 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7956 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7957 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7958 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7959 rt2800_register_write(rt2x00dev, offset, reg);
7960
7961 return 0;
7962}
e783619e 7963EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7964
37a41b4a 7965u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7966{
7967 struct rt2x00_dev *rt2x00dev = hw->priv;
7968 u64 tsf;
7969 u32 reg;
7970
7971 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7972 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7973 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7974 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7975
7976 return tsf;
7977}
e783619e 7978EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7979
e783619e 7980int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 7981 struct ieee80211_ampdu_params *params)
1df90809 7982{
50ea05ef
SS		 7983 struct ieee80211_sta *sta = params->sta;
7984 enum ieee80211_ampdu_mlme_action action = params->action;
7985 u16 tid = params->tid;
af35323d 7986 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7987 int ret = 0;
7988
af35323d
HS		 7989 /*
7990 * Don't allow aggregation for stations the hardware isn't aware
7991 * of because tx status reports for frames to an unknown station
ed8e0ed5
SG		 7992 * always contain wcid=WCID_END+1 and thus we can't distinguish
7993 * between multiple stations which leads to unwanted situations
7994 * when the hw reorders frames due to aggregation.
af35323d 7995 */
ed8e0ed5 7996 if (sta_priv->wcid > WCID_END)
af35323d
HS		 7997 return 1;
7998
1df90809
HS		 7999 switch (action) {
8000 case IEEE80211_AMPDU_RX_START:
8001 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 8002 /*
8003 * The hw itself takes care of setting up BlockAck mechanisms.
8004 * So, we only have to allow mac80211 to nagotiate a BlockAck
8005 * agreement. Once that is done, the hw will BlockAck incoming
8006 * AMPDUs without further setup.
8007 */
1df90809
HS		 8008 break;
8009 case IEEE80211_AMPDU_TX_START:
8010 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8011 break;
18b559d5
JB		 8012 case IEEE80211_AMPDU_TX_STOP_CONT:
8013 case IEEE80211_AMPDU_TX_STOP_FLUSH:
8014 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 8015 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8016 break;
8017 case IEEE80211_AMPDU_TX_OPERATIONAL:
8018 break;
8019 default:
ec9c4989
JP		 8020 rt2x00_warn((struct rt2x00_dev *)hw->priv,
8021 "Unknown AMPDU action\n");
1df90809
HS		 8022 }
8023
8024 return ret;
8025}
e783619e 8026EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 8027
977206d7
HS		 8028int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
8029 struct survey_info *survey)
8030{
8031 struct rt2x00_dev *rt2x00dev = hw->priv;
8032 struct ieee80211_conf *conf = &hw->conf;
8033 u32 idle, busy, busy_ext;
8034
8035 if (idx != 0)
8036 return -ENOENT;
8037
675a0b04 8038 survey->channel = conf->chandef.chan;
977206d7
HS		 8039
8040 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8041 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8042 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8043
8044 if (idle || busy) {
4ed20beb
JB		 8045 survey->filled = SURVEY_INFO_TIME |
8046 SURVEY_INFO_TIME_BUSY |
8047 SURVEY_INFO_TIME_EXT_BUSY;
977206d7 8048
4ed20beb
JB		 8049 survey->time = (idle + busy) / 1000;
8050 survey->time_busy = busy / 1000;
8051 survey->time_ext_busy = busy_ext / 1000;
977206d7
HS		 8052 }
8053
9931df26
HS		 8054 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8055 survey->filled |= SURVEY_INFO_IN_USE;
8056
977206d7
HS		 8057 return 0;
8058
8059}
8060EXPORT_SYMBOL_GPL(rt2800_get_survey);
8061
a5ea2f02
ID		 8062MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8063MODULE_VERSION(DRV_VERSION);
8064MODULE_DESCRIPTION("Ralink RT2800 library");
8065MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror