]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/wireless/ralink/rt2x00/rt2800lib.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2800: don't set ht parameters for non-aggregated frames
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ralink / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
ec9c4989 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
89297425 109
fcf51541
BZ		 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
89297425
BZ		 112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
89297425 141
fcf51541
BZ		 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
89297425
BZ		 144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
89297425 165
fcf51541
BZ		 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
89297425
BZ		 168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
89297425 196
fcf51541
BZ		 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
89297425
BZ		 199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
89297425 221
379448fe
GJ		 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
fa31d157
GJ		 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 279 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
379448fe
GJ		 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
fa31d157
GJ		 312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
379448fe
GJ		 317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
3e38d3da
GJ		 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
379448fe
GJ		 335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
379448fe
GJ		 344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
379448fe
GJ		 353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 357}
358
022138ca
GJ		 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
379448fe
GJ		 364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 368}
369
16ebd608
WH		 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(&reg, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(&reg, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(&reg, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
89297425
BZ		 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
ee303e54 437 /*
cea90e55 438 * SOC devices don't support MCU requests.
ee303e54 439 */
cea90e55 440 if (rt2x00_is_soc(rt2x00dev))
ee303e54 441 return;
89297425
BZ		 442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 464
5ffddc49
ID		 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
ec9c4989 477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
67a4c1e2
GW		 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
08e53100
HS		 487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
67a4c1e2
GW		 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
08e53100 497 msleep(10);
67a4c1e2
GW		 498 }
499
ec9c4989 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
f7b395e9
JK		 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
ae1b1c5d
GJ		 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
f31c9a8c
ID		 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
f31c9a8c 589 */
a89534ed 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 591 fw_len = 4096;
a89534ed 592 else
f31c9a8c 593 fw_len = 8192;
f31c9a8c 594
a89534ed 595 multiple = true;
f31c9a8c
ID		 596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
16ebd608
WH		 633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
f31c9a8c
ID		 640
641 /*
b9eca242
ID		 642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 644 */
b9eca242 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 646
f31c9a8c
ID		 647 /*
648 * Wait for stable hardware.
649 */
5ffddc49 650 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 651 return -EBUSY;
f31c9a8c 652
adde5882 653 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
f31c9a8c 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 664 }
f31c9a8c 665
b7e1d225
JK		 666 rt2800_disable_wpdma(rt2x00dev);
667
f31c9a8c
ID		 668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 685 return -EBUSY;
686 }
687
4ed1dd2a
SG		 688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
f7b395e9 692 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 693
f31c9a8c
ID		 694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 699 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
f31c9a8c
ID		 703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
0c5879bc
ID		 709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
59679b91 711{
0c5879bc 712 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 713 u32 word;
557985ae 714 int i;
59679b91
GW		 715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 749 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
2b23cdaa 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
557985ae
SG		 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 762 *
763 * Nulify all remaining words as well, we don't know how to program them.
59679b91 764 */
557985ae
SG		 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
59679b91 767}
0c5879bc 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 769
ff6133be 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 771{
7fc41755
LT		 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
57fbcce3 780 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
3e38d3da 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
7fc41755 810 return (int)max(rssi0, rssi2);
74861922
ID		 811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
74861922
ID		 847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
31937c42 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
b34793ee 865 int aggr, ampdu;
14433331
HS		 866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
14433331 871 rt2x00_desc_read(txwi, 0, &word);
b34793ee 872
14433331 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
14433331 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
5356d963 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
14433331 899
f16d2db7
HS		 900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
14433331
HS		 903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
21c6af6b
GJ		 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
634b8059
GJ		 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
ba08910e
SG		 950static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
951{
952 struct data_queue *queue = rt2x00dev->bcn;
953 struct queue_entry *entry;
954 int i, bcn_num = 0;
955 u64 off, reg = 0;
956 u32 bssid_dw1;
957
958 /*
959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
960 */
961 for (i = 0; i < queue->limit; i++) {
962 entry = &queue->entries[i];
963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
964 continue;
965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
966 reg |= off << (8 * bcn_num);
967 bcn_num++;
968 }
969
970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
971
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
974
975 /*
976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
977 */
978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
980 bcn_num > 0 ? bcn_num - 1 : 0);
981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
982}
983
f0194b2d
GW		 984void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
985{
986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
988 unsigned int beacon_base;
739fd940 989 unsigned int padding_len;
d76dfc61 990 u32 orig_reg, reg;
f0bda571 991 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 992
993 /*
994 * Disable beaconing while we are reloading the beacon data,
995 * otherwise we might be sending out invalid data.
996 */
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 998 orig_reg = reg;
f0194b2d
GW		 999 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002 /*
1003 * Add space for the TXWI in front of the skb.
1004 */
f0bda571 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1006
1007 /*
1008 * Register descriptor details in skb frame descriptor.
1009 */
1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011 skbdesc->desc = entry->skb->data;
f0bda571 1012 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1013
1014 /*
1015 * Add the TXWI for the beacon to the skb.
1016 */
0c5879bc 1017 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1018
1019 /*
1020 * Dump beacon to userspace through debugfs.
1021 */
1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024 /*
739fd940 1025 * Write entire beacon with TXWI and padding to register.
f0194b2d 1026 */
739fd940 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1028 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1030 /* skb freed by skb_pad() on failure */
1031 entry->skb = NULL;
1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033 return;
1034 }
1035
21c6af6b
GJ		 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
739fd940
WK		 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039 entry->skb->len + padding_len);
ba08910e
SG		 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042 /*
1043 * Change global beacons settings.
1044 */
1045 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1046
1047 /*
bc0df75a 1048 * Restore beaconing state.
f0194b2d 1049 */
bc0df75a 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1051
1052 /*
1053 * Clean up beacon skb.
1054 */
1055 dev_kfree_skb_any(entry->skb);
1056 entry->skb = NULL;
1057}
50e888ea 1058EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1059
69cf36a4 1060static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1061 unsigned int index)
fdb87251
HS		 1062{
1063 int i;
0879f875 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1065 unsigned int beacon_base;
1066
21c6af6b 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1068
1069 /*
1070 * For the Beacon base registers we only need to clear
1071 * the whole TXWI which (when set to 0) will invalidate
1072 * the entire beacon.
1073 */
f0bda571 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076}
1077
69cf36a4
HS		 1078void rt2800_clear_beacon(struct queue_entry *entry)
1079{
1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1081 u32 orig_reg, reg;
69cf36a4
HS		 1082
1083 /*
1084 * Disable beaconing while we are reloading the beacon data,
1085 * otherwise we might be sending out invalid data.
1086 */
bc0df75a
SG		 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088 reg = orig_reg;
69cf36a4
HS		 1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092 /*
1093 * Clear beacon.
1094 */
77f7c0f3 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1097
ba08910e
SG		 1098 /*
1099 * Change global beacons settings.
1100 */
1101 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1102 /*
bc0df75a 1103 * Restore beaconing state.
69cf36a4 1104 */
bc0df75a 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1106}
1107EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
f4450616
BZ		 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110const struct rt2x00debug rt2800_rt2x00debug = {
1111 .owner = THIS_MODULE,
1112 .csr = {
1113 .read = rt2800_register_read,
1114 .write = rt2800_register_write,
1115 .flags = RT2X00DEBUGFS_OFFSET,
1116 .word_base = CSR_REG_BASE,
1117 .word_size = sizeof(u32),
1118 .word_count = CSR_REG_SIZE / sizeof(u32),
1119 },
1120 .eeprom = {
3e38d3da
GJ		 1121 /* NOTE: The local EEPROM access functions can't
1122 * be used here, use the generic versions instead.
1123 */
f4450616
BZ		 1124 .read = rt2x00_eeprom_read,
1125 .write = rt2x00_eeprom_write,
1126 .word_base = EEPROM_BASE,
1127 .word_size = sizeof(u16),
1128 .word_count = EEPROM_SIZE / sizeof(u16),
1129 },
1130 .bbp = {
1131 .read = rt2800_bbp_read,
1132 .write = rt2800_bbp_write,
1133 .word_base = BBP_BASE,
1134 .word_size = sizeof(u8),
1135 .word_count = BBP_SIZE / sizeof(u8),
1136 },
1137 .rf = {
1138 .read = rt2x00_rf_read,
1139 .write = rt2800_rf_write,
1140 .word_base = RF_BASE,
1141 .word_size = sizeof(u32),
1142 .word_count = RF_SIZE / sizeof(u32),
1143 },
f2bd7f16
AA		 1144 .rfcsr = {
1145 .read = rt2800_rfcsr_read,
1146 .write = rt2800_rfcsr_write,
1147 .word_base = RFCSR_BASE,
1148 .word_size = sizeof(u8),
1149 .word_count = RFCSR_SIZE / sizeof(u8),
1150 },
f4450616
BZ		 1151};
1152EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156{
1157 u32 reg;
1158
a89534ed
WH		 1159 if (rt2x00_rt(rt2x00dev, RT3290)) {
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162 } else {
99bdf51a
GW		 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1165 }
f4450616
BZ		 1166}
1167EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169#ifdef CONFIG_RT2X00_LIB_LEDS
1170static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171 enum led_brightness brightness)
1172{
1173 struct rt2x00_led *led =
1174 container_of(led_cdev, struct rt2x00_led, led_dev);
1175 unsigned int enabled = brightness != LED_OFF;
1176 unsigned int bg_mode =
57fbcce3 1177 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
f4450616
BZ		 1178 unsigned int polarity =
1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180 EEPROM_FREQ_LED_POLARITY);
1181 unsigned int ledmode =
1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183 EEPROM_FREQ_LED_MODE);
44704e5d 1184 u32 reg;
f4450616 1185
44704e5d
LE		 1186 /* Check for SoC (SOC devices don't support MCU requests) */
1187 if (rt2x00_is_soc(led->rt2x00dev)) {
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190 /* Set LED Polarity */
1191 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193 /* Set LED Mode */
1194 if (led->type == LED_TYPE_RADIO) {
1195 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196 enabled ? 3 : 0);
1197 } else if (led->type == LED_TYPE_ASSOC) {
1198 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199 enabled ? 3 : 0);
1200 } else if (led->type == LED_TYPE_QUALITY) {
1201 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202 enabled ? 3 : 0);
1203 }
1204
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207 } else {
1208 if (led->type == LED_TYPE_RADIO) {
1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210 enabled ? 0x20 : 0);
1211 } else if (led->type == LED_TYPE_ASSOC) {
1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214 } else if (led->type == LED_TYPE_QUALITY) {
1215 /*
1216 * The brightness is divided into 6 levels (0 - 5),
1217 * The specs tell us the following levels:
1218 * 0, 1 ,3, 7, 15, 31
1219 * to determine the level in a simple way we can simply
1220 * work with bitshifting:
1221 * (1 << level) - 1
1222 */
1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224 (1 << brightness / (LED_FULL / 6)) - 1,
1225 polarity);
1226 }
f4450616
BZ		 1227 }
1228}
1229
b3579d6a 1230static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1231 struct rt2x00_led *led, enum led_type type)
1232{
1233 led->rt2x00dev = rt2x00dev;
1234 led->type = type;
1235 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1236 led->flags = LED_INITIALIZED;
1237}
f4450616
BZ		 1238#endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240/*
1241 * Configuration handlers.
1242 */
a2b1328a
HS		 1243static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244 const u8 *address,
1245 int wcid)
f4450616
BZ		 1246{
1247 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1248 u32 offset;
1249
1250 offset = MAC_WCID_ENTRY(wcid);
1251
1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253 if (address)
1254 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256 rt2800_register_multiwrite(rt2x00dev, offset,
1257 &wcid_entry, sizeof(wcid_entry));
1258}
1259
1260static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261{
1262 u32 offset;
1263 offset = MAC_WCID_ATTR_ENTRY(wcid);
1264 rt2800_register_write(rt2x00dev, offset, 0);
1265}
1266
1267static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268 int wcid, u32 bssidx)
1269{
1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271 u32 reg;
1272
1273 /*
1274 * The BSS Idx numbers is split in a main value of 3 bits,
1275 * and a extended field for adding one additional bit to the value.
1276 */
1277 rt2800_register_read(rt2x00dev, offset, &reg);
1278 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280 (bssidx & 0x8) >> 3);
1281 rt2800_register_write(rt2x00dev, offset, reg);
1282}
1283
1284static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_crypto *crypto,
1286 struct ieee80211_key_conf *key)
1287{
f4450616
BZ		 1288 struct mac_iveiv_entry iveiv_entry;
1289 u32 offset;
1290 u32 reg;
1291
1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
e4a0ab34
ID		 1294 if (crypto->cmd == SET_KEY) {
1295 rt2800_register_read(rt2x00dev, offset, &reg);
1296 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298 /*
1299 * Both the cipher as the BSS Idx numbers are split in a main
1300 * value of 3 bits, and a extended field for adding one additional
1301 * bit to the value.
1302 */
1303 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304 (crypto->cipher & 0x7));
1305 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1307 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308 rt2800_register_write(rt2x00dev, offset, reg);
1309 } else {
a2b1328a
HS		 1310 /* Delete the cipher without touching the bssidx */
1311 rt2800_register_read(rt2x00dev, offset, &reg);
1312 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1317 }
f4450616
BZ		 1318
1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322 if ((crypto->cipher == CIPHER_TKIP) ||
1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324 (crypto->cipher == CIPHER_AES))
1325 iveiv_entry.iv[3] |= 0x20;
1326 iveiv_entry.iv[3] |= key->keyidx << 6;
1327 rt2800_register_multiwrite(rt2x00dev, offset,
1328 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1329}
1330
1331int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332 struct rt2x00lib_crypto *crypto,
1333 struct ieee80211_key_conf *key)
1334{
1335 struct hw_key_entry key_entry;
1336 struct rt2x00_field32 field;
1337 u32 offset;
1338 u32 reg;
1339
1340 if (crypto->cmd == SET_KEY) {
1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343 memcpy(key_entry.key, crypto->key,
1344 sizeof(key_entry.key));
1345 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346 sizeof(key_entry.tx_mic));
1347 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348 sizeof(key_entry.rx_mic));
1349
1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351 rt2800_register_multiwrite(rt2x00dev, offset,
1352 &key_entry, sizeof(key_entry));
1353 }
1354
1355 /*
1356 * The cipher types are stored over multiple registers
1357 * starting with SHARED_KEY_MODE_BASE each word will have
1358 * 32 bits and contains the cipher types for 2 bssidx each.
1359 * Using the correct defines correctly will cause overhead,
1360 * so just calculate the correct offset.
1361 */
1362 field.bit_offset = 4 * (key->hw_key_idx % 8);
1363 field.bit_mask = 0x7 << field.bit_offset;
1364
1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367 rt2800_register_read(rt2x00dev, offset, &reg);
1368 rt2x00_set_field32(&reg, field,
1369 (crypto->cmd == SET_KEY) * crypto->cipher);
1370 rt2800_register_write(rt2x00dev, offset, reg);
1371
1372 /*
1373 * Update WCID information
1374 */
a2b1328a
HS		 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377 crypto->bssidx);
1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1379
1380 return 0;
1381}
1382EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
1384int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1385 struct rt2x00lib_crypto *crypto,
1386 struct ieee80211_key_conf *key)
1387{
1388 struct hw_key_entry key_entry;
1389 u32 offset;
1390
1391 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1392 /*
1393 * Allow key configuration only for STAs that are
1394 * known by the hw.
1395 */
ed8e0ed5 1396 if (crypto->wcid > WCID_END)
f4450616 1397 return -ENOSPC;
a2b1328a 1398 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1399
1400 memcpy(key_entry.key, crypto->key,
1401 sizeof(key_entry.key));
1402 memcpy(key_entry.tx_mic, crypto->tx_mic,
1403 sizeof(key_entry.tx_mic));
1404 memcpy(key_entry.rx_mic, crypto->rx_mic,
1405 sizeof(key_entry.rx_mic));
1406
1407 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1408 rt2800_register_multiwrite(rt2x00dev, offset,
1409 &key_entry, sizeof(key_entry));
1410 }
1411
1412 /*
1413 * Update WCID information
1414 */
a2b1328a 1415 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1416
1417 return 0;
1418}
1419EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1420
a2b1328a
HS		 1421int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1422 struct ieee80211_sta *sta)
1423{
1424 int wcid;
1425 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
ed8e0ed5 1426 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
a2b1328a
HS		 1427
1428 /*
ed8e0ed5
SG		 1429 * Search for the first free WCID entry and return the corresponding
1430 * index.
a2b1328a 1431 */
ed8e0ed5 1432 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
a2b1328a
HS		 1433
1434 /*
1435 * Store selected wcid even if it is invalid so that we can
1436 * later decide if the STA is uploaded into the hw.
1437 */
1438 sta_priv->wcid = wcid;
1439
1440 /*
1441 * No space left in the device, however, we can still communicate
1442 * with the STA -> No error.
1443 */
ed8e0ed5 1444 if (wcid > WCID_END)
a2b1328a
HS		 1445 return 0;
1446
ed8e0ed5
SG		 1447 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1448
a2b1328a
HS		 1449 /*
1450 * Clean up WCID attributes and write STA address to the device.
1451 */
1452 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1453 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1454 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1455 rt2x00lib_get_bssidx(rt2x00dev, vif));
1456 return 0;
1457}
1458EXPORT_SYMBOL_GPL(rt2800_sta_add);
1459
1460int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1461{
ed8e0ed5
SG		 1462 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1463
1464 if (wcid > WCID_END)
1465 return 0;
a2b1328a
HS		 1466 /*
1467 * Remove WCID entry, no need to clean the attributes as they will
1468 * get renewed when the WCID is reused.
1469 */
1470 rt2800_config_wcid(rt2x00dev, NULL, wcid);
ed8e0ed5 1471 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
a2b1328a
HS		 1472
1473 return 0;
1474}
1475EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1476
f4450616
BZ		 1477void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1478 const unsigned int filter_flags)
1479{
1480 u32 reg;
1481
1482 /*
1483 * Start configuration steps.
1484 * Note that the version error will always be dropped
1485 * and broadcast frames will always be accepted since
1486 * there is no filter for it at this time.
1487 */
1488 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1489 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1490 !(filter_flags & FIF_FCSFAIL));
1491 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1492 !(filter_flags & FIF_PLCPFAIL));
262c741e
EC		 1493 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1494 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
f4450616
BZ		 1495 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1496 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1497 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1498 !(filter_flags & FIF_ALLMULTI));
1499 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1501 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1502 !(filter_flags & FIF_CONTROL));
1503 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1504 !(filter_flags & FIF_CONTROL));
1505 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1506 !(filter_flags & FIF_CONTROL));
1507 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1508 !(filter_flags & FIF_CONTROL));
1509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1510 !(filter_flags & FIF_CONTROL));
1511 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1512 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1513 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1515 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1517 !(filter_flags & FIF_CONTROL));
1518 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1519}
1520EXPORT_SYMBOL_GPL(rt2800_config_filter);
1521
1522void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1523 struct rt2x00intf_conf *conf, const unsigned int flags)
1524{
f4450616 1525 u32 reg;
fa8b4b22 1526 bool update_bssid = false;
f4450616
BZ		 1527
1528 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1529 /*
1530 * Enable synchronisation.
1531 */
1532 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1533 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1534 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1535
1536 if (conf->sync == TSF_SYNC_AP_NONE) {
1537 /*
1538 * Tune beacon queue transmit parameters for AP mode
1539 */
1540 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1541 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1542 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1543 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1544 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1545 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1546 } else {
1547 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1548 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1549 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1550 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1551 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1552 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1553 }
f4450616
BZ		 1554 }
1555
1556 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1557 if (flags & CONFIG_UPDATE_TYPE &&
1558 conf->sync == TSF_SYNC_AP_NONE) {
1559 /*
1560 * The BSSID register has to be set to our own mac
1561 * address in AP mode.
1562 */
1563 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1564 update_bssid = true;
1565 }
1566
c600c826
ID		 1567 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1568 reg = le32_to_cpu(conf->mac[1]);
1569 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1570 conf->mac[1] = cpu_to_le32(reg);
1571 }
f4450616
BZ		 1572
1573 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1574 conf->mac, sizeof(conf->mac));
1575 }
1576
fa8b4b22 1577 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1578 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1579 reg = le32_to_cpu(conf->bssid[1]);
1580 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1581 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1582 conf->bssid[1] = cpu_to_le32(reg);
1583 }
f4450616
BZ		 1584
1585 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1586 conf->bssid, sizeof(conf->bssid));
1587 }
1588}
1589EXPORT_SYMBOL_GPL(rt2800_config_intf);
1590
87c1915d
HS		 1591static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1592 struct rt2x00lib_erp *erp)
1593{
1594 bool any_sta_nongf = !!(erp->ht_opmode &
1595 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1596 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1597 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1598 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1599 u32 reg;
1600
1601 /* default protection rate for HT20: OFDM 24M */
1602 mm20_rate = gf20_rate = 0x4004;
1603
1604 /* default protection rate for HT40: duplicate OFDM 24M */
1605 mm40_rate = gf40_rate = 0x4084;
1606
1607 switch (protection) {
1608 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1609 /*
1610 * All STAs in this BSS are HT20/40 but there might be
1611 * STAs not supporting greenfield mode.
1612 * => Disable protection for HT transmissions.
1613 */
1614 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1615
1616 break;
1617 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1618 /*
1619 * All STAs in this BSS are HT20 or HT20/40 but there
1620 * might be STAs not supporting greenfield mode.
1621 * => Protect all HT40 transmissions.
1622 */
1623 mm20_mode = gf20_mode = 0;
6c40063d 1624 mm40_mode = gf40_mode = 1;
87c1915d
HS		 1625
1626 break;
1627 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1628 /*
1629 * Nonmember protection:
1630 * According to 802.11n we _should_ protect all
1631 * HT transmissions (but we don't have to).
1632 *
1633 * But if cts_protection is enabled we _shall_ protect
1634 * all HT transmissions using a CCK rate.
1635 *
1636 * And if any station is non GF we _shall_ protect
1637 * GF transmissions.
1638 *
1639 * We decide to protect everything
1640 * -> fall through to mixed mode.
1641 */
1642 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1643 /*
1644 * Legacy STAs are present
1645 * => Protect all HT transmissions.
1646 */
6c40063d 1647 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
87c1915d
HS		 1648
1649 /*
1650 * If erp protection is needed we have to protect HT
1651 * transmissions with CCK 11M long preamble.
1652 */
1653 if (erp->cts_protection) {
1654 /* don't duplicate RTS/CTS in CCK mode */
1655 mm20_rate = mm40_rate = 0x0003;
1656 gf20_rate = gf40_rate = 0x0003;
1657 }
1658 break;
6403eab1 1659 }
87c1915d
HS		 1660
1661 /* check for STAs not supporting greenfield mode */
1662 if (any_sta_nongf)
6c40063d 1663 gf20_mode = gf40_mode = 1;
87c1915d
HS		 1664
1665 /* Update HT protection config */
1666 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1667 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1668 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1669 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1670
1671 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1672 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1673 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1674 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1675
1676 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1677 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1678 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1679 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1680
1681 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1682 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1683 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1684 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1685}
1686
02044643
HS		 1687void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1688 u32 changed)
f4450616
BZ		 1689{
1690 u32 reg;
1691
02044643
HS		 1692 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1693 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
02044643
HS		 1694 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1695 !!erp->short_preamble);
1696 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1697 }
f4450616 1698
02044643
HS		 1699 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1700 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1701 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1702 erp->cts_protection ? 2 : 0);
1703 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1704 }
f4450616 1705
02044643
HS		 1706 if (changed & BSS_CHANGED_BASIC_RATES) {
1707 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
770e4b73 1708 0xff0 | erp->basic_rates);
02044643
HS		 1709 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1710 }
f4450616 1711
02044643
HS		 1712 if (changed & BSS_CHANGED_ERP_SLOT) {
1713 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1714 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1715 erp->slot_time);
1716 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1717
02044643
HS		 1718 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1719 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1720 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1721 }
f4450616 1722
02044643
HS		 1723 if (changed & BSS_CHANGED_BEACON_INT) {
1724 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1725 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1726 erp->beacon_int * 16);
1727 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1728 }
87c1915d
HS		 1729
1730 if (changed & BSS_CHANGED_HT)
1731 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1732}
1733EXPORT_SYMBOL_GPL(rt2800_config_erp);
1734
872834df
GW		 1735static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1736{
1737 u32 reg;
1738 u16 eeprom;
1739 u8 led_ctrl, led_g_mode, led_r_mode;
1740
1741 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
57fbcce3 1742 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
872834df
GW		 1743 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1744 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1745 } else {
1746 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1747 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1748 }
1749 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1750
1751 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1752 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1753 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1754 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1755 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1756 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1757 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1758 if (led_ctrl == 0 || led_ctrl > 0x40) {
1759 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1760 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1761 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1762 } else {
1763 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1764 (led_g_mode << 2) | led_r_mode, 1);
1765 }
1766 }
1767}
1768
d96aa640
RJH		 1769static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1770 enum antenna ant)
1771{
1772 u32 reg;
1773 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1774 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1775
1776 if (rt2x00_is_pci(rt2x00dev)) {
1777 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1778 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1779 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1780 } else if (rt2x00_is_usb(rt2x00dev))
1781 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1782 eesk_pin, 0);
1783
99bdf51a
GW		 1784 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1785 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1786 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1787 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1788}
1789
f4450616
BZ		 1790void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1791{
1792 u8 r1;
1793 u8 r3;
d96aa640 1794 u16 eeprom;
f4450616
BZ		 1795
1796 rt2800_bbp_read(rt2x00dev, 1, &r1);
1797 rt2800_bbp_read(rt2x00dev, 3, &r3);
1798
872834df 1799 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1800 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1801 rt2800_config_3572bt_ant(rt2x00dev);
1802
f4450616
BZ		 1803 /*
1804 * Configure the TX antenna.
1805 */
d96aa640 1806 switch (ant->tx_chain_num) {
f4450616
BZ		 1807 case 1:
1808 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1809 break;
1810 case 2:
872834df 1811 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1812 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1813 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1814 else
1815 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1816 break;
1817 case 3:
4788ac1e 1818 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1819 break;
1820 }
1821
1822 /*
1823 * Configure the RX antenna.
1824 */
d96aa640 1825 switch (ant->rx_chain_num) {
f4450616 1826 case 1:
d96aa640
RJH		 1827 if (rt2x00_rt(rt2x00dev, RT3070) ||
1828 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1829 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1830 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1831 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1832 EEPROM_NIC_CONF1, &eeprom);
1833 if (rt2x00_get_field16(eeprom,
1834 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1835 rt2800_set_ant_diversity(rt2x00dev,
1836 rt2x00dev->default_ant.rx);
1837 }
f4450616
BZ		 1838 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1839 break;
1840 case 2:
872834df 1841 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1842 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1843 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1844 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
57fbcce3 1845 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
872834df
GW		 1846 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1847 } else {
1848 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1849 }
f4450616
BZ		 1850 break;
1851 case 3:
1852 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1853 break;
1854 }
1855
1856 rt2800_bbp_write(rt2x00dev, 3, r3);
1857 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1858
1859 if (rt2x00_rt(rt2x00dev, RT3593)) {
1860 if (ant->rx_chain_num == 1)
1861 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1862 else
1863 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1864 }
f4450616
BZ		 1865}
1866EXPORT_SYMBOL_GPL(rt2800_config_ant);
1867
1868static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1869 struct rt2x00lib_conf *libconf)
1870{
1871 u16 eeprom;
1872 short lna_gain;
1873
1874 if (libconf->rf.channel <= 14) {
3e38d3da 1875 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1876 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1877 } else if (libconf->rf.channel <= 64) {
3e38d3da 1878 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1879 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1880 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1881 if (rt2x00_rt(rt2x00dev, RT3593)) {
1882 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1883 lna_gain = rt2x00_get_field16(eeprom,
1884 EEPROM_EXT_LNA2_A1);
1885 } else {
1886 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1887 lna_gain = rt2x00_get_field16(eeprom,
1888 EEPROM_RSSI_BG2_LNA_A1);
1889 }
f4450616 1890 } else {
f36bb0ca
GJ		 1891 if (rt2x00_rt(rt2x00dev, RT3593)) {
1892 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1893 lna_gain = rt2x00_get_field16(eeprom,
1894 EEPROM_EXT_LNA2_A2);
1895 } else {
1896 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1897 lna_gain = rt2x00_get_field16(eeprom,
1898 EEPROM_RSSI_A2_LNA_A2);
1899 }
f4450616
BZ		 1900 }
1901
1902 rt2x00dev->lna_gain = lna_gain;
1903}
1904
3f1b8739
GJ		 1905#define FREQ_OFFSET_BOUND 0x5f
1906
1907static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1908{
1909 u8 freq_offset, prev_freq_offset;
1910 u8 rfcsr, prev_rfcsr;
1911
1912 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1913 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1914
1915 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1916 prev_rfcsr = rfcsr;
1917
1918 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1919 if (rfcsr == prev_rfcsr)
1920 return;
1921
1922 if (rt2x00_is_usb(rt2x00dev)) {
1923 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1924 freq_offset, prev_rfcsr);
1925 return;
1926 }
1927
1928 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1929 while (prev_freq_offset != freq_offset) {
1930 if (prev_freq_offset < freq_offset)
1931 prev_freq_offset++;
1932 else
1933 prev_freq_offset--;
1934
1935 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1936 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1937
1938 usleep_range(1000, 1500);
1939 }
1940}
1941
06855ef4
GW		 1942static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1943 struct ieee80211_conf *conf,
1944 struct rf_channel *rf,
1945 struct channel_info *info)
f4450616
BZ		 1946{
1947 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1948
d96aa640 1949 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1950 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1951
d96aa640 1952 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1953 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1954 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1955 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1956 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1957
1958 if (rf->channel > 14) {
1959 /*
1960 * When TX power is below 0, we should increase it by 7 to
25985edc 1961 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1962 * However this means that values between 0 and 7 have
1963 * double meaning, and we should set a 7DBm boost flag.
1964 */
1965 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1966 (info->default_power1 >= 0));
f4450616 1967
8d1331b3
ID		 1968 if (info->default_power1 < 0)
1969 info->default_power1 += 7;
f4450616 1970
8d1331b3 1971 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1972
1973 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1974 (info->default_power2 >= 0));
f4450616 1975
8d1331b3
ID		 1976 if (info->default_power2 < 0)
1977 info->default_power2 += 7;
f4450616 1978
8d1331b3 1979 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1980 } else {
8d1331b3
ID		 1981 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1982 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1983 }
1984
1985 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1986
1987 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1988 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1989 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1990 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1991
1992 udelay(200);
1993
1994 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1995 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1996 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1997 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1998
1999 udelay(200);
2000
2001 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2002 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2003 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2004 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2005}
2006
06855ef4
GW		 2007static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2008 struct ieee80211_conf *conf,
2009 struct rf_channel *rf,
2010 struct channel_info *info)
f4450616 2011{
3a1c0128 2012 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2013 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2014
2015 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2016
2017 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2018 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2019 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2020
2021 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2022 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2023 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2024
2025 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2026 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2027 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2028
5a673964 2029 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2030 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2031 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2032
2033 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2034 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2035 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2036 rt2x00dev->default_ant.rx_chain_num <= 1);
2037 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2038 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2039 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2040 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2041 rt2x00dev->default_ant.tx_chain_num <= 1);
2042 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2043 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2044 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2045
f4450616
BZ		 2046 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2047 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2048 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2049
f1f12f98
SG		 2050 if (rt2x00_rt(rt2x00dev, RT3390)) {
2051 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2052 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2053 } else {
3a1c0128
GW		 2054 if (conf_is_ht40(conf)) {
2055 calib_tx = drv_data->calibration_bw40;
2056 calib_rx = drv_data->calibration_bw40;
2057 } else {
2058 calib_tx = drv_data->calibration_bw20;
2059 calib_rx = drv_data->calibration_bw20;
2060 }
f1f12f98
SG		 2061 }
2062
2063 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2064 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2065 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2066
2067 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2068 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2069 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2070
71976907 2071 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2072 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2073 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2074
2075 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2076 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2077 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2078 msleep(1);
2079 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2080 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2081}
2082
872834df
GW		 2083static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2084 struct ieee80211_conf *conf,
2085 struct rf_channel *rf,
2086 struct channel_info *info)
2087{
3a1c0128 2088 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2089 u8 rfcsr;
2090 u32 reg;
2091
2092 if (rf->channel <= 14) {
5d137dff
GW		 2093 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2094 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2095 } else {
2096 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2097 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2098 }
2099
2100 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2101 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2102
2103 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2104 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2105 if (rf->channel <= 14)
2106 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2107 else
2108 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2109 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2110
2111 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2112 if (rf->channel <= 14)
2113 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2114 else
2115 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2116 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2117
2118 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2119 if (rf->channel <= 14) {
2120 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2121 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2122 info->default_power1);
872834df
GW		 2123 } else {
2124 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2125 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2126 (info->default_power1 & 0x3) |
2127 ((info->default_power1 & 0xC) << 1));
2128 }
2129 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2130
2131 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2132 if (rf->channel <= 14) {
2133 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2134 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2135 info->default_power2);
872834df
GW		 2136 } else {
2137 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2138 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2139 (info->default_power2 & 0x3) |
2140 ((info->default_power2 & 0xC) << 1));
2141 }
2142 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2143
2144 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2145 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2146 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2147 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2148 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2149 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2150 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2151 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2152 if (rf->channel <= 14) {
2153 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2154 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2155 }
2156 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2157 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2158 } else {
2159 switch (rt2x00dev->default_ant.tx_chain_num) {
2160 case 1:
2161 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2162 case 2:
2163 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2164 break;
2165 }
2166
2167 switch (rt2x00dev->default_ant.rx_chain_num) {
2168 case 1:
2169 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2170 case 2:
2171 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2172 break;
2173 }
2174 }
2175 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2176
2177 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2178 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2179 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2180
3a1c0128
GW		 2181 if (conf_is_ht40(conf)) {
2182 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2183 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2184 } else {
2185 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2186 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2187 }
872834df
GW		 2188
2189 if (rf->channel <= 14) {
2190 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2191 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2192 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2193 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2194 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2195 rfcsr = 0x4c;
2196 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2197 drv_data->txmixer_gain_24g);
2198 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2199 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2200 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2201 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2202 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2203 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2204 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2205 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2206 } else {
58b8ae14
GW		 2207 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2208 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2209 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2210 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2211 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2212 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2213 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2214 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2215 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2216 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2217 rfcsr = 0x7a;
2218 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2219 drv_data->txmixer_gain_5g);
2220 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2221 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2222 if (rf->channel <= 64) {
2223 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2224 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2225 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2226 } else if (rf->channel <= 128) {
2227 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2228 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2229 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2230 } else {
2231 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2232 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2233 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2234 }
2235 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2236 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2237 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2238 }
2239
99bdf51a
GW		 2240 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2241 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2242 if (rf->channel <= 14)
99bdf51a 2243 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2244 else
99bdf51a
GW		 2245 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2246 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2247
2248 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2249 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2250 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2251}
60687ba7 2252
f42b0465
GJ		 2253static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2254 struct ieee80211_conf *conf,
2255 struct rf_channel *rf,
2256 struct channel_info *info)
2257{
2258 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2259 u8 txrx_agc_fc;
2260 u8 txrx_h20m;
2261 u8 rfcsr;
2262 u8 bbp;
2263 const bool txbf_enabled = false; /* TODO */
2264
2265 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2266 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2267 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2268 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2269 rt2800_bbp_write(rt2x00dev, 109, bbp);
2270
2271 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2272 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2273 rt2800_bbp_write(rt2x00dev, 110, bbp);
2274
2275 if (rf->channel <= 14) {
2276 /* Restore BBP 25 & 26 for 2.4 GHz */
2277 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2278 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2279 } else {
2280 /* Hard code BBP 25 & 26 for 5GHz */
2281
2282 /* Enable IQ Phase correction */
2283 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2284 /* Setup IQ Phase correction value */
2285 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2286 }
2287
2288 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2289 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2290
2291 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2292 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2293 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2294
2295 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2296 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2297 if (rf->channel <= 14)
2298 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2299 else
2300 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2301 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2302
2303 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2304 if (rf->channel <= 14) {
2305 rfcsr = 0;
2306 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2307 info->default_power1 & 0x1f);
2308 } else {
2309 if (rt2x00_is_usb(rt2x00dev))
2310 rfcsr = 0x40;
2311
2312 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2313 ((info->default_power1 & 0x18) << 1) |
2314 (info->default_power1 & 7));
2315 }
2316 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2317
2318 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2319 if (rf->channel <= 14) {
2320 rfcsr = 0;
2321 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2322 info->default_power2 & 0x1f);
2323 } else {
2324 if (rt2x00_is_usb(rt2x00dev))
2325 rfcsr = 0x40;
2326
2327 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2328 ((info->default_power2 & 0x18) << 1) |
2329 (info->default_power2 & 7));
2330 }
2331 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2332
2333 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2334 if (rf->channel <= 14) {
2335 rfcsr = 0;
2336 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2337 info->default_power3 & 0x1f);
2338 } else {
2339 if (rt2x00_is_usb(rt2x00dev))
2340 rfcsr = 0x40;
2341
2342 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2343 ((info->default_power3 & 0x18) << 1) |
2344 (info->default_power3 & 7));
2345 }
2346 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2347
2348 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2349 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2350 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2351 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2352 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2353 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2354 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2355 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2356 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2357
2358 switch (rt2x00dev->default_ant.tx_chain_num) {
2359 case 3:
2360 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2361 /* fallthrough */
2362 case 2:
2363 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2364 /* fallthrough */
2365 case 1:
2366 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2367 break;
2368 }
2369
2370 switch (rt2x00dev->default_ant.rx_chain_num) {
2371 case 3:
2372 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2373 /* fallthrough */
2374 case 2:
2375 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2376 /* fallthrough */
2377 case 1:
2378 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2379 break;
2380 }
2381 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2382
e979a8ab 2383 rt2800_adjust_freq_offset(rt2x00dev);
f42b0465
GJ		 2384
2385 if (conf_is_ht40(conf)) {
2386 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2387 RFCSR24_TX_AGC_FC);
2388 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2389 RFCSR24_TX_H20M);
2390 } else {
2391 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2392 RFCSR24_TX_AGC_FC);
2393 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2394 RFCSR24_TX_H20M);
2395 }
2396
2397 /* NOTE: the reference driver does not writes the new value
2398 * back to RFCSR 32
2399 */
2400 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2401 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2402
2403 if (rf->channel <= 14)
2404 rfcsr = 0xa0;
2405 else
2406 rfcsr = 0x80;
2407 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2408
2409 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2410 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2411 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2412 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2413
2414 /* Band selection */
2415 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2416 if (rf->channel <= 14)
2417 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2418 else
2419 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2420 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2421
2422 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2423 if (rf->channel <= 14)
2424 rfcsr = 0x3c;
2425 else
2426 rfcsr = 0x20;
2427 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2428
2429 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2430 if (rf->channel <= 14)
2431 rfcsr = 0x1a;
2432 else
2433 rfcsr = 0x12;
2434 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2435
2436 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2437 if (rf->channel >= 1 && rf->channel <= 14)
2438 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2439 else if (rf->channel >= 36 && rf->channel <= 64)
2440 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2441 else if (rf->channel >= 100 && rf->channel <= 128)
2442 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2443 else
2444 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2445 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2446
2447 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2448 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2449 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2450
2451 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2452
2453 if (rf->channel <= 14) {
2454 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2455 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2456 } else {
2457 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2458 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2459 }
2460
2461 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2462 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2463 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2464
2465 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2466 if (rf->channel <= 14) {
2467 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2468 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2469 } else {
2470 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2471 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2472 }
2473 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2474
2475 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2476 if (rf->channel <= 14)
2477 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2478 else
2479 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2480
2481 if (txbf_enabled)
2482 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2483
2484 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2485
2486 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2487 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2488 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2489
2490 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2491 if (rf->channel <= 14)
2492 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2493 else
2494 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2495 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2496
2497 if (rf->channel <= 14) {
2498 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2499 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2500 } else {
2501 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2502 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2503 }
2504
2505 /* Initiate VCO calibration */
2506 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2507 if (rf->channel <= 14) {
2508 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2509 } else {
2510 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2511 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2512 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2513 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2514 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2515 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2516 }
2517 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2518
2519 if (rf->channel >= 1 && rf->channel <= 14) {
2520 rfcsr = 0x23;
2521 if (txbf_enabled)
2522 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2523 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2524
2525 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2526 } else if (rf->channel >= 36 && rf->channel <= 64) {
2527 rfcsr = 0x36;
2528 if (txbf_enabled)
2529 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2530 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2531
2532 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2533 } else if (rf->channel >= 100 && rf->channel <= 128) {
2534 rfcsr = 0x32;
2535 if (txbf_enabled)
2536 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2537 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2538
2539 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2540 } else {
2541 rfcsr = 0x30;
2542 if (txbf_enabled)
2543 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2544 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2545
2546 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2547 }
2548}
2549
7573cb5b 2550#define POWER_BOUND 0x27
8f821098 2551#define POWER_BOUND_5G 0x2b
0c9e5fb9 2552
a89534ed
WH		 2553static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2554 struct ieee80211_conf *conf,
2555 struct rf_channel *rf,
2556 struct channel_info *info)
2557{
2558 u8 rfcsr;
2559
2560 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2561 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2562 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2563 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2564 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2565
2566 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2567 if (info->default_power1 > POWER_BOUND)
2568 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2569 else
2570 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2571 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2572
0c9e5fb9 2573 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2574
2575 if (rf->channel <= 14) {
2576 if (rf->channel == 6)
2577 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2578 else
2579 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2580
2581 if (rf->channel >= 1 && rf->channel <= 6)
2582 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2583 else if (rf->channel >= 7 && rf->channel <= 11)
2584 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2585 else if (rf->channel >= 12 && rf->channel <= 14)
2586 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2587 }
2588}
2589
03839951
DG		 2590static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2591 struct ieee80211_conf *conf,
2592 struct rf_channel *rf,
2593 struct channel_info *info)
2594{
2595 u8 rfcsr;
2596
2597 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2598 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2599
2600 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2601 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2602 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2603
2604 if (info->default_power1 > POWER_BOUND)
2605 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2606 else
2607 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2608
2609 if (info->default_power2 > POWER_BOUND)
2610 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2611 else
2612 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2613
0c9e5fb9 2614 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2615
2616 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2617 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2618 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2619
2620 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2621 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2622 else
2623 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2624
2625 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2626 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2627 else
2628 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2629
2630 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2631 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2632
2633 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2634
2635 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2636}
2637
60687ba7 2638static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2639 struct ieee80211_conf *conf,
2640 struct rf_channel *rf,
2641 struct channel_info *info)
2642{
2643 u8 rfcsr;
adde5882
GJ		 2644
2645 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2646 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2647 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2648 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2649 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2650
2651 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2652 if (info->default_power1 > POWER_BOUND)
2653 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2654 else
2655 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2656 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2657
cff3d1f0
ZL		 2658 if (rt2x00_rt(rt2x00dev, RT5392)) {
2659 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2660 if (info->default_power2 > POWER_BOUND)
7573cb5b 2661 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2662 else
2663 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2664 info->default_power2);
2665 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2666 }
2667
adde5882 2668 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2669 if (rt2x00_rt(rt2x00dev, RT5392)) {
2670 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2671 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2672 }
adde5882
GJ		 2673 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2674 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2675 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2676 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2677 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2678
0c9e5fb9 2679 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2680
adde5882
GJ		 2681 if (rf->channel <= 14) {
2682 int idx = rf->channel-1;
2683
c429dfef 2684 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2685 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2686 /* r55/r59 value array of channel 1~14 */
2687 static const char r55_bt_rev[] = {0x83, 0x83,
2688 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2689 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2690 static const char r59_bt_rev[] = {0x0e, 0x0e,
2691 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2692 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2693
2694 rt2800_rfcsr_write(rt2x00dev, 55,
2695 r55_bt_rev[idx]);
2696 rt2800_rfcsr_write(rt2x00dev, 59,
2697 r59_bt_rev[idx]);
2698 } else {
2699 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2700 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2701 0x88, 0x88, 0x86, 0x85, 0x84};
2702
2703 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2704 }
2705 } else {
2706 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2707 static const char r55_nonbt_rev[] = {0x23, 0x23,
2708 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2709 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2710 static const char r59_nonbt_rev[] = {0x07, 0x07,
2711 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2712 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2713
2714 rt2800_rfcsr_write(rt2x00dev, 55,
2715 r55_nonbt_rev[idx]);
2716 rt2800_rfcsr_write(rt2x00dev, 59,
2717 r59_nonbt_rev[idx]);
2ed71884 2718 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2719 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2720 static const char r59_non_bt[] = {0x8f, 0x8f,
2721 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2722 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2723
2724 rt2800_rfcsr_write(rt2x00dev, 59,
2725 r59_non_bt[idx]);
2726 }
2727 }
2728 }
60687ba7
RST		 2729}
2730
8f821098
SG		 2731static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2732 struct ieee80211_conf *conf,
2733 struct rf_channel *rf,
2734 struct channel_info *info)
2735{
2736 u8 rfcsr, ep_reg;
d5ae7a6b 2737 u32 reg;
8f821098
SG		 2738 int power_bound;
2739
2740 /* TODO */
2741 const bool is_11b = false;
2742 const bool is_type_ep = false;
2743
d5ae7a6b
SG		 2744 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2745 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2746 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2747 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2748
2749 /* Order of values on rf_channel entry: N, K, mod, R */
2750 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2751
2752 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2753 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2754 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2755 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2756 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2757
2758 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2759 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2760 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2761 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2762
2763 if (rf->channel <= 14) {
2764 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2765 /* FIXME: RF11 owerwrite ? */
2766 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2767 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2768 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2769 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2770 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2771 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2772 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2773 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2774 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2775 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2776 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2777 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2778 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2779 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2780 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2781 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2782 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2783 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2784 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2785 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2786 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2787 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2788 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2789 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2790 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2791 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2792 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2793 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2794
2795 /* TODO RF27 <- tssi */
2796
2797 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2798 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2799 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2800
2801 if (is_11b) {
2802 /* CCK */
2803 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2804 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2805 if (is_type_ep)
2806 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2807 else
2808 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2809 } else {
2810 /* OFDM */
2811 if (is_type_ep)
2812 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2813 else
2814 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2815 }
2816
2817 power_bound = POWER_BOUND;
2818 ep_reg = 0x2;
2819 } else {
2820 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2821 /* FIMXE: RF11 overwrite */
2822 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2823 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2824 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2825 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2826 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2827 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2828 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2829 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2830 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2831 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2832 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2833 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2834 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2835 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2836
2837 /* TODO RF27 <- tssi */
2838
2839 if (rf->channel >= 36 && rf->channel <= 64) {
2840
2841 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2842 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2843 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2844 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2845 if (rf->channel <= 50)
2846 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2847 else if (rf->channel >= 52)
2848 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2849 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2850 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2851 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2852 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2853 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2854 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2855 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2856 if (rf->channel <= 50) {
2857 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2858 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2859 } else if (rf->channel >= 52) {
2860 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2861 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2862 }
2863
2864 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2865 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2866 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2867
2868 } else if (rf->channel >= 100 && rf->channel <= 165) {
2869
2870 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2871 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2872 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2873 if (rf->channel <= 153) {
2874 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2875 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2876 } else if (rf->channel >= 155) {
2877 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2878 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2879 }
2880 if (rf->channel <= 138) {
2881 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2882 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2883 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2884 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2885 } else if (rf->channel >= 140) {
2886 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2887 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2888 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2889 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2890 }
2891 if (rf->channel <= 124)
2892 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2893 else if (rf->channel >= 126)
2894 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2895 if (rf->channel <= 138)
2896 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2897 else if (rf->channel >= 140)
2898 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2899 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2900 if (rf->channel <= 138)
2901 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2902 else if (rf->channel >= 140)
2903 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2904 if (rf->channel <= 128)
2905 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2906 else if (rf->channel >= 130)
2907 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2908 if (rf->channel <= 116)
2909 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2910 else if (rf->channel >= 118)
2911 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2912 if (rf->channel <= 138)
2913 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2914 else if (rf->channel >= 140)
2915 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2916 if (rf->channel <= 116)
2917 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2918 else if (rf->channel >= 118)
2919 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2920 }
2921
2922 power_bound = POWER_BOUND_5G;
2923 ep_reg = 0x3;
2924 }
2925
2926 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2927 if (info->default_power1 > power_bound)
2928 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2929 else
2930 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2931 if (is_type_ep)
2932 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2933 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2934
2935 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2936 if (info->default_power2 > power_bound)
8f821098
SG		 2937 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2938 else
2939 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2940 if (is_type_ep)
2941 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2942 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2943
2944 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2945 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2946 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2947
2948 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2949 rt2x00dev->default_ant.tx_chain_num >= 1);
2950 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2951 rt2x00dev->default_ant.tx_chain_num == 2);
2952 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2953
2954 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2955 rt2x00dev->default_ant.rx_chain_num >= 1);
2956 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2957 rt2x00dev->default_ant.rx_chain_num == 2);
2958 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2959
2960 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2961 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2962
2963 if (conf_is_ht40(conf))
2964 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2965 else
2966 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2967
2968 if (!is_11b) {
2969 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2970 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2971 }
2972
2973 /* TODO proper frequency adjustment */
0c9e5fb9 2974 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2975
2976 /* TODO merge with others */
2977 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2978 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2979 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2980
2981 /* BBP settings */
2982 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2983 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2984 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2985
2986 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2987 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2988 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2989 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2990
2991 /* GLRT band configuration */
2992 rt2800_bbp_write(rt2x00dev, 195, 128);
2993 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2994 rt2800_bbp_write(rt2x00dev, 195, 129);
2995 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2996 rt2800_bbp_write(rt2x00dev, 195, 130);
2997 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2998 rt2800_bbp_write(rt2x00dev, 195, 131);
2999 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3000 rt2800_bbp_write(rt2x00dev, 195, 133);
3001 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3002 rt2800_bbp_write(rt2x00dev, 195, 124);
3003 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3004}
3005
5bc2dd06
SG		 3006static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3007 const unsigned int word,
3008 const u8 value)
3009{
3010 u8 chain, reg;
3011
3012 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3013 rt2800_bbp_read(rt2x00dev, 27, &reg);
3014 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3015 rt2800_bbp_write(rt2x00dev, 27, reg);
3016
3017 rt2800_bbp_write(rt2x00dev, word, value);
3018 }
3019}
3020
8756130b
SG		 3021static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3022{
3023 u8 cal;
3024
415e3f2f 3025 /* TX0 IQ Gain */
8756130b 3026 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3027 if (channel <= 14)
3028 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3029 else if (channel >= 36 && channel <= 64)
3030 cal = rt2x00_eeprom_byte(rt2x00dev,
3031 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3032 else if (channel >= 100 && channel <= 138)
3033 cal = rt2x00_eeprom_byte(rt2x00dev,
3034 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3035 else if (channel >= 140 && channel <= 165)
3036 cal = rt2x00_eeprom_byte(rt2x00dev,
3037 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3038 else
3039 cal = 0;
8756130b
SG		 3040 rt2800_bbp_write(rt2x00dev, 159, cal);
3041
415e3f2f 3042 /* TX0 IQ Phase */
8756130b 3043 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3044 if (channel <= 14)
3045 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3046 else if (channel >= 36 && channel <= 64)
3047 cal = rt2x00_eeprom_byte(rt2x00dev,
3048 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3049 else if (channel >= 100 && channel <= 138)
3050 cal = rt2x00_eeprom_byte(rt2x00dev,
3051 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3052 else if (channel >= 140 && channel <= 165)
3053 cal = rt2x00_eeprom_byte(rt2x00dev,
3054 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3055 else
3056 cal = 0;
8756130b
SG		 3057 rt2800_bbp_write(rt2x00dev, 159, cal);
3058
415e3f2f 3059 /* TX1 IQ Gain */
8756130b 3060 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3061 if (channel <= 14)
3062 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3063 else if (channel >= 36 && channel <= 64)
3064 cal = rt2x00_eeprom_byte(rt2x00dev,
3065 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3066 else if (channel >= 100 && channel <= 138)
3067 cal = rt2x00_eeprom_byte(rt2x00dev,
3068 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3069 else if (channel >= 140 && channel <= 165)
3070 cal = rt2x00_eeprom_byte(rt2x00dev,
3071 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3072 else
3073 cal = 0;
8756130b
SG		 3074 rt2800_bbp_write(rt2x00dev, 159, cal);
3075
415e3f2f 3076 /* TX1 IQ Phase */
8756130b 3077 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3078 if (channel <= 14)
3079 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3080 else if (channel >= 36 && channel <= 64)
3081 cal = rt2x00_eeprom_byte(rt2x00dev,
3082 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3083 else if (channel >= 100 && channel <= 138)
3084 cal = rt2x00_eeprom_byte(rt2x00dev,
3085 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3086 else if (channel >= 140 && channel <= 165)
3087 cal = rt2x00_eeprom_byte(rt2x00dev,
3088 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3089 else
3090 cal = 0;
8756130b
SG		 3091 rt2800_bbp_write(rt2x00dev, 159, cal);
3092
415e3f2f
SG		 3093 /* FIXME: possible RX0, RX1 callibration ? */
3094
8756130b
SG		 3095 /* RF IQ compensation control */
3096 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3097 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3098 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3099
3100 /* RF IQ imbalance compensation control */
3101 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3102 cal = rt2x00_eeprom_byte(rt2x00dev,
3103 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3104 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3105}
3106
97aa03f1
GJ		 3107static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3108 unsigned int channel,
3109 char txpower)
3110{
fc739cfe
GJ		 3111 if (rt2x00_rt(rt2x00dev, RT3593))
3112 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3113
97aa03f1
GJ		 3114 if (channel <= 14)
3115 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3116
3117 if (rt2x00_rt(rt2x00dev, RT3593))
3118 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3119 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3120 else
3121 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3122}
3123
f4450616
BZ		 3124static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3125 struct ieee80211_conf *conf,
3126 struct rf_channel *rf,
3127 struct channel_info *info)
3128{
3129 u32 reg;
3130 unsigned int tx_pin;
a89534ed 3131 u8 bbp, rfcsr;
f4450616 3132
97aa03f1
GJ		 3133 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3134 info->default_power1);
3135 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3136 info->default_power2);
c0a14369
GJ		 3137 if (rt2x00dev->default_ant.tx_chain_num > 2)
3138 info->default_power3 =
3139 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3140 info->default_power3);
46323e11 3141
5aa57015
GW		 3142 switch (rt2x00dev->chip.rf) {
3143 case RF2020:
3144 case RF3020:
3145 case RF3021:
3146 case RF3022:
3147 case RF3320:
06855ef4 3148 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3149 break;
3150 case RF3052:
872834df 3151 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3152 break;
f42b0465
GJ		 3153 case RF3053:
3154 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3155 break;
a89534ed
WH		 3156 case RF3290:
3157 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3158 break;
03839951
DG		 3159 case RF3322:
3160 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3161 break;
3b9b74ba 3162 case RF3070:
ccf91bd6 3163 case RF5360:
ac0372ab 3164 case RF5362:
5aa57015 3165 case RF5370:
2ed71884 3166 case RF5372:
5aa57015 3167 case RF5390:
cff3d1f0 3168 case RF5392:
adde5882 3169 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3170 break;
8f821098
SG		 3171 case RF5592:
3172 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3173 break;
5aa57015 3174 default:
06855ef4 3175 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3176 }
f4450616 3177
3b9b74ba
SG		 3178 if (rt2x00_rf(rt2x00dev, RF3070) ||
3179 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3180 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed 3181 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3182 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3183 rt2x00_rf(rt2x00dev, RF5370) ||
3184 rt2x00_rf(rt2x00dev, RF5372) ||
3185 rt2x00_rf(rt2x00dev, RF5390) ||
3186 rt2x00_rf(rt2x00dev, RF5392)) {
3187 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3188 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3189 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3190 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3191
3192 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3193 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3194 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3195 }
3196
f4450616
BZ		 3197 /*
3198 * Change BBP settings
3199 */
03839951
DG		 3200 if (rt2x00_rt(rt2x00dev, RT3352)) {
3201 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3202 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3203 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3204 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3205 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3206 if (rf->channel > 14) {
3207 /* Disable CCK Packet detection on 5GHz */
3208 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3209 } else {
3210 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3211 }
3212
3213 if (conf_is_ht40(conf))
3214 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3215 else
3216 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3217
3218 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3219 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3220 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3221 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3222 } else {
3223 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3224 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3225 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3226 rt2800_bbp_write(rt2x00dev, 86, 0);
3227 }
f4450616
BZ		 3228
3229 if (rf->channel <= 14) {
2ed71884 3230 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3231 !rt2x00_rt(rt2x00dev, RT5392)) {
c429dfef 3232 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3233 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3234 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3235 } else {
f42b0465
GJ		 3236 if (rt2x00_rt(rt2x00dev, RT3593))
3237 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3238 else
3239 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3240 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3241 }
f42b0465
GJ		 3242 if (rt2x00_rt(rt2x00dev, RT3593))
3243 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3244 }
f42b0465 3245
f4450616 3246 } else {
872834df
GW		 3247 if (rt2x00_rt(rt2x00dev, RT3572))
3248 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3249 else if (rt2x00_rt(rt2x00dev, RT3593))
3250 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3251 else
3252 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3253
f42b0465
GJ		 3254 if (rt2x00_rt(rt2x00dev, RT3593))
3255 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3256
c429dfef 3257 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3258 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3259 else
3260 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3261 }
3262
3263 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3264 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3265 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3266 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3267 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3268
872834df
GW		 3269 if (rt2x00_rt(rt2x00dev, RT3572))
3270 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3271
f4450616
BZ		 3272 tx_pin = 0;
3273
bb16d488
GJ		 3274 switch (rt2x00dev->default_ant.tx_chain_num) {
3275 case 3:
3276 /* Turn on tertiary PAs */
3277 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3278 rf->channel > 14);
3279 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3280 rf->channel <= 14);
3281 /* fall-through */
3282 case 2:
3283 /* Turn on secondary PAs */
65f31b5e
GW		 3284 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3285 rf->channel > 14);
3286 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3287 rf->channel <= 14);
bb16d488
GJ		 3288 /* fall-through */
3289 case 1:
3290 /* Turn on primary PAs */
3291 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3292 rf->channel > 14);
c429dfef 3293 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3294 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3295 else
3296 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3297 rf->channel <= 14);
3298 break;
f4450616
BZ		 3299 }
3300
bb16d488
GJ		 3301 switch (rt2x00dev->default_ant.rx_chain_num) {
3302 case 3:
3303 /* Turn on tertiary LNAs */
3304 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3305 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3306 /* fall-through */
3307 case 2:
3308 /* Turn on secondary LNAs */
f4450616
BZ		 3309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3310 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3311 /* fall-through */
3312 case 1:
3313 /* Turn on primary LNAs */
3314 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3315 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3316 break;
f4450616
BZ		 3317 }
3318
f4450616
BZ		 3319 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3320 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3321
3322 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3323
733aec6a 3324 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3325 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3326
733aec6a
GJ		 3327 /* AGC init */
3328 if (rf->channel <= 14)
3329 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3330 else
3331 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3332
3333 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3334 }
3335
f42b0465 3336 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3337 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3338
60751001
GJ		 3339 /* Band selection */
3340 if (rt2x00_is_usb(rt2x00dev) ||
3341 rt2x00_is_pcie(rt2x00dev)) {
3342 /* GPIO #8 controls all paths */
f42b0465
GJ		 3343 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3344 if (rf->channel <= 14)
3345 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3346 else
3347 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3348 }
f42b0465 3349
60751001
GJ		 3350 /* LNA PE control. */
3351 if (rt2x00_is_usb(rt2x00dev)) {
3352 /* GPIO #4 controls PE0 and PE1,
3353 * GPIO #7 controls PE2
3354 */
f42b0465
GJ		 3355 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3356 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3357
f42b0465
GJ		 3358 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3359 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3360 } else if (rt2x00_is_pcie(rt2x00dev)) {
3361 /* GPIO #4 controls PE0, PE1 and PE2 */
3362 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3363 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3364 }
3365
60751001
GJ		 3366 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3367
f42b0465
GJ		 3368 /* AGC init */
3369 if (rf->channel <= 14)
3370 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3371 else
3372 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3373
3374 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3375
3376 usleep_range(1000, 1500);
3377 }
3378
6803141b
SG		 3379 if (rt2x00_rt(rt2x00dev, RT5592)) {
3380 rt2800_bbp_write(rt2x00dev, 195, 141);
3381 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3382
8ba0ebf3
SG		 3383 /* AGC init */
3384 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3385 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3386
8756130b 3387 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3388 }
3389
f4450616
BZ		 3390 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3391 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3392 rt2800_bbp_write(rt2x00dev, 4, bbp);
3393
3394 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3395 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3396 rt2800_bbp_write(rt2x00dev, 3, bbp);
3397
8d0c9b65 3398 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3399 if (conf_is_ht40(conf)) {
3400 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3401 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3402 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3403 } else {
3404 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3405 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3406 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3407 }
3408 }
3409
3410 msleep(1);
977206d7
HS		 3411
3412 /*
3413 * Clear channel statistic counters
3414 */
3415 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3416 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3417 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3418
3419 /*
3420 * Clear update flag
3421 */
3422 if (rt2x00_rt(rt2x00dev, RT3352)) {
3423 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3424 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3425 rt2800_bbp_write(rt2x00dev, 49, bbp);
3426 }
f4450616
BZ		 3427}
3428
9e33a355
HS		 3429static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3430{
3431 u8 tssi_bounds[9];
3432 u8 current_tssi;
3433 u16 eeprom;
3434 u8 step;
3435 int i;
3436
6e956da2
SG		 3437 /*
3438 * First check if temperature compensation is supported.
3439 */
3440 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3441 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3442 return 0;
3443
9e33a355
HS		 3444 /*
3445 * Read TSSI boundaries for temperature compensation from
3446 * the EEPROM.
3447 *
3448 * Array idx 0 1 2 3 4 5 6 7 8
3449 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3450 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3451 */
57fbcce3 3452 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3e38d3da 3453 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3454 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3455 EEPROM_TSSI_BOUND_BG1_MINUS4);
3456 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3457 EEPROM_TSSI_BOUND_BG1_MINUS3);
3458
3e38d3da 3459 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3460 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3461 EEPROM_TSSI_BOUND_BG2_MINUS2);
3462 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3463 EEPROM_TSSI_BOUND_BG2_MINUS1);
3464
3e38d3da 3465 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3466 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3467 EEPROM_TSSI_BOUND_BG3_REF);
3468 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3469 EEPROM_TSSI_BOUND_BG3_PLUS1);
3470
3e38d3da 3471 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3472 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3473 EEPROM_TSSI_BOUND_BG4_PLUS2);
3474 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3475 EEPROM_TSSI_BOUND_BG4_PLUS3);
3476
3e38d3da 3477 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3478 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3479 EEPROM_TSSI_BOUND_BG5_PLUS4);
3480
3481 step = rt2x00_get_field16(eeprom,
3482 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3483 } else {
3e38d3da 3484 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3485 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3486 EEPROM_TSSI_BOUND_A1_MINUS4);
3487 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3488 EEPROM_TSSI_BOUND_A1_MINUS3);
3489
3e38d3da 3490 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3491 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3492 EEPROM_TSSI_BOUND_A2_MINUS2);
3493 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3494 EEPROM_TSSI_BOUND_A2_MINUS1);
3495
3e38d3da 3496 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3497 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3498 EEPROM_TSSI_BOUND_A3_REF);
3499 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3500 EEPROM_TSSI_BOUND_A3_PLUS1);
3501
3e38d3da 3502 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3503 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3504 EEPROM_TSSI_BOUND_A4_PLUS2);
3505 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3506 EEPROM_TSSI_BOUND_A4_PLUS3);
3507
3e38d3da 3508 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3509 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3510 EEPROM_TSSI_BOUND_A5_PLUS4);
3511
3512 step = rt2x00_get_field16(eeprom,
3513 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3514 }
3515
3516 /*
3517 * Check if temperature compensation is supported.
3518 */
bf7e1abe 3519 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3520 return 0;
3521
3522 /*
3523 * Read current TSSI (BBP 49).
3524 */
3525 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3526
3527 /*
3528 * Compare TSSI value (BBP49) with the compensation boundaries
3529 * from the EEPROM and increase or decrease tx power.
3530 */
3531 for (i = 0; i <= 3; i++) {
3532 if (current_tssi > tssi_bounds[i])
3533 break;
3534 }
3535
3536 if (i == 4) {
3537 for (i = 8; i >= 5; i--) {
3538 if (current_tssi < tssi_bounds[i])
3539 break;
3540 }
3541 }
3542
3543 return (i - 4) * step;
3544}
3545
e90c54b2 3546static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
57fbcce3 3547 enum nl80211_band band)
e90c54b2
RJH		 3548{
3549 u16 eeprom;
3550 u8 comp_en;
3551 u8 comp_type;
75faae8b 3552 int comp_value = 0;
e90c54b2 3553
3e38d3da 3554 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3555
75faae8b
HS		 3556 /*
3557 * HT40 compensation not required.
3558 */
3559 if (eeprom == 0xffff ||
3560 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3561 return 0;
3562
57fbcce3 3563 if (band == NL80211_BAND_2GHZ) {
e90c54b2
RJH		 3564 comp_en = rt2x00_get_field16(eeprom,
3565 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3566 if (comp_en) {
3567 comp_type = rt2x00_get_field16(eeprom,
3568 EEPROM_TXPOWER_DELTA_TYPE_2G);
3569 comp_value = rt2x00_get_field16(eeprom,
3570 EEPROM_TXPOWER_DELTA_VALUE_2G);
3571 if (!comp_type)
3572 comp_value = -comp_value;
3573 }
3574 } else {
3575 comp_en = rt2x00_get_field16(eeprom,
3576 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3577 if (comp_en) {
3578 comp_type = rt2x00_get_field16(eeprom,
3579 EEPROM_TXPOWER_DELTA_TYPE_5G);
3580 comp_value = rt2x00_get_field16(eeprom,
3581 EEPROM_TXPOWER_DELTA_VALUE_5G);
3582 if (!comp_type)
3583 comp_value = -comp_value;
3584 }
3585 }
3586
3587 return comp_value;
3588}
3589
1e4cf249
SG		 3590static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3591 int power_level, int max_power)
3592{
3593 int delta;
3594
c429dfef 3595 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 3596 return 0;
3597
3598 /*
3599 * XXX: We don't know the maximum transmit power of our hardware since
3600 * the EEPROM doesn't expose it. We only know that we are calibrated
3601 * to 100% tx power.
3602 *
3603 * Hence, we assume the regulatory limit that cfg80211 calulated for
3604 * the current channel is our maximum and if we are requested to lower
3605 * the value we just reduce our tx power accordingly.
3606 */
3607 delta = power_level - max_power;
3608 return min(delta, 0);
3609}
3610
fa71a160 3611static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
57fbcce3 3612 enum nl80211_band band, int power_level,
fa71a160 3613 u8 txpower, int delta)
e90c54b2 3614{
e90c54b2
RJH		 3615 u16 eeprom;
3616 u8 criterion;
3617 u8 eirp_txpower;
3618 u8 eirp_txpower_criterion;
3619 u8 reg_limit;
e90c54b2 3620
34542ff5
GJ		 3621 if (rt2x00_rt(rt2x00dev, RT3593))
3622 return min_t(u8, txpower, 0xc);
3623
c429dfef 3624 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 3625 /*
3626 * Check if eirp txpower exceed txpower_limit.
3627 * We use OFDM 6M as criterion and its eirp txpower
3628 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3629 * .11b data rate need add additional 4dbm
3630 * when calculating eirp txpower.
3631 */
022138ca
GJ		 3632 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3633 1, &eeprom);
d9bceaeb
SG		 3634 criterion = rt2x00_get_field16(eeprom,
3635 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3636
3e38d3da 3637 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3638 &eeprom);
e90c54b2 3639
57fbcce3 3640 if (band == NL80211_BAND_2GHZ)
e90c54b2
RJH		 3641 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3642 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3643 else
3644 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3645 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3646
3647 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3648 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3649
3650 reg_limit = (eirp_txpower > power_level) ?
3651 (eirp_txpower - power_level) : 0;
3652 } else
3653 reg_limit = 0;
3654
19f3fa24
SG		 3655 txpower = max(0, txpower + delta - reg_limit);
3656 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3657}
3658
34542ff5
GJ		 3659
3660enum {
3661 TX_PWR_CFG_0_IDX,
3662 TX_PWR_CFG_1_IDX,
3663 TX_PWR_CFG_2_IDX,
3664 TX_PWR_CFG_3_IDX,
3665 TX_PWR_CFG_4_IDX,
3666 TX_PWR_CFG_5_IDX,
3667 TX_PWR_CFG_6_IDX,
3668 TX_PWR_CFG_7_IDX,
3669 TX_PWR_CFG_8_IDX,
3670 TX_PWR_CFG_9_IDX,
3671 TX_PWR_CFG_0_EXT_IDX,
3672 TX_PWR_CFG_1_EXT_IDX,
3673 TX_PWR_CFG_2_EXT_IDX,
3674 TX_PWR_CFG_3_EXT_IDX,
3675 TX_PWR_CFG_4_EXT_IDX,
3676 TX_PWR_CFG_IDX_COUNT,
3677};
3678
3679static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3680 struct ieee80211_channel *chan,
3681 int power_level)
3682{
3683 u8 txpower;
3684 u16 eeprom;
3685 u32 regs[TX_PWR_CFG_IDX_COUNT];
3686 unsigned int offset;
57fbcce3 3687 enum nl80211_band band = chan->band;
34542ff5
GJ		 3688 int delta;
3689 int i;
3690
3691 memset(regs, '\0', sizeof(regs));
3692
3693 /* TODO: adapt TX power reduction from the rt28xx code */
3694
3695 /* calculate temperature compensation delta */
3696 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3697
57fbcce3 3698 if (band == NL80211_BAND_5GHZ)
34542ff5
GJ		 3699 offset = 16;
3700 else
3701 offset = 0;
3702
3703 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3704 offset += 8;
3705
3706 /* read the next four txpower values */
3707 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3708 offset, &eeprom);
3709
3710 /* CCK 1MBS,2MBS */
3711 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3712 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3713 txpower, delta);
3714 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3715 TX_PWR_CFG_0_CCK1_CH0, txpower);
3716 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3717 TX_PWR_CFG_0_CCK1_CH1, txpower);
3718 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3719 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3720
3721 /* CCK 5.5MBS,11MBS */
3722 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3723 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3724 txpower, delta);
3725 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3726 TX_PWR_CFG_0_CCK5_CH0, txpower);
3727 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3728 TX_PWR_CFG_0_CCK5_CH1, txpower);
3729 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3730 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3731
3732 /* OFDM 6MBS,9MBS */
3733 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3734 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3735 txpower, delta);
3736 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3737 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3738 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3739 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3740 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3741 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3742
3743 /* OFDM 12MBS,18MBS */
3744 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3745 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3746 txpower, delta);
3747 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3748 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3749 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3750 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3751 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3752 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3753
3754 /* read the next four txpower values */
3755 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3756 offset + 1, &eeprom);
3757
3758 /* OFDM 24MBS,36MBS */
3759 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3760 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3761 txpower, delta);
3762 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3763 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3764 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3765 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3766 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3767 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3768
3769 /* OFDM 48MBS */
3770 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3771 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3772 txpower, delta);
3773 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3774 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3775 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3776 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3777 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3778 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3779
3780 /* OFDM 54MBS */
3781 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3782 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3783 txpower, delta);
3784 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3785 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3786 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3787 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3788 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3789 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3790
3791 /* read the next four txpower values */
3792 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3793 offset + 2, &eeprom);
3794
3795 /* MCS 0,1 */
3796 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3797 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3798 txpower, delta);
3799 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3800 TX_PWR_CFG_1_MCS0_CH0, txpower);
3801 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3802 TX_PWR_CFG_1_MCS0_CH1, txpower);
3803 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3804 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3805
3806 /* MCS 2,3 */
3807 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3808 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3809 txpower, delta);
3810 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3811 TX_PWR_CFG_1_MCS2_CH0, txpower);
3812 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3813 TX_PWR_CFG_1_MCS2_CH1, txpower);
3814 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3815 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3816
3817 /* MCS 4,5 */
3818 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3819 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3820 txpower, delta);
3821 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3822 TX_PWR_CFG_2_MCS4_CH0, txpower);
3823 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3824 TX_PWR_CFG_2_MCS4_CH1, txpower);
3825 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3826 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3827
3828 /* MCS 6 */
3829 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3830 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3831 txpower, delta);
3832 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3833 TX_PWR_CFG_2_MCS6_CH0, txpower);
3834 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3835 TX_PWR_CFG_2_MCS6_CH1, txpower);
3836 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3837 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3838
3839 /* read the next four txpower values */
3840 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3841 offset + 3, &eeprom);
3842
3843 /* MCS 7 */
3844 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3845 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3846 txpower, delta);
3847 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3848 TX_PWR_CFG_7_MCS7_CH0, txpower);
3849 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3850 TX_PWR_CFG_7_MCS7_CH1, txpower);
3851 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3852 TX_PWR_CFG_7_MCS7_CH2, txpower);
3853
3854 /* MCS 8,9 */
3855 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3856 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3857 txpower, delta);
3858 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3859 TX_PWR_CFG_2_MCS8_CH0, txpower);
3860 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3861 TX_PWR_CFG_2_MCS8_CH1, txpower);
3862 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3863 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3864
3865 /* MCS 10,11 */
3866 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3867 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3868 txpower, delta);
3869 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3870 TX_PWR_CFG_2_MCS10_CH0, txpower);
3871 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3872 TX_PWR_CFG_2_MCS10_CH1, txpower);
3873 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3874 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3875
3876 /* MCS 12,13 */
3877 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3878 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3879 txpower, delta);
3880 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3881 TX_PWR_CFG_3_MCS12_CH0, txpower);
3882 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3883 TX_PWR_CFG_3_MCS12_CH1, txpower);
3884 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3885 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3886
3887 /* read the next four txpower values */
3888 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3889 offset + 4, &eeprom);
3890
3891 /* MCS 14 */
3892 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3893 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3894 txpower, delta);
3895 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3896 TX_PWR_CFG_3_MCS14_CH0, txpower);
3897 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3898 TX_PWR_CFG_3_MCS14_CH1, txpower);
3899 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3900 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3901
3902 /* MCS 15 */
3903 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3904 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3905 txpower, delta);
3906 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3907 TX_PWR_CFG_8_MCS15_CH0, txpower);
3908 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3909 TX_PWR_CFG_8_MCS15_CH1, txpower);
3910 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3911 TX_PWR_CFG_8_MCS15_CH2, txpower);
3912
3913 /* MCS 16,17 */
3914 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3915 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3916 txpower, delta);
3917 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3918 TX_PWR_CFG_5_MCS16_CH0, txpower);
3919 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3920 TX_PWR_CFG_5_MCS16_CH1, txpower);
3921 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3922 TX_PWR_CFG_5_MCS16_CH2, txpower);
3923
3924 /* MCS 18,19 */
3925 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3926 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3927 txpower, delta);
3928 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3929 TX_PWR_CFG_5_MCS18_CH0, txpower);
3930 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3931 TX_PWR_CFG_5_MCS18_CH1, txpower);
3932 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3933 TX_PWR_CFG_5_MCS18_CH2, txpower);
3934
3935 /* read the next four txpower values */
3936 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3937 offset + 5, &eeprom);
3938
3939 /* MCS 20,21 */
3940 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3941 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3942 txpower, delta);
3943 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3944 TX_PWR_CFG_6_MCS20_CH0, txpower);
3945 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3946 TX_PWR_CFG_6_MCS20_CH1, txpower);
3947 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3948 TX_PWR_CFG_6_MCS20_CH2, txpower);
3949
3950 /* MCS 22 */
3951 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3952 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3953 txpower, delta);
3954 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3955 TX_PWR_CFG_6_MCS22_CH0, txpower);
3956 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3957 TX_PWR_CFG_6_MCS22_CH1, txpower);
3958 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3959 TX_PWR_CFG_6_MCS22_CH2, txpower);
3960
3961 /* MCS 23 */
3962 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3963 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3964 txpower, delta);
3965 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3966 TX_PWR_CFG_8_MCS23_CH0, txpower);
3967 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3968 TX_PWR_CFG_8_MCS23_CH1, txpower);
3969 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3970 TX_PWR_CFG_8_MCS23_CH2, txpower);
3971
3972 /* read the next four txpower values */
3973 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3974 offset + 6, &eeprom);
3975
3976 /* STBC, MCS 0,1 */
3977 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3978 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3979 txpower, delta);
3980 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3981 TX_PWR_CFG_3_STBC0_CH0, txpower);
3982 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3983 TX_PWR_CFG_3_STBC0_CH1, txpower);
3984 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3985 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3986
3987 /* STBC, MCS 2,3 */
3988 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3989 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3990 txpower, delta);
3991 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3992 TX_PWR_CFG_3_STBC2_CH0, txpower);
3993 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3994 TX_PWR_CFG_3_STBC2_CH1, txpower);
3995 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3996 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3997
3998 /* STBC, MCS 4,5 */
3999 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4000 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4001 txpower, delta);
4002 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4003 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4004 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4005 txpower);
4006
4007 /* STBC, MCS 6 */
4008 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4009 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4010 txpower, delta);
4011 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4012 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4013 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4014 txpower);
4015
4016 /* read the next four txpower values */
4017 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4018 offset + 7, &eeprom);
4019
4020 /* STBC, MCS 7 */
4021 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4022 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4023 txpower, delta);
4024 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4025 TX_PWR_CFG_9_STBC7_CH0, txpower);
4026 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4027 TX_PWR_CFG_9_STBC7_CH1, txpower);
4028 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4029 TX_PWR_CFG_9_STBC7_CH2, txpower);
4030
4031 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4032 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4033 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4034 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4035 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4036 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4037 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4038 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4039 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4040 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4041
4042 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4043 regs[TX_PWR_CFG_0_EXT_IDX]);
4044 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4045 regs[TX_PWR_CFG_1_EXT_IDX]);
4046 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4047 regs[TX_PWR_CFG_2_EXT_IDX]);
4048 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4049 regs[TX_PWR_CFG_3_EXT_IDX]);
4050 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4051 regs[TX_PWR_CFG_4_EXT_IDX]);
4052
4053 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4054 rt2x00_dbg(rt2x00dev,
4055 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
57fbcce3 4056 (band == NL80211_BAND_5GHZ) ? '5' : '2',
34542ff5
GJ		 4057 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4058 '4' : '2',
4059 (i > TX_PWR_CFG_9_IDX) ?
4060 (i - TX_PWR_CFG_9_IDX - 1) : i,
4061 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4062 (unsigned long) regs[i]);
4063}
4064
7a66205a
SG		 4065/*
4066 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4067 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4068 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4069 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4070 * Reference per rate transmit power values are located in the EEPROM at
4071 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4072 * current conditions (i.e. band, bandwidth, temperature, user settings).
4073 */
34542ff5
GJ		 4074static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4075 struct ieee80211_channel *chan,
4076 int power_level)
f4450616 4077{
cee2c731 4078 u8 txpower, r1;
5e846004 4079 u16 eeprom;
cee2c731
SG		 4080 u32 reg, offset;
4081 int i, is_rate_b, delta, power_ctrl;
57fbcce3 4082 enum nl80211_band band = chan->band;
2af242e1
HS		 4083
4084 /*
7a66205a
SG		 4085 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4086 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4087 */
4088 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4089
9e33a355 4090 /*
7a66205a
SG		 4091 * Calculate temperature compensation. Depends on measurement of current
4092 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4093 * to temperature or maybe other factors) is smaller or bigger than
4094 * expected. We adjust it, based on TSSI reference and boundaries values
4095 * provided in EEPROM.
9e33a355 4096 */
87dd2d76
SG		 4097 switch (rt2x00dev->chip.rt) {
4098 case RT2860:
4099 case RT2872:
4100 case RT2883:
4101 case RT3070:
4102 case RT3071:
4103 case RT3090:
4104 case RT3572:
4105 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4106 break;
4107 default:
4108 /* TODO: temperature compensation code for other chips. */
4109 break;
4110 }
f4450616 4111
1e4cf249 4112 /*
7a66205a
SG		 4113 * Decrease power according to user settings, on devices with unknown
4114 * maximum tx power. For other devices we take user power_level into
4115 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4116 */
4117 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4118 chan->max_power);
4119
5e846004 4120 /*
cee2c731
SG		 4121 * BBP_R1 controls TX power for all rates, it allow to set the following
4122 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4123 *
4124 * TODO: we do not use +6 dBm option to do not increase power beyond
4125 * regulatory limit, however this could be utilized for devices with
4126 * CAPABILITY_POWER_LIMIT.
8c8d2017 4127 */
87dd2d76
SG		 4128 if (delta <= -12) {
4129 power_ctrl = 2;
4130 delta += 12;
4131 } else if (delta <= -6) {
4132 power_ctrl = 1;
4133 delta += 6;
4134 } else {
4135 power_ctrl = 0;
cee2c731 4136 }
87dd2d76
SG		 4137 rt2800_bbp_read(rt2x00dev, 1, &r1);
4138 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4139 rt2800_bbp_write(rt2x00dev, 1, r1);
8c8d2017 4140
5e846004
HS		 4141 offset = TX_PWR_CFG_0;
4142
4143 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4144 /* just to be safe */
4145 if (offset > TX_PWR_CFG_4)
4146 break;
4147
4148 rt2800_register_read(rt2x00dev, offset, &reg);
4149
4150 /* read the next four txpower values */
022138ca
GJ		 4151 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4152 i, &eeprom);
5e846004 4153
e90c54b2
RJH		 4154 is_rate_b = i ? 0 : 1;
4155 /*
4156 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4157 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4158 * TX_PWR_CFG_4: unknown
4159 */
5e846004
HS		 4160 txpower = rt2x00_get_field16(eeprom,
4161 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4162 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4163 power_level, txpower, delta);
e90c54b2 4164 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4165
e90c54b2
RJH		 4166 /*
4167 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4168 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4169 * TX_PWR_CFG_4: unknown
4170 */
5e846004
HS		 4171 txpower = rt2x00_get_field16(eeprom,
4172 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4173 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4174 power_level, txpower, delta);
e90c54b2 4175 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4176
e90c54b2
RJH		 4177 /*
4178 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4179 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4180 * TX_PWR_CFG_4: unknown
4181 */
5e846004
HS		 4182 txpower = rt2x00_get_field16(eeprom,
4183 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4184 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4185 power_level, txpower, delta);
e90c54b2 4186 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4187
e90c54b2
RJH		 4188 /*
4189 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4190 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4191 * TX_PWR_CFG_4: unknown
4192 */
5e846004
HS		 4193 txpower = rt2x00_get_field16(eeprom,
4194 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4195 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4196 power_level, txpower, delta);
e90c54b2 4197 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4198
4199 /* read the next four txpower values */
022138ca
GJ		 4200 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4201 i + 1, &eeprom);
5e846004 4202
e90c54b2
RJH		 4203 is_rate_b = 0;
4204 /*
4205 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4206 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4207 * TX_PWR_CFG_4: unknown
4208 */
5e846004
HS		 4209 txpower = rt2x00_get_field16(eeprom,
4210 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4211 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4212 power_level, txpower, delta);
e90c54b2 4213 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4214
e90c54b2
RJH		 4215 /*
4216 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4217 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4218 * TX_PWR_CFG_4: unknown
4219 */
5e846004
HS		 4220 txpower = rt2x00_get_field16(eeprom,
4221 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4222 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4223 power_level, txpower, delta);
e90c54b2 4224 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4225
e90c54b2
RJH		 4226 /*
4227 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4228 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4229 * TX_PWR_CFG_4: unknown
4230 */
5e846004
HS		 4231 txpower = rt2x00_get_field16(eeprom,
4232 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4233 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4234 power_level, txpower, delta);
e90c54b2 4235 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4236
e90c54b2
RJH		 4237 /*
4238 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4239 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4240 * TX_PWR_CFG_4: unknown
4241 */
5e846004
HS		 4242 txpower = rt2x00_get_field16(eeprom,
4243 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4244 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4245 power_level, txpower, delta);
e90c54b2 4246 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4247
4248 rt2800_register_write(rt2x00dev, offset, reg);
4249
4250 /* next TX_PWR_CFG register */
4251 offset += 4;
4252 }
f4450616
BZ		 4253}
4254
34542ff5
GJ		 4255static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4256 struct ieee80211_channel *chan,
4257 int power_level)
4258{
4259 if (rt2x00_rt(rt2x00dev, RT3593))
4260 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4261 else
4262 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4263}
4264
9e33a355
HS		 4265void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4266{
675a0b04 4267 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4268 rt2x00dev->tx_power);
4269}
4270EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4271
2e9c43dd
JL		 4272void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4273{
4274 u32 tx_pin;
4275 u8 rfcsr;
4276
4277 /*
4278 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4279 * designed to be controlled in oscillation frequency by a voltage
4280 * input. Maybe the temperature will affect the frequency of
4281 * oscillation to be shifted. The VCO calibration will be called
4282 * periodically to adjust the frequency to be precision.
4283 */
4284
4285 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4286 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4287 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4288
4289 switch (rt2x00dev->chip.rf) {
4290 case RF2020:
4291 case RF3020:
4292 case RF3021:
4293 case RF3022:
4294 case RF3320:
4295 case RF3052:
4296 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4297 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4298 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4299 break;
1095df07 4300 case RF3053:
3b9b74ba 4301 case RF3070:
a89534ed 4302 case RF3290:
ccf91bd6 4303 case RF5360:
ac0372ab 4304 case RF5362:
2e9c43dd
JL		 4305 case RF5370:
4306 case RF5372:
4307 case RF5390:
cff3d1f0 4308 case RF5392:
2e9c43dd 4309 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4310 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4311 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4312 break;
4313 default:
4314 return;
4315 }
4316
4317 mdelay(1);
4318
4319 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4320 if (rt2x00dev->rf_channel <= 14) {
4321 switch (rt2x00dev->default_ant.tx_chain_num) {
4322 case 3:
4323 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4324 /* fall through */
4325 case 2:
4326 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4327 /* fall through */
4328 case 1:
4329 default:
4330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4331 break;
4332 }
4333 } else {
4334 switch (rt2x00dev->default_ant.tx_chain_num) {
4335 case 3:
4336 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4337 /* fall through */
4338 case 2:
4339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4340 /* fall through */
4341 case 1:
4342 default:
4343 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4344 break;
4345 }
4346 }
4347 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4348
4349}
4350EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4351
f4450616
BZ		 4352static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4353 struct rt2x00lib_conf *libconf)
4354{
4355 u32 reg;
4356
4357 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4358 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4359 libconf->conf->short_frame_max_tx_count);
4360 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4361 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4362 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4363}
4364
4365static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4366 struct rt2x00lib_conf *libconf)
4367{
4368 enum dev_state state =
4369 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4370 STATE_SLEEP : STATE_AWAKE;
4371 u32 reg;
4372
4373 if (state == STATE_SLEEP) {
4374 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4375
4376 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4377 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4378 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4379 libconf->conf->listen_interval - 1);
4380 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4381 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4382
4383 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4384 } else {
f4450616
BZ		 4385 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4386 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4387 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4388 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4389 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4390
4391 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4392 }
4393}
4394
4395void rt2800_config(struct rt2x00_dev *rt2x00dev,
4396 struct rt2x00lib_conf *libconf,
4397 const unsigned int flags)
4398{
4399 /* Always recalculate LNA gain before changing configuration */
4400 rt2800_config_lna_gain(rt2x00dev, libconf);
4401
e90c54b2 4402 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4403 rt2800_config_channel(rt2x00dev, libconf->conf,
4404 &libconf->rf, &libconf->channel);
675a0b04 4405 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4406 libconf->conf->power_level);
e90c54b2 4407 }
f4450616 4408 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4409 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4410 libconf->conf->power_level);
f4450616
BZ		 4411 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4412 rt2800_config_retry_limit(rt2x00dev, libconf);
4413 if (flags & IEEE80211_CONF_CHANGE_PS)
4414 rt2800_config_ps(rt2x00dev, libconf);
4415}
4416EXPORT_SYMBOL_GPL(rt2800_config);
4417
4418/*
4419 * Link tuning
4420 */
4421void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4422{
4423 u32 reg;
4424
4425 /*
4426 * Update FCS error count from register.
4427 */
4428 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4429 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4430}
4431EXPORT_SYMBOL_GPL(rt2800_link_stats);
4432
4433static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4434{
8c6728b0
GW		 4435 u8 vgc;
4436
57fbcce3 4437 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
d5385bfc 4438 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4439 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4440 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4441 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4442 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4443 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 4444 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 4445 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4446 rt2x00_rt(rt2x00dev, RT5392) ||
4447 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4448 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4449 else
4450 vgc = 0x2e + rt2x00dev->lna_gain;
4451 } else { /* 5GHZ band */
733aec6a 4452 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 4453 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4454 else if (rt2x00_rt(rt2x00dev, RT5592))
4455 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4456 else {
4457 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4458 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4459 else
4460 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4461 }
f4450616
BZ		 4462 }
4463
8c6728b0 4464 return vgc;
f4450616
BZ		 4465}
4466
4467static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4468 struct link_qual *qual, u8 vgc_level)
4469{
4470 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 4471 if (rt2x00_rt(rt2x00dev, RT3572) ||
4472 rt2x00_rt(rt2x00dev, RT3593)) {
4473 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4474 vgc_level);
4475 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 4476 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4477 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 4478 } else {
3d81535e 4479 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 4480 }
4481
f4450616
BZ		 4482 qual->vgc_level = vgc_level;
4483 qual->vgc_level_reg = vgc_level;
4484 }
4485}
4486
4487void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4488{
4489 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4490}
4491EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4492
4493void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4494 const u32 count)
4495{
3d81535e
SG		 4496 u8 vgc;
4497
8d0c9b65 4498 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4499 return;
e25aa82a
GJ		 4500
4501 /* When RSSI is better than a certain threshold, increase VGC
4502 * with a chip specific value in order to improve the balance
4503 * between sensibility and noise isolation.
f4450616 4504 */
3d81535e
SG		 4505
4506 vgc = rt2800_get_default_vgc(rt2x00dev);
4507
e25aa82a
GJ		 4508 switch (rt2x00dev->chip.rt) {
4509 case RT3572:
4510 case RT3593:
4511 if (qual->rssi > -65) {
57fbcce3 4512 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
e25aa82a
GJ		 4513 vgc += 0x20;
4514 else
4515 vgc += 0x10;
4516 }
4517 break;
4518
4519 case RT5592:
0beb1bbf
GJ		 4520 if (qual->rssi > -65)
4521 vgc += 0x20;
e25aa82a
GJ		 4522 break;
4523
4524 default:
0beb1bbf
GJ		 4525 if (qual->rssi > -80)
4526 vgc += 0x10;
e25aa82a 4527 break;
0beb1bbf 4528 }
3d81535e
SG		 4529
4530 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4531}
4532EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4533
4534/*
4535 * Initialization functions.
4536 */
b9a07ae9 4537static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4538{
4539 u32 reg;
d5385bfc 4540 u16 eeprom;
fcf51541 4541 unsigned int i;
e3a896b9 4542 int ret;
fcf51541 4543
f7b395e9 4544 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4545
e3a896b9
GW		 4546 ret = rt2800_drv_init_registers(rt2x00dev);
4547 if (ret)
4548 return ret;
fcf51541 4549
fcf51541
BZ		 4550 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4551 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4552
4553 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4554
4555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4556 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4558 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4559 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4560 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4561 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4562 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4563
a9dce149
GW		 4564 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4565
4566 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4567 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4568 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4569 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4570
a89534ed
WH		 4571 if (rt2x00_rt(rt2x00dev, RT3290)) {
4572 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4573 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4574 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4575 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4576 }
4577
4578 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4579 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4580 rt2x00_set_field32(&reg, LDO0_EN, 1);
4581 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4582 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4583 }
4584
4585 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4586 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4587 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4588 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4589 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4590
4591 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4592 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4593 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4594
4595 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4596 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4597 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4598 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4599 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4600 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4601
4602 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4603 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4604 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4605 }
4606
64522957 4607 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4608 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4609 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4610 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4611
4612 if (rt2x00_rt(rt2x00dev, RT3290))
4613 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4614 0x00000404);
4615 else
4616 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4617 0x00000400);
4618
fcf51541 4619 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4620 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4621 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4622 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4623 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4624 &eeprom);
38c8a566 4625 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4626 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4627 0x0000002c);
4628 else
4629 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4630 0x0000000f);
4631 } else {
4632 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4633 }
d5385bfc 4634 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4635 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4636
4637 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4638 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4639 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4640 } else {
4641 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4642 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4643 }
c295a81d
HS		 4644 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4645 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4646 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4647 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4648 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4649 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4650 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4651 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4652 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4653 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4654 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4655 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4656 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4657 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4658 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4659 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4660 &eeprom);
4661 if (rt2x00_get_field16(eeprom,
4662 EEPROM_NIC_CONF1_DAC_TEST))
4663 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4664 0x0000001f);
4665 else
4666 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4667 0x0000000f);
4668 } else {
4669 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4670 0x00000000);
4671 }
2ed71884 4672 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
231aeca1 4673 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4674 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4675 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4676 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
231aeca1
SG		 4677 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
4678 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4679 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4680 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4681 } else {
4682 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4683 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4684 }
4685
4686 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4687 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4688 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4689 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4690 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4691 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4692 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4693 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4694 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4695 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4696
4697 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4698 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4699 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4700 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4701 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4702
4703 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4704 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4705 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4706 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4707 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4708 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4709 else
4710 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4711 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4712 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4713 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4714
a9dce149
GW		 4715 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4716 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4717 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4718 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4719 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4720 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4721 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4722 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4723 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4724
fcf51541
BZ		 4725 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4726
a9dce149
GW		 4727 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4728 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4729 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4730 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4731 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4732 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4733 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4734 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4735
fcf51541
BZ		 4736 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4737 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4738 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
be82de9d 4739 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
fcf51541 4740 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
be82de9d 4741 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
fcf51541
BZ		 4742 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4743 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4744 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4745
4746 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4747 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4748 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4749 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4750 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4751 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4752 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4753 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4754 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4755 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4756 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4757 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4758
4759 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4760 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4761 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4762 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4763 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4764 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4765 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4766 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4767 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4768 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4769 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4770 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4771
4772 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4773 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 4774 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4775 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4776 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4777 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4778 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4779 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4780 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4781 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4782 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4783 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4784
4785 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4786 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 4787 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4788 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4789 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4790 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4791 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4792 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4793 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4794 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4795 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4796 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4797
4798 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4799 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
8d79b007 4800 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4801 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4802 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4803 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4804 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4805 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4806 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4807 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4808 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4809 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4810
4811 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4812 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
8d79b007 4813 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6f492b6d 4814 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
8d79b007 4815 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
fcf51541
BZ		 4816 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4817 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4818 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4819 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4820 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4821 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4822 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4823
cea90e55 4824 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4825 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4826
4827 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4828 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4829 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4830 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4831 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4832 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4833 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4834 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4835 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4836 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4837 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4838 }
4839
961621ab
HS		 4840 /*
4841 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4842 * although it is reserved.
4843 */
4844 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4845 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4846 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4847 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4848 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4849 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4850 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4851 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4852 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4853 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4854 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4855 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4856
7641328d
SG		 4857 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4858 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4859
4860 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4861 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4862 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4863 IEEE80211_MAX_RTS_THRESHOLD);
4864 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4865 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4866
4867 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4868
a21c2ab4
HS		 4869 /*
4870 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4871 * time should be set to 16. However, the original Ralink driver uses
4872 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4873 * connection problems with 11g + CTS protection. Hence, use the same
4874 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4875 */
a9dce149 4876 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4877 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4878 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4879 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4880 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4881 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4882 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4883
fcf51541
BZ		 4884 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4885
4886 /*
4887 * ASIC will keep garbage value after boot, clear encryption keys.
4888 */
4889 for (i = 0; i < 4; i++)
4890 rt2800_register_write(rt2x00dev,
4891 SHARED_KEY_MODE_ENTRY(i), 0);
4892
4893 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4894 rt2800_config_wcid(rt2x00dev, NULL, i);
4895 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4896 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4897 }
4898
4899 /*
4900 * Clear all beacons
fcf51541 4901 */
77f7c0f3
GJ		 4902 for (i = 0; i < 8; i++)
4903 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4904
cea90e55 4905 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4906 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4907 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4908 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4909 } else if (rt2x00_is_pcie(rt2x00dev)) {
4910 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4911 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4912 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4913 }
4914
4915 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4916 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4917 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4918 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4919 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4920 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4921 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4922 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4923 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4924 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4925
4926 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4927 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4928 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4929 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4930 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4931 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4932 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4933 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4934 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4935 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4936
4937 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4938 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4939 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4940 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4941 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4942 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4943 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4944 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4945 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4946 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4947
4948 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4949 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4950 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4951 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4952 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4953 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4954
47ee3eb1
HS		 4955 /*
4956 * Do not force the BA window size, we use the TXWI to set it
4957 */
4958 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4959 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4960 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4961 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4962
fcf51541
BZ		 4963 /*
4964 * We must clear the error counters.
4965 * These registers are cleared on read,
4966 * so we may pass a useless variable to store the value.
4967 */
4968 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4969 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4970 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4971 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4972 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4973 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4974
9f926fb5
HS		 4975 /*
4976 * Setup leadtime for pre tbtt interrupt to 6ms
4977 */
4978 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4979 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4980 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4981
977206d7
HS		 4982 /*
4983 * Set up channel statistics timer
4984 */
4985 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4986 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4987 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4988 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4989 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4990 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4991 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4992
fcf51541
BZ		 4993 return 0;
4994}
fcf51541
BZ		 4995
4996static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4997{
4998 unsigned int i;
4999 u32 reg;
5000
5001 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5002 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5003 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5004 return 0;
5005
5006 udelay(REGISTER_BUSY_DELAY);
5007 }
5008
ec9c4989 5009 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5010 return -EACCES;
5011}
5012
5013static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5014{
5015 unsigned int i;
5016 u8 value;
5017
5018 /*
5019 * BBP was enabled after firmware was loaded,
5020 * but we need to reactivate it now.
5021 */
5022 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5023 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5024 msleep(1);
5025
5026 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5027 rt2800_bbp_read(rt2x00dev, 0, &value);
5028 if ((value != 0xff) && (value != 0x00))
5029 return 0;
5030 udelay(REGISTER_BUSY_DELAY);
5031 }
5032
ec9c4989 5033 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5034 return -EACCES;
5035}
5036
a7bbbe5c
SG		 5037static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5038{
5039 u8 value;
5040
5041 rt2800_bbp_read(rt2x00dev, 4, &value);
5042 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5043 rt2800_bbp_write(rt2x00dev, 4, value);
5044}
5045
c2675487
SG		 5046static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5047{
5048 rt2800_bbp_write(rt2x00dev, 142, 1);
5049 rt2800_bbp_write(rt2x00dev, 143, 57);
5050}
5051
a7bbbe5c
SG		 5052static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5053{
5054 const u8 glrt_table[] = {
5055 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5056 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5057 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5058 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5059 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5060 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5061 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5062 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5063 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5064 };
5065 int i;
5066
5067 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5068 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5069 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5070 }
5071};
5072
624708b8 5073static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5074{
5075 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5076 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5077 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5078 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5079 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5080 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5081 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5082 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5083 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5084 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5085 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5086 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5087 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5088 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5089 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5090 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5091}
5092
5df1ff3a
SG		 5093static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5094{
5095 u16 eeprom;
5096 u8 value;
5097
5098 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5099 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5100 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5101 value |= 0x20;
5102 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5103 value &= ~0x02;
5104 rt2800_bbp_write(rt2x00dev, 138, value);
5105}
5106
dae62957
SG		 5107static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5108{
b2f8e0bd 5109 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5110
5111 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5112 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5113
5114 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5115 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5116
5117 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5118
5119 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5120 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5121
5122 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5123
5124 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5125
5126 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5127
5128 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5129
5130 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5131
5132 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5133
5134 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5135
5136 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5137
5138 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5139}
5140
39ab3e8b
SG		 5141static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5142{
e379de12
SG		 5143 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5144 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5145
5146 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5147 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5148 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5149 } else {
5150 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5151 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5152 }
8d97be38
SG		 5153
5154 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5155
5156 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5157
5158 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5159
5160 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5161
5162 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5163 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5164 else
5165 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5166
5167 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5168
5169 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5170
5171 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5172
5173 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5174
5175 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5176
5177 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5178}
5179
5180static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5181{
e379de12
SG		 5182 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5183 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5184
5185 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5186 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5187
5188 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5189
5190 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5191 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5192 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5193
5194 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5195
5196 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5197
5198 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5199
5200 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5201
5202 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5203
5204 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5205
5206 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5207 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5208 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5209 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5210 else
5211 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5212
5213 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5214
5215 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5216
5217 if (rt2x00_rt(rt2x00dev, RT3071) ||
5218 rt2x00_rt(rt2x00dev, RT3090))
5219 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5220}
5221
5222static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5223{
6addb24e
SG		 5224 u8 value;
5225
c3223573 5226 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5227
5228 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5229
5230 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5231 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5232
5233 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5234
5235 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5236 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5237 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5238 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5239
5240 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5241
5242 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5243
5244 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5245 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5246 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5247 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5248
5249 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5250
5251 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5252
5253 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5254
5255 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5256
5257 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5258
5259 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5260
5261 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5262
5263 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5264
5265 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5266
5267 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5268
5269 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5270
5271 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5272 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5273 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5274 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5275 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5276 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5277 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5278 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5279 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5280 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5281
5282 rt2800_bbp_read(rt2x00dev, 47, &value);
5283 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5284 rt2800_bbp_write(rt2x00dev, 47, value);
5285
5286 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5287 rt2800_bbp_read(rt2x00dev, 3, &value);
5288 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5289 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5290 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5291}
5292
5293static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5294{
29f3a58b
SG		 5295 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5296 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5297
5298 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5299
5300 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5301
5302 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5303 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5304
5305 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5306
5307 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5308 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5309 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5310 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5311
5312 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5313
5314 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5315
5316 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5317 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5318 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5319
5320 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5321
5322 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5323
5324 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5325
5326 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5327
5328 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5329
5330 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5331
5332 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5333
5334 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5335
5336 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5337
5338 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5339
5340 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5341
5342 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5343
5344 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5345
5346 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5347 /* Set ITxBF timeout to 0x9c40=1000msec */
5348 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5349 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5350 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5351 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5352 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5353 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5354 /* Reprogram the inband interface to put right values in RXWI */
5355 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5356 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5357 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5358 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5359 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5360 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5361 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5362 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5363
5364 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5365}
5366
5367static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5368{
e379de12
SG		 5369 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5370 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5371
5372 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5373 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5374
5375 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5376
5377 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5378 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5379 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5380
5381 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5382
5383 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5384
5385 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5386
5387 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5388
5389 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5390
5391 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5392
5393 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5394 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5395 else
5396 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5397
5398 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5399
5400 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5401
5402 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5403}
5404
5405static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5406{
b2f8e0bd 5407 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5408
5409 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5410 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5411
5412 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5413 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5414
5415 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5416
5417 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5418 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5419 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5420
5421 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5422
5423 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5424
5425 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5426
5427 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5428
5429 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5430
5431 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5432
5433 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5434
5435 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5436
5437 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5438
5439 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5440}
5441
b189a181
GJ		 5442static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5443{
5444 rt2800_init_bbp_early(rt2x00dev);
5445
5446 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5447 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5448 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5449 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5450
5451 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5452
5453 /* Enable DC filter */
5454 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5455 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5456}
5457
39ab3e8b
SG		 5458static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5459{
32ef8f49
SG		 5460 int ant, div_mode;
5461 u16 eeprom;
5462 u8 value;
5463
c3223573 5464 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5465
5466 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5467
5468 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5469 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5470
5471 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 5472
58422191 5473 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 5474 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5475 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5476 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5477
5478 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 5479
58422191
SG		 5480 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5481
43f535e2
SG		 5482 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5483 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5484 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5485
5486 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5487
5488 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5489
5490 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5491
5492 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5493
5494 if (rt2x00_rt(rt2x00dev, RT5392))
5495 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5496
5497 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5498
5499 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5500
5501 if (rt2x00_rt(rt2x00dev, RT5392)) {
5502 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5503 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5504 }
672d1188
SG		 5505
5506 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5507
5508 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5509
5510 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5511
5512 if (rt2x00_rt(rt2x00dev, RT5390))
5513 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5514 else if (rt2x00_rt(rt2x00dev, RT5392))
5515 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5516 else
5517 WARN_ON(1);
f2b6777c
SG		 5518
5519 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5520
5521 if (rt2x00_rt(rt2x00dev, RT5392)) {
5522 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5523 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5524 }
5df1ff3a
SG		 5525
5526 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5527
3e38d3da 5528 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5529 div_mode = rt2x00_get_field16(eeprom,
5530 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5531 ant = (div_mode == 3) ? 1 : 0;
5532
5533 /* check if this is a Bluetooth combo card */
c429dfef 5534 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 5535 u32 reg;
5536
5537 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5538 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5539 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5540 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5541 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5542 if (ant == 0)
5543 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5544 else if (ant == 1)
5545 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5546 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5547 }
5548
5549 /* This chip has hardware antenna diversity*/
5550 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5551 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5552 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5553 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5554 }
5555
5556 rt2800_bbp_read(rt2x00dev, 152, &value);
5557 if (ant == 0)
5558 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5559 else
5560 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5561 rt2800_bbp_write(rt2x00dev, 152, value);
5562
5563 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5564}
5565
a7bbbe5c
SG		 5566static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5567{
5568 int ant, div_mode;
5569 u16 eeprom;
5570 u8 value;
5571
624708b8 5572 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5573
a7bbbe5c
SG		 5574 rt2800_bbp_read(rt2x00dev, 105, &value);
5575 rt2x00_set_field8(&value, BBP105_MLD,
5576 rt2x00dev->default_ant.rx_chain_num == 2);
5577 rt2800_bbp_write(rt2x00dev, 105, value);
5578
5579 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5580
5581 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5582 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5583 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5584 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5585 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5586 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5587 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5588 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5589 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5590 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5591 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5592 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5593 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5594 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5595 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5596 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5597 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5598 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5599 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5600 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5601 /* FIXME BBP105 owerwrite */
5602 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5603 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5604 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5605 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5606 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5607 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5608
5609 /* Initialize GLRT (Generalized Likehood Radio Test) */
5610 rt2800_init_bbp_5592_glrt(rt2x00dev);
5611
5612 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5613
3e38d3da 5614 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5615 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5616 ant = (div_mode == 3) ? 1 : 0;
5617 rt2800_bbp_read(rt2x00dev, 152, &value);
5618 if (ant == 0) {
5619 /* Main antenna */
5620 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5621 } else {
5622 /* Auxiliary antenna */
5623 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5624 }
5625 rt2800_bbp_write(rt2x00dev, 152, value);
5626
5627 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5628 rt2800_bbp_read(rt2x00dev, 254, &value);
5629 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5630 rt2800_bbp_write(rt2x00dev, 254, value);
5631 }
5632
c2675487
SG		 5633 rt2800_init_freq_calibration(rt2x00dev);
5634
a7bbbe5c 5635 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5636 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5637 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5638}
5639
a1ef5039 5640static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5641{
5642 unsigned int i;
5643 u16 eeprom;
5644 u8 reg_id;
5645 u8 value;
5646
dae62957
SG		 5647 if (rt2800_is_305x_soc(rt2x00dev))
5648 rt2800_init_bbp_305x_soc(rt2x00dev);
5649
39ab3e8b
SG		 5650 switch (rt2x00dev->chip.rt) {
5651 case RT2860:
5652 case RT2872:
5653 case RT2883:
5654 rt2800_init_bbp_28xx(rt2x00dev);
5655 break;
5656 case RT3070:
5657 case RT3071:
5658 case RT3090:
5659 rt2800_init_bbp_30xx(rt2x00dev);
5660 break;
5661 case RT3290:
5662 rt2800_init_bbp_3290(rt2x00dev);
5663 break;
5664 case RT3352:
5665 rt2800_init_bbp_3352(rt2x00dev);
5666 break;
5667 case RT3390:
5668 rt2800_init_bbp_3390(rt2x00dev);
5669 break;
5670 case RT3572:
5671 rt2800_init_bbp_3572(rt2x00dev);
5672 break;
b189a181
GJ		 5673 case RT3593:
5674 rt2800_init_bbp_3593(rt2x00dev);
5675 return;
39ab3e8b
SG		 5676 case RT5390:
5677 case RT5392:
5678 rt2800_init_bbp_53xx(rt2x00dev);
5679 break;
5680 case RT5592:
a7bbbe5c 5681 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5682 return;
a7bbbe5c
SG		 5683 }
5684
fcf51541 5685 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5686 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5687 &eeprom);
fcf51541
BZ		 5688
5689 if (eeprom != 0xffff && eeprom != 0x0000) {
5690 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5691 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5692 rt2800_bbp_write(rt2x00dev, reg_id, value);
5693 }
5694 }
fcf51541 5695}
fcf51541 5696
d9517f2f
SG		 5697static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5698{
5699 u32 reg;
5700
5701 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5702 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5703 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5704}
5705
c5b3c350
SG		 5706static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5707 u8 filter_target)
fcf51541
BZ		 5708{
5709 unsigned int i;
5710 u8 bbp;
5711 u8 rfcsr;
5712 u8 passband;
5713 u8 stopband;
5714 u8 overtuned = 0;
c5b3c350 5715 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5716
5717 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5718
5719 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5720 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5721 rt2800_bbp_write(rt2x00dev, 4, bbp);
5722
80d184e6
RJH		 5723 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5724 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5725 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5726
fcf51541
BZ		 5727 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5728 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5729 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5730
5731 /*
5732 * Set power & frequency of passband test tone
5733 */
5734 rt2800_bbp_write(rt2x00dev, 24, 0);
5735
5736 for (i = 0; i < 100; i++) {
5737 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5738 msleep(1);
5739
5740 rt2800_bbp_read(rt2x00dev, 55, &passband);
5741 if (passband)
5742 break;
5743 }
5744
5745 /*
5746 * Set power & frequency of stopband test tone
5747 */
5748 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5749
5750 for (i = 0; i < 100; i++) {
5751 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5752 msleep(1);
5753
5754 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5755
5756 if ((passband - stopband) <= filter_target) {
5757 rfcsr24++;
5758 overtuned += ((passband - stopband) == filter_target);
5759 } else
5760 break;
5761
5762 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5763 }
5764
5765 rfcsr24 -= !!overtuned;
5766
5767 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5768 return rfcsr24;
5769}
5770
ce94ede9
SG		 5771static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5772 const unsigned int rf_reg)
5773{
5774 u8 rfcsr;
5775
5776 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5777 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5778 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5779 msleep(1);
5780 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5781 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5782}
5783
c5b3c350
SG		 5784static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5785{
5786 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5787 u8 filter_tgt_bw20;
5788 u8 filter_tgt_bw40;
5789 u8 rfcsr, bbp;
5790
5791 /*
5792 * TODO: sync filter_tgt values with vendor driver
5793 */
5794 if (rt2x00_rt(rt2x00dev, RT3070)) {
5795 filter_tgt_bw20 = 0x16;
5796 filter_tgt_bw40 = 0x19;
5797 } else {
5798 filter_tgt_bw20 = 0x13;
5799 filter_tgt_bw40 = 0x15;
5800 }
5801
5802 drv_data->calibration_bw20 =
5803 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5804 drv_data->calibration_bw40 =
5805 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5806
5807 /*
5808 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5809 */
5810 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5811 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5812
5813 /*
5814 * Set back to initial state
5815 */
5816 rt2800_bbp_write(rt2x00dev, 24, 0);
5817
5818 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5819 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5820 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5821
5822 /*
5823 * Set BBP back to BW20
5824 */
5825 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5826 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5827 rt2800_bbp_write(rt2x00dev, 4, bbp);
5828}
5829
da8064c2
SG		 5830static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5831{
5832 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5833 u8 min_gain, rfcsr, bbp;
5834 u16 eeprom;
5835
5836 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5837
5838 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5839 if (rt2x00_rt(rt2x00dev, RT3070) ||
5840 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5841 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5842 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 5843 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 5844 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5845 }
5846
5847 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5848 if (drv_data->txmixer_gain_24g >= min_gain) {
5849 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5850 drv_data->txmixer_gain_24g);
5851 }
5852
5853 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5854
5855 if (rt2x00_rt(rt2x00dev, RT3090)) {
5856 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5857 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5858 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5859 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5860 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5861 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5862 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5863 rt2800_bbp_write(rt2x00dev, 138, bbp);
5864 }
5865
5866 if (rt2x00_rt(rt2x00dev, RT3070)) {
5867 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5868 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5869 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5870 else
5871 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5872 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5873 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5874 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5875 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5876 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5877 rt2x00_rt(rt2x00dev, RT3090) ||
5878 rt2x00_rt(rt2x00dev, RT3390)) {
5879 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5880 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5881 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5882 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5883 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5884 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5885 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5886
5887 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5888 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5889 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5890
5891 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5892 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5893 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5894
5895 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5896 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5897 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5898 }
5899}
5900
ab7078ac
GJ		 5901static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5902{
5903 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5904 u8 rfcsr;
5905 u8 tx_gain;
5906
5907 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5908 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5909 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5910
5911 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5912 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5913 RFCSR17_TXMIXER_GAIN);
5914 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5915 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5916
5917 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5918 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5919 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5920
5921 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5922 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5923 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5924
5925 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5926 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5927 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5928 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5929
5930 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5931 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5932 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5933
5934 /* TODO: enable stream mode */
5935}
5936
f7df8fe5
SG		 5937static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5938{
5939 u8 reg;
5940 u16 eeprom;
5941
5942 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5943 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5944 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5945 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5946 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5947 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5948 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5949 rt2800_bbp_write(rt2x00dev, 138, reg);
5950
5951 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5952 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5953 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5954
5955 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5956 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5957 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5958
5959 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5960
5961 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5962 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5963 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5964}
5965
d5374ef1
SG		 5966static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5967{
ce94ede9
SG		 5968 rt2800_rf_init_calibration(rt2x00dev, 30);
5969
d5374ef1
SG		 5970 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5971 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5972 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5973 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5974 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5975 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5976 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5977 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5978 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5979 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5980 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5981 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5982 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5983 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5984 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5985 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5986 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5987 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5988 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5989 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5990 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5991 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5992 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5993 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5994 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5995 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5996 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5997 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5998 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5999 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6000 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6001 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6002}
6003
6004static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6005{
c9a221b2
SG		 6006 u8 rfcsr;
6007 u16 eeprom;
6008 u32 reg;
6009
ce94ede9
SG		 6010 /* XXX vendor driver do this only for 3070 */
6011 rt2800_rf_init_calibration(rt2x00dev, 30);
6012
d5374ef1
SG		 6013 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6014 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6015 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6016 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6017 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6018 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6019 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6020 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6021 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6022 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6023 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6024 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6025 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6026 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6027 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6028 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6029 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6030 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6031 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6032
6033 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6034 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6035 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6036 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6037 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6038 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6039 rt2x00_rt(rt2x00dev, RT3090)) {
6040 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6041
6042 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6043 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6044 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6045
6046 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6047 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6048 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6049 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6050 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6051 &eeprom);
c9a221b2
SG		 6052 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6053 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6054 else
6055 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6056 }
6057 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6058
6059 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6060 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6061 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6062 }
c5b3c350
SG		 6063
6064 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6065
6066 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6067 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6068 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6069 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6070
6071 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6072 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6073}
6074
6075static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6076{
f9cdcbb1
SG		 6077 u8 rfcsr;
6078
ce94ede9
SG		 6079 rt2800_rf_init_calibration(rt2x00dev, 2);
6080
d5374ef1
SG		 6081 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6082 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6083 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6084 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6085 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6086 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6087 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6088 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6089 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6090 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6091 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6092 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6093 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6094 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6095 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6096 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6097 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6098 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6099 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6100 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6101 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6102 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6103 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6104 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6105 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6106 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6107 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6108 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6109 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6110 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6111 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6112 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6113 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6114 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6115 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6116 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6117 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6118 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6119 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6120 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6121 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6122 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6123 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6124 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6125 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6126 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6127
6128 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6129 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6130 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6131
6132 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6133 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6134}
6135
6136static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6137{
ce94ede9
SG		 6138 rt2800_rf_init_calibration(rt2x00dev, 30);
6139
d5374ef1
SG		 6140 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6141 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6142 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6143 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6144 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6145 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6146 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6147 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6148 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6149 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6150 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6151 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6152 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6153 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6154 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6155 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6156 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6157 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6158 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6159 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6160 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6161 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6162 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6163 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6164 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6165 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6166 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6167 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6168 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6169 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6170 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6171 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6172 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6173 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6174 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6175 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6176 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6177 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6178 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6179 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6180 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6181 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6182 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6183 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6184 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6185 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6186 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6187 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6188 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6189 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6190 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6191 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6192 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6193 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6194 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6195 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6196 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6197 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6198 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6199 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6200 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6201 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6202 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6203
6204 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6205 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6206 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6207}
6208
6209static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6210{
2971e66f
SG		 6211 u32 reg;
6212
ce94ede9
SG		 6213 rt2800_rf_init_calibration(rt2x00dev, 30);
6214
d5374ef1
SG		 6215 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6216 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6217 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6218 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6219 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6220 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6221 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6222 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6223 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6224 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6225 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6226 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6227 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6228 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6229 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6230 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6231 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6232 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6233 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6234 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6235 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6236 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6237 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6238 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6239 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6240 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6241 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6242 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6243 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6244 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6245 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6246 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6247
6248 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6249 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6250 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6251
6252 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6253
6254 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6255 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6256
6257 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6258 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6259}
6260
6261static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6262{
87d91db9
SG		 6263 u8 rfcsr;
6264 u32 reg;
6265
ce94ede9
SG		 6266 rt2800_rf_init_calibration(rt2x00dev, 30);
6267
d5374ef1
SG		 6268 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6269 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6270 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6271 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6272 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6273 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6274 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6275 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6276 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6277 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6278 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6279 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6280 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6281 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6282 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6283 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6284 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6285 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6286 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6287 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6288 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6289 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6290 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6291 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6292 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6293 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6294 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6295 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6296 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6297 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6298 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6299
6300 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6301 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6302 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6303
6304 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6305 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6306 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6307 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6308 msleep(1);
6309 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6310 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6311 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6312 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6313
6314 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6315 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6316 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6317}
6318
d63f7e8c
GJ		 6319static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6320{
6321 u8 bbp;
6322 bool txbf_enabled = false; /* FIXME */
6323
6324 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6325 if (rt2x00dev->default_ant.rx_chain_num == 1)
6326 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6327 else
6328 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6329 rt2800_bbp_write(rt2x00dev, 105, bbp);
6330
6331 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6332
6333 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6334 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6335 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6336 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6337 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6338 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6339 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6340 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6341
6342 if (txbf_enabled)
6343 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6344 else
6345 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6346
6347 /* SNR mapping */
6348 rt2800_bbp_write(rt2x00dev, 142, 6);
6349 rt2800_bbp_write(rt2x00dev, 143, 160);
6350 rt2800_bbp_write(rt2x00dev, 142, 7);
6351 rt2800_bbp_write(rt2x00dev, 143, 161);
6352 rt2800_bbp_write(rt2x00dev, 142, 8);
6353 rt2800_bbp_write(rt2x00dev, 143, 162);
6354
6355 /* ADC/DAC control */
6356 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6357
6358 /* RX AGC energy lower bound in log2 */
6359 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6360
6361 /* FIXME: BBP 105 owerwrite? */
6362 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6363
d63f7e8c
GJ		 6364}
6365
ab7078ac
GJ		 6366static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6367{
6368 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6369 u32 reg;
6370 u8 rfcsr;
6371
6372 /* Disable GPIO #4 and #7 function for LAN PE control */
6373 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6374 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6375 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6376 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6377
6378 /* Initialize default register values */
6379 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6380 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6381 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6382 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6383 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6384 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6385 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6386 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6387 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6388 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6389 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6390 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6391 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6392 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6393 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6394 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6395 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6396 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6397 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6398 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6399 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6400 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6401 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6402 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6403 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6404 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6405 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6406 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6407 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6408 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6409 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6410 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6411
6412 /* Initiate calibration */
6413 /* TODO: use rt2800_rf_init_calibration ? */
6414 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6415 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6416 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6417
6418 rt2800_adjust_freq_offset(rt2x00dev);
6419
6420 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6421 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6422 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6423
6424 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6425 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6426 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6427 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6428 usleep_range(1000, 1500);
6429 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6430 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6431 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6432
6433 /* Set initial values for RX filter calibration */
6434 drv_data->calibration_bw20 = 0x1f;
6435 drv_data->calibration_bw40 = 0x2f;
6436
6437 /* Save BBP 25 & 26 values for later use in channel switching */
6438 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6439 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6440
6441 rt2800_led_open_drain_enable(rt2x00dev);
6442 rt2800_normal_mode_setup_3593(rt2x00dev);
6443
d63f7e8c 6444 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6445
6446 /* TODO: enable stream mode support */
6447}
6448
d5374ef1
SG		 6449static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6450{
ce94ede9
SG		 6451 rt2800_rf_init_calibration(rt2x00dev, 2);
6452
d5374ef1
SG		 6453 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6454 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6455 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6456 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6457 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6458 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6459 else
6460 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6461 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6462 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6463 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 6464 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 6465 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6466 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6467 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6468 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6469 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6470 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6471
6472 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6473 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6474 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6475 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6476 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 6477 if (rt2x00_is_usb(rt2x00dev) &&
6478 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 6479 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6480 else
6481 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6482 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6483 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6484 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6485 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6486
7122e660 6487 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 6488 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6489 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6490 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6491 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6492 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6493 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6494 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6495 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6496 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6497
c8520bcb 6498 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 6499 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6500 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6501 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6502 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6503 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6504 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6505 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6506 else
6507 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6508 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6509 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6510 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6511
6512 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6513 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6514 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6515 else
6516 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6517 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6518 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 6519 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6520 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6521 else
6522 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 6523 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6524 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 6525 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 6526
6527 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 6528 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6529 if (rt2x00_is_usb(rt2x00dev))
6530 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6531 else
6532 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6533 } else {
6534 if (rt2x00_is_usb(rt2x00dev))
6535 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6536 else
6537 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6538 }
d5374ef1
SG		 6539 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6540 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6541
6542 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6543
6544 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6545}
6546
6547static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6548{
ce94ede9
SG		 6549 rt2800_rf_init_calibration(rt2x00dev, 2);
6550
d5374ef1 6551 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 6552 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6553 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6554 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6555 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6556 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6557 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6558 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6559 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6560 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6561 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6562 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6563 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6564 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6565 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6566 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6567 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6568 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6569 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6570 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6571 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6572 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6573 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6574 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6575 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6576 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6577 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6578 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6579 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6580 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6581 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6582 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6583 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6584 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6585 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6586 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6587 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6588 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6589 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6590 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6591 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6592 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6593 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6594 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6595 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6596 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6597 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6598 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6599 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6600 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6601 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6602 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6603 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6604 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6605 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6606 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6607 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6608 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6609
6610 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6611
6612 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6613}
6614
0c9e5fb9
SG		 6615static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6616{
ce94ede9
SG		 6617 rt2800_rf_init_calibration(rt2x00dev, 30);
6618
0c9e5fb9
SG		 6619 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6620 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 6621 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6622 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6623 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6624 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6625 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6626 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6627 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6628 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6629 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6630 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6631 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6632 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6633 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6634 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6635 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6636 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6637 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6638 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6639 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6640
6641 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6642 msleep(1);
6643
6644 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6645
c630ccf1
SG		 6646 /* Enable DC filter */
6647 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6648 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6649
f7df8fe5 6650 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6651
6652 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6653 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6654
6655 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6656}
6657
074f2529 6658static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6659{
d5374ef1
SG		 6660 if (rt2800_is_305x_soc(rt2x00dev)) {
6661 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6662 return;
d5374ef1
SG		 6663 }
6664
6665 switch (rt2x00dev->chip.rt) {
6666 case RT3070:
6667 case RT3071:
6668 case RT3090:
6669 rt2800_init_rfcsr_30xx(rt2x00dev);
6670 break;
6671 case RT3290:
6672 rt2800_init_rfcsr_3290(rt2x00dev);
6673 break;
6674 case RT3352:
6675 rt2800_init_rfcsr_3352(rt2x00dev);
6676 break;
6677 case RT3390:
6678 rt2800_init_rfcsr_3390(rt2x00dev);
6679 break;
6680 case RT3572:
6681 rt2800_init_rfcsr_3572(rt2x00dev);
6682 break;
ab7078ac
GJ		 6683 case RT3593:
6684 rt2800_init_rfcsr_3593(rt2x00dev);
6685 break;
d5374ef1
SG		 6686 case RT5390:
6687 rt2800_init_rfcsr_5390(rt2x00dev);
6688 break;
6689 case RT5392:
6690 rt2800_init_rfcsr_5392(rt2x00dev);
6691 break;
0c9e5fb9
SG		 6692 case RT5592:
6693 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6694 break;
8cdd15e0 6695 }
fcf51541 6696}
b9a07ae9
ID		 6697
6698int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6699{
6700 u32 reg;
6701 u16 word;
6702
6703 /*
61edc7fa 6704 * Initialize MAC registers.
b9a07ae9
ID		 6705 */
6706 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6707 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6708 return -EIO;
6709
61edc7fa
SG		 6710 /*
6711 * Wait BBP/RF to wake up.
6712 */
f4e1a4d3
SG		 6713 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6714 return -EIO;
6715
b9a07ae9 6716 /*
61edc7fa 6717 * Send signal during boot time to initialize firmware.
b9a07ae9 6718 */
c630ccf1
SG		 6719 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6720 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 6721 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 6722 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 6723 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 6724 msleep(1);
6725
61edc7fa
SG		 6726 /*
6727 * Make sure BBP is up and running.
6728 */
f4e1a4d3 6729 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6730 return -EIO;
b9a07ae9 6731
61edc7fa
SG		 6732 /*
6733 * Initialize BBP/RF registers.
6734 */
a1ef5039 6735 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6736 rt2800_init_rfcsr(rt2x00dev);
6737
b9a07ae9
ID		 6738 if (rt2x00_is_usb(rt2x00dev) &&
6739 (rt2x00_rt(rt2x00dev, RT3070) ||
6740 rt2x00_rt(rt2x00dev, RT3071) ||
6741 rt2x00_rt(rt2x00dev, RT3572))) {
6742 udelay(200);
6743 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6744 udelay(10);
6745 }
6746
6747 /*
6748 * Enable RX.
6749 */
6750 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6751 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6752 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6753 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6754
6755 udelay(50);
6756
6757 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6758 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6759 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
b9a07ae9
ID		 6760 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6761 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6762
6763 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6764 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6765 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6766 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6767
6768 /*
6769 * Initialize LED control
6770 */
3e38d3da 6771 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6772 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6773 word & 0xff, (word >> 8) & 0xff);
6774
3e38d3da 6775 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6776 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6777 word & 0xff, (word >> 8) & 0xff);
6778
3e38d3da 6779 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6780 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6781 word & 0xff, (word >> 8) & 0xff);
6782
6783 return 0;
6784}
6785EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6786
6787void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6788{
6789 u32 reg;
6790
f7b395e9 6791 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6792
6793 /* Wait for DMA, ignore error */
6794 rt2800_wait_wpdma_ready(rt2x00dev);
6795
6796 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6797 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6798 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6799 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6800}
6801EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6802
30e84034
BZ		 6803int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6804{
6805 u32 reg;
a89534ed 6806 u16 efuse_ctrl_reg;
30e84034 6807
a89534ed
WH		 6808 if (rt2x00_rt(rt2x00dev, RT3290))
6809 efuse_ctrl_reg = EFUSE_CTRL_3290;
6810 else
6811 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6812
a89534ed 6813 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6814 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6815}
6816EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6817
6818static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6819{
6820 u32 reg;
a89534ed
WH		 6821 u16 efuse_ctrl_reg;
6822 u16 efuse_data0_reg;
6823 u16 efuse_data1_reg;
6824 u16 efuse_data2_reg;
6825 u16 efuse_data3_reg;
6826
6827 if (rt2x00_rt(rt2x00dev, RT3290)) {
6828 efuse_ctrl_reg = EFUSE_CTRL_3290;
6829 efuse_data0_reg = EFUSE_DATA0_3290;
6830 efuse_data1_reg = EFUSE_DATA1_3290;
6831 efuse_data2_reg = EFUSE_DATA2_3290;
6832 efuse_data3_reg = EFUSE_DATA3_3290;
6833 } else {
6834 efuse_ctrl_reg = EFUSE_CTRL;
6835 efuse_data0_reg = EFUSE_DATA0;
6836 efuse_data1_reg = EFUSE_DATA1;
6837 efuse_data2_reg = EFUSE_DATA2;
6838 efuse_data3_reg = EFUSE_DATA3;
6839 }
31a4cf1f
GW		 6840 mutex_lock(&rt2x00dev->csr_mutex);
6841
a89534ed 6842 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6843 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6844 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6845 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6846 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6847
6848 /* Wait until the EEPROM has been loaded */
a89534ed 6849 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6850 /* Apparently the data is read from end to start */
a89534ed 6851 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6852 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6853 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6854 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6855 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6856 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6857 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6858 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6859 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6860
6861 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6862}
6863
a02308e9 6864int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6865{
6866 unsigned int i;
6867
6868 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6869 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6870
6871 return 0;
30e84034
BZ		 6872}
6873EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6874
a3f1625d
GJ		 6875static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6876{
6877 u16 word;
6878
6316c786
GJ		 6879 if (rt2x00_rt(rt2x00dev, RT3593))
6880 return 0;
6881
a3f1625d
GJ		 6882 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6883 if ((word & 0x00ff) != 0x00ff)
6884 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6885
6886 return 0;
6887}
6888
6889static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6890{
6891 u16 word;
6892
6316c786
GJ		 6893 if (rt2x00_rt(rt2x00dev, RT3593))
6894 return 0;
6895
a3f1625d
GJ		 6896 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6897 if ((word & 0x00ff) != 0x00ff)
6898 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6899
6900 return 0;
6901}
6902
ad417a53 6903static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6904{
77c06c2c 6905 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6906 u16 word;
6907 u8 *mac;
6908 u8 default_lna_gain;
a02308e9 6909 int retval;
38bd7b8a 6910
ad417a53
GW		 6911 /*
6912 * Read the EEPROM.
6913 */
a02308e9
GJ		 6914 retval = rt2800_read_eeprom(rt2x00dev);
6915 if (retval)
6916 return retval;
ad417a53 6917
38bd7b8a
BZ		 6918 /*
6919 * Start validation of the data that has been read.
6920 */
3e38d3da 6921 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9766cb70 6922 rt2x00lib_set_mac_address(rt2x00dev, mac);
38bd7b8a 6923
3e38d3da 6924 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6925 if (word == 0xffff) {
38c8a566
RJH		 6926 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6927 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6928 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6929 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6930 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6931 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6932 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6933 /*
6934 * There is a max of 2 RX streams for RT28x0 series
6935 */
38c8a566
RJH		 6936 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6937 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6938 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6939 }
6940
3e38d3da 6941 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6942 if (word == 0xffff) {
38c8a566
RJH		 6943 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6944 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6945 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6946 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6947 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6948 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6949 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6950 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6951 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6952 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6953 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6954 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6955 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6956 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6957 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6958 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6959 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6960 }
6961
3e38d3da 6962 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6963 if ((word & 0x00ff) == 0x00ff) {
6964 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6965 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6966 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6967 }
6968 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6969 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6970 LED_MODE_TXRX_ACTIVITY);
6971 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6972 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6973 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6974 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6975 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 6976 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 6977 }
6978
6979 /*
6980 * During the LNA validation we are going to use
6981 * lna0 as correct value. Note that EEPROM_LNA
6982 * is never validated.
6983 */
3e38d3da 6984 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 6985 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6986
3e38d3da 6987 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 6988 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6989 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6990 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6991 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 6992 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 6993
a3f1625d 6994 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 6995
3e38d3da 6996 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 6997 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6998 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 6999 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7000 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7001 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7002 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7003 default_lna_gain);
7004 }
3e38d3da 7005 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 7006
a3f1625d 7007 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 7008
3e38d3da 7009 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 7010 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7011 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7012 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7013 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 7014 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 7015
3e38d3da 7016 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 7017 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7018 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 7019 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7020 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7021 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7022 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7023 default_lna_gain);
7024 }
3e38d3da 7025 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 7026
f36bb0ca
GJ		 7027 if (rt2x00_rt(rt2x00dev, RT3593)) {
7028 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7029 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7030 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7031 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7032 default_lna_gain);
7033 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7034 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7035 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7036 default_lna_gain);
7037 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7038 }
7039
38bd7b8a
BZ		 7040 return 0;
7041}
38bd7b8a 7042
ad417a53 7043static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 7044{
38bd7b8a
BZ		 7045 u16 value;
7046 u16 eeprom;
86868b26 7047 u16 rf;
38bd7b8a 7048
86868b26
GJ		 7049 /*
7050 * Read EEPROM word for configuration.
7051 */
3e38d3da 7052 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 7053
7054 /*
7055 * Identify RF chipset by EEPROM value
7056 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7057 * RT53xx: defined in "EEPROM_CHIP_ID" field
7058 */
7059 if (rt2x00_rt(rt2x00dev, RT3290) ||
7060 rt2x00_rt(rt2x00dev, RT5390) ||
7061 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7062 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7063 else
7064 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7065
7066 switch (rf) {
d331eb51
LF		 7067 case RF2820:
7068 case RF2850:
7069 case RF2720:
7070 case RF2750:
7071 case RF3020:
7072 case RF2020:
7073 case RF3021:
7074 case RF3022:
7075 case RF3052:
0f5af26a 7076 case RF3053:
3b9b74ba 7077 case RF3070:
a89534ed 7078 case RF3290:
d331eb51 7079 case RF3320:
03839951 7080 case RF3322:
ccf91bd6 7081 case RF5360:
ac0372ab 7082 case RF5362:
d331eb51 7083 case RF5370:
2ed71884 7084 case RF5372:
d331eb51 7085 case RF5390:
cff3d1f0 7086 case RF5392:
b8863f8b 7087 case RF5592:
d331eb51
LF		 7088 break;
7089 default:
ec9c4989
JP		 7090 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7091 rf);
38bd7b8a
BZ		 7092 return -ENODEV;
7093 }
7094
86868b26
GJ		 7095 rt2x00_set_rf(rt2x00dev, rf);
7096
38bd7b8a
BZ		 7097 /*
7098 * Identify default antenna configuration.
7099 */
d96aa640 7100 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7101 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7102 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7103 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7104
3e38d3da 7105 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7106
7107 if (rt2x00_rt(rt2x00dev, RT3070) ||
7108 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7109 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7110 rt2x00_rt(rt2x00dev, RT3390)) {
7111 value = rt2x00_get_field16(eeprom,
7112 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7113 switch (value) {
7114 case 0:
7115 case 1:
7116 case 2:
7117 rt2x00dev->default_ant.tx = ANTENNA_A;
7118 rt2x00dev->default_ant.rx = ANTENNA_A;
7119 break;
7120 case 3:
7121 rt2x00dev->default_ant.tx = ANTENNA_A;
7122 rt2x00dev->default_ant.rx = ANTENNA_B;
7123 break;
7124 }
7125 } else {
7126 rt2x00dev->default_ant.tx = ANTENNA_A;
7127 rt2x00dev->default_ant.rx = ANTENNA_A;
7128 }
7129
0586a11b
AA		 7130 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7131 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7132 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7133 }
7134
38bd7b8a 7135 /*
9328fdac 7136 * Determine external LNA informations.
38bd7b8a 7137 */
38c8a566 7138 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7139 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7140 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7141 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7142
7143 /*
7144 * Detect if this device has an hardware controlled radio.
7145 */
38c8a566 7146 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7147 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7148
fdbc7b0a
GW		 7149 /*
7150 * Detect if this device has Bluetooth co-existence.
7151 */
7152 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7153 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7154
9328fdac
GW		 7155 /*
7156 * Read frequency offset and RF programming sequence.
7157 */
3e38d3da 7158 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7159 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7160
38bd7b8a
BZ		 7161 /*
7162 * Store led settings, for correct led behaviour.
7163 */
7164#ifdef CONFIG_RT2X00_LIB_LEDS
7165 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7166 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7167 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7168
9328fdac 7169 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7170#endif /* CONFIG_RT2X00_LIB_LEDS */
7171
e90c54b2
RJH		 7172 /*
7173 * Check if support EIRP tx power limit feature.
7174 */
3e38d3da 7175 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7176
7177 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7178 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7179 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7180
38bd7b8a
BZ		 7181 return 0;
7182}
38bd7b8a 7183
4da2933f 7184/*
55f9321a 7185 * RF value list for rt28xx
4da2933f
BZ		 7186 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7187 */
7188static const struct rf_channel rf_vals[] = {
7189 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7190 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7191 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7192 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7193 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7194 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7195 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7196 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7197 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7198 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7199 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7200 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7201 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7202 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7203
7204 /* 802.11 UNI / HyperLan 2 */
7205 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7206 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7207 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7208 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7209 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7210 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7211 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7212 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7213 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7214 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7215 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7216 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7217
7218 /* 802.11 HyperLan 2 */
7219 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7220 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7221 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7222 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7223 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7224 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7225 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7226 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7227 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7228 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7229 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7230 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7231 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7232 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7233 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7234 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7235
7236 /* 802.11 UNII */
7237 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7238 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7239 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7240 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7241 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7242 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7243 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7244 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7245 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7246 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7247 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7248
7249 /* 802.11 Japan */
7250 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7251 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7252 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7253 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7254 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7255 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7256 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7257};
7258
7259/*
55f9321a 7260 * RF value list for rt3xxx
b6b561c3 7261 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 7262 */
55f9321a 7263static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7264 {1, 241, 2, 2 },
7265 {2, 241, 2, 7 },
7266 {3, 242, 2, 2 },
7267 {4, 242, 2, 7 },
7268 {5, 243, 2, 2 },
7269 {6, 243, 2, 7 },
7270 {7, 244, 2, 2 },
7271 {8, 244, 2, 7 },
7272 {9, 245, 2, 2 },
7273 {10, 245, 2, 7 },
7274 {11, 246, 2, 2 },
7275 {12, 246, 2, 7 },
7276 {13, 247, 2, 2 },
7277 {14, 248, 2, 4 },
55f9321a
ID		 7278
7279 /* 802.11 UNI / HyperLan 2 */
7280 {36, 0x56, 0, 4},
7281 {38, 0x56, 0, 6},
7282 {40, 0x56, 0, 8},
7283 {44, 0x57, 0, 0},
7284 {46, 0x57, 0, 2},
7285 {48, 0x57, 0, 4},
7286 {52, 0x57, 0, 8},
7287 {54, 0x57, 0, 10},
7288 {56, 0x58, 0, 0},
7289 {60, 0x58, 0, 4},
7290 {62, 0x58, 0, 6},
7291 {64, 0x58, 0, 8},
7292
7293 /* 802.11 HyperLan 2 */
7294 {100, 0x5b, 0, 8},
7295 {102, 0x5b, 0, 10},
7296 {104, 0x5c, 0, 0},
7297 {108, 0x5c, 0, 4},
7298 {110, 0x5c, 0, 6},
7299 {112, 0x5c, 0, 8},
7300 {116, 0x5d, 0, 0},
7301 {118, 0x5d, 0, 2},
7302 {120, 0x5d, 0, 4},
7303 {124, 0x5d, 0, 8},
7304 {126, 0x5d, 0, 10},
7305 {128, 0x5e, 0, 0},
7306 {132, 0x5e, 0, 4},
7307 {134, 0x5e, 0, 6},
7308 {136, 0x5e, 0, 8},
7309 {140, 0x5f, 0, 0},
7310
7311 /* 802.11 UNII */
7312 {149, 0x5f, 0, 9},
7313 {151, 0x5f, 0, 11},
7314 {153, 0x60, 0, 1},
7315 {157, 0x60, 0, 5},
7316 {159, 0x60, 0, 7},
7317 {161, 0x60, 0, 9},
7318 {165, 0x61, 0, 1},
7319 {167, 0x61, 0, 3},
7320 {169, 0x61, 0, 5},
7321 {171, 0x61, 0, 7},
7322 {173, 0x61, 0, 9},
4da2933f
BZ		 7323};
7324
7848b231
SG		 7325static const struct rf_channel rf_vals_5592_xtal20[] = {
7326 /* Channel, N, K, mod, R */
7327 {1, 482, 4, 10, 3},
7328 {2, 483, 4, 10, 3},
7329 {3, 484, 4, 10, 3},
7330 {4, 485, 4, 10, 3},
7331 {5, 486, 4, 10, 3},
7332 {6, 487, 4, 10, 3},
7333 {7, 488, 4, 10, 3},
7334 {8, 489, 4, 10, 3},
7335 {9, 490, 4, 10, 3},
7336 {10, 491, 4, 10, 3},
7337 {11, 492, 4, 10, 3},
7338 {12, 493, 4, 10, 3},
7339 {13, 494, 4, 10, 3},
7340 {14, 496, 8, 10, 3},
7341 {36, 172, 8, 12, 1},
7342 {38, 173, 0, 12, 1},
7343 {40, 173, 4, 12, 1},
7344 {42, 173, 8, 12, 1},
7345 {44, 174, 0, 12, 1},
7346 {46, 174, 4, 12, 1},
7347 {48, 174, 8, 12, 1},
7348 {50, 175, 0, 12, 1},
7349 {52, 175, 4, 12, 1},
7350 {54, 175, 8, 12, 1},
7351 {56, 176, 0, 12, 1},
7352 {58, 176, 4, 12, 1},
7353 {60, 176, 8, 12, 1},
7354 {62, 177, 0, 12, 1},
7355 {64, 177, 4, 12, 1},
7356 {100, 183, 4, 12, 1},
7357 {102, 183, 8, 12, 1},
7358 {104, 184, 0, 12, 1},
7359 {106, 184, 4, 12, 1},
7360 {108, 184, 8, 12, 1},
7361 {110, 185, 0, 12, 1},
7362 {112, 185, 4, 12, 1},
7363 {114, 185, 8, 12, 1},
7364 {116, 186, 0, 12, 1},
7365 {118, 186, 4, 12, 1},
7366 {120, 186, 8, 12, 1},
7367 {122, 187, 0, 12, 1},
7368 {124, 187, 4, 12, 1},
7369 {126, 187, 8, 12, 1},
7370 {128, 188, 0, 12, 1},
7371 {130, 188, 4, 12, 1},
7372 {132, 188, 8, 12, 1},
7373 {134, 189, 0, 12, 1},
7374 {136, 189, 4, 12, 1},
7375 {138, 189, 8, 12, 1},
7376 {140, 190, 0, 12, 1},
7377 {149, 191, 6, 12, 1},
7378 {151, 191, 10, 12, 1},
7379 {153, 192, 2, 12, 1},
7380 {155, 192, 6, 12, 1},
7381 {157, 192, 10, 12, 1},
7382 {159, 193, 2, 12, 1},
7383 {161, 193, 6, 12, 1},
7384 {165, 194, 2, 12, 1},
7385 {184, 164, 0, 12, 1},
7386 {188, 164, 4, 12, 1},
7387 {192, 165, 8, 12, 1},
7388 {196, 166, 0, 12, 1},
7389};
7390
7391static const struct rf_channel rf_vals_5592_xtal40[] = {
7392 /* Channel, N, K, mod, R */
7393 {1, 241, 2, 10, 3},
7394 {2, 241, 7, 10, 3},
7395 {3, 242, 2, 10, 3},
7396 {4, 242, 7, 10, 3},
7397 {5, 243, 2, 10, 3},
7398 {6, 243, 7, 10, 3},
7399 {7, 244, 2, 10, 3},
7400 {8, 244, 7, 10, 3},
7401 {9, 245, 2, 10, 3},
7402 {10, 245, 7, 10, 3},
7403 {11, 246, 2, 10, 3},
7404 {12, 246, 7, 10, 3},
7405 {13, 247, 2, 10, 3},
7406 {14, 248, 4, 10, 3},
7407 {36, 86, 4, 12, 1},
7408 {38, 86, 6, 12, 1},
7409 {40, 86, 8, 12, 1},
7410 {42, 86, 10, 12, 1},
7411 {44, 87, 0, 12, 1},
7412 {46, 87, 2, 12, 1},
7413 {48, 87, 4, 12, 1},
7414 {50, 87, 6, 12, 1},
7415 {52, 87, 8, 12, 1},
7416 {54, 87, 10, 12, 1},
7417 {56, 88, 0, 12, 1},
7418 {58, 88, 2, 12, 1},
7419 {60, 88, 4, 12, 1},
7420 {62, 88, 6, 12, 1},
7421 {64, 88, 8, 12, 1},
7422 {100, 91, 8, 12, 1},
7423 {102, 91, 10, 12, 1},
7424 {104, 92, 0, 12, 1},
7425 {106, 92, 2, 12, 1},
7426 {108, 92, 4, 12, 1},
7427 {110, 92, 6, 12, 1},
7428 {112, 92, 8, 12, 1},
7429 {114, 92, 10, 12, 1},
7430 {116, 93, 0, 12, 1},
7431 {118, 93, 2, 12, 1},
7432 {120, 93, 4, 12, 1},
7433 {122, 93, 6, 12, 1},
7434 {124, 93, 8, 12, 1},
7435 {126, 93, 10, 12, 1},
7436 {128, 94, 0, 12, 1},
7437 {130, 94, 2, 12, 1},
7438 {132, 94, 4, 12, 1},
7439 {134, 94, 6, 12, 1},
7440 {136, 94, 8, 12, 1},
7441 {138, 94, 10, 12, 1},
7442 {140, 95, 0, 12, 1},
7443 {149, 95, 9, 12, 1},
7444 {151, 95, 11, 12, 1},
7445 {153, 96, 1, 12, 1},
7446 {155, 96, 3, 12, 1},
7447 {157, 96, 5, 12, 1},
7448 {159, 96, 7, 12, 1},
7449 {161, 96, 9, 12, 1},
7450 {165, 97, 1, 12, 1},
7451 {184, 82, 0, 12, 1},
7452 {188, 82, 4, 12, 1},
7453 {192, 82, 8, 12, 1},
7454 {196, 83, 0, 12, 1},
7455};
7456
ad417a53 7457static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7458{
4da2933f
BZ		 7459 struct hw_mode_spec *spec = &rt2x00dev->spec;
7460 struct channel_info *info;
8d1331b3
ID		 7461 char *default_power1;
7462 char *default_power2;
c0a14369 7463 char *default_power3;
cea5b03d 7464 unsigned int i, tx_chains, rx_chains;
7848b231 7465 u32 reg;
4da2933f 7466
93b6bd26 7467 /*
58e33a21 7468 * Disable powersaving as default.
93b6bd26 7469 */
58e33a21 7470 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 7471
4da2933f
BZ		 7472 /*
7473 * Initialize all hw fields.
7474 */
30686bf7
JB		 7475 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
7476 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
7477 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
7478 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
7479 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9d4f09b8 7480
5a5b6ed6
HS		 7481 /*
7482 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7483 * unless we are capable of sending the buffered frames out after the
7484 * DTIM transmission using rt2x00lib_beacondone. This will send out
7485 * multicast and broadcast traffic immediately instead of buffering it
7486 * infinitly and thus dropping it after some time.
7487 */
7488 if (!rt2x00_is_usb(rt2x00dev))
30686bf7 7489 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
4da2933f 7490
2557654d
CYY		 7491 /* Set MFP if HW crypto is disabled. */
7492 if (rt2800_hwcrypt_disabled(rt2x00dev))
7493 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
7494
4da2933f
BZ		 7495 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7496 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7497 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7498 EEPROM_MAC_ADDR_0));
7499
3f2bee24
HS		 7500 /*
7501 * As rt2800 has a global fallback table we cannot specify
7502 * more then one tx rate per frame but since the hw will
7503 * try several rates (based on the fallback table) we should
ba3b9e5e 7504 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7505 * we are going to try. Otherwise mac80211 will truncate our
7506 * reported tx rates and the rc algortihm will end up with
7507 * incorrect data.
7508 */
ba3b9e5e
HS		 7509 rt2x00dev->hw->max_rates = 1;
7510 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7511 rt2x00dev->hw->max_rate_tries = 1;
7512
4da2933f
BZ		 7513 /*
7514 * Initialize hw_mode information.
7515 */
4da2933f
BZ		 7516 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7517
4a32c36d
GJ		 7518 switch (rt2x00dev->chip.rf) {
7519 case RF2720:
7520 case RF2820:
4da2933f
BZ		 7521 spec->num_channels = 14;
7522 spec->channels = rf_vals;
4a32c36d
GJ		 7523 break;
7524
7525 case RF2750:
7526 case RF2850:
4da2933f
BZ		 7527 spec->num_channels = ARRAY_SIZE(rf_vals);
7528 spec->channels = rf_vals;
4a32c36d
GJ		 7529 break;
7530
7531 case RF2020:
7532 case RF3020:
7533 case RF3021:
7534 case RF3022:
7535 case RF3070:
7536 case RF3290:
7537 case RF3320:
7538 case RF3322:
7539 case RF5360:
ac0372ab 7540 case RF5362:
4a32c36d
GJ		 7541 case RF5370:
7542 case RF5372:
7543 case RF5390:
7544 case RF5392:
55f9321a
ID		 7545 spec->num_channels = 14;
7546 spec->channels = rf_vals_3x;
4a32c36d
GJ		 7547 break;
7548
7549 case RF3052:
7550 case RF3053:
55f9321a
ID		 7551 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7552 spec->channels = rf_vals_3x;
4a32c36d 7553 break;
7848b231 7554
4a32c36d 7555 case RF5592:
7848b231
SG		 7556 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7557 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7558 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7559 spec->channels = rf_vals_5592_xtal40;
7560 } else {
7561 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7562 spec->channels = rf_vals_5592_xtal20;
7563 }
4a32c36d 7564 break;
4da2933f
BZ		 7565 }
7566
53216d6a
SG		 7567 if (WARN_ON_ONCE(!spec->channels))
7568 return -ENODEV;
7569
53c5a099
GJ		 7570 spec->supported_bands = SUPPORT_BAND_2GHZ;
7571 if (spec->num_channels > 14)
7572 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7573
4da2933f
BZ		 7574 /*
7575 * Initialize HT information.
7576 */
5122d898 7577 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7578 spec->ht.ht_supported = true;
7579 else
7580 spec->ht.ht_supported = false;
7581
4da2933f 7582 spec->ht.cap =
06443e46 7583 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7584 IEEE80211_HT_CAP_GRN_FLD |
7585 IEEE80211_HT_CAP_SGI_20 |
aa674631 7586 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7587
cea5b03d
SG		 7588 tx_chains = rt2x00dev->default_ant.tx_chain_num;
7589 rx_chains = rt2x00dev->default_ant.rx_chain_num;
7590
7591 if (tx_chains >= 2)
22cabaa6
HS		 7592 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7593
cea5b03d 7594 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 7595
a08b9819 7596 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
4da2933f 7597 spec->ht.ampdu_density = 4;
cea5b03d
SG		 7598 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7599 if (tx_chains != rx_chains) {
7600 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
7601 spec->ht.mcs.tx_params |=
7602 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
7603 }
4da2933f 7604
cea5b03d 7605 switch (rx_chains) {
4da2933f
BZ		 7606 case 3:
7607 spec->ht.mcs.rx_mask[2] = 0xff;
7608 case 2:
7609 spec->ht.mcs.rx_mask[1] = 0xff;
7610 case 1:
7611 spec->ht.mcs.rx_mask[0] = 0xff;
7612 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7613 break;
7614 }
7615
7616 /*
7617 * Create channel information array
7618 */
baeb2ffa 7619 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7620 if (!info)
7621 return -ENOMEM;
7622
7623 spec->channels_info = info;
7624
3e38d3da
GJ		 7625 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7626 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7627
c0a14369
GJ		 7628 if (rt2x00dev->default_ant.tx_chain_num > 2)
7629 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7630 EEPROM_EXT_TXPOWER_BG3);
7631 else
7632 default_power3 = NULL;
7633
4da2933f 7634 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7635 info[i].default_power1 = default_power1[i];
7636 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7637 if (default_power3)
7638 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7639 }
7640
7641 if (spec->num_channels > 14) {
3e38d3da
GJ		 7642 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7643 EEPROM_TXPOWER_A1);
7644 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7645 EEPROM_TXPOWER_A2);
4da2933f 7646
c0a14369
GJ		 7647 if (rt2x00dev->default_ant.tx_chain_num > 2)
7648 default_power3 =
7649 rt2800_eeprom_addr(rt2x00dev,
7650 EEPROM_EXT_TXPOWER_A3);
7651 else
7652 default_power3 = NULL;
7653
4da2933f 7654 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7655 info[i].default_power1 = default_power1[i - 14];
7656 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7657 if (default_power3)
7658 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7659 }
7660 }
7661
2e9c43dd
JL		 7662 switch (rt2x00dev->chip.rf) {
7663 case RF2020:
7664 case RF3020:
7665 case RF3021:
7666 case RF3022:
7667 case RF3320:
7668 case RF3052:
1095df07 7669 case RF3053:
3b9b74ba 7670 case RF3070:
a89534ed 7671 case RF3290:
ccf91bd6 7672 case RF5360:
ac0372ab 7673 case RF5362:
2e9c43dd
JL		 7674 case RF5370:
7675 case RF5372:
7676 case RF5390:
cff3d1f0 7677 case RF5392:
2e9c43dd
JL		 7678 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7679 break;
7680 }
7681
4da2933f
BZ		 7682 return 0;
7683}
ad417a53 7684
cbafb601
GJ		 7685static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7686{
7687 u32 reg;
7688 u32 rt;
7689 u32 rev;
7690
7691 if (rt2x00_rt(rt2x00dev, RT3290))
7692 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7693 else
7694 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7695
7696 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7697 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7698
7699 switch (rt) {
7700 case RT2860:
7701 case RT2872:
7702 case RT2883:
7703 case RT3070:
7704 case RT3071:
7705 case RT3090:
7706 case RT3290:
7707 case RT3352:
7708 case RT3390:
7709 case RT3572:
2dc2bd2f 7710 case RT3593:
cbafb601
GJ		 7711 case RT5390:
7712 case RT5392:
7713 case RT5592:
7714 break;
7715 default:
ec9c4989
JP		 7716 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7717 rt, rev);
cbafb601
GJ		 7718 return -ENODEV;
7719 }
7720
7721 rt2x00_set_rt(rt2x00dev, rt, rev);
7722
7723 return 0;
7724}
7725
ad417a53
GW		 7726int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7727{
7728 int retval;
7729 u32 reg;
7730
cbafb601
GJ		 7731 retval = rt2800_probe_rt(rt2x00dev);
7732 if (retval)
7733 return retval;
7734
ad417a53
GW		 7735 /*
7736 * Allocate eeprom data.
7737 */
7738 retval = rt2800_validate_eeprom(rt2x00dev);
7739 if (retval)
7740 return retval;
7741
7742 retval = rt2800_init_eeprom(rt2x00dev);
7743 if (retval)
7744 return retval;
7745
7746 /*
7747 * Enable rfkill polling by setting GPIO direction of the
7748 * rfkill switch GPIO pin correctly.
7749 */
7750 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7751 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7752 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7753
7754 /*
7755 * Initialize hw specifications.
7756 */
7757 retval = rt2800_probe_hw_mode(rt2x00dev);
7758 if (retval)
7759 return retval;
7760
7761 /*
7762 * Set device capabilities.
7763 */
7764 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7765 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7766 if (!rt2x00_is_usb(rt2x00dev))
7767 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7768
7769 /*
7770 * Set device requirements.
7771 */
7772 if (!rt2x00_is_soc(rt2x00dev))
7773 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7774 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7775 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7776 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7777 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7778 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7779 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7780 if (rt2x00_is_usb(rt2x00dev))
7781 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7782 else {
7783 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7784 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7785 }
7786
7787 /*
7788 * Set the rssi offset.
7789 */
7790 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7791
7792 return 0;
7793}
7794EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7795
2ce33995
BZ		 7796/*
7797 * IEEE80211 stack callback functions.
7798 */
9352c19f
JB		 7799void rt2800_get_key_seq(struct ieee80211_hw *hw,
7800 struct ieee80211_key_conf *key,
7801 struct ieee80211_key_seq *seq)
2ce33995
BZ		 7802{
7803 struct rt2x00_dev *rt2x00dev = hw->priv;
7804 struct mac_iveiv_entry iveiv_entry;
7805 u32 offset;
7806
9352c19f
JB		 7807 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
7808 return;
7809
7810 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
2ce33995
BZ		 7811 rt2800_register_multiread(rt2x00dev, offset,
7812 &iveiv_entry, sizeof(iveiv_entry));
7813
9352c19f
JB		 7814 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
7815 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
2ce33995 7816}
9352c19f 7817EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
2ce33995 7818
e783619e 7819int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7820{
7821 struct rt2x00_dev *rt2x00dev = hw->priv;
7822 u32 reg;
7823 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7824
7825 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7826 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7827 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7828
7829 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7830 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7831 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7832
7833 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7834 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7835 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7836
7837 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7838 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7839 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7840
7841 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7842 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7843 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7844
7845 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7846 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7847 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7848
7849 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7850 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7851 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7852
7853 return 0;
7854}
e783619e 7855EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7856
8a3a3c85
EP		 7857int rt2800_conf_tx(struct ieee80211_hw *hw,
7858 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7859 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7860{
7861 struct rt2x00_dev *rt2x00dev = hw->priv;
7862 struct data_queue *queue;
7863 struct rt2x00_field32 field;
7864 int retval;
7865 u32 reg;
7866 u32 offset;
7867
7868 /*
7869 * First pass the configuration through rt2x00lib, that will
7870 * update the queue settings and validate the input. After that
7871 * we are free to update the registers based on the value
7872 * in the queue parameter.
7873 */
8a3a3c85 7874 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7875 if (retval)
7876 return retval;
7877
7878 /*
7879 * We only need to perform additional register initialization
7880 * for WMM queues/
7881 */
7882 if (queue_idx >= 4)
7883 return 0;
7884
11f818e0 7885 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7886
7887 /* Update WMM TXOP register */
7888 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7889 field.bit_offset = (queue_idx & 1) * 16;
7890 field.bit_mask = 0xffff << field.bit_offset;
7891
7892 rt2800_register_read(rt2x00dev, offset, &reg);
7893 rt2x00_set_field32(&reg, field, queue->txop);
7894 rt2800_register_write(rt2x00dev, offset, reg);
7895
7896 /* Update WMM registers */
7897 field.bit_offset = queue_idx * 4;
7898 field.bit_mask = 0xf << field.bit_offset;
7899
7900 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7901 rt2x00_set_field32(&reg, field, queue->aifs);
7902 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7903
7904 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7905 rt2x00_set_field32(&reg, field, queue->cw_min);
7906 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7907
7908 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7909 rt2x00_set_field32(&reg, field, queue->cw_max);
7910 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7911
7912 /* Update EDCA registers */
7913 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7914
7915 rt2800_register_read(rt2x00dev, offset, &reg);
7916 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7917 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7918 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7919 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7920 rt2800_register_write(rt2x00dev, offset, reg);
7921
7922 return 0;
7923}
e783619e 7924EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7925
37a41b4a 7926u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7927{
7928 struct rt2x00_dev *rt2x00dev = hw->priv;
7929 u64 tsf;
7930 u32 reg;
7931
7932 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7933 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7934 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7935 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7936
7937 return tsf;
7938}
e783619e 7939EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7940
e783619e 7941int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 7942 struct ieee80211_ampdu_params *params)
1df90809 7943{
50ea05ef
SS		 7944 struct ieee80211_sta *sta = params->sta;
7945 enum ieee80211_ampdu_mlme_action action = params->action;
7946 u16 tid = params->tid;
af35323d 7947 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7948 int ret = 0;
7949
af35323d
HS		 7950 /*
7951 * Don't allow aggregation for stations the hardware isn't aware
7952 * of because tx status reports for frames to an unknown station
ed8e0ed5
SG		 7953 * always contain wcid=WCID_END+1 and thus we can't distinguish
7954 * between multiple stations which leads to unwanted situations
7955 * when the hw reorders frames due to aggregation.
af35323d 7956 */
ed8e0ed5 7957 if (sta_priv->wcid > WCID_END)
af35323d
HS		 7958 return 1;
7959
1df90809
HS		 7960 switch (action) {
7961 case IEEE80211_AMPDU_RX_START:
7962 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7963 /*
7964 * The hw itself takes care of setting up BlockAck mechanisms.
7965 * So, we only have to allow mac80211 to nagotiate a BlockAck
7966 * agreement. Once that is done, the hw will BlockAck incoming
7967 * AMPDUs without further setup.
7968 */
1df90809
HS		 7969 break;
7970 case IEEE80211_AMPDU_TX_START:
7971 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7972 break;
18b559d5
JB		 7973 case IEEE80211_AMPDU_TX_STOP_CONT:
7974 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7975 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7976 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7977 break;
7978 case IEEE80211_AMPDU_TX_OPERATIONAL:
7979 break;
7980 default:
ec9c4989
JP		 7981 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7982 "Unknown AMPDU action\n");
1df90809
HS		 7983 }
7984
7985 return ret;
7986}
e783619e 7987EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 7988
977206d7
HS		 7989int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7990 struct survey_info *survey)
7991{
7992 struct rt2x00_dev *rt2x00dev = hw->priv;
7993 struct ieee80211_conf *conf = &hw->conf;
7994 u32 idle, busy, busy_ext;
7995
7996 if (idx != 0)
7997 return -ENOENT;
7998
675a0b04 7999 survey->channel = conf->chandef.chan;
977206d7
HS		 8000
8001 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8002 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8003 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8004
8005 if (idle || busy) {
4ed20beb
JB		 8006 survey->filled = SURVEY_INFO_TIME |
8007 SURVEY_INFO_TIME_BUSY |
8008 SURVEY_INFO_TIME_EXT_BUSY;
977206d7 8009
4ed20beb
JB		 8010 survey->time = (idle + busy) / 1000;
8011 survey->time_busy = busy / 1000;
8012 survey->time_ext_busy = busy_ext / 1000;
977206d7
HS		 8013 }
8014
9931df26
HS		 8015 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8016 survey->filled |= SURVEY_INFO_IN_USE;
8017
977206d7
HS		 8018 return 0;
8019
8020}
8021EXPORT_SYMBOL_GPL(rt2800_get_survey);
8022
a5ea2f02
ID		 8023MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8024MODULE_VERSION(DRV_VERSION);
8025MODULE_DESCRIPTION("Ralink RT2800 library");
8026MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror