]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/wireless/realtek/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: rtl8192cu: Fix outstanding GCC 6.4.0 warnings
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / realtek / rtl8192cu / hal / rtl8192c / rtl8192c_rf6052.c
CommitLineData
e2251930 1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8a0aaba8 4 *
e2251930 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20/******************************************************************************
8a0aaba8 21 *
22 *
e2251930 23 * Module: rtl8192c_rf6052.c ( Source C File)
8a0aaba8 24 *
25 * Note: Provide RF 6052 series relative API.
e2251930 26 *
8a0aaba8 27 * Function:
28 *
29 * Export:
30 *
31 * Abbrev:
32 *
e2251930 33 * History:
34 * Data Who Remark
8a0aaba8 35 *
e2251930 36 * 09/25/2008 MHC Create initial version.
37 * 11/05/2008 MHC Add API for tw power setting.
8a0aaba8 38 *
39 *
e2251930 40******************************************************************************/
41
42#define _RTL8192C_RF6052_C_
43
44#include <drv_conf.h>
45#include <osdep_service.h>
46#include <drv_types.h>
47#include <rtw_byteorder.h>
48
49#include <rtl8192c_hal.h>
50
51/*---------------------------Define Local Constant---------------------------*/
52// Define local structure for debug!!!!!
53typedef struct RF_Shadow_Compare_Map {
54 // Shadow register value
55 u32 Value;
56 // Compare or not flag
57 u8 Compare;
58 // Record If it had ever modified unpredicted
59 u8 ErrorOrNot;
60 // Recorver Flag
61 u8 Recorver;
62 //
63 u8 Driver_Write;
64}RF_SHADOW_T;
65/*---------------------------Define Local Constant---------------------------*/
66
67
68/*------------------------Define global variable-----------------------------*/
69/*------------------------Define global variable-----------------------------*/
70
71
72/*------------------------Define local variable------------------------------*/
73// 2008/11/20 MH For Debug only, RF
74//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
75static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
76/*------------------------Define local variable------------------------------*/
77
78
79/*-----------------------------------------------------------------------------
80 * Function: RF_ChangeTxPath
81 *
82 * Overview: For RL6052, we must change some RF settign for 1T or 2T.
83 *
84 * Input: u2Byte DataRate // 0x80-8f, 0x90-9f
85 *
86 * Output: NONE
87 *
88 * Return: NONE
89 *
90 * Revised History:
91 * When Who Remark
92 * 09/25/2008 MHC Create Version 0.
93 * Firmwaer support the utility later.
94 *
95 *---------------------------------------------------------------------------*/
8a0aaba8 96void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
e2251930 97 IN u16 DataRate)
98{
99// We do not support gain table change inACUT now !!!! Delete later !!!
100#if 0//(RTL92SE_FPGA_VERIFY == 0)
8a0aaba8 101 static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
102 static u4Byte tx_gain_tbl1[6]
e2251930 103 = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
8a0aaba8 104 static u4Byte tx_gain_tbl2[6]
e2251930 105 = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
106 u1Byte i;
8a0aaba8 107
e2251930 108 if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
109 {
110 // Set TX SYNC power G2G3 loop filter
8a0aaba8 111 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 112 RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
8a0aaba8 113 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 114 RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
115
116 // Change TX AGC gain table
8a0aaba8 117 for (i = 0; i < 6; i++)
118 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 119 RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
120
121 // Set PA to high value
8a0aaba8 122 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 123 RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
124 }
125 else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
126 {
127 // Set TX SYNC power G2G3 loop filter
8a0aaba8 128 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 129 RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
8a0aaba8 130 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 131 RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
132
133 // Change TX AGC gain table
134 for (i = 0; i < 6; i++)
8a0aaba8 135 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 136 RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
137
138 // Set PA low gain
8a0aaba8 139 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
e2251930 140 RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
141 }
8a0aaba8 142#endif
143
e2251930 144} /* RF_ChangeTxPath */
145
146
147/*-----------------------------------------------------------------------------
148 * Function: PHY_RF6052SetBandwidth()
149 *
150 * Overview: This function is called by SetBWModeCallback8190Pci() only
151 *
152 * Input: PADAPTER Adapter
153 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
154 *
155 * Output: NONE
156 *
157 * Return: NONE
158 *
159 * Note: For RF type 0222D
160 *---------------------------------------------------------------------------*/
161VOID
162rtl8192c_PHY_RF6052SetBandwidth(
163 IN PADAPTER Adapter,
164 IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
8a0aaba8 165{
e2251930 166 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8a0aaba8 167
e2251930 168 switch(Bandwidth)
169 {
170 case HT_CHANNEL_WIDTH_20:
171 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
172 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
173 break;
8a0aaba8 174
e2251930 175 case HT_CHANNEL_WIDTH_40:
176 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff));
8a0aaba8 177 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
e2251930 178 break;
8a0aaba8 179
e2251930 180 default:
181 //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
8a0aaba8 182 break;
e2251930 183 }
8a0aaba8 184
e2251930 185}
186
187
188/*-----------------------------------------------------------------------------
189 * Function: PHY_RF6052SetCckTxPower
190 *
8a0aaba8 191 * Overview:
e2251930 192 *
193 * Input: NONE
194 *
195 * Output: NONE
196 *
197 * Return: NONE
198 *
199 * Revised History:
200 * When Who Remark
201 * 11/05/2008 MHC Simulate 8192series..
202 *
203 *---------------------------------------------------------------------------*/
204
205VOID
206rtl8192c_PHY_RF6052SetCckTxPower(
207 IN PADAPTER Adapter,
208 IN u8* pPowerlevel)
209{
210 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
211 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
212 struct dm_priv *pdmpriv = &pHalData->dmpriv;
213 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
8a0aaba8 214 //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
e2251930 215 u32 TxAGC[2]={0, 0}, tmpval=0;
216 BOOLEAN TurboScanOff = _FALSE;
217 u8 idx1, idx2;
218 u8* ptr;
219
8a0aaba8 220 // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU.
e2251930 221 // Otherwise, external PA will be broken if power index > 0x20.
222#ifdef CONFIG_USB_HCI
223 if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA)
224#else
225 if (pHalData->EEPROMRegulatory != 0)
226#endif
227 {
228 //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA);
229 TurboScanOff = _TRUE;
230 }
231
232 if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
233 {
234 TxAGC[RF_PATH_A] = 0x3f3f3f3f;
235 TxAGC[RF_PATH_B] = 0x3f3f3f3f;
236
237 TurboScanOff = _TRUE;//disable turbo scan
8a0aaba8 238
e2251930 239 if(TurboScanOff)
240 {
241 for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
242 {
8a0aaba8 243 TxAGC[idx1] =
e2251930 244 pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
245 (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
246#ifdef CONFIG_USB_HCI
247 // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
248 if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
249 TxAGC[idx1] = 0x20;
250#endif
251 }
252 }
253 }
254 else
255 {
256// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
257// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
258// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
259 if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
8a0aaba8 260 {
e2251930 261 TxAGC[RF_PATH_A] = 0x10101010;
262 TxAGC[RF_PATH_B] = 0x10101010;
263 }
264 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
8a0aaba8 265 {
e2251930 266 TxAGC[RF_PATH_A] = 0x00000000;
267 TxAGC[RF_PATH_B] = 0x00000000;
268 }
269 else
270 {
271 for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
272 {
8a0aaba8 273 TxAGC[idx1] =
e2251930 274 pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
275 (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
276 }
277
278 if(pHalData->EEPROMRegulatory==0)
279 {
8a0aaba8 280 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
e2251930 281 (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
282 TxAGC[RF_PATH_A] += tmpval;
8a0aaba8 283
284 tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
e2251930 285 (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
286 TxAGC[RF_PATH_B] += tmpval;
287 }
288 }
289 }
290
291 for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
292 {
293 ptr = (u8*)(&(TxAGC[idx1]));
294 for(idx2=0; idx2<4; idx2++)
295 {
296 if(*ptr > RF6052_MAX_TX_PWR)
297 *ptr = RF6052_MAX_TX_PWR;
298 ptr++;
299 }
300 }
301
302 // rf-A cck tx power
303 tmpval = TxAGC[RF_PATH_A]&0xff;
304 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
305 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
306 tmpval = TxAGC[RF_PATH_A]>>8;
307 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
308 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
309
310 // rf-B cck tx power
311 tmpval = TxAGC[RF_PATH_B]>>24;
312 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
313 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
314 tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
315 PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
8a0aaba8 316 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
e2251930 317 // tmpval, rTxAGC_B_CCK1_55_Mcs32));
8a0aaba8 318
e2251930 319} /* PHY_RF6052SetCckTxPower */
320
321//
322// powerbase0 for OFDM rates
323// powerbase1 for HT MCS rates
324//
325static void getPowerBase(
326 IN PADAPTER Adapter,
327 IN u8* pPowerLevel,
328 IN u8 Channel,
329 IN OUT u32* OfdmBase,
330 IN OUT u32* MCSBase
331 )
332{
333 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
334 u32 powerBase0, powerBase1;
335 u8 Legacy_pwrdiff=0;
336 s8 HT20_pwrdiff=0;
337 u8 i, powerlevel[2];
338
339 for(i=0; i<2; i++)
340 {
341 powerlevel[i] = pPowerLevel[i];
8a0aaba8 342 Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
343 powerBase0 = powerlevel[i] + Legacy_pwrdiff;
e2251930 344
345 powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
346 *(OfdmBase+i) = powerBase0;
347 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
348 }
349
350 for(i=0; i<2; i++)
351 {
352 //Check HT20 to HT40 diff
353 if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
354 {
355 HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
356 powerlevel[i] += HT20_pwrdiff;
357 }
358 powerBase1 = powerlevel[i];
359 powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
360 *(MCSBase+i) = powerBase1;
361 //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
362 }
363}
364
365static void getTxPowerWriteValByRegulatory(
366 IN PADAPTER Adapter,
367 IN u8 Channel,
368 IN u8 index,
369 IN u32* powerBase0,
370 IN u32* powerBase1,
371 OUT u32* pOutWriteVal
372 )
373{
374 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
375 struct dm_priv *pdmpriv = &pHalData->dmpriv;
43a45cd7 376 u8 i, chnlGroup = 0, pwr_diff_limit[4];
e2251930 377 u32 writeVal, customer_limit, rf;
8a0aaba8 378
e2251930 379 //
380 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
381 //
382 for(rf=0; rf<2; rf++)
383 {
384 switch(pHalData->EEPROMRegulatory)
385 {
386 case 0: // Realtek better performance
387 // increase power diff defined by Realtek for large power
388 chnlGroup = 0;
8a0aaba8 389 //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
e2251930 390 // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
8a0aaba8 391 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
e2251930 392 ((index<2)?powerBase0[rf]:powerBase1[rf]);
393 //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
394 break;
395 case 1: // Realtek regulatory
396 // increase power diff defined by Realtek for regulatory
397 {
398 if(pHalData->pwrGroupCnt == 1)
399 chnlGroup = 0;
400 if(pHalData->pwrGroupCnt >= 3)
401 {
402 if(Channel <= 3)
403 chnlGroup = 0;
404 else if(Channel >= 4 && Channel <= 9)
405 chnlGroup = 1;
406 else if(Channel > 9)
407 chnlGroup = 2;
408
409 if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
410 chnlGroup++;
411 else
412 chnlGroup+=4;
413 }
8a0aaba8 414 //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
e2251930 415 //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
8a0aaba8 416 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
e2251930 417 ((index<2)?powerBase0[rf]:powerBase1[rf]);
418 //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
419 }
420 break;
421 case 2: // Better regulatory
422 // don't increase any power diff
423 writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
424 //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
425 break;
426 case 3: // Customer defined power diff.
427 // increase power diff defined by customer.
428 chnlGroup = 0;
8a0aaba8 429 //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
e2251930 430 // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
431
432 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
433 {
8a0aaba8 434 //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
e2251930 435 // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
436 }
437 else
438 {
8a0aaba8 439 //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
e2251930 440 // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
441 }
442 for (i=0; i<4; i++)
443 {
444 pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
445 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
446 {
447 if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
448 pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
449 }
450 else
451 {
452 if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
453 pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
454 }
455 }
456 customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
457 (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
458 //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
459
460 writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
461 //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
462 break;
463 default:
464 chnlGroup = 0;
8a0aaba8 465 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
e2251930 466 ((index<2)?powerBase0[rf]:powerBase1[rf]);
467 //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
468 break;
469 }
470
471// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
472// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
473// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
474
475 if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
476 writeVal = 0x14141414;
477 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
478 writeVal = 0x00000000;
479
480
481 // 20100628 Joseph: High power mode for BT-Coexist mechanism.
482 // This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
483 if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
484 {
485 //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
486 writeVal = writeVal - 0x06060606;
487 }
488 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
489 {
490 //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
491 writeVal = writeVal;
492 }
493 *(pOutWriteVal+rf) = writeVal;
494 }
495}
496
497static void writeOFDMPowerReg(
498 IN PADAPTER Adapter,
499 IN u8 index,
500 IN u32* pValue
501 )
502{
503 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8a0aaba8 504 u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
505 rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
e2251930 506 rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
8a0aaba8 507 u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
e2251930 508 rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
509 rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
510 u8 i, rf, pwr_val[4];
511 u32 writeVal;
512 u16 RegOffset;
513
514 for(rf=0; rf<2; rf++)
515 {
516 writeVal = pValue[rf];
517 for(i=0; i<4; i++)
518 {
519 pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
520 if (pwr_val[i] > RF6052_MAX_TX_PWR)
521 pwr_val[i] = RF6052_MAX_TX_PWR;
522 }
523 writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
524
525 if(rf == 0)
526 RegOffset = RegOffset_A[index];
527 else
528 RegOffset = RegOffset_B[index];
8a0aaba8 529
e2251930 530 PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
531 //RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
532
533 // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
8a0aaba8 534 if(((pHalData->rf_type == RF_2T2R) &&
e2251930 535 (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
8a0aaba8 536 ((pHalData->rf_type != RF_2T2R) &&
e2251930 537 (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
538 {
539 writeVal = pwr_val[3];
540 if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
541 RegOffset = 0xc90;
542 if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
543 RegOffset = 0xc98;
544 for(i=0; i<3; i++)
545 {
546 if(i!=2)
547 writeVal = (writeVal>8)?(writeVal-8):0;
548 else
549 writeVal = (writeVal>6)?(writeVal-6):0;
550 rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
551 }
552 }
553 }
554}
555/*-----------------------------------------------------------------------------
556 * Function: PHY_RF6052SetOFDMTxPower
557 *
8a0aaba8 558 * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
e2251930 559 * different channel and read original value in TX power register area from
560 * 0xe00. We increase offset and original value to be correct tx pwr.
561 *
562 * Input: NONE
563 *
564 * Output: NONE
565 *
566 * Return: NONE
567 *
568 * Revised History:
569 * When Who Remark
570 * 11/05/2008 MHC Simulate 8192 series method.
571 * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
572 * A/B pwr difference or legacy/HT pwr diff.
573 * 2. We concern with path B legacy/HT OFDM difference.
574 * 01/22/2009 MHC Support new EPRO format from SD3.
575 *
576 *---------------------------------------------------------------------------*/
8a0aaba8 577VOID
e2251930 578rtl8192c_PHY_RF6052SetOFDMTxPower(
579 IN PADAPTER Adapter,
580 IN u8* pPowerLevel,
581 IN u8 Channel)
582{
583 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
584 u32 writeVal[2], powerBase0[2], powerBase1[2];
585 u8 index = 0;
586
587 getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]);
588
589 for(index=0; index<6; index++)
590 {
8a0aaba8 591 getTxPowerWriteValByRegulatory(Adapter, Channel, index,
e2251930 592 &powerBase0[0], &powerBase1[0], &writeVal[0]);
593
594 writeOFDMPowerReg(Adapter, index, &writeVal[0]);
595 }
8a0aaba8 596
e2251930 597}
598
599
600static VOID
601phy_RF6052_Config_HardCode(
602 IN PADAPTER Adapter
603 )
604{
8a0aaba8 605
e2251930 606 // Set Default Bandwidth to 20M
607 //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
608
609 // TODO: Set Default Channel to channel one for RTL8225
8a0aaba8 610
e2251930 611}
612
613static int
614phy_RF6052_Config_ParaFile(
615 IN PADAPTER Adapter
616 )
617{
43a45cd7 618 u32 u4RegValue=0;
8a0aaba8 619 u8 eRFPath;
620 BB_REGISTER_DEFINITION_T *pPhyReg;
e2251930 621
622 int rtStatus = _SUCCESS;
623 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8a0aaba8 624 static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
e2251930 625 static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
626#ifdef CONFIG_USB_HCI
8a0aaba8 627 static char sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard;
e2251930 628 static char sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard;
8a0aaba8 629 static char sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP;
e2251930 630#endif
8a0aaba8 631 static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
e2251930 632 static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
8a0aaba8 633 static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A;
e2251930 634 static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B;
8a0aaba8 635 char *pszRadioAFile, *pszRadioBFile;
e2251930 636
637
638 if(IS_HARDWARE_TYPE_8192C(Adapter))
639 {
640 if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
641 {
642 pszRadioAFile = sz92CRadioAFile;
643 pszRadioBFile = sz92CRadioBFile;
644 }
645 else
646 {
647 pszRadioAFile = sz88CRadioAFile;
648 pszRadioBFile = sz88CRadioBFile;
649#ifdef CONFIG_USB_HCI
650 if( BOARD_MINICARD == pHalData->BoardType)
651 {
652 pszRadioAFile = sz88CRadioAFile_mCard;
653 pszRadioBFile = sz88CRadioBFile_mCard;
654 }
655 else if( BOARD_USB_High_PA == pHalData->BoardType)
656 {
657 pszRadioAFile = sz88CRadioAFile_HP;
658 }
8a0aaba8 659#endif
e2251930 660 }
661 }
662 else if(IS_HARDWARE_TYPE_8723A(Adapter))
663 {
664 pszRadioAFile = sz8723RadioAFile;
8a0aaba8 665 pszRadioBFile = sz8723RadioBFile;
e2251930 666 }
667
668 //3//-----------------------------------------------------------------
669 //3// <2> Initialize RF
670 //3//-----------------------------------------------------------------
671 //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
672 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
673 {
674
675 pPhyReg = &pHalData->PHYRegDef[eRFPath];
8a0aaba8 676
677 /*----Store original RFENV control type----*/
e2251930 678 switch(eRFPath)
679 {
680 case RF_PATH_A:
681 case RF_PATH_C:
682 u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
683 break;
684 case RF_PATH_B :
685 case RF_PATH_D:
686 u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
687 break;
688 }
689
8a0aaba8 690 /*----Set RF_ENV enable----*/
e2251930 691 PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
692 rtw_udelay_os(1);//PlatformStallExecution(1);
8a0aaba8 693
e2251930 694 /*----Set RF_ENV output high----*/
695 PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
696 rtw_udelay_os(1);//PlatformStallExecution(1);
697
698 /* Set bit number of Address and Data for RF register */
699 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
700 rtw_udelay_os(1);//PlatformStallExecution(1);
701
702 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
703 rtw_udelay_os(1);//PlatformStallExecution(1);
704
705 /*----Initialize RF fom connfiguration file----*/
706 switch(eRFPath)
707 {
708 case RF_PATH_A:
709#ifdef CONFIG_EMBEDDED_FWIMG
710 rtStatus= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
711#else
712 rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
713#endif
714 break;
715 case RF_PATH_B:
716#ifdef CONFIG_EMBEDDED_FWIMG
717 rtStatus = rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
8a0aaba8 718#else
e2251930 719 rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
720#endif
721 break;
722 case RF_PATH_C:
723 break;
724 case RF_PATH_D:
725 break;
726 }
727
728 /*----Restore RFENV control type----*/;
729 switch(eRFPath)
730 {
731 case RF_PATH_A:
732 case RF_PATH_C:
733 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
734 break;
735 case RF_PATH_B :
736 case RF_PATH_D:
737 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
738 break;
739 }
740
741 if(rtStatus != _SUCCESS){
742 //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
743 goto phy_RF6052_Config_ParaFile_Fail;
744 }
745
746 }
747
748 //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
749 return rtStatus;
8a0aaba8 750
751phy_RF6052_Config_ParaFile_Fail:
e2251930 752 return rtStatus;
753}
754
755
756int
757PHY_RF6052_Config8192C(
758 IN PADAPTER Adapter)
759{
760 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8a0aaba8 761 int rtStatus = _SUCCESS;
762
e2251930 763 //
764 // Initialize general global value
765 //
766 // TODO: Extend RF_PATH_C and RF_PATH_D in the future
767 if(pHalData->rf_type == RF_1T1R)
768 pHalData->NumTotalRFPath = 1;
769 else
770 pHalData->NumTotalRFPath = 2;
771
772 //
773 // Config BB and RF
774 //
775 rtStatus = phy_RF6052_Config_ParaFile(Adapter);
8a0aaba8 776#if 0
e2251930 777 switch( Adapter->MgntInfo.bRegHwParaFile )
778 {
779 case 0:
780 phy_RF6052_Config_HardCode(Adapter);
781 break;
782
783 case 1:
784 rtStatus = phy_RF6052_Config_ParaFile(Adapter);
785 break;
786
787 case 2:
8a0aaba8 788 // Partial Modify.
e2251930 789 phy_RF6052_Config_HardCode(Adapter);
790 phy_RF6052_Config_ParaFile(Adapter);
791 break;
792
793 default:
794 phy_RF6052_Config_HardCode(Adapter);
795 break;
796 }
8a0aaba8 797#endif
e2251930 798 return rtStatus;
8a0aaba8 799
e2251930 800}
801
802
803//
804// ==> RF shadow Operation API Code Section!!!
805//
806/*-----------------------------------------------------------------------------
807 * Function: PHY_RFShadowRead
808 * PHY_RFShadowWrite
809 * PHY_RFShadowCompare
810 * PHY_RFShadowRecorver
811 * PHY_RFShadowCompareAll
812 * PHY_RFShadowRecorverAll
813 * PHY_RFShadowCompareFlagSet
814 * PHY_RFShadowRecorverFlagSet
815 *
816 * Overview: When we set RF register, we must write shadow at first.
817 * When we are running, we must compare shadow abd locate error addr.
818 * Decide to recorver or not.
819 *
820 * Input: NONE
821 *
822 * Output: NONE
823 *
824 * Return: NONE
825 *
826 * Revised History:
827 * When Who Remark
828 * 11/20/2008 MHC Create Version 0.
829 *
830 *---------------------------------------------------------------------------*/
831u32
832PHY_RFShadowRead(
833 IN PADAPTER Adapter,
834 IN RF_RADIO_PATH_E eRFPath,
835 IN u32 Offset)
836{
837 return RF_Shadow[eRFPath][Offset].Value;
8a0aaba8 838
e2251930 839} /* PHY_RFShadowRead */
840
841
842VOID
843PHY_RFShadowWrite(
844 IN PADAPTER Adapter,
845 IN RF_RADIO_PATH_E eRFPath,
846 IN u32 Offset,
847 IN u32 Data)
848{
849 RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
850 RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
8a0aaba8 851
e2251930 852} /* PHY_RFShadowWrite */
853
854
855BOOLEAN
856PHY_RFShadowCompare(
857 IN PADAPTER Adapter,
858 IN RF_RADIO_PATH_E eRFPath,
859 IN u32 Offset)
860{
861 u32 reg;
862 // Check if we need to check the register
863 if (RF_Shadow[eRFPath][Offset].Compare == _TRUE)
864 {
865 reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
866 // Compare shadow and real rf register for 20bits!!
867 if (RF_Shadow[eRFPath][Offset].Value != reg)
868 {
869 // Locate error position.
870 RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
8a0aaba8 871 //RT_TRACE(COMP_INIT, DBG_LOUD,
872 //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",
e2251930 873 //eRFPath, Offset, reg));
874 }
875 return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
876 }
877 return _FALSE;
878} /* PHY_RFShadowCompare */
879
880
881VOID
882PHY_RFShadowRecorver(
883 IN PADAPTER Adapter,
884 IN RF_RADIO_PATH_E eRFPath,
885 IN u32 Offset)
886{
887 // Check if the address is error
888 if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE)
889 {
890 // Check if we need to recorver the register.
891 if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE)
892 {
8a0aaba8 893 PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
e2251930 894 RF_Shadow[eRFPath][Offset].Value);
8a0aaba8 895 //RT_TRACE(COMP_INIT, DBG_LOUD,
896 //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
e2251930 897 //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
898 }
899 }
8a0aaba8 900
e2251930 901} /* PHY_RFShadowRecorver */
902
903
904VOID
905PHY_RFShadowCompareAll(
906 IN PADAPTER Adapter)
907{
908 u32 eRFPath;
909 u32 Offset;
910
911 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
912 {
913 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
914 {
915 PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
916 }
917 }
8a0aaba8 918
e2251930 919} /* PHY_RFShadowCompareAll */
920
921
922VOID
923PHY_RFShadowRecorverAll(
924 IN PADAPTER Adapter)
925{
926 u32 eRFPath;
927 u32 Offset;
928
929 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
930 {
931 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
932 {
933 PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
934 }
935 }
8a0aaba8 936
e2251930 937} /* PHY_RFShadowRecorverAll */
938
939
940VOID
941PHY_RFShadowCompareFlagSet(
942 IN PADAPTER Adapter,
943 IN RF_RADIO_PATH_E eRFPath,
944 IN u32 Offset,
945 IN u8 Type)
946{
947 // Set True or False!!!
948 RF_Shadow[eRFPath][Offset].Compare = Type;
8a0aaba8 949
e2251930 950} /* PHY_RFShadowCompareFlagSet */
951
952
953VOID
954PHY_RFShadowRecorverFlagSet(
955 IN PADAPTER Adapter,
956 IN RF_RADIO_PATH_E eRFPath,
957 IN u32 Offset,
958 IN u8 Type)
959{
960 // Set True or False!!!
961 RF_Shadow[eRFPath][Offset].Recorver= Type;
8a0aaba8 962
e2251930 963} /* PHY_RFShadowRecorverFlagSet */
964
965
966VOID
967PHY_RFShadowCompareFlagSetAll(
968 IN PADAPTER Adapter)
969{
970 u32 eRFPath;
971 u32 Offset;
972
973 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
974 {
975 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
976 {
977 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
978 if (Offset != 0x26 && Offset != 0x27)
979 PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);
980 else
981 PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);
982 }
983 }
8a0aaba8 984
e2251930 985} /* PHY_RFShadowCompareFlagSetAll */
986
987
988VOID
989PHY_RFShadowRecorverFlagSetAll(
990 IN PADAPTER Adapter)
991{
992 u32 eRFPath;
993 u32 Offset;
994
995 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
996 {
997 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
998 {
999 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
1000 if (Offset != 0x26 && Offset != 0x27)
1001 PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);
1002 else
1003 PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);
1004 }
1005 }
8a0aaba8 1006
e2251930 1007} /* PHY_RFShadowCompareFlagSetAll */
1008
1009VOID
1010PHY_RFShadowRefresh(
1011 IN PADAPTER Adapter)
1012{
1013 u32 eRFPath;
1014 u32 Offset;
1015
1016 for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
1017 {
9b7bc9f5 1018 for (Offset = 0; Offset < RF6052_MAX_REG; Offset++)
e2251930 1019 {
1020 RF_Shadow[eRFPath][Offset].Value = 0;
1021 RF_Shadow[eRFPath][Offset].Compare = _FALSE;
1022 RF_Shadow[eRFPath][Offset].Recorver = _FALSE;
1023 RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;
1024 RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;
1025 }
1026 }
8a0aaba8 1027
e2251930 1028} /* PHY_RFShadowRead */
1029
1030/* End of HalRf6052.c */
8a0aaba8 1031
ubuntu-bionic-kernel mirror