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5b497af4 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
26f1fad2 | 2 | /* |
1ee83789 | 3 | * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> |
26f1fad2 | 4 | * |
26f1fad2 JS |
5 | * Register definitions taken from original Realtek rtl8723au driver |
6 | */ | |
7 | ||
8 | /* 0x0000 ~ 0x00FF System Configuration */ | |
9 | #define REG_SYS_ISO_CTRL 0x0000 | |
10 | #define SYS_ISO_MD2PP BIT(0) | |
11 | #define SYS_ISO_ANALOG_IPS BIT(5) | |
12 | #define SYS_ISO_DIOR BIT(9) | |
13 | #define SYS_ISO_PWC_EV25V BIT(14) | |
14 | #define SYS_ISO_PWC_EV12V BIT(15) | |
15 | ||
16 | #define REG_SYS_FUNC 0x0002 | |
17 | #define SYS_FUNC_BBRSTB BIT(0) | |
18 | #define SYS_FUNC_BB_GLB_RSTN BIT(1) | |
19 | #define SYS_FUNC_USBA BIT(2) | |
20 | #define SYS_FUNC_UPLL BIT(3) | |
21 | #define SYS_FUNC_USBD BIT(4) | |
22 | #define SYS_FUNC_DIO_PCIE BIT(5) | |
23 | #define SYS_FUNC_PCIEA BIT(6) | |
24 | #define SYS_FUNC_PPLL BIT(7) | |
25 | #define SYS_FUNC_PCIED BIT(8) | |
26 | #define SYS_FUNC_DIOE BIT(9) | |
27 | #define SYS_FUNC_CPU_ENABLE BIT(10) | |
28 | #define SYS_FUNC_DCORE BIT(11) | |
29 | #define SYS_FUNC_ELDR BIT(12) | |
30 | #define SYS_FUNC_DIO_RF BIT(13) | |
31 | #define SYS_FUNC_HWPDN BIT(14) | |
32 | #define SYS_FUNC_MREGEN BIT(15) | |
33 | ||
34 | #define REG_APS_FSMCO 0x0004 | |
35 | #define APS_FSMCO_PFM_ALDN BIT(1) | |
36 | #define APS_FSMCO_PFM_WOWL BIT(3) | |
37 | #define APS_FSMCO_ENABLE_POWERDOWN BIT(4) | |
38 | #define APS_FSMCO_MAC_ENABLE BIT(8) | |
39 | #define APS_FSMCO_MAC_OFF BIT(9) | |
5b22a111 | 40 | #define APS_FSMCO_SW_LPS BIT(10) |
26f1fad2 JS |
41 | #define APS_FSMCO_HW_SUSPEND BIT(11) |
42 | #define APS_FSMCO_PCIE BIT(12) | |
43 | #define APS_FSMCO_HW_POWERDOWN BIT(15) | |
44 | #define APS_FSMCO_WLON_RESET BIT(16) | |
45 | ||
46 | #define REG_SYS_CLKR 0x0008 | |
47 | #define SYS_CLK_ANAD16V_ENABLE BIT(0) | |
48 | #define SYS_CLK_ANA8M BIT(1) | |
49 | #define SYS_CLK_MACSLP BIT(4) | |
50 | #define SYS_CLK_LOADER_ENABLE BIT(5) | |
51 | #define SYS_CLK_80M_SSC_DISABLE BIT(7) | |
52 | #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) | |
53 | #define SYS_CLK_PHY_SSC_RSTB BIT(9) | |
54 | #define SYS_CLK_SEC_CLK_ENABLE BIT(10) | |
55 | #define SYS_CLK_MAC_CLK_ENABLE BIT(11) | |
56 | #define SYS_CLK_ENABLE BIT(12) | |
57 | #define SYS_CLK_RING_CLK_ENABLE BIT(13) | |
58 | ||
59 | #define REG_9346CR 0x000a | |
60 | #define EEPROM_BOOT BIT(4) | |
61 | #define EEPROM_ENABLE BIT(5) | |
62 | ||
63 | #define REG_EE_VPD 0x000c | |
64 | #define REG_AFE_MISC 0x0010 | |
42836db1 JS |
65 | #define AFE_MISC_WL_XTAL_CTRL BIT(6) |
66 | ||
26f1fad2 JS |
67 | #define REG_SPS0_CTRL 0x0011 |
68 | #define REG_SPS_OCP_CFG 0x0018 | |
c05a9dbf | 69 | #define REG_8192E_LDOV12_CTRL 0x0014 |
26f1fad2 JS |
70 | #define REG_RSV_CTRL 0x001c |
71 | ||
72 | #define REG_RF_CTRL 0x001f | |
73 | #define RF_ENABLE BIT(0) | |
74 | #define RF_RSTB BIT(1) | |
75 | #define RF_SDMRSTB BIT(2) | |
76 | ||
77 | #define REG_LDOA15_CTRL 0x0020 | |
78 | #define LDOA15_ENABLE BIT(0) | |
79 | #define LDOA15_STANDBY BIT(1) | |
80 | #define LDOA15_OBUF BIT(2) | |
81 | #define LDOA15_REG_VOS BIT(3) | |
82 | #define LDOA15_VOADJ_SHIFT 4 | |
83 | ||
84 | #define REG_LDOV12D_CTRL 0x0021 | |
85 | #define LDOV12D_ENABLE BIT(0) | |
86 | #define LDOV12D_STANDBY BIT(1) | |
87 | #define LDOV12D_VADJ_SHIFT 4 | |
88 | ||
89 | #define REG_LDOHCI12_CTRL 0x0022 | |
90 | ||
91 | #define REG_LPLDO_CTRL 0x0023 | |
92 | #define LPLDO_HSM BIT(2) | |
93 | #define LPLDO_LSM_DIS BIT(3) | |
94 | ||
95 | #define REG_AFE_XTAL_CTRL 0x0024 | |
96 | #define AFE_XTAL_ENABLE BIT(0) | |
97 | #define AFE_XTAL_B_SELECT BIT(1) | |
98 | #define AFE_XTAL_GATE_USB BIT(8) | |
99 | #define AFE_XTAL_GATE_AFE BIT(11) | |
100 | #define AFE_XTAL_RF_GATE BIT(14) | |
101 | #define AFE_XTAL_GATE_DIG BIT(17) | |
102 | #define AFE_XTAL_BT_GATE BIT(20) | |
103 | ||
28e460b0 JS |
104 | /* |
105 | * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu | |
106 | */ | |
26f1fad2 JS |
107 | #define REG_AFE_PLL_CTRL 0x0028 |
108 | #define AFE_PLL_ENABLE BIT(0) | |
109 | #define AFE_PLL_320_ENABLE BIT(1) | |
110 | #define APE_PLL_FREF_SELECT BIT(2) | |
111 | #define AFE_PLL_EDGE_SELECT BIT(3) | |
112 | #define AFE_PLL_WDOGB BIT(4) | |
113 | #define AFE_PLL_LPF_ENABLE BIT(5) | |
114 | ||
115 | #define REG_MAC_PHY_CTRL 0x002c | |
116 | ||
117 | #define REG_EFUSE_CTRL 0x0030 | |
118 | #define REG_EFUSE_TEST 0x0034 | |
119 | #define EFUSE_TRPT BIT(7) | |
120 | /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ | |
121 | #define EFUSE_CELL_SEL (BIT(8) | BIT(9)) | |
122 | #define EFUSE_LDOE25_ENABLE BIT(31) | |
123 | #define EFUSE_SELECT_MASK 0x0300 | |
124 | #define EFUSE_WIFI_SELECT 0x0000 | |
125 | #define EFUSE_BT0_SELECT 0x0100 | |
126 | #define EFUSE_BT1_SELECT 0x0200 | |
127 | #define EFUSE_BT2_SELECT 0x0300 | |
128 | ||
129 | #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ | |
130 | #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ | |
131 | ||
132 | #define REG_PWR_DATA 0x0038 | |
37f44dc7 | 133 | #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) |
42836db1 | 134 | |
26f1fad2 JS |
135 | #define REG_CAL_TIMER 0x003c |
136 | #define REG_ACLK_MON 0x003e | |
137 | #define REG_GPIO_MUXCFG 0x0040 | |
138 | #define REG_GPIO_IO_SEL 0x0042 | |
139 | #define REG_MAC_PINMUX_CFG 0x0043 | |
140 | #define REG_GPIO_PIN_CTRL 0x0044 | |
141 | #define REG_GPIO_INTM 0x0048 | |
42836db1 JS |
142 | #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) |
143 | ||
26f1fad2 | 144 | #define REG_LEDCFG0 0x004c |
42836db1 | 145 | #define LEDCFG0_DPDT_SELECT BIT(23) |
26f1fad2 JS |
146 | #define REG_LEDCFG1 0x004d |
147 | #define REG_LEDCFG2 0x004e | |
148 | #define LEDCFG2_DPDT_SELECT BIT(7) | |
149 | #define REG_LEDCFG3 0x004f | |
150 | #define REG_LEDCFG REG_LEDCFG2 | |
151 | #define REG_FSIMR 0x0050 | |
152 | #define REG_FSISR 0x0054 | |
153 | #define REG_HSIMR 0x0058 | |
154 | #define REG_HSISR 0x005c | |
155 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ | |
156 | #define REG_GPIO_PIN_CTRL_2 0x0060 | |
157 | /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ | |
158 | #define REG_GPIO_IO_SEL_2 0x0062 | |
42836db1 JS |
159 | #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) |
160 | #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) | |
26f1fad2 | 161 | |
14d88560 JS |
162 | /* RTL8723B */ |
163 | #define REG_PAD_CTRL1 0x0064 | |
42836db1 JS |
164 | #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) |
165 | ||
26f1fad2 JS |
166 | /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ |
167 | #define REG_MULTI_FUNC_CTRL 0x0068 | |
168 | ||
169 | #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW | |
170 | powerdown source */ | |
171 | #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity | |
172 | control */ | |
173 | #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ | |
174 | ||
175 | #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW | |
176 | powerdown source */ | |
177 | #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW | |
178 | powerdown source */ | |
179 | #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity | |
180 | control */ | |
181 | #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ | |
182 | #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS | |
183 | RF HW powerdown source */ | |
184 | #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW | |
185 | powerdown source */ | |
186 | #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity | |
187 | control */ | |
188 | #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ | |
189 | ||
28e460b0 | 190 | #define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ |
c05a9dbf JS |
191 | #define REG_LDO_SW_CTRL 0x007c /* 8192eu */ |
192 | ||
26f1fad2 JS |
193 | #define REG_MCU_FW_DL 0x0080 |
194 | #define MCU_FW_DL_ENABLE BIT(0) | |
195 | #define MCU_FW_DL_READY BIT(1) | |
196 | #define MCU_FW_DL_CSUM_REPORT BIT(2) | |
197 | #define MCU_MAC_INIT_READY BIT(3) | |
198 | #define MCU_BB_INIT_READY BIT(4) | |
199 | #define MCU_RF_INIT_READY BIT(5) | |
200 | #define MCU_WINT_INIT_READY BIT(6) | |
201 | #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ | |
202 | #define MCU_CP_RESET BIT(23) | |
203 | ||
204 | #define REG_HMBOX_EXT_0 0x0088 | |
205 | #define REG_HMBOX_EXT_1 0x008a | |
206 | #define REG_HMBOX_EXT_2 0x008c | |
207 | #define REG_HMBOX_EXT_3 0x008e | |
0b096289 | 208 | |
14d88560 | 209 | /* Interrupt registers for 8192e/8723bu/8812 */ |
99ad16cb | 210 | #define REG_HIMR0 0x00b0 |
0b096289 JS |
211 | #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit |
212 | of the packet is set */ | |
213 | #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ | |
214 | #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ | |
215 | #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ | |
216 | #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ | |
217 | #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ | |
218 | #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle | |
219 | indication interrupt */ | |
220 | #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ | |
221 | #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ | |
222 | #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & | |
223 | HSISR is true) */ | |
224 | #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt | |
225 | Extension for Win7 */ | |
226 | #define IMR0_ATIMEND BIT(12) /* CTWidnow End or | |
227 | ATIM Window End */ | |
228 | #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator | |
229 | (HISR1 & HIMR1 is true) */ | |
230 | #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT | |
231 | Status, Write 1 to clear */ | |
232 | #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT | |
233 | Status, Write 1 to clear */ | |
234 | #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT | |
235 | Status, Write 1 to clear */ | |
236 | #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ | |
237 | #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ | |
238 | #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ | |
239 | #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ | |
240 | #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ | |
241 | #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ | |
242 | #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ | |
243 | #define IMR0_ROK BIT(0) /* Receive DMA OK */ | |
14d88560 | 244 | #define REG_HISR0 0x00b4 |
99ad16cb | 245 | #define REG_HIMR1 0x00b8 |
0b096289 JS |
246 | #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ |
247 | #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ | |
248 | #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ | |
249 | #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ | |
250 | #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ | |
251 | #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ | |
252 | #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ | |
253 | #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ | |
254 | #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ | |
255 | #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ | |
256 | #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ | |
257 | #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ | |
258 | #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ | |
259 | #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ | |
260 | #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension | |
261 | for Win7 */ | |
262 | #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, | |
263 | write 1 to clear */ | |
264 | #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, | |
265 | write 1 to clear */ | |
266 | #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ | |
267 | #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ | |
14d88560 | 268 | #define REG_HISR1 0x00bc |
99ad16cb | 269 | |
26f1fad2 JS |
270 | /* Host suspend counter on FPGA platform */ |
271 | #define REG_HOST_SUSP_CNT 0x00bc | |
272 | /* Efuse access protection for RTL8723 */ | |
273 | #define REG_EFUSE_ACCESS 0x00cf | |
274 | #define REG_BIST_SCAN 0x00d0 | |
275 | #define REG_BIST_RPT 0x00d4 | |
276 | #define REG_BIST_ROM_RPT 0x00d8 | |
277 | #define REG_USB_SIE_INTF 0x00e0 | |
278 | #define REG_PCIE_MIO_INTF 0x00e4 | |
279 | #define REG_PCIE_MIO_INTD 0x00e8 | |
280 | #define REG_HPON_FSM 0x00ec | |
281 | #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) | |
282 | #define HPON_FSM_BONDING_1T2R BIT(22) | |
283 | #define REG_SYS_CFG 0x00f0 | |
284 | #define SYS_CFG_XCLK_VLD BIT(0) | |
285 | #define SYS_CFG_ACLK_VLD BIT(1) | |
286 | #define SYS_CFG_UCLK_VLD BIT(2) | |
287 | #define SYS_CFG_PCLK_VLD BIT(3) | |
288 | #define SYS_CFG_PCIRSTB BIT(4) | |
289 | #define SYS_CFG_V15_VLD BIT(5) | |
290 | #define SYS_CFG_TRP_B15V_EN BIT(7) | |
f0769775 | 291 | #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ |
26f1fad2 JS |
292 | #define SYS_CFG_SIC_IDLE BIT(8) |
293 | #define SYS_CFG_BD_MAC2 BIT(9) | |
294 | #define SYS_CFG_BD_MAC1 BIT(10) | |
295 | #define SYS_CFG_IC_MACPHY_MODE BIT(11) | |
296 | #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) | |
297 | #define SYS_CFG_BT_FUNC BIT(16) | |
298 | #define SYS_CFG_VENDOR_ID BIT(19) | |
0e5d435a JS |
299 | #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) |
300 | #define SYS_CFG_VENDOR_ID_TSMC 0 | |
301 | #define SYS_CFG_VENDOR_ID_SMIC BIT(18) | |
302 | #define SYS_CFG_VENDOR_ID_UMC BIT(19) | |
26f1fad2 JS |
303 | #define SYS_CFG_PAD_HWPD_IDN BIT(22) |
304 | #define SYS_CFG_TRP_VAUX_EN BIT(23) | |
305 | #define SYS_CFG_TRP_BT_EN BIT(24) | |
c05a9dbf | 306 | #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ |
26f1fad2 JS |
307 | #define SYS_CFG_BD_PKG_SEL BIT(25) |
308 | #define SYS_CFG_BD_HCI_SEL BIT(26) | |
309 | #define SYS_CFG_TYPE_ID BIT(27) | |
310 | #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, | |
311 | 1:Test(RLE); 0:MP(RL) */ | |
312 | #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; | |
313 | 0:Switching regulator mode*/ | |
314 | #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ | |
315 | #define SYS_CFG_CHIP_VERSION_SHIFT 12 | |
316 | ||
317 | #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ | |
318 | #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) | |
319 | #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) | |
320 | #define GPIO_HCI_SEL (BIT(4) | BIT(5)) | |
321 | #define GPIO_PKG_SEL_HCI BIT(6) | |
322 | #define GPIO_FEN_GPS BIT(7) | |
323 | #define GPIO_FEN_BT BIT(8) | |
324 | #define GPIO_FEN_WL BIT(9) | |
325 | #define GPIO_FEN_PCI BIT(10) | |
326 | #define GPIO_FEN_USB BIT(11) | |
327 | #define GPIO_BTRF_HWPDN_N BIT(12) | |
328 | #define GPIO_WLRF_HWPDN_N BIT(13) | |
329 | #define GPIO_PDN_BT_N BIT(14) | |
330 | #define GPIO_PDN_GPS_N BIT(15) | |
331 | #define GPIO_BT_CTL_HWPDN BIT(16) | |
332 | #define GPIO_GPS_CTL_HWPDN BIT(17) | |
333 | #define GPIO_PPHY_SUSB BIT(20) | |
334 | #define GPIO_UPHY_SUSB BIT(21) | |
335 | #define GPIO_PCI_SUSEN BIT(22) | |
336 | #define GPIO_USB_SUSEN BIT(23) | |
337 | #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) | |
338 | ||
c05a9dbf JS |
339 | #define REG_SYS_CFG2 0x00fc /* 8192eu */ |
340 | ||
26f1fad2 JS |
341 | /* 0x0100 ~ 0x01FF MACTOP General Configuration */ |
342 | #define REG_CR 0x0100 | |
343 | #define CR_HCI_TXDMA_ENABLE BIT(0) | |
344 | #define CR_HCI_RXDMA_ENABLE BIT(1) | |
345 | #define CR_TXDMA_ENABLE BIT(2) | |
346 | #define CR_RXDMA_ENABLE BIT(3) | |
347 | #define CR_PROTOCOL_ENABLE BIT(4) | |
348 | #define CR_SCHEDULE_ENABLE BIT(5) | |
349 | #define CR_MAC_TX_ENABLE BIT(6) | |
350 | #define CR_MAC_RX_ENABLE BIT(7) | |
351 | #define CR_SW_BEACON_ENABLE BIT(8) | |
352 | #define CR_SECURITY_ENABLE BIT(9) | |
353 | #define CR_CALTIMER_ENABLE BIT(10) | |
354 | ||
355 | /* Media Status Register */ | |
356 | #define REG_MSR 0x0102 | |
357 | #define MSR_LINKTYPE_MASK 0x3 | |
358 | #define MSR_LINKTYPE_NONE 0x0 | |
359 | #define MSR_LINKTYPE_ADHOC 0x1 | |
360 | #define MSR_LINKTYPE_STATION 0x2 | |
361 | #define MSR_LINKTYPE_AP 0x3 | |
362 | ||
363 | #define REG_PBP 0x0104 | |
364 | #define PBP_PAGE_SIZE_RX_SHIFT 0 | |
365 | #define PBP_PAGE_SIZE_TX_SHIFT 4 | |
366 | #define PBP_PAGE_SIZE_64 0x0 | |
367 | #define PBP_PAGE_SIZE_128 0x1 | |
368 | #define PBP_PAGE_SIZE_256 0x2 | |
369 | #define PBP_PAGE_SIZE_512 0x3 | |
370 | #define PBP_PAGE_SIZE_1024 0x4 | |
371 | ||
372 | #define REG_TRXDMA_CTRL 0x010c | |
3e88ca44 | 373 | #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) |
26f1fad2 JS |
374 | #define TRXDMA_CTRL_VOQ_SHIFT 4 |
375 | #define TRXDMA_CTRL_VIQ_SHIFT 6 | |
376 | #define TRXDMA_CTRL_BEQ_SHIFT 8 | |
377 | #define TRXDMA_CTRL_BKQ_SHIFT 10 | |
378 | #define TRXDMA_CTRL_MGQ_SHIFT 12 | |
379 | #define TRXDMA_CTRL_HIQ_SHIFT 14 | |
380 | #define TRXDMA_QUEUE_LOW 1 | |
381 | #define TRXDMA_QUEUE_NORMAL 2 | |
382 | #define TRXDMA_QUEUE_HIGH 3 | |
383 | ||
384 | #define REG_TRXFF_BNDY 0x0114 | |
385 | #define REG_TRXFF_STATUS 0x0118 | |
386 | #define REG_RXFF_PTR 0x011c | |
387 | #define REG_HIMR 0x0120 | |
388 | #define REG_HISR 0x0124 | |
389 | #define REG_HIMRE 0x0128 | |
390 | #define REG_HISRE 0x012c | |
391 | #define REG_CPWM 0x012f | |
392 | #define REG_FWIMR 0x0130 | |
393 | #define REG_FWISR 0x0134 | |
394 | #define REG_PKTBUF_DBG_CTRL 0x0140 | |
395 | #define REG_PKTBUF_DBG_DATA_L 0x0144 | |
396 | #define REG_PKTBUF_DBG_DATA_H 0x0148 | |
397 | ||
398 | #define REG_TC0_CTRL 0x0150 | |
399 | #define REG_TC1_CTRL 0x0154 | |
400 | #define REG_TC2_CTRL 0x0158 | |
401 | #define REG_TC3_CTRL 0x015c | |
402 | #define REG_TC4_CTRL 0x0160 | |
403 | #define REG_TCUNIT_BASE 0x0164 | |
404 | #define REG_MBIST_START 0x0174 | |
405 | #define REG_MBIST_DONE 0x0178 | |
406 | #define REG_MBIST_FAIL 0x017c | |
407 | #define REG_C2HEVT_MSG_NORMAL 0x01a0 | |
14d88560 JS |
408 | /* 8192EU/8723BU/8812 */ |
409 | #define REG_C2HEVT_CMD_ID_8723B 0x01ae | |
26f1fad2 JS |
410 | #define REG_C2HEVT_CLEAR 0x01af |
411 | #define REG_C2HEVT_MSG_TEST 0x01b8 | |
412 | #define REG_MCUTST_1 0x01c0 | |
413 | #define REG_FMTHR 0x01c8 | |
414 | #define REG_HMTFR 0x01cc | |
415 | #define REG_HMBOX_0 0x01d0 | |
416 | #define REG_HMBOX_1 0x01d4 | |
417 | #define REG_HMBOX_2 0x01d8 | |
418 | #define REG_HMBOX_3 0x01dc | |
419 | ||
420 | #define REG_LLT_INIT 0x01e0 | |
421 | #define LLT_OP_INACTIVE 0x0 | |
422 | #define LLT_OP_WRITE (0x1 << 30) | |
423 | #define LLT_OP_READ (0x2 << 30) | |
424 | #define LLT_OP_MASK (0x3 << 30) | |
425 | ||
426 | #define REG_BB_ACCEESS_CTRL 0x01e8 | |
427 | #define REG_BB_ACCESS_DATA 0x01ec | |
428 | ||
29c2139c JS |
429 | #define REG_HMBOX_EXT0_8723B 0x01f0 |
430 | #define REG_HMBOX_EXT1_8723B 0x01f4 | |
431 | #define REG_HMBOX_EXT2_8723B 0x01f8 | |
432 | #define REG_HMBOX_EXT3_8723B 0x01fc | |
433 | ||
26f1fad2 JS |
434 | /* 0x0200 ~ 0x027F TXDMA Configuration */ |
435 | #define REG_RQPN 0x0200 | |
436 | #define RQPN_HI_PQ_SHIFT 0 | |
437 | #define RQPN_LO_PQ_SHIFT 8 | |
89c2a097 | 438 | #define RQPN_PUB_PQ_SHIFT 16 |
26f1fad2 JS |
439 | #define RQPN_LOAD BIT(31) |
440 | ||
441 | #define REG_FIFOPAGE 0x0204 | |
442 | #define REG_TDECTRL 0x0208 | |
443 | #define REG_TXDMA_OFFSET_CHK 0x020c | |
b63d0aac | 444 | #define TXDMA_OFFSET_DROP_DATA_EN BIT(9) |
26f1fad2 JS |
445 | #define REG_TXDMA_STATUS 0x0210 |
446 | #define REG_RQPN_NPQ 0x0214 | |
0635f8ce JS |
447 | #define RQPN_NPQ_SHIFT 0 |
448 | #define RQPN_EPQ_SHIFT 16 | |
26f1fad2 | 449 | |
74b99bed JS |
450 | #define REG_AUTO_LLT 0x0224 |
451 | #define AUTO_LLT_INIT_LLT BIT(16) | |
452 | ||
7e9567ff JS |
453 | #define REG_DWBCN1_CTRL_8723B 0x0228 |
454 | ||
26f1fad2 | 455 | /* 0x0280 ~ 0x02FF RXDMA Configuration */ |
08eca32e JS |
456 | #define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits |
457 | 8-14: USB DMA timeout | |
458 | 15 : Aggregation enable | |
459 | Only seems to be used | |
460 | on 8723bu/8192eu */ | |
c6594ffd | 461 | #define RXDMA_USB_AGG_ENABLE BIT(31) |
26f1fad2 | 462 | #define REG_RXPKT_NUM 0x0284 |
430b454c JS |
463 | #define RXPKT_NUM_RXDMA_IDLE BIT(17) |
464 | #define RXPKT_NUM_RW_RELEASE_EN BIT(18) | |
26f1fad2 JS |
465 | #define REG_RXDMA_STATUS 0x0288 |
466 | ||
c6594ffd JS |
467 | /* Presumably only found on newer chips such as 8723bu */ |
468 | #define REG_RX_DMA_CTRL_8723B 0x0286 | |
c3690604 | 469 | #define REG_RXDMA_PRO_8723B 0x0290 |
c6594ffd | 470 | |
26f1fad2 JS |
471 | #define REG_RF_BB_CMD_ADDR 0x02c0 |
472 | #define REG_RF_BB_CMD_DATA 0x02c4 | |
473 | ||
474 | /* spec version 11 */ | |
475 | /* 0x0400 ~ 0x047F Protocol Configuration */ | |
931d9278 JS |
476 | /* 8192c, 8192d */ |
477 | #define REG_VOQ_INFO 0x0400 | |
478 | #define REG_VIQ_INFO 0x0404 | |
479 | #define REG_BEQ_INFO 0x0408 | |
480 | #define REG_BKQ_INFO 0x040c | |
481 | /* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ | |
482 | #define REG_Q0_INFO 0x400 | |
483 | #define REG_Q1_INFO 0x404 | |
484 | #define REG_Q2_INFO 0x408 | |
485 | #define REG_Q3_INFO 0x40c | |
486 | ||
487 | #define REG_MGQ_INFO 0x0410 | |
488 | #define REG_HGQ_INFO 0x0414 | |
489 | #define REG_BCNQ_INFO 0x0418 | |
26f1fad2 JS |
490 | |
491 | #define REG_CPU_MGQ_INFORMATION 0x041c | |
492 | #define REG_FWHW_TXQ_CTRL 0x0420 | |
493 | #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) | |
494 | #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) | |
495 | ||
496 | #define REG_HWSEQ_CTRL 0x0423 | |
497 | #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 | |
498 | #define REG_TXPKTBUF_MGQ_BDNY 0x0425 | |
499 | #define REG_LIFETIME_EN 0x0426 | |
500 | #define REG_MULTI_BCNQ_OFFSET 0x0427 | |
501 | ||
502 | #define REG_SPEC_SIFS 0x0428 | |
503 | #define SPEC_SIFS_CCK_MASK 0x00ff | |
504 | #define SPEC_SIFS_CCK_SHIFT 0 | |
505 | #define SPEC_SIFS_OFDM_MASK 0xff00 | |
506 | #define SPEC_SIFS_OFDM_SHIFT 8 | |
507 | ||
508 | #define REG_RETRY_LIMIT 0x042a | |
509 | #define RETRY_LIMIT_LONG_SHIFT 0 | |
510 | #define RETRY_LIMIT_LONG_MASK 0x003f | |
511 | #define RETRY_LIMIT_SHORT_SHIFT 8 | |
512 | #define RETRY_LIMIT_SHORT_MASK 0x3f00 | |
513 | ||
514 | #define REG_DARFRC 0x0430 | |
515 | #define REG_RARFRC 0x0438 | |
516 | #define REG_RESPONSE_RATE_SET 0x0440 | |
517 | #define RESPONSE_RATE_BITMAP_ALL 0xfffff | |
518 | #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 | |
519 | #define RSR_1M BIT(0) | |
520 | #define RSR_2M BIT(1) | |
521 | #define RSR_5_5M BIT(2) | |
522 | #define RSR_11M BIT(3) | |
523 | #define RSR_6M BIT(4) | |
524 | #define RSR_9M BIT(5) | |
525 | #define RSR_12M BIT(6) | |
526 | #define RSR_18M BIT(7) | |
527 | #define RSR_24M BIT(8) | |
528 | #define RSR_36M BIT(9) | |
529 | #define RSR_48M BIT(10) | |
530 | #define RSR_54M BIT(11) | |
531 | #define RSR_MCS0 BIT(12) | |
532 | #define RSR_MCS1 BIT(13) | |
533 | #define RSR_MCS2 BIT(14) | |
534 | #define RSR_MCS3 BIT(15) | |
535 | #define RSR_MCS4 BIT(16) | |
536 | #define RSR_MCS5 BIT(17) | |
537 | #define RSR_MCS6 BIT(18) | |
538 | #define RSR_MCS7 BIT(19) | |
539 | #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ | |
540 | #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ | |
541 | #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ | |
542 | RSR_RSC_LOWER_SUB_CHANNEL) | |
543 | #define RSR_ACK_SHORT_PREAMBLE BIT(23) | |
544 | ||
545 | #define REG_ARFR0 0x0444 | |
546 | #define REG_ARFR1 0x0448 | |
547 | #define REG_ARFR2 0x044c | |
548 | #define REG_ARFR3 0x0450 | |
c3690604 | 549 | #define REG_AMPDU_MAX_TIME_8723B 0x0456 |
26f1fad2 JS |
550 | #define REG_AGGLEN_LMT 0x0458 |
551 | #define REG_AMPDU_MIN_SPACE 0x045c | |
552 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d | |
553 | #define REG_FAST_EDCA_CTRL 0x0460 | |
554 | #define REG_RD_RESP_PKT_TH 0x0463 | |
555 | #define REG_INIRTS_RATE_SEL 0x0480 | |
c3f9506f JS |
556 | /* 8723bu */ |
557 | #define REG_DATA_SUBCHANNEL 0x0483 | |
558 | /* 8723au */ | |
26f1fad2 | 559 | #define REG_INIDATA_RATE_SEL 0x0484 |
931d9278 JS |
560 | /* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ |
561 | #define REG_MACID_SLEEP_3_8732B 0x0484 | |
562 | #define REG_MACID_SLEEP_1_8732B 0x0488 | |
26f1fad2 JS |
563 | |
564 | #define REG_POWER_STATUS 0x04a4 | |
565 | #define REG_POWER_STAGE1 0x04b4 | |
566 | #define REG_POWER_STAGE2 0x04b8 | |
c6594ffd | 567 | #define REG_AMPDU_BURST_MODE_8723B 0x04bc |
26f1fad2 JS |
568 | #define REG_PKT_VO_VI_LIFE_TIME 0x04c0 |
569 | #define REG_PKT_BE_BK_LIFE_TIME 0x04c2 | |
570 | #define REG_STBC_SETTING 0x04c4 | |
b052b7fc | 571 | #define REG_QUEUE_CTRL 0x04c6 |
c3690604 | 572 | #define REG_HT_SINGLE_AMPDU_8723B 0x04c7 |
26f1fad2 JS |
573 | #define REG_PROT_MODE_CTRL 0x04c8 |
574 | #define REG_MAX_AGGR_NUM 0x04ca | |
575 | #define REG_RTS_MAX_AGGR_NUM 0x04cb | |
576 | #define REG_BAR_MODE_CTRL 0x04cc | |
577 | #define REG_RA_TRY_RATE_AGG_LMT 0x04cf | |
931d9278 JS |
578 | /* MACID_DROP for 8723a */ |
579 | #define REG_MACID_DROP_8732A 0x04d0 | |
580 | /* EARLY_MODE_CONTROL 8188e */ | |
581 | #define REG_EARLY_MODE_CONTROL_8188E 0x04d0 | |
582 | /* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ | |
583 | #define REG_MACID_SLEEP_2_8732B 0x04d0 | |
584 | #define REG_MACID_SLEEP 0x04d4 | |
26f1fad2 JS |
585 | #define REG_NQOS_SEQ 0x04dc |
586 | #define REG_QOS_SEQ 0x04de | |
587 | #define REG_NEED_CPU_HANDLE 0x04e0 | |
588 | #define REG_PKT_LOSE_RPT 0x04e1 | |
589 | #define REG_PTCL_ERR_STATUS 0x04e2 | |
cecfd3cb | 590 | #define REG_TX_REPORT_CTRL 0x04ec |
fe37d5f6 JS |
591 | #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) |
592 | ||
cecfd3cb | 593 | #define REG_TX_REPORT_TIME 0x04f0 |
26f1fad2 JS |
594 | #define REG_DUMMY 0x04fc |
595 | ||
596 | /* 0x0500 ~ 0x05FF EDCA Configuration */ | |
597 | #define REG_EDCA_VO_PARAM 0x0500 | |
598 | #define REG_EDCA_VI_PARAM 0x0504 | |
599 | #define REG_EDCA_BE_PARAM 0x0508 | |
600 | #define REG_EDCA_BK_PARAM 0x050c | |
601 | #define EDCA_PARAM_ECW_MIN_SHIFT 8 | |
602 | #define EDCA_PARAM_ECW_MAX_SHIFT 12 | |
603 | #define EDCA_PARAM_TXOP_SHIFT 16 | |
604 | #define REG_BEACON_TCFG 0x0510 | |
605 | #define REG_PIFS 0x0512 | |
606 | #define REG_RDG_PIFS 0x0513 | |
607 | #define REG_SIFS_CCK 0x0514 | |
608 | #define REG_SIFS_OFDM 0x0516 | |
609 | #define REG_TSFTR_SYN_OFFSET 0x0518 | |
610 | #define REG_AGGR_BREAK_TIME 0x051a | |
611 | #define REG_SLOT 0x051b | |
612 | #define REG_TX_PTCL_CTRL 0x0520 | |
613 | #define REG_TXPAUSE 0x0522 | |
614 | #define REG_DIS_TXREQ_CLR 0x0523 | |
615 | #define REG_RD_CTRL 0x0524 | |
616 | #define REG_TBTT_PROHIBIT 0x0540 | |
617 | #define REG_RD_NAV_NXT 0x0544 | |
618 | #define REG_NAV_PROT_LEN 0x0546 | |
619 | ||
620 | #define REG_BEACON_CTRL 0x0550 | |
621 | #define REG_BEACON_CTRL_1 0x0551 | |
622 | #define BEACON_ATIM BIT(0) | |
623 | #define BEACON_CTRL_MBSSID BIT(1) | |
624 | #define BEACON_CTRL_TX_BEACON_RPT BIT(2) | |
625 | #define BEACON_FUNCTION_ENABLE BIT(3) | |
626 | #define BEACON_DISABLE_TSF_UPDATE BIT(4) | |
627 | ||
628 | #define REG_MBID_NUM 0x0552 | |
629 | #define REG_DUAL_TSF_RST 0x0553 | |
630 | #define DUAL_TSF_RESET_TSF0 BIT(0) | |
631 | #define DUAL_TSF_RESET_TSF1 BIT(1) | |
632 | #define DUAL_TSF_RESET_P2P BIT(4) | |
633 | #define DUAL_TSF_TX_OK BIT(5) | |
634 | ||
635 | /* The same as REG_MBSSID_BCN_SPACE */ | |
636 | #define REG_BCN_INTERVAL 0x0554 | |
637 | #define REG_MBSSID_BCN_SPACE 0x0554 | |
638 | ||
639 | #define REG_DRIVER_EARLY_INT 0x0558 | |
640 | #define DRIVER_EARLY_INT_TIME 5 | |
641 | ||
642 | #define REG_BEACON_DMA_TIME 0x0559 | |
643 | #define BEACON_DMA_ATIME_INT_TIME 2 | |
644 | ||
645 | #define REG_ATIMWND 0x055a | |
c3690604 | 646 | #define REG_USTIME_TSF_8723B 0x055c |
26f1fad2 JS |
647 | #define REG_BCN_MAX_ERR 0x055d |
648 | #define REG_RXTSF_OFFSET_CCK 0x055e | |
649 | #define REG_RXTSF_OFFSET_OFDM 0x055f | |
650 | #define REG_TSFTR 0x0560 | |
651 | #define REG_TSFTR1 0x0568 | |
652 | #define REG_INIT_TSFTR 0x0564 | |
653 | #define REG_ATIMWND_1 0x0570 | |
654 | #define REG_PSTIMER 0x0580 | |
655 | #define REG_TIMER0 0x0584 | |
656 | #define REG_TIMER1 0x0588 | |
657 | #define REG_ACM_HW_CTRL 0x05c0 | |
658 | #define ACM_HW_CTRL_BK BIT(0) | |
659 | #define ACM_HW_CTRL_BE BIT(1) | |
660 | #define ACM_HW_CTRL_VI BIT(2) | |
661 | #define ACM_HW_CTRL_VO BIT(3) | |
662 | #define REG_ACM_RST_CTRL 0x05c1 | |
663 | #define REG_ACMAVG 0x05c2 | |
664 | #define REG_VO_ADMTIME 0x05c4 | |
665 | #define REG_VI_ADMTIME 0x05c6 | |
666 | #define REG_BE_ADMTIME 0x05c8 | |
667 | #define REG_EDCA_RANDOM_GEN 0x05cc | |
668 | #define REG_SCH_TXCMD 0x05d0 | |
669 | ||
670 | /* define REG_FW_TSF_SYNC_CNT 0x04a0 */ | |
f1785fbf | 671 | #define REG_SCH_TX_CMD 0x05f8 |
26f1fad2 JS |
672 | #define REG_FW_RESET_TSF_CNT_1 0x05fc |
673 | #define REG_FW_RESET_TSF_CNT_0 0x05fd | |
674 | #define REG_FW_BCN_DIS_CNT 0x05fe | |
675 | ||
676 | /* 0x0600 ~ 0x07FF WMAC Configuration */ | |
677 | #define REG_APSD_CTRL 0x0600 | |
678 | #define APSD_CTRL_OFF BIT(6) | |
679 | #define APSD_CTRL_OFF_STATUS BIT(7) | |
680 | #define REG_BW_OPMODE 0x0603 | |
681 | #define BW_OPMODE_20MHZ BIT(2) | |
682 | #define BW_OPMODE_5G BIT(1) | |
683 | #define BW_OPMODE_11J BIT(0) | |
684 | ||
685 | #define REG_TCR 0x0604 | |
686 | ||
687 | /* Receive Configuration Register */ | |
688 | #define REG_RCR 0x0608 | |
689 | #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ | |
690 | #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ | |
691 | #define RCR_ACCEPT_MCAST BIT(2) | |
692 | #define RCR_ACCEPT_BCAST BIT(3) | |
693 | #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match | |
694 | packet */ | |
695 | #define RCR_ACCEPT_PM BIT(5) /* Accept power management | |
696 | packet */ | |
697 | #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ | |
698 | #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet | |
699 | (Rx beacon, probe rsp) */ | |
700 | #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ | |
701 | #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ | |
b40027ba BR |
702 | #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use |
703 | REG_RXFLTMAP2 */ | |
704 | #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use | |
705 | REG_RXFLTMAP1 */ | |
706 | #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use | |
707 | REG_RXFLTMAP0 */ | |
26f1fad2 | 708 | #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ |
22229fcb JS |
709 | #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet |
710 | interrupt */ | |
711 | #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet | |
712 | interrupt */ | |
713 | #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ | |
26f1fad2 | 714 | #define RCR_MFBEN BIT(22) |
22229fcb JS |
715 | #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection |
716 | function. Search KEYCAM for | |
717 | each rx packet to check if | |
718 | LSIGEN bit is set. */ | |
26f1fad2 | 719 | #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ |
22229fcb | 720 | #define RCR_FORCE_ACK BIT(26) |
26f1fad2 JS |
721 | #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ |
722 | #define RCR_APPEND_PHYSTAT BIT(28) | |
723 | #define RCR_APPEND_ICV BIT(29) | |
724 | #define RCR_APPEND_MIC BIT(30) | |
725 | #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ | |
726 | ||
727 | #define REG_RX_PKT_LIMIT 0x060c | |
728 | #define REG_RX_DLK_TIME 0x060d | |
729 | #define REG_RX_DRVINFO_SZ 0x060f | |
730 | ||
731 | #define REG_MACID 0x0610 | |
732 | #define REG_BSSID 0x0618 | |
733 | #define REG_MAR 0x0620 | |
734 | #define REG_MBIDCAMCFG 0x0628 | |
735 | ||
736 | #define REG_USTIME_EDCA 0x0638 | |
737 | #define REG_MAC_SPEC_SIFS 0x063a | |
738 | ||
739 | /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ | |
740 | /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ | |
741 | #define REG_R2T_SIFS 0x063c | |
742 | /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ | |
743 | #define REG_T2T_SIFS 0x063e | |
744 | #define REG_ACKTO 0x0640 | |
745 | #define REG_CTS2TO 0x0641 | |
746 | #define REG_EIFS 0x0642 | |
747 | ||
748 | /* WMA, BA, CCX */ | |
749 | #define REG_NAV_CTRL 0x0650 | |
750 | /* In units of 128us */ | |
751 | #define REG_NAV_UPPER 0x0652 | |
752 | #define NAV_UPPER_UNIT 128 | |
753 | ||
754 | #define REG_BACAMCMD 0x0654 | |
755 | #define REG_BACAMCONTENT 0x0658 | |
756 | #define REG_LBDLY 0x0660 | |
757 | #define REG_FWDLY 0x0661 | |
758 | #define REG_RXERR_RPT 0x0664 | |
759 | #define REG_WMAC_TRXPTCL_CTL 0x0668 | |
c3f9506f JS |
760 | #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) |
761 | #define WMAC_TRXPTCL_CTL_BW_20 0 | |
762 | #define WMAC_TRXPTCL_CTL_BW_40 BIT(7) | |
763 | #define WMAC_TRXPTCL_CTL_BW_80 BIT(8) | |
26f1fad2 JS |
764 | |
765 | /* Security */ | |
766 | #define REG_CAM_CMD 0x0670 | |
767 | #define CAM_CMD_POLLING BIT(31) | |
768 | #define CAM_CMD_WRITE BIT(16) | |
769 | #define CAM_CMD_KEY_SHIFT 3 | |
770 | #define REG_CAM_WRITE 0x0674 | |
771 | #define CAM_WRITE_VALID BIT(15) | |
772 | #define REG_CAM_READ 0x0678 | |
773 | #define REG_CAM_DEBUG 0x067c | |
774 | #define REG_SECURITY_CFG 0x0680 | |
775 | #define SEC_CFG_TX_USE_DEFKEY BIT(0) | |
776 | #define SEC_CFG_RX_USE_DEFKEY BIT(1) | |
777 | #define SEC_CFG_TX_SEC_ENABLE BIT(2) | |
778 | #define SEC_CFG_RX_SEC_ENABLE BIT(3) | |
779 | #define SEC_CFG_SKBYA2 BIT(4) | |
780 | #define SEC_CFG_NO_SKMC BIT(5) | |
781 | #define SEC_CFG_TXBC_USE_DEFKEY BIT(6) | |
782 | #define SEC_CFG_RXBC_USE_DEFKEY BIT(7) | |
783 | ||
784 | /* Power */ | |
785 | #define REG_WOW_CTRL 0x0690 | |
786 | #define REG_PSSTATUS 0x0691 | |
787 | #define REG_PS_RX_INFO 0x0692 | |
788 | #define REG_LPNAV_CTRL 0x0694 | |
789 | #define REG_WKFMCAM_CMD 0x0698 | |
790 | #define REG_WKFMCAM_RWD 0x069c | |
b40027ba BR |
791 | |
792 | /* | |
793 | * RX Filters: each bit corresponds to the numerical value of the subtype. | |
794 | * If it is set the subtype frame type is passed. The filter is only used when | |
795 | * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit | |
796 | * in the RCR are low. | |
797 | * | |
798 | * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set | |
799 | * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. | |
800 | */ | |
801 | #define REG_RXFLTMAP0 0x06a0 /* Management frames */ | |
802 | #define REG_RXFLTMAP1 0x06a2 /* Control frames */ | |
803 | #define REG_RXFLTMAP2 0x06a4 /* Data frames */ | |
804 | ||
26f1fad2 JS |
805 | #define REG_BCN_PSR_RPT 0x06a8 |
806 | #define REG_CALB32K_CTRL 0x06ac | |
807 | #define REG_PKT_MON_CTRL 0x06b4 | |
3ca7b32c JS |
808 | #define REG_BT_COEX_TABLE1 0x06c0 |
809 | #define REG_BT_COEX_TABLE2 0x06c4 | |
810 | #define REG_BT_COEX_TABLE3 0x06c8 | |
811 | #define REG_BT_COEX_TABLE4 0x06cc | |
26f1fad2 JS |
812 | #define REG_WMAC_RESP_TXINFO 0x06d8 |
813 | ||
814 | #define REG_MACID1 0x0700 | |
815 | #define REG_BSSID1 0x0708 | |
816 | ||
e1547c53 JS |
817 | /* |
818 | * This seems to be 8723bu specific | |
819 | */ | |
820 | #define REG_BT_CONTROL_8723BU 0x0764 | |
821 | #define BT_CONTROL_BT_GRANT BIT(12) | |
822 | ||
f37e9228 JS |
823 | #define REG_WLAN_ACT_CONTROL_8723B 0x076e |
824 | ||
26f1fad2 JS |
825 | #define REG_FPGA0_RF_MODE 0x0800 |
826 | #define FPGA_RF_MODE BIT(0) | |
827 | #define FPGA_RF_MODE_JAPAN BIT(1) | |
828 | #define FPGA_RF_MODE_CCK BIT(24) | |
829 | #define FPGA_RF_MODE_OFDM BIT(25) | |
830 | ||
831 | #define REG_FPGA0_TX_INFO 0x0804 | |
dce7548f JS |
832 | #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) |
833 | #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) | |
834 | #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) | |
835 | #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) | |
26f1fad2 JS |
836 | #define REG_FPGA0_PSD_FUNC 0x0808 |
837 | #define REG_FPGA0_TX_GAIN 0x080c | |
838 | #define REG_FPGA0_RF_TIMING1 0x0810 | |
839 | #define REG_FPGA0_RF_TIMING2 0x0814 | |
840 | #define REG_FPGA0_POWER_SAVE 0x0818 | |
841 | #define FPGA0_PS_LOWER_CHANNEL BIT(26) | |
842 | #define FPGA0_PS_UPPER_CHANNEL BIT(27) | |
843 | ||
844 | #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ | |
845 | #define FPGA0_HSSI_PARM1_PI BIT(8) | |
846 | #define REG_FPGA0_XA_HSSI_PARM2 0x0824 | |
847 | #define REG_FPGA0_XB_HSSI_PARM1 0x0828 | |
848 | #define REG_FPGA0_XB_HSSI_PARM2 0x082c | |
849 | #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 | |
850 | #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 | |
851 | #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 | |
852 | #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ | |
853 | #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) | |
854 | #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) | |
855 | ||
856 | #define REG_TX_AGC_B_RATE18_06 0x0830 | |
857 | #define REG_TX_AGC_B_RATE54_24 0x0834 | |
858 | #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 | |
859 | #define REG_TX_AGC_B_MCS03_MCS00 0x083c | |
860 | ||
861 | #define REG_FPGA0_XA_LSSI_PARM 0x0840 | |
862 | #define REG_FPGA0_XB_LSSI_PARM 0x0844 | |
863 | #define FPGA0_LSSI_PARM_ADDR_SHIFT 20 | |
864 | #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 | |
865 | #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff | |
866 | ||
867 | #define REG_TX_AGC_B_MCS07_MCS04 0x0848 | |
868 | #define REG_TX_AGC_B_MCS11_MCS08 0x084c | |
869 | ||
870 | #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c | |
871 | ||
872 | #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ | |
873 | #define REG_FPGA0_XB_RF_INT_OE 0x0864 | |
874 | #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 | |
875 | #define FPGA0_INT_OE_ANTENNA_A BIT(8) | |
876 | #define FPGA0_INT_OE_ANTENNA_B BIT(9) | |
877 | #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ | |
878 | FPGA0_INT_OE_ANTENNA_B) | |
879 | ||
880 | #define REG_TX_AGC_B_MCS15_MCS12 0x0868 | |
881 | #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c | |
882 | ||
883 | #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 | |
884 | #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ | |
885 | #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ | |
886 | #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 | |
887 | #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ | |
888 | #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ | |
889 | #define FPGA0_RF_3WIRE_DATA BIT(0) | |
890 | #define FPGA0_RF_3WIRE_CLOC BIT(1) | |
891 | #define FPGA0_RF_3WIRE_LOAD BIT(2) | |
892 | #define FPGA0_RF_3WIRE_RW BIT(3) | |
893 | #define FPGA0_RF_3WIRE_MASK 0xf | |
894 | #define FPGA0_RF_RFENV BIT(4) | |
895 | #define FPGA0_RF_TRSW BIT(5) /* Useless now */ | |
896 | #define FPGA0_RF_TRSWB BIT(6) | |
897 | #define FPGA0_RF_ANTSW BIT(8) | |
898 | #define FPGA0_RF_ANTSWB BIT(9) | |
899 | #define FPGA0_RF_PAPE BIT(10) | |
900 | #define FPGA0_RF_PAPE5G BIT(11) | |
901 | #define FPGA0_RF_BD_CTRL_SHIFT 16 | |
902 | ||
903 | #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ | |
904 | #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ | |
905 | #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ | |
906 | #define REG_FPGA0_XCD_RF_PARM 0x087c | |
907 | #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ | |
908 | #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ | |
909 | #define FPGA0_RF_PARM_RFA_ENABLE BIT(1) | |
910 | #define FPGA0_RF_PARM_RFB_ENABLE BIT(17) | |
911 | #define FPGA0_RF_PARM_CLK_GATE BIT(31) | |
912 | ||
913 | #define REG_FPGA0_ANALOG1 0x0880 | |
914 | #define REG_FPGA0_ANALOG2 0x0884 | |
915 | #define FPGA0_ANALOG2_20MHZ BIT(10) | |
916 | #define REG_FPGA0_ANALOG3 0x0888 | |
917 | #define REG_FPGA0_ANALOG4 0x088c | |
918 | ||
9c79bf95 JS |
919 | #define REG_NHM_TH9_TH10_8723B 0x0890 |
920 | #define REG_NHM_TIMER_8723B 0x0894 | |
921 | #define REG_NHM_TH3_TO_TH0_8723B 0x0898 | |
922 | #define REG_NHM_TH7_TO_TH4_8723B 0x089c | |
923 | ||
26f1fad2 JS |
924 | #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ |
925 | #define REG_FPGA0_XB_LSSI_READBACK 0x08a4 | |
926 | #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ | |
927 | #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ | |
928 | ||
929 | #define REG_FPGA1_RF_MODE 0x0900 | |
930 | ||
931 | #define REG_FPGA1_TX_INFO 0x090c | |
af9e4d6d JS |
932 | #define REG_DPDT_CTRL 0x092c /* 8723BU */ |
933 | #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ | |
934 | #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ | |
935 | #define REG_RFE_BUFFER 0x0944 /* 8723BU */ | |
e1547c53 | 936 | #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ |
26f1fad2 JS |
937 | |
938 | #define REG_CCK0_SYSTEM 0x0a00 | |
939 | #define CCK0_SIDEBAND BIT(4) | |
940 | ||
941 | #define REG_CCK0_AFE_SETTING 0x0a04 | |
bd8fe40c JS |
942 | #define CCK0_AFE_RX_MASK 0x0f000000 |
943 | #define CCK0_AFE_RX_ANT_AB BIT(24) | |
944 | #define CCK0_AFE_RX_ANT_A 0 | |
945 | #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) | |
26f1fad2 JS |
946 | |
947 | #define REG_CONFIG_ANT_A 0x0b68 | |
948 | #define REG_CONFIG_ANT_B 0x0b6c | |
949 | ||
950 | #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 | |
951 | #define OFDM_RF_PATH_RX_MASK 0x0f | |
952 | #define OFDM_RF_PATH_RX_A BIT(0) | |
953 | #define OFDM_RF_PATH_RX_B BIT(1) | |
954 | #define OFDM_RF_PATH_RX_C BIT(2) | |
955 | #define OFDM_RF_PATH_RX_D BIT(3) | |
956 | #define OFDM_RF_PATH_TX_MASK 0xf0 | |
957 | #define OFDM_RF_PATH_TX_A BIT(4) | |
958 | #define OFDM_RF_PATH_TX_B BIT(5) | |
959 | #define OFDM_RF_PATH_TX_C BIT(6) | |
960 | #define OFDM_RF_PATH_TX_D BIT(7) | |
961 | ||
962 | #define REG_OFDM0_TR_MUX_PAR 0x0c08 | |
963 | ||
9c79bf95 JS |
964 | #define REG_OFDM0_FA_RSTC 0x0c0c |
965 | ||
26f1fad2 JS |
966 | #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 |
967 | #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c | |
968 | ||
969 | #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c | |
970 | ||
ce6f2e36 JS |
971 | #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 |
972 | #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) | |
973 | ||
26f1fad2 JS |
974 | #define REG_OFDM0_XA_AGC_CORE1 0x0c50 |
975 | #define REG_OFDM0_XA_AGC_CORE2 0x0c54 | |
976 | #define REG_OFDM0_XB_AGC_CORE1 0x0c58 | |
977 | #define REG_OFDM0_XB_AGC_CORE2 0x0c5c | |
978 | #define REG_OFDM0_XC_AGC_CORE1 0x0c60 | |
979 | #define REG_OFDM0_XC_AGC_CORE2 0x0c64 | |
980 | #define REG_OFDM0_XD_AGC_CORE1 0x0c68 | |
981 | #define REG_OFDM0_XD_AGC_CORE2 0x0c6c | |
982 | #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F | |
983 | ||
984 | #define REG_OFDM0_AGC_PARM1 0x0c70 | |
985 | ||
986 | #define REG_OFDM0_AGCR_SSI_TABLE 0x0c78 | |
987 | ||
988 | #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 | |
989 | #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 | |
990 | #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 | |
991 | #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 | |
992 | ||
993 | #define REG_OFDM0_XC_TX_AFE 0x0c94 | |
994 | #define REG_OFDM0_XD_TX_AFE 0x0c9c | |
995 | ||
996 | #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 | |
997 | ||
c3f9506f JS |
998 | /* 8723bu */ |
999 | #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 | |
1000 | ||
26f1fad2 JS |
1001 | #define REG_OFDM1_LSTF 0x0d00 |
1002 | #define OFDM_LSTF_PRIME_CH_LOW BIT(10) | |
1003 | #define OFDM_LSTF_PRIME_CH_HIGH BIT(11) | |
1004 | #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ | |
1005 | OFDM_LSTF_PRIME_CH_HIGH) | |
1006 | #define OFDM_LSTF_CONTINUE_TX BIT(28) | |
1007 | #define OFDM_LSTF_SINGLE_CARRIER BIT(29) | |
1008 | #define OFDM_LSTF_SINGLE_TONE BIT(30) | |
1009 | #define OFDM_LSTF_MASK 0x70000000 | |
1010 | ||
1011 | #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 | |
1012 | ||
1013 | #define REG_TX_AGC_A_RATE18_06 0x0e00 | |
1014 | #define REG_TX_AGC_A_RATE54_24 0x0e04 | |
1015 | #define REG_TX_AGC_A_CCK1_MCS32 0x0e08 | |
1016 | #define REG_TX_AGC_A_MCS03_MCS00 0x0e10 | |
1017 | #define REG_TX_AGC_A_MCS07_MCS04 0x0e14 | |
1018 | #define REG_TX_AGC_A_MCS11_MCS08 0x0e18 | |
1019 | #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c | |
1020 | ||
1021 | #define REG_FPGA0_IQK 0x0e28 | |
1022 | ||
1023 | #define REG_TX_IQK_TONE_A 0x0e30 | |
1024 | #define REG_RX_IQK_TONE_A 0x0e34 | |
1025 | #define REG_TX_IQK_PI_A 0x0e38 | |
1026 | #define REG_RX_IQK_PI_A 0x0e3c | |
1027 | ||
1028 | #define REG_TX_IQK 0x0e40 | |
1029 | #define REG_RX_IQK 0x0e44 | |
1030 | #define REG_IQK_AGC_PTS 0x0e48 | |
1031 | #define REG_IQK_AGC_RSP 0x0e4c | |
1032 | #define REG_TX_IQK_TONE_B 0x0e50 | |
1033 | #define REG_RX_IQK_TONE_B 0x0e54 | |
1034 | #define REG_TX_IQK_PI_B 0x0e58 | |
1035 | #define REG_RX_IQK_PI_B 0x0e5c | |
1036 | #define REG_IQK_AGC_CONT 0x0e60 | |
1037 | ||
1038 | #define REG_BLUETOOTH 0x0e6c | |
1039 | #define REG_RX_WAIT_CCA 0x0e70 | |
1040 | #define REG_TX_CCK_RFON 0x0e74 | |
1041 | #define REG_TX_CCK_BBON 0x0e78 | |
1042 | #define REG_TX_OFDM_RFON 0x0e7c | |
1043 | #define REG_TX_OFDM_BBON 0x0e80 | |
1044 | #define REG_TX_TO_RX 0x0e84 | |
1045 | #define REG_TX_TO_TX 0x0e88 | |
1046 | #define REG_RX_CCK 0x0e8c | |
1047 | ||
1048 | #define REG_TX_POWER_BEFORE_IQK_A 0x0e94 | |
1049 | #define REG_TX_POWER_AFTER_IQK_A 0x0e9c | |
1050 | ||
1051 | #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 | |
1052 | #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 | |
1053 | #define REG_RX_POWER_AFTER_IQK_A 0x0ea8 | |
1054 | #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac | |
1055 | ||
1056 | #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 | |
1057 | #define REG_TX_POWER_AFTER_IQK_B 0x0ebc | |
1058 | ||
1059 | #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 | |
1060 | #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 | |
1061 | #define REG_RX_POWER_AFTER_IQK_B 0x0ec8 | |
1062 | #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc | |
1063 | ||
1064 | #define REG_RX_OFDM 0x0ed0 | |
1065 | #define REG_RX_WAIT_RIFS 0x0ed4 | |
1066 | #define REG_RX_TO_RX 0x0ed8 | |
1067 | #define REG_STANDBY 0x0edc | |
1068 | #define REG_SLEEP 0x0ee0 | |
1069 | #define REG_PMPD_ANAEN 0x0eec | |
1070 | ||
1071 | #define REG_FW_START_ADDRESS 0x1000 | |
1072 | ||
1073 | #define REG_USB_INFO 0xfe17 | |
1074 | #define REG_USB_HIMR 0xfe38 | |
1075 | #define USB_HIMR_TIMEOUT2 BIT(31) | |
1076 | #define USB_HIMR_TIMEOUT1 BIT(30) | |
1077 | #define USB_HIMR_PSTIMEOUT BIT(29) | |
1078 | #define USB_HIMR_GTINT4 BIT(28) | |
1079 | #define USB_HIMR_GTINT3 BIT(27) | |
1080 | #define USB_HIMR_TXBCNERR BIT(26) | |
1081 | #define USB_HIMR_TXBCNOK BIT(25) | |
1082 | #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) | |
1083 | #define USB_HIMR_BCNDMAINT3 BIT(23) | |
1084 | #define USB_HIMR_BCNDMAINT2 BIT(22) | |
1085 | #define USB_HIMR_BCNDMAINT1 BIT(21) | |
1086 | #define USB_HIMR_BCNDMAINT0 BIT(20) | |
1087 | #define USB_HIMR_BCNDOK3 BIT(19) | |
1088 | #define USB_HIMR_BCNDOK2 BIT(18) | |
1089 | #define USB_HIMR_BCNDOK1 BIT(17) | |
1090 | #define USB_HIMR_BCNDOK0 BIT(16) | |
1091 | #define USB_HIMR_HSISR_IND BIT(15) | |
1092 | #define USB_HIMR_BCNDMAINT_E BIT(14) | |
1093 | /* RSVD BIT(13) */ | |
1094 | #define USB_HIMR_CTW_END BIT(12) | |
1095 | /* RSVD BIT(11) */ | |
1096 | #define USB_HIMR_C2HCMD BIT(10) | |
1097 | #define USB_HIMR_CPWM2 BIT(9) | |
1098 | #define USB_HIMR_CPWM BIT(8) | |
1099 | #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK | |
1100 | Interrupt */ | |
1101 | #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK | |
1102 | Interrupt */ | |
1103 | #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ | |
1104 | #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ | |
1105 | #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ | |
1106 | #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ | |
1107 | #define USB_HIMR_RDU BIT(1) /* Receive Descriptor | |
1108 | Unavailable */ | |
1109 | #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ | |
1110 | ||
1111 | #define REG_USB_SPECIAL_OPTION 0xfe55 | |
e4ac0a8a JS |
1112 | #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ |
1113 | #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to | |
1114 | deliver interrupt packet. | |
1115 | 0: Use int, 1: use bulk */ | |
3021e51f | 1116 | #define REG_USB_HRPWM 0xfe58 |
26f1fad2 | 1117 | #define REG_USB_DMA_AGG_TO 0xfe5b |
08eca32e JS |
1118 | #define REG_USB_AGG_TIMEOUT 0xfe5c |
1119 | #define REG_USB_AGG_THRESH 0xfe5d | |
26f1fad2 JS |
1120 | |
1121 | #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ | |
1122 | #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ | |
1123 | #define REG_NORMAL_SIE_OPTIONAL 0xfe64 | |
1124 | #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ | |
1125 | #define REG_NORMAL_SIE_EP_TX 0xfe66 | |
1126 | #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f | |
1127 | #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 | |
1128 | #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 | |
1129 | ||
1130 | #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ | |
1131 | #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c | |
1132 | #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ | |
1133 | #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ | |
1134 | #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ | |
1135 | ||
1136 | /* RF6052 registers */ | |
1137 | #define RF6052_REG_AC 0x00 | |
1138 | #define RF6052_REG_IQADJ_G1 0x01 | |
1139 | #define RF6052_REG_IQADJ_G2 0x02 | |
1140 | #define RF6052_REG_BS_PA_APSET_G1_G4 0x03 | |
1141 | #define RF6052_REG_BS_PA_APSET_G5_G8 0x04 | |
1142 | #define RF6052_REG_POW_TRSW 0x05 | |
1143 | #define RF6052_REG_GAIN_RX 0x06 | |
1144 | #define RF6052_REG_GAIN_TX 0x07 | |
1145 | #define RF6052_REG_TXM_IDAC 0x08 | |
1146 | #define RF6052_REG_IPA_G 0x09 | |
1147 | #define RF6052_REG_TXBIAS_G 0x0a | |
1148 | #define RF6052_REG_TXPA_AG 0x0b | |
1149 | #define RF6052_REG_IPA_A 0x0c | |
1150 | #define RF6052_REG_TXBIAS_A 0x0d | |
1151 | #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e | |
1152 | #define RF6052_REG_BS_IQGEN 0x0f | |
1153 | #define RF6052_REG_MODE1 0x10 | |
1154 | #define RF6052_REG_MODE2 0x11 | |
1155 | #define RF6052_REG_RX_AGC_HP 0x12 | |
1156 | #define RF6052_REG_TX_AGC 0x13 | |
1157 | #define RF6052_REG_BIAS 0x14 | |
1158 | #define RF6052_REG_IPA 0x15 | |
1159 | #define RF6052_REG_TXBIAS 0x16 | |
1160 | #define RF6052_REG_POW_ABILITY 0x17 | |
1161 | #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ | |
1162 | #define MODE_AG_CHANNEL_MASK 0x3ff | |
1163 | #define MODE_AG_CHANNEL_20MHZ BIT(10) | |
c3f9506f JS |
1164 | #define MODE_AG_BW_MASK (BIT(10) | BIT(11)) |
1165 | #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) | |
1166 | #define MODE_AG_BW_40MHZ_8723B BIT(10) | |
1167 | #define MODE_AG_BW_80MHZ_8723B 0 | |
26f1fad2 JS |
1168 | |
1169 | #define RF6052_REG_TOP 0x19 | |
1170 | #define RF6052_REG_RX_G1 0x1a | |
1171 | #define RF6052_REG_RX_G2 0x1b | |
1172 | #define RF6052_REG_RX_BB2 0x1c | |
1173 | #define RF6052_REG_RX_BB1 0x1d | |
1174 | #define RF6052_REG_RCK1 0x1e | |
1175 | #define RF6052_REG_RCK2 0x1f | |
1176 | #define RF6052_REG_TX_G1 0x20 | |
1177 | #define RF6052_REG_TX_G2 0x21 | |
1178 | #define RF6052_REG_TX_G3 0x22 | |
1179 | #define RF6052_REG_TX_BB1 0x23 | |
1180 | #define RF6052_REG_T_METER 0x24 | |
1181 | #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ | |
1182 | #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ | |
1183 | #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ | |
1184 | #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ | |
1185 | #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ | |
1186 | #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ | |
1187 | #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ | |
1188 | #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ | |
1189 | ||
1190 | #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ | |
1191 | ||
1192 | #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ | |
1193 | #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ | |
1194 | #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ | |
e1547c53 JS |
1195 | |
1196 | /* | |
1197 | * NextGen regs: 8723BU | |
1198 | */ | |
541bca7f JS |
1199 | #define RF6052_REG_T_METER_8723B 0x42 |
1200 | #define RF6052_REG_UNKNOWN_43 0x43 | |
1201 | #define RF6052_REG_UNKNOWN_55 0x55 | |
f991f4e9 | 1202 | #define RF6052_REG_UNKNOWN_56 0x56 |
541bca7f JS |
1203 | #define RF6052_REG_S0S1 0xb0 |
1204 | #define RF6052_REG_UNKNOWN_DF 0xdf | |
1205 | #define RF6052_REG_UNKNOWN_ED 0xed | |
1206 | #define RF6052_REG_WE_LUT 0xef |