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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / realtek / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
a8d76066 3 * Copyright(c) 2009-2012 Realtek Corporation.
0c817338
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
0c817338
LF		 14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
0c817338 26#include "wifi.h"
d273bb20 27#include "core.h"
0c817338
LF		 28#include "pci.h"
29#include "base.h"
30#include "ps.h"
c7cfe38e 31#include "efuse.h"
38506ece 32#include <linux/interrupt.h>
d273bb20 33#include <linux/export.h>
f11bbfd8 34#include <linux/kmemleak.h>
6f334c2b
LF		 35#include <linux/module.h>
36
37MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
38MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
39MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
40MODULE_LICENSE("GPL");
41MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
0c817338
LF		 42
43static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38506ece
LF		 44 INTEL_VENDOR_ID,
45 ATI_VENDOR_ID,
46 AMD_VENDOR_ID,
47 SIS_VENDOR_ID
0c817338
LF		 48};
49
c7cfe38e
C		 50static const u8 ac_to_hwq[] = {
51 VO_QUEUE,
52 VI_QUEUE,
53 BE_QUEUE,
54 BK_QUEUE
55};
56
d3bb1429 57static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 58 struct sk_buff *skb)
59{
60 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 61 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 62 u8 queue_index = skb_get_queue_mapping(skb);
63
64 if (unlikely(ieee80211_is_beacon(fc)))
65 return BEACON_QUEUE;
26634c4b 66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
c7cfe38e
C		 67 return MGNT_QUEUE;
68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
69 if (ieee80211_is_nullfunc(fc))
70 return HIGH_QUEUE;
71
72 return ac_to_hwq[queue_index];
73}
74
0c817338
LF		 75/* Update PCI dependent default settings*/
76static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
77{
78 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
80 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
81 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
82 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 83 u8 init_aspm;
0c817338
LF		 84
85 ppsc->reg_rfps_level = 0;
3db1cd5c 86 ppsc->support_aspm = false;
0c817338
LF		 87
88 /*Update PCI ASPM setting */
89 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
90 switch (rtlpci->const_pci_aspm) {
91 case 0:
92 /*No ASPM */
93 break;
94
95 case 1:
96 /*ASPM dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
98 break;
99
100 case 2:
101 /*ASPM with Clock Req dynamically enabled/disable. */
102 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
103 RT_RF_OFF_LEVL_CLK_REQ);
104 break;
105
106 case 3:
107 /*
108 * Always enable ASPM and Clock Req
109 * from initialization to halt.
110 * */
111 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
112 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
113 RT_RF_OFF_LEVL_CLK_REQ);
114 break;
115
116 case 4:
117 /*
118 * Always enable ASPM without Clock Req
119 * from initialization to halt.
120 * */
121 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
122 RT_RF_OFF_LEVL_CLK_REQ);
123 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
124 break;
125 }
126
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
128
129 /*Update Radio OFF setting */
130 switch (rtlpci->const_hwsw_rfoff_d3) {
131 case 1:
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 break;
135
136 case 2:
137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
140 break;
141
142 case 3:
143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
144 break;
145 }
146
147 /*Set HW definition to determine if it supports ASPM. */
148 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 149 case 0:{
150 /*Not support ASPM. */
151 bool support_aspm = false;
152 ppsc->support_aspm = support_aspm;
153 break;
154 }
155 case 1:{
156 /*Support ASPM. */
157 bool support_aspm = true;
158 bool support_backdoor = true;
159 ppsc->support_aspm = support_aspm;
160
161 /*if (priv->oem_id == RT_CID_TOSHIBA &&
162 !priv->ndis_adapter.amd_l1_patch)
163 support_backdoor = false; */
164
165 ppsc->support_backdoor = support_backdoor;
166
167 break;
168 }
0c817338
LF		 169 case 2:
170 /*ASPM value set by chipset. */
c7cfe38e
C		 171 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
172 bool support_aspm = true;
173 ppsc->support_aspm = support_aspm;
174 }
0c817338
LF		 175 break;
176 default:
b03d968b
LF		 177 pr_err("switch case %#x not processed\n",
178 rtlpci->const_support_pciaspm);
0c817338
LF		 179 break;
180 }
c7cfe38e
C		 181
182 /* toshiba aspm issue, toshiba will set aspm selfly
183 * so we should not set aspm in driver */
184 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
185 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
186 init_aspm == 0x43)
187 ppsc->support_aspm = false;
188}
189
0c817338
LF		 190static bool _rtl_pci_platform_switch_device_pci_aspm(
191 struct ieee80211_hw *hw,
192 u8 value)
193{
194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 195 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
196
197 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
198 value |= 0x40;
0c817338 199
0c817338
LF		 200 pci_write_config_byte(rtlpci->pdev, 0x80, value);
201
32473284 202 return false;
0c817338
LF		 203}
204
205/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
1d73c51a 206static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0c817338
LF		 207{
208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 210
0c817338 211 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 212
c7cfe38e
C		 213 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
214 udelay(100);
0c817338
LF		 215}
216
217/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
218static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
219{
220 struct rtl_priv *rtlpriv = rtl_priv(hw);
221 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
222 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
224 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 225 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
226 /*Retrieve original configuration settings. */
227 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
228 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
229 pcibridge_linkctrlreg;
230 u16 aspmlevel = 0;
32473284 231 u8 tmp_u1b = 0;
0c817338 232
c7cfe38e
C		 233 if (!ppsc->support_aspm)
234 return;
235
0c817338
LF		 236 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
237 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 238 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 239
240 return;
241 }
242
243 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
244 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
245 _rtl_pci_switch_clk_req(hw, 0x0);
246 }
247
32473284
LF		 248 /*for promising device will in L0 state after an I/O. */
249 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 250
251 /*Set corresponding value. */
252 aspmlevel |= BIT(0) | BIT(1);
253 linkctrl_reg &= ~aspmlevel;
254 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
255
256 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
257 udelay(50);
258
259 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 260 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
261 pcibridge_linkctrlreg);
0c817338
LF		 262
263 udelay(50);
0c817338
LF		 264}
265
266/*
267 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
268 *power saving We should follow the sequence to enable
269 *RTL8192SE first then enable Pci Bridge ASPM
270 *or the system will show bluescreen.
271 */
272static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
273{
274 struct rtl_priv *rtlpriv = rtl_priv(hw);
275 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
276 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
280 u16 aspmlevel;
281 u8 u_pcibridge_aspmsetting;
282 u8 u_device_aspmsetting;
283
c7cfe38e
C		 284 if (!ppsc->support_aspm)
285 return;
286
0c817338
LF		 287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 289 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 290 return;
291 }
292
293 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 294
295 u_pcibridge_aspmsetting =
296 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
297 rtlpci->const_hostpci_aspm_setting;
298
299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
300 u_pcibridge_aspmsetting &= ~BIT(0);
301
886e14b6
LF		 302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
303 u_pcibridge_aspmsetting);
0c817338
LF		 304
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
26634c4b 306 "PlatformEnableASPM(): Write reg[%x] = %x\n",
f30d7507
JP		 307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
308 u_pcibridge_aspmsetting);
0c817338
LF		 309
310 udelay(50);
311
312 /*Get ASPM level (with/without Clock Req) */
313 aspmlevel = rtlpci->const_devicepci_aspm_setting;
314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
315
316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
318
319 u_device_aspmsetting |= aspmlevel;
320
321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
322
323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
327 }
c7cfe38e 328 udelay(100);
0c817338
LF		 329}
330
331static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
332{
886e14b6 333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 334
335 bool status = false;
336 u8 offset_e0;
337 unsigned offset_e4;
338
886e14b6 339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 340
886e14b6 341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 342
343 if (offset_e0 == 0xA0) {
886e14b6 344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 345 if (offset_e4 & BIT(23))
346 status = true;
347 }
348
349 return status;
350}
351
26634c4b
LF		 352static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
353 struct rtl_priv **buddy_priv)
354{
355 struct rtl_priv *rtlpriv = rtl_priv(hw);
356 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
357 bool find_buddy_priv = false;
37c52934 358 struct rtl_priv *tpriv;
26634c4b
LF		 359 struct rtl_pci_priv *tpcipriv = NULL;
360
361 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
362 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
363 list) {
37c52934
LF		 364 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
365 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
366 "pcipriv->ndis_adapter.funcnumber %x\n",
367 pcipriv->ndis_adapter.funcnumber);
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
369 "tpcipriv->ndis_adapter.funcnumber %x\n",
370 tpcipriv->ndis_adapter.funcnumber);
371
372 if ((pcipriv->ndis_adapter.busnumber ==
373 tpcipriv->ndis_adapter.busnumber) &&
374 (pcipriv->ndis_adapter.devnumber ==
375 tpcipriv->ndis_adapter.devnumber) &&
376 (pcipriv->ndis_adapter.funcnumber !=
377 tpcipriv->ndis_adapter.funcnumber)) {
378 find_buddy_priv = true;
379 break;
26634c4b
LF		 380 }
381 }
382 }
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
385 "find_buddy_priv %d\n", find_buddy_priv);
386
387 if (find_buddy_priv)
388 *buddy_priv = tpriv;
389
390 return find_buddy_priv;
391}
392
d3bb1429 393static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 394{
395 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 396 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 397 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 398 u8 linkctrl_reg;
c7cfe38e 399 u8 num4bbytes;
0c817338 400
c7cfe38e 401 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 402
403 /*Read Link Control Register */
886e14b6 404 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 405
406 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
407}
408
409static void rtl_pci_parse_configuration(struct pci_dev *pdev,
410 struct ieee80211_hw *hw)
411{
412 struct rtl_priv *rtlpriv = rtl_priv(hw);
413 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
414
415 u8 tmp;
332badc3 416 u16 linkctrl_reg;
0c817338
LF		 417
418 /*Link Control Register */
332badc3
JL		 419 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
420 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
0c817338 421
f30d7507
JP		 422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
423 pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 424
425 pci_read_config_byte(pdev, 0x98, &tmp);
426 tmp |= BIT(4);
427 pci_write_config_byte(pdev, 0x98, tmp);
428
429 tmp = 0x17;
430 pci_write_config_byte(pdev, 0x70f, tmp);
431}
432
c7cfe38e 433static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 434{
435 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
436
437 _rtl_pci_update_default_setting(hw);
438
439 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
440 /*Always enable ASPM & Clock Req. */
441 rtl_pci_enable_aspm(hw);
442 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
443 }
444
445}
446
0c817338
LF		 447static void _rtl_pci_io_handler_init(struct device *dev,
448 struct ieee80211_hw *hw)
449{
450 struct rtl_priv *rtlpriv = rtl_priv(hw);
451
452 rtlpriv->io.dev = dev;
453
454 rtlpriv->io.write8_async = pci_write8_async;
455 rtlpriv->io.write16_async = pci_write16_async;
456 rtlpriv->io.write32_async = pci_write32_async;
457
458 rtlpriv->io.read8_sync = pci_read8_sync;
459 rtlpriv->io.read16_sync = pci_read16_sync;
460 rtlpriv->io.read32_sync = pci_read32_sync;
461
462}
463
c7cfe38e
C		 464static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
465 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
466{
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
26634c4b 469 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
c7cfe38e 470 struct sk_buff *next_skb;
26634c4b 471 u8 additionlen = FCS_LEN;
c7cfe38e
C		 472
473 /* here open is 4, wep/tkip is 8, aes is 12*/
474 if (info->control.hw_key)
475 additionlen += info->control.hw_key->icv_len;
476
477 /* The most skb num is 6 */
478 tcb_desc->empkt_num = 0;
479 spin_lock_bh(&rtlpriv->locks.waitq_lock);
480 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
481 struct ieee80211_tx_info *next_info;
482
483 next_info = IEEE80211_SKB_CB(next_skb);
484 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
485 tcb_desc->empkt_len[tcb_desc->empkt_num] =
486 next_skb->len + additionlen;
487 tcb_desc->empkt_num++;
488 } else {
489 break;
490 }
491
492 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
493 next_skb))
494 break;
495
26634c4b 496 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
c7cfe38e
C		 497 break;
498 }
499 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
500
501 return true;
502}
503
504/* just for early mode now */
505static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
506{
507 struct rtl_priv *rtlpriv = rtl_priv(hw);
508 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
509 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
510 struct sk_buff *skb = NULL;
511 struct ieee80211_tx_info *info = NULL;
26634c4b 512 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
fb914ebf 513 int tid;
c7cfe38e
C		 514
515 if (!rtlpriv->rtlhal.earlymode_enable)
516 return;
517
26634c4b
LF		 518 if (rtlpriv->dm.supp_phymode_switch &&
519 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
520 (rtlpriv->buddy_priv &&
521 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
522 return;
c7cfe38e
C		 523 /* we juse use em for BE/BK/VI/VO */
524 for (tid = 7; tid >= 0; tid--) {
2a00def4 525 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
c7cfe38e
C		 526 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
527 while (!mac->act_scanning &&
528 rtlpriv->psc.rfpwr_state == ERFON) {
529 struct rtl_tcb_desc tcb_desc;
530 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
531
532 spin_lock_bh(&rtlpriv->locks.waitq_lock);
533 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
26634c4b
LF		 534 (ring->entries - skb_queue_len(&ring->queue) >
535 rtlhal->max_earlymode_num)) {
c7cfe38e
C		 536 skb = skb_dequeue(&mac->skb_waitq[tid]);
537 } else {
538 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
539 break;
540 }
541 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
542
543 /* Some macaddr can't do early mode. like
544 * multicast/broadcast/no_qos data */
545 info = IEEE80211_SKB_CB(skb);
546 if (info->flags & IEEE80211_TX_CTL_AMPDU)
547 _rtl_update_earlymode_info(hw, skb,
548 &tcb_desc, tid);
549
36323f81 550 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
c7cfe38e
C		 551 }
552 }
553}
554
555
0c817338
LF		 556static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
557{
558 struct rtl_priv *rtlpriv = rtl_priv(hw);
559 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
560
561 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
562
563 while (skb_queue_len(&ring->queue)) {
0c817338
LF		 564 struct sk_buff *skb;
565 struct ieee80211_tx_info *info;
c7cfe38e
C		 566 __le16 fc;
567 u8 tid;
38506ece 568 u8 *entry;
0c817338 569
38506ece
LF		 570 if (rtlpriv->use_new_trx_flow)
571 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
572 else
573 entry = (u8 *)(&ring->desc[ring->idx]);
0c817338 574
d0311314
TT		 575 if (rtlpriv->cfg->ops->get_available_desc &&
576 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) {
577 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG,
578 "no available desc!\n");
579 return;
580 }
581
38506ece 582 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
0c817338
LF		 583 return;
584 ring->idx = (ring->idx + 1) % ring->entries;
585
586 skb = __skb_dequeue(&ring->queue);
587 pci_unmap_single(rtlpci->pdev,
d3bb1429 588 rtlpriv->cfg->ops->
38506ece 589 get_desc((u8 *)entry, true,
d3bb1429 590 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 591 skb->len, PCI_DMA_TODEVICE);
592
c7cfe38e
C		 593 /* remove early mode header */
594 if (rtlpriv->rtlhal.earlymode_enable)
595 skb_pull(skb, EM_HDR_LEN);
596
0c817338 597 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
f30d7507
JP		 598 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
599 ring->idx,
600 skb_queue_len(&ring->queue),
38506ece 601 *(u16 *)(skb->data + 22));
0c817338 602
c7cfe38e
C		 603 if (prio == TXCMD_QUEUE) {
604 dev_kfree_skb(skb);
605 goto tx_status_ok;
606
607 }
608
609 /* for sw LPS, just after NULL skb send out, we can
26634c4b
LF		 610 * sure AP knows we are sleeping, we should not let
611 * rf sleep
612 */
c7cfe38e
C		 613 fc = rtl_get_fc(skb);
614 if (ieee80211_is_nullfunc(fc)) {
615 if (ieee80211_has_pm(fc)) {
9c050440 616 rtlpriv->mac80211.offchan_delay = true;
3db1cd5c 617 rtlpriv->psc.state_inap = true;
c7cfe38e 618 } else {
3db1cd5c 619 rtlpriv->psc.state_inap = false;
c7cfe38e
C		 620 }
621 }
26634c4b
LF		 622 if (ieee80211_is_action(fc)) {
623 struct ieee80211_mgmt *action_frame =
624 (struct ieee80211_mgmt *)skb->data;
625 if (action_frame->u.action.u.ht_smps.action ==
626 WLAN_HT_ACTION_SMPS) {
627 dev_kfree_skb(skb);
628 goto tx_status_ok;
629 }
630 }
c7cfe38e
C		 631
632 /* update tid tx pkt num */
633 tid = rtl_get_tid(skb);
634 if (tid <= 7)
635 rtlpriv->link_info.tidtx_inperiod[tid]++;
636
0c817338
LF		 637 info = IEEE80211_SKB_CB(skb);
638 ieee80211_tx_info_clear_status(info);
639
640 info->flags |= IEEE80211_TX_STAT_ACK;
641 /*info->status.rates[0].count = 1; */
642
643 ieee80211_tx_status_irqsafe(hw, skb);
644
d0311314 645 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
0c817338 646
d0311314 647 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
4f4378de 648 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
f30d7507
JP		 649 prio, ring->idx,
650 skb_queue_len(&ring->queue));
0c817338
LF		 651
652 ieee80211_wake_queue(hw,
653 skb_get_queue_mapping
654 (skb));
655 }
c7cfe38e 656tx_status_ok:
0c817338
LF		 657 skb = NULL;
658 }
659
660 if (((rtlpriv->link_info.num_rx_inperiod +
ba9f93f8
LF		 661 rtlpriv->link_info.num_tx_inperiod) > 8) ||
662 (rtlpriv->link_info.num_rx_inperiod > 2))
663 rtl_lps_leave(hw);
0c817338
LF		 664}
665
38506ece 666static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
e9538cf4
LF		 667 struct sk_buff *new_skb, u8 *entry,
668 int rxring_idx, int desc_idx)
fd854772
MM		 669{
670 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece
LF		 671 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
672 u32 bufferaddress;
673 u8 tmp_one = 1;
674 struct sk_buff *skb;
675
e9538cf4
LF		 676 if (likely(new_skb)) {
677 skb = new_skb;
678 goto remap;
679 }
38506ece
LF		 680 skb = dev_alloc_skb(rtlpci->rxbuffersize);
681 if (!skb)
682 return 0;
38506ece 683
e9538cf4 684remap:
38506ece
LF		 685 /* just set skb->cb to mapping addr for pci_unmap_single use */
686 *((dma_addr_t *)skb->cb) =
687 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
688 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
689 bufferaddress = *((dma_addr_t *)skb->cb);
690 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
691 return 0;
e9538cf4 692 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
38506ece
LF		 693 if (rtlpriv->use_new_trx_flow) {
694 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
695 HW_DESC_RX_PREPARE,
696 (u8 *)&bufferaddress);
fd854772 697 } else {
38506ece
LF		 698 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
699 HW_DESC_RXBUFF_ADDR,
700 (u8 *)&bufferaddress);
701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
702 HW_DESC_RXPKT_LEN,
703 (u8 *)&rtlpci->rxbuffersize);
704 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
705 HW_DESC_RXOWN,
706 (u8 *)&tmp_one);
fd854772 707 }
38506ece
LF		 708 return 1;
709}
fd854772 710
38506ece
LF		 711/* inorder to receive 8K AMSDU we have set skb to
712 * 9100bytes in init rx ring, but if this packet is
713 * not a AMSDU, this large packet will be sent to
714 * TCP/IP directly, this cause big packet ping fail
715 * like: "ping -s 65507", so here we will realloc skb
716 * based on the true size of packet, Mac80211
717 * Probably will do it better, but does not yet.
718 *
719 * Some platform will fail when alloc skb sometimes.
720 * in this condition, we will send the old skb to
721 * mac80211 directly, this will not cause any other
722 * issues, but only this packet will be lost by TCP/IP
723 */
724static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
725 struct sk_buff *skb,
726 struct ieee80211_rx_status rx_status)
727{
728 if (unlikely(!rtl_action_proc(hw, skb, false))) {
729 dev_kfree_skb_any(skb);
730 } else {
731 struct sk_buff *uskb = NULL;
38506ece
LF		 732
733 uskb = dev_alloc_skb(skb->len + 128);
734 if (likely(uskb)) {
735 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
736 sizeof(rx_status));
b952f4df 737 skb_put_data(uskb, skb->data, skb->len);
38506ece
LF		 738 dev_kfree_skb_any(skb);
739 ieee80211_rx_irqsafe(hw, uskb);
740 } else {
741 ieee80211_rx_irqsafe(hw, skb);
742 }
fd854772 743 }
38506ece 744}
fd854772 745
38506ece
LF		 746/*hsisr interrupt handler*/
747static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
748{
749 struct rtl_priv *rtlpriv = rtl_priv(hw);
750 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
fd854772 751
38506ece
LF		 752 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
753 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
754 rtlpci->sys_irq_mask);
fd854772
MM		 755}
756
0c817338
LF		 757static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
758{
759 struct rtl_priv *rtlpriv = rtl_priv(hw);
760 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece 761 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
0c817338
LF		 762 struct ieee80211_rx_status rx_status = { 0 };
763 unsigned int count = rtlpci->rxringcount;
764 u8 own;
765 u8 tmp_one;
38506ece
LF		 766 bool unicast = false;
767 u8 hw_queue = 0;
768 unsigned int rx_remained_cnt;
0c817338
LF		 769 struct rtl_stats stats = {
770 .signal = 0,
0c817338
LF		 771 .rate = 0,
772 };
773
774 /*RX NORMAL PKT */
775 while (count--) {
38506ece
LF		 776 struct ieee80211_hdr *hdr;
777 __le16 fc;
778 u16 len;
779 /*rx buffer descriptor */
780 struct rtl_rx_buffer_desc *buffer_desc = NULL;
781 /*if use new trx flow, it means wifi info */
782 struct rtl_rx_desc *pdesc = NULL;
0c817338 783 /*rx pkt */
38506ece
LF		 784 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
785 rtlpci->rx_ring[rxring_idx].idx];
e9538cf4 786 struct sk_buff *new_skb;
38506ece
LF		 787
788 if (rtlpriv->use_new_trx_flow) {
789 rx_remained_cnt =
790 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
791 hw_queue);
d0311314 792 if (rx_remained_cnt == 0)
38506ece 793 return;
f99551a2
LF		 794 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
795 rtlpci->rx_ring[rxring_idx].idx];
796 pdesc = (struct rtl_rx_desc *)skb->data;
38506ece
LF		 797 } else { /* rx descriptor */
798 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
799 rtlpci->rx_ring[rxring_idx].idx];
800
801 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
802 false,
803 HW_DESC_OWN);
804 if (own) /* wait data to be filled by hardware */
805 return;
806 }
6633d649 807
38506ece
LF		 808 /* Reaching this point means: data is filled already
809 * AAAAAAttention !!!
810 * We can NOT access 'skb' before 'pci_unmap_single'
811 */
812 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
813 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
814
e9538cf4
LF		 815 /* get a new skb - if fail, old one will be reused */
816 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
aeb2d2a4 817 if (unlikely(!new_skb))
e9538cf4 818 goto no_new;
38506ece 819 memset(&rx_status , 0 , sizeof(rx_status));
2c333366 820 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
38506ece 821 &rx_status, (u8 *)pdesc, skb);
2c333366 822
38506ece
LF		 823 if (rtlpriv->use_new_trx_flow)
824 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
825 (u8 *)buffer_desc,
826 hw_queue);
8db8ddf1 827
38506ece
LF		 828 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
829 HW_DESC_RXPKT_LEN);
2c333366 830
38506ece
LF		 831 if (skb->end - skb->tail > len) {
832 skb_put(skb, len);
833 if (rtlpriv->use_new_trx_flow)
834 skb_reserve(skb, stats.rx_drvinfo_size +
835 stats.rx_bufshift + 24);
836 else
837 skb_reserve(skb, stats.rx_drvinfo_size +
838 stats.rx_bufshift);
38506ece
LF		 839 } else {
840 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
841 "skb->end - skb->tail = %d, len is %d\n",
842 skb->end - skb->tail, len);
d0311314
TT		 843 dev_kfree_skb_any(skb);
844 goto new_trx_end;
38506ece
LF		 845 }
846 /* handle command packet here */
d1cd5ba4 847 if (rtlpriv->cfg->ops->rx_command_packet &&
ce254243 848 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
38506ece 849 dev_kfree_skb_any(skb);
d0311314 850 goto new_trx_end;
38506ece 851 }
2c333366
MM		 852
853 /*
854 * NOTICE This can not be use for mac80211,
855 * this is done in mac80211 code,
38506ece 856 * if done here sec DHCP will fail
2c333366
MM		 857 * skb_trim(skb, skb->len - 4);
858 */
859
38506ece
LF		 860 hdr = rtl_get_hdr(skb);
861 fc = rtl_get_fc(skb);
862
863 if (!stats.crc && !stats.hwerror) {
864 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
865 sizeof(rx_status));
866
867 if (is_broadcast_ether_addr(hdr->addr1)) {
868 ;/*TODO*/
869 } else if (is_multicast_ether_addr(hdr->addr1)) {
870 ;/*TODO*/
871 } else {
872 unicast = true;
873 rtlpriv->stats.rxbytesunicast += skb->len;
874 }
cad737df 875 rtl_is_special_data(hw, skb, false, true);
0c817338 876
38506ece
LF		 877 if (ieee80211_is_data(fc)) {
878 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
879 if (unicast)
880 rtlpriv->link_info.num_rx_inperiod++;
881 }
882 /* static bcn for roaming */
883 rtl_beacon_statistic(hw, skb);
884 rtl_p2p_info(hw, (void *)skb->data, skb->len);
885 /* for sw lps */
886 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
887 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
888 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
889 (rtlpriv->rtlhal.current_bandtype ==
890 BAND_ON_2_4G) &&
891 (ieee80211_is_beacon(fc) ||
892 ieee80211_is_probe_resp(fc))) {
893 dev_kfree_skb_any(skb);
894 } else {
895 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
896 }
897 } else {
898 dev_kfree_skb_any(skb);
899 }
d0311314 900new_trx_end:
38506ece
LF		 901 if (rtlpriv->use_new_trx_flow) {
902 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
903 rtlpci->rx_ring[hw_queue].next_rx_rp %=
904 RTL_PCI_MAX_RX_COUNT;
905
906 rx_remained_cnt--;
907 rtl_write_word(rtlpriv, 0x3B4,
908 rtlpci->rx_ring[hw_queue].next_rx_rp);
909 }
2c333366 910 if (((rtlpriv->link_info.num_rx_inperiod +
a269913c 911 rtlpriv->link_info.num_tx_inperiod) > 8) ||
ba9f93f8
LF		 912 (rtlpriv->link_info.num_rx_inperiod > 2))
913 rtl_lps_leave(hw);
e9538cf4
LF		 914 skb = new_skb;
915no_new:
38506ece 916 if (rtlpriv->use_new_trx_flow) {
e9538cf4 917 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
38506ece 918 rxring_idx,
e9538cf4 919 rtlpci->rx_ring[rxring_idx].idx);
38506ece 920 } else {
e9538cf4
LF		 921 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
922 rxring_idx,
38506ece 923 rtlpci->rx_ring[rxring_idx].idx);
38506ece
LF		 924 if (rtlpci->rx_ring[rxring_idx].idx ==
925 rtlpci->rxringcount - 1)
926 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
927 false,
928 HW_DESC_RXERO,
929 (u8 *)&tmp_one);
930 }
931 rtlpci->rx_ring[rxring_idx].idx =
932 (rtlpci->rx_ring[rxring_idx].idx + 1) %
933 rtlpci->rxringcount;
0c817338 934 }
0c817338
LF		 935}
936
0c817338
LF		 937static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
938{
939 struct ieee80211_hw *hw = dev_id;
38506ece 940 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 941 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 942 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 943 unsigned long flags;
944 u32 inta = 0;
945 u32 intb = 0;
de2e56ce 946 irqreturn_t ret = IRQ_HANDLED;
0c817338 947
38506ece
LF		 948 if (rtlpci->irq_enabled == 0)
949 return ret;
950
951 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags);
952 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 953
954 /*read ISR: 4/8bytes */
955 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
956
957 /*Shared IRQ or HW disappared */
0529c6b8 958 if (!inta || inta == 0xffff)
0c817338
LF		 959 goto done;
960
961 /*<1> beacon related */
962 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
963 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 964 "beacon ok interrupt!\n");
0c817338
LF		 965 }
966
967 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
968 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 969 "beacon err interrupt!\n");
0c817338
LF		 970 }
971
972 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
f30d7507 973 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0c817338
LF		 974 }
975
e6deaf81 976 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
0c817338 977 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 978 "prepare beacon for interrupt!\n");
0c817338
LF		 979 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
980 }
981
38506ece
LF		 982 /*<2> Tx related */
983 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
f30d7507 984 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0c817338
LF		 985
986 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
987 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 988 "Manage ok interrupt!\n");
0c817338
LF		 989 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
990 }
991
992 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
993 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 994 "HIGH_QUEUE ok interrupt!\n");
0c817338
LF		 995 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
996 }
997
998 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
999 rtlpriv->link_info.num_tx_inperiod++;
1000
1001 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1002 "BK Tx OK interrupt!\n");
0c817338
LF		 1003 _rtl_pci_tx_isr(hw, BK_QUEUE);
1004 }
1005
1006 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1007 rtlpriv->link_info.num_tx_inperiod++;
1008
1009 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1010 "BE TX OK interrupt!\n");
0c817338
LF		 1011 _rtl_pci_tx_isr(hw, BE_QUEUE);
1012 }
1013
1014 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1015 rtlpriv->link_info.num_tx_inperiod++;
1016
1017 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1018 "VI TX OK interrupt!\n");
0c817338
LF		 1019 _rtl_pci_tx_isr(hw, VI_QUEUE);
1020 }
1021
1022 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1023 rtlpriv->link_info.num_tx_inperiod++;
1024
1025 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1026 "Vo TX OK interrupt!\n");
0c817338
LF		 1027 _rtl_pci_tx_isr(hw, VO_QUEUE);
1028 }
1029
c7cfe38e
C		 1030 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1031 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1032 rtlpriv->link_info.num_tx_inperiod++;
1033
1034 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 1035 "CMD TX OK interrupt!\n");
c7cfe38e
C		 1036 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1037 }
1038 }
1039
38506ece 1040 /*<3> Rx related */
0c817338 1041 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
f30d7507 1042 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
c7cfe38e 1043 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1044 }
1045
1046 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1047 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 1048 "rx descriptor unavailable!\n");
c7cfe38e 1049 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1050 }
1051
38506ece 1052 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
f30d7507 1053 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
c7cfe38e 1054 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1055 }
1056
38506ece 1057 /*<4> fw related*/
26634c4b
LF		 1058 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1059 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1060 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1061 "firmware interrupt!\n");
1062 queue_delayed_work(rtlpriv->works.rtl_wq,
1063 &rtlpriv->works.fwevt_wq, 0);
1064 }
1065 }
1066
38506ece
LF		 1067 /*<5> hsisr related*/
1068 /* Only 8188EE & 8723BE Supported.
1069 * If Other ICs Come in, System will corrupt,
1070 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1071 * are not initialized
1072 */
1073 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1074 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1075 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1076 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1077 "hsisr interrupt!\n");
1078 _rtl_pci_hs_interrupt(hw);
1079 }
1080 }
1081
c7cfe38e
C		 1082 if (rtlpriv->rtlhal.earlymode_enable)
1083 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1084
0c817338 1085done:
38506ece 1086 rtlpriv->cfg->ops->enable_interrupt(hw);
0c817338 1087 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 1088 return ret;
0c817338
LF		 1089}
1090
1091static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1092{
c7cfe38e 1093 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 1094}
1095
1096static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1097{
1098 struct rtl_priv *rtlpriv = rtl_priv(hw);
1099 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1100 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 1101 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 1102 struct ieee80211_hdr *hdr = NULL;
1103 struct ieee80211_tx_info *info = NULL;
1104 struct sk_buff *pskb = NULL;
1105 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 1106 struct rtl_tcb_desc tcb_desc;
f3355dd9
LF		 1107 /*This is for new trx flow*/
1108 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
0c817338 1109 u8 temp_one = 1;
be0b5e63 1110 u8 *entry;
0c817338 1111
c7cfe38e 1112 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 1113 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1114 pskb = __skb_dequeue(&ring->queue);
be0b5e63
LF		 1115 if (rtlpriv->use_new_trx_flow)
1116 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1117 else
1118 entry = (u8 *)(&ring->desc[ring->idx]);
1119 if (pskb) {
1120 pci_unmap_single(rtlpci->pdev,
1121 rtlpriv->cfg->ops->get_desc(
1122 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1123 pskb->len, PCI_DMA_TODEVICE);
0c817338 1124 kfree_skb(pskb);
be0b5e63 1125 }
0c817338
LF		 1126
1127 /*NB: the beacon data buffer must be 32-bit aligned. */
1128 pskb = ieee80211_beacon_get(hw, mac->vif);
1129 if (pskb == NULL)
1130 return;
c7cfe38e 1131 hdr = rtl_get_hdr(pskb);
0c817338 1132 info = IEEE80211_SKB_CB(pskb);
0c817338 1133 pdesc = &ring->desc[0];
38506ece
LF		 1134 if (rtlpriv->use_new_trx_flow)
1135 pbuffer_desc = &ring->buffer_desc[0];
1136
1137 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
f3355dd9
LF		 1138 (u8 *)pbuffer_desc, info, NULL, pskb,
1139 BEACON_QUEUE, &tcb_desc);
0c817338
LF		 1140
1141 __skb_queue_tail(&ring->queue, pskb);
1142
fb6eaf2c
LF		 1143 if (rtlpriv->use_new_trx_flow) {
1144 temp_one = 4;
1145 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1146 HW_DESC_OWN, (u8 *)&temp_one);
1147 } else {
1148 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1149 &temp_one);
1150 }
0c817338
LF		 1151 return;
1152}
1153
1154static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1155{
1156 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece
LF		 1157 struct rtl_priv *rtlpriv = rtl_priv(hw);
1158 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
0c817338 1159 u8 i;
38506ece
LF		 1160 u16 desc_num;
1161
1162 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1163 desc_num = TX_DESC_NUM_92E;
1164 else
1165 desc_num = RT_TXDESC_NUM;
0c817338
LF		 1166
1167 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
38506ece 1168 rtlpci->txringcount[i] = desc_num;
0c817338
LF		 1169
1170 /*
1171 *we just alloc 2 desc for beacon queue,
1172 *because we just need first desc in hw beacon.
1173 */
1174 rtlpci->txringcount[BEACON_QUEUE] = 2;
1175
38506ece 1176 /*BE queue need more descriptor for performance
0c817338
LF		 1177 *consideration or, No more tx desc will happen,
1178 *and may cause mac80211 mem leakage.
1179 */
38506ece
LF		 1180 if (!rtl_priv(hw)->use_new_trx_flow)
1181 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
0c817338
LF		 1182
1183 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1184 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1185}
1186
1187static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1188 struct pci_dev *pdev)
1189{
1190 struct rtl_priv *rtlpriv = rtl_priv(hw);
1191 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1194
1195 rtlpci->up_first_time = true;
1196 rtlpci->being_init_adapter = false;
1197
1198 rtlhal->hw = hw;
1199 rtlpci->pdev = pdev;
1200
0c817338
LF		 1201 /*Tx/Rx related var */
1202 _rtl_pci_init_trx_var(hw);
1203
37c52934
LF		 1204 /*IBSS*/
1205 mac->beacon_interval = 100;
0c817338 1206
c7cfe38e
C		 1207 /*AMPDU*/
1208 mac->min_space_cfg = 0;
0c817338
LF		 1209 mac->max_mss_density = 0;
1210 /*set sane AMPDU defaults */
1211 mac->current_ampdu_density = 7;
1212 mac->current_ampdu_factor = 3;
1213
8d0d43e3
PKS		 1214 /*Retry Limit*/
1215 mac->retry_short = 7;
1216 mac->retry_long = 7;
1217
c7cfe38e 1218 /*QOS*/
2cddad3c 1219 rtlpci->acm_method = EACMWAY2_SW;
0c817338
LF		 1220
1221 /*task */
1222 tasklet_init(&rtlpriv->works.irq_tasklet,
1223 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1224 (unsigned long)hw);
1225 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1226 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1227 (unsigned long)hw);
a269913c
LF		 1228 INIT_WORK(&rtlpriv->works.lps_change_work,
1229 rtl_lps_change_work_callback);
0c817338
LF		 1230}
1231
1232static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1233 unsigned int prio, unsigned int entries)
1234{
1235 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1236 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece
LF		 1237 struct rtl_tx_buffer_desc *buffer_desc;
1238 struct rtl_tx_desc *desc;
1239 dma_addr_t buffer_desc_dma, desc_dma;
0c817338
LF		 1240 u32 nextdescaddress;
1241 int i;
1242
38506ece
LF		 1243 /* alloc tx buffer desc for new trx flow*/
1244 if (rtlpriv->use_new_trx_flow) {
1245 buffer_desc =
1246 pci_zalloc_consistent(rtlpci->pdev,
1247 sizeof(*buffer_desc) * entries,
1248 &buffer_desc_dma);
1249
1250 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
b03d968b
LF		 1251 pr_err("Cannot allocate TX ring (prio = %d)\n",
1252 prio);
38506ece
LF		 1253 return -ENOMEM;
1254 }
1255
1256 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1257 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1258
1259 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1260 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1261 rtlpci->tx_ring[prio].avl_desc = entries;
1262 }
1263
1264 /* alloc dma for this ring */
1265 desc = pci_zalloc_consistent(rtlpci->pdev,
1266 sizeof(*desc) * entries, &desc_dma);
1267
1268 if (!desc || (unsigned long)desc & 0xFF) {
b03d968b 1269 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
0c817338
LF		 1270 return -ENOMEM;
1271 }
1272
38506ece
LF		 1273 rtlpci->tx_ring[prio].desc = desc;
1274 rtlpci->tx_ring[prio].dma = desc_dma;
1275
0c817338
LF		 1276 rtlpci->tx_ring[prio].idx = 0;
1277 rtlpci->tx_ring[prio].entries = entries;
1278 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1279
f30d7507 1280 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
38506ece
LF		 1281 prio, desc);
1282
1283 /* init every desc in this ring */
1284 if (!rtlpriv->use_new_trx_flow) {
1285 for (i = 0; i < entries; i++) {
1286 nextdescaddress = (u32)desc_dma +
1287 ((i + 1) % entries) *
1288 sizeof(*desc);
1289
1290 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1291 true,
1292 HW_DESC_TX_NEXTDESC_ADDR,
1293 (u8 *)&nextdescaddress);
1294 }
0c817338 1295 }
0c817338
LF		 1296 return 0;
1297}
1298
38506ece 1299static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
0c817338
LF		 1300{
1301 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece 1303 int i;
0c817338 1304
38506ece
LF		 1305 if (rtlpriv->use_new_trx_flow) {
1306 struct rtl_rx_buffer_desc *entry = NULL;
1307 /* alloc dma for this ring */
1308 rtlpci->rx_ring[rxring_idx].buffer_desc =
1309 pci_zalloc_consistent(rtlpci->pdev,
1310 sizeof(*rtlpci->rx_ring[rxring_idx].
1311 buffer_desc) *
1312 rtlpci->rxringcount,
1313 &rtlpci->rx_ring[rxring_idx].dma);
1314 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1315 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
b03d968b 1316 pr_err("Cannot allocate RX ring\n");
0c817338
LF		 1317 return -ENOMEM;
1318 }
1319
38506ece
LF		 1320 /* init every desc in this ring */
1321 rtlpci->rx_ring[rxring_idx].idx = 0;
1322 for (i = 0; i < rtlpci->rxringcount; i++) {
1323 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
e9538cf4 1324 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
38506ece
LF		 1325 rxring_idx, i))
1326 return -ENOMEM;
1327 }
1328 } else {
1329 struct rtl_rx_desc *entry = NULL;
1330 u8 tmp_one = 1;
1331 /* alloc dma for this ring */
1332 rtlpci->rx_ring[rxring_idx].desc =
1333 pci_zalloc_consistent(rtlpci->pdev,
1334 sizeof(*rtlpci->rx_ring[rxring_idx].
1335 desc) * rtlpci->rxringcount,
1336 &rtlpci->rx_ring[rxring_idx].dma);
1337 if (!rtlpci->rx_ring[rxring_idx].desc ||
1338 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
b03d968b 1339 pr_err("Cannot allocate RX ring\n");
38506ece
LF		 1340 return -ENOMEM;
1341 }
0c817338 1342
38506ece
LF		 1343 /* init every desc in this ring */
1344 rtlpci->rx_ring[rxring_idx].idx = 0;
0019a2c9 1345
0c817338 1346 for (i = 0; i < rtlpci->rxringcount; i++) {
38506ece 1347 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
e9538cf4 1348 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
38506ece
LF		 1349 rxring_idx, i))
1350 return -ENOMEM;
0c817338
LF		 1351 }
1352
f3355dd9 1353 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
2c208890 1354 HW_DESC_RXERO, &tmp_one);
0c817338
LF		 1355 }
1356 return 0;
1357}
1358
1359static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1360 unsigned int prio)
1361{
1362 struct rtl_priv *rtlpriv = rtl_priv(hw);
1363 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1364 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1365
38506ece 1366 /* free every desc in this ring */
0c817338 1367 while (skb_queue_len(&ring->queue)) {
38506ece 1368 u8 *entry;
0c817338
LF		 1369 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1370
38506ece
LF		 1371 if (rtlpriv->use_new_trx_flow)
1372 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1373 else
1374 entry = (u8 *)(&ring->desc[ring->idx]);
1375
0c817338 1376 pci_unmap_single(rtlpci->pdev,
d3bb1429 1377 rtlpriv->cfg->
38506ece 1378 ops->get_desc((u8 *)entry, true,
d3bb1429 1379 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1380 skb->len, PCI_DMA_TODEVICE);
1381 kfree_skb(skb);
1382 ring->idx = (ring->idx + 1) % ring->entries;
1383 }
1384
38506ece
LF		 1385 /* free dma of this ring */
1386 pci_free_consistent(rtlpci->pdev,
1387 sizeof(*ring->desc) * ring->entries,
1388 ring->desc, ring->dma);
1389 ring->desc = NULL;
1390 if (rtlpriv->use_new_trx_flow) {
7f66c2f9 1391 pci_free_consistent(rtlpci->pdev,
caea2172 1392 sizeof(*ring->buffer_desc) * ring->entries,
38506ece 1393 ring->buffer_desc, ring->buffer_desc_dma);
caea2172 1394 ring->buffer_desc = NULL;
7f66c2f9 1395 }
0c817338
LF		 1396}
1397
38506ece 1398static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
0c817338 1399{
38506ece
LF		 1400 struct rtl_priv *rtlpriv = rtl_priv(hw);
1401 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1402 int i;
0c817338 1403
38506ece
LF		 1404 /* free every desc in this ring */
1405 for (i = 0; i < rtlpci->rxringcount; i++) {
1406 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
0c817338 1407
38506ece
LF		 1408 if (!skb)
1409 continue;
1410 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1411 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1412 kfree_skb(skb);
1413 }
1414
1415 /* free dma of this ring */
1416 if (rtlpriv->use_new_trx_flow) {
1417 pci_free_consistent(rtlpci->pdev,
1418 sizeof(*rtlpci->rx_ring[rxring_idx].
1419 buffer_desc) * rtlpci->rxringcount,
1420 rtlpci->rx_ring[rxring_idx].buffer_desc,
1421 rtlpci->rx_ring[rxring_idx].dma);
1422 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1423 } else {
1424 pci_free_consistent(rtlpci->pdev,
1425 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1426 rtlpci->rxringcount,
1427 rtlpci->rx_ring[rxring_idx].desc,
1428 rtlpci->rx_ring[rxring_idx].dma);
1429 rtlpci->rx_ring[rxring_idx].desc = NULL;
0c817338
LF		 1430 }
1431}
1432
1433static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1434{
1435 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1436 int ret;
38506ece 1437 int i, rxring_idx;
0c817338 1438
38506ece
LF		 1439 /* rxring_idx 0:RX_MPDU_QUEUE
1440 * rxring_idx 1:RX_CMD_QUEUE
1441 */
1442 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1443 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1444 if (ret)
1445 return ret;
1446 }
0c817338
LF		 1447
1448 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1449 ret = _rtl_pci_init_tx_ring(hw, i,
1450 rtlpci->txringcount[i]);
1451 if (ret)
1452 goto err_free_rings;
1453 }
1454
1455 return 0;
1456
1457err_free_rings:
38506ece
LF		 1458 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1459 _rtl_pci_free_rx_ring(hw, rxring_idx);
0c817338
LF		 1460
1461 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
38506ece
LF		 1462 if (rtlpci->tx_ring[i].desc ||
1463 rtlpci->tx_ring[i].buffer_desc)
0c817338
LF		 1464 _rtl_pci_free_tx_ring(hw, i);
1465
1466 return 1;
1467}
1468
1469static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1470{
38506ece 1471 u32 i, rxring_idx;
0c817338
LF		 1472
1473 /*free rx rings */
38506ece
LF		 1474 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1475 _rtl_pci_free_rx_ring(hw, rxring_idx);
0c817338
LF		 1476
1477 /*free tx rings */
1478 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1479 _rtl_pci_free_tx_ring(hw, i);
1480
1481 return 0;
1482}
1483
1484int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1485{
1486 struct rtl_priv *rtlpriv = rtl_priv(hw);
1487 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece 1488 int i, rxring_idx;
0c817338
LF		 1489 unsigned long flags;
1490 u8 tmp_one = 1;
38506ece
LF		 1491 u32 bufferaddress;
1492 /* rxring_idx 0:RX_MPDU_QUEUE */
1493 /* rxring_idx 1:RX_CMD_QUEUE */
1494 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1495 /* force the rx_ring[RX_MPDU_QUEUE/
1496 * RX_CMD_QUEUE].idx to the first one
1497 *new trx flow, do nothing
1498 */
1499 if (!rtlpriv->use_new_trx_flow &&
1500 rtlpci->rx_ring[rxring_idx].desc) {
0c817338
LF		 1501 struct rtl_rx_desc *entry = NULL;
1502
38506ece 1503 rtlpci->rx_ring[rxring_idx].idx = 0;
0c817338 1504 for (i = 0; i < rtlpci->rxringcount; i++) {
38506ece
LF		 1505 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1506 bufferaddress =
1507 rtlpriv->cfg->ops->get_desc((u8 *)entry,
1508 false , HW_DESC_RXBUFF_ADDR);
1509 memset((u8 *)entry , 0 ,
1510 sizeof(*rtlpci->rx_ring
1511 [rxring_idx].desc));/*clear one entry*/
1512 if (rtlpriv->use_new_trx_flow) {
1513 rtlpriv->cfg->ops->set_desc(hw,
1514 (u8 *)entry, false,
1515 HW_DESC_RX_PREPARE,
1516 (u8 *)&bufferaddress);
1517 } else {
1518 rtlpriv->cfg->ops->set_desc(hw,
1519 (u8 *)entry, false,
1520 HW_DESC_RXBUFF_ADDR,
1521 (u8 *)&bufferaddress);
1522 rtlpriv->cfg->ops->set_desc(hw,
1523 (u8 *)entry, false,
1524 HW_DESC_RXPKT_LEN,
1525 (u8 *)&rtlpci->rxbuffersize);
1526 rtlpriv->cfg->ops->set_desc(hw,
1527 (u8 *)entry, false,
1528 HW_DESC_RXOWN,
1529 (u8 *)&tmp_one);
1530 }
0c817338 1531 }
38506ece
LF		 1532 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1533 HW_DESC_RXERO, (u8 *)&tmp_one);
0c817338 1534 }
38506ece 1535 rtlpci->rx_ring[rxring_idx].idx = 0;
0c817338
LF		 1536 }
1537
1538 /*
1539 *after reset, release previous pending packet,
1540 *and force the tx idx to the first one
1541 */
38506ece 1542 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1543 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
38506ece
LF		 1544 if (rtlpci->tx_ring[i].desc ||
1545 rtlpci->tx_ring[i].buffer_desc) {
0c817338
LF		 1546 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1547
1548 while (skb_queue_len(&ring->queue)) {
38506ece
LF		 1549 u8 *entry;
1550 struct sk_buff *skb =
1551 __skb_dequeue(&ring->queue);
1552 if (rtlpriv->use_new_trx_flow)
1553 entry = (u8 *)(&ring->buffer_desc
1554 [ring->idx]);
1555 else
1556 entry = (u8 *)(&ring->desc[ring->idx]);
0c817338
LF		 1557
1558 pci_unmap_single(rtlpci->pdev,
d3bb1429 1559 rtlpriv->cfg->ops->
0c817338
LF		 1560 get_desc((u8 *)
1561 entry,
1562 true,
d3bb1429 1563 HW_DESC_TXBUFF_ADDR),
0c817338 1564 skb->len, PCI_DMA_TODEVICE);
cf968937 1565 dev_kfree_skb_irq(skb);
38506ece 1566 ring->idx = (ring->idx + 1) % ring->entries;
0c817338
LF		 1567 }
1568 ring->idx = 0;
1569 }
1570 }
38506ece 1571 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1572
0c817338
LF		 1573 return 0;
1574}
1575
c7cfe38e 1576static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
36323f81 1577 struct ieee80211_sta *sta,
c7cfe38e 1578 struct sk_buff *skb)
0c817338 1579{
c7cfe38e 1580 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e
C		 1581 struct rtl_sta_info *sta_entry = NULL;
1582 u8 tid = rtl_get_tid(skb);
0f015453 1583 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 1584
1585 if (!sta)
1586 return false;
1587 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1588
1589 if (!rtlpriv->rtlhal.earlymode_enable)
1590 return false;
0f015453
LF		 1591 if (ieee80211_is_nullfunc(fc))
1592 return false;
1593 if (ieee80211_is_qos_nullfunc(fc))
1594 return false;
1595 if (ieee80211_is_pspoll(fc))
1596 return false;
c7cfe38e
C		 1597 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1598 return false;
1599 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1600 return false;
1601 if (tid > 7)
1602 return false;
1603
1604 /* maybe every tid should be checked */
1605 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1606 return false;
1607
1608 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1609 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1610 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1611
c7cfe38e 1612 return true;
0c817338
LF		 1613}
1614
36323f81
TH		 1615static int rtl_pci_tx(struct ieee80211_hw *hw,
1616 struct ieee80211_sta *sta,
1617 struct sk_buff *skb,
1618 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1619{
1620 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1621 struct rtl_sta_info *sta_entry = NULL;
0c817338
LF		 1622 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1623 struct rtl8192_tx_ring *ring;
1624 struct rtl_tx_desc *pdesc;
f3355dd9 1625 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
38506ece 1626 u16 idx;
c7cfe38e 1627 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1628 unsigned long flags;
c7cfe38e
C		 1629 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1630 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1631 u8 *pda_addr = hdr->addr1;
1632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1633 /*ssn */
0c817338
LF		 1634 u8 tid = 0;
1635 u16 seq_number = 0;
1636 u8 own;
1637 u8 temp_one = 1;
1638
0f015453
LF		 1639 if (ieee80211_is_mgmt(fc))
1640 rtl_tx_mgmt_proc(hw, skb);
c7cfe38e
C		 1641
1642 if (rtlpriv->psc.sw_ps_enabled) {
1643 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1644 !ieee80211_has_pm(fc))
1645 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1646 }
0c817338 1647
c7cfe38e 1648 rtl_action_proc(hw, skb, true);
0c817338
LF		 1649
1650 if (is_multicast_ether_addr(pda_addr))
1651 rtlpriv->stats.txbytesmulticast += skb->len;
1652 else if (is_broadcast_ether_addr(pda_addr))
1653 rtlpriv->stats.txbytesbroadcast += skb->len;
1654 else
1655 rtlpriv->stats.txbytesunicast += skb->len;
1656
1657 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1658 ring = &rtlpci->tx_ring[hw_queue];
38506ece
LF		 1659 if (hw_queue != BEACON_QUEUE) {
1660 if (rtlpriv->use_new_trx_flow)
1661 idx = ring->cur_tx_wp;
1662 else
1663 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1664 ring->entries;
1665 } else {
0c817338 1666 idx = 0;
38506ece 1667 }
0c817338
LF		 1668
1669 pdesc = &ring->desc[idx];
f3355dd9
LF		 1670 if (rtlpriv->use_new_trx_flow) {
1671 ptx_bd_desc = &ring->buffer_desc[idx];
1672 } else {
1673 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
1674 true, HW_DESC_OWN);
0c817338 1675
f3355dd9
LF		 1676 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1677 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
4f4378de 1678 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
f3355dd9
LF		 1679 hw_queue, ring->idx, idx,
1680 skb_queue_len(&ring->queue));
0c817338 1681
f3355dd9
LF		 1682 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1683 flags);
1684 return skb->len;
1685 }
0c817338
LF		 1686 }
1687
d0311314
TT		 1688 if (rtlpriv->cfg->ops->get_available_desc &&
1689 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1690 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1691 "get_available_desc fail\n");
1692 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1693 flags);
1694 return skb->len;
1695 }
1696
0c817338 1697 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1698 tid = rtl_get_tid(skb);
1699 if (sta) {
1700 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1701 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1702 IEEE80211_SCTL_SEQ) >> 4;
1703 seq_number += 1;
1704
1705 if (!ieee80211_has_morefrags(hdr->frame_control))
1706 sta_entry->tids[tid].seq_number = seq_number;
1707 }
0c817338
LF		 1708 }
1709
1710 if (ieee80211_is_data(fc))
1711 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1712
c7cfe38e 1713 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
f3355dd9 1714 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
0c817338
LF		 1715
1716 __skb_queue_tail(&ring->queue, skb);
1717
f3355dd9
LF		 1718 if (rtlpriv->use_new_trx_flow) {
1719 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
9cb76aa9 1720 HW_DESC_OWN, &hw_queue);
f3355dd9
LF		 1721 } else {
1722 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
9cb76aa9 1723 HW_DESC_OWN, &temp_one);
f3355dd9 1724 }
0c817338
LF		 1725
1726 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1727 hw_queue != BEACON_QUEUE) {
0c817338 1728 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
4f4378de 1729 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
f30d7507
JP		 1730 hw_queue, ring->idx, idx,
1731 skb_queue_len(&ring->queue));
0c817338
LF		 1732
1733 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1734 }
1735
1736 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1737
1738 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1739
1740 return 0;
1741}
1742
38506ece 1743static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
c7cfe38e
C		 1744{
1745 struct rtl_priv *rtlpriv = rtl_priv(hw);
1746 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1747 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
26634c4b 1748 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e
C		 1749 u16 i = 0;
1750 int queue_id;
1751 struct rtl8192_tx_ring *ring;
1752
26634c4b
LF		 1753 if (mac->skip_scan)
1754 return;
1755
c7cfe38e
C		 1756 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1757 u32 queue_len;
38506ece
LF		 1758
1759 if (((queues >> queue_id) & 0x1) == 0) {
1760 queue_id--;
1761 continue;
1762 }
c7cfe38e
C		 1763 ring = &pcipriv->dev.tx_ring[queue_id];
1764 queue_len = skb_queue_len(&ring->queue);
1765 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1766 queue_id == TXCMD_QUEUE) {
1767 queue_id--;
1768 continue;
1769 } else {
1770 msleep(20);
1771 i++;
1772 }
1773
1774 /* we just wait 1s for all queues */
1775 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1776 is_hal_stop(rtlhal) || i >= 200)
1777 return;
1778 }
1779}
1780
d3bb1429 1781static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1782{
1783 struct rtl_priv *rtlpriv = rtl_priv(hw);
1784 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1785
1786 _rtl_pci_deinit_trx_ring(hw);
1787
1788 synchronize_irq(rtlpci->pdev->irq);
1789 tasklet_kill(&rtlpriv->works.irq_tasklet);
a269913c 1790 cancel_work_sync(&rtlpriv->works.lps_change_work);
0c817338
LF		 1791
1792 flush_workqueue(rtlpriv->works.rtl_wq);
1793 destroy_workqueue(rtlpriv->works.rtl_wq);
1794
1795}
1796
d3bb1429 1797static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338 1798{
0c817338
LF		 1799 int err;
1800
1801 _rtl_pci_init_struct(hw, pdev);
1802
1803 err = _rtl_pci_init_trx_ring(hw);
1804 if (err) {
b03d968b 1805 pr_err("tx ring initialization failed\n");
12325280 1806 return err;
0c817338
LF		 1807 }
1808
12325280 1809 return 0;
0c817338
LF		 1810}
1811
d3bb1429 1812static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1813{
1814 struct rtl_priv *rtlpriv = rtl_priv(hw);
1815 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1816 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1817 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
8d0d43e3 1818 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
0c817338
LF		 1819
1820 int err;
1821
1822 rtl_pci_reset_trx_ring(hw);
1823
1824 rtlpci->driver_is_goingto_unload = false;
08054200
LF		 1825 if (rtlpriv->cfg->ops->get_btc_status &&
1826 rtlpriv->cfg->ops->get_btc_status()) {
38506ece
LF		 1827 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1828 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1829 }
0c817338
LF		 1830 err = rtlpriv->cfg->ops->hw_init(hw);
1831 if (err) {
1832 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507 1833 "Failed to config hardware!\n");
0c817338
LF		 1834 return err;
1835 }
8d0d43e3
PKS		 1836 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1837 &rtlmac->retry_long);
0c817338
LF		 1838
1839 rtlpriv->cfg->ops->enable_interrupt(hw);
f30d7507 1840 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
0c817338
LF		 1841
1842 rtl_init_rx_config(hw);
1843
fb914ebf 1844 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1845 set_hal_start(rtlhal);
1846
1847 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1848
1849 rtlpci->up_first_time = false;
1850
38506ece 1851 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n");
0c817338
LF		 1852 return 0;
1853}
1854
d3bb1429 1855static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1856{
1857 struct rtl_priv *rtlpriv = rtl_priv(hw);
1858 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1859 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1860 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1861 unsigned long flags;
1862 u8 RFInProgressTimeOut = 0;
1863
38506ece
LF		 1864 if (rtlpriv->cfg->ops->get_btc_status())
1865 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
1866
0c817338 1867 /*
fb914ebf 1868 *should be before disable interrupt&adapter
0c817338
LF		 1869 *and will do it immediately.
1870 */
1871 set_hal_stop(rtlhal);
1872
9278db62 1873 rtlpci->driver_is_goingto_unload = true;
0c817338 1874 rtlpriv->cfg->ops->disable_interrupt(hw);
a269913c 1875 cancel_work_sync(&rtlpriv->works.lps_change_work);
0c817338
LF		 1876
1877 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1878 while (ppsc->rfchange_inprogress) {
1879 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1880 if (RFInProgressTimeOut > 100) {
1881 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1882 break;
1883 }
1884 mdelay(1);
1885 RFInProgressTimeOut++;
1886 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1887 }
1888 ppsc->rfchange_inprogress = true;
1889 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1890
0c817338 1891 rtlpriv->cfg->ops->hw_disable(hw);
b0302aba
LF		 1892 /* some things are not needed if firmware not available */
1893 if (!rtlpriv->max_fw_size)
1894 return;
0c817338
LF		 1895 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1896
1897 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1898 ppsc->rfchange_inprogress = false;
1899 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1900
1901 rtl_pci_enable_aspm(hw);
1902}
1903
1904static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1905 struct ieee80211_hw *hw)
1906{
1907 struct rtl_priv *rtlpriv = rtl_priv(hw);
1908 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1909 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1910 struct pci_dev *bridge_pdev = pdev->bus->self;
1911 u16 venderid;
1912 u16 deviceid;
c7cfe38e 1913 u8 revisionid;
0c817338
LF		 1914 u16 irqline;
1915 u8 tmp;
1916
fc7707a4 1917 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1918 venderid = pdev->vendor;
1919 deviceid = pdev->device;
c7cfe38e 1920 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1921 pci_read_config_word(pdev, 0x3C, &irqline);
1922
fa7ccfb1
LF		 1923 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1924 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1925 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1926 * the correct driver is r8192e_pci, thus this routine should
1927 * return false.
1928 */
1929 if (deviceid == RTL_PCI_8192SE_DID &&
1930 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1931 return false;
1932
0c817338
LF		 1933 if (deviceid == RTL_PCI_8192_DID ||
1934 deviceid == RTL_PCI_0044_DID ||
1935 deviceid == RTL_PCI_0047_DID ||
1936 deviceid == RTL_PCI_8192SE_DID ||
1937 deviceid == RTL_PCI_8174_DID ||
1938 deviceid == RTL_PCI_8173_DID ||
1939 deviceid == RTL_PCI_8172_DID ||
1940 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1941 switch (revisionid) {
0c817338
LF		 1942 case RTL_PCI_REVISION_ID_8192PCIE:
1943 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1944 "8192 PCI-E is found - vid/did=%x/%x\n",
1945 venderid, deviceid);
0c817338 1946 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
0f015453 1947 return false;
0c817338
LF		 1948 case RTL_PCI_REVISION_ID_8192SE:
1949 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1950 "8192SE is found - vid/did=%x/%x\n",
1951 venderid, deviceid);
0c817338
LF		 1952 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1953 break;
1954 default:
1955 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1956 "Err: Unknown device - vid/did=%x/%x\n",
1957 venderid, deviceid);
0c817338
LF		 1958 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1959 break;
1960
1961 }
0f015453
LF		 1962 } else if (deviceid == RTL_PCI_8723AE_DID) {
1963 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1964 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1965 "8723AE PCI-E is found - "
1966 "vid/did=%x/%x\n", venderid, deviceid);
0c817338
LF		 1967 } else if (deviceid == RTL_PCI_8192CET_DID ||
1968 deviceid == RTL_PCI_8192CE_DID ||
1969 deviceid == RTL_PCI_8191CE_DID ||
1970 deviceid == RTL_PCI_8188CE_DID) {
1971 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1972 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1973 "8192C PCI-E is found - vid/did=%x/%x\n",
1974 venderid, deviceid);
c7cfe38e
C		 1975 } else if (deviceid == RTL_PCI_8192DE_DID ||
1976 deviceid == RTL_PCI_8192DE_DID2) {
1977 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1978 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1979 "8192D PCI-E is found - vid/did=%x/%x\n",
1980 venderid, deviceid);
5c69177d
LF		 1981 } else if (deviceid == RTL_PCI_8188EE_DID) {
1982 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1983 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1984 "Find adapter, Hardware type is 8188EE\n");
38506ece
LF		 1985 } else if (deviceid == RTL_PCI_8723BE_DID) {
1986 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1987 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1988 "Find adapter, Hardware type is 8723BE\n");
1989 } else if (deviceid == RTL_PCI_8192EE_DID) {
1990 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1991 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1992 "Find adapter, Hardware type is 8192EE\n");
1993 } else if (deviceid == RTL_PCI_8821AE_DID) {
1994 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1995 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1996 "Find adapter, Hardware type is 8821AE\n");
1997 } else if (deviceid == RTL_PCI_8812AE_DID) {
1998 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1999 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
2000 "Find adapter, Hardware type is 8812AE\n");
0c817338
LF		 2001 } else {
2002 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 2003 "Err: Unknown device - vid/did=%x/%x\n",
2004 venderid, deviceid);
0c817338
LF		 2005
2006 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2007 }
2008
c7cfe38e
C		 2009 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2010 if (revisionid == 0 || revisionid == 1) {
2011 if (revisionid == 0) {
f30d7507
JP		 2012 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2013 "Find 92DE MAC0\n");
c7cfe38e
C		 2014 rtlhal->interfaceindex = 0;
2015 } else if (revisionid == 1) {
2016 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 2017 "Find 92DE MAC1\n");
c7cfe38e
C		 2018 rtlhal->interfaceindex = 1;
2019 }
2020 } else {
2021 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 2022 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2023 venderid, deviceid, revisionid);
c7cfe38e
C		 2024 rtlhal->interfaceindex = 0;
2025 }
2026 }
38506ece
LF		 2027
2028 /* 92ee use new trx flow */
2029 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
2030 rtlpriv->use_new_trx_flow = true;
2031 else
2032 rtlpriv->use_new_trx_flow = false;
2033
0c817338
LF		 2034 /*find bus info */
2035 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2036 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2037 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2038
38506ece
LF		 2039 /*find bridge info */
2040 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
26634c4b
LF		 2041 /* some ARM have no bridge_pdev and will crash here
2042 * so we should check if bridge_pdev is NULL
2043 */
b6b67df3
LF		 2044 if (bridge_pdev) {
2045 /*find bridge info if available */
2046 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2047 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2048 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2049 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2050 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2051 "Pci Bridge Vendor is found index: %d\n",
2052 tmp);
b6b67df3
LF		 2053 break;
2054 }
0c817338
LF		 2055 }
2056 }
2057
2058 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2059 PCI_BRIDGE_VENDOR_UNKNOWN) {
2060 pcipriv->ndis_adapter.pcibridge_busnum =
2061 bridge_pdev->bus->number;
2062 pcipriv->ndis_adapter.pcibridge_devnum =
2063 PCI_SLOT(bridge_pdev->devfn);
2064 pcipriv->ndis_adapter.pcibridge_funcnum =
2065 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 2066 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2067 pci_pcie_cap(bridge_pdev);
0c817338
LF		 2068 pcipriv->ndis_adapter.num4bytes =
2069 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2070
2071 rtl_pci_get_linkcontrol_field(hw);
2072
2073 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2074 PCI_BRIDGE_VENDOR_AMD) {
2075 pcipriv->ndis_adapter.amd_l1_patch =
2076 rtl_pci_get_amd_l1_patch(hw);
2077 }
2078 }
2079
2080 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2081 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2082 pcipriv->ndis_adapter.busnumber,
2083 pcipriv->ndis_adapter.devnumber,
2084 pcipriv->ndis_adapter.funcnumber,
2085 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 2086
2087 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2088 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2089 pcipriv->ndis_adapter.pcibridge_busnum,
2090 pcipriv->ndis_adapter.pcibridge_devnum,
2091 pcipriv->ndis_adapter.pcibridge_funcnum,
2092 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2093 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2094 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2095 pcipriv->ndis_adapter.amd_l1_patch);
0c817338
LF		 2096
2097 rtl_pci_parse_configuration(pdev, hw);
26634c4b 2098 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
0c817338
LF		 2099
2100 return true;
2101}
2102
94010fa0
AL		 2103static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2104{
2105 struct rtl_priv *rtlpriv = rtl_priv(hw);
2106 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2107 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2108 int ret;
2109
2110 ret = pci_enable_msi(rtlpci->pdev);
2111 if (ret < 0)
2112 return ret;
2113
2114 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2115 IRQF_SHARED, KBUILD_MODNAME, hw);
2116 if (ret < 0) {
2117 pci_disable_msi(rtlpci->pdev);
2118 return ret;
2119 }
2120
2121 rtlpci->using_msi = true;
2122
2123 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2124 "MSI Interrupt Mode!\n");
2125 return 0;
2126}
2127
2128static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2129{
2130 struct rtl_priv *rtlpriv = rtl_priv(hw);
2131 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2132 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2133 int ret;
2134
2135 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2136 IRQF_SHARED, KBUILD_MODNAME, hw);
2137 if (ret < 0)
2138 return ret;
2139
2140 rtlpci->using_msi = false;
2141 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2142 "Pin-based Interrupt Mode!\n");
2143 return 0;
2144}
2145
2146static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2147{
2148 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2149 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2150 int ret;
2151
2152 if (rtlpci->msi_support) {
2153 ret = rtl_pci_intr_mode_msi(hw);
2154 if (ret < 0)
2155 ret = rtl_pci_intr_mode_legacy(hw);
2156 } else {
2157 ret = rtl_pci_intr_mode_legacy(hw);
2158 }
2159 return ret;
2160}
2161
9e2ff36b 2162int rtl_pci_probe(struct pci_dev *pdev,
0c817338
LF		 2163 const struct pci_device_id *id)
2164{
2165 struct ieee80211_hw *hw = NULL;
2166
2167 struct rtl_priv *rtlpriv = NULL;
2168 struct rtl_pci_priv *pcipriv = NULL;
2169 struct rtl_pci *rtlpci;
2170 unsigned long pmem_start, pmem_len, pmem_flags;
2171 int err;
2172
2173 err = pci_enable_device(pdev);
2174 if (err) {
531940f9 2175 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
9d833ed7 2176 pci_name(pdev));
0c817338
LF		 2177 return err;
2178 }
2179
2180 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2181 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
531940f9
LF		 2182 WARN_ONCE(true,
2183 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
3d86b930
TG		 2184 err = -ENOMEM;
2185 goto fail1;
0c817338
LF		 2186 }
2187 }
2188
2189 pci_set_master(pdev);
2190
2191 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2192 sizeof(struct rtl_priv), &rtl_ops);
2193 if (!hw) {
531940f9 2194 WARN_ONCE(true,
9d833ed7 2195 "%s : ieee80211 alloc failed\n", pci_name(pdev));
0c817338
LF		 2196 err = -ENOMEM;
2197 goto fail1;
2198 }
2199
2200 SET_IEEE80211_DEV(hw, &pdev->dev);
2201 pci_set_drvdata(pdev, hw);
2202
2203 rtlpriv = hw->priv;
26634c4b 2204 rtlpriv->hw = hw;
0c817338
LF		 2205 pcipriv = (void *)rtlpriv->priv;
2206 pcipriv->dev.pdev = pdev;
b0302aba 2207 init_completion(&rtlpriv->firmware_loading_complete);
38506ece
LF		 2208 /*proximity init here*/
2209 rtlpriv->proximity.proxim_on = false;
2210
2211 pcipriv = (void *)rtlpriv->priv;
2212 pcipriv->dev.pdev = pdev;
0c817338 2213
c7cfe38e
C		 2214 /* init cfg & intf_ops */
2215 rtlpriv->rtlhal.interface = INTF_PCI;
2216 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2217 rtlpriv->intf_ops = &rtl_pci_ops;
6f334c2b 2218 rtlpriv->glb_var = &rtl_global_var;
c7cfe38e 2219
0c817338
LF		 2220 /* MEM map */
2221 err = pci_request_regions(pdev, KBUILD_MODNAME);
2222 if (err) {
531940f9 2223 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
3d86b930 2224 goto fail1;
0c817338
LF		 2225 }
2226
c7cfe38e
C		 2227 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2228 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2229 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 2230
2231 /*shared mem start */
2232 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 2233 (unsigned long)pci_iomap(pdev,
2234 rtlpriv->cfg->bar_id, pmem_len);
0c817338 2235 if (rtlpriv->io.pci_mem_start == 0) {
531940f9 2236 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
3d86b930 2237 err = -ENOMEM;
0c817338
LF		 2238 goto fail2;
2239 }
2240
2241 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2242 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2243 pmem_start, pmem_len, pmem_flags,
2244 rtlpriv->io.pci_mem_start);
0c817338
LF		 2245
2246 /* Disable Clk Request */
2247 pci_write_config_byte(pdev, 0x81, 0);
2248 /* leave D3 mode */
2249 pci_write_config_byte(pdev, 0x44, 0);
2250 pci_write_config_byte(pdev, 0x04, 0x06);
2251 pci_write_config_byte(pdev, 0x04, 0x07);
2252
0c817338 2253 /* find adapter */
3d86b930
TG		 2254 if (!_rtl_pci_find_adapter(pdev, hw)) {
2255 err = -ENODEV;
fa7ccfb1 2256 goto fail3;
3d86b930 2257 }
0c817338
LF		 2258
2259 /* Init IO handler */
2260 _rtl_pci_io_handler_init(&pdev->dev, hw);
2261
2262 /*like read eeprom and so on */
2263 rtlpriv->cfg->ops->read_eeprom_info(hw);
2264
7d63a5f9 2265 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
b03d968b 2266 pr_err("Can't init_sw_vars\n");
7d63a5f9
LF		 2267 err = -ENODEV;
2268 goto fail3;
2269 }
2270 rtlpriv->cfg->ops->init_sw_leds(hw);
2271
2272 /*aspm */
2273 rtl_pci_init_aspm(hw);
2274
0c817338
LF		 2275 /* Init mac80211 sw */
2276 err = rtl_init_core(hw);
2277 if (err) {
b03d968b 2278 pr_err("Can't allocate sw for mac80211\n");
0c817338
LF		 2279 goto fail3;
2280 }
2281
2282 /* Init PCI sw */
12325280 2283 err = rtl_pci_init(hw, pdev);
0c817338 2284 if (err) {
b03d968b 2285 pr_err("Failed to init PCI\n");
0c817338
LF		 2286 goto fail3;
2287 }
2288
38506ece
LF		 2289 err = ieee80211_register_hw(hw);
2290 if (err) {
b03d968b 2291 pr_err("Can't register mac80211 hw.\n");
574e02ab
LF		 2292 err = -ENODEV;
2293 goto fail3;
2294 }
38506ece 2295 rtlpriv->mac80211.mac80211_registered = 1;
574e02ab 2296
38506ece
LF		 2297 /*init rfkill */
2298 rtl_init_rfkill(hw); /* Init PCI sw */
2299
0c817338 2300 rtlpci = rtl_pcidev(pcipriv);
94010fa0 2301 err = rtl_pci_intr_mode_decide(hw);
0c817338
LF		 2302 if (err) {
2303 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 2304 "%s: failed to register IRQ handler\n",
2305 wiphy_name(hw->wiphy));
0c817338 2306 goto fail3;
0c817338 2307 }
b0302aba 2308 rtlpci->irq_alloc = 1;
0c817338 2309
38506ece 2310 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
0c817338
LF		 2311 return 0;
2312
2313fail3:
38506ece 2314 pci_set_drvdata(pdev, NULL);
0c817338 2315 rtl_deinit_core(hw);
0c817338
LF		 2316
2317 if (rtlpriv->io.pci_mem_start != 0)
62e63975 2318 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2319
2320fail2:
2321 pci_release_regions(pdev);
b0302aba 2322 complete(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2323
2324fail1:
3d86b930
TG		 2325 if (hw)
2326 ieee80211_free_hw(hw);
0c817338
LF		 2327 pci_disable_device(pdev);
2328
3d86b930 2329 return err;
0c817338
LF		 2330
2331}
2332EXPORT_SYMBOL(rtl_pci_probe);
2333
2334void rtl_pci_disconnect(struct pci_dev *pdev)
2335{
2336 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2337 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2338 struct rtl_priv *rtlpriv = rtl_priv(hw);
2339 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2340 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2341
b0302aba
LF		 2342 /* just in case driver is removed before firmware callback */
2343 wait_for_completion(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2344 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2345
0c817338
LF		 2346 /*ieee80211_unregister_hw will call ops_stop */
2347 if (rtlmac->mac80211_registered == 1) {
2348 ieee80211_unregister_hw(hw);
2349 rtlmac->mac80211_registered = 0;
2350 } else {
2351 rtl_deinit_deferred_work(hw);
2352 rtlpriv->intf_ops->adapter_stop(hw);
2353 }
44eb65cf 2354 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 2355
2356 /*deinit rfkill */
2357 rtl_deinit_rfkill(hw);
2358
2359 rtl_pci_deinit(hw);
2360 rtl_deinit_core(hw);
0c817338
LF		 2361 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2362
2363 if (rtlpci->irq_alloc) {
2364 free_irq(rtlpci->pdev->irq, hw);
2365 rtlpci->irq_alloc = 0;
2366 }
2367
94010fa0
AL		 2368 if (rtlpci->using_msi)
2369 pci_disable_msi(rtlpci->pdev);
2370
26634c4b 2371 list_del(&rtlpriv->list);
0c817338 2372 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 2373 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2374 pci_release_regions(pdev);
2375 }
2376
2377 pci_disable_device(pdev);
c7cfe38e
C		 2378
2379 rtl_pci_disable_aspm(hw);
2380
38506ece
LF		 2381 pci_set_drvdata(pdev, NULL);
2382
0c817338
LF		 2383 ieee80211_free_hw(hw);
2384}
2385EXPORT_SYMBOL(rtl_pci_disconnect);
2386
244a77e9 2387#ifdef CONFIG_PM_SLEEP
0c817338
LF		 2388/***************************************
2389kernel pci power state define:
2390PCI_D0 ((pci_power_t __force) 0)
2391PCI_D1 ((pci_power_t __force) 1)
2392PCI_D2 ((pci_power_t __force) 2)
2393PCI_D3hot ((pci_power_t __force) 3)
2394PCI_D3cold ((pci_power_t __force) 4)
2395PCI_UNKNOWN ((pci_power_t __force) 5)
2396
2397This function is called when system
2398goes into suspend state mac80211 will
2399call rtl_mac_stop() from the mac80211
2400suspend function first, So there is
2401no need to call hw_disable here.
2402****************************************/
603be388 2403int rtl_pci_suspend(struct device *dev)
0c817338 2404{
603be388 2405 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2406 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2407 struct rtl_priv *rtlpriv = rtl_priv(hw);
2408
2409 rtlpriv->cfg->ops->hw_suspend(hw);
2410 rtl_deinit_rfkill(hw);
2411
0c817338
LF		 2412 return 0;
2413}
2414EXPORT_SYMBOL(rtl_pci_suspend);
2415
603be388 2416int rtl_pci_resume(struct device *dev)
0c817338 2417{
603be388 2418 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2419 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2420 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 2421
c7cfe38e
C		 2422 rtlpriv->cfg->ops->hw_resume(hw);
2423 rtl_init_rfkill(hw);
0c817338
LF		 2424 return 0;
2425}
2426EXPORT_SYMBOL(rtl_pci_resume);
244a77e9 2427#endif /* CONFIG_PM_SLEEP */
0c817338 2428
1bfcfdcc 2429const struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2430 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2431 .adapter_start = rtl_pci_start,
2432 .adapter_stop = rtl_pci_stop,
26634c4b 2433 .check_buddy_priv = rtl_pci_check_buddy_priv,
0c817338 2434 .adapter_tx = rtl_pci_tx,
c7cfe38e 2435 .flush = rtl_pci_flush,
0c817338 2436 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2437 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2438
2439 .disable_aspm = rtl_pci_disable_aspm,
2440 .enable_aspm = rtl_pci_enable_aspm,
2441};
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