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UBUNTU: Ubuntu-5.11.0-22.23
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / realtek / rtlwifi / pci.c
CommitLineData
d27a76fa
LF		 1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2009-2012 Realtek Corporation.*/
0c817338 3
0c817338 4#include "wifi.h"
d273bb20 5#include "core.h"
0c817338
LF		 6#include "pci.h"
7#include "base.h"
8#include "ps.h"
c7cfe38e 9#include "efuse.h"
38506ece 10#include <linux/interrupt.h>
d273bb20 11#include <linux/export.h>
6f334c2b
LF		 12#include <linux/module.h>
13
14MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17MODULE_LICENSE("GPL");
18MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
0c817338
LF		 19
20static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38506ece
LF		 21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
0c817338
LF		 25};
26
c7cfe38e
C		 27static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32};
33
ae0122b6 34static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
c7cfe38e
C		 35{
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 37 __le16 fc = rtl_get_fc(skb);
c7cfe38e 38 u8 queue_index = skb_get_queue_mapping(skb);
e298be2a 39 struct ieee80211_hdr *hdr;
c7cfe38e
C		 40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
26634c4b 43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
c7cfe38e
C		 44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
e298be2a
PKS		 48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
c7cfe38e
C		 55
56 return ac_to_hwq[queue_index];
57}
58
0c817338
LF		 59/* Update PCI dependent default settings*/
60static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61{
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 67 u8 init_aspm;
0c817338
LF		 68
69 ppsc->reg_rfps_level = 0;
3db1cd5c 70 ppsc->support_aspm = false;
0c817338
LF		 71
72 /*Update PCI ASPM setting */
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76 /*No ASPM */
77 break;
78
79 case 1:
80 /*ASPM dynamically enabled/disable. */
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85 /*ASPM with Clock Req dynamically enabled/disable. */
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
ae0122b6 91 /* Always enable ASPM and Clock Req
0c817338 92 * from initialization to halt.
ae0122b6 93 */
0c817338
LF		 94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
ae0122b6 100 /* Always enable ASPM without Clock Req
0c817338 101 * from initialization to halt.
ae0122b6 102 */
0c817338
LF		 103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111 /*Update Radio OFF setting */
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129 /*Set HW definition to determine if it supports ASPM. */
130 switch (rtlpci->const_support_pciaspm) {
5f647f4d
LF		 131 case 0:
132 /*Not support ASPM. */
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136 /*Support ASPM. */
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
0c817338
LF		 140 case 2:
141 /*ASPM value set by chipset. */
5f647f4d
LF		 142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
0c817338
LF		 144 break;
145 default:
b03d968b
LF		 146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
0c817338
LF		 148 break;
149 }
c7cfe38e
C		 150
151 /* toshiba aspm issue, toshiba will set aspm selfly
ae0122b6
LF		 152 * so we should not set aspm in driver
153 */
c7cfe38e
C		 154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
ae0122b6 156 init_aspm == 0x43)
c7cfe38e
C		 157 ppsc->support_aspm = false;
158}
159
0c817338
LF		 160static bool _rtl_pci_platform_switch_device_pci_aspm(
161 struct ieee80211_hw *hw,
162 u8 value)
163{
164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166
167 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
168 value |= 0x40;
0c817338 169
0c817338
LF		 170 pci_write_config_byte(rtlpci->pdev, 0x80, value);
171
32473284 172 return false;
0c817338
LF		 173}
174
175/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
1d73c51a 176static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0c817338
LF		 177{
178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 180
0c817338 181 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 182
c7cfe38e
C		 183 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
184 udelay(100);
0c817338
LF		 185}
186
187/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
188static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
189{
190 struct rtl_priv *rtlpriv = rtl_priv(hw);
191 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
194 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 195 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
196 /*Retrieve original configuration settings. */
197 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
198 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
199 pcibridge_linkctrlreg;
200 u16 aspmlevel = 0;
32473284 201 u8 tmp_u1b = 0;
0c817338 202
c7cfe38e
C		 203 if (!ppsc->support_aspm)
204 return;
205
0c817338 206 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
f108a420
LF		 207 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
208 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 209
210 return;
211 }
212
213 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
214 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
215 _rtl_pci_switch_clk_req(hw, 0x0);
216 }
217
32473284
LF		 218 /*for promising device will in L0 state after an I/O. */
219 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 220
221 /*Set corresponding value. */
222 aspmlevel |= BIT(0) | BIT(1);
223 linkctrl_reg &= ~aspmlevel;
224 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
225
226 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
227 udelay(50);
228
229 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 230 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
231 pcibridge_linkctrlreg);
0c817338
LF		 232
233 udelay(50);
0c817338
LF		 234}
235
ae0122b6 236/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
0c817338
LF		 237 *power saving We should follow the sequence to enable
238 *RTL8192SE first then enable Pci Bridge ASPM
239 *or the system will show bluescreen.
240 */
241static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
242{
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
246 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 247 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 248 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
249 u16 aspmlevel;
250 u8 u_pcibridge_aspmsetting;
251 u8 u_device_aspmsetting;
252
c7cfe38e
C		 253 if (!ppsc->support_aspm)
254 return;
255
0c817338 256 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
f108a420
LF		 257 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
258 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 259 return;
260 }
261
262 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 263
264 u_pcibridge_aspmsetting =
265 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
266 rtlpci->const_hostpci_aspm_setting;
267
268 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
269 u_pcibridge_aspmsetting &= ~BIT(0);
270
886e14b6
LF		 271 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
272 u_pcibridge_aspmsetting);
0c817338 273
f108a420
LF		 274 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
275 "PlatformEnableASPM(): Write reg[%x] = %x\n",
276 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
277 u_pcibridge_aspmsetting);
0c817338
LF		 278
279 udelay(50);
280
281 /*Get ASPM level (with/without Clock Req) */
282 aspmlevel = rtlpci->const_devicepci_aspm_setting;
283 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
284
285 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
286 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
287
288 u_device_aspmsetting |= aspmlevel;
289
290 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
291
292 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
293 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
294 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
295 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
296 }
c7cfe38e 297 udelay(100);
0c817338
LF		 298}
299
300static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
301{
886e14b6 302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 303
304 bool status = false;
305 u8 offset_e0;
ae0122b6 306 unsigned int offset_e4;
0c817338 307
886e14b6 308 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 309
886e14b6 310 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 311
312 if (offset_e0 == 0xA0) {
886e14b6 313 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 314 if (offset_e4 & BIT(23))
315 status = true;
316 }
317
318 return status;
319}
320
26634c4b
LF		 321static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
322 struct rtl_priv **buddy_priv)
323{
324 struct rtl_priv *rtlpriv = rtl_priv(hw);
325 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
326 bool find_buddy_priv = false;
37c52934 327 struct rtl_priv *tpriv;
26634c4b
LF		 328 struct rtl_pci_priv *tpcipriv = NULL;
329
330 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
331 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
332 list) {
37c52934 333 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
f108a420
LF		 334 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
335 "pcipriv->ndis_adapter.funcnumber %x\n",
37c52934 336 pcipriv->ndis_adapter.funcnumber);
f108a420
LF		 337 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
338 "tpcipriv->ndis_adapter.funcnumber %x\n",
37c52934
LF		 339 tpcipriv->ndis_adapter.funcnumber);
340
ae0122b6
LF		 341 if (pcipriv->ndis_adapter.busnumber ==
342 tpcipriv->ndis_adapter.busnumber &&
343 pcipriv->ndis_adapter.devnumber ==
344 tpcipriv->ndis_adapter.devnumber &&
345 pcipriv->ndis_adapter.funcnumber !=
346 tpcipriv->ndis_adapter.funcnumber) {
37c52934
LF		 347 find_buddy_priv = true;
348 break;
26634c4b
LF		 349 }
350 }
351 }
352
f108a420
LF		 353 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
354 "find_buddy_priv %d\n", find_buddy_priv);
26634c4b
LF		 355
356 if (find_buddy_priv)
357 *buddy_priv = tpriv;
358
359 return find_buddy_priv;
360}
361
d3bb1429 362static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 363{
364 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 365 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 366 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 367 u8 linkctrl_reg;
c7cfe38e 368 u8 num4bbytes;
0c817338 369
c7cfe38e 370 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 371
372 /*Read Link Control Register */
886e14b6 373 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 374
375 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
376}
377
378static void rtl_pci_parse_configuration(struct pci_dev *pdev,
ae0122b6 379 struct ieee80211_hw *hw)
0c817338
LF		 380{
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
383
384 u8 tmp;
332badc3 385 u16 linkctrl_reg;
0c817338
LF		 386
387 /*Link Control Register */
332badc3
JL		 388 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
389 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
0c817338 390
f108a420
LF		 391 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
392 pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 393
394 pci_read_config_byte(pdev, 0x98, &tmp);
395 tmp |= BIT(4);
396 pci_write_config_byte(pdev, 0x98, tmp);
397
398 tmp = 0x17;
399 pci_write_config_byte(pdev, 0x70f, tmp);
400}
401
c7cfe38e 402static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 403{
404 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
405
406 _rtl_pci_update_default_setting(hw);
407
408 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
409 /*Always enable ASPM & Clock Req. */
410 rtl_pci_enable_aspm(hw);
411 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
412 }
0c817338
LF		 413}
414
0c817338
LF		 415static void _rtl_pci_io_handler_init(struct device *dev,
416 struct ieee80211_hw *hw)
417{
418 struct rtl_priv *rtlpriv = rtl_priv(hw);
419
420 rtlpriv->io.dev = dev;
421
422 rtlpriv->io.write8_async = pci_write8_async;
423 rtlpriv->io.write16_async = pci_write16_async;
424 rtlpriv->io.write32_async = pci_write32_async;
425
426 rtlpriv->io.read8_sync = pci_read8_sync;
427 rtlpriv->io.read16_sync = pci_read16_sync;
428 rtlpriv->io.read32_sync = pci_read32_sync;
0c817338
LF		 429}
430
c7cfe38e 431static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
ae0122b6
LF		 432 struct sk_buff *skb,
433 struct rtl_tcb_desc *tcb_desc, u8 tid)
c7cfe38e
C		 434{
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
26634c4b 437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
c7cfe38e 438 struct sk_buff *next_skb;
26634c4b 439 u8 additionlen = FCS_LEN;
c7cfe38e
C		 440
441 /* here open is 4, wep/tkip is 8, aes is 12*/
442 if (info->control.hw_key)
443 additionlen += info->control.hw_key->icv_len;
444
445 /* The most skb num is 6 */
446 tcb_desc->empkt_num = 0;
447 spin_lock_bh(&rtlpriv->locks.waitq_lock);
448 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
449 struct ieee80211_tx_info *next_info;
450
451 next_info = IEEE80211_SKB_CB(next_skb);
452 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
453 tcb_desc->empkt_len[tcb_desc->empkt_num] =
454 next_skb->len + additionlen;
455 tcb_desc->empkt_num++;
456 } else {
457 break;
458 }
459
460 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
461 next_skb))
462 break;
463
26634c4b 464 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
c7cfe38e
C		 465 break;
466 }
467 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
468
469 return true;
470}
471
472/* just for early mode now */
473static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
474{
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
478 struct sk_buff *skb = NULL;
479 struct ieee80211_tx_info *info = NULL;
26634c4b 480 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
fb914ebf 481 int tid;
c7cfe38e
C		 482
483 if (!rtlpriv->rtlhal.earlymode_enable)
484 return;
485
26634c4b
LF		 486 if (rtlpriv->dm.supp_phymode_switch &&
487 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
488 (rtlpriv->buddy_priv &&
489 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
490 return;
ae0122b6 491 /* we just use em for BE/BK/VI/VO */
c7cfe38e 492 for (tid = 7; tid >= 0; tid--) {
2a00def4 493 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
c7cfe38e 494 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
ae0122b6 495
c7cfe38e
C		 496 while (!mac->act_scanning &&
497 rtlpriv->psc.rfpwr_state == ERFON) {
498 struct rtl_tcb_desc tcb_desc;
ae0122b6 499
c7cfe38e
C		 500 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
501
38bb0bae 502 spin_lock(&rtlpriv->locks.waitq_lock);
c7cfe38e 503 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
26634c4b
LF		 504 (ring->entries - skb_queue_len(&ring->queue) >
505 rtlhal->max_earlymode_num)) {
c7cfe38e
C		 506 skb = skb_dequeue(&mac->skb_waitq[tid]);
507 } else {
38bb0bae 508 spin_unlock(&rtlpriv->locks.waitq_lock);
c7cfe38e
C		 509 break;
510 }
38bb0bae 511 spin_unlock(&rtlpriv->locks.waitq_lock);
c7cfe38e
C		 512
513 /* Some macaddr can't do early mode. like
ae0122b6
LF		 514 * multicast/broadcast/no_qos data
515 */
c7cfe38e
C		 516 info = IEEE80211_SKB_CB(skb);
517 if (info->flags & IEEE80211_TX_CTL_AMPDU)
518 _rtl_update_earlymode_info(hw, skb,
519 &tcb_desc, tid);
520
36323f81 521 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
c7cfe38e
C		 522 }
523 }
524}
525
0c817338
LF		 526static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
527{
528 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
530
531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
532
533 while (skb_queue_len(&ring->queue)) {
0c817338
LF		 534 struct sk_buff *skb;
535 struct ieee80211_tx_info *info;
c7cfe38e
C		 536 __le16 fc;
537 u8 tid;
38506ece 538 u8 *entry;
0c817338 539
38506ece
LF		 540 if (rtlpriv->use_new_trx_flow)
541 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
542 else
543 entry = (u8 *)(&ring->desc[ring->idx]);
0c817338 544
38506ece 545 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
0c817338
LF		 546 return;
547 ring->idx = (ring->idx + 1) % ring->entries;
548
549 skb = __skb_dequeue(&ring->queue);
0dc0b5c2
CJ		 550 dma_unmap_single(&rtlpci->pdev->dev,
551 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
552 true, HW_DESC_TXBUFF_ADDR),
553 skb->len, DMA_TO_DEVICE);
0c817338 554
c7cfe38e
C		 555 /* remove early mode header */
556 if (rtlpriv->rtlhal.earlymode_enable)
557 skb_pull(skb, EM_HDR_LEN);
558
f108a420
LF		 559 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
560 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
561 ring->idx,
562 skb_queue_len(&ring->queue),
563 *(u16 *)(skb->data + 22));
0c817338 564
c7cfe38e
C		 565 if (prio == TXCMD_QUEUE) {
566 dev_kfree_skb(skb);
567 goto tx_status_ok;
c7cfe38e
C		 568 }
569
570 /* for sw LPS, just after NULL skb send out, we can
26634c4b
LF		 571 * sure AP knows we are sleeping, we should not let
572 * rf sleep
573 */
c7cfe38e
C		 574 fc = rtl_get_fc(skb);
575 if (ieee80211_is_nullfunc(fc)) {
576 if (ieee80211_has_pm(fc)) {
9c050440 577 rtlpriv->mac80211.offchan_delay = true;
3db1cd5c 578 rtlpriv->psc.state_inap = true;
c7cfe38e 579 } else {
3db1cd5c 580 rtlpriv->psc.state_inap = false;
c7cfe38e
C		 581 }
582 }
26634c4b
LF		 583 if (ieee80211_is_action(fc)) {
584 struct ieee80211_mgmt *action_frame =
585 (struct ieee80211_mgmt *)skb->data;
586 if (action_frame->u.action.u.ht_smps.action ==
587 WLAN_HT_ACTION_SMPS) {
588 dev_kfree_skb(skb);
589 goto tx_status_ok;
590 }
591 }
c7cfe38e
C		 592
593 /* update tid tx pkt num */
594 tid = rtl_get_tid(skb);
595 if (tid <= 7)
596 rtlpriv->link_info.tidtx_inperiod[tid]++;
597
0c817338 598 info = IEEE80211_SKB_CB(skb);
0c817338 599
6acfbb81
TEH		 600 if (likely(!ieee80211_is_nullfunc(fc))) {
601 ieee80211_tx_info_clear_status(info);
602 info->flags |= IEEE80211_TX_STAT_ACK;
603 /*info->status.rates[0].count = 1; */
604 ieee80211_tx_status_irqsafe(hw, skb);
605 } else {
606 rtl_tx_ackqueue(hw, skb);
607 }
0c817338 608
d0311314 609 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
f108a420
LF		 610 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
611 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
612 prio, ring->idx,
613 skb_queue_len(&ring->queue));
0c817338 614
ae0122b6 615 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
0c817338 616 }
c7cfe38e 617tx_status_ok:
0c817338
LF		 618 skb = NULL;
619 }
620
621 if (((rtlpriv->link_info.num_rx_inperiod +
ba9f93f8 622 rtlpriv->link_info.num_tx_inperiod) > 8) ||
ae0122b6 623 rtlpriv->link_info.num_rx_inperiod > 2)
920872e0 624 rtl_lps_leave(hw, false);
0c817338
LF		 625}
626
38506ece 627static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
e9538cf4
LF		 628 struct sk_buff *new_skb, u8 *entry,
629 int rxring_idx, int desc_idx)
fd854772
MM		 630{
631 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece
LF		 632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
633 u32 bufferaddress;
634 u8 tmp_one = 1;
635 struct sk_buff *skb;
636
e9538cf4
LF		 637 if (likely(new_skb)) {
638 skb = new_skb;
639 goto remap;
640 }
38506ece
LF		 641 skb = dev_alloc_skb(rtlpci->rxbuffersize);
642 if (!skb)
643 return 0;
38506ece 644
e9538cf4 645remap:
38506ece
LF		 646 /* just set skb->cb to mapping addr for pci_unmap_single use */
647 *((dma_addr_t *)skb->cb) =
0dc0b5c2
CJ		 648 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
649 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
38506ece 650 bufferaddress = *((dma_addr_t *)skb->cb);
0dc0b5c2 651 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
38506ece 652 return 0;
e9538cf4 653 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
38506ece 654 if (rtlpriv->use_new_trx_flow) {
0c07bd74 655 /* skb->cb may be 64 bit address */
38506ece
LF		 656 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
657 HW_DESC_RX_PREPARE,
0c07bd74 658 (u8 *)(dma_addr_t *)skb->cb);
fd854772 659 } else {
38506ece
LF		 660 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
661 HW_DESC_RXBUFF_ADDR,
662 (u8 *)&bufferaddress);
663 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
664 HW_DESC_RXPKT_LEN,
665 (u8 *)&rtlpci->rxbuffersize);
666 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
667 HW_DESC_RXOWN,
668 (u8 *)&tmp_one);
fd854772 669 }
38506ece
LF		 670 return 1;
671}
fd854772 672
38506ece
LF		 673/* inorder to receive 8K AMSDU we have set skb to
674 * 9100bytes in init rx ring, but if this packet is
675 * not a AMSDU, this large packet will be sent to
676 * TCP/IP directly, this cause big packet ping fail
677 * like: "ping -s 65507", so here we will realloc skb
678 * based on the true size of packet, Mac80211
679 * Probably will do it better, but does not yet.
680 *
681 * Some platform will fail when alloc skb sometimes.
682 * in this condition, we will send the old skb to
683 * mac80211 directly, this will not cause any other
684 * issues, but only this packet will be lost by TCP/IP
685 */
686static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
687 struct sk_buff *skb,
688 struct ieee80211_rx_status rx_status)
689{
690 if (unlikely(!rtl_action_proc(hw, skb, false))) {
691 dev_kfree_skb_any(skb);
692 } else {
693 struct sk_buff *uskb = NULL;
38506ece
LF		 694
695 uskb = dev_alloc_skb(skb->len + 128);
696 if (likely(uskb)) {
697 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
698 sizeof(rx_status));
b952f4df 699 skb_put_data(uskb, skb->data, skb->len);
38506ece
LF		 700 dev_kfree_skb_any(skb);
701 ieee80211_rx_irqsafe(hw, uskb);
702 } else {
703 ieee80211_rx_irqsafe(hw, skb);
704 }
fd854772 705 }
38506ece 706}
fd854772 707
38506ece
LF		 708/*hsisr interrupt handler*/
709static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
710{
711 struct rtl_priv *rtlpriv = rtl_priv(hw);
712 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
fd854772 713
38506ece
LF		 714 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
715 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
716 rtlpci->sys_irq_mask);
fd854772
MM		 717}
718
0c817338
LF		 719static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
720{
721 struct rtl_priv *rtlpriv = rtl_priv(hw);
722 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece 723 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
0c817338
LF		 724 struct ieee80211_rx_status rx_status = { 0 };
725 unsigned int count = rtlpci->rxringcount;
726 u8 own;
727 u8 tmp_one;
38506ece
LF		 728 bool unicast = false;
729 u8 hw_queue = 0;
fb9829e9 730 unsigned int rx_remained_cnt = 0;
0c817338
LF		 731 struct rtl_stats stats = {
732 .signal = 0,
0c817338
LF		 733 .rate = 0,
734 };
735
736 /*RX NORMAL PKT */
737 while (count--) {
38506ece
LF		 738 struct ieee80211_hdr *hdr;
739 __le16 fc;
740 u16 len;
741 /*rx buffer descriptor */
742 struct rtl_rx_buffer_desc *buffer_desc = NULL;
743 /*if use new trx flow, it means wifi info */
744 struct rtl_rx_desc *pdesc = NULL;
0c817338 745 /*rx pkt */
38506ece
LF		 746 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
747 rtlpci->rx_ring[rxring_idx].idx];
e9538cf4 748 struct sk_buff *new_skb;
38506ece
LF		 749
750 if (rtlpriv->use_new_trx_flow) {
fb9829e9
PKS		 751 if (rx_remained_cnt == 0)
752 rx_remained_cnt =
38506ece
LF		 753 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
754 hw_queue);
d0311314 755 if (rx_remained_cnt == 0)
38506ece 756 return;
f99551a2
LF		 757 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
758 rtlpci->rx_ring[rxring_idx].idx];
759 pdesc = (struct rtl_rx_desc *)skb->data;
38506ece
LF		 760 } else { /* rx descriptor */
761 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
762 rtlpci->rx_ring[rxring_idx].idx];
763
0c07bd74 764 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
38506ece
LF		 765 false,
766 HW_DESC_OWN);
767 if (own) /* wait data to be filled by hardware */
768 return;
769 }
6633d649 770
38506ece
LF		 771 /* Reaching this point means: data is filled already
772 * AAAAAAttention !!!
773 * We can NOT access 'skb' before 'pci_unmap_single'
774 */
0dc0b5c2
CJ		 775 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
776 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
38506ece 777
e9538cf4
LF		 778 /* get a new skb - if fail, old one will be reused */
779 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
aeb2d2a4 780 if (unlikely(!new_skb))
e9538cf4 781 goto no_new;
ae0122b6 782 memset(&rx_status, 0, sizeof(rx_status));
2c333366 783 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
38506ece 784 &rx_status, (u8 *)pdesc, skb);
2c333366 785
38506ece
LF		 786 if (rtlpriv->use_new_trx_flow)
787 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
788 (u8 *)buffer_desc,
789 hw_queue);
8db8ddf1 790
0c07bd74 791 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
38506ece 792 HW_DESC_RXPKT_LEN);
2c333366 793
38506ece
LF		 794 if (skb->end - skb->tail > len) {
795 skb_put(skb, len);
796 if (rtlpriv->use_new_trx_flow)
797 skb_reserve(skb, stats.rx_drvinfo_size +
798 stats.rx_bufshift + 24);
799 else
800 skb_reserve(skb, stats.rx_drvinfo_size +
801 stats.rx_bufshift);
38506ece 802 } else {
f108a420
LF		 803 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
804 "skb->end - skb->tail = %d, len is %d\n",
805 skb->end - skb->tail, len);
d0311314
TT		 806 dev_kfree_skb_any(skb);
807 goto new_trx_end;
38506ece
LF		 808 }
809 /* handle command packet here */
23ffab17 810 if (stats.packet_report_type == C2H_PACKET) {
9ae6ed27 811 rtl_c2hcmd_enqueue(hw, skb);
ae0122b6 812 goto new_trx_end;
38506ece 813 }
2c333366 814
ae0122b6 815 /* NOTICE This can not be use for mac80211,
2c333366 816 * this is done in mac80211 code,
38506ece 817 * if done here sec DHCP will fail
2c333366
MM		 818 * skb_trim(skb, skb->len - 4);
819 */
820
38506ece
LF		 821 hdr = rtl_get_hdr(skb);
822 fc = rtl_get_fc(skb);
823
b43f4a16 824 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
38506ece
LF		 825 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
826 sizeof(rx_status));
827
828 if (is_broadcast_ether_addr(hdr->addr1)) {
829 ;/*TODO*/
830 } else if (is_multicast_ether_addr(hdr->addr1)) {
831 ;/*TODO*/
832 } else {
833 unicast = true;
834 rtlpriv->stats.rxbytesunicast += skb->len;
835 }
cad737df 836 rtl_is_special_data(hw, skb, false, true);
0c817338 837
38506ece
LF		 838 if (ieee80211_is_data(fc)) {
839 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
840 if (unicast)
841 rtlpriv->link_info.num_rx_inperiod++;
842 }
c76ab8e7
PKS		 843
844 rtl_collect_scan_list(hw, skb);
845
38506ece
LF		 846 /* static bcn for roaming */
847 rtl_beacon_statistic(hw, skb);
848 rtl_p2p_info(hw, (void *)skb->data, skb->len);
849 /* for sw lps */
850 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
851 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
ae0122b6
LF		 852 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
853 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
38506ece
LF		 854 (ieee80211_is_beacon(fc) ||
855 ieee80211_is_probe_resp(fc))) {
856 dev_kfree_skb_any(skb);
857 } else {
858 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
859 }
860 } else {
b43f4a16 861 /* drop packets with errors or those too short */
38506ece
LF		 862 dev_kfree_skb_any(skb);
863 }
d0311314 864new_trx_end:
38506ece
LF		 865 if (rtlpriv->use_new_trx_flow) {
866 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
867 rtlpci->rx_ring[hw_queue].next_rx_rp %=
868 RTL_PCI_MAX_RX_COUNT;
869
870 rx_remained_cnt--;
871 rtl_write_word(rtlpriv, 0x3B4,
872 rtlpci->rx_ring[hw_queue].next_rx_rp);
873 }
2c333366 874 if (((rtlpriv->link_info.num_rx_inperiod +
a269913c 875 rtlpriv->link_info.num_tx_inperiod) > 8) ||
ae0122b6 876 rtlpriv->link_info.num_rx_inperiod > 2)
920872e0 877 rtl_lps_leave(hw, false);
e9538cf4
LF		 878 skb = new_skb;
879no_new:
38506ece 880 if (rtlpriv->use_new_trx_flow) {
e9538cf4 881 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
38506ece 882 rxring_idx,
e9538cf4 883 rtlpci->rx_ring[rxring_idx].idx);
38506ece 884 } else {
e9538cf4
LF		 885 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
886 rxring_idx,
38506ece 887 rtlpci->rx_ring[rxring_idx].idx);
38506ece
LF		 888 if (rtlpci->rx_ring[rxring_idx].idx ==
889 rtlpci->rxringcount - 1)
890 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
891 false,
892 HW_DESC_RXERO,
893 (u8 *)&tmp_one);
894 }
895 rtlpci->rx_ring[rxring_idx].idx =
896 (rtlpci->rx_ring[rxring_idx].idx + 1) %
897 rtlpci->rxringcount;
0c817338 898 }
0c817338
LF		 899}
900
0c817338
LF		 901static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
902{
903 struct ieee80211_hw *hw = dev_id;
38506ece 904 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338 905 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 906 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 907 unsigned long flags;
78aa6012
LF		 908 struct rtl_int intvec = {0};
909
de2e56ce 910 irqreturn_t ret = IRQ_HANDLED;
0c817338 911
38506ece
LF		 912 if (rtlpci->irq_enabled == 0)
913 return ret;
914
ae0122b6 915 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
38506ece 916 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 917
918 /*read ISR: 4/8bytes */
78aa6012 919 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
0c817338 920
ae0122b6 921 /*Shared IRQ or HW disappeared */
78aa6012 922 if (!intvec.inta || intvec.inta == 0xffff)
0c817338
LF		 923 goto done;
924
925 /*<1> beacon related */
78aa6012 926 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
f108a420
LF		 927 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
928 "beacon ok interrupt!\n");
0c817338 929
78aa6012 930 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
f108a420
LF		 931 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
932 "beacon err interrupt!\n");
0c817338 933
78aa6012 934 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
f108a420 935 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0c817338 936
78aa6012 937 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
f108a420
LF		 938 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
939 "prepare beacon for interrupt!\n");
0c817338
LF		 940 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
941 }
942
38506ece 943 /*<2> Tx related */
78aa6012 944 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
f108a420 945 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0c817338 946
78aa6012 947 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
f108a420
LF		 948 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
949 "Manage ok interrupt!\n");
0c817338
LF		 950 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
951 }
952
78aa6012 953 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
f108a420
LF		 954 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
955 "HIGH_QUEUE ok interrupt!\n");
0c817338
LF		 956 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
957 }
958
78aa6012 959 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
0c817338
LF		 960 rtlpriv->link_info.num_tx_inperiod++;
961
f108a420
LF		 962 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
963 "BK Tx OK interrupt!\n");
0c817338
LF		 964 _rtl_pci_tx_isr(hw, BK_QUEUE);
965 }
966
78aa6012 967 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
0c817338
LF		 968 rtlpriv->link_info.num_tx_inperiod++;
969
f108a420
LF		 970 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
971 "BE TX OK interrupt!\n");
0c817338
LF		 972 _rtl_pci_tx_isr(hw, BE_QUEUE);
973 }
974
78aa6012 975 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
0c817338
LF		 976 rtlpriv->link_info.num_tx_inperiod++;
977
f108a420
LF		 978 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
979 "VI TX OK interrupt!\n");
0c817338
LF		 980 _rtl_pci_tx_isr(hw, VI_QUEUE);
981 }
982
78aa6012 983 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
0c817338
LF		 984 rtlpriv->link_info.num_tx_inperiod++;
985
f108a420
LF		 986 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
987 "Vo TX OK interrupt!\n");
0c817338
LF		 988 _rtl_pci_tx_isr(hw, VO_QUEUE);
989 }
990
89d3e8ab 991 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
78aa6012 992 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
89d3e8ab
PKS		 993 rtlpriv->link_info.num_tx_inperiod++;
994
f108a420
LF		 995 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
996 "H2C TX OK interrupt!\n");
89d3e8ab
PKS		 997 _rtl_pci_tx_isr(hw, H2C_QUEUE);
998 }
999 }
1000
c7cfe38e 1001 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
78aa6012 1002 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
c7cfe38e
C		 1003 rtlpriv->link_info.num_tx_inperiod++;
1004
f108a420
LF		 1005 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1006 "CMD TX OK interrupt!\n");
c7cfe38e
C		 1007 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1008 }
1009 }
1010
38506ece 1011 /*<3> Rx related */
78aa6012 1012 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
f108a420 1013 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
c7cfe38e 1014 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1015 }
1016
78aa6012 1017 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
f108a420
LF		 1018 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1019 "rx descriptor unavailable!\n");
c7cfe38e 1020 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1021 }
1022
78aa6012 1023 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
f108a420 1024 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
c7cfe38e 1025 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1026 }
1027
38506ece 1028 /*<4> fw related*/
26634c4b 1029 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
78aa6012 1030 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
f108a420
LF		 1031 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1032 "firmware interrupt!\n");
26634c4b
LF		 1033 queue_delayed_work(rtlpriv->works.rtl_wq,
1034 &rtlpriv->works.fwevt_wq, 0);
1035 }
1036 }
1037
38506ece
LF		 1038 /*<5> hsisr related*/
1039 /* Only 8188EE & 8723BE Supported.
1040 * If Other ICs Come in, System will corrupt,
1041 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1042 * are not initialized
1043 */
1044 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1045 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
78aa6012
LF		 1046 if (unlikely(intvec.inta &
1047 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
f108a420
LF		 1048 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
1049 "hsisr interrupt!\n");
38506ece
LF		 1050 _rtl_pci_hs_interrupt(hw);
1051 }
1052 }
1053
c7cfe38e
C		 1054 if (rtlpriv->rtlhal.earlymode_enable)
1055 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1056
0c817338 1057done:
38506ece 1058 rtlpriv->cfg->ops->enable_interrupt(hw);
0c817338 1059 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 1060 return ret;
0c817338
LF		 1061}
1062
d3ccc14d 1063static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
0c817338 1064{
d3ccc14d
AP		 1065 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
1066 struct ieee80211_hw *hw = rtlpriv->hw;
c7cfe38e 1067 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 1068}
1069
d3ccc14d 1070static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
0c817338 1071{
d3ccc14d
AP		 1072 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1073 works.irq_prepare_bcn_tasklet);
1074 struct ieee80211_hw *hw = rtlpriv->hw;
0c817338
LF		 1075 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1076 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 1077 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 1078 struct ieee80211_hdr *hdr = NULL;
1079 struct ieee80211_tx_info *info = NULL;
1080 struct sk_buff *pskb = NULL;
1081 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 1082 struct rtl_tcb_desc tcb_desc;
f3355dd9
LF		 1083 /*This is for new trx flow*/
1084 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
0c817338 1085 u8 temp_one = 1;
be0b5e63 1086 u8 *entry;
0c817338 1087
c7cfe38e 1088 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 1089 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1090 pskb = __skb_dequeue(&ring->queue);
be0b5e63
LF		 1091 if (rtlpriv->use_new_trx_flow)
1092 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1093 else
1094 entry = (u8 *)(&ring->desc[ring->idx]);
1095 if (pskb) {
0dc0b5c2
CJ		 1096 dma_unmap_single(&rtlpci->pdev->dev,
1097 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1098 true, HW_DESC_TXBUFF_ADDR),
1099 pskb->len, DMA_TO_DEVICE);
0c817338 1100 kfree_skb(pskb);
be0b5e63 1101 }
0c817338
LF		 1102
1103 /*NB: the beacon data buffer must be 32-bit aligned. */
1104 pskb = ieee80211_beacon_get(hw, mac->vif);
ae0122b6 1105 if (!pskb)
0c817338 1106 return;
c7cfe38e 1107 hdr = rtl_get_hdr(pskb);
0c817338 1108 info = IEEE80211_SKB_CB(pskb);
0c817338 1109 pdesc = &ring->desc[0];
38506ece
LF		 1110 if (rtlpriv->use_new_trx_flow)
1111 pbuffer_desc = &ring->buffer_desc[0];
1112
1113 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
f3355dd9
LF		 1114 (u8 *)pbuffer_desc, info, NULL, pskb,
1115 BEACON_QUEUE, &tcb_desc);
0c817338
LF		 1116
1117 __skb_queue_tail(&ring->queue, pskb);
1118
fb6eaf2c
LF		 1119 if (rtlpriv->use_new_trx_flow) {
1120 temp_one = 4;
1121 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1122 HW_DESC_OWN, (u8 *)&temp_one);
1123 } else {
1124 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1125 &temp_one);
1126 }
0c817338
LF		 1127}
1128
1129static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1130{
1131 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece
LF		 1132 struct rtl_priv *rtlpriv = rtl_priv(hw);
1133 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
0c817338 1134 u8 i;
38506ece
LF		 1135 u16 desc_num;
1136
1137 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1138 desc_num = TX_DESC_NUM_92E;
57869e4b
PKS		 1139 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1140 desc_num = TX_DESC_NUM_8822B;
38506ece
LF		 1141 else
1142 desc_num = RT_TXDESC_NUM;
0c817338
LF		 1143
1144 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
38506ece 1145 rtlpci->txringcount[i] = desc_num;
0c817338 1146
ae0122b6 1147 /*we just alloc 2 desc for beacon queue,
0c817338
LF		 1148 *because we just need first desc in hw beacon.
1149 */
1150 rtlpci->txringcount[BEACON_QUEUE] = 2;
1151
38506ece 1152 /*BE queue need more descriptor for performance
0c817338
LF		 1153 *consideration or, No more tx desc will happen,
1154 *and may cause mac80211 mem leakage.
1155 */
38506ece
LF		 1156 if (!rtl_priv(hw)->use_new_trx_flow)
1157 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
0c817338
LF		 1158
1159 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1160 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1161}
1162
1163static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
ae0122b6 1164 struct pci_dev *pdev)
0c817338
LF		 1165{
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1169 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1170
1171 rtlpci->up_first_time = true;
1172 rtlpci->being_init_adapter = false;
1173
1174 rtlhal->hw = hw;
1175 rtlpci->pdev = pdev;
1176
0c817338
LF		 1177 /*Tx/Rx related var */
1178 _rtl_pci_init_trx_var(hw);
1179
37c52934
LF		 1180 /*IBSS*/
1181 mac->beacon_interval = 100;
0c817338 1182
c7cfe38e
C		 1183 /*AMPDU*/
1184 mac->min_space_cfg = 0;
0c817338
LF		 1185 mac->max_mss_density = 0;
1186 /*set sane AMPDU defaults */
1187 mac->current_ampdu_density = 7;
1188 mac->current_ampdu_factor = 3;
1189
8d0d43e3
PKS		 1190 /*Retry Limit*/
1191 mac->retry_short = 7;
1192 mac->retry_long = 7;
1193
c7cfe38e 1194 /*QOS*/
2cddad3c 1195 rtlpci->acm_method = EACMWAY2_SW;
0c817338
LF		 1196
1197 /*task */
d3ccc14d
AP		 1198 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1199 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1200 _rtl_pci_prepare_bcn_tasklet);
a269913c
LF		 1201 INIT_WORK(&rtlpriv->works.lps_change_work,
1202 rtl_lps_change_work_callback);
0c817338
LF		 1203}
1204
1205static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1206 unsigned int prio, unsigned int entries)
1207{
1208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece
LF		 1210 struct rtl_tx_buffer_desc *buffer_desc;
1211 struct rtl_tx_desc *desc;
1212 dma_addr_t buffer_desc_dma, desc_dma;
0c817338
LF		 1213 u32 nextdescaddress;
1214 int i;
1215
38506ece
LF		 1216 /* alloc tx buffer desc for new trx flow*/
1217 if (rtlpriv->use_new_trx_flow) {
1218 buffer_desc =
0dc0b5c2
CJ		 1219 dma_alloc_coherent(&rtlpci->pdev->dev,
1220 sizeof(*buffer_desc) * entries,
1221 &buffer_desc_dma, GFP_KERNEL);
38506ece
LF		 1222
1223 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
b03d968b
LF		 1224 pr_err("Cannot allocate TX ring (prio = %d)\n",
1225 prio);
38506ece
LF		 1226 return -ENOMEM;
1227 }
1228
1229 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1230 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1231
1232 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1233 rtlpci->tx_ring[prio].cur_tx_wp = 0;
38506ece
LF		 1234 }
1235
1236 /* alloc dma for this ring */
0dc0b5c2
CJ		 1237 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1238 &desc_dma, GFP_KERNEL);
38506ece
LF		 1239
1240 if (!desc || (unsigned long)desc & 0xFF) {
b03d968b 1241 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
0c817338
LF		 1242 return -ENOMEM;
1243 }
1244
38506ece
LF		 1245 rtlpci->tx_ring[prio].desc = desc;
1246 rtlpci->tx_ring[prio].dma = desc_dma;
1247
0c817338
LF		 1248 rtlpci->tx_ring[prio].idx = 0;
1249 rtlpci->tx_ring[prio].entries = entries;
1250 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1251
f108a420
LF		 1252 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1253 prio, desc);
38506ece
LF		 1254
1255 /* init every desc in this ring */
1256 if (!rtlpriv->use_new_trx_flow) {
1257 for (i = 0; i < entries; i++) {
1258 nextdescaddress = (u32)desc_dma +
1259 ((i + 1) % entries) *
1260 sizeof(*desc);
1261
1262 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1263 true,
1264 HW_DESC_TX_NEXTDESC_ADDR,
1265 (u8 *)&nextdescaddress);
1266 }
0c817338 1267 }
0c817338
LF		 1268 return 0;
1269}
1270
38506ece 1271static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
0c817338
LF		 1272{
1273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1274 struct rtl_priv *rtlpriv = rtl_priv(hw);
38506ece 1275 int i;
0c817338 1276
38506ece
LF		 1277 if (rtlpriv->use_new_trx_flow) {
1278 struct rtl_rx_buffer_desc *entry = NULL;
1279 /* alloc dma for this ring */
1280 rtlpci->rx_ring[rxring_idx].buffer_desc =
0dc0b5c2
CJ		 1281 dma_alloc_coherent(&rtlpci->pdev->dev,
1282 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1283 rtlpci->rxringcount,
1284 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
38506ece
LF		 1285 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1286 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
b03d968b 1287 pr_err("Cannot allocate RX ring\n");
0c817338
LF		 1288 return -ENOMEM;
1289 }
1290
38506ece
LF		 1291 /* init every desc in this ring */
1292 rtlpci->rx_ring[rxring_idx].idx = 0;
1293 for (i = 0; i < rtlpci->rxringcount; i++) {
1294 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
e9538cf4 1295 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
38506ece
LF		 1296 rxring_idx, i))
1297 return -ENOMEM;
1298 }
1299 } else {
1300 struct rtl_rx_desc *entry = NULL;
1301 u8 tmp_one = 1;
1302 /* alloc dma for this ring */
1303 rtlpci->rx_ring[rxring_idx].desc =
0dc0b5c2
CJ		 1304 dma_alloc_coherent(&rtlpci->pdev->dev,
1305 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1306 rtlpci->rxringcount,
1307 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
38506ece
LF		 1308 if (!rtlpci->rx_ring[rxring_idx].desc ||
1309 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
b03d968b 1310 pr_err("Cannot allocate RX ring\n");
38506ece
LF		 1311 return -ENOMEM;
1312 }
0c817338 1313
38506ece
LF		 1314 /* init every desc in this ring */
1315 rtlpci->rx_ring[rxring_idx].idx = 0;
0019a2c9 1316
0c817338 1317 for (i = 0; i < rtlpci->rxringcount; i++) {
38506ece 1318 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
e9538cf4 1319 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
38506ece
LF		 1320 rxring_idx, i))
1321 return -ENOMEM;
0c817338
LF		 1322 }
1323
f3355dd9 1324 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
2c208890 1325 HW_DESC_RXERO, &tmp_one);
0c817338
LF		 1326 }
1327 return 0;
1328}
1329
1330static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
ae0122b6 1331 unsigned int prio)
0c817338
LF		 1332{
1333 struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1335 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1336
38506ece 1337 /* free every desc in this ring */
0c817338 1338 while (skb_queue_len(&ring->queue)) {
38506ece 1339 u8 *entry;
0c817338
LF		 1340 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1341
38506ece
LF		 1342 if (rtlpriv->use_new_trx_flow)
1343 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1344 else
1345 entry = (u8 *)(&ring->desc[ring->idx]);
1346
0dc0b5c2 1347 dma_unmap_single(&rtlpci->pdev->dev,
ae0122b6 1348 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
0dc0b5c2
CJ		 1349 true, HW_DESC_TXBUFF_ADDR),
1350 skb->len, DMA_TO_DEVICE);
0c817338
LF		 1351 kfree_skb(skb);
1352 ring->idx = (ring->idx + 1) % ring->entries;
1353 }
1354
38506ece 1355 /* free dma of this ring */
0dc0b5c2
CJ		 1356 dma_free_coherent(&rtlpci->pdev->dev,
1357 sizeof(*ring->desc) * ring->entries, ring->desc,
1358 ring->dma);
38506ece
LF		 1359 ring->desc = NULL;
1360 if (rtlpriv->use_new_trx_flow) {
0dc0b5c2
CJ		 1361 dma_free_coherent(&rtlpci->pdev->dev,
1362 sizeof(*ring->buffer_desc) * ring->entries,
1363 ring->buffer_desc, ring->buffer_desc_dma);
caea2172 1364 ring->buffer_desc = NULL;
7f66c2f9 1365 }
0c817338
LF		 1366}
1367
38506ece 1368static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
0c817338 1369{
38506ece
LF		 1370 struct rtl_priv *rtlpriv = rtl_priv(hw);
1371 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1372 int i;
0c817338 1373
38506ece
LF		 1374 /* free every desc in this ring */
1375 for (i = 0; i < rtlpci->rxringcount; i++) {
1376 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
0c817338 1377
38506ece
LF		 1378 if (!skb)
1379 continue;
0dc0b5c2
CJ		 1380 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1381 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
38506ece
LF		 1382 kfree_skb(skb);
1383 }
1384
1385 /* free dma of this ring */
1386 if (rtlpriv->use_new_trx_flow) {
0dc0b5c2
CJ		 1387 dma_free_coherent(&rtlpci->pdev->dev,
1388 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1389 rtlpci->rxringcount,
1390 rtlpci->rx_ring[rxring_idx].buffer_desc,
1391 rtlpci->rx_ring[rxring_idx].dma);
38506ece
LF		 1392 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1393 } else {
0dc0b5c2
CJ		 1394 dma_free_coherent(&rtlpci->pdev->dev,
1395 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1396 rtlpci->rxringcount,
1397 rtlpci->rx_ring[rxring_idx].desc,
1398 rtlpci->rx_ring[rxring_idx].dma);
38506ece 1399 rtlpci->rx_ring[rxring_idx].desc = NULL;
0c817338
LF		 1400 }
1401}
1402
1403static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1404{
1405 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1406 int ret;
38506ece 1407 int i, rxring_idx;
0c817338 1408
38506ece
LF		 1409 /* rxring_idx 0:RX_MPDU_QUEUE
1410 * rxring_idx 1:RX_CMD_QUEUE
1411 */
1412 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1413 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1414 if (ret)
1415 return ret;
1416 }
0c817338
LF		 1417
1418 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
ae0122b6 1419 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
0c817338
LF		 1420 if (ret)
1421 goto err_free_rings;
1422 }
1423
1424 return 0;
1425
1426err_free_rings:
38506ece
LF		 1427 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1428 _rtl_pci_free_rx_ring(hw, rxring_idx);
0c817338
LF		 1429
1430 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
38506ece
LF		 1431 if (rtlpci->tx_ring[i].desc ||
1432 rtlpci->tx_ring[i].buffer_desc)
0c817338
LF		 1433 _rtl_pci_free_tx_ring(hw, i);
1434
1435 return 1;
1436}
1437
1438static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1439{
38506ece 1440 u32 i, rxring_idx;
0c817338
LF		 1441
1442 /*free rx rings */
38506ece
LF		 1443 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1444 _rtl_pci_free_rx_ring(hw, rxring_idx);
0c817338
LF		 1445
1446 /*free tx rings */
1447 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1448 _rtl_pci_free_tx_ring(hw, i);
1449
1450 return 0;
1451}
1452
1453int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1454{
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
38506ece 1457 int i, rxring_idx;
0c817338
LF		 1458 unsigned long flags;
1459 u8 tmp_one = 1;
38506ece
LF		 1460 u32 bufferaddress;
1461 /* rxring_idx 0:RX_MPDU_QUEUE */
1462 /* rxring_idx 1:RX_CMD_QUEUE */
1463 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1464 /* force the rx_ring[RX_MPDU_QUEUE/
1465 * RX_CMD_QUEUE].idx to the first one
1466 *new trx flow, do nothing
ae0122b6 1467 */
38506ece
LF		 1468 if (!rtlpriv->use_new_trx_flow &&
1469 rtlpci->rx_ring[rxring_idx].desc) {
0c817338
LF		 1470 struct rtl_rx_desc *entry = NULL;
1471
38506ece 1472 rtlpci->rx_ring[rxring_idx].idx = 0;
0c817338 1473 for (i = 0; i < rtlpci->rxringcount; i++) {
38506ece
LF		 1474 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1475 bufferaddress =
0c07bd74 1476 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
ae0122b6
LF		 1477 false, HW_DESC_RXBUFF_ADDR);
1478 memset((u8 *)entry, 0,
38506ece
LF		 1479 sizeof(*rtlpci->rx_ring
1480 [rxring_idx].desc));/*clear one entry*/
1481 if (rtlpriv->use_new_trx_flow) {
1482 rtlpriv->cfg->ops->set_desc(hw,
1483 (u8 *)entry, false,
1484 HW_DESC_RX_PREPARE,
1485 (u8 *)&bufferaddress);
1486 } else {
1487 rtlpriv->cfg->ops->set_desc(hw,
1488 (u8 *)entry, false,
1489 HW_DESC_RXBUFF_ADDR,
1490 (u8 *)&bufferaddress);
1491 rtlpriv->cfg->ops->set_desc(hw,
1492 (u8 *)entry, false,
1493 HW_DESC_RXPKT_LEN,
1494 (u8 *)&rtlpci->rxbuffersize);
1495 rtlpriv->cfg->ops->set_desc(hw,
1496 (u8 *)entry, false,
1497 HW_DESC_RXOWN,
1498 (u8 *)&tmp_one);
1499 }
0c817338 1500 }
38506ece
LF		 1501 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1502 HW_DESC_RXERO, (u8 *)&tmp_one);
0c817338 1503 }
38506ece 1504 rtlpci->rx_ring[rxring_idx].idx = 0;
0c817338
LF		 1505 }
1506
ae0122b6 1507 /*after reset, release previous pending packet,
0c817338
LF		 1508 *and force the tx idx to the first one
1509 */
38506ece 1510 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1511 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
38506ece
LF		 1512 if (rtlpci->tx_ring[i].desc ||
1513 rtlpci->tx_ring[i].buffer_desc) {
0c817338
LF		 1514 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1515
1516 while (skb_queue_len(&ring->queue)) {
38506ece
LF		 1517 u8 *entry;
1518 struct sk_buff *skb =
1519 __skb_dequeue(&ring->queue);
1520 if (rtlpriv->use_new_trx_flow)
1521 entry = (u8 *)(&ring->buffer_desc
1522 [ring->idx]);
1523 else
1524 entry = (u8 *)(&ring->desc[ring->idx]);
0c817338 1525
0dc0b5c2
CJ		 1526 dma_unmap_single(&rtlpci->pdev->dev,
1527 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1528 true, HW_DESC_TXBUFF_ADDR),
1529 skb->len, DMA_TO_DEVICE);
cf968937 1530 dev_kfree_skb_irq(skb);
38506ece 1531 ring->idx = (ring->idx + 1) % ring->entries;
0c817338 1532 }
b7573a0a
TSL		 1533
1534 if (rtlpriv->use_new_trx_flow) {
1535 rtlpci->tx_ring[i].cur_tx_rp = 0;
1536 rtlpci->tx_ring[i].cur_tx_wp = 0;
1537 }
1538
0c817338 1539 ring->idx = 0;
b7573a0a 1540 ring->entries = rtlpci->txringcount[i];
0c817338
LF		 1541 }
1542 }
38506ece 1543 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1544
0c817338
LF		 1545 return 0;
1546}
1547
c7cfe38e 1548static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
36323f81 1549 struct ieee80211_sta *sta,
c7cfe38e 1550 struct sk_buff *skb)
0c817338 1551{
c7cfe38e 1552 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e
C		 1553 struct rtl_sta_info *sta_entry = NULL;
1554 u8 tid = rtl_get_tid(skb);
0f015453 1555 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 1556
1557 if (!sta)
1558 return false;
1559 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1560
1561 if (!rtlpriv->rtlhal.earlymode_enable)
1562 return false;
0f015453
LF		 1563 if (ieee80211_is_nullfunc(fc))
1564 return false;
1565 if (ieee80211_is_qos_nullfunc(fc))
1566 return false;
1567 if (ieee80211_is_pspoll(fc))
1568 return false;
c7cfe38e
C		 1569 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1570 return false;
1571 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1572 return false;
1573 if (tid > 7)
1574 return false;
1575
1576 /* maybe every tid should be checked */
1577 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1578 return false;
1579
1580 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1581 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1582 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1583
c7cfe38e 1584 return true;
0c817338
LF		 1585}
1586
36323f81
TH		 1587static int rtl_pci_tx(struct ieee80211_hw *hw,
1588 struct ieee80211_sta *sta,
1589 struct sk_buff *skb,
1590 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1591{
1592 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338
LF		 1593 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1594 struct rtl8192_tx_ring *ring;
1595 struct rtl_tx_desc *pdesc;
f3355dd9 1596 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
38506ece 1597 u16 idx;
c7cfe38e 1598 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1599 unsigned long flags;
c7cfe38e
C		 1600 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1601 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1602 u8 *pda_addr = hdr->addr1;
1603 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 1604 u8 own;
1605 u8 temp_one = 1;
1606
0f015453
LF		 1607 if (ieee80211_is_mgmt(fc))
1608 rtl_tx_mgmt_proc(hw, skb);
c7cfe38e
C		 1609
1610 if (rtlpriv->psc.sw_ps_enabled) {
1611 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
ae0122b6 1612 !ieee80211_has_pm(fc))
c7cfe38e
C		 1613 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1614 }
0c817338 1615
c7cfe38e 1616 rtl_action_proc(hw, skb, true);
0c817338
LF		 1617
1618 if (is_multicast_ether_addr(pda_addr))
1619 rtlpriv->stats.txbytesmulticast += skb->len;
1620 else if (is_broadcast_ether_addr(pda_addr))
1621 rtlpriv->stats.txbytesbroadcast += skb->len;
1622 else
1623 rtlpriv->stats.txbytesunicast += skb->len;
1624
1625 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338 1626 ring = &rtlpci->tx_ring[hw_queue];
38506ece
LF		 1627 if (hw_queue != BEACON_QUEUE) {
1628 if (rtlpriv->use_new_trx_flow)
1629 idx = ring->cur_tx_wp;
1630 else
1631 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1632 ring->entries;
1633 } else {
0c817338 1634 idx = 0;
38506ece 1635 }
0c817338
LF		 1636
1637 pdesc = &ring->desc[idx];
f3355dd9
LF		 1638 if (rtlpriv->use_new_trx_flow) {
1639 ptx_bd_desc = &ring->buffer_desc[idx];
1640 } else {
0c07bd74 1641 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
f3355dd9 1642 true, HW_DESC_OWN);
0c817338 1643
ae0122b6 1644 if (own == 1 && hw_queue != BEACON_QUEUE) {
f108a420
LF		 1645 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1646 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1647 hw_queue, ring->idx, idx,
1648 skb_queue_len(&ring->queue));
0c817338 1649
f3355dd9
LF		 1650 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1651 flags);
1652 return skb->len;
1653 }
0c817338
LF		 1654 }
1655
d0311314
TT		 1656 if (rtlpriv->cfg->ops->get_available_desc &&
1657 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
f108a420
LF		 1658 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1659 "get_available_desc fail\n");
ae0122b6
LF		 1660 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1661 return skb->len;
d0311314
TT		 1662 }
1663
0c817338
LF		 1664 if (ieee80211_is_data(fc))
1665 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1666
c7cfe38e 1667 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
f3355dd9 1668 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
0c817338
LF		 1669
1670 __skb_queue_tail(&ring->queue, skb);
1671
f3355dd9
LF		 1672 if (rtlpriv->use_new_trx_flow) {
1673 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
9cb76aa9 1674 HW_DESC_OWN, &hw_queue);
f3355dd9
LF		 1675 } else {
1676 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
9cb76aa9 1677 HW_DESC_OWN, &temp_one);
f3355dd9 1678 }
0c817338
LF		 1679
1680 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1681 hw_queue != BEACON_QUEUE) {
f108a420
LF		 1682 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1683 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
f30d7507
JP		 1684 hw_queue, ring->idx, idx,
1685 skb_queue_len(&ring->queue));
0c817338
LF		 1686
1687 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1688 }
1689
1690 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1691
1692 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1693
1694 return 0;
1695}
1696
38506ece 1697static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
c7cfe38e
C		 1698{
1699 struct rtl_priv *rtlpriv = rtl_priv(hw);
1700 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1701 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
26634c4b 1702 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e
C		 1703 u16 i = 0;
1704 int queue_id;
1705 struct rtl8192_tx_ring *ring;
1706
26634c4b
LF		 1707 if (mac->skip_scan)
1708 return;
1709
c7cfe38e
C		 1710 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1711 u32 queue_len;
38506ece
LF		 1712
1713 if (((queues >> queue_id) & 0x1) == 0) {
1714 queue_id--;
1715 continue;
1716 }
c7cfe38e
C		 1717 ring = &pcipriv->dev.tx_ring[queue_id];
1718 queue_len = skb_queue_len(&ring->queue);
1719 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
ae0122b6 1720 queue_id == TXCMD_QUEUE) {
c7cfe38e
C		 1721 queue_id--;
1722 continue;
1723 } else {
1724 msleep(20);
1725 i++;
1726 }
1727
1728 /* we just wait 1s for all queues */
1729 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
ae0122b6 1730 is_hal_stop(rtlhal) || i >= 200)
c7cfe38e
C		 1731 return;
1732 }
1733}
1734
d3bb1429 1735static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1736{
1737 struct rtl_priv *rtlpriv = rtl_priv(hw);
1738 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1739
1740 _rtl_pci_deinit_trx_ring(hw);
1741
1742 synchronize_irq(rtlpci->pdev->irq);
1743 tasklet_kill(&rtlpriv->works.irq_tasklet);
a269913c 1744 cancel_work_sync(&rtlpriv->works.lps_change_work);
0c817338
LF		 1745
1746 flush_workqueue(rtlpriv->works.rtl_wq);
1747 destroy_workqueue(rtlpriv->works.rtl_wq);
0c817338
LF		 1748}
1749
d3bb1429 1750static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338 1751{
0c817338
LF		 1752 int err;
1753
1754 _rtl_pci_init_struct(hw, pdev);
1755
1756 err = _rtl_pci_init_trx_ring(hw);
1757 if (err) {
b03d968b 1758 pr_err("tx ring initialization failed\n");
12325280 1759 return err;
0c817338
LF		 1760 }
1761
12325280 1762 return 0;
0c817338
LF		 1763}
1764
d3bb1429 1765static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1766{
1767 struct rtl_priv *rtlpriv = rtl_priv(hw);
1768 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1769 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1770 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
8d0d43e3 1771 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
9177c336 1772 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
0c817338
LF		 1773
1774 int err;
1775
1776 rtl_pci_reset_trx_ring(hw);
1777
1778 rtlpci->driver_is_goingto_unload = false;
08054200
LF		 1779 if (rtlpriv->cfg->ops->get_btc_status &&
1780 rtlpriv->cfg->ops->get_btc_status()) {
f1cb27ed 1781 rtlpriv->btcoexist.btc_info.ap_num = 36;
9177c336
PKS		 1782 btc_ops->btc_init_variables(rtlpriv);
1783 btc_ops->btc_init_hal_vars(rtlpriv);
1784 } else if (btc_ops) {
1785 btc_ops->btc_init_variables_wifi_only(rtlpriv);
38506ece 1786 }
9177c336 1787
0c817338
LF		 1788 err = rtlpriv->cfg->ops->hw_init(hw);
1789 if (err) {
f108a420
LF		 1790 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1791 "Failed to config hardware!\n");
8cc782cd
LF		 1792 kfree(rtlpriv->btcoexist.btc_context);
1793 kfree(rtlpriv->btcoexist.wifi_only_context);
0c817338
LF		 1794 return err;
1795 }
8d0d43e3
PKS		 1796 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1797 &rtlmac->retry_long);
0c817338
LF		 1798
1799 rtlpriv->cfg->ops->enable_interrupt(hw);
f108a420 1800 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
0c817338
LF		 1801
1802 rtl_init_rx_config(hw);
1803
fb914ebf 1804 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1805 set_hal_start(rtlhal);
1806
1807 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1808
1809 rtlpci->up_first_time = false;
1810
f108a420 1811 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
0c817338
LF		 1812 return 0;
1813}
1814
d3bb1429 1815static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1816{
1817 struct rtl_priv *rtlpriv = rtl_priv(hw);
1818 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1819 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1820 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1821 unsigned long flags;
ae0122b6 1822 u8 rf_timeout = 0;
0c817338 1823
38506ece 1824 if (rtlpriv->cfg->ops->get_btc_status())
40d9dd4f
PKS		 1825 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1826
1827 if (rtlpriv->btcoexist.btc_ops)
1828 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
38506ece 1829
ae0122b6 1830 /*should be before disable interrupt&adapter
0c817338
LF		 1831 *and will do it immediately.
1832 */
1833 set_hal_stop(rtlhal);
1834
9278db62 1835 rtlpci->driver_is_goingto_unload = true;
0c817338 1836 rtlpriv->cfg->ops->disable_interrupt(hw);
a269913c 1837 cancel_work_sync(&rtlpriv->works.lps_change_work);
0c817338
LF		 1838
1839 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1840 while (ppsc->rfchange_inprogress) {
1841 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
ae0122b6 1842 if (rf_timeout > 100) {
0c817338
LF		 1843 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1844 break;
1845 }
1846 mdelay(1);
ae0122b6 1847 rf_timeout++;
0c817338
LF		 1848 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1849 }
1850 ppsc->rfchange_inprogress = true;
1851 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1852
0c817338 1853 rtlpriv->cfg->ops->hw_disable(hw);
b0302aba
LF		 1854 /* some things are not needed if firmware not available */
1855 if (!rtlpriv->max_fw_size)
1856 return;
0c817338
LF		 1857 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1858
1859 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1860 ppsc->rfchange_inprogress = false;
1861 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1862
1863 rtl_pci_enable_aspm(hw);
1864}
1865
1866static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
ae0122b6 1867 struct ieee80211_hw *hw)
0c817338
LF		 1868{
1869 struct rtl_priv *rtlpriv = rtl_priv(hw);
1870 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1871 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1872 struct pci_dev *bridge_pdev = pdev->bus->self;
1873 u16 venderid;
1874 u16 deviceid;
c7cfe38e 1875 u8 revisionid;
0c817338
LF		 1876 u16 irqline;
1877 u8 tmp;
1878
fc7707a4 1879 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1880 venderid = pdev->vendor;
1881 deviceid = pdev->device;
c7cfe38e 1882 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1883 pci_read_config_word(pdev, 0x3C, &irqline);
1884
fa7ccfb1
LF		 1885 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1886 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1887 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1888 * the correct driver is r8192e_pci, thus this routine should
1889 * return false.
1890 */
1891 if (deviceid == RTL_PCI_8192SE_DID &&
1892 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1893 return false;
1894
0c817338
LF		 1895 if (deviceid == RTL_PCI_8192_DID ||
1896 deviceid == RTL_PCI_0044_DID ||
1897 deviceid == RTL_PCI_0047_DID ||
1898 deviceid == RTL_PCI_8192SE_DID ||
1899 deviceid == RTL_PCI_8174_DID ||
1900 deviceid == RTL_PCI_8173_DID ||
1901 deviceid == RTL_PCI_8172_DID ||
1902 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1903 switch (revisionid) {
0c817338 1904 case RTL_PCI_REVISION_ID_8192PCIE:
f108a420
LF		 1905 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1906 "8192 PCI-E is found - vid/did=%x/%x\n",
1907 venderid, deviceid);
0c817338 1908 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
0f015453 1909 return false;
0c817338 1910 case RTL_PCI_REVISION_ID_8192SE:
f108a420
LF		 1911 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1912 "8192SE is found - vid/did=%x/%x\n",
1913 venderid, deviceid);
0c817338
LF		 1914 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1915 break;
1916 default:
f108a420
LF		 1917 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1918 "Err: Unknown device - vid/did=%x/%x\n",
1919 venderid, deviceid);
0c817338
LF		 1920 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1921 break;
0c817338 1922 }
0f015453
LF		 1923 } else if (deviceid == RTL_PCI_8723AE_DID) {
1924 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
f108a420
LF		 1925 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1926 "8723AE PCI-E is found - vid/did=%x/%x\n",
1927 venderid, deviceid);
0c817338
LF		 1928 } else if (deviceid == RTL_PCI_8192CET_DID ||
1929 deviceid == RTL_PCI_8192CE_DID ||
1930 deviceid == RTL_PCI_8191CE_DID ||
1931 deviceid == RTL_PCI_8188CE_DID) {
1932 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
f108a420
LF		 1933 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1934 "8192C PCI-E is found - vid/did=%x/%x\n",
1935 venderid, deviceid);
c7cfe38e
C		 1936 } else if (deviceid == RTL_PCI_8192DE_DID ||
1937 deviceid == RTL_PCI_8192DE_DID2) {
1938 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
f108a420
LF		 1939 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1940 "8192D PCI-E is found - vid/did=%x/%x\n",
1941 venderid, deviceid);
5c69177d
LF		 1942 } else if (deviceid == RTL_PCI_8188EE_DID) {
1943 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
f108a420
LF		 1944 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1945 "Find adapter, Hardware type is 8188EE\n");
38506ece 1946 } else if (deviceid == RTL_PCI_8723BE_DID) {
ae0122b6 1947 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
f108a420
LF		 1948 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1949 "Find adapter, Hardware type is 8723BE\n");
38506ece 1950 } else if (deviceid == RTL_PCI_8192EE_DID) {
ae0122b6 1951 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
f108a420
LF		 1952 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1953 "Find adapter, Hardware type is 8192EE\n");
38506ece 1954 } else if (deviceid == RTL_PCI_8821AE_DID) {
ae0122b6 1955 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
f108a420
LF		 1956 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1957 "Find adapter, Hardware type is 8821AE\n");
38506ece 1958 } else if (deviceid == RTL_PCI_8812AE_DID) {
ae0122b6 1959 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
f108a420
LF		 1960 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1961 "Find adapter, Hardware type is 8812AE\n");
68929a83
PKS		 1962 } else if (deviceid == RTL_PCI_8822BE_DID) {
1963 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1964 rtlhal->bandset = BAND_ON_BOTH;
f108a420
LF		 1965 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1966 "Find adapter, Hardware type is 8822BE\n");
0c817338 1967 } else {
f108a420
LF		 1968 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1969 "Err: Unknown device - vid/did=%x/%x\n",
f30d7507 1970 venderid, deviceid);
0c817338
LF		 1971
1972 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1973 }
1974
c7cfe38e
C		 1975 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1976 if (revisionid == 0 || revisionid == 1) {
1977 if (revisionid == 0) {
f108a420
LF		 1978 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1979 "Find 92DE MAC0\n");
c7cfe38e
C		 1980 rtlhal->interfaceindex = 0;
1981 } else if (revisionid == 1) {
f108a420
LF		 1982 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1983 "Find 92DE MAC1\n");
c7cfe38e
C		 1984 rtlhal->interfaceindex = 1;
1985 }
1986 } else {
f108a420
LF		 1987 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1988 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
f30d7507 1989 venderid, deviceid, revisionid);
c7cfe38e
C		 1990 rtlhal->interfaceindex = 0;
1991 }
1992 }
38506ece 1993
57869e4b
PKS		 1994 switch (rtlhal->hw_type) {
1995 case HARDWARE_TYPE_RTL8192EE:
1996 case HARDWARE_TYPE_RTL8822BE:
1997 /* use new trx flow */
38506ece 1998 rtlpriv->use_new_trx_flow = true;
57869e4b
PKS		 1999 break;
2000
2001 default:
38506ece 2002 rtlpriv->use_new_trx_flow = false;
57869e4b
PKS		 2003 break;
2004 }
38506ece 2005
0c817338
LF		 2006 /*find bus info */
2007 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2008 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2009 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2010
38506ece
LF		 2011 /*find bridge info */
2012 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
26634c4b
LF		 2013 /* some ARM have no bridge_pdev and will crash here
2014 * so we should check if bridge_pdev is NULL
2015 */
b6b67df3
LF		 2016 if (bridge_pdev) {
2017 /*find bridge info if available */
2018 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2019 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2020 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2021 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
f108a420
LF		 2022 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2023 "Pci Bridge Vendor is found index: %d\n",
2024 tmp);
b6b67df3
LF		 2025 break;
2026 }
0c817338
LF		 2027 }
2028 }
2029
2030 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2031 PCI_BRIDGE_VENDOR_UNKNOWN) {
2032 pcipriv->ndis_adapter.pcibridge_busnum =
2033 bridge_pdev->bus->number;
2034 pcipriv->ndis_adapter.pcibridge_devnum =
2035 PCI_SLOT(bridge_pdev->devfn);
2036 pcipriv->ndis_adapter.pcibridge_funcnum =
2037 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 2038 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2039 pci_pcie_cap(bridge_pdev);
0c817338
LF		 2040 pcipriv->ndis_adapter.num4bytes =
2041 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2042
2043 rtl_pci_get_linkcontrol_field(hw);
2044
2045 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2046 PCI_BRIDGE_VENDOR_AMD) {
2047 pcipriv->ndis_adapter.amd_l1_patch =
2048 rtl_pci_get_amd_l1_patch(hw);
2049 }
2050 }
2051
f108a420
LF		 2052 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2053 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2054 pcipriv->ndis_adapter.busnumber,
2055 pcipriv->ndis_adapter.devnumber,
2056 pcipriv->ndis_adapter.funcnumber,
2057 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
0c817338 2058
f108a420
LF		 2059 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2060 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2061 pcipriv->ndis_adapter.pcibridge_busnum,
2062 pcipriv->ndis_adapter.pcibridge_devnum,
2063 pcipriv->ndis_adapter.pcibridge_funcnum,
2064 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2065 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2066 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2067 pcipriv->ndis_adapter.amd_l1_patch);
0c817338
LF		 2068
2069 rtl_pci_parse_configuration(pdev, hw);
26634c4b 2070 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
0c817338
LF		 2071
2072 return true;
2073}
2074
94010fa0
AL		 2075static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2076{
2077 struct rtl_priv *rtlpriv = rtl_priv(hw);
2078 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2079 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2080 int ret;
2081
2082 ret = pci_enable_msi(rtlpci->pdev);
2083 if (ret < 0)
2084 return ret;
2085
2086 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2087 IRQF_SHARED, KBUILD_MODNAME, hw);
2088 if (ret < 0) {
2089 pci_disable_msi(rtlpci->pdev);
2090 return ret;
2091 }
2092
2093 rtlpci->using_msi = true;
2094
f108a420
LF		 2095 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2096 "MSI Interrupt Mode!\n");
94010fa0
AL		 2097 return 0;
2098}
2099
2100static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2101{
2102 struct rtl_priv *rtlpriv = rtl_priv(hw);
2103 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2104 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2105 int ret;
2106
2107 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2108 IRQF_SHARED, KBUILD_MODNAME, hw);
2109 if (ret < 0)
2110 return ret;
2111
2112 rtlpci->using_msi = false;
f108a420
LF		 2113 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2114 "Pin-based Interrupt Mode!\n");
94010fa0
AL		 2115 return 0;
2116}
2117
2118static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2119{
2120 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2121 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2122 int ret;
2123
2124 if (rtlpci->msi_support) {
2125 ret = rtl_pci_intr_mode_msi(hw);
2126 if (ret < 0)
2127 ret = rtl_pci_intr_mode_legacy(hw);
2128 } else {
2129 ret = rtl_pci_intr_mode_legacy(hw);
2130 }
2131 return ret;
2132}
2133
0c07bd74
PKS		 2134static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2135{
2136 u8 value;
2137
2138 pci_read_config_byte(pdev, 0x719, &value);
2139
2140 /* 0x719 Bit5 is DMA64 bit fetch. */
2141 if (dma64)
2142 value |= BIT(5);
2143 else
2144 value &= ~BIT(5);
2145
2146 pci_write_config_byte(pdev, 0x719, value);
2147}
2148
9e2ff36b 2149int rtl_pci_probe(struct pci_dev *pdev,
ae0122b6 2150 const struct pci_device_id *id)
0c817338
LF		 2151{
2152 struct ieee80211_hw *hw = NULL;
2153
2154 struct rtl_priv *rtlpriv = NULL;
2155 struct rtl_pci_priv *pcipriv = NULL;
2156 struct rtl_pci *rtlpci;
2157 unsigned long pmem_start, pmem_len, pmem_flags;
2158 int err;
2159
2160 err = pci_enable_device(pdev);
2161 if (err) {
531940f9 2162 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
9d833ed7 2163 pci_name(pdev));
0c817338
LF		 2164 return err;
2165 }
2166
0c07bd74 2167 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
0dc0b5c2
CJ		 2168 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2169 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
0c07bd74
PKS		 2170 WARN_ONCE(true,
2171 "Unable to obtain 64bit DMA for consistent allocations\n");
2172 err = -ENOMEM;
2173 goto fail1;
2174 }
2175
2176 platform_enable_dma64(pdev, true);
0dc0b5c2
CJ		 2177 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2178 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
531940f9
LF		 2179 WARN_ONCE(true,
2180 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
3d86b930
TG		 2181 err = -ENOMEM;
2182 goto fail1;
0c817338 2183 }
0c07bd74
PKS		 2184
2185 platform_enable_dma64(pdev, false);
0c817338
LF		 2186 }
2187
2188 pci_set_master(pdev);
2189
2190 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2191 sizeof(struct rtl_priv), &rtl_ops);
2192 if (!hw) {
531940f9 2193 WARN_ONCE(true,
9d833ed7 2194 "%s : ieee80211 alloc failed\n", pci_name(pdev));
0c817338
LF		 2195 err = -ENOMEM;
2196 goto fail1;
2197 }
2198
2199 SET_IEEE80211_DEV(hw, &pdev->dev);
2200 pci_set_drvdata(pdev, hw);
2201
2202 rtlpriv = hw->priv;
26634c4b 2203 rtlpriv->hw = hw;
0c817338
LF		 2204 pcipriv = (void *)rtlpriv->priv;
2205 pcipriv->dev.pdev = pdev;
b0302aba 2206 init_completion(&rtlpriv->firmware_loading_complete);
38506ece
LF		 2207 /*proximity init here*/
2208 rtlpriv->proximity.proxim_on = false;
2209
2210 pcipriv = (void *)rtlpriv->priv;
2211 pcipriv->dev.pdev = pdev;
0c817338 2212
c7cfe38e
C		 2213 /* init cfg & intf_ops */
2214 rtlpriv->rtlhal.interface = INTF_PCI;
2215 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2216 rtlpriv->intf_ops = &rtl_pci_ops;
6f334c2b 2217 rtlpriv->glb_var = &rtl_global_var;
2cdd634e 2218 rtl_efuse_ops_init(hw);
c7cfe38e 2219
0c817338
LF		 2220 /* MEM map */
2221 err = pci_request_regions(pdev, KBUILD_MODNAME);
2222 if (err) {
531940f9 2223 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
3d86b930 2224 goto fail1;
0c817338
LF		 2225 }
2226
c7cfe38e
C		 2227 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2228 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2229 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 2230
2231 /*shared mem start */
2232 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 2233 (unsigned long)pci_iomap(pdev,
2234 rtlpriv->cfg->bar_id, pmem_len);
0c817338 2235 if (rtlpriv->io.pci_mem_start == 0) {
531940f9 2236 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
3d86b930 2237 err = -ENOMEM;
0c817338
LF		 2238 goto fail2;
2239 }
2240
f108a420
LF		 2241 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2242 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2243 pmem_start, pmem_len, pmem_flags,
2244 rtlpriv->io.pci_mem_start);
0c817338
LF		 2245
2246 /* Disable Clk Request */
2247 pci_write_config_byte(pdev, 0x81, 0);
2248 /* leave D3 mode */
2249 pci_write_config_byte(pdev, 0x44, 0);
2250 pci_write_config_byte(pdev, 0x04, 0x06);
2251 pci_write_config_byte(pdev, 0x04, 0x07);
2252
0c817338 2253 /* find adapter */
3d86b930
TG		 2254 if (!_rtl_pci_find_adapter(pdev, hw)) {
2255 err = -ENODEV;
fc81bab5 2256 goto fail2;
3d86b930 2257 }
0c817338
LF		 2258
2259 /* Init IO handler */
2260 _rtl_pci_io_handler_init(&pdev->dev, hw);
2261
2262 /*like read eeprom and so on */
2263 rtlpriv->cfg->ops->read_eeprom_info(hw);
2264
7d63a5f9 2265 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
b03d968b 2266 pr_err("Can't init_sw_vars\n");
7d63a5f9
LF		 2267 err = -ENODEV;
2268 goto fail3;
2269 }
2270 rtlpriv->cfg->ops->init_sw_leds(hw);
2271
2272 /*aspm */
2273 rtl_pci_init_aspm(hw);
2274
0c817338
LF		 2275 /* Init mac80211 sw */
2276 err = rtl_init_core(hw);
2277 if (err) {
b03d968b 2278 pr_err("Can't allocate sw for mac80211\n");
0c817338
LF		 2279 goto fail3;
2280 }
2281
2282 /* Init PCI sw */
12325280 2283 err = rtl_pci_init(hw, pdev);
0c817338 2284 if (err) {
b03d968b 2285 pr_err("Failed to init PCI\n");
0c817338
LF		 2286 goto fail3;
2287 }
2288
38506ece
LF		 2289 err = ieee80211_register_hw(hw);
2290 if (err) {
b03d968b 2291 pr_err("Can't register mac80211 hw.\n");
574e02ab
LF		 2292 err = -ENODEV;
2293 goto fail3;
2294 }
38506ece 2295 rtlpriv->mac80211.mac80211_registered = 1;
574e02ab 2296
610247f4
PKS		 2297 /* add for debug */
2298 rtl_debug_add_one(hw);
2299
38506ece
LF		 2300 /*init rfkill */
2301 rtl_init_rfkill(hw); /* Init PCI sw */
2302
0c817338 2303 rtlpci = rtl_pcidev(pcipriv);
94010fa0 2304 err = rtl_pci_intr_mode_decide(hw);
0c817338 2305 if (err) {
f108a420
LF		 2306 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2307 "%s: failed to register IRQ handler\n",
2308 wiphy_name(hw->wiphy));
0c817338 2309 goto fail3;
0c817338 2310 }
b0302aba 2311 rtlpci->irq_alloc = 1;
0c817338 2312
38506ece 2313 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
0c817338
LF		 2314 return 0;
2315
2316fail3:
38506ece 2317 pci_set_drvdata(pdev, NULL);
0c817338 2318 rtl_deinit_core(hw);
0c817338 2319
fc81bab5 2320fail2:
0c817338 2321 if (rtlpriv->io.pci_mem_start != 0)
62e63975 2322 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338 2323
0c817338 2324 pci_release_regions(pdev);
b0302aba 2325 complete(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2326
2327fail1:
3d86b930
TG		 2328 if (hw)
2329 ieee80211_free_hw(hw);
0c817338
LF		 2330 pci_disable_device(pdev);
2331
3d86b930 2332 return err;
0c817338
LF		 2333}
2334EXPORT_SYMBOL(rtl_pci_probe);
2335
2336void rtl_pci_disconnect(struct pci_dev *pdev)
2337{
2338 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2339 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2340 struct rtl_priv *rtlpriv = rtl_priv(hw);
2341 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2342 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2343
b0302aba
LF		 2344 /* just in case driver is removed before firmware callback */
2345 wait_for_completion(&rtlpriv->firmware_loading_complete);
0c817338
LF		 2346 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2347
610247f4
PKS		 2348 /* remove form debug */
2349 rtl_debug_remove_one(hw);
2350
0c817338
LF		 2351 /*ieee80211_unregister_hw will call ops_stop */
2352 if (rtlmac->mac80211_registered == 1) {
2353 ieee80211_unregister_hw(hw);
2354 rtlmac->mac80211_registered = 0;
2355 } else {
12dfa2f6 2356 rtl_deinit_deferred_work(hw, false);
0c817338
LF		 2357 rtlpriv->intf_ops->adapter_stop(hw);
2358 }
44eb65cf 2359 rtlpriv->cfg->ops->disable_interrupt(hw);
0c817338
LF		 2360
2361 /*deinit rfkill */
2362 rtl_deinit_rfkill(hw);
2363
2364 rtl_pci_deinit(hw);
2365 rtl_deinit_core(hw);
0c817338
LF		 2366 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2367
2368 if (rtlpci->irq_alloc) {
2369 free_irq(rtlpci->pdev->irq, hw);
2370 rtlpci->irq_alloc = 0;
2371 }
2372
94010fa0
AL		 2373 if (rtlpci->using_msi)
2374 pci_disable_msi(rtlpci->pdev);
2375
26634c4b 2376 list_del(&rtlpriv->list);
0c817338 2377 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 2378 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2379 pci_release_regions(pdev);
2380 }
2381
2382 pci_disable_device(pdev);
c7cfe38e
C		 2383
2384 rtl_pci_disable_aspm(hw);
2385
38506ece
LF		 2386 pci_set_drvdata(pdev, NULL);
2387
0c817338
LF		 2388 ieee80211_free_hw(hw);
2389}
2390EXPORT_SYMBOL(rtl_pci_disconnect);
2391
244a77e9 2392#ifdef CONFIG_PM_SLEEP
0c817338 2393/***************************************
ae0122b6
LF		 2394 * kernel pci power state define:
2395 * PCI_D0 ((pci_power_t __force) 0)
2396 * PCI_D1 ((pci_power_t __force) 1)
2397 * PCI_D2 ((pci_power_t __force) 2)
2398 * PCI_D3hot ((pci_power_t __force) 3)
2399 * PCI_D3cold ((pci_power_t __force) 4)
2400 * PCI_UNKNOWN ((pci_power_t __force) 5)
2401
2402 * This function is called when system
2403 * goes into suspend state mac80211 will
2404 * call rtl_mac_stop() from the mac80211
2405 * suspend function first, So there is
2406 * no need to call hw_disable here.
2407 ****************************************/
603be388 2408int rtl_pci_suspend(struct device *dev)
0c817338 2409{
e7338e03 2410 struct ieee80211_hw *hw = dev_get_drvdata(dev);
c7cfe38e
C		 2411 struct rtl_priv *rtlpriv = rtl_priv(hw);
2412
2413 rtlpriv->cfg->ops->hw_suspend(hw);
2414 rtl_deinit_rfkill(hw);
2415
0c817338
LF		 2416 return 0;
2417}
2418EXPORT_SYMBOL(rtl_pci_suspend);
2419
603be388 2420int rtl_pci_resume(struct device *dev)
0c817338 2421{
e7338e03 2422 struct ieee80211_hw *hw = dev_get_drvdata(dev);
c7cfe38e 2423 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 2424
c7cfe38e
C		 2425 rtlpriv->cfg->ops->hw_resume(hw);
2426 rtl_init_rfkill(hw);
0c817338
LF		 2427 return 0;
2428}
2429EXPORT_SYMBOL(rtl_pci_resume);
244a77e9 2430#endif /* CONFIG_PM_SLEEP */
0c817338 2431
1bfcfdcc 2432const struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2433 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2434 .adapter_start = rtl_pci_start,
2435 .adapter_stop = rtl_pci_stop,
26634c4b 2436 .check_buddy_priv = rtl_pci_check_buddy_priv,
0c817338 2437 .adapter_tx = rtl_pci_tx,
c7cfe38e 2438 .flush = rtl_pci_flush,
0c817338 2439 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2440 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2441
2442 .disable_aspm = rtl_pci_disable_aspm,
2443 .enable_aspm = rtl_pci_enable_aspm,
2444};
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