[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192cu / phy.c

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#include "../wifi.h"
#include "../pci.h"
#include "../ps.h"
#include "../core.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "../rtl8192c/phy_common.h"
#include "rf.h"
#include "dm.h"
#include "../rtl8192c/dm_common.h"
#include "../rtl8192c/fw_common.h"
#include "table.h"

u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
			     enum radio_path rfpath, u32 regaddr, u32 bitmask)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u32 original_value, readback_value, bitshift;
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
		 regaddr, rfpath, bitmask);
	if (rtlphy->rf_mode != RF_OP_BY_FW) {
		original_value = _rtl92c_phy_rf_serial_read(hw,
							    rfpath, regaddr);
	} else {
		original_value = _rtl92c_phy_fw_rf_serial_read(hw,
							       rfpath, regaddr);
	}
	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	readback_value = (original_value & bitmask) >> bitshift;
	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
		 regaddr, rfpath, bitmask, original_value);
	return readback_value;
}

void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
			    enum radio_path rfpath,
			    u32 regaddr, u32 bitmask, u32 data)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	u32 original_value, bitshift;

	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
		 regaddr, bitmask, data, rfpath);
	if (rtlphy->rf_mode != RF_OP_BY_FW) {
		if (bitmask != RFREG_OFFSET_MASK) {
			original_value = _rtl92c_phy_rf_serial_read(hw,
								    rfpath,
								    regaddr);
			bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
			data =
			    ((original_value & (~bitmask)) |
			     (data << bitshift));
		}
		_rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
	} else {
		if (bitmask != RFREG_OFFSET_MASK) {
			original_value = _rtl92c_phy_fw_rf_serial_read(hw,
								       rfpath,
								       regaddr);
			bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
			data =
			    ((original_value & (~bitmask)) |
			     (data << bitshift));
		}
		_rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
	}
	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
		 regaddr, bitmask, data, rfpath);
}

bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
{
	bool rtstatus;

	rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
	return rtstatus;
}

bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
{
	bool rtstatus = true;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u16 regval;
	u32 regval32;
	u8 b_reg_hwparafile = 1;

	_rtl92c_phy_init_bb_rf_register_definition(hw);
	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
		       BIT(0) | BIT(1));
	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
	rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
		       FEN_BB_GLB_RSTn | FEN_BBRSTB);
	regval32 = rtl_read_dword(rtlpriv, 0x87c);
	rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
	rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
	if (b_reg_hwparafile == 1)
		rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
	return rtstatus;
}

bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	u32 i;
	u32 arraylength;
	u32 *ptrarray;

	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
	arraylength =  rtlphy->hwparam_tables[MAC_REG].length ;
	ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CUMAC_2T_ARRAY\n");
	for (i = 0; i < arraylength; i = i + 2)
		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
	return true;
}

bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
					    u8 configtype)
{
	int i;
	u32 *phy_regarray_table;
	u32 *agctab_array_table;
	u16 phy_reg_arraylen, agctab_arraylen;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	if (IS_92C_SERIAL(rtlhal->version)) {
		agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
		agctab_array_table =  rtlphy->hwparam_tables[AGCTAB_2T].pdata;
		phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
		phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
	} else {
		agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
		agctab_array_table =  rtlphy->hwparam_tables[AGCTAB_1T].pdata;
		phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
		phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
	}
	if (configtype == BASEBAND_CONFIG_PHY_REG) {
		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
			rtl_addr_delay(phy_regarray_table[i]);
			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
				      phy_regarray_table[i + 1]);
			udelay(1);
			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
				 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
				 phy_regarray_table[i],
				 phy_regarray_table[i + 1]);
		}
	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
		for (i = 0; i < agctab_arraylen; i = i + 2) {
			rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
				      agctab_array_table[i + 1]);
			udelay(1);
			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
				 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
				 agctab_array_table[i],
				 agctab_array_table[i + 1]);
		}
	}
	return true;
}

bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
					      u8 configtype)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	int i;
	u32 *phy_regarray_table_pg;
	u16 phy_regarray_pg_len;

	rtlphy->pwrgroup_cnt = 0;
	phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
	phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
	if (configtype == BASEBAND_CONFIG_PHY_REG) {
		for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
			rtl_addr_delay(phy_regarray_table_pg[i]);
			_rtl92c_store_pwrIndex_diffrate_offset(hw,
						  phy_regarray_table_pg[i],
						  phy_regarray_table_pg[i + 1],
						  phy_regarray_table_pg[i + 2]);
		}
	} else {
		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
			 "configtype != BaseBand_Config_PHY_REG\n");
	}
	return true;
}

bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
					  enum radio_path rfpath)
{
	int i;
	u32 *radioa_array_table;
	u32 *radiob_array_table;
	u16 radioa_arraylen, radiob_arraylen;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	if (IS_92C_SERIAL(rtlhal->version)) {
		radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
		radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
		radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
		radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
			 "Radio_A:RTL8192CURADIOA_2TARRAY\n");
		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
			 "Radio_B:RTL8192CU_RADIOB_2TARRAY\n");
	} else {
		radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
		radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
		radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
		radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
			 "Radio_A:RTL8192CU_RADIOA_1TARRAY\n");
		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
			 "Radio_B:RTL8192CU_RADIOB_1TARRAY\n");
	}
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
	switch (rfpath) {
	case RF90_PATH_A:
		for (i = 0; i < radioa_arraylen; i = i + 2) {
			rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
					RFREG_OFFSET_MASK,
					radioa_array_table[i + 1]);
		}
		break;
	case RF90_PATH_B:
		for (i = 0; i < radiob_arraylen; i = i + 2) {
			rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
					RFREG_OFFSET_MASK,
					radiob_array_table[i + 1]);
		}
		break;
	case RF90_PATH_C:
	case RF90_PATH_D:
		pr_err("switch case %#x not processed\n", rfpath);
		break;
	default:
		break;
	}
	return true;
}

void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	u8 reg_bw_opmode;
	u8 reg_prsr_rsc;

	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
		 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
		 "20MHz" : "40MHz");
	if (is_hal_stop(rtlhal)) {
		rtlphy->set_bwmode_inprogress = false;
		return;
	}
	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
	switch (rtlphy->current_chan_bw) {
	case HT_CHANNEL_WIDTH_20:
		reg_bw_opmode |= BW_OPMODE_20MHZ;
		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
		break;
	case HT_CHANNEL_WIDTH_20_40:
		reg_bw_opmode &= ~BW_OPMODE_20MHZ;
		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
		reg_prsr_rsc =
		    (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
		break;
	default:
		pr_err("unknown bandwidth: %#X\n",
		       rtlphy->current_chan_bw);
		break;
	}
	switch (rtlphy->current_chan_bw) {
	case HT_CHANNEL_WIDTH_20:
		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
		break;
	case HT_CHANNEL_WIDTH_20_40:
		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
		rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
			      (mac->cur_40_prime_sc >> 1));
		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
		rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
			      (mac->cur_40_prime_sc ==
			       HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
		break;
	default:
		pr_err("unknown bandwidth: %#X\n",
		       rtlphy->current_chan_bw);
		break;
	}
	rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
	rtlphy->set_bwmode_inprogress = false;
	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
}

void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	mutex_lock(&rtlpriv->io.bb_mutex);
	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
	mutex_unlock(&rtlpriv->io.bb_mutex);
}

void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
{
	u8 tmpreg;
	u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	tmpreg = rtl_read_byte(rtlpriv, 0xd03);

	if ((tmpreg & 0x70) != 0)
		rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
	else
		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);

	if ((tmpreg & 0x70) != 0) {
		rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
		if (is2t)
			rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
						  MASK12BITS);
		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
			      (rf_a_mode & 0x8FFFF) | 0x10000);
		if (is2t)
			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
				      (rf_b_mode & 0x8FFFF) | 0x10000);
	}
	lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
	rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
	mdelay(100);
	if ((tmpreg & 0x70) != 0) {
		rtl_write_byte(rtlpriv, 0xd03, tmpreg);
		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
		if (is2t)
			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
				      rf_b_mode);
	} else {
		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
	}
}

static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
					    enum rf_pwrstate rfpwr_state)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
	bool bresult = true;
	u8 i, queue_id;
	struct rtl8192_tx_ring *ring = NULL;

	switch (rfpwr_state) {
	case ERFON:
		if ((ppsc->rfpwr_state == ERFOFF) &&
		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
			bool rtstatus;
			u32 InitializeCount = 0;

			do {
				InitializeCount++;
				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
					 "IPS Set eRf nic enable\n");
				rtstatus = rtl_ps_enable_nic(hw);
			} while (!rtstatus && (InitializeCount < 10));
			RT_CLEAR_PS_LEVEL(ppsc,
					  RT_RF_OFF_LEVL_HALT_NIC);
		} else {
			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
				 "Set ERFON sleeped:%d ms\n",
				 jiffies_to_msecs(jiffies -
						  ppsc->last_sleep_jiffies));
			ppsc->last_awake_jiffies = jiffies;
			rtl92ce_phy_set_rf_on(hw);
		}
		if (mac->link_state == MAC80211_LINKED) {
			rtlpriv->cfg->ops->led_control(hw,
						       LED_CTL_LINK);
		} else {
			rtlpriv->cfg->ops->led_control(hw,
						       LED_CTL_NO_LINK);
		}
		break;
	case ERFOFF:
		for (queue_id = 0, i = 0;
		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
			ring = &pcipriv->dev.tx_ring[queue_id];
			if (skb_queue_len(&ring->queue) == 0 ||
				queue_id == BEACON_QUEUE) {
				queue_id++;
				continue;
			} else {
				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
					 i + 1,
					 queue_id,
					 skb_queue_len(&ring->queue));
				udelay(10);
				i++;
			}
			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
					 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
					 MAX_DOZE_WAITING_TIMES_9x,
					 queue_id,
					 skb_queue_len(&ring->queue));
				break;
			}
		}
		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
				 "IPS Set eRf nic disable\n");
			rtl_ps_disable_nic(hw);
			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
		} else {
			if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
				rtlpriv->cfg->ops->led_control(hw,
							 LED_CTL_NO_LINK);
			} else {
				rtlpriv->cfg->ops->led_control(hw,
							 LED_CTL_POWER_OFF);
			}
		}
		break;
	case ERFSLEEP:
		if (ppsc->rfpwr_state == ERFOFF)
			return false;
		for (queue_id = 0, i = 0;
		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
			ring = &pcipriv->dev.tx_ring[queue_id];
			if (skb_queue_len(&ring->queue) == 0) {
				queue_id++;
				continue;
			} else {
				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
					 i + 1, queue_id,
					 skb_queue_len(&ring->queue));
				udelay(10);
				i++;
			}
			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
					 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
					 MAX_DOZE_WAITING_TIMES_9x,
					 queue_id,
					 skb_queue_len(&ring->queue));
				break;
			}
		}
		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
			 "Set ERFSLEEP awaked:%d ms\n",
			 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
		ppsc->last_sleep_jiffies = jiffies;
		_rtl92c_phy_set_rf_sleep(hw);
		break;
	default:
		pr_err("switch case %#x not processed\n",
		       rfpwr_state);
		bresult = false;
		break;
	}
	if (bresult)
		ppsc->rfpwr_state = rfpwr_state;
	return bresult;
}

bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
				    enum rf_pwrstate rfpwr_state)
{
	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
	bool bresult = false;

	if (rfpwr_state == ppsc->rfpwr_state)
		return bresult;
	bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
	return bresult;
}
Commit	Line	Data
f0a39ae7 G	1	/******************************************************************************
f0a39ae7 G	2	*
c1d6604d	3	* Copyright(c) 2009-2012 Realtek Corporation.
f0a39ae7 G	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
f0a39ae7 G	14	* The full GNU General Public License is included in this distribution in the
	15	* file called LICENSE.
	16	*
	17	* Contact Information:
	18	* wlanfae <wlanfae@realtek.com>
	19	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	20	* Hsinchu 300, Taiwan.
	21	*
	22	* Larry Finger <Larry.Finger@lwfinger.net>
	23	*
	24	*****************************************************************************/
	25
	26	#include "../wifi.h"
	27	#include "../pci.h"
	28	#include "../ps.h"
25b13dbc	29	#include "../core.h"
f0a39ae7 G	30	#include "reg.h"
	31	#include "def.h"
	32	#include "phy.h"
9f087a92	33	#include "../rtl8192c/phy_common.h"
f0a39ae7 G	34	#include "rf.h"
f0a39ae7 G	35	#include "dm.h"
9f087a92 LF	36	#include "../rtl8192c/dm_common.h"
9f087a92 LF	37	#include "../rtl8192c/fw_common.h"
f0a39ae7 G	38	#include "table.h"
f0a39ae7 G	39
1472d3a8	40	u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
d3bb1429	41	enum radio_path rfpath, u32 regaddr, u32 bitmask)
f0a39ae7 G	42	{
	43	struct rtl_priv *rtlpriv = rtl_priv(hw);
	44	u32 original_value, readback_value, bitshift;
	45	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	46
f30d7507 JP	47	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
	48	"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
	49	regaddr, rfpath, bitmask);
f0a39ae7 G	50	if (rtlphy->rf_mode != RF_OP_BY_FW) {
	51	original_value = _rtl92c_phy_rf_serial_read(hw,
	52	rfpath, regaddr);
	53	} else {
	54	original_value = _rtl92c_phy_fw_rf_serial_read(hw,
	55	rfpath, regaddr);
	56	}
	57	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	58	readback_value = (original_value & bitmask) >> bitshift;
	59	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507 JP	60	"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
f30d7507 JP	61	regaddr, rfpath, bitmask, original_value);
f0a39ae7 G	62	return readback_value;
	63	}
	64
1472d3a8	65	void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
d3bb1429 LF	66	enum radio_path rfpath,
d3bb1429 LF	67	u32 regaddr, u32 bitmask, u32 data)
f0a39ae7 G	68	{
	69	struct rtl_priv *rtlpriv = rtl_priv(hw);
	70	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	71	u32 original_value, bitshift;
	72
	73	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507 JP	74	"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
f30d7507 JP	75	regaddr, bitmask, data, rfpath);
f0a39ae7 G	76	if (rtlphy->rf_mode != RF_OP_BY_FW) {
	77	if (bitmask != RFREG_OFFSET_MASK) {
	78	original_value = _rtl92c_phy_rf_serial_read(hw,
	79	rfpath,
	80	regaddr);
	81	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	82	data =
	83	((original_value & (~bitmask)) \|
	84	(data << bitshift));
	85	}
	86	_rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
	87	} else {
	88	if (bitmask != RFREG_OFFSET_MASK) {
	89	original_value = _rtl92c_phy_fw_rf_serial_read(hw,
	90	rfpath,
	91	regaddr);
	92	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	93	data =
	94	((original_value & (~bitmask)) \|
	95	(data << bitshift));
	96	}
	97	_rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
	98	}
f30d7507 JP	99	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
	100	"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
	101	regaddr, bitmask, data, rfpath);
f0a39ae7 G	102	}
f0a39ae7 G	103
1472d3a8	104	bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
f0a39ae7 G	105	{
f0a39ae7 G	106	bool rtstatus;
f0a39ae7	107
1472d3a8	108	rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
f0a39ae7 G	109	return rtstatus;
	110	}
	111
1472d3a8	112	bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
f0a39ae7 G	113	{
	114	bool rtstatus = true;
	115	struct rtl_priv *rtlpriv = rtl_priv(hw);
f0a39ae7	116	u16 regval;
8a719208	117	u32 regval32;
f0a39ae7 G	118	u8 b_reg_hwparafile = 1;
	119
	120	_rtl92c_phy_init_bb_rf_register_definition(hw);
	121	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
	122	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval \| BIT(13) \|
	123	BIT(0) \| BIT(1));
	124	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
	125	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
	126	rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN \| RF_RSTB \| RF_SDMRSTB);
f5372e94 TY	127	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA \| FEN_USBD \|
f5372e94 TY	128	FEN_BB_GLB_RSTn \| FEN_BBRSTB);
8a719208 MCA	129	regval32 = rtl_read_dword(rtlpriv, 0x87c);
8a719208 MCA	130	rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
f5372e94	131	rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
f0a39ae7 G	132	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
	133	if (b_reg_hwparafile == 1)
	134	rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
	135	return rtstatus;
	136	}
	137
1472d3a8	138	bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
f0a39ae7 G	139	{
	140	struct rtl_priv *rtlpriv = rtl_priv(hw);
	141	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	142	u32 i;
	143	u32 arraylength;
	144	u32 *ptrarray;
	145
f30d7507	146	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
f0a39ae7 G	147	arraylength = rtlphy->hwparam_tables[MAC_REG].length ;
f0a39ae7 G	148	ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
8657f9c4	149	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CUMAC_2T_ARRAY\n");
f0a39ae7 G	150	for (i = 0; i < arraylength; i = i + 2)
	151	rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
	152	return true;
	153	}
	154
1472d3a8	155	bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
d3bb1429	156	u8 configtype)
f0a39ae7 G	157	{
	158	int i;
	159	u32 *phy_regarray_table;
	160	u32 *agctab_array_table;
	161	u16 phy_reg_arraylen, agctab_arraylen;
	162	struct rtl_priv *rtlpriv = rtl_priv(hw);
	163	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	164	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	165
	166	if (IS_92C_SERIAL(rtlhal->version)) {
	167	agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
	168	agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
	169	phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
	170	phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
	171	} else {
	172	agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
	173	agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
	174	phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
	175	phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
	176	}
	177	if (configtype == BASEBAND_CONFIG_PHY_REG) {
	178	for (i = 0; i < phy_reg_arraylen; i = i + 2) {
25b13dbc	179	rtl_addr_delay(phy_regarray_table[i]);
f0a39ae7 G	180	rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
	181	phy_regarray_table[i + 1]);
	182	udelay(1);
	183	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 JP	184	"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
	185	phy_regarray_table[i],
	186	phy_regarray_table[i + 1]);
f0a39ae7	187	}
f0a39ae7 G	188	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
	189	for (i = 0; i < agctab_arraylen; i = i + 2) {
	190	rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
	191	agctab_array_table[i + 1]);
	192	udelay(1);
	193	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 JP	194	"The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
	195	agctab_array_table[i],
	196	agctab_array_table[i + 1]);
f0a39ae7 G	197	}
	198	}
	199	return true;
	200	}
	201
1472d3a8	202	bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
d3bb1429	203	u8 configtype)
f0a39ae7 G	204	{
	205	struct rtl_priv *rtlpriv = rtl_priv(hw);
	206	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	207	int i;
	208	u32 *phy_regarray_table_pg;
	209	u16 phy_regarray_pg_len;
	210
	211	rtlphy->pwrgroup_cnt = 0;
	212	phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
	213	phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
	214	if (configtype == BASEBAND_CONFIG_PHY_REG) {
	215	for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
25b13dbc	216	rtl_addr_delay(phy_regarray_table_pg[i]);
f0a39ae7 G	217	_rtl92c_store_pwrIndex_diffrate_offset(hw,
	218	phy_regarray_table_pg[i],
	219	phy_regarray_table_pg[i + 1],
	220	phy_regarray_table_pg[i + 2]);
	221	}
	222	} else {
	223	RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
f30d7507	224	"configtype != BaseBand_Config_PHY_REG\n");
f0a39ae7 G	225	}
	226	return true;
	227	}
	228
1472d3a8	229	bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
f0a39ae7 G	230	enum radio_path rfpath)
	231	{
	232	int i;
	233	u32 *radioa_array_table;
	234	u32 *radiob_array_table;
	235	u16 radioa_arraylen, radiob_arraylen;
	236	struct rtl_priv *rtlpriv = rtl_priv(hw);
	237	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	238	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	239
	240	if (IS_92C_SERIAL(rtlhal->version)) {
	241	radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
	242	radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
	243	radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
	244	radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
	245	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4	246	"Radio_A:RTL8192CURADIOA_2TARRAY\n");
f0a39ae7	247	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4	248	"Radio_B:RTL8192CU_RADIOB_2TARRAY\n");
f0a39ae7 G	249	} else {
	250	radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
	251	radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
	252	radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
	253	radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
	254	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4	255	"Radio_A:RTL8192CU_RADIOA_1TARRAY\n");
f0a39ae7	256	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4	257	"Radio_B:RTL8192CU_RADIOB_1TARRAY\n");
f0a39ae7	258	}
f30d7507	259	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
f0a39ae7 G	260	switch (rfpath) {
	261	case RF90_PATH_A:
	262	for (i = 0; i < radioa_arraylen; i = i + 2) {
25b13dbc LF	263	rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
	264	RFREG_OFFSET_MASK,
	265	radioa_array_table[i + 1]);
f0a39ae7	266	}
f0a39ae7 G	267	break;
	268	case RF90_PATH_B:
	269	for (i = 0; i < radiob_arraylen; i = i + 2) {
25b13dbc LF	270	rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
	271	RFREG_OFFSET_MASK,
	272	radiob_array_table[i + 1]);
f0a39ae7 G	273	}
	274	break;
	275	case RF90_PATH_C:
f0a39ae7	276	case RF90_PATH_D:
c38af3f0	277	pr_err("switch case %#x not processed\n", rfpath);
f0a39ae7	278	break;
25b13dbc LF	279	default:
25b13dbc LF	280	break;
f0a39ae7 G	281	}
	282	return true;
	283	}
	284
1472d3a8	285	void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
f0a39ae7 G	286	{
	287	struct rtl_priv *rtlpriv = rtl_priv(hw);
	288	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	289	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	290	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	291	u8 reg_bw_opmode;
	292	u8 reg_prsr_rsc;
	293
f30d7507 JP	294	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
	295	rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
	296	"20MHz" : "40MHz");
f0a39ae7 G	297	if (is_hal_stop(rtlhal)) {
	298	rtlphy->set_bwmode_inprogress = false;
	299	return;
	300	}
	301	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
	302	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
	303	switch (rtlphy->current_chan_bw) {
	304	case HT_CHANNEL_WIDTH_20:
	305	reg_bw_opmode \|= BW_OPMODE_20MHZ;
	306	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
	307	break;
	308	case HT_CHANNEL_WIDTH_20_40:
	309	reg_bw_opmode &= ~BW_OPMODE_20MHZ;
	310	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
	311	reg_prsr_rsc =
	312	(reg_prsr_rsc & 0x90) \| (mac->cur_40_prime_sc << 5);
	313	rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
	314	break;
	315	default:
c38af3f0 LF	316	pr_err("unknown bandwidth: %#X\n",
c38af3f0 LF	317	rtlphy->current_chan_bw);
f0a39ae7 G	318	break;
	319	}
	320	switch (rtlphy->current_chan_bw) {
	321	case HT_CHANNEL_WIDTH_20:
	322	rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
	323	rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
	324	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
	325	break;
	326	case HT_CHANNEL_WIDTH_20_40:
	327	rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
	328	rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
	329	rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
	330	(mac->cur_40_prime_sc >> 1));
	331	rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
	332	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
	333	rtl_set_bbreg(hw, 0x818, (BIT(26) \| BIT(27)),
	334	(mac->cur_40_prime_sc ==
	335	HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
	336	break;
	337	default:
c38af3f0 LF	338	pr_err("unknown bandwidth: %#X\n",
c38af3f0 LF	339	rtlphy->current_chan_bw);
f0a39ae7 G	340	break;
f0a39ae7 G	341	}
1472d3a8	342	rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
f0a39ae7	343	rtlphy->set_bwmode_inprogress = false;
f30d7507	344	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
f0a39ae7 G	345	}
f0a39ae7 G	346
1472d3a8	347	void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
f0a39ae7 G	348	{
	349	struct rtl_priv *rtlpriv = rtl_priv(hw);
	350
	351	mutex_lock(&rtlpriv->io.bb_mutex);
	352	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
	353	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
	354	mutex_unlock(&rtlpriv->io.bb_mutex);
	355	}
	356
1472d3a8	357	void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
f0a39ae7 G	358	{
	359	u8 tmpreg;
	360	u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
	361	struct rtl_priv *rtlpriv = rtl_priv(hw);
	362
	363	tmpreg = rtl_read_byte(rtlpriv, 0xd03);
	364
	365	if ((tmpreg & 0x70) != 0)
	366	rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
	367	else
	368	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
	369
	370	if ((tmpreg & 0x70) != 0) {
	371	rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
	372	if (is2t)
	373	rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
	374	MASK12BITS);
	375	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
	376	(rf_a_mode & 0x8FFFF) \| 0x10000);
	377	if (is2t)
	378	rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
	379	(rf_b_mode & 0x8FFFF) \| 0x10000);
	380	}
	381	lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
	382	rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal \| 0x08000);
	383	mdelay(100);
	384	if ((tmpreg & 0x70) != 0) {
	385	rtl_write_byte(rtlpriv, 0xd03, tmpreg);
	386	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
	387	if (is2t)
	388	rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
	389	rf_b_mode);
	390	} else {
	391	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
	392	}
	393	}
	394
d3bb1429	395	static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
f0a39ae7 G	396	enum rf_pwrstate rfpwr_state)
	397	{
	398	struct rtl_priv *rtlpriv = rtl_priv(hw);
	399	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
	400	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	401	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
	402	bool bresult = true;
	403	u8 i, queue_id;
	404	struct rtl8192_tx_ring *ring = NULL;
	405
f0a39ae7 G	406	switch (rfpwr_state) {
	407	case ERFON:
	408	if ((ppsc->rfpwr_state == ERFOFF) &&
	409	RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
	410	bool rtstatus;
	411	u32 InitializeCount = 0;
	412
	413	do {
	414	InitializeCount++;
	415	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507	416	"IPS Set eRf nic enable\n");
f0a39ae7	417	rtstatus = rtl_ps_enable_nic(hw);
23677ce3	418	} while (!rtstatus && (InitializeCount < 10));
f0a39ae7 G	419	RT_CLEAR_PS_LEVEL(ppsc,
	420	RT_RF_OFF_LEVL_HALT_NIC);
	421	} else {
	422	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 JP	423	"Set ERFON sleeped:%d ms\n",
	424	jiffies_to_msecs(jiffies -
	425	ppsc->last_sleep_jiffies));
f0a39ae7 G	426	ppsc->last_awake_jiffies = jiffies;
	427	rtl92ce_phy_set_rf_on(hw);
	428	}
	429	if (mac->link_state == MAC80211_LINKED) {
	430	rtlpriv->cfg->ops->led_control(hw,
	431	LED_CTL_LINK);
	432	} else {
	433	rtlpriv->cfg->ops->led_control(hw,
	434	LED_CTL_NO_LINK);
	435	}
	436	break;
	437	case ERFOFF:
	438	for (queue_id = 0, i = 0;
	439	queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
	440	ring = &pcipriv->dev.tx_ring[queue_id];
	441	if (skb_queue_len(&ring->queue) == 0 \|\|
	442	queue_id == BEACON_QUEUE) {
	443	queue_id++;
	444	continue;
	445	} else {
	446	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 JP	447	"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
	448	i + 1,
	449	queue_id,
	450	skb_queue_len(&ring->queue));
f0a39ae7 G	451	udelay(10);
	452	i++;
	453	}
	454	if (i >= MAX_DOZE_WAITING_TIMES_9x) {
	455	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 JP	456	"ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
	457	MAX_DOZE_WAITING_TIMES_9x,
	458	queue_id,
	459	skb_queue_len(&ring->queue));
f0a39ae7 G	460	break;
	461	}
	462	}
	463	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
	464	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507	465	"IPS Set eRf nic disable\n");
f0a39ae7 G	466	rtl_ps_disable_nic(hw);
	467	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
	468	} else {
	469	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
	470	rtlpriv->cfg->ops->led_control(hw,
	471	LED_CTL_NO_LINK);
	472	} else {
	473	rtlpriv->cfg->ops->led_control(hw,
	474	LED_CTL_POWER_OFF);
	475	}
	476	}
	477	break;
	478	case ERFSLEEP:
	479	if (ppsc->rfpwr_state == ERFOFF)
91ddff8a	480	return false;
f0a39ae7 G	481	for (queue_id = 0, i = 0;
	482	queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
	483	ring = &pcipriv->dev.tx_ring[queue_id];
	484	if (skb_queue_len(&ring->queue) == 0) {
	485	queue_id++;
	486	continue;
	487	} else {
	488	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 JP	489	"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
	490	i + 1, queue_id,
	491	skb_queue_len(&ring->queue));
f0a39ae7 G	492	udelay(10);
	493	i++;
	494	}
	495	if (i >= MAX_DOZE_WAITING_TIMES_9x) {
	496	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 JP	497	"ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
	498	MAX_DOZE_WAITING_TIMES_9x,
	499	queue_id,
	500	skb_queue_len(&ring->queue));
f0a39ae7 G	501	break;
	502	}
	503	}
	504	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 JP	505	"Set ERFSLEEP awaked:%d ms\n",
f30d7507 JP	506	jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
f0a39ae7	507	ppsc->last_sleep_jiffies = jiffies;
1472d3a8	508	_rtl92c_phy_set_rf_sleep(hw);
f0a39ae7 G	509	break;
f0a39ae7 G	510	default:
c38af3f0 LF	511	pr_err("switch case %#x not processed\n",
c38af3f0 LF	512	rfpwr_state);
f0a39ae7 G	513	bresult = false;
	514	break;
	515	}
	516	if (bresult)
	517	ppsc->rfpwr_state = rfpwr_state;
f0a39ae7 G	518	return bresult;
	519	}
	520
1472d3a8	521	bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
d3bb1429	522	enum rf_pwrstate rfpwr_state)
f0a39ae7 G	523	{
	524	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
	525	bool bresult = false;
	526
	527	if (rfpwr_state == ppsc->rfpwr_state)
	528	return bresult;
1472d3a8	529	bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
f0a39ae7 G	530	return bresult;
f0a39ae7 G	531	}