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5bd4f692 LF |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright(c) 2009-2012 Realtek Corporation.*/ | |
7274a8c2 CL |
3 | |
4 | #include "../wifi.h" | |
5 | #include "../pci.h" | |
6 | #include "../ps.h" | |
25b13dbc | 7 | #include "../core.h" |
7274a8c2 CL |
8 | #include "reg.h" |
9 | #include "def.h" | |
10 | #include "phy.h" | |
11 | #include "rf.h" | |
12 | #include "dm.h" | |
13 | #include "table.h" | |
14 | #include "sw.h" | |
15 | #include "hw.h" | |
16 | ||
17 | #define MAX_RF_IMR_INDEX 12 | |
18 | #define MAX_RF_IMR_INDEX_NORMAL 13 | |
19 | #define RF_REG_NUM_FOR_C_CUT_5G 6 | |
20 | #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 | |
21 | #define RF_REG_NUM_FOR_C_CUT_2G 5 | |
22 | #define RF_CHNL_NUM_5G 19 | |
23 | #define RF_CHNL_NUM_5G_40M 17 | |
24 | #define TARGET_CHNL_NUM_5G 221 | |
25 | #define TARGET_CHNL_NUM_2G 14 | |
26 | #define CV_CURVE_CNT 64 | |
27 | ||
28 | static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { | |
29 | 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 | |
30 | }; | |
31 | ||
32 | static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { | |
33 | RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 | |
34 | }; | |
35 | ||
36 | static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { | |
37 | RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 | |
38 | }; | |
39 | ||
40 | static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { | |
41 | 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E | |
42 | }; | |
43 | ||
44 | static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { | |
45 | BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), | |
46 | BIT(10) | BIT(9), | |
47 | BIT(18) | BIT(17) | BIT(16) | BIT(1), | |
48 | BIT(2) | BIT(1), | |
49 | BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | |
50 | }; | |
51 | ||
52 | static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { | |
53 | 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, | |
54 | 112, 116, 120, 124, 128, 132, 136, 140 | |
55 | }; | |
56 | ||
57 | static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { | |
58 | 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, | |
59 | 118, 122, 126, 130, 134, 138 | |
60 | }; | |
61 | static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { | |
62 | {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, | |
63 | {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, | |
64 | {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, | |
65 | {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, | |
66 | {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} | |
67 | }; | |
68 | ||
69 | static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { | |
70 | {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, | |
71 | {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, | |
72 | {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} | |
73 | }; | |
74 | ||
75 | static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; | |
76 | ||
77 | static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { | |
78 | {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, | |
79 | {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, | |
80 | {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} | |
81 | }; | |
82 | ||
83 | /* [mode][patha+b][reg] */ | |
84 | static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = { | |
85 | { | |
86 | /* channel 1-14. */ | |
87 | { | |
88 | 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, | |
89 | 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff | |
90 | }, | |
91 | /* path 36-64 */ | |
92 | { | |
93 | 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, | |
94 | 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, | |
95 | 0x32c9a | |
96 | }, | |
97 | /* 100 -165 */ | |
98 | { | |
99 | 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, | |
100 | 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a | |
101 | } | |
102 | } | |
103 | }; | |
104 | ||
105 | static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0}; | |
106 | ||
107 | static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0}; | |
108 | ||
109 | static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { | |
110 | 25141, 25116, 25091, 25066, 25041, | |
111 | 25016, 24991, 24966, 24941, 24917, | |
112 | 24892, 24867, 24843, 24818, 24794, | |
113 | 24770, 24765, 24721, 24697, 24672, | |
114 | 24648, 24624, 24600, 24576, 24552, | |
115 | 24528, 24504, 24480, 24457, 24433, | |
116 | 24409, 24385, 24362, 24338, 24315, | |
117 | 24291, 24268, 24245, 24221, 24198, | |
118 | 24175, 24151, 24128, 24105, 24082, | |
119 | 24059, 24036, 24013, 23990, 23967, | |
120 | 23945, 23922, 23899, 23876, 23854, | |
121 | 23831, 23809, 23786, 23764, 23741, | |
122 | 23719, 23697, 23674, 23652, 23630, | |
123 | 23608, 23586, 23564, 23541, 23519, | |
124 | 23498, 23476, 23454, 23432, 23410, | |
125 | 23388, 23367, 23345, 23323, 23302, | |
126 | 23280, 23259, 23237, 23216, 23194, | |
127 | 23173, 23152, 23130, 23109, 23088, | |
128 | 23067, 23046, 23025, 23003, 22982, | |
129 | 22962, 22941, 22920, 22899, 22878, | |
130 | 22857, 22837, 22816, 22795, 22775, | |
131 | 22754, 22733, 22713, 22692, 22672, | |
132 | 22652, 22631, 22611, 22591, 22570, | |
133 | 22550, 22530, 22510, 22490, 22469, | |
134 | 22449, 22429, 22409, 22390, 22370, | |
135 | 22350, 22336, 22310, 22290, 22271, | |
136 | 22251, 22231, 22212, 22192, 22173, | |
137 | 22153, 22134, 22114, 22095, 22075, | |
138 | 22056, 22037, 22017, 21998, 21979, | |
139 | 21960, 21941, 21921, 21902, 21883, | |
140 | 21864, 21845, 21826, 21807, 21789, | |
141 | 21770, 21751, 21732, 21713, 21695, | |
142 | 21676, 21657, 21639, 21620, 21602, | |
143 | 21583, 21565, 21546, 21528, 21509, | |
144 | 21491, 21473, 21454, 21436, 21418, | |
145 | 21400, 21381, 21363, 21345, 21327, | |
146 | 21309, 21291, 21273, 21255, 21237, | |
147 | 21219, 21201, 21183, 21166, 21148, | |
148 | 21130, 21112, 21095, 21077, 21059, | |
149 | 21042, 21024, 21007, 20989, 20972, | |
150 | 25679, 25653, 25627, 25601, 25575, | |
151 | 25549, 25523, 25497, 25471, 25446, | |
152 | 25420, 25394, 25369, 25343, 25318, | |
153 | 25292, 25267, 25242, 25216, 25191, | |
154 | 25166 | |
155 | }; | |
156 | ||
157 | /* channel 1~14 */ | |
158 | static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { | |
159 | 26084, 26030, 25976, 25923, 25869, 25816, 25764, | |
160 | 25711, 25658, 25606, 25554, 25502, 25451, 25328 | |
161 | }; | |
162 | ||
163 | static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask) | |
164 | { | |
165 | u32 i; | |
166 | ||
167 | for (i = 0; i <= 31; i++) { | |
168 | if (((bitmask >> i) & 0x1) == 1) | |
169 | break; | |
170 | } | |
171 | ||
172 | return i; | |
173 | } | |
174 | ||
175 | u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) | |
176 | { | |
177 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
178 | struct rtl_hal *rtlhal = rtl_hal(rtlpriv); | |
179 | u32 returnvalue, originalvalue, bitshift; | |
7274a8c2 | 180 | |
f30d7507 JP |
181 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", |
182 | regaddr, bitmask); | |
7274a8c2 | 183 | if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) { |
7949513b RS |
184 | u8 dbi_direct = 0; |
185 | ||
7274a8c2 CL |
186 | /* mac1 use phy0 read radio_b. */ |
187 | /* mac0 use phy1 read radio_b. */ | |
188 | if (rtlhal->during_mac1init_radioa) | |
189 | dbi_direct = BIT(3); | |
190 | else if (rtlhal->during_mac0init_radiob) | |
191 | dbi_direct = BIT(3) | BIT(2); | |
192 | originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr, | |
193 | dbi_direct); | |
194 | } else { | |
195 | originalvalue = rtl_read_dword(rtlpriv, regaddr); | |
196 | } | |
197 | bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); | |
198 | returnvalue = (originalvalue & bitmask) >> bitshift; | |
f30d7507 JP |
199 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, |
200 | "BBR MASK=0x%x Addr[0x%x]=0x%x\n", | |
201 | bitmask, regaddr, originalvalue); | |
7274a8c2 CL |
202 | return returnvalue; |
203 | } | |
204 | ||
205 | void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, | |
206 | u32 regaddr, u32 bitmask, u32 data) | |
207 | { | |
208 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
209 | struct rtl_hal *rtlhal = rtl_hal(rtlpriv); | |
210 | u8 dbi_direct = 0; | |
211 | u32 originalvalue, bitshift; | |
212 | ||
f30d7507 JP |
213 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, |
214 | "regaddr(%#x), bitmask(%#x), data(%#x)\n", | |
215 | regaddr, bitmask, data); | |
7274a8c2 CL |
216 | if (rtlhal->during_mac1init_radioa) |
217 | dbi_direct = BIT(3); | |
218 | else if (rtlhal->during_mac0init_radiob) | |
219 | /* mac0 use phy1 write radio_b. */ | |
220 | dbi_direct = BIT(3) | BIT(2); | |
25b13dbc | 221 | if (bitmask != MASKDWORD) { |
7274a8c2 CL |
222 | if (rtlhal->during_mac1init_radioa || |
223 | rtlhal->during_mac0init_radiob) | |
224 | originalvalue = rtl92de_read_dword_dbi(hw, | |
225 | (u16) regaddr, | |
226 | dbi_direct); | |
227 | else | |
228 | originalvalue = rtl_read_dword(rtlpriv, regaddr); | |
229 | bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); | |
230 | data = ((originalvalue & (~bitmask)) | (data << bitshift)); | |
231 | } | |
232 | if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) | |
233 | rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct); | |
234 | else | |
235 | rtl_write_dword(rtlpriv, regaddr, data); | |
f30d7507 JP |
236 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, |
237 | "regaddr(%#x), bitmask(%#x), data(%#x)\n", | |
238 | regaddr, bitmask, data); | |
7274a8c2 CL |
239 | } |
240 | ||
241 | static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, | |
242 | enum radio_path rfpath, u32 offset) | |
243 | { | |
244 | ||
245 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
246 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
247 | struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; | |
248 | u32 newoffset; | |
249 | u32 tmplong, tmplong2; | |
250 | u8 rfpi_enable = 0; | |
251 | u32 retvalue; | |
252 | ||
253 | newoffset = offset; | |
25b13dbc | 254 | tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); |
7274a8c2 CL |
255 | if (rfpath == RF90_PATH_A) |
256 | tmplong2 = tmplong; | |
257 | else | |
25b13dbc | 258 | tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); |
7274a8c2 CL |
259 | tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | |
260 | (newoffset << 23) | BLSSIREADEDGE; | |
25b13dbc | 261 | rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, |
7274a8c2 CL |
262 | tmplong & (~BLSSIREADEDGE)); |
263 | udelay(10); | |
25b13dbc | 264 | rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); |
7274a8c2 CL |
265 | udelay(50); |
266 | udelay(50); | |
25b13dbc | 267 | rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, |
7274a8c2 CL |
268 | tmplong | BLSSIREADEDGE); |
269 | udelay(10); | |
270 | if (rfpath == RF90_PATH_A) | |
271 | rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, | |
272 | BIT(8)); | |
273 | else if (rfpath == RF90_PATH_B) | |
274 | rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, | |
275 | BIT(8)); | |
276 | if (rfpi_enable) | |
da17fcff | 277 | retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, |
7274a8c2 CL |
278 | BLSSIREADBACKDATA); |
279 | else | |
da17fcff | 280 | retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, |
7274a8c2 | 281 | BLSSIREADBACKDATA); |
f30d7507 | 282 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", |
da17fcff | 283 | rfpath, pphyreg->rf_rb, retvalue); |
7274a8c2 CL |
284 | return retvalue; |
285 | } | |
286 | ||
287 | static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, | |
288 | enum radio_path rfpath, | |
289 | u32 offset, u32 data) | |
290 | { | |
291 | u32 data_and_addr; | |
292 | u32 newoffset; | |
293 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
294 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
295 | struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; | |
296 | ||
297 | newoffset = offset; | |
298 | /* T65 RF */ | |
299 | data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; | |
25b13dbc | 300 | rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); |
f30d7507 JP |
301 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", |
302 | rfpath, pphyreg->rf3wire_offset, data_and_addr); | |
7274a8c2 CL |
303 | } |
304 | ||
305 | u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, | |
306 | enum radio_path rfpath, u32 regaddr, u32 bitmask) | |
307 | { | |
308 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
309 | u32 original_value, readback_value, bitshift; | |
7274a8c2 | 310 | |
f30d7507 JP |
311 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, |
312 | "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", | |
313 | regaddr, rfpath, bitmask); | |
92541dd9 | 314 | spin_lock(&rtlpriv->locks.rf_lock); |
7274a8c2 CL |
315 | original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); |
316 | bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); | |
317 | readback_value = (original_value & bitmask) >> bitshift; | |
92541dd9 | 318 | spin_unlock(&rtlpriv->locks.rf_lock); |
f30d7507 JP |
319 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, |
320 | "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", | |
321 | regaddr, rfpath, bitmask, original_value); | |
7274a8c2 CL |
322 | return readback_value; |
323 | } | |
324 | ||
325 | void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, | |
326 | u32 regaddr, u32 bitmask, u32 data) | |
327 | { | |
328 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
329 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
330 | u32 original_value, bitshift; | |
7274a8c2 CL |
331 | |
332 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, | |
f30d7507 JP |
333 | "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", |
334 | regaddr, bitmask, data, rfpath); | |
7274a8c2 CL |
335 | if (bitmask == 0) |
336 | return; | |
92541dd9 | 337 | spin_lock(&rtlpriv->locks.rf_lock); |
7274a8c2 | 338 | if (rtlphy->rf_mode != RF_OP_BY_FW) { |
25b13dbc | 339 | if (bitmask != RFREG_OFFSET_MASK) { |
7274a8c2 CL |
340 | original_value = _rtl92d_phy_rf_serial_read(hw, |
341 | rfpath, regaddr); | |
342 | bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); | |
343 | data = ((original_value & (~bitmask)) | | |
344 | (data << bitshift)); | |
345 | } | |
346 | _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); | |
347 | } | |
92541dd9 | 348 | spin_unlock(&rtlpriv->locks.rf_lock); |
f30d7507 JP |
349 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, |
350 | "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", | |
351 | regaddr, bitmask, data, rfpath); | |
7274a8c2 CL |
352 | } |
353 | ||
354 | bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) | |
355 | { | |
356 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
357 | u32 i; | |
358 | u32 arraylength; | |
359 | u32 *ptrarray; | |
360 | ||
f30d7507 | 361 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); |
7274a8c2 CL |
362 | arraylength = MAC_2T_ARRAYLENGTH; |
363 | ptrarray = rtl8192de_mac_2tarray; | |
f30d7507 | 364 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n"); |
7274a8c2 CL |
365 | for (i = 0; i < arraylength; i = i + 2) |
366 | rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); | |
367 | if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { | |
368 | /* improve 2-stream TX EVM */ | |
369 | /* rtl_write_byte(rtlpriv, 0x14,0x71); */ | |
370 | /* AMPDU aggregation number 9 */ | |
371 | /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ | |
372 | rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); | |
373 | } else { | |
374 | /* 92D need to test to decide the num. */ | |
375 | rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); | |
376 | } | |
377 | return true; | |
378 | } | |
379 | ||
380 | static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) | |
381 | { | |
382 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
383 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
384 | ||
385 | /* RF Interface Sowrtware Control */ | |
386 | /* 16 LSBs if read 32-bit from 0x870 */ | |
387 | rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; | |
388 | /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ | |
389 | rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; | |
390 | /* 16 LSBs if read 32-bit from 0x874 */ | |
391 | rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; | |
392 | /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ | |
393 | ||
394 | rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; | |
395 | /* RF Interface Readback Value */ | |
396 | /* 16 LSBs if read 32-bit from 0x8E0 */ | |
397 | rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; | |
398 | /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ | |
399 | rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; | |
400 | /* 16 LSBs if read 32-bit from 0x8E4 */ | |
401 | rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; | |
402 | /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ | |
403 | rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; | |
404 | ||
405 | /* RF Interface Output (and Enable) */ | |
406 | /* 16 LSBs if read 32-bit from 0x860 */ | |
407 | rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; | |
408 | /* 16 LSBs if read 32-bit from 0x864 */ | |
409 | rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; | |
410 | ||
411 | /* RF Interface (Output and) Enable */ | |
412 | /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ | |
413 | rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; | |
414 | /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ | |
415 | rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; | |
416 | ||
417 | /* Addr of LSSI. Wirte RF register by driver */ | |
418 | /* LSSI Parameter */ | |
419 | rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = | |
420 | RFPGA0_XA_LSSIPARAMETER; | |
421 | rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = | |
422 | RFPGA0_XB_LSSIPARAMETER; | |
423 | ||
424 | /* RF parameter */ | |
425 | /* BB Band Select */ | |
426 | rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; | |
427 | rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; | |
428 | rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; | |
429 | rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; | |
430 | ||
431 | /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ | |
432 | /* Tx gain stage */ | |
433 | rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; | |
434 | /* Tx gain stage */ | |
435 | rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; | |
436 | /* Tx gain stage */ | |
437 | rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; | |
438 | /* Tx gain stage */ | |
439 | rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; | |
440 | ||
441 | /* Tranceiver A~D HSSI Parameter-1 */ | |
442 | /* wire control parameter1 */ | |
443 | rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; | |
444 | /* wire control parameter1 */ | |
445 | rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; | |
446 | ||
447 | /* Tranceiver A~D HSSI Parameter-2 */ | |
448 | /* wire control parameter2 */ | |
449 | rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; | |
450 | /* wire control parameter2 */ | |
451 | rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; | |
452 | ||
453 | /* RF switch Control */ | |
454 | /* TR/Ant switch control */ | |
da17fcff LF |
455 | rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; |
456 | rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; | |
457 | rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; | |
458 | rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; | |
7274a8c2 CL |
459 | |
460 | /* AGC control 1 */ | |
461 | rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; | |
462 | rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; | |
463 | rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; | |
464 | rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; | |
465 | ||
466 | /* AGC control 2 */ | |
467 | rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; | |
468 | rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; | |
469 | rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; | |
470 | rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; | |
471 | ||
472 | /* RX AFE control 1 */ | |
da17fcff LF |
473 | rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; |
474 | rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; | |
475 | rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; | |
476 | rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; | |
7274a8c2 CL |
477 | |
478 | /*RX AFE control 1 */ | |
479 | rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; | |
480 | rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; | |
481 | rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; | |
482 | rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; | |
483 | ||
484 | /* Tx AFE control 1 */ | |
b83faeda LF |
485 | rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; |
486 | rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; | |
487 | rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; | |
488 | rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; | |
7274a8c2 CL |
489 | |
490 | /* Tx AFE control 2 */ | |
b83faeda LF |
491 | rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; |
492 | rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; | |
493 | rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; | |
494 | rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; | |
7274a8c2 CL |
495 | |
496 | /* Tranceiver LSSI Readback SI mode */ | |
da17fcff LF |
497 | rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; |
498 | rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; | |
499 | rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; | |
500 | rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; | |
7274a8c2 CL |
501 | |
502 | /* Tranceiver LSSI Readback PI mode */ | |
da17fcff LF |
503 | rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; |
504 | rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; | |
7274a8c2 CL |
505 | } |
506 | ||
507 | static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, | |
508 | u8 configtype) | |
509 | { | |
510 | int i; | |
511 | u32 *phy_regarray_table; | |
512 | u32 *agctab_array_table = NULL; | |
513 | u32 *agctab_5garray_table; | |
514 | u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; | |
515 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
516 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
517 | ||
518 | /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */ | |
519 | if (rtlhal->interfaceindex == 0) { | |
520 | agctab_arraylen = AGCTAB_ARRAYLENGTH; | |
521 | agctab_array_table = rtl8192de_agctab_array; | |
522 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 523 | " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); |
7274a8c2 CL |
524 | } else { |
525 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
526 | agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; | |
527 | agctab_array_table = rtl8192de_agctab_2garray; | |
528 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 529 | " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); |
7274a8c2 CL |
530 | } else { |
531 | agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH; | |
532 | agctab_5garray_table = rtl8192de_agctab_5garray; | |
533 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 534 | " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); |
7274a8c2 CL |
535 | |
536 | } | |
537 | } | |
538 | phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; | |
539 | phy_regarray_table = rtl8192de_phy_reg_2tarray; | |
540 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 541 | " ===> phy:Rtl819XPHY_REG_Array_PG\n"); |
7274a8c2 CL |
542 | if (configtype == BASEBAND_CONFIG_PHY_REG) { |
543 | for (i = 0; i < phy_reg_arraylen; i = i + 2) { | |
25b13dbc LF |
544 | rtl_addr_delay(phy_regarray_table[i]); |
545 | rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, | |
7274a8c2 CL |
546 | phy_regarray_table[i + 1]); |
547 | udelay(1); | |
548 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 JP |
549 | "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", |
550 | phy_regarray_table[i], | |
551 | phy_regarray_table[i + 1]); | |
7274a8c2 CL |
552 | } |
553 | } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { | |
554 | if (rtlhal->interfaceindex == 0) { | |
555 | for (i = 0; i < agctab_arraylen; i = i + 2) { | |
556 | rtl_set_bbreg(hw, agctab_array_table[i], | |
25b13dbc | 557 | MASKDWORD, |
7274a8c2 CL |
558 | agctab_array_table[i + 1]); |
559 | /* Add 1us delay between BB/RF register | |
560 | * setting. */ | |
561 | udelay(1); | |
562 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
5856cd5b | 563 | "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", |
7274a8c2 | 564 | agctab_array_table[i], |
f30d7507 | 565 | agctab_array_table[i + 1]); |
7274a8c2 CL |
566 | } |
567 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 568 | "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n"); |
7274a8c2 CL |
569 | } else { |
570 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
571 | for (i = 0; i < agctab_arraylen; i = i + 2) { | |
572 | rtl_set_bbreg(hw, agctab_array_table[i], | |
25b13dbc | 573 | MASKDWORD, |
7274a8c2 CL |
574 | agctab_array_table[i + 1]); |
575 | /* Add 1us delay between BB/RF register | |
576 | * setting. */ | |
577 | udelay(1); | |
578 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
5856cd5b | 579 | "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", |
7274a8c2 | 580 | agctab_array_table[i], |
f30d7507 | 581 | agctab_array_table[i + 1]); |
7274a8c2 CL |
582 | } |
583 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 584 | "Load Rtl819XAGCTAB_2GArray\n"); |
7274a8c2 CL |
585 | } else { |
586 | for (i = 0; i < agctab_5garraylen; i = i + 2) { | |
587 | rtl_set_bbreg(hw, | |
588 | agctab_5garray_table[i], | |
25b13dbc | 589 | MASKDWORD, |
7274a8c2 CL |
590 | agctab_5garray_table[i + 1]); |
591 | /* Add 1us delay between BB/RF registeri | |
592 | * setting. */ | |
593 | udelay(1); | |
594 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
5856cd5b | 595 | "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", |
7274a8c2 | 596 | agctab_5garray_table[i], |
f30d7507 | 597 | agctab_5garray_table[i + 1]); |
7274a8c2 CL |
598 | } |
599 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 600 | "Load Rtl819XAGCTAB_5GArray\n"); |
7274a8c2 CL |
601 | } |
602 | } | |
603 | } | |
604 | return true; | |
605 | } | |
606 | ||
607 | static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, | |
608 | u32 regaddr, u32 bitmask, | |
609 | u32 data) | |
610 | { | |
611 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
612 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
02b6ab0a LF |
613 | int index; |
614 | ||
615 | if (regaddr == RTXAGC_A_RATE18_06) | |
616 | index = 0; | |
617 | else if (regaddr == RTXAGC_A_RATE54_24) | |
618 | index = 1; | |
619 | else if (regaddr == RTXAGC_A_CCK1_MCS32) | |
620 | index = 6; | |
621 | else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) | |
622 | index = 7; | |
623 | else if (regaddr == RTXAGC_A_MCS03_MCS00) | |
624 | index = 2; | |
625 | else if (regaddr == RTXAGC_A_MCS07_MCS04) | |
626 | index = 3; | |
627 | else if (regaddr == RTXAGC_A_MCS11_MCS08) | |
628 | index = 4; | |
629 | else if (regaddr == RTXAGC_A_MCS15_MCS12) | |
630 | index = 5; | |
631 | else if (regaddr == RTXAGC_B_RATE18_06) | |
632 | index = 8; | |
633 | else if (regaddr == RTXAGC_B_RATE54_24) | |
634 | index = 9; | |
635 | else if (regaddr == RTXAGC_B_CCK1_55_MCS32) | |
636 | index = 14; | |
637 | else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) | |
638 | index = 15; | |
639 | else if (regaddr == RTXAGC_B_MCS03_MCS00) | |
640 | index = 10; | |
641 | else if (regaddr == RTXAGC_B_MCS07_MCS04) | |
642 | index = 11; | |
643 | else if (regaddr == RTXAGC_B_MCS11_MCS08) | |
644 | index = 12; | |
645 | else if (regaddr == RTXAGC_B_MCS15_MCS12) | |
646 | index = 13; | |
647 | else | |
648 | return; | |
7274a8c2 | 649 | |
da17fcff | 650 | rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; |
02b6ab0a | 651 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, |
4f4378de | 652 | "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", |
02b6ab0a | 653 | rtlphy->pwrgroup_cnt, index, |
da17fcff | 654 | rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); |
02b6ab0a | 655 | if (index == 13) |
7274a8c2 | 656 | rtlphy->pwrgroup_cnt++; |
7274a8c2 CL |
657 | } |
658 | ||
659 | static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, | |
660 | u8 configtype) | |
661 | { | |
662 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
663 | int i; | |
664 | u32 *phy_regarray_table_pg; | |
665 | u16 phy_regarray_pg_len; | |
666 | ||
667 | phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; | |
668 | phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; | |
669 | if (configtype == BASEBAND_CONFIG_PHY_REG) { | |
670 | for (i = 0; i < phy_regarray_pg_len; i = i + 3) { | |
25b13dbc | 671 | rtl_addr_delay(phy_regarray_table_pg[i]); |
7274a8c2 CL |
672 | _rtl92d_store_pwrindex_diffrate_offset(hw, |
673 | phy_regarray_table_pg[i], | |
674 | phy_regarray_table_pg[i + 1], | |
675 | phy_regarray_table_pg[i + 2]); | |
676 | } | |
677 | } else { | |
678 | RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, | |
f30d7507 | 679 | "configtype != BaseBand_Config_PHY_REG\n"); |
7274a8c2 CL |
680 | } |
681 | return true; | |
682 | } | |
683 | ||
684 | static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw) | |
685 | { | |
686 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
687 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
688 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
689 | bool rtstatus = true; | |
690 | ||
f30d7507 | 691 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); |
7274a8c2 CL |
692 | rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, |
693 | BASEBAND_CONFIG_PHY_REG); | |
23677ce3 | 694 | if (!rtstatus) { |
b8c79f45 | 695 | pr_err("Write BB Reg Fail!!\n"); |
7274a8c2 CL |
696 | return false; |
697 | } | |
698 | ||
699 | /* if (rtlphy->rf_type == RF_1T2R) { | |
700 | * _rtl92c_phy_bb_config_1t(hw); | |
f30d7507 | 701 | * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); |
7274a8c2 CL |
702 | *} */ |
703 | ||
704 | if (rtlefuse->autoload_failflag == false) { | |
705 | rtlphy->pwrgroup_cnt = 0; | |
706 | rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw, | |
707 | BASEBAND_CONFIG_PHY_REG); | |
708 | } | |
23677ce3 | 709 | if (!rtstatus) { |
b8c79f45 | 710 | pr_err("BB_PG Reg Fail!!\n"); |
7274a8c2 CL |
711 | return false; |
712 | } | |
713 | rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, | |
714 | BASEBAND_CONFIG_AGC_TAB); | |
23677ce3 | 715 | if (!rtstatus) { |
b8c79f45 | 716 | pr_err("AGC Table Fail\n"); |
7274a8c2 CL |
717 | return false; |
718 | } | |
719 | rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, | |
720 | RFPGA0_XA_HSSIPARAMETER2, 0x200)); | |
721 | ||
722 | return true; | |
723 | } | |
724 | ||
725 | bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) | |
726 | { | |
727 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
728 | u16 regval; | |
729 | u32 regvaldw; | |
730 | u8 value; | |
731 | ||
732 | _rtl92d_phy_init_bb_rf_register_definition(hw); | |
733 | regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); | |
734 | rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, | |
735 | regval | BIT(13) | BIT(0) | BIT(1)); | |
736 | rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); | |
737 | rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); | |
738 | /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ | |
739 | value = rtl_read_byte(rtlpriv, REG_RF_CTRL); | |
740 | rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | | |
741 | RF_SDMRSTB); | |
742 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | | |
b83faeda | 743 | FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB); |
7274a8c2 CL |
744 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); |
745 | if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) { | |
746 | regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); | |
747 | rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); | |
748 | } | |
749 | ||
750 | return _rtl92d_phy_bb_config(hw); | |
751 | } | |
752 | ||
753 | bool rtl92d_phy_rf_config(struct ieee80211_hw *hw) | |
754 | { | |
755 | return rtl92d_phy_rf6052_config(hw); | |
756 | } | |
757 | ||
758 | bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, | |
759 | enum rf_content content, | |
760 | enum radio_path rfpath) | |
761 | { | |
eb8b27ad | 762 | int i; |
7274a8c2 CL |
763 | u32 *radioa_array_table; |
764 | u32 *radiob_array_table; | |
765 | u16 radioa_arraylen, radiob_arraylen; | |
766 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
767 | ||
768 | radioa_arraylen = RADIOA_2T_ARRAYLENGTH; | |
769 | radioa_array_table = rtl8192de_radioa_2tarray; | |
770 | radiob_arraylen = RADIOB_2T_ARRAYLENGTH; | |
771 | radiob_array_table = rtl8192de_radiob_2tarray; | |
772 | if (rtlpriv->efuse.internal_pa_5g[0]) { | |
773 | radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; | |
774 | radioa_array_table = rtl8192de_radioa_2t_int_paarray; | |
775 | } | |
776 | if (rtlpriv->efuse.internal_pa_5g[1]) { | |
777 | radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; | |
778 | radiob_array_table = rtl8192de_radiob_2t_int_paarray; | |
779 | } | |
780 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 781 | "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); |
7274a8c2 | 782 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, |
f30d7507 JP |
783 | "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); |
784 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); | |
7274a8c2 CL |
785 | |
786 | /* this only happens when DMDP, mac0 start on 2.4G, | |
787 | * mac1 start on 5G, mac 0 has to set phy0&phy1 | |
788 | * pathA or mac1 has to set phy0&phy1 pathA */ | |
789 | if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) { | |
790 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 791 | " ===> althougth Path A, we load radiob.txt\n"); |
7274a8c2 CL |
792 | radioa_arraylen = radiob_arraylen; |
793 | radioa_array_table = radiob_array_table; | |
794 | } | |
795 | switch (rfpath) { | |
796 | case RF90_PATH_A: | |
797 | for (i = 0; i < radioa_arraylen; i = i + 2) { | |
25b13dbc LF |
798 | rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], |
799 | RFREG_OFFSET_MASK, | |
800 | radioa_array_table[i + 1]); | |
7274a8c2 CL |
801 | } |
802 | break; | |
803 | case RF90_PATH_B: | |
804 | for (i = 0; i < radiob_arraylen; i = i + 2) { | |
25b13dbc LF |
805 | rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], |
806 | RFREG_OFFSET_MASK, | |
807 | radiob_array_table[i + 1]); | |
7274a8c2 CL |
808 | } |
809 | break; | |
810 | case RF90_PATH_C: | |
7274a8c2 | 811 | case RF90_PATH_D: |
b8c79f45 | 812 | pr_err("switch case %#x not processed\n", rfpath); |
7274a8c2 CL |
813 | break; |
814 | } | |
815 | return true; | |
816 | } | |
817 | ||
818 | void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) | |
819 | { | |
820 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
821 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
822 | ||
823 | rtlphy->default_initialgain[0] = | |
25b13dbc | 824 | (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); |
7274a8c2 | 825 | rtlphy->default_initialgain[1] = |
25b13dbc | 826 | (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); |
7274a8c2 | 827 | rtlphy->default_initialgain[2] = |
25b13dbc | 828 | (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); |
7274a8c2 | 829 | rtlphy->default_initialgain[3] = |
25b13dbc | 830 | (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); |
7274a8c2 | 831 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, |
f30d7507 JP |
832 | "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", |
833 | rtlphy->default_initialgain[0], | |
834 | rtlphy->default_initialgain[1], | |
835 | rtlphy->default_initialgain[2], | |
836 | rtlphy->default_initialgain[3]); | |
7274a8c2 | 837 | rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, |
25b13dbc | 838 | MASKBYTE0); |
7274a8c2 | 839 | rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, |
25b13dbc | 840 | MASKDWORD); |
7274a8c2 | 841 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, |
f30d7507 JP |
842 | "Default framesync (0x%x) = 0x%x\n", |
843 | ROFDM0_RXDETECTOR3, rtlphy->framesync); | |
7274a8c2 CL |
844 | } |
845 | ||
846 | static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, | |
847 | u8 *cckpowerlevel, u8 *ofdmpowerlevel) | |
848 | { | |
849 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
850 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
851 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
852 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
853 | u8 index = (channel - 1); | |
854 | ||
855 | /* 1. CCK */ | |
856 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
857 | /* RF-A */ | |
858 | cckpowerlevel[RF90_PATH_A] = | |
859 | rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; | |
860 | /* RF-B */ | |
861 | cckpowerlevel[RF90_PATH_B] = | |
862 | rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; | |
863 | } else { | |
864 | cckpowerlevel[RF90_PATH_A] = 0; | |
865 | cckpowerlevel[RF90_PATH_B] = 0; | |
866 | } | |
867 | /* 2. OFDM for 1S or 2S */ | |
868 | if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { | |
869 | /* Read HT 40 OFDM TX power */ | |
870 | ofdmpowerlevel[RF90_PATH_A] = | |
871 | rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; | |
872 | ofdmpowerlevel[RF90_PATH_B] = | |
873 | rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; | |
874 | } else if (rtlphy->rf_type == RF_2T2R) { | |
875 | /* Read HT 40 OFDM TX power */ | |
876 | ofdmpowerlevel[RF90_PATH_A] = | |
877 | rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; | |
878 | ofdmpowerlevel[RF90_PATH_B] = | |
879 | rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; | |
880 | } | |
881 | } | |
882 | ||
883 | static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, | |
884 | u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) | |
885 | { | |
886 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
887 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
888 | ||
889 | rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; | |
890 | rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; | |
891 | } | |
892 | ||
893 | static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) | |
894 | { | |
7274a8c2 CL |
895 | u8 place = chnl; |
896 | ||
897 | if (chnl > 14) { | |
bb6fa826 LF |
898 | for (place = 14; place < sizeof(channel5g); place++) { |
899 | if (channel5g[place] == chnl) { | |
7274a8c2 CL |
900 | place++; |
901 | break; | |
902 | } | |
903 | } | |
904 | } | |
905 | return place; | |
906 | } | |
907 | ||
908 | void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) | |
909 | { | |
910 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
911 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
912 | u8 cckpowerlevel[2], ofdmpowerlevel[2]; | |
913 | ||
23677ce3 | 914 | if (!rtlefuse->txpwr_fromeprom) |
7274a8c2 CL |
915 | return; |
916 | channel = _rtl92c_phy_get_rightchnlplace(channel); | |
917 | _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], | |
918 | &ofdmpowerlevel[0]); | |
919 | if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) | |
920 | _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], | |
921 | &ofdmpowerlevel[0]); | |
922 | if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) | |
923 | rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); | |
924 | rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); | |
925 | } | |
926 | ||
7274a8c2 CL |
927 | void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, |
928 | enum nl80211_channel_type ch_type) | |
929 | { | |
930 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
931 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
932 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
933 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
934 | unsigned long flag = 0; | |
935 | u8 reg_prsr_rsc; | |
936 | u8 reg_bw_opmode; | |
937 | ||
938 | if (rtlphy->set_bwmode_inprogress) | |
939 | return; | |
940 | if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { | |
941 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 942 | "FALSE driver sleep or unload\n"); |
7274a8c2 CL |
943 | return; |
944 | } | |
945 | rtlphy->set_bwmode_inprogress = true; | |
f30d7507 JP |
946 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", |
947 | rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? | |
948 | "20MHz" : "40MHz"); | |
7274a8c2 CL |
949 | reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); |
950 | reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); | |
951 | switch (rtlphy->current_chan_bw) { | |
952 | case HT_CHANNEL_WIDTH_20: | |
953 | reg_bw_opmode |= BW_OPMODE_20MHZ; | |
954 | rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); | |
955 | break; | |
956 | case HT_CHANNEL_WIDTH_20_40: | |
957 | reg_bw_opmode &= ~BW_OPMODE_20MHZ; | |
958 | rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); | |
959 | ||
960 | reg_prsr_rsc = (reg_prsr_rsc & 0x90) | | |
961 | (mac->cur_40_prime_sc << 5); | |
962 | rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); | |
963 | break; | |
964 | default: | |
b8c79f45 LF |
965 | pr_err("unknown bandwidth: %#X\n", |
966 | rtlphy->current_chan_bw); | |
7274a8c2 CL |
967 | break; |
968 | } | |
969 | switch (rtlphy->current_chan_bw) { | |
970 | case HT_CHANNEL_WIDTH_20: | |
971 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); | |
972 | rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); | |
973 | /* SET BIT10 BIT11 for receive cck */ | |
974 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | | |
975 | BIT(11), 3); | |
976 | break; | |
977 | case HT_CHANNEL_WIDTH_20_40: | |
978 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); | |
979 | rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); | |
980 | /* Set Control channel to upper or lower. | |
981 | * These settings are required only for 40MHz */ | |
982 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
983 | rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); | |
984 | rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, | |
985 | (mac->cur_40_prime_sc >> 1)); | |
986 | rtl92d_release_cckandrw_pagea_ctl(hw, &flag); | |
987 | } | |
988 | rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); | |
989 | /* SET BIT10 BIT11 for receive cck */ | |
990 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | | |
991 | BIT(11), 0); | |
992 | rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), | |
993 | (mac->cur_40_prime_sc == | |
994 | HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); | |
995 | break; | |
996 | default: | |
b8c79f45 LF |
997 | pr_err("unknown bandwidth: %#X\n", |
998 | rtlphy->current_chan_bw); | |
7274a8c2 CL |
999 | break; |
1000 | ||
1001 | } | |
1002 | rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); | |
1003 | rtlphy->set_bwmode_inprogress = false; | |
f30d7507 | 1004 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); |
7274a8c2 CL |
1005 | } |
1006 | ||
1007 | static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) | |
1008 | { | |
1009 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); | |
1010 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); | |
25b13dbc | 1011 | rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); |
7274a8c2 CL |
1012 | rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); |
1013 | } | |
1014 | ||
1015 | static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) | |
1016 | { | |
1017 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1018 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
eb8b27ad | 1019 | u8 value8; |
7274a8c2 | 1020 | |
f30d7507 | 1021 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); |
7274a8c2 CL |
1022 | rtlhal->bandset = band; |
1023 | rtlhal->current_bandtype = band; | |
1024 | if (IS_92D_SINGLEPHY(rtlhal->version)) | |
1025 | rtlhal->bandset = BAND_ON_BOTH; | |
1026 | /* stop RX/Tx */ | |
1027 | _rtl92d_phy_stop_trx_before_changeband(hw); | |
1028 | /* reconfig BB/RF according to wireless mode */ | |
1029 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
1030 | /* BB & RF Config */ | |
f30d7507 | 1031 | RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); |
7274a8c2 CL |
1032 | if (rtlhal->interfaceindex == 1) |
1033 | _rtl92d_phy_config_bb_with_headerfile(hw, | |
1034 | BASEBAND_CONFIG_AGC_TAB); | |
1035 | } else { | |
1036 | /* 5G band */ | |
f30d7507 | 1037 | RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); |
7274a8c2 CL |
1038 | if (rtlhal->interfaceindex == 1) |
1039 | _rtl92d_phy_config_bb_with_headerfile(hw, | |
1040 | BASEBAND_CONFIG_AGC_TAB); | |
1041 | } | |
1042 | rtl92d_update_bbrf_configuration(hw); | |
1043 | if (rtlhal->current_bandtype == BAND_ON_2_4G) | |
1044 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); | |
1045 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); | |
1046 | ||
1047 | /* 20M BW. */ | |
1048 | /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ | |
1049 | rtlhal->reloadtxpowerindex = true; | |
1050 | /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ | |
1051 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
1052 | value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == | |
1053 | 0 ? REG_MAC0 : REG_MAC1)); | |
1054 | value8 |= BIT(1); | |
1055 | rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == | |
1056 | 0 ? REG_MAC0 : REG_MAC1), value8); | |
1057 | } else { | |
1058 | value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == | |
1059 | 0 ? REG_MAC0 : REG_MAC1)); | |
1060 | value8 &= (~BIT(1)); | |
1061 | rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == | |
1062 | 0 ? REG_MAC0 : REG_MAC1), value8); | |
1063 | } | |
eb8b27ad | 1064 | mdelay(1); |
f30d7507 | 1065 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); |
7274a8c2 CL |
1066 | } |
1067 | ||
1068 | static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, | |
1069 | u8 channel, u8 rfpath) | |
1070 | { | |
1071 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1072 | u32 imr_num = MAX_RF_IMR_INDEX; | |
25b13dbc | 1073 | u32 rfmask = RFREG_OFFSET_MASK; |
7274a8c2 CL |
1074 | u8 group, i; |
1075 | unsigned long flag = 0; | |
1076 | ||
f30d7507 | 1077 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); |
7274a8c2 | 1078 | if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { |
f30d7507 | 1079 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); |
7274a8c2 CL |
1080 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); |
1081 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); | |
1082 | /* fc area 0xd2c */ | |
1083 | if (channel > 99) | |
1084 | rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | | |
1085 | BIT(14), 2); | |
1086 | else | |
1087 | rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | | |
1088 | BIT(14), 1); | |
1089 | /* leave 0 for channel1-14. */ | |
1090 | group = channel <= 64 ? 1 : 2; | |
1091 | imr_num = MAX_RF_IMR_INDEX_NORMAL; | |
1092 | for (i = 0; i < imr_num; i++) | |
1093 | rtl_set_rfreg(hw, (enum radio_path)rfpath, | |
1094 | rf_reg_for_5g_swchnl_normal[i], rfmask, | |
1095 | rf_imr_param_normal[0][group][i]); | |
1096 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); | |
1097 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); | |
1098 | } else { | |
1099 | /* G band. */ | |
1100 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, | |
f30d7507 JP |
1101 | "Load RF IMR parameters for G band. IMR already setting %d\n", |
1102 | rtlpriv->rtlhal.load_imrandiqk_setting_for2g); | |
1103 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); | |
7274a8c2 CL |
1104 | if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { |
1105 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, | |
f30d7507 JP |
1106 | "Load RF IMR parameters for G band. %d\n", |
1107 | rfpath); | |
7274a8c2 CL |
1108 | rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); |
1109 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); | |
1110 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, | |
1111 | 0x00f00000, 0xf); | |
1112 | imr_num = MAX_RF_IMR_INDEX_NORMAL; | |
1113 | for (i = 0; i < imr_num; i++) { | |
1114 | rtl_set_rfreg(hw, (enum radio_path)rfpath, | |
1115 | rf_reg_for_5g_swchnl_normal[i], | |
25b13dbc | 1116 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
1117 | rf_imr_param_normal[0][0][i]); |
1118 | } | |
1119 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, | |
1120 | 0x00f00000, 0); | |
1121 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); | |
1122 | rtl92d_release_cckandrw_pagea_ctl(hw, &flag); | |
1123 | } | |
1124 | } | |
f30d7507 | 1125 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); |
7274a8c2 CL |
1126 | } |
1127 | ||
1128 | static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, | |
1129 | u8 rfpath, u32 *pu4_regval) | |
1130 | { | |
1131 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1132 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1133 | struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; | |
1134 | ||
f30d7507 | 1135 | RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); |
7274a8c2 CL |
1136 | /*----Store original RFENV control type----*/ |
1137 | switch (rfpath) { | |
1138 | case RF90_PATH_A: | |
1139 | case RF90_PATH_C: | |
1140 | *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); | |
1141 | break; | |
1142 | case RF90_PATH_B: | |
1143 | case RF90_PATH_D: | |
1144 | *pu4_regval = | |
1145 | rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); | |
1146 | break; | |
1147 | } | |
1148 | /*----Set RF_ENV enable----*/ | |
1149 | rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); | |
1150 | udelay(1); | |
1151 | /*----Set RF_ENV output high----*/ | |
1152 | rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); | |
1153 | udelay(1); | |
1154 | /* Set bit number of Address and Data for RF register */ | |
1155 | /* Set 1 to 4 bits for 8255 */ | |
1156 | rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); | |
1157 | udelay(1); | |
1158 | /*Set 0 to 12 bits for 8255 */ | |
1159 | rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); | |
1160 | udelay(1); | |
f30d7507 | 1161 | RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); |
7274a8c2 CL |
1162 | } |
1163 | ||
1164 | static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, | |
1165 | u32 *pu4_regval) | |
1166 | { | |
1167 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1168 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1169 | struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; | |
1170 | ||
f30d7507 | 1171 | RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); |
84d216c6 | 1172 | /*----Restore RFENV control type----*/ |
7274a8c2 CL |
1173 | switch (rfpath) { |
1174 | case RF90_PATH_A: | |
1175 | case RF90_PATH_C: | |
1176 | rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); | |
1177 | break; | |
1178 | case RF90_PATH_B: | |
1179 | case RF90_PATH_D: | |
1180 | rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, | |
1181 | *pu4_regval); | |
1182 | break; | |
1183 | } | |
f30d7507 | 1184 | RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); |
7274a8c2 CL |
1185 | } |
1186 | ||
1187 | static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) | |
1188 | { | |
1189 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1190 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1191 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
1192 | u8 path = rtlhal->current_bandtype == | |
1193 | BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B; | |
1194 | u8 index = 0, i = 0, rfpath = RF90_PATH_A; | |
1195 | bool need_pwr_down = false, internal_pa = false; | |
1196 | u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; | |
1197 | ||
f30d7507 | 1198 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); |
7274a8c2 CL |
1199 | /* config path A for 5G */ |
1200 | if (rtlhal->current_bandtype == BAND_ON_5G) { | |
f30d7507 | 1201 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); |
7274a8c2 | 1202 | u4tmp = curveindex_5g[channel - 1]; |
4c48869f JP |
1203 | RTPRINT(rtlpriv, FINIT, INIT_IQK, |
1204 | "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); | |
7274a8c2 CL |
1205 | for (i = 0; i < RF_CHNL_NUM_5G; i++) { |
1206 | if (channel == rf_chnl_5g[i] && channel <= 140) | |
1207 | index = 0; | |
1208 | } | |
1209 | for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { | |
1210 | if (channel == rf_chnl_5g_40m[i] && channel <= 140) | |
1211 | index = 1; | |
1212 | } | |
1213 | if (channel == 149 || channel == 155 || channel == 161) | |
1214 | index = 2; | |
1215 | else if (channel == 151 || channel == 153 || channel == 163 | |
1216 | || channel == 165) | |
1217 | index = 3; | |
1218 | else if (channel == 157 || channel == 159) | |
1219 | index = 4; | |
1220 | ||
1221 | if (rtlhal->macphymode == DUALMAC_DUALPHY | |
1222 | && rtlhal->interfaceindex == 1) { | |
1223 | need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false); | |
1224 | rtlhal->during_mac1init_radioa = true; | |
1225 | /* asume no this case */ | |
1226 | if (need_pwr_down) | |
1227 | _rtl92d_phy_enable_rf_env(hw, path, | |
1228 | &u4regvalue); | |
1229 | } | |
1230 | for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { | |
1231 | if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { | |
1232 | rtl_set_rfreg(hw, (enum radio_path)path, | |
1233 | rf_reg_for_c_cut_5g[i], | |
25b13dbc | 1234 | RFREG_OFFSET_MASK, 0xE439D); |
7274a8c2 CL |
1235 | } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { |
1236 | u4tmp2 = (rf_reg_pram_c_5g[index][i] & | |
1237 | 0x7FF) | (u4tmp << 11); | |
1238 | if (channel == 36) | |
1239 | u4tmp2 &= ~(BIT(7) | BIT(6)); | |
1240 | rtl_set_rfreg(hw, (enum radio_path)path, | |
1241 | rf_reg_for_c_cut_5g[i], | |
25b13dbc | 1242 | RFREG_OFFSET_MASK, u4tmp2); |
7274a8c2 CL |
1243 | } else { |
1244 | rtl_set_rfreg(hw, (enum radio_path)path, | |
1245 | rf_reg_for_c_cut_5g[i], | |
25b13dbc | 1246 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
1247 | rf_reg_pram_c_5g[index][i]); |
1248 | } | |
1249 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, | |
f30d7507 JP |
1250 | "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", |
1251 | rf_reg_for_c_cut_5g[i], | |
1252 | rf_reg_pram_c_5g[index][i], | |
1253 | path, index, | |
1254 | rtl_get_rfreg(hw, (enum radio_path)path, | |
1255 | rf_reg_for_c_cut_5g[i], | |
25b13dbc | 1256 | RFREG_OFFSET_MASK)); |
7274a8c2 CL |
1257 | } |
1258 | if (need_pwr_down) | |
1259 | _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); | |
1260 | if (rtlhal->during_mac1init_radioa) | |
1261 | rtl92d_phy_powerdown_anotherphy(hw, false); | |
1262 | if (channel < 149) | |
1263 | value = 0x07; | |
1264 | else if (channel >= 149) | |
1265 | value = 0x02; | |
1266 | if (channel >= 36 && channel <= 64) | |
1267 | index = 0; | |
1268 | else if (channel >= 100 && channel <= 140) | |
1269 | index = 1; | |
1270 | else | |
1271 | index = 2; | |
1272 | for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; | |
1273 | rfpath++) { | |
1274 | if (rtlhal->macphymode == DUALMAC_DUALPHY && | |
1275 | rtlhal->interfaceindex == 1) /* MAC 1 5G */ | |
1276 | internal_pa = rtlpriv->efuse.internal_pa_5g[1]; | |
1277 | else | |
1278 | internal_pa = | |
1279 | rtlpriv->efuse.internal_pa_5g[rfpath]; | |
1280 | if (internal_pa) { | |
1281 | for (i = 0; | |
1282 | i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; | |
1283 | i++) { | |
1284 | rtl_set_rfreg(hw, rfpath, | |
1285 | rf_for_c_cut_5g_internal_pa[i], | |
25b13dbc | 1286 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
1287 | rf_pram_c_5g_int_pa[index][i]); |
1288 | RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, | |
f30d7507 | 1289 | "offset 0x%x value 0x%x path %d index %d\n", |
7274a8c2 CL |
1290 | rf_for_c_cut_5g_internal_pa[i], |
1291 | rf_pram_c_5g_int_pa[index][i], | |
f30d7507 | 1292 | rfpath, index); |
7274a8c2 CL |
1293 | } |
1294 | } else { | |
1295 | rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, | |
1296 | mask, value); | |
1297 | } | |
1298 | } | |
1299 | } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
f30d7507 | 1300 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); |
7274a8c2 | 1301 | u4tmp = curveindex_2g[channel - 1]; |
4c48869f JP |
1302 | RTPRINT(rtlpriv, FINIT, INIT_IQK, |
1303 | "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); | |
7274a8c2 CL |
1304 | if (channel == 1 || channel == 2 || channel == 4 || channel == 9 |
1305 | || channel == 10 || channel == 11 || channel == 12) | |
1306 | index = 0; | |
1307 | else if (channel == 3 || channel == 13 || channel == 14) | |
1308 | index = 1; | |
1309 | else if (channel >= 5 && channel <= 8) | |
1310 | index = 2; | |
1311 | if (rtlhal->macphymode == DUALMAC_DUALPHY) { | |
1312 | path = RF90_PATH_A; | |
1313 | if (rtlhal->interfaceindex == 0) { | |
1314 | need_pwr_down = | |
1315 | rtl92d_phy_enable_anotherphy(hw, true); | |
1316 | rtlhal->during_mac0init_radiob = true; | |
1317 | ||
1318 | if (need_pwr_down) | |
1319 | _rtl92d_phy_enable_rf_env(hw, path, | |
1320 | &u4regvalue); | |
1321 | } | |
1322 | } | |
1323 | for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { | |
1324 | if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) | |
1325 | rtl_set_rfreg(hw, (enum radio_path)path, | |
1326 | rf_reg_for_c_cut_2g[i], | |
25b13dbc | 1327 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
1328 | (rf_reg_param_for_c_cut_2g[index][i] | |
1329 | BIT(17))); | |
1330 | else | |
1331 | rtl_set_rfreg(hw, (enum radio_path)path, | |
1332 | rf_reg_for_c_cut_2g[i], | |
25b13dbc | 1333 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
1334 | rf_reg_param_for_c_cut_2g |
1335 | [index][i]); | |
1336 | RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, | |
f30d7507 JP |
1337 | "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", |
1338 | rf_reg_for_c_cut_2g[i], | |
1339 | rf_reg_param_for_c_cut_2g[index][i], | |
1340 | rf_reg_mask_for_c_cut_2g[i], path, index, | |
1341 | rtl_get_rfreg(hw, (enum radio_path)path, | |
1342 | rf_reg_for_c_cut_2g[i], | |
25b13dbc | 1343 | RFREG_OFFSET_MASK)); |
7274a8c2 CL |
1344 | } |
1345 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f JP |
1346 | "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", |
1347 | rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); | |
7274a8c2 CL |
1348 | |
1349 | rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, | |
25b13dbc | 1350 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
1351 | rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); |
1352 | if (need_pwr_down) | |
1353 | _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); | |
1354 | if (rtlhal->during_mac0init_radiob) | |
1355 | rtl92d_phy_powerdown_anotherphy(hw, true); | |
1356 | } | |
f30d7507 | 1357 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); |
7274a8c2 CL |
1358 | } |
1359 | ||
1360 | u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) | |
1361 | { | |
1362 | u8 channel_all[59] = { | |
1363 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
1364 | 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, | |
1365 | 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, | |
1366 | 114, 116, 118, 120, 122, 124, 126, 128, 130, | |
1367 | 132, 134, 136, 138, 140, 149, 151, 153, 155, | |
1368 | 157, 159, 161, 163, 165 | |
1369 | }; | |
1370 | u8 place = chnl; | |
1371 | ||
1372 | if (chnl > 14) { | |
1373 | for (place = 14; place < sizeof(channel_all); place++) { | |
1374 | if (channel_all[place] == chnl) | |
1375 | return place - 13; | |
1376 | } | |
1377 | } | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | #define MAX_TOLERANCE 5 | |
1383 | #define IQK_DELAY_TIME 1 /* ms */ | |
1384 | #define MAX_TOLERANCE_92D 3 | |
1385 | ||
1386 | /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ | |
1387 | static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) | |
1388 | { | |
1389 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1390 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1391 | u32 regeac, rege94, rege9c, regea4; | |
1392 | u8 result = 0; | |
1393 | ||
4c48869f | 1394 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); |
7274a8c2 | 1395 | /* path-A IQK setting */ |
4c48869f | 1396 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); |
7274a8c2 | 1397 | if (rtlhal->interfaceindex == 0) { |
25b13dbc LF |
1398 | rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); |
1399 | rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); | |
7274a8c2 | 1400 | } else { |
25b13dbc LF |
1401 | rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); |
1402 | rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); | |
7274a8c2 | 1403 | } |
25b13dbc LF |
1404 | rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); |
1405 | rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); | |
7274a8c2 CL |
1406 | /* path-B IQK setting */ |
1407 | if (configpathb) { | |
25b13dbc LF |
1408 | rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); |
1409 | rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); | |
1410 | rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); | |
1411 | rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); | |
7274a8c2 CL |
1412 | } |
1413 | /* LO calibration setting */ | |
4c48869f | 1414 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); |
25b13dbc | 1415 | rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); |
7274a8c2 | 1416 | /* One shot, path A LOK & IQK */ |
4c48869f | 1417 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); |
25b13dbc LF |
1418 | rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); |
1419 | rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); | |
7274a8c2 CL |
1420 | /* delay x ms */ |
1421 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f JP |
1422 | "Delay %d ms for One shot, path A LOK & IQK\n", |
1423 | IQK_DELAY_TIME); | |
faeef8ac | 1424 | mdelay(IQK_DELAY_TIME); |
7274a8c2 | 1425 | /* Check failed */ |
25b13dbc | 1426 | regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); |
4c48869f | 1427 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); |
25b13dbc | 1428 | rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); |
4c48869f | 1429 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); |
25b13dbc | 1430 | rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); |
4c48869f | 1431 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); |
25b13dbc | 1432 | regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); |
4c48869f | 1433 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); |
7274a8c2 CL |
1434 | if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && |
1435 | (((rege9c & 0x03FF0000) >> 16) != 0x42)) | |
1436 | result |= 0x01; | |
1437 | else /* if Tx not OK, ignore Rx */ | |
1438 | return result; | |
1439 | /* if Tx is OK, check whether Rx is OK */ | |
1440 | if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && | |
1441 | (((regeac & 0x03FF0000) >> 16) != 0x36)) | |
1442 | result |= 0x02; | |
1443 | else | |
4c48869f | 1444 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); |
7274a8c2 CL |
1445 | return result; |
1446 | } | |
1447 | ||
1448 | /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ | |
1449 | static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, | |
1450 | bool configpathb) | |
1451 | { | |
1452 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1453 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1454 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1455 | u32 regeac, rege94, rege9c, regea4; | |
1456 | u8 result = 0; | |
1457 | u8 i; | |
1458 | u8 retrycount = 2; | |
b83faeda | 1459 | u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27); |
7274a8c2 CL |
1460 | |
1461 | if (rtlhal->interfaceindex == 1) { /* PHY1 */ | |
b83faeda LF |
1462 | TXOKBIT = BIT(31); |
1463 | RXOKBIT = BIT(30); | |
7274a8c2 | 1464 | } |
4c48869f | 1465 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); |
7274a8c2 | 1466 | /* path-A IQK setting */ |
4c48869f | 1467 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); |
25b13dbc LF |
1468 | rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); |
1469 | rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); | |
1470 | rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); | |
1471 | rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); | |
7274a8c2 CL |
1472 | /* path-B IQK setting */ |
1473 | if (configpathb) { | |
25b13dbc LF |
1474 | rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); |
1475 | rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); | |
1476 | rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); | |
1477 | rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); | |
7274a8c2 CL |
1478 | } |
1479 | /* LO calibration setting */ | |
4c48869f | 1480 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); |
25b13dbc | 1481 | rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); |
7274a8c2 | 1482 | /* path-A PA on */ |
25b13dbc LF |
1483 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); |
1484 | rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); | |
7274a8c2 CL |
1485 | for (i = 0; i < retrycount; i++) { |
1486 | /* One shot, path A LOK & IQK */ | |
1487 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1488 | "One shot, path A LOK & IQK!\n"); |
25b13dbc LF |
1489 | rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); |
1490 | rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); | |
7274a8c2 CL |
1491 | /* delay x ms */ |
1492 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f JP |
1493 | "Delay %d ms for One shot, path A LOK & IQK.\n", |
1494 | IQK_DELAY_TIME); | |
faeef8ac | 1495 | mdelay(IQK_DELAY_TIME * 10); |
7274a8c2 | 1496 | /* Check failed */ |
25b13dbc | 1497 | regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); |
4c48869f | 1498 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); |
25b13dbc | 1499 | rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); |
4c48869f | 1500 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); |
25b13dbc | 1501 | rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); |
4c48869f | 1502 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); |
25b13dbc | 1503 | regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); |
4c48869f | 1504 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); |
b83faeda | 1505 | if (!(regeac & TXOKBIT) && |
7274a8c2 CL |
1506 | (((rege94 & 0x03FF0000) >> 16) != 0x142)) { |
1507 | result |= 0x01; | |
1508 | } else { /* if Tx not OK, ignore Rx */ | |
1509 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1510 | "Path A Tx IQK fail!!\n"); |
7274a8c2 CL |
1511 | continue; |
1512 | } | |
1513 | ||
1514 | /* if Tx is OK, check whether Rx is OK */ | |
b83faeda | 1515 | if (!(regeac & RXOKBIT) && |
7274a8c2 CL |
1516 | (((regea4 & 0x03FF0000) >> 16) != 0x132)) { |
1517 | result |= 0x02; | |
1518 | break; | |
1519 | } else { | |
1520 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1521 | "Path A Rx IQK fail!!\n"); |
7274a8c2 CL |
1522 | } |
1523 | } | |
1524 | /* path A PA off */ | |
25b13dbc | 1525 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, |
7274a8c2 | 1526 | rtlphy->iqk_bb_backup[0]); |
25b13dbc | 1527 | rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, |
7274a8c2 CL |
1528 | rtlphy->iqk_bb_backup[1]); |
1529 | return result; | |
1530 | } | |
1531 | ||
1532 | /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ | |
1533 | static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw) | |
1534 | { | |
1535 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1536 | u32 regeac, regeb4, regebc, regec4, regecc; | |
1537 | u8 result = 0; | |
1538 | ||
4c48869f | 1539 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); |
7274a8c2 | 1540 | /* One shot, path B LOK & IQK */ |
4c48869f | 1541 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); |
25b13dbc LF |
1542 | rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); |
1543 | rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); | |
7274a8c2 CL |
1544 | /* delay x ms */ |
1545 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1546 | "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); |
faeef8ac | 1547 | mdelay(IQK_DELAY_TIME); |
7274a8c2 | 1548 | /* Check failed */ |
25b13dbc | 1549 | regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); |
4c48869f | 1550 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); |
25b13dbc | 1551 | regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); |
4c48869f | 1552 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); |
25b13dbc | 1553 | regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); |
4c48869f | 1554 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); |
25b13dbc | 1555 | regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); |
4c48869f | 1556 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); |
25b13dbc | 1557 | regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); |
4c48869f | 1558 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); |
7274a8c2 CL |
1559 | if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && |
1560 | (((regebc & 0x03FF0000) >> 16) != 0x42)) | |
1561 | result |= 0x01; | |
1562 | else | |
1563 | return result; | |
1564 | if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && | |
1565 | (((regecc & 0x03FF0000) >> 16) != 0x36)) | |
1566 | result |= 0x02; | |
1567 | else | |
4c48869f | 1568 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); |
7274a8c2 CL |
1569 | return result; |
1570 | } | |
1571 | ||
1572 | /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ | |
1573 | static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) | |
1574 | { | |
1575 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1576 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1577 | u32 regeac, regeb4, regebc, regec4, regecc; | |
1578 | u8 result = 0; | |
1579 | u8 i; | |
1580 | u8 retrycount = 2; | |
1581 | ||
4c48869f | 1582 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); |
7274a8c2 | 1583 | /* path-A IQK setting */ |
4c48869f | 1584 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); |
25b13dbc LF |
1585 | rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); |
1586 | rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); | |
1587 | rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); | |
1588 | rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); | |
7274a8c2 CL |
1589 | |
1590 | /* path-B IQK setting */ | |
25b13dbc LF |
1591 | rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); |
1592 | rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); | |
1593 | rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); | |
1594 | rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); | |
7274a8c2 CL |
1595 | |
1596 | /* LO calibration setting */ | |
4c48869f | 1597 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); |
25b13dbc | 1598 | rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); |
7274a8c2 CL |
1599 | |
1600 | /* path-B PA on */ | |
25b13dbc LF |
1601 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); |
1602 | rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); | |
7274a8c2 CL |
1603 | |
1604 | for (i = 0; i < retrycount; i++) { | |
1605 | /* One shot, path B LOK & IQK */ | |
1606 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1607 | "One shot, path A LOK & IQK!\n"); |
25b13dbc LF |
1608 | rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); |
1609 | rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); | |
7274a8c2 CL |
1610 | |
1611 | /* delay x ms */ | |
1612 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1613 | "Delay %d ms for One shot, path B LOK & IQK.\n", 10); |
faeef8ac | 1614 | mdelay(IQK_DELAY_TIME * 10); |
7274a8c2 CL |
1615 | |
1616 | /* Check failed */ | |
25b13dbc | 1617 | regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); |
4c48869f | 1618 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); |
25b13dbc | 1619 | regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); |
4c48869f | 1620 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); |
25b13dbc | 1621 | regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); |
4c48869f | 1622 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); |
25b13dbc | 1623 | regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); |
4c48869f | 1624 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); |
25b13dbc | 1625 | regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); |
4c48869f | 1626 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); |
7274a8c2 CL |
1627 | if (!(regeac & BIT(31)) && |
1628 | (((regeb4 & 0x03FF0000) >> 16) != 0x142)) | |
1629 | result |= 0x01; | |
1630 | else | |
1631 | continue; | |
1632 | if (!(regeac & BIT(30)) && | |
1633 | (((regec4 & 0x03FF0000) >> 16) != 0x132)) { | |
1634 | result |= 0x02; | |
1635 | break; | |
1636 | } else { | |
1637 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1638 | "Path B Rx IQK fail!!\n"); |
7274a8c2 CL |
1639 | } |
1640 | } | |
1641 | ||
1642 | /* path B PA off */ | |
25b13dbc | 1643 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, |
7274a8c2 | 1644 | rtlphy->iqk_bb_backup[0]); |
25b13dbc | 1645 | rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, |
7274a8c2 CL |
1646 | rtlphy->iqk_bb_backup[2]); |
1647 | return result; | |
1648 | } | |
1649 | ||
1650 | static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, | |
1651 | u32 *adda_reg, u32 *adda_backup, | |
1652 | u32 regnum) | |
1653 | { | |
1654 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1655 | u32 i; | |
1656 | ||
4c48869f | 1657 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); |
7274a8c2 | 1658 | for (i = 0; i < regnum; i++) |
25b13dbc | 1659 | adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); |
7274a8c2 CL |
1660 | } |
1661 | ||
1662 | static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, | |
1663 | u32 *macreg, u32 *macbackup) | |
1664 | { | |
1665 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1666 | u32 i; | |
1667 | ||
4c48869f | 1668 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); |
7274a8c2 CL |
1669 | for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) |
1670 | macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); | |
1671 | macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); | |
1672 | } | |
1673 | ||
1674 | static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, | |
1675 | u32 *adda_reg, u32 *adda_backup, | |
1676 | u32 regnum) | |
1677 | { | |
1678 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1679 | u32 i; | |
1680 | ||
1681 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1682 | "Reload ADDA power saving parameters !\n"); |
7274a8c2 | 1683 | for (i = 0; i < regnum; i++) |
25b13dbc | 1684 | rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); |
7274a8c2 CL |
1685 | } |
1686 | ||
1687 | static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, | |
1688 | u32 *macreg, u32 *macbackup) | |
1689 | { | |
1690 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1691 | u32 i; | |
1692 | ||
4c48869f | 1693 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); |
7274a8c2 CL |
1694 | for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) |
1695 | rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); | |
1696 | rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); | |
1697 | } | |
1698 | ||
1699 | static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, | |
1700 | u32 *adda_reg, bool patha_on, bool is2t) | |
1701 | { | |
1702 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1703 | u32 pathon; | |
1704 | u32 i; | |
1705 | ||
4c48869f | 1706 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); |
7274a8c2 CL |
1707 | pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; |
1708 | if (patha_on) | |
1709 | pathon = rtlpriv->rtlhal.interfaceindex == 0 ? | |
1710 | 0x04db25a4 : 0x0b1b25a4; | |
1711 | for (i = 0; i < IQK_ADDA_REG_NUM; i++) | |
25b13dbc | 1712 | rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); |
7274a8c2 CL |
1713 | } |
1714 | ||
1715 | static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, | |
1716 | u32 *macreg, u32 *macbackup) | |
1717 | { | |
1718 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1719 | u32 i; | |
1720 | ||
4c48869f | 1721 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); |
7274a8c2 CL |
1722 | rtl_write_byte(rtlpriv, macreg[0], 0x3F); |
1723 | ||
1724 | for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) | |
1725 | rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & | |
1726 | (~BIT(3)))); | |
1727 | rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); | |
1728 | } | |
1729 | ||
1730 | static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) | |
1731 | { | |
1732 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
4c48869f | 1733 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); |
7274a8c2 | 1734 | |
25b13dbc LF |
1735 | rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); |
1736 | rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); | |
1737 | rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); | |
7274a8c2 CL |
1738 | } |
1739 | ||
1740 | static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) | |
1741 | { | |
1742 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1743 | u32 mode; | |
1744 | ||
1745 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1746 | "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); |
7274a8c2 | 1747 | mode = pi_mode ? 0x01000100 : 0x01000000; |
25b13dbc LF |
1748 | rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); |
1749 | rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); | |
7274a8c2 CL |
1750 | } |
1751 | ||
1752 | static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], | |
1753 | u8 t, bool is2t) | |
1754 | { | |
1755 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1756 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1757 | u32 i; | |
1758 | u8 patha_ok, pathb_ok; | |
1759 | static u32 adda_reg[IQK_ADDA_REG_NUM] = { | |
1760 | RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, | |
1761 | 0xe78, 0xe7c, 0xe80, 0xe84, | |
1762 | 0xe88, 0xe8c, 0xed0, 0xed4, | |
1763 | 0xed8, 0xedc, 0xee0, 0xeec | |
1764 | }; | |
1765 | static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { | |
1766 | 0x522, 0x550, 0x551, 0x040 | |
1767 | }; | |
1768 | static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { | |
1769 | RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, | |
1770 | RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, | |
1771 | RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, | |
1772 | RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, | |
1773 | ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 | |
1774 | }; | |
1775 | const u32 retrycount = 2; | |
1776 | u32 bbvalue; | |
1777 | ||
4c48869f | 1778 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); |
7274a8c2 | 1779 | if (t == 0) { |
25b13dbc | 1780 | bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); |
4c48869f JP |
1781 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); |
1782 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", | |
1783 | is2t ? "2T2R" : "1T1R"); | |
7274a8c2 CL |
1784 | |
1785 | /* Save ADDA parameters, turn Path A ADDA on */ | |
1786 | _rtl92d_phy_save_adda_registers(hw, adda_reg, | |
1787 | rtlphy->adda_backup, IQK_ADDA_REG_NUM); | |
1788 | _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, | |
1789 | rtlphy->iqk_mac_backup); | |
1790 | _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, | |
1791 | rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); | |
1792 | } | |
1793 | _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); | |
1794 | if (t == 0) | |
1795 | rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, | |
1796 | RFPGA0_XA_HSSIPARAMETER1, BIT(8)); | |
1797 | ||
1798 | /* Switch BB to PI mode to do IQ Calibration. */ | |
1799 | if (!rtlphy->rfpi_enable) | |
1800 | _rtl92d_phy_pimode_switch(hw, true); | |
1801 | ||
1802 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); | |
25b13dbc LF |
1803 | rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); |
1804 | rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); | |
1805 | rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); | |
7274a8c2 CL |
1806 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); |
1807 | if (is2t) { | |
25b13dbc | 1808 | rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, |
7274a8c2 | 1809 | 0x00010000); |
25b13dbc | 1810 | rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, |
7274a8c2 CL |
1811 | 0x00010000); |
1812 | } | |
1813 | /* MAC settings */ | |
1814 | _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, | |
1815 | rtlphy->iqk_mac_backup); | |
1816 | /* Page B init */ | |
25b13dbc | 1817 | rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); |
7274a8c2 | 1818 | if (is2t) |
25b13dbc | 1819 | rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); |
7274a8c2 | 1820 | /* IQ calibration setting */ |
4c48869f | 1821 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); |
25b13dbc LF |
1822 | rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); |
1823 | rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); | |
1824 | rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); | |
7274a8c2 CL |
1825 | for (i = 0; i < retrycount; i++) { |
1826 | patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); | |
1827 | if (patha_ok == 0x03) { | |
1828 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1829 | "Path A IQK Success!!\n"); |
25b13dbc | 1830 | result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & |
7274a8c2 | 1831 | 0x3FF0000) >> 16; |
25b13dbc | 1832 | result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & |
7274a8c2 | 1833 | 0x3FF0000) >> 16; |
25b13dbc | 1834 | result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & |
7274a8c2 | 1835 | 0x3FF0000) >> 16; |
25b13dbc | 1836 | result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & |
7274a8c2 CL |
1837 | 0x3FF0000) >> 16; |
1838 | break; | |
1839 | } else if (i == (retrycount - 1) && patha_ok == 0x01) { | |
1840 | /* Tx IQK OK */ | |
1841 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1842 | "Path A IQK Only Tx Success!!\n"); |
7274a8c2 | 1843 | |
25b13dbc | 1844 | result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & |
7274a8c2 | 1845 | 0x3FF0000) >> 16; |
25b13dbc | 1846 | result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & |
7274a8c2 CL |
1847 | 0x3FF0000) >> 16; |
1848 | } | |
1849 | } | |
1850 | if (0x00 == patha_ok) | |
4c48869f | 1851 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); |
7274a8c2 CL |
1852 | if (is2t) { |
1853 | _rtl92d_phy_patha_standby(hw); | |
1854 | /* Turn Path B ADDA on */ | |
1855 | _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); | |
1856 | for (i = 0; i < retrycount; i++) { | |
1857 | pathb_ok = _rtl92d_phy_pathb_iqk(hw); | |
1858 | if (pathb_ok == 0x03) { | |
1859 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1860 | "Path B IQK Success!!\n"); |
7274a8c2 | 1861 | result[t][4] = (rtl_get_bbreg(hw, 0xeb4, |
25b13dbc | 1862 | MASKDWORD) & 0x3FF0000) >> 16; |
7274a8c2 | 1863 | result[t][5] = (rtl_get_bbreg(hw, 0xebc, |
25b13dbc | 1864 | MASKDWORD) & 0x3FF0000) >> 16; |
7274a8c2 | 1865 | result[t][6] = (rtl_get_bbreg(hw, 0xec4, |
25b13dbc | 1866 | MASKDWORD) & 0x3FF0000) >> 16; |
7274a8c2 | 1867 | result[t][7] = (rtl_get_bbreg(hw, 0xecc, |
25b13dbc | 1868 | MASKDWORD) & 0x3FF0000) >> 16; |
7274a8c2 CL |
1869 | break; |
1870 | } else if (i == (retrycount - 1) && pathb_ok == 0x01) { | |
1871 | /* Tx IQK OK */ | |
1872 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1873 | "Path B Only Tx IQK Success!!\n"); |
7274a8c2 | 1874 | result[t][4] = (rtl_get_bbreg(hw, 0xeb4, |
25b13dbc | 1875 | MASKDWORD) & 0x3FF0000) >> 16; |
7274a8c2 | 1876 | result[t][5] = (rtl_get_bbreg(hw, 0xebc, |
25b13dbc | 1877 | MASKDWORD) & 0x3FF0000) >> 16; |
7274a8c2 CL |
1878 | } |
1879 | } | |
1880 | if (0x00 == pathb_ok) | |
1881 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1882 | "Path B IQK failed!!\n"); |
7274a8c2 CL |
1883 | } |
1884 | ||
1885 | /* Back to BB mode, load original value */ | |
1886 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 1887 | "IQK:Back to BB mode, load original value!\n"); |
7274a8c2 | 1888 | |
25b13dbc | 1889 | rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); |
7274a8c2 CL |
1890 | if (t != 0) { |
1891 | /* Switch back BB to SI mode after finish IQ Calibration. */ | |
1892 | if (!rtlphy->rfpi_enable) | |
1893 | _rtl92d_phy_pimode_switch(hw, false); | |
1894 | /* Reload ADDA power saving parameters */ | |
1895 | _rtl92d_phy_reload_adda_registers(hw, adda_reg, | |
1896 | rtlphy->adda_backup, IQK_ADDA_REG_NUM); | |
1897 | /* Reload MAC parameters */ | |
1898 | _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, | |
1899 | rtlphy->iqk_mac_backup); | |
1900 | if (is2t) | |
1901 | _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, | |
1902 | rtlphy->iqk_bb_backup, | |
1903 | IQK_BB_REG_NUM); | |
1904 | else | |
1905 | _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, | |
1906 | rtlphy->iqk_bb_backup, | |
1907 | IQK_BB_REG_NUM - 1); | |
1908 | /* load 0xe30 IQC default value */ | |
25b13dbc LF |
1909 | rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); |
1910 | rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); | |
7274a8c2 | 1911 | } |
4c48869f | 1912 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); |
7274a8c2 CL |
1913 | } |
1914 | ||
1915 | static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, | |
1916 | long result[][8], u8 t) | |
1917 | { | |
1918 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1919 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1920 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
1921 | u8 patha_ok, pathb_ok; | |
1922 | static u32 adda_reg[IQK_ADDA_REG_NUM] = { | |
1923 | RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, | |
1924 | 0xe78, 0xe7c, 0xe80, 0xe84, | |
1925 | 0xe88, 0xe8c, 0xed0, 0xed4, | |
1926 | 0xed8, 0xedc, 0xee0, 0xeec | |
1927 | }; | |
1928 | static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { | |
1929 | 0x522, 0x550, 0x551, 0x040 | |
1930 | }; | |
1931 | static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { | |
1932 | RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, | |
1933 | RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, | |
1934 | RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, | |
1935 | RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, | |
1936 | ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 | |
1937 | }; | |
1938 | u32 bbvalue; | |
1939 | bool is2t = IS_92D_SINGLEPHY(rtlhal->version); | |
1940 | ||
1941 | /* Note: IQ calibration must be performed after loading | |
1942 | * PHY_REG.txt , and radio_a, radio_b.txt */ | |
1943 | ||
4c48869f | 1944 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); |
faeef8ac | 1945 | mdelay(IQK_DELAY_TIME * 20); |
7274a8c2 | 1946 | if (t == 0) { |
25b13dbc | 1947 | bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); |
4c48869f JP |
1948 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); |
1949 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", | |
1950 | is2t ? "2T2R" : "1T1R"); | |
7274a8c2 CL |
1951 | /* Save ADDA parameters, turn Path A ADDA on */ |
1952 | _rtl92d_phy_save_adda_registers(hw, adda_reg, | |
1953 | rtlphy->adda_backup, | |
1954 | IQK_ADDA_REG_NUM); | |
1955 | _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, | |
1956 | rtlphy->iqk_mac_backup); | |
1957 | if (is2t) | |
1958 | _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, | |
1959 | rtlphy->iqk_bb_backup, | |
1960 | IQK_BB_REG_NUM); | |
1961 | else | |
1962 | _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, | |
1963 | rtlphy->iqk_bb_backup, | |
1964 | IQK_BB_REG_NUM - 1); | |
1965 | } | |
1966 | _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); | |
1967 | /* MAC settings */ | |
1968 | _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, | |
1969 | rtlphy->iqk_mac_backup); | |
1970 | if (t == 0) | |
1971 | rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, | |
1972 | RFPGA0_XA_HSSIPARAMETER1, BIT(8)); | |
1973 | /* Switch BB to PI mode to do IQ Calibration. */ | |
1974 | if (!rtlphy->rfpi_enable) | |
1975 | _rtl92d_phy_pimode_switch(hw, true); | |
1976 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); | |
25b13dbc LF |
1977 | rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); |
1978 | rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); | |
1979 | rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); | |
7274a8c2 CL |
1980 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); |
1981 | ||
1982 | /* Page B init */ | |
25b13dbc | 1983 | rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); |
7274a8c2 | 1984 | if (is2t) |
25b13dbc | 1985 | rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); |
7274a8c2 | 1986 | /* IQ calibration setting */ |
4c48869f | 1987 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); |
25b13dbc LF |
1988 | rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); |
1989 | rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); | |
1990 | rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); | |
7274a8c2 CL |
1991 | patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); |
1992 | if (patha_ok == 0x03) { | |
4c48869f | 1993 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); |
25b13dbc | 1994 | result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & |
7274a8c2 | 1995 | 0x3FF0000) >> 16; |
25b13dbc | 1996 | result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & |
7274a8c2 | 1997 | 0x3FF0000) >> 16; |
25b13dbc | 1998 | result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & |
7274a8c2 | 1999 | 0x3FF0000) >> 16; |
25b13dbc | 2000 | result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & |
7274a8c2 CL |
2001 | 0x3FF0000) >> 16; |
2002 | } else if (patha_ok == 0x01) { /* Tx IQK OK */ | |
2003 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2004 | "Path A IQK Only Tx Success!!\n"); |
7274a8c2 | 2005 | |
25b13dbc | 2006 | result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & |
7274a8c2 | 2007 | 0x3FF0000) >> 16; |
25b13dbc | 2008 | result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & |
7274a8c2 CL |
2009 | 0x3FF0000) >> 16; |
2010 | } else { | |
4c48869f | 2011 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); |
7274a8c2 CL |
2012 | } |
2013 | if (is2t) { | |
2014 | /* _rtl92d_phy_patha_standby(hw); */ | |
2015 | /* Turn Path B ADDA on */ | |
2016 | _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); | |
2017 | pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); | |
2018 | if (pathb_ok == 0x03) { | |
2019 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2020 | "Path B IQK Success!!\n"); |
25b13dbc | 2021 | result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & |
7274a8c2 | 2022 | 0x3FF0000) >> 16; |
25b13dbc | 2023 | result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & |
7274a8c2 | 2024 | 0x3FF0000) >> 16; |
25b13dbc | 2025 | result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & |
7274a8c2 | 2026 | 0x3FF0000) >> 16; |
25b13dbc | 2027 | result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & |
7274a8c2 CL |
2028 | 0x3FF0000) >> 16; |
2029 | } else if (pathb_ok == 0x01) { /* Tx IQK OK */ | |
2030 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2031 | "Path B Only Tx IQK Success!!\n"); |
25b13dbc | 2032 | result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & |
7274a8c2 | 2033 | 0x3FF0000) >> 16; |
25b13dbc | 2034 | result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & |
7274a8c2 CL |
2035 | 0x3FF0000) >> 16; |
2036 | } else { | |
2037 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2038 | "Path B IQK failed!!\n"); |
7274a8c2 CL |
2039 | } |
2040 | } | |
2041 | ||
2042 | /* Back to BB mode, load original value */ | |
2043 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2044 | "IQK:Back to BB mode, load original value!\n"); |
25b13dbc | 2045 | rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); |
7274a8c2 CL |
2046 | if (t != 0) { |
2047 | if (is2t) | |
2048 | _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, | |
2049 | rtlphy->iqk_bb_backup, | |
2050 | IQK_BB_REG_NUM); | |
2051 | else | |
2052 | _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, | |
2053 | rtlphy->iqk_bb_backup, | |
2054 | IQK_BB_REG_NUM - 1); | |
2055 | /* Reload MAC parameters */ | |
2056 | _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, | |
2057 | rtlphy->iqk_mac_backup); | |
2058 | /* Switch back BB to SI mode after finish IQ Calibration. */ | |
2059 | if (!rtlphy->rfpi_enable) | |
2060 | _rtl92d_phy_pimode_switch(hw, false); | |
2061 | /* Reload ADDA power saving parameters */ | |
2062 | _rtl92d_phy_reload_adda_registers(hw, adda_reg, | |
2063 | rtlphy->adda_backup, | |
2064 | IQK_ADDA_REG_NUM); | |
2065 | } | |
4c48869f | 2066 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); |
7274a8c2 CL |
2067 | } |
2068 | ||
2069 | static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, | |
2070 | long result[][8], u8 c1, u8 c2) | |
2071 | { | |
2072 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2073 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2074 | u32 i, j, diff, sim_bitmap, bound; | |
2075 | u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ | |
2076 | bool bresult = true; | |
2077 | bool is2t = IS_92D_SINGLEPHY(rtlhal->version); | |
2078 | ||
2079 | if (is2t) | |
2080 | bound = 8; | |
2081 | else | |
2082 | bound = 4; | |
2083 | sim_bitmap = 0; | |
2084 | for (i = 0; i < bound; i++) { | |
2085 | diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - | |
2086 | result[c2][i]) : (result[c2][i] - result[c1][i]); | |
2087 | if (diff > MAX_TOLERANCE_92D) { | |
2088 | if ((i == 2 || i == 6) && !sim_bitmap) { | |
2089 | if (result[c1][i] + result[c1][i + 1] == 0) | |
2090 | final_candidate[(i / 4)] = c2; | |
2091 | else if (result[c2][i] + result[c2][i + 1] == 0) | |
2092 | final_candidate[(i / 4)] = c1; | |
2093 | else | |
2094 | sim_bitmap = sim_bitmap | (1 << i); | |
2095 | } else { | |
2096 | sim_bitmap = sim_bitmap | (1 << i); | |
2097 | } | |
2098 | } | |
2099 | } | |
2100 | if (sim_bitmap == 0) { | |
2101 | for (i = 0; i < (bound / 4); i++) { | |
2102 | if (final_candidate[i] != 0xFF) { | |
2103 | for (j = i * 4; j < (i + 1) * 4 - 2; j++) | |
2104 | result[3][j] = | |
2105 | result[final_candidate[i]][j]; | |
2106 | bresult = false; | |
2107 | } | |
2108 | } | |
2109 | return bresult; | |
2110 | } | |
2111 | if (!(sim_bitmap & 0x0F)) { /* path A OK */ | |
2112 | for (i = 0; i < 4; i++) | |
2113 | result[3][i] = result[c1][i]; | |
2114 | } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ | |
2115 | for (i = 0; i < 2; i++) | |
2116 | result[3][i] = result[c1][i]; | |
2117 | } | |
2118 | if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ | |
2119 | for (i = 4; i < 8; i++) | |
2120 | result[3][i] = result[c1][i]; | |
2121 | } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ | |
2122 | for (i = 4; i < 6; i++) | |
2123 | result[3][i] = result[c1][i]; | |
2124 | } | |
2125 | return false; | |
2126 | } | |
2127 | ||
2128 | static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, | |
2129 | bool iqk_ok, long result[][8], | |
2130 | u8 final_candidate, bool txonly) | |
2131 | { | |
2132 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2133 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2134 | u32 oldval_0, val_x, tx0_a, reg; | |
2135 | long val_y, tx0_c; | |
2136 | bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || | |
2137 | rtlhal->macphymode == DUALMAC_DUALPHY; | |
2138 | ||
2139 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2140 | "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); |
7274a8c2 CL |
2141 | if (final_candidate == 0xFF) { |
2142 | return; | |
2143 | } else if (iqk_ok) { | |
b83faeda | 2144 | oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, |
25b13dbc | 2145 | MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ |
7274a8c2 CL |
2146 | val_x = result[final_candidate][0]; |
2147 | if ((val_x & 0x00000200) != 0) | |
2148 | val_x = val_x | 0xFFFFFC00; | |
2149 | tx0_a = (val_x * oldval_0) >> 8; | |
4c48869f JP |
2150 | RTPRINT(rtlpriv, FINIT, INIT_IQK, |
2151 | "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", | |
2152 | val_x, tx0_a, oldval_0); | |
b83faeda | 2153 | rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); |
7274a8c2 CL |
2154 | rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), |
2155 | ((val_x * oldval_0 >> 7) & 0x1)); | |
2156 | val_y = result[final_candidate][1]; | |
2157 | if ((val_y & 0x00000200) != 0) | |
2158 | val_y = val_y | 0xFFFFFC00; | |
2159 | /* path B IQK result + 3 */ | |
2160 | if (rtlhal->interfaceindex == 1 && | |
2161 | rtlhal->current_bandtype == BAND_ON_5G) | |
2162 | val_y += 3; | |
2163 | tx0_c = (val_y * oldval_0) >> 8; | |
4c48869f JP |
2164 | RTPRINT(rtlpriv, FINIT, INIT_IQK, |
2165 | "Y = 0x%lx, tx0_c = 0x%lx\n", | |
2166 | val_y, tx0_c); | |
b83faeda | 2167 | rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, |
7274a8c2 | 2168 | ((tx0_c & 0x3C0) >> 6)); |
b83faeda | 2169 | rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, |
7274a8c2 CL |
2170 | (tx0_c & 0x3F)); |
2171 | if (is2t) | |
2172 | rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), | |
2173 | ((val_y * oldval_0 >> 7) & 0x1)); | |
4c48869f | 2174 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", |
b83faeda | 2175 | rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, |
25b13dbc | 2176 | MASKDWORD)); |
7274a8c2 | 2177 | if (txonly) { |
4c48869f | 2178 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); |
7274a8c2 CL |
2179 | return; |
2180 | } | |
2181 | reg = result[final_candidate][2]; | |
2182 | rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); | |
2183 | reg = result[final_candidate][3] & 0x3F; | |
2184 | rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); | |
2185 | reg = (result[final_candidate][3] >> 6) & 0xF; | |
2186 | rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); | |
2187 | } | |
2188 | } | |
2189 | ||
2190 | static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, | |
2191 | bool iqk_ok, long result[][8], u8 final_candidate, bool txonly) | |
2192 | { | |
2193 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2194 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2195 | u32 oldval_1, val_x, tx1_a, reg; | |
2196 | long val_y, tx1_c; | |
2197 | ||
4c48869f JP |
2198 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", |
2199 | iqk_ok ? "Success" : "Failed"); | |
7274a8c2 CL |
2200 | if (final_candidate == 0xFF) { |
2201 | return; | |
2202 | } else if (iqk_ok) { | |
b83faeda | 2203 | oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, |
25b13dbc | 2204 | MASKDWORD) >> 22) & 0x3FF; |
7274a8c2 CL |
2205 | val_x = result[final_candidate][4]; |
2206 | if ((val_x & 0x00000200) != 0) | |
2207 | val_x = val_x | 0xFFFFFC00; | |
2208 | tx1_a = (val_x * oldval_1) >> 8; | |
4c48869f JP |
2209 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", |
2210 | val_x, tx1_a); | |
b83faeda | 2211 | rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); |
7274a8c2 CL |
2212 | rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), |
2213 | ((val_x * oldval_1 >> 7) & 0x1)); | |
2214 | val_y = result[final_candidate][5]; | |
2215 | if ((val_y & 0x00000200) != 0) | |
2216 | val_y = val_y | 0xFFFFFC00; | |
2217 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
2218 | val_y += 3; | |
2219 | tx1_c = (val_y * oldval_1) >> 8; | |
4c48869f JP |
2220 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", |
2221 | val_y, tx1_c); | |
b83faeda | 2222 | rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, |
7274a8c2 | 2223 | ((tx1_c & 0x3C0) >> 6)); |
b83faeda | 2224 | rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, |
7274a8c2 CL |
2225 | (tx1_c & 0x3F)); |
2226 | rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), | |
2227 | ((val_y * oldval_1 >> 7) & 0x1)); | |
2228 | if (txonly) | |
2229 | return; | |
2230 | reg = result[final_candidate][6]; | |
2231 | rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); | |
2232 | reg = result[final_candidate][7] & 0x3F; | |
2233 | rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); | |
2234 | reg = (result[final_candidate][7] >> 6) & 0xF; | |
2235 | rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); | |
2236 | } | |
2237 | } | |
2238 | ||
2239 | void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw) | |
2240 | { | |
2241 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2242 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2243 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2244 | long result[4][8]; | |
2245 | u8 i, final_candidate, indexforchannel; | |
2246 | bool patha_ok, pathb_ok; | |
2247 | long rege94, rege9c, regea4, regeac, regeb4; | |
2248 | long regebc, regec4, regecc, regtmp = 0; | |
2249 | bool is12simular, is13simular, is23simular; | |
2250 | unsigned long flag = 0; | |
2251 | ||
2252 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2253 | "IQK:Start!!!channel %d\n", rtlphy->current_channel); |
7274a8c2 CL |
2254 | for (i = 0; i < 8; i++) { |
2255 | result[0][i] = 0; | |
2256 | result[1][i] = 0; | |
2257 | result[2][i] = 0; | |
2258 | result[3][i] = 0; | |
2259 | } | |
2260 | final_candidate = 0xff; | |
2261 | patha_ok = false; | |
2262 | pathb_ok = false; | |
2263 | is12simular = false; | |
2264 | is23simular = false; | |
2265 | is13simular = false; | |
2266 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2267 | "IQK !!!currentband %d\n", rtlhal->current_bandtype); |
7274a8c2 CL |
2268 | rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); |
2269 | for (i = 0; i < 3; i++) { | |
2270 | if (rtlhal->current_bandtype == BAND_ON_5G) { | |
2271 | _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i); | |
2272 | } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
2273 | if (IS_92D_SINGLEPHY(rtlhal->version)) | |
2274 | _rtl92d_phy_iq_calibrate(hw, result, i, true); | |
2275 | else | |
2276 | _rtl92d_phy_iq_calibrate(hw, result, i, false); | |
2277 | } | |
2278 | if (i == 1) { | |
2279 | is12simular = _rtl92d_phy_simularity_compare(hw, result, | |
2280 | 0, 1); | |
2281 | if (is12simular) { | |
2282 | final_candidate = 0; | |
2283 | break; | |
2284 | } | |
2285 | } | |
2286 | if (i == 2) { | |
2287 | is13simular = _rtl92d_phy_simularity_compare(hw, result, | |
2288 | 0, 2); | |
2289 | if (is13simular) { | |
2290 | final_candidate = 0; | |
2291 | break; | |
2292 | } | |
2293 | is23simular = _rtl92d_phy_simularity_compare(hw, result, | |
2294 | 1, 2); | |
2295 | if (is23simular) { | |
2296 | final_candidate = 1; | |
2297 | } else { | |
2298 | for (i = 0; i < 8; i++) | |
2299 | regtmp += result[3][i]; | |
2300 | ||
2301 | if (regtmp != 0) | |
2302 | final_candidate = 3; | |
2303 | else | |
2304 | final_candidate = 0xFF; | |
2305 | } | |
2306 | } | |
2307 | } | |
2308 | rtl92d_release_cckandrw_pagea_ctl(hw, &flag); | |
2309 | for (i = 0; i < 4; i++) { | |
2310 | rege94 = result[i][0]; | |
2311 | rege9c = result[i][1]; | |
2312 | regea4 = result[i][2]; | |
2313 | regeac = result[i][3]; | |
2314 | regeb4 = result[i][4]; | |
2315 | regebc = result[i][5]; | |
2316 | regec4 = result[i][6]; | |
2317 | regecc = result[i][7]; | |
2318 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2319 | "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", |
7274a8c2 | 2320 | rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, |
4c48869f | 2321 | regecc); |
7274a8c2 CL |
2322 | } |
2323 | if (final_candidate != 0xff) { | |
2324 | rtlphy->reg_e94 = rege94 = result[final_candidate][0]; | |
2325 | rtlphy->reg_e9c = rege9c = result[final_candidate][1]; | |
2326 | regea4 = result[final_candidate][2]; | |
2327 | regeac = result[final_candidate][3]; | |
2328 | rtlphy->reg_eb4 = regeb4 = result[final_candidate][4]; | |
2329 | rtlphy->reg_ebc = regebc = result[final_candidate][5]; | |
2330 | regec4 = result[final_candidate][6]; | |
2331 | regecc = result[final_candidate][7]; | |
2332 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2333 | "IQK: final_candidate is %x\n", final_candidate); |
7274a8c2 | 2334 | RTPRINT(rtlpriv, FINIT, INIT_IQK, |
4c48869f | 2335 | "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", |
7274a8c2 | 2336 | rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, |
4c48869f | 2337 | regecc); |
7274a8c2 CL |
2338 | patha_ok = pathb_ok = true; |
2339 | } else { | |
2340 | rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ | |
2341 | rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ | |
2342 | } | |
2343 | if ((rege94 != 0) /*&&(regea4 != 0) */) | |
2344 | _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result, | |
2345 | final_candidate, (regea4 == 0)); | |
2346 | if (IS_92D_SINGLEPHY(rtlhal->version)) { | |
2347 | if ((regeb4 != 0) /*&&(regec4 != 0) */) | |
2348 | _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, | |
2349 | final_candidate, (regec4 == 0)); | |
2350 | } | |
2351 | if (final_candidate != 0xFF) { | |
2352 | indexforchannel = rtl92d_get_rightchnlplace_for_iqk( | |
2353 | rtlphy->current_channel); | |
2354 | ||
2355 | for (i = 0; i < IQK_MATRIX_REG_NUM; i++) | |
e6deaf81 | 2356 | rtlphy->iqk_matrix[indexforchannel]. |
7274a8c2 | 2357 | value[0][i] = result[final_candidate][i]; |
e6deaf81 | 2358 | rtlphy->iqk_matrix[indexforchannel].iqk_done = |
7274a8c2 CL |
2359 | true; |
2360 | ||
2361 | RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, | |
f30d7507 | 2362 | "IQK OK indexforchannel %d\n", indexforchannel); |
7274a8c2 CL |
2363 | } |
2364 | } | |
2365 | ||
2366 | void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) | |
2367 | { | |
2368 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2369 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2370 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2371 | u8 indexforchannel; | |
2372 | ||
f30d7507 | 2373 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); |
7274a8c2 CL |
2374 | /*------Do IQK for normal chip and test chip 5G band------- */ |
2375 | indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); | |
f30d7507 JP |
2376 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", |
2377 | indexforchannel, | |
e6deaf81 LF |
2378 | rtlphy->iqk_matrix[indexforchannel].iqk_done); |
2379 | if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && | |
7274a8c2 CL |
2380 | rtlphy->need_iqk) { |
2381 | /* Re Do IQK. */ | |
2382 | RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, | |
f30d7507 | 2383 | "Do IQK Matrix reg for channel:%d....\n", channel); |
7274a8c2 CL |
2384 | rtl92d_phy_iq_calibrate(hw); |
2385 | } else { | |
2386 | /* Just load the value. */ | |
2387 | /* 2G band just load once. */ | |
2388 | if (((!rtlhal->load_imrandiqk_setting_for2g) && | |
2389 | indexforchannel == 0) || indexforchannel > 0) { | |
2390 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, | |
f30d7507 JP |
2391 | "Just Read IQK Matrix reg for channel:%d....\n", |
2392 | channel); | |
e6deaf81 | 2393 | if ((rtlphy->iqk_matrix[indexforchannel]. |
7274a8c2 CL |
2394 | value[0] != NULL) |
2395 | /*&&(regea4 != 0) */) | |
2396 | _rtl92d_phy_patha_fill_iqk_matrix(hw, true, | |
e6deaf81 | 2397 | rtlphy->iqk_matrix[ |
7274a8c2 | 2398 | indexforchannel].value, 0, |
e6deaf81 | 2399 | (rtlphy->iqk_matrix[ |
7274a8c2 CL |
2400 | indexforchannel].value[0][2] == 0)); |
2401 | if (IS_92D_SINGLEPHY(rtlhal->version)) { | |
e6deaf81 | 2402 | if ((rtlphy->iqk_matrix[ |
7274a8c2 CL |
2403 | indexforchannel].value[0][4] != 0) |
2404 | /*&&(regec4 != 0) */) | |
2405 | _rtl92d_phy_pathb_fill_iqk_matrix(hw, | |
2406 | true, | |
e6deaf81 | 2407 | rtlphy->iqk_matrix[ |
7274a8c2 | 2408 | indexforchannel].value, 0, |
e6deaf81 | 2409 | (rtlphy->iqk_matrix[ |
7274a8c2 CL |
2410 | indexforchannel].value[0][6] |
2411 | == 0)); | |
2412 | } | |
2413 | } | |
2414 | } | |
2415 | rtlphy->need_iqk = false; | |
f30d7507 | 2416 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); |
7274a8c2 CL |
2417 | } |
2418 | ||
2419 | static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) | |
2420 | { | |
2421 | u32 ret; | |
2422 | ||
2423 | if (val1 >= val2) | |
2424 | ret = val1 - val2; | |
2425 | else | |
2426 | ret = val2 - val1; | |
2427 | return ret; | |
2428 | } | |
2429 | ||
2430 | static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) | |
2431 | { | |
2432 | ||
2433 | int i; | |
7274a8c2 | 2434 | |
bb6fa826 LF |
2435 | for (i = 0; i < sizeof(channel5g); i++) |
2436 | if (channel == channel5g[i]) | |
7274a8c2 CL |
2437 | return true; |
2438 | return false; | |
2439 | } | |
2440 | ||
2441 | static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, | |
2442 | u32 *targetchnl, u32 * curvecount_val, | |
2443 | bool is5g, u32 *curveindex) | |
2444 | { | |
2445 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2446 | u32 smallest_abs_val = 0xffffffff, u4tmp; | |
2447 | u8 i, j; | |
2448 | u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; | |
2449 | ||
2450 | for (i = 0; i < chnl_num; i++) { | |
2451 | if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) | |
2452 | continue; | |
2453 | curveindex[i] = 0; | |
2454 | for (j = 0; j < (CV_CURVE_CNT * 2); j++) { | |
2455 | u4tmp = _rtl92d_phy_get_abs(targetchnl[i], | |
2456 | curvecount_val[j]); | |
2457 | ||
2458 | if (u4tmp < smallest_abs_val) { | |
2459 | curveindex[i] = j; | |
2460 | smallest_abs_val = u4tmp; | |
2461 | } | |
2462 | } | |
2463 | smallest_abs_val = 0xffffffff; | |
4c48869f JP |
2464 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", |
2465 | i, curveindex[i]); | |
7274a8c2 CL |
2466 | } |
2467 | } | |
2468 | ||
2469 | static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, | |
2470 | u8 channel) | |
2471 | { | |
2472 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2473 | u8 erfpath = rtlpriv->rtlhal.current_bandtype == | |
2474 | BAND_ON_5G ? RF90_PATH_A : | |
2475 | IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? | |
2476 | RF90_PATH_B : RF90_PATH_A; | |
2477 | u32 u4tmp = 0, u4regvalue = 0; | |
2478 | bool bneed_powerdown_radio = false; | |
2479 | ||
f30d7507 | 2480 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); |
4c48869f JP |
2481 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", |
2482 | rtlpriv->rtlhal.current_bandtype); | |
2483 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); | |
7274a8c2 CL |
2484 | if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ |
2485 | u4tmp = curveindex_5g[channel-1]; | |
2486 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4f4378de | 2487 | "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); |
7274a8c2 CL |
2488 | if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && |
2489 | rtlpriv->rtlhal.interfaceindex == 1) { | |
2490 | bneed_powerdown_radio = | |
2491 | rtl92d_phy_enable_anotherphy(hw, false); | |
2492 | rtlpriv->rtlhal.during_mac1init_radioa = true; | |
2493 | /* asume no this case */ | |
2494 | if (bneed_powerdown_radio) | |
2495 | _rtl92d_phy_enable_rf_env(hw, erfpath, | |
2496 | &u4regvalue); | |
2497 | } | |
2498 | rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); | |
2499 | if (bneed_powerdown_radio) | |
2500 | _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); | |
2501 | if (rtlpriv->rtlhal.during_mac1init_radioa) | |
2502 | rtl92d_phy_powerdown_anotherphy(hw, false); | |
2503 | } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { | |
2504 | u4tmp = curveindex_2g[channel-1]; | |
2505 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4f4378de | 2506 | "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); |
7274a8c2 CL |
2507 | if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && |
2508 | rtlpriv->rtlhal.interfaceindex == 0) { | |
2509 | bneed_powerdown_radio = | |
2510 | rtl92d_phy_enable_anotherphy(hw, true); | |
2511 | rtlpriv->rtlhal.during_mac0init_radiob = true; | |
2512 | if (bneed_powerdown_radio) | |
2513 | _rtl92d_phy_enable_rf_env(hw, erfpath, | |
2514 | &u4regvalue); | |
2515 | } | |
2516 | rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); | |
2517 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4f4378de | 2518 | "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", |
4c48869f | 2519 | rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); |
7274a8c2 CL |
2520 | if (bneed_powerdown_radio) |
2521 | _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); | |
2522 | if (rtlpriv->rtlhal.during_mac0init_radiob) | |
2523 | rtl92d_phy_powerdown_anotherphy(hw, true); | |
2524 | } | |
f30d7507 | 2525 | RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); |
7274a8c2 CL |
2526 | } |
2527 | ||
2528 | static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) | |
2529 | { | |
2530 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2531 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2532 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
2533 | u8 tmpreg, index, rf_mode[2]; | |
2534 | u8 path = is2t ? 2 : 1; | |
2535 | u8 i; | |
2536 | u32 u4tmp, offset; | |
2537 | u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; | |
2538 | u16 timeout = 800, timecount = 0; | |
2539 | ||
2540 | /* Check continuous TX and Packet TX */ | |
2541 | tmpreg = rtl_read_byte(rtlpriv, 0xd03); | |
2542 | /* if Deal with contisuous TX case, disable all continuous TX */ | |
2543 | /* if Deal with Packet TX case, block all queues */ | |
2544 | if ((tmpreg & 0x70) != 0) | |
2545 | rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); | |
2546 | else | |
2547 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); | |
2548 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); | |
2549 | for (index = 0; index < path; index++) { | |
2550 | /* 1. Read original RF mode */ | |
2551 | offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; | |
2552 | rf_mode[index] = rtl_read_byte(rtlpriv, offset); | |
2553 | /* 2. Set RF mode = standby mode */ | |
2554 | rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, | |
25b13dbc | 2555 | RFREG_OFFSET_MASK, 0x010000); |
7274a8c2 CL |
2556 | if (rtlpci->init_ready) { |
2557 | /* switch CV-curve control by LC-calibration */ | |
2558 | rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, | |
2559 | BIT(17), 0x0); | |
2560 | /* 4. Set LC calibration begin */ | |
2561 | rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, | |
2562 | 0x08000, 0x01); | |
2563 | } | |
2564 | u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, | |
25b13dbc | 2565 | RFREG_OFFSET_MASK); |
7274a8c2 CL |
2566 | while ((!(u4tmp & BIT(11))) && timecount <= timeout) { |
2567 | mdelay(50); | |
2568 | timecount += 50; | |
2569 | u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, | |
25b13dbc | 2570 | RF_SYN_G6, RFREG_OFFSET_MASK); |
7274a8c2 CL |
2571 | } |
2572 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2573 | "PHY_LCK finish delay for %d ms=2\n", timecount); |
25b13dbc | 2574 | u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); |
7274a8c2 CL |
2575 | if (index == 0 && rtlhal->interfaceindex == 0) { |
2576 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2577 | "path-A / 5G LCK\n"); |
7274a8c2 CL |
2578 | } else { |
2579 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f | 2580 | "path-B / 2.4G LCK\n"); |
7274a8c2 CL |
2581 | } |
2582 | memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2); | |
2583 | /* Set LC calibration off */ | |
2584 | rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, | |
2585 | 0x08000, 0x0); | |
4c48869f | 2586 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); |
7274a8c2 CL |
2587 | /* save Curve-counting number */ |
2588 | for (i = 0; i < CV_CURVE_CNT; i++) { | |
2589 | u32 readval = 0, readval2 = 0; | |
2590 | rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, | |
2591 | 0x7f, i); | |
2592 | ||
2593 | rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, | |
25b13dbc | 2594 | RFREG_OFFSET_MASK, 0x0); |
7274a8c2 | 2595 | readval = rtl_get_rfreg(hw, (enum radio_path)index, |
25b13dbc | 2596 | 0x4F, RFREG_OFFSET_MASK); |
7274a8c2 CL |
2597 | curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; |
2598 | /* reg 0x4f [4:0] */ | |
2599 | /* reg 0x50 [19:10] */ | |
2600 | readval2 = rtl_get_rfreg(hw, (enum radio_path)index, | |
2601 | 0x50, 0xffc00); | |
2602 | curvecount_val[2 * i] = (((readval & 0x1F) << 10) | | |
2603 | readval2); | |
2604 | } | |
2605 | if (index == 0 && rtlhal->interfaceindex == 0) | |
2606 | _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, | |
2607 | curvecount_val, | |
2608 | true, curveindex_5g); | |
2609 | else | |
2610 | _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, | |
2611 | curvecount_val, | |
2612 | false, curveindex_2g); | |
2613 | /* switch CV-curve control mode */ | |
2614 | rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, | |
2615 | BIT(17), 0x1); | |
2616 | } | |
2617 | ||
2618 | /* Restore original situation */ | |
2619 | for (index = 0; index < path; index++) { | |
2620 | offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; | |
2621 | rtl_write_byte(rtlpriv, offset, 0x50); | |
2622 | rtl_write_byte(rtlpriv, offset, rf_mode[index]); | |
2623 | } | |
2624 | if ((tmpreg & 0x70) != 0) | |
2625 | rtl_write_byte(rtlpriv, 0xd03, tmpreg); | |
2626 | else /*Deal with Packet TX case */ | |
2627 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); | |
2628 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); | |
2629 | _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); | |
2630 | } | |
2631 | ||
2632 | static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) | |
2633 | { | |
2634 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2635 | ||
4c48869f | 2636 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n"); |
7274a8c2 CL |
2637 | _rtl92d_phy_lc_calibrate_sw(hw, is2t); |
2638 | } | |
2639 | ||
2640 | void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) | |
2641 | { | |
2642 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2643 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2644 | struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); | |
2645 | u32 timeout = 2000, timecount = 0; | |
2646 | ||
2647 | while (rtlpriv->mac80211.act_scanning && timecount < timeout) { | |
2648 | udelay(50); | |
2649 | timecount += 50; | |
2650 | } | |
2651 | ||
2652 | rtlphy->lck_inprogress = true; | |
2653 | RTPRINT(rtlpriv, FINIT, INIT_IQK, | |
4c48869f JP |
2654 | "LCK:Start!!! currentband %x delay %d ms\n", |
2655 | rtlhal->current_bandtype, timecount); | |
7274a8c2 CL |
2656 | if (IS_92D_SINGLEPHY(rtlhal->version)) { |
2657 | _rtl92d_phy_lc_calibrate(hw, true); | |
2658 | } else { | |
2659 | /* For 1T1R */ | |
2660 | _rtl92d_phy_lc_calibrate(hw, false); | |
2661 | } | |
2662 | rtlphy->lck_inprogress = false; | |
4c48869f | 2663 | RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); |
7274a8c2 CL |
2664 | } |
2665 | ||
08aba42f | 2666 | void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) |
7274a8c2 CL |
2667 | { |
2668 | return; | |
2669 | } | |
2670 | ||
2671 | static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, | |
2672 | u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, | |
2673 | u32 para1, u32 para2, u32 msdelay) | |
2674 | { | |
2675 | struct swchnlcmd *pcmd; | |
2676 | ||
2677 | if (cmdtable == NULL) { | |
531940f9 | 2678 | WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n"); |
7274a8c2 CL |
2679 | return false; |
2680 | } | |
2681 | if (cmdtableidx >= cmdtablesz) | |
2682 | return false; | |
2683 | ||
2684 | pcmd = cmdtable + cmdtableidx; | |
2685 | pcmd->cmdid = cmdid; | |
2686 | pcmd->para1 = para1; | |
2687 | pcmd->para2 = para2; | |
2688 | pcmd->msdelay = msdelay; | |
2689 | return true; | |
2690 | } | |
2691 | ||
2692 | void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) | |
2693 | { | |
2694 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2695 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2696 | u8 i; | |
2697 | ||
2698 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 2699 | "settings regs %d default regs %d\n", |
e6deaf81 | 2700 | (int)(sizeof(rtlphy->iqk_matrix) / |
f30d7507 JP |
2701 | sizeof(struct iqk_matrix_regs)), |
2702 | IQK_MATRIX_REG_NUM); | |
7274a8c2 CL |
2703 | /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ |
2704 | for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { | |
e6deaf81 LF |
2705 | rtlphy->iqk_matrix[i].value[0][0] = 0x100; |
2706 | rtlphy->iqk_matrix[i].value[0][2] = 0x100; | |
2707 | rtlphy->iqk_matrix[i].value[0][4] = 0x100; | |
2708 | rtlphy->iqk_matrix[i].value[0][6] = 0x100; | |
2709 | rtlphy->iqk_matrix[i].value[0][1] = 0x0; | |
2710 | rtlphy->iqk_matrix[i].value[0][3] = 0x0; | |
2711 | rtlphy->iqk_matrix[i].value[0][5] = 0x0; | |
2712 | rtlphy->iqk_matrix[i].value[0][7] = 0x0; | |
2713 | rtlphy->iqk_matrix[i].iqk_done = false; | |
7274a8c2 CL |
2714 | } |
2715 | } | |
2716 | ||
2717 | static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, | |
2718 | u8 channel, u8 *stage, u8 *step, | |
2719 | u32 *delay) | |
2720 | { | |
2721 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2722 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2723 | struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; | |
2724 | u32 precommoncmdcnt; | |
2725 | struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; | |
2726 | u32 postcommoncmdcnt; | |
2727 | struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; | |
2728 | u32 rfdependcmdcnt; | |
2729 | struct swchnlcmd *currentcmd = NULL; | |
2730 | u8 rfpath; | |
2731 | u8 num_total_rfpath = rtlphy->num_total_rfpath; | |
2732 | ||
2733 | precommoncmdcnt = 0; | |
2734 | _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, | |
2735 | MAX_PRECMD_CNT, | |
2736 | CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); | |
2737 | _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, | |
2738 | MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); | |
2739 | postcommoncmdcnt = 0; | |
2740 | _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, | |
2741 | MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); | |
2742 | rfdependcmdcnt = 0; | |
2743 | _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, | |
2744 | MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, | |
2745 | RF_CHNLBW, channel, 0); | |
2746 | _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, | |
2747 | MAX_RFDEPENDCMD_CNT, CMDID_END, | |
2748 | 0, 0, 0); | |
2749 | ||
2750 | do { | |
2751 | switch (*stage) { | |
2752 | case 0: | |
2753 | currentcmd = &precommoncmd[*step]; | |
2754 | break; | |
2755 | case 1: | |
2756 | currentcmd = &rfdependcmd[*step]; | |
2757 | break; | |
2758 | case 2: | |
2759 | currentcmd = &postcommoncmd[*step]; | |
2760 | break; | |
2761 | } | |
2762 | if (currentcmd->cmdid == CMDID_END) { | |
2763 | if ((*stage) == 2) { | |
2764 | return true; | |
2765 | } else { | |
2766 | (*stage)++; | |
2767 | (*step) = 0; | |
2768 | continue; | |
2769 | } | |
2770 | } | |
2771 | switch (currentcmd->cmdid) { | |
2772 | case CMDID_SET_TXPOWEROWER_LEVEL: | |
2773 | rtl92d_phy_set_txpower_level(hw, channel); | |
2774 | break; | |
2775 | case CMDID_WRITEPORT_ULONG: | |
2776 | rtl_write_dword(rtlpriv, currentcmd->para1, | |
2777 | currentcmd->para2); | |
2778 | break; | |
2779 | case CMDID_WRITEPORT_USHORT: | |
2780 | rtl_write_word(rtlpriv, currentcmd->para1, | |
2781 | (u16)currentcmd->para2); | |
2782 | break; | |
2783 | case CMDID_WRITEPORT_UCHAR: | |
2784 | rtl_write_byte(rtlpriv, currentcmd->para1, | |
2785 | (u8)currentcmd->para2); | |
2786 | break; | |
2787 | case CMDID_RF_WRITEREG: | |
2788 | for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { | |
2789 | rtlphy->rfreg_chnlval[rfpath] = | |
2790 | ((rtlphy->rfreg_chnlval[rfpath] & | |
2791 | 0xffffff00) | currentcmd->para2); | |
2792 | if (rtlpriv->rtlhal.current_bandtype == | |
2793 | BAND_ON_5G) { | |
2794 | if (currentcmd->para2 > 99) | |
2795 | rtlphy->rfreg_chnlval[rfpath] = | |
2796 | rtlphy->rfreg_chnlval | |
2797 | [rfpath] | (BIT(18)); | |
2798 | else | |
2799 | rtlphy->rfreg_chnlval[rfpath] = | |
2800 | rtlphy->rfreg_chnlval | |
2801 | [rfpath] & (~BIT(18)); | |
2802 | rtlphy->rfreg_chnlval[rfpath] |= | |
2803 | (BIT(16) | BIT(8)); | |
2804 | } else { | |
2805 | rtlphy->rfreg_chnlval[rfpath] &= | |
2806 | ~(BIT(8) | BIT(16) | BIT(18)); | |
2807 | } | |
2808 | rtl_set_rfreg(hw, (enum radio_path)rfpath, | |
2809 | currentcmd->para1, | |
25b13dbc | 2810 | RFREG_OFFSET_MASK, |
7274a8c2 CL |
2811 | rtlphy->rfreg_chnlval[rfpath]); |
2812 | _rtl92d_phy_reload_imr_setting(hw, channel, | |
2813 | rfpath); | |
2814 | } | |
2815 | _rtl92d_phy_switch_rf_setting(hw, channel); | |
2816 | /* do IQK when all parameters are ready */ | |
2817 | rtl92d_phy_reload_iqk_setting(hw, channel); | |
2818 | break; | |
2819 | default: | |
b8c79f45 LF |
2820 | pr_err("switch case %#x not processed\n", |
2821 | currentcmd->cmdid); | |
7274a8c2 CL |
2822 | break; |
2823 | } | |
2824 | break; | |
2825 | } while (true); | |
2826 | (*delay) = currentcmd->msdelay; | |
2827 | (*step)++; | |
2828 | return false; | |
2829 | } | |
2830 | ||
2831 | u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) | |
2832 | { | |
2833 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2834 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2835 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
2836 | u32 delay; | |
2837 | u32 timeout = 1000, timecount = 0; | |
2838 | u8 channel = rtlphy->current_channel; | |
2839 | u32 ret_value; | |
2840 | ||
2841 | if (rtlphy->sw_chnl_inprogress) | |
2842 | return 0; | |
2843 | if (rtlphy->set_bwmode_inprogress) | |
2844 | return 0; | |
2845 | ||
2846 | if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { | |
2847 | RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, | |
f30d7507 | 2848 | "sw_chnl_inprogress false driver sleep or unload\n"); |
7274a8c2 CL |
2849 | return 0; |
2850 | } | |
2851 | while (rtlphy->lck_inprogress && timecount < timeout) { | |
2852 | mdelay(50); | |
2853 | timecount += 50; | |
2854 | } | |
2855 | if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && | |
2856 | rtlhal->bandset == BAND_ON_BOTH) { | |
2857 | ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, | |
25b13dbc | 2858 | MASKDWORD); |
7274a8c2 CL |
2859 | if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) |
2860 | rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); | |
2861 | else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) | |
2862 | rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G); | |
2863 | } | |
2864 | switch (rtlhal->current_bandtype) { | |
2865 | case BAND_ON_5G: | |
2866 | /* Get first channel error when change between | |
2867 | * 5G and 2.4G band. */ | |
2868 | if (channel <= 14) | |
2869 | return 0; | |
531940f9 | 2870 | WARN_ONCE((channel <= 14), "rtl8192de: 5G but channel<=14\n"); |
7274a8c2 CL |
2871 | break; |
2872 | case BAND_ON_2_4G: | |
2873 | /* Get first channel error when change between | |
2874 | * 5G and 2.4G band. */ | |
2875 | if (channel > 14) | |
2876 | return 0; | |
531940f9 | 2877 | WARN_ONCE((channel > 14), "rtl8192de: 2G but channel>14\n"); |
7274a8c2 CL |
2878 | break; |
2879 | default: | |
531940f9 | 2880 | WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n", |
9d833ed7 | 2881 | rtlpriv->mac80211.mode); |
7274a8c2 CL |
2882 | break; |
2883 | } | |
2884 | rtlphy->sw_chnl_inprogress = true; | |
2885 | if (channel == 0) | |
2886 | channel = 1; | |
2887 | rtlphy->sw_chnl_stage = 0; | |
2888 | rtlphy->sw_chnl_step = 0; | |
2889 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, | |
f30d7507 | 2890 | "switch to channel%d\n", rtlphy->current_channel); |
7274a8c2 CL |
2891 | |
2892 | do { | |
2893 | if (!rtlphy->sw_chnl_inprogress) | |
2894 | break; | |
2895 | if (!_rtl92d_phy_sw_chnl_step_by_step(hw, | |
2896 | rtlphy->current_channel, | |
2897 | &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) { | |
2898 | if (delay > 0) | |
2899 | mdelay(delay); | |
2900 | else | |
2901 | continue; | |
2902 | } else { | |
2903 | rtlphy->sw_chnl_inprogress = false; | |
2904 | } | |
2905 | break; | |
2906 | } while (true); | |
f30d7507 | 2907 | RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); |
7274a8c2 CL |
2908 | rtlphy->sw_chnl_inprogress = false; |
2909 | return 1; | |
2910 | } | |
2911 | ||
2912 | static void rtl92d_phy_set_io(struct ieee80211_hw *hw) | |
2913 | { | |
2914 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
c21916ec | 2915 | struct dig_t *de_digtable = &rtlpriv->dm_digtable; |
7274a8c2 CL |
2916 | struct rtl_phy *rtlphy = &(rtlpriv->phy); |
2917 | ||
2918 | RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, | |
f30d7507 JP |
2919 | "--->Cmd(%#x), set_io_inprogress(%d)\n", |
2920 | rtlphy->current_io_type, rtlphy->set_io_inprogress); | |
7274a8c2 CL |
2921 | switch (rtlphy->current_io_type) { |
2922 | case IO_CMD_RESUME_DM_BY_SCAN: | |
c21916ec | 2923 | de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; |
7274a8c2 CL |
2924 | rtl92d_dm_write_dig(hw); |
2925 | rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); | |
2926 | break; | |
2927 | case IO_CMD_PAUSE_DM_BY_SCAN: | |
c21916ec LF |
2928 | rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; |
2929 | de_digtable->cur_igvalue = 0x37; | |
7274a8c2 CL |
2930 | rtl92d_dm_write_dig(hw); |
2931 | break; | |
2932 | default: | |
b8c79f45 LF |
2933 | pr_err("switch case %#x not processed\n", |
2934 | rtlphy->current_io_type); | |
7274a8c2 CL |
2935 | break; |
2936 | } | |
2937 | rtlphy->set_io_inprogress = false; | |
f30d7507 JP |
2938 | RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", |
2939 | rtlphy->current_io_type); | |
7274a8c2 CL |
2940 | } |
2941 | ||
2942 | bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) | |
2943 | { | |
2944 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2945 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2946 | bool postprocessing = false; | |
2947 | ||
2948 | RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, | |
f30d7507 JP |
2949 | "-->IO Cmd(%#x), set_io_inprogress(%d)\n", |
2950 | iotype, rtlphy->set_io_inprogress); | |
7274a8c2 CL |
2951 | do { |
2952 | switch (iotype) { | |
2953 | case IO_CMD_RESUME_DM_BY_SCAN: | |
2954 | RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, | |
f30d7507 | 2955 | "[IO CMD] Resume DM after scan\n"); |
7274a8c2 CL |
2956 | postprocessing = true; |
2957 | break; | |
2958 | case IO_CMD_PAUSE_DM_BY_SCAN: | |
2959 | RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, | |
f30d7507 | 2960 | "[IO CMD] Pause DM before scan\n"); |
7274a8c2 CL |
2961 | postprocessing = true; |
2962 | break; | |
2963 | default: | |
b8c79f45 LF |
2964 | pr_err("switch case %#x not processed\n", |
2965 | iotype); | |
7274a8c2 CL |
2966 | break; |
2967 | } | |
2968 | } while (false); | |
2969 | if (postprocessing && !rtlphy->set_io_inprogress) { | |
2970 | rtlphy->set_io_inprogress = true; | |
2971 | rtlphy->current_io_type = iotype; | |
2972 | } else { | |
2973 | return false; | |
2974 | } | |
2975 | rtl92d_phy_set_io(hw); | |
f30d7507 | 2976 | RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); |
7274a8c2 CL |
2977 | return true; |
2978 | } | |
2979 | ||
2980 | static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) | |
2981 | { | |
2982 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2983 | ||
2984 | /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ | |
2985 | /* b. SPS_CTRL 0x11[7:0] = 0x2b */ | |
2986 | if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) | |
2987 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); | |
2988 | /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ | |
2989 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); | |
2990 | /* RF_ON_EXCEP(d~g): */ | |
2991 | /* d. APSD_CTRL 0x600[7:0] = 0x00 */ | |
2992 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); | |
2993 | /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ | |
2994 | /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ | |
2995 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); | |
2996 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); | |
2997 | /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ | |
2998 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); | |
2999 | } | |
3000 | ||
3001 | static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw) | |
3002 | { | |
3003 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3004 | u32 u4btmp; | |
3005 | u8 delay = 5; | |
3006 | ||
3007 | /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ | |
3008 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); | |
3009 | /* b. RF path 0 offset 0x00 = 0x00 disable RF */ | |
25b13dbc | 3010 | rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); |
7274a8c2 CL |
3011 | /* c. APSD_CTRL 0x600[7:0] = 0x40 */ |
3012 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); | |
3013 | /* d. APSD_CTRL 0x600[7:0] = 0x00 | |
3014 | * APSD_CTRL 0x600[7:0] = 0x00 | |
3015 | * RF path 0 offset 0x00 = 0x00 | |
3016 | * APSD_CTRL 0x600[7:0] = 0x40 | |
3017 | * */ | |
25b13dbc | 3018 | u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); |
7274a8c2 CL |
3019 | while (u4btmp != 0 && delay > 0) { |
3020 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); | |
25b13dbc | 3021 | rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); |
7274a8c2 | 3022 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); |
25b13dbc | 3023 | u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); |
7274a8c2 CL |
3024 | delay--; |
3025 | } | |
3026 | if (delay == 0) { | |
3027 | /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ | |
3028 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); | |
3029 | ||
3030 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); | |
3031 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); | |
3032 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); | |
3033 | RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, | |
f30d7507 | 3034 | "Fail !!! Switch RF timeout\n"); |
7274a8c2 CL |
3035 | return; |
3036 | } | |
3037 | /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ | |
3038 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); | |
3039 | /* f. SPS_CTRL 0x11[7:0] = 0x22 */ | |
3040 | if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) | |
3041 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); | |
3042 | /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ | |
3043 | } | |
3044 | ||
3045 | bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, | |
3046 | enum rf_pwrstate rfpwr_state) | |
3047 | { | |
3048 | ||
3049 | bool bresult = true; | |
3050 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3051 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
3052 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
3053 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
3054 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
3055 | u8 i, queue_id; | |
3056 | struct rtl8192_tx_ring *ring = NULL; | |
3057 | ||
3058 | if (rfpwr_state == ppsc->rfpwr_state) | |
3059 | return false; | |
3060 | switch (rfpwr_state) { | |
3061 | case ERFON: | |
3062 | if ((ppsc->rfpwr_state == ERFOFF) && | |
3063 | RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { | |
3064 | bool rtstatus; | |
b83faeda | 3065 | u32 initializecount = 0; |
7274a8c2 | 3066 | do { |
b83faeda | 3067 | initializecount++; |
7274a8c2 | 3068 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, |
f30d7507 | 3069 | "IPS Set eRf nic enable\n"); |
7274a8c2 | 3070 | rtstatus = rtl_ps_enable_nic(hw); |
b83faeda | 3071 | } while (!rtstatus && (initializecount < 10)); |
7274a8c2 CL |
3072 | |
3073 | RT_CLEAR_PS_LEVEL(ppsc, | |
3074 | RT_RF_OFF_LEVL_HALT_NIC); | |
3075 | } else { | |
3076 | RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, | |
f30d7507 | 3077 | "awake, sleeped:%d ms state_inap:%x\n", |
7274a8c2 | 3078 | jiffies_to_msecs(jiffies - |
f30d7507 JP |
3079 | ppsc->last_sleep_jiffies), |
3080 | rtlpriv->psc.state_inap); | |
7274a8c2 CL |
3081 | ppsc->last_awake_jiffies = jiffies; |
3082 | _rtl92d_phy_set_rfon(hw); | |
3083 | } | |
3084 | ||
3085 | if (mac->link_state == MAC80211_LINKED) | |
3086 | rtlpriv->cfg->ops->led_control(hw, | |
3087 | LED_CTL_LINK); | |
3088 | else | |
3089 | rtlpriv->cfg->ops->led_control(hw, | |
3090 | LED_CTL_NO_LINK); | |
3091 | break; | |
3092 | case ERFOFF: | |
3093 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { | |
3094 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, | |
f30d7507 | 3095 | "IPS Set eRf nic disable\n"); |
7274a8c2 CL |
3096 | rtl_ps_disable_nic(hw); |
3097 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
3098 | } else { | |
3099 | if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) | |
3100 | rtlpriv->cfg->ops->led_control(hw, | |
3101 | LED_CTL_NO_LINK); | |
3102 | else | |
3103 | rtlpriv->cfg->ops->led_control(hw, | |
3104 | LED_CTL_POWER_OFF); | |
3105 | } | |
3106 | break; | |
3107 | case ERFSLEEP: | |
3108 | if (ppsc->rfpwr_state == ERFOFF) | |
91ddff8a | 3109 | return false; |
7274a8c2 CL |
3110 | |
3111 | for (queue_id = 0, i = 0; | |
3112 | queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { | |
3113 | ring = &pcipriv->dev.tx_ring[queue_id]; | |
3114 | if (skb_queue_len(&ring->queue) == 0 || | |
3115 | queue_id == BEACON_QUEUE) { | |
3116 | queue_id++; | |
3117 | continue; | |
3118 | } else if (rtlpci->pdev->current_state != PCI_D0) { | |
3119 | RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, | |
f30d7507 JP |
3120 | "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", |
3121 | i + 1, queue_id); | |
7274a8c2 CL |
3122 | break; |
3123 | } else { | |
3124 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
3125 | "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", |
3126 | i + 1, queue_id, | |
3127 | skb_queue_len(&ring->queue)); | |
7274a8c2 CL |
3128 | udelay(10); |
3129 | i++; | |
3130 | } | |
3131 | ||
3132 | if (i >= MAX_DOZE_WAITING_TIMES_9x) { | |
3133 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
3134 | "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", |
3135 | MAX_DOZE_WAITING_TIMES_9x, queue_id, | |
3136 | skb_queue_len(&ring->queue)); | |
7274a8c2 CL |
3137 | break; |
3138 | } | |
3139 | } | |
3140 | RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, | |
f30d7507 JP |
3141 | "Set rfsleep awaked:%d ms\n", |
3142 | jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); | |
3143 | RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, | |
3144 | "sleep awaked:%d ms state_inap:%x\n", | |
3145 | jiffies_to_msecs(jiffies - | |
3146 | ppsc->last_awake_jiffies), | |
3147 | rtlpriv->psc.state_inap); | |
7274a8c2 CL |
3148 | ppsc->last_sleep_jiffies = jiffies; |
3149 | _rtl92d_phy_set_rfsleep(hw); | |
3150 | break; | |
3151 | default: | |
b8c79f45 LF |
3152 | pr_err("switch case %#x not processed\n", |
3153 | rfpwr_state); | |
7274a8c2 CL |
3154 | bresult = false; |
3155 | break; | |
3156 | } | |
3157 | if (bresult) | |
3158 | ppsc->rfpwr_state = rfpwr_state; | |
3159 | return bresult; | |
3160 | } | |
3161 | ||
3162 | void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) | |
3163 | { | |
3164 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3165 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
3166 | u8 offset = REG_MAC_PHY_CTRL_NORMAL; | |
3167 | ||
3168 | switch (rtlhal->macphymode) { | |
3169 | case DUALMAC_DUALPHY: | |
3170 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 3171 | "MacPhyMode: DUALMAC_DUALPHY\n"); |
7274a8c2 CL |
3172 | rtl_write_byte(rtlpriv, offset, 0xF3); |
3173 | break; | |
3174 | case SINGLEMAC_SINGLEPHY: | |
3175 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 3176 | "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); |
7274a8c2 CL |
3177 | rtl_write_byte(rtlpriv, offset, 0xF4); |
3178 | break; | |
3179 | case DUALMAC_SINGLEPHY: | |
3180 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 3181 | "MacPhyMode: DUALMAC_SINGLEPHY\n"); |
7274a8c2 CL |
3182 | rtl_write_byte(rtlpriv, offset, 0xF1); |
3183 | break; | |
3184 | } | |
3185 | } | |
3186 | ||
3187 | void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) | |
3188 | { | |
3189 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3190 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
3191 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
3192 | ||
3193 | switch (rtlhal->macphymode) { | |
3194 | case DUALMAC_SINGLEPHY: | |
3195 | rtlphy->rf_type = RF_2T2R; | |
f1b00f4d | 3196 | rtlhal->version |= RF_TYPE_2T2R; |
7274a8c2 CL |
3197 | rtlhal->bandset = BAND_ON_BOTH; |
3198 | rtlhal->current_bandtype = BAND_ON_2_4G; | |
3199 | break; | |
3200 | ||
3201 | case SINGLEMAC_SINGLEPHY: | |
3202 | rtlphy->rf_type = RF_2T2R; | |
f1b00f4d | 3203 | rtlhal->version |= RF_TYPE_2T2R; |
7274a8c2 CL |
3204 | rtlhal->bandset = BAND_ON_BOTH; |
3205 | rtlhal->current_bandtype = BAND_ON_2_4G; | |
3206 | break; | |
3207 | ||
3208 | case DUALMAC_DUALPHY: | |
3209 | rtlphy->rf_type = RF_1T1R; | |
f1b00f4d | 3210 | rtlhal->version &= RF_TYPE_1T1R; |
7274a8c2 CL |
3211 | /* Now we let MAC0 run on 5G band. */ |
3212 | if (rtlhal->interfaceindex == 0) { | |
3213 | rtlhal->bandset = BAND_ON_5G; | |
3214 | rtlhal->current_bandtype = BAND_ON_5G; | |
3215 | } else { | |
3216 | rtlhal->bandset = BAND_ON_2_4G; | |
3217 | rtlhal->current_bandtype = BAND_ON_2_4G; | |
3218 | } | |
3219 | break; | |
3220 | default: | |
3221 | break; | |
3222 | } | |
3223 | } | |
3224 | ||
3225 | u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) | |
3226 | { | |
3227 | u8 group; | |
3228 | u8 channel_info[59] = { | |
3229 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
3230 | 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, | |
3231 | 58, 60, 62, 64, 100, 102, 104, 106, 108, | |
3232 | 110, 112, 114, 116, 118, 120, 122, 124, | |
3233 | 126, 128, 130, 132, 134, 136, 138, 140, | |
3234 | 149, 151, 153, 155, 157, 159, 161, 163, | |
3235 | 165 | |
3236 | }; | |
3237 | ||
3238 | if (channel_info[chnl] <= 3) | |
3239 | group = 0; | |
3240 | else if (channel_info[chnl] <= 9) | |
3241 | group = 1; | |
3242 | else if (channel_info[chnl] <= 14) | |
3243 | group = 2; | |
3244 | else if (channel_info[chnl] <= 44) | |
3245 | group = 3; | |
3246 | else if (channel_info[chnl] <= 54) | |
3247 | group = 4; | |
3248 | else if (channel_info[chnl] <= 64) | |
3249 | group = 5; | |
3250 | else if (channel_info[chnl] <= 112) | |
3251 | group = 6; | |
3252 | else if (channel_info[chnl] <= 126) | |
3253 | group = 7; | |
3254 | else if (channel_info[chnl] <= 140) | |
3255 | group = 8; | |
3256 | else if (channel_info[chnl] <= 153) | |
3257 | group = 9; | |
3258 | else if (channel_info[chnl] <= 159) | |
3259 | group = 10; | |
3260 | else | |
3261 | group = 11; | |
3262 | return group; | |
3263 | } | |
3264 | ||
3265 | void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) | |
3266 | { | |
3267 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3268 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
3269 | unsigned long flags; | |
3270 | u8 value8; | |
3271 | u16 i; | |
3272 | u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); | |
3273 | ||
3274 | /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ | |
3275 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
3276 | value8 = rtl_read_byte(rtlpriv, mac_reg); | |
3277 | value8 |= BIT(1); | |
3278 | rtl_write_byte(rtlpriv, mac_reg, value8); | |
3279 | } else { | |
3280 | value8 = rtl_read_byte(rtlpriv, mac_reg); | |
3281 | value8 &= (~BIT(1)); | |
3282 | rtl_write_byte(rtlpriv, mac_reg, value8); | |
3283 | } | |
3284 | ||
3285 | if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { | |
3286 | value8 = rtl_read_byte(rtlpriv, REG_MAC0); | |
3287 | rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); | |
3288 | } else { | |
3289 | spin_lock_irqsave(&globalmutex_power, flags); | |
3290 | if (rtlhal->interfaceindex == 0) { | |
3291 | value8 = rtl_read_byte(rtlpriv, REG_MAC0); | |
3292 | rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); | |
3293 | } else { | |
3294 | value8 = rtl_read_byte(rtlpriv, REG_MAC1); | |
3295 | rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); | |
3296 | } | |
3297 | value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); | |
3298 | spin_unlock_irqrestore(&globalmutex_power, flags); | |
3299 | for (i = 0; i < 200; i++) { | |
3300 | if ((value8 & BIT(7)) == 0) { | |
3301 | break; | |
3302 | } else { | |
3303 | udelay(500); | |
3304 | spin_lock_irqsave(&globalmutex_power, flags); | |
3305 | value8 = rtl_read_byte(rtlpriv, | |
3306 | REG_POWER_OFF_IN_PROCESS); | |
3307 | spin_unlock_irqrestore(&globalmutex_power, | |
3308 | flags); | |
3309 | } | |
3310 | } | |
3311 | if (i == 200) | |
531940f9 | 3312 | WARN_ONCE(true, "rtl8192de: Another mac power off over time\n"); |
7274a8c2 CL |
3313 | } |
3314 | } | |
3315 | ||
3316 | void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) | |
3317 | { | |
3318 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3319 | ||
3320 | switch (rtlpriv->rtlhal.macphymode) { | |
3321 | case DUALMAC_DUALPHY: | |
3322 | rtl_write_byte(rtlpriv, REG_DMC, 0x0); | |
3323 | rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); | |
3324 | rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); | |
3325 | break; | |
3326 | case DUALMAC_SINGLEPHY: | |
3327 | rtl_write_byte(rtlpriv, REG_DMC, 0xf8); | |
3328 | rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); | |
3329 | rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); | |
3330 | break; | |
3331 | case SINGLEMAC_SINGLEPHY: | |
3332 | rtl_write_byte(rtlpriv, REG_DMC, 0x0); | |
3333 | rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); | |
3334 | rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); | |
3335 | break; | |
3336 | default: | |
3337 | break; | |
3338 | } | |
3339 | } | |
3340 | ||
3341 | void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) | |
3342 | { | |
3343 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3344 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
3345 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
3346 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
3347 | u8 rfpath, i; | |
3348 | ||
f30d7507 | 3349 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); |
7274a8c2 CL |
3350 | /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ |
3351 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
3352 | /* r_select_5G for path_A/B,0x878 */ | |
3353 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); | |
3354 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); | |
3355 | if (rtlhal->macphymode != DUALMAC_DUALPHY) { | |
3356 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); | |
3357 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); | |
3358 | } | |
3359 | /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ | |
3360 | rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); | |
3361 | /* fc_area 0xd2c */ | |
3362 | rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); | |
3363 | /* 5G LAN ON */ | |
3364 | rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); | |
3365 | /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ | |
b83faeda | 3366 | rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, |
7274a8c2 | 3367 | 0x40000100); |
b83faeda | 3368 | rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, |
7274a8c2 CL |
3369 | 0x40000100); |
3370 | if (rtlhal->macphymode == DUALMAC_DUALPHY) { | |
3371 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, | |
3372 | BIT(10) | BIT(6) | BIT(5), | |
3373 | ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | | |
3374 | (rtlefuse->eeprom_c9 & BIT(1)) | | |
3375 | ((rtlefuse->eeprom_cc & BIT(1)) << 4)); | |
3376 | rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, | |
3377 | BIT(10) | BIT(6) | BIT(5), | |
3378 | ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | | |
3379 | ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | | |
3380 | ((rtlefuse->eeprom_cc & BIT(0)) << 5)); | |
3381 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); | |
3382 | } else { | |
3383 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, | |
3384 | BIT(26) | BIT(22) | BIT(21) | BIT(10) | | |
3385 | BIT(6) | BIT(5), | |
3386 | ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | | |
3387 | (rtlefuse->eeprom_c9 & BIT(1)) | | |
3388 | ((rtlefuse->eeprom_cc & BIT(1)) << 4) | | |
3389 | ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | | |
3390 | ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | | |
3391 | ((rtlefuse->eeprom_cc & BIT(3)) << 18)); | |
3392 | rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, | |
3393 | BIT(10) | BIT(6) | BIT(5), | |
3394 | ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | | |
3395 | ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | | |
3396 | ((rtlefuse->eeprom_cc & BIT(0)) << 5)); | |
3397 | rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, | |
3398 | BIT(10) | BIT(6) | BIT(5), | |
3399 | ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | | |
3400 | ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | | |
3401 | ((rtlefuse->eeprom_cc & BIT(2)) << 3)); | |
3402 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, | |
3403 | BIT(31) | BIT(15), 0); | |
3404 | } | |
3405 | /* 1.5V_LDO */ | |
3406 | } else { | |
3407 | /* r_select_5G for path_A/B */ | |
3408 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); | |
3409 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); | |
3410 | if (rtlhal->macphymode != DUALMAC_DUALPHY) { | |
3411 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); | |
3412 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); | |
3413 | } | |
3414 | /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ | |
3415 | rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); | |
3416 | /* fc_area */ | |
3417 | rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); | |
3418 | /* 5G LAN ON */ | |
3419 | rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); | |
3420 | /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ | |
3421 | if (rtlefuse->internal_pa_5g[0]) | |
b83faeda | 3422 | rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, |
7274a8c2 CL |
3423 | 0x2d4000b5); |
3424 | else | |
b83faeda | 3425 | rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, |
7274a8c2 CL |
3426 | 0x20000080); |
3427 | if (rtlefuse->internal_pa_5g[1]) | |
b83faeda | 3428 | rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, |
7274a8c2 CL |
3429 | 0x2d4000b5); |
3430 | else | |
b83faeda | 3431 | rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, |
7274a8c2 CL |
3432 | 0x20000080); |
3433 | if (rtlhal->macphymode == DUALMAC_DUALPHY) { | |
3434 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, | |
3435 | BIT(10) | BIT(6) | BIT(5), | |
3436 | (rtlefuse->eeprom_cc & BIT(5))); | |
3437 | rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), | |
3438 | ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); | |
3439 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), | |
3440 | (rtlefuse->eeprom_cc & BIT(4)) >> 4); | |
3441 | } else { | |
3442 | rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, | |
3443 | BIT(26) | BIT(22) | BIT(21) | BIT(10) | | |
3444 | BIT(6) | BIT(5), | |
3445 | (rtlefuse->eeprom_cc & BIT(5)) | | |
3446 | ((rtlefuse->eeprom_cc & BIT(7)) << 14)); | |
3447 | rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), | |
3448 | ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); | |
3449 | rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), | |
3450 | ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); | |
3451 | rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, | |
3452 | BIT(31) | BIT(15), | |
3453 | ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | | |
3454 | ((rtlefuse->eeprom_cc & BIT(6)) << 10)); | |
3455 | } | |
3456 | } | |
3457 | /* update IQK related settings */ | |
25b13dbc LF |
3458 | rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); |
3459 | rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); | |
b83faeda | 3460 | rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); |
7274a8c2 CL |
3461 | rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | |
3462 | BIT(26) | BIT(24), 0x00); | |
b83faeda | 3463 | rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); |
7274a8c2 CL |
3464 | rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); |
3465 | rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); | |
3466 | ||
3467 | /* Update RF */ | |
3468 | for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; | |
3469 | rfpath++) { | |
3470 | if (rtlhal->current_bandtype == BAND_ON_2_4G) { | |
33b8261e | 3471 | /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ |
7274a8c2 CL |
3472 | rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | |
3473 | BIT(18), 0); | |
3474 | /* RF0x0b[16:14] =3b'111 */ | |
3475 | rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, | |
3476 | 0x1c000, 0x07); | |
3477 | } else { | |
33b8261e | 3478 | /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ |
7274a8c2 CL |
3479 | rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | |
3480 | BIT(16) | BIT(18), | |
3481 | (BIT(16) | BIT(8)) >> 8); | |
3482 | } | |
3483 | } | |
3484 | /* Update for all band. */ | |
3485 | /* DMDP */ | |
3486 | if (rtlphy->rf_type == RF_1T1R) { | |
3487 | /* Use antenna 0,0xc04,0xd04 */ | |
25b13dbc | 3488 | rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); |
7274a8c2 CL |
3489 | rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); |
3490 | ||
3491 | /* enable ad/da clock1 for dual-phy reg0x888 */ | |
3492 | if (rtlhal->interfaceindex == 0) { | |
3493 | rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | | |
3494 | BIT(13), 0x3); | |
3495 | } else { | |
3496 | rtl92d_phy_enable_anotherphy(hw, false); | |
3497 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 3498 | "MAC1 use DBI to update 0x888\n"); |
7274a8c2 CL |
3499 | /* 0x888 */ |
3500 | rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN, | |
3501 | rtl92de_read_dword_dbi(hw, | |
3502 | RFPGA0_ADDALLOCKEN, | |
3503 | BIT(3)) | BIT(12) | BIT(13), | |
3504 | BIT(3)); | |
3505 | rtl92d_phy_powerdown_anotherphy(hw, false); | |
3506 | } | |
3507 | } else { | |
3508 | /* Single PHY */ | |
3509 | /* Use antenna 0 & 1,0xc04,0xd04 */ | |
25b13dbc | 3510 | rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); |
7274a8c2 CL |
3511 | rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); |
3512 | /* disable ad/da clock1,0x888 */ | |
3513 | rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); | |
3514 | } | |
3515 | for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; | |
3516 | rfpath++) { | |
3517 | rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, | |
25b13dbc | 3518 | RF_CHNLBW, RFREG_OFFSET_MASK); |
7274a8c2 | 3519 | rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, |
25b13dbc | 3520 | RFREG_OFFSET_MASK); |
7274a8c2 CL |
3521 | } |
3522 | for (i = 0; i < 2; i++) | |
f30d7507 JP |
3523 | RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", |
3524 | rtlphy->rfreg_chnlval[i]); | |
3525 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); | |
7274a8c2 CL |
3526 | |
3527 | } | |
3528 | ||
3529 | bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw) | |
3530 | { | |
3531 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
3532 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
3533 | u8 u1btmp; | |
3534 | unsigned long flags; | |
3535 | ||
3536 | if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { | |
3537 | u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); | |
3538 | rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); | |
3539 | return true; | |
3540 | } | |
3541 | spin_lock_irqsave(&globalmutex_power, flags); | |
3542 | if (rtlhal->interfaceindex == 0) { | |
3543 | u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); | |
3544 | rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); | |
3545 | u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); | |
3546 | u1btmp &= MAC1_ON; | |
3547 | } else { | |
3548 | u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); | |
3549 | rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON)); | |
3550 | u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); | |
3551 | u1btmp &= MAC0_ON; | |
3552 | } | |
3553 | if (u1btmp) { | |
3554 | spin_unlock_irqrestore(&globalmutex_power, flags); | |
3555 | return false; | |
3556 | } | |
3557 | u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); | |
3558 | u1btmp |= BIT(7); | |
3559 | rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); | |
3560 | spin_unlock_irqrestore(&globalmutex_power, flags); | |
3561 | return true; | |
3562 | } |