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e3037485 YHC |
1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2018-2019 Realtek Corporation | |
3 | */ | |
4 | ||
5 | #ifndef __RTK_PCI_H_ | |
6 | #define __RTK_PCI_H_ | |
7 | ||
2e86ef41 LJ |
8 | #include "main.h" |
9 | ||
e3037485 YHC |
10 | #define RTK_DEFAULT_TX_DESC_NUM 128 |
11 | #define RTK_BEQ_TX_DESC_NUM 256 | |
12 | ||
13 | #define RTK_MAX_RX_DESC_NUM 512 | |
ee755732 TEH |
14 | /* 11K + rx desc size */ |
15 | #define RTK_PCI_RX_BUF_SIZE (11454 + 24) | |
e3037485 YHC |
16 | |
17 | #define RTK_PCI_CTRL 0x300 | |
18 | #define BIT_RST_TRXDMA_INTF BIT(20) | |
19 | #define BIT_RX_TAG_EN BIT(15) | |
20 | #define REG_DBI_WDATA_V1 0x03E8 | |
d2e2c47e | 21 | #define REG_DBI_RDATA_V1 0x03EC |
e3037485 | 22 | #define REG_DBI_FLAG_V1 0x03F0 |
83a5a2d7 YHC |
23 | #define BIT_DBI_RFLAG BIT(17) |
24 | #define BIT_DBI_WFLAG BIT(16) | |
25 | #define BITS_DBI_WREN GENMASK(15, 12) | |
26 | #define BITS_DBI_ADDR_MASK GENMASK(11, 2) | |
27 | ||
e3037485 YHC |
28 | #define REG_MDIO_V1 0x03F4 |
29 | #define REG_PCIE_MIX_CFG 0x03F8 | |
83a5a2d7 | 30 | #define BITS_MDIO_ADDR_MASK GENMASK(4, 0) |
e3037485 | 31 | #define BIT_MDIO_WFLAG_V1 BIT(5) |
83a5a2d7 YHC |
32 | #define RTW_PCI_MDIO_PG_SZ BIT(5) |
33 | #define RTW_PCI_MDIO_PG_OFFS_G1 0 | |
34 | #define RTW_PCI_MDIO_PG_OFFS_G2 2 | |
35 | #define RTW_PCI_WR_RETRY_CNT 20 | |
e3037485 | 36 | |
d2e2c47e YHC |
37 | #define RTK_PCIE_LINK_CFG 0x0719 |
38 | #define BIT_CLKREQ_SW_EN BIT(4) | |
3dff7c6e | 39 | #define BIT_L1_SW_EN BIT(3) |
8d52b46c | 40 | #define BIT_CLKREQ_N_PAD BIT(0) |
2a422555 | 41 | #define RTK_PCIE_CLKDLY_CTRL 0x0725 |
d2e2c47e | 42 | |
e3037485 YHC |
43 | #define BIT_PCI_BCNQ_FLAG BIT(4) |
44 | #define RTK_PCI_TXBD_DESA_BCNQ 0x308 | |
45 | #define RTK_PCI_TXBD_DESA_H2CQ 0x1320 | |
46 | #define RTK_PCI_TXBD_DESA_MGMTQ 0x310 | |
47 | #define RTK_PCI_TXBD_DESA_BKQ 0x330 | |
48 | #define RTK_PCI_TXBD_DESA_BEQ 0x328 | |
49 | #define RTK_PCI_TXBD_DESA_VIQ 0x320 | |
50 | #define RTK_PCI_TXBD_DESA_VOQ 0x318 | |
51 | #define RTK_PCI_TXBD_DESA_HI0Q 0x340 | |
52 | #define RTK_PCI_RXBD_DESA_MPDUQ 0x338 | |
53 | ||
a5697a65 | 54 | #define TRX_BD_IDX_MASK GENMASK(11, 0) |
9e2fd298 | 55 | #define TRX_BD_HW_IDX_MASK GENMASK(27, 16) |
a5697a65 | 56 | |
e3037485 YHC |
57 | /* BCNQ is specialized for rsvd page, does not need to specify a number */ |
58 | #define RTK_PCI_TXBD_NUM_H2CQ 0x1328 | |
59 | #define RTK_PCI_TXBD_NUM_MGMTQ 0x380 | |
60 | #define RTK_PCI_TXBD_NUM_BKQ 0x38A | |
61 | #define RTK_PCI_TXBD_NUM_BEQ 0x388 | |
62 | #define RTK_PCI_TXBD_NUM_VIQ 0x386 | |
63 | #define RTK_PCI_TXBD_NUM_VOQ 0x384 | |
64 | #define RTK_PCI_TXBD_NUM_HI0Q 0x38C | |
65 | #define RTK_PCI_RXBD_NUM_MPDUQ 0x382 | |
66 | #define RTK_PCI_TXBD_IDX_H2CQ 0x132C | |
67 | #define RTK_PCI_TXBD_IDX_MGMTQ 0x3B0 | |
68 | #define RTK_PCI_TXBD_IDX_BKQ 0x3AC | |
69 | #define RTK_PCI_TXBD_IDX_BEQ 0x3A8 | |
70 | #define RTK_PCI_TXBD_IDX_VIQ 0x3A4 | |
71 | #define RTK_PCI_TXBD_IDX_VOQ 0x3A0 | |
72 | #define RTK_PCI_TXBD_IDX_HI0Q 0x3B8 | |
73 | #define RTK_PCI_RXBD_IDX_MPDUQ 0x3B4 | |
74 | ||
75 | #define RTK_PCI_TXBD_RWPTR_CLR 0x39C | |
76 | #define RTK_PCI_TXBD_H2CQ_CSR 0x1330 | |
77 | ||
78 | #define BIT_CLR_H2CQ_HOST_IDX BIT(16) | |
79 | #define BIT_CLR_H2CQ_HW_IDX BIT(8) | |
80 | ||
81 | #define RTK_PCI_HIMR0 0x0B0 | |
82 | #define RTK_PCI_HISR0 0x0B4 | |
83 | #define RTK_PCI_HIMR1 0x0B8 | |
84 | #define RTK_PCI_HISR1 0x0BC | |
85 | #define RTK_PCI_HIMR2 0x10B0 | |
86 | #define RTK_PCI_HISR2 0x10B4 | |
87 | #define RTK_PCI_HIMR3 0x10B8 | |
88 | #define RTK_PCI_HISR3 0x10BC | |
89 | /* IMR 0 */ | |
90 | #define IMR_TIMER2 BIT(31) | |
91 | #define IMR_TIMER1 BIT(30) | |
92 | #define IMR_PSTIMEOUT BIT(29) | |
93 | #define IMR_GTINT4 BIT(28) | |
94 | #define IMR_GTINT3 BIT(27) | |
95 | #define IMR_TBDER BIT(26) | |
96 | #define IMR_TBDOK BIT(25) | |
97 | #define IMR_TSF_BIT32_TOGGLE BIT(24) | |
98 | #define IMR_BCNDMAINT0 BIT(20) | |
99 | #define IMR_BCNDOK0 BIT(16) | |
100 | #define IMR_HSISR_IND_ON_INT BIT(15) | |
101 | #define IMR_BCNDMAINT_E BIT(14) | |
102 | #define IMR_ATIMEND BIT(12) | |
103 | #define IMR_HISR1_IND_INT BIT(11) | |
104 | #define IMR_C2HCMD BIT(10) | |
105 | #define IMR_CPWM2 BIT(9) | |
106 | #define IMR_CPWM BIT(8) | |
107 | #define IMR_HIGHDOK BIT(7) | |
108 | #define IMR_MGNTDOK BIT(6) | |
109 | #define IMR_BKDOK BIT(5) | |
110 | #define IMR_BEDOK BIT(4) | |
111 | #define IMR_VIDOK BIT(3) | |
112 | #define IMR_VODOK BIT(2) | |
113 | #define IMR_RDU BIT(1) | |
114 | #define IMR_ROK BIT(0) | |
115 | /* IMR 1 */ | |
116 | #define IMR_TXFIFO_TH_INT BIT(30) | |
117 | #define IMR_BTON_STS_UPDATE BIT(29) | |
118 | #define IMR_MCUERR BIT(28) | |
119 | #define IMR_BCNDMAINT7 BIT(27) | |
120 | #define IMR_BCNDMAINT6 BIT(26) | |
121 | #define IMR_BCNDMAINT5 BIT(25) | |
122 | #define IMR_BCNDMAINT4 BIT(24) | |
123 | #define IMR_BCNDMAINT3 BIT(23) | |
124 | #define IMR_BCNDMAINT2 BIT(22) | |
125 | #define IMR_BCNDMAINT1 BIT(21) | |
126 | #define IMR_BCNDOK7 BIT(20) | |
127 | #define IMR_BCNDOK6 BIT(19) | |
128 | #define IMR_BCNDOK5 BIT(18) | |
129 | #define IMR_BCNDOK4 BIT(17) | |
130 | #define IMR_BCNDOK3 BIT(16) | |
131 | #define IMR_BCNDOK2 BIT(15) | |
132 | #define IMR_BCNDOK1 BIT(14) | |
133 | #define IMR_ATIMEND_E BIT(13) | |
134 | #define IMR_ATIMEND BIT(12) | |
135 | #define IMR_TXERR BIT(11) | |
136 | #define IMR_RXERR BIT(10) | |
137 | #define IMR_TXFOVW BIT(9) | |
138 | #define IMR_RXFOVW BIT(8) | |
139 | #define IMR_CPU_MGQ_TXDONE BIT(5) | |
140 | #define IMR_PS_TIMER_C BIT(4) | |
141 | #define IMR_PS_TIMER_B BIT(3) | |
142 | #define IMR_PS_TIMER_A BIT(2) | |
143 | #define IMR_CPUMGQ_TX_TIMER BIT(1) | |
144 | /* IMR 3 */ | |
145 | #define IMR_H2CDOK BIT(16) | |
146 | ||
9e2fd298 PHH |
147 | enum rtw_pci_flags { |
148 | RTW_PCI_FLAG_NAPI_RUNNING, | |
149 | ||
150 | NUM_OF_RTW_PCI_FLAGS, | |
151 | }; | |
152 | ||
e3037485 YHC |
153 | /* one element is reserved to know if the ring is closed */ |
154 | static inline int avail_desc(u32 wp, u32 rp, u32 len) | |
155 | { | |
156 | if (rp > wp) | |
157 | return rp - wp - 1; | |
158 | else | |
159 | return len - wp + rp - 1; | |
160 | } | |
161 | ||
162 | #define RTK_PCI_TXBD_OWN_OFFSET 15 | |
163 | #define RTK_PCI_TXBD_BCN_WORK 0x383 | |
164 | ||
165 | struct rtw_pci_tx_buffer_desc { | |
166 | __le16 buf_size; | |
167 | __le16 psb_len; | |
168 | __le32 dma; | |
169 | }; | |
170 | ||
171 | struct rtw_pci_tx_data { | |
172 | dma_addr_t dma; | |
173 | u8 sn; | |
174 | }; | |
175 | ||
176 | struct rtw_pci_ring { | |
177 | u8 *head; | |
178 | dma_addr_t dma; | |
179 | ||
180 | u8 desc_size; | |
181 | ||
182 | u32 len; | |
183 | u32 wp; | |
184 | u32 rp; | |
185 | }; | |
186 | ||
187 | struct rtw_pci_tx_ring { | |
188 | struct rtw_pci_ring r; | |
189 | struct sk_buff_head queue; | |
190 | bool queue_stopped; | |
191 | }; | |
192 | ||
193 | struct rtw_pci_rx_buffer_desc { | |
194 | __le16 buf_size; | |
195 | __le16 total_pkt_size; | |
196 | __le32 dma; | |
197 | }; | |
198 | ||
199 | struct rtw_pci_rx_ring { | |
200 | struct rtw_pci_ring r; | |
201 | struct sk_buff *buf[RTK_MAX_RX_DESC_NUM]; | |
202 | }; | |
203 | ||
204 | #define RX_TAG_MAX 8192 | |
205 | ||
206 | struct rtw_pci { | |
207 | struct pci_dev *pdev; | |
208 | ||
57fb39e2 BN |
209 | /* Used for PCI interrupt. */ |
210 | spinlock_t hwirq_lock; | |
9e2fd298 | 211 | /* Used for PCI TX ring/queueing, and enable INT. */ |
e3037485 YHC |
212 | spinlock_t irq_lock; |
213 | u32 irq_mask[4]; | |
214 | bool irq_enabled; | |
7bd3760c | 215 | bool running; |
e3037485 | 216 | |
9e2fd298 PHH |
217 | /* napi structure */ |
218 | struct net_device netdev; | |
219 | struct napi_struct napi; | |
220 | ||
e3037485 | 221 | u16 rx_tag; |
aaab5d0e | 222 | DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM); |
e3037485 YHC |
223 | struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM]; |
224 | struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM]; | |
d2e2c47e | 225 | u16 link_ctrl; |
1a0cba8d KHF |
226 | atomic_t link_usage; |
227 | bool rx_no_aspm; | |
9e2fd298 | 228 | DECLARE_BITMAP(flags, NUM_OF_RTW_PCI_FLAGS); |
e3037485 YHC |
229 | |
230 | void __iomem *mmap; | |
231 | }; | |
232 | ||
91aeaf09 | 233 | extern const struct dev_pm_ops rtw_pm_ops; |
2e86ef41 LJ |
234 | |
235 | int rtw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); | |
236 | void rtw_pci_remove(struct pci_dev *pdev); | |
237 | void rtw_pci_shutdown(struct pci_dev *pdev); | |
238 | ||
bbdd1d85 | 239 | static inline u32 max_num_of_tx_queue(u8 queue) |
e3037485 YHC |
240 | { |
241 | u32 max_num; | |
242 | ||
243 | switch (queue) { | |
244 | case RTW_TX_QUEUE_BE: | |
245 | max_num = RTK_BEQ_TX_DESC_NUM; | |
246 | break; | |
247 | case RTW_TX_QUEUE_BCN: | |
248 | max_num = 1; | |
249 | break; | |
250 | default: | |
251 | max_num = RTK_DEFAULT_TX_DESC_NUM; | |
252 | break; | |
253 | } | |
254 | ||
255 | return max_num; | |
256 | } | |
257 | ||
258 | static inline struct | |
259 | rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb) | |
260 | { | |
261 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
262 | ||
263 | BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) > | |
264 | sizeof(info->status.status_driver_data)); | |
265 | ||
266 | return (struct rtw_pci_tx_data *)info->status.status_driver_data; | |
267 | } | |
268 | ||
269 | static inline | |
270 | struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring, | |
271 | u32 size) | |
272 | { | |
273 | u8 *buf_desc; | |
274 | ||
275 | buf_desc = ring->r.head + ring->r.wp * size; | |
276 | return (struct rtw_pci_tx_buffer_desc *)buf_desc; | |
277 | } | |
278 | ||
279 | #endif |