[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / realtek / rtw88 / phy.h

/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2018-2019  Realtek Corporation
 */

#ifndef __RTW_PHY_H_
#define __RTW_PHY_H_

#include "debug.h"

extern u8 rtw_cck_rates[];
extern u8 rtw_ofdm_rates[];
extern u8 rtw_ht_1s_rates[];
extern u8 rtw_ht_2s_rates[];
extern u8 rtw_vht_1s_rates[];
extern u8 rtw_vht_2s_rates[];
extern u8 *rtw_rate_section[];
extern u8 rtw_rate_size[];

void rtw_phy_init(struct rtw_dev *rtwdev);
void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
		    u32 addr, u32 mask);
u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
			 u32 addr, u32 mask);
bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
			       u32 addr, u32 mask, u32 data);
bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
			  u32 addr, u32 mask, u32 data);
bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
			      u32 addr, u32 mask, u32 data);
void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
		     u32 addr, u32 data);
void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
		     u32 addr, u32 data);
void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
		    u32 addr, u32 data);
void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
		    u32 addr, u32 data);
void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
void rtw_phy_load_tables(struct rtw_dev *rtwdev);
u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
			      enum rtw_bandwidth bw, u8 channel, u8 regd);
void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path);
bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
				      u8 path);
u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path);
s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
			       struct rtw_swing_table *swing_table,
			       u8 tbl_path, u8 therm_path, u8 delta);
bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev);
bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev);
void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
				struct rtw_swing_table *swing_table);
void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
			 struct rtw_rx_pkt_stat *pkt_stat);
void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev);

struct rtw_txpwr_lmt_cfg_pair {
	u8 regd;
	u8 band;
	u8 bw;
	u8 rs;
	u8 ch;
	s8 txpwr_lmt;
};

struct rtw_phy_pg_cfg_pair {
	u32 band;
	u32 rf_path;
	u32 tx_num;
	u32 addr;
	u32 bitmask;
	u32 data;
};

#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path)	\
const struct rtw_table name ## _tbl = {			\
	.data = name,					\
	.size = ARRAY_SIZE(name),			\
	.parse = rtw_parse_tbl_phy_cond,		\
	.do_cfg = cfg,					\
	.rf_path = path,				\
}

#define RTW_DECL_TABLE_PHY_COND(name, cfg)		\
	RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)

#define RTW_DECL_TABLE_RF_RADIO(name, path)		\
	RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)

#define RTW_DECL_TABLE_BB_PG(name)			\
const struct rtw_table name ## _tbl = {			\
	.data = name,					\
	.size = ARRAY_SIZE(name),			\
	.parse = rtw_parse_tbl_bb_pg,			\
}

#define RTW_DECL_TABLE_TXPWR_LMT(name)			\
const struct rtw_table name ## _tbl = {			\
	.data = name,					\
	.size = ARRAY_SIZE(name),			\
	.parse = rtw_parse_tbl_txpwr_lmt,		\
}

static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
{
	struct rtw_chip_info *chip = rtwdev->chip;
	struct rtw_efuse *efuse = &rtwdev->efuse;
	const struct rtw_rfe_def *rfe_def = NULL;

	if (chip->rfe_defs_size == 0)
		return NULL;

	if (efuse->rfe_option < chip->rfe_defs_size)
		rfe_def = &chip->rfe_defs[efuse->rfe_option];

	rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
	return rfe_def;
}

static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
{
	const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);

	if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
		rtw_err(rtwdev, "rfe %d isn't supported\n",
			rtwdev->efuse.rfe_option);
		return -ENODEV;
	}

	return 0;
}

void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);

struct rtw_power_params {
	u8 pwr_base;
	s8 pwr_offset;
	s8 pwr_limit;
	s8 pwr_remnant;
};

void
rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
			u8 rate, u8 bw, u8 ch, u8 regd,
			struct rtw_power_params *pwr_param);

enum rtw_phy_cck_pd_lv {
	CCK_PD_LV0,
	CCK_PD_LV1,
	CCK_PD_LV2,
	CCK_PD_LV3,
	CCK_PD_LV4,
	CCK_PD_LV_MAX,
};

#define	MASKBYTE0		0xff
#define	MASKBYTE1		0xff00
#define	MASKBYTE2		0xff0000
#define	MASKBYTE3		0xff000000
#define	MASKHWORD		0xffff0000
#define	MASKLWORD		0x0000ffff
#define	MASKDWORD		0xffffffff
#define RFREG_MASK		0xfffff

#define	MASK7BITS		0x7f
#define	MASK12BITS		0xfff
#define	MASKH4BITS		0xf0000000
#define	MASK20BITS		0xfffff
#define	MASK24BITS		0xffffff

#define MASKH3BYTES		0xffffff00
#define MASKL3BYTES		0x00ffffff
#define MASKBYTE2HIGHNIBBLE	0x00f00000
#define MASKBYTE3LOWNIBBLE	0x0f000000
#define	MASKL3BYTES		0x00ffffff

#define CCK_FA_AVG_RESET 0xffffffff

#define LSSI_READ_ADDR_MASK	0x7f800000
#define LSSI_READ_EDGE_MASK	0x80000000
#define LSSI_READ_DATA_MASK	0xfffff

#define RRSR_RATE_ORDER_MAX	0xfffff
#define RRSR_RATE_ORDER_CCK_LEN	4

#endif
Commit	Line	Data
e3037485 YHC	1	/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
	2	/* Copyright(c) 2018-2019 Realtek Corporation
	3	*/
	4
	5	#ifndef __RTW_PHY_H_
	6	#define __RTW_PHY_H_
	7
	8	#include "debug.h"
	9
	10	extern u8 rtw_cck_rates[];
	11	extern u8 rtw_ofdm_rates[];
	12	extern u8 rtw_ht_1s_rates[];
	13	extern u8 rtw_ht_2s_rates[];
	14	extern u8 rtw_vht_1s_rates[];
	15	extern u8 rtw_vht_2s_rates[];
	16	extern u8 *rtw_rate_section[];
	17	extern u8 rtw_rate_size[];
	18
	19	void rtw_phy_init(struct rtw_dev *rtwdev);
	20	void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
	21	u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
	22	u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
	23	u32 addr, u32 mask);
e0c27cdb PKS	24	u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
e0c27cdb PKS	25	u32 addr, u32 mask);
e3037485 YHC	26	bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
	27	u32 addr, u32 mask, u32 data);
	28	bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
	29	u32 addr, u32 mask, u32 data);
	30	bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
	31	u32 addr, u32 mask, u32 data);
e3037485 YHC	32	void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
	33	void rtw_parse_tbl_phy_cond(struct rtw_dev rtwdev, const struct rtw_table tbl);
	34	void rtw_parse_tbl_bb_pg(struct rtw_dev rtwdev, const struct rtw_table tbl);
	35	void rtw_parse_tbl_txpwr_lmt(struct rtw_dev rtwdev, const struct rtw_table tbl);
	36	void rtw_phy_cfg_mac(struct rtw_dev rtwdev, const struct rtw_table tbl,
	37	u32 addr, u32 data);
	38	void rtw_phy_cfg_agc(struct rtw_dev rtwdev, const struct rtw_table tbl,
	39	u32 addr, u32 data);
	40	void rtw_phy_cfg_bb(struct rtw_dev rtwdev, const struct rtw_table tbl,
	41	u32 addr, u32 data);
	42	void rtw_phy_cfg_rf(struct rtw_dev rtwdev, const struct rtw_table tbl,
	43	u32 addr, u32 data);
0d350f0a	44	void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
e3037485	45	void rtw_phy_load_tables(struct rtw_dev *rtwdev);
c97ee3e0 TEH	46	u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
c97ee3e0 TEH	47	enum rtw_bandwidth bw, u8 channel, u8 regd);
e3037485 YHC	48	void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
	49	void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
	50	void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
c97ee3e0 TEH	51	void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path);
	52	bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
	53	u8 path);
	54	u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path);
	55	s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
	56	struct rtw_swing_table *swing_table,
	57	u8 tbl_path, u8 therm_path, u8 delta);
7ae7784e	58	bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev);
c97ee3e0 TEH	59	bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev);
	60	void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
	61	struct rtw_swing_table *swing_table);
fb8517f4 PHH	62	void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
fb8517f4 PHH	63	struct rtw_rx_pkt_stat *pkt_stat);
1188301f	64	void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev);
e3037485	65
3457f86d BN	66	struct rtw_txpwr_lmt_cfg_pair {
	67	u8 regd;
	68	u8 band;
	69	u8 bw;
	70	u8 rs;
	71	u8 ch;
	72	s8 txpwr_lmt;
	73	};
	74
0b8db87d YHC	75	struct rtw_phy_pg_cfg_pair {
	76	u32 band;
	77	u32 rf_path;
	78	u32 tx_num;
	79	u32 addr;
	80	u32 bitmask;
	81	u32 data;
	82	};
	83
e3037485 YHC	84	#define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \
	85	const struct rtw_table name ## _tbl = { \
	86	.data = name, \
	87	.size = ARRAY_SIZE(name), \
	88	.parse = rtw_parse_tbl_phy_cond, \
	89	.do_cfg = cfg, \
	90	.rf_path = path, \
	91	}
	92
	93	#define RTW_DECL_TABLE_PHY_COND(name, cfg) \
	94	RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
	95
	96	#define RTW_DECL_TABLE_RF_RADIO(name, path) \
	97	RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
	98
	99	#define RTW_DECL_TABLE_BB_PG(name) \
	100	const struct rtw_table name ## _tbl = { \
	101	.data = name, \
	102	.size = ARRAY_SIZE(name), \
	103	.parse = rtw_parse_tbl_bb_pg, \
	104	}
	105
	106	#define RTW_DECL_TABLE_TXPWR_LMT(name) \
	107	const struct rtw_table name ## _tbl = { \
	108	.data = name, \
	109	.size = ARRAY_SIZE(name), \
	110	.parse = rtw_parse_tbl_txpwr_lmt, \
	111	}
	112
	113	static inline const struct rtw_rfe_def rtw_get_rfe_def(struct rtw_dev rtwdev)
	114	{
	115	struct rtw_chip_info *chip = rtwdev->chip;
	116	struct rtw_efuse *efuse = &rtwdev->efuse;
	117	const struct rtw_rfe_def *rfe_def = NULL;
	118
	119	if (chip->rfe_defs_size == 0)
	120	return NULL;
	121
	122	if (efuse->rfe_option < chip->rfe_defs_size)
	123	rfe_def = &chip->rfe_defs[efuse->rfe_option];
	124
	125	rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
	126	return rfe_def;
	127	}
	128
	129	static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
	130	{
	131	const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
	132
	133	if (!rfe_def \|\| !rfe_def->phy_pg_tbl \|\| !rfe_def->txpwr_lmt_tbl) {
	134	rtw_err(rtwdev, "rfe %d isn't supported\n",
	135	rtwdev->efuse.rfe_option);
	136	return -ENODEV;
	137	}
	138
	139	return 0;
	140	}
	141
	142	void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
	143
b7414222 ZZY	144	struct rtw_power_params {
	145	u8 pwr_base;
	146	s8 pwr_offset;
	147	s8 pwr_limit;
608d2a08	148	s8 pwr_remnant;
b7414222 ZZY	149	};
	150
	151	void
	152	rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
	153	u8 rate, u8 bw, u8 ch, u8 regd,
	154	struct rtw_power_params *pwr_param);
	155
18a0696e TEH	156	enum rtw_phy_cck_pd_lv {
	157	CCK_PD_LV0,
	158	CCK_PD_LV1,
	159	CCK_PD_LV2,
	160	CCK_PD_LV3,
	161	CCK_PD_LV4,
	162	CCK_PD_LV_MAX,
	163	};
	164
e3037485 YHC	165	#define MASKBYTE0 0xff
	166	#define MASKBYTE1 0xff00
	167	#define MASKBYTE2 0xff0000
	168	#define MASKBYTE3 0xff000000
	169	#define MASKHWORD 0xffff0000
	170	#define MASKLWORD 0x0000ffff
	171	#define MASKDWORD 0xffffffff
	172	#define RFREG_MASK 0xfffff
	173
	174	#define MASK7BITS 0x7f
	175	#define MASK12BITS 0xfff
	176	#define MASKH4BITS 0xf0000000
	177	#define MASK20BITS 0xfffff
	178	#define MASK24BITS 0xffffff
	179
	180	#define MASKH3BYTES 0xffffff00
	181	#define MASKL3BYTES 0x00ffffff
	182	#define MASKBYTE2HIGHNIBBLE 0x00f00000
	183	#define MASKBYTE3LOWNIBBLE 0x0f000000
	184	#define MASKL3BYTES 0x00ffffff
	185
479c4ee9 TEH	186	#define CCK_FA_AVG_RESET 0xffffffff
479c4ee9 TEH	187
e0c27cdb PKS	188	#define LSSI_READ_ADDR_MASK 0x7f800000
	189	#define LSSI_READ_EDGE_MASK 0x80000000
	190	#define LSSI_READ_DATA_MASK 0xfffff
	191
48308726 PHH	192	#define RRSR_RATE_ORDER_MAX 0xfffff
	193	#define RRSR_RATE_ORDER_CCK_LEN 4
	194
e3037485	195	#endif