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e3037485 YHC |
1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
2 | /* Copyright(c) 2018-2019 Realtek Corporation | |
3 | */ | |
4 | ||
5 | #include "main.h" | |
4136214f | 6 | #include "coex.h" |
e3037485 YHC |
7 | #include "fw.h" |
8 | #include "tx.h" | |
9 | #include "rx.h" | |
10 | #include "phy.h" | |
11 | #include "rtw8822b.h" | |
12 | #include "rtw8822b_table.h" | |
13 | #include "mac.h" | |
14 | #include "reg.h" | |
15 | #include "debug.h" | |
0bd95573 | 16 | #include "bf.h" |
e3037485 YHC |
17 | |
18 | static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, | |
19 | u8 rx_path, bool is_tx2_path); | |
20 | ||
21 | static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse, | |
22 | struct rtw8822b_efuse *map) | |
23 | { | |
24 | ether_addr_copy(efuse->addr, map->e.mac_addr); | |
25 | } | |
26 | ||
27 | static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) | |
28 | { | |
29 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
30 | struct rtw8822b_efuse *map; | |
31 | int i; | |
32 | ||
33 | map = (struct rtw8822b_efuse *)log_map; | |
34 | ||
35 | efuse->rfe_option = map->rfe_option; | |
4136214f | 36 | efuse->rf_board_option = map->rf_board_option; |
e3037485 YHC |
37 | efuse->crystal_cap = map->xtal_k; |
38 | efuse->pa_type_2g = map->pa_type; | |
39 | efuse->pa_type_5g = map->pa_type; | |
40 | efuse->lna_type_2g = map->lna_type_2g[0]; | |
41 | efuse->lna_type_5g = map->lna_type_5g[0]; | |
42 | efuse->channel_plan = map->channel_plan; | |
43 | efuse->country_code[0] = map->country_code[0]; | |
44 | efuse->country_code[1] = map->country_code[1]; | |
45 | efuse->bt_setting = map->rf_bt_setting; | |
46 | efuse->regd = map->rf_board_option & 0x7; | |
c97ee3e0 TEH |
47 | efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; |
48 | efuse->thermal_meter_k = map->thermal_meter; | |
e3037485 YHC |
49 | |
50 | for (i = 0; i < 4; i++) | |
51 | efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; | |
52 | ||
53 | switch (rtw_hci_type(rtwdev)) { | |
54 | case RTW_HCI_TYPE_PCIE: | |
55 | rtw8822be_efuse_parsing(efuse, map); | |
56 | break; | |
57 | default: | |
58 | /* unsupported now */ | |
59 | return -ENOTSUPP; | |
60 | } | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
65 | static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev) | |
66 | { | |
67 | /* chip top mux */ | |
68 | rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); | |
69 | rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); | |
70 | rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); | |
71 | ||
72 | /* from s0 or s1 */ | |
73 | rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); | |
74 | rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); | |
75 | ||
76 | /* input or output */ | |
77 | rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); | |
78 | rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); | |
79 | } | |
80 | ||
c97ee3e0 TEH |
81 | #define RTW_TXSCALE_SIZE 37 |
82 | static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = { | |
83 | 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, | |
84 | 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, | |
85 | 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, | |
86 | 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe | |
87 | }; | |
88 | ||
89 | static const u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev) | |
90 | { | |
91 | u8 i = 0; | |
92 | u32 swing, table_value; | |
93 | ||
94 | swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); | |
95 | for (i = 0; i < RTW_TXSCALE_SIZE; i++) { | |
96 | table_value = rtw8822b_txscale_tbl[i]; | |
97 | if (swing == table_value) | |
98 | break; | |
99 | } | |
100 | ||
101 | return i; | |
102 | } | |
103 | ||
104 | static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev) | |
105 | { | |
106 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
107 | u8 swing_idx = rtw8822b_get_swing_index(rtwdev); | |
108 | u8 path; | |
109 | ||
110 | if (swing_idx >= RTW_TXSCALE_SIZE) | |
111 | dm_info->default_ofdm_index = 24; | |
112 | else | |
113 | dm_info->default_ofdm_index = swing_idx; | |
114 | ||
115 | for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { | |
116 | ewma_thermal_init(&dm_info->avg_thermal[path]); | |
117 | dm_info->delta_power_index[path] = 0; | |
118 | } | |
119 | dm_info->pwr_trk_triggered = false; | |
120 | dm_info->pwr_trk_init_trigger = true; | |
121 | dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; | |
122 | } | |
123 | ||
0bd95573 TEH |
124 | static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev) |
125 | { | |
126 | rtw_bf_phy_init(rtwdev); | |
127 | /* Grouping bitmap parameters */ | |
128 | rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); | |
129 | } | |
130 | ||
e3037485 YHC |
131 | static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev) |
132 | { | |
133 | struct rtw_hal *hal = &rtwdev->hal; | |
134 | u8 crystal_cap; | |
135 | bool is_tx2_path; | |
136 | ||
137 | /* power on BB/RF domain */ | |
138 | rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, | |
139 | BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); | |
140 | rtw_write8_set(rtwdev, REG_RF_CTRL, | |
141 | BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); | |
142 | rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); | |
143 | ||
144 | /* pre init before header files config */ | |
145 | rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); | |
146 | ||
147 | rtw_phy_load_tables(rtwdev); | |
148 | ||
149 | crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; | |
150 | rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); | |
151 | rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); | |
152 | ||
153 | /* post init after header files config */ | |
154 | rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); | |
155 | ||
156 | is_tx2_path = false; | |
157 | rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, | |
158 | is_tx2_path); | |
159 | rtw_phy_init(rtwdev); | |
160 | ||
161 | rtw8822b_phy_rfe_init(rtwdev); | |
c97ee3e0 | 162 | rtw8822b_pwrtrack_init(rtwdev); |
0bd95573 TEH |
163 | |
164 | rtw8822b_phy_bf_init(rtwdev); | |
e3037485 YHC |
165 | } |
166 | ||
167 | #define WLAN_SLOT_TIME 0x09 | |
168 | #define WLAN_PIFS_TIME 0x19 | |
169 | #define WLAN_SIFS_CCK_CONT_TX 0xA | |
170 | #define WLAN_SIFS_OFDM_CONT_TX 0xE | |
171 | #define WLAN_SIFS_CCK_TRX 0x10 | |
172 | #define WLAN_SIFS_OFDM_TRX 0x10 | |
173 | #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ | |
174 | #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ | |
175 | #define WLAN_RDG_NAV 0x05 | |
176 | #define WLAN_TXOP_NAV 0x1B | |
177 | #define WLAN_CCK_RX_TSF 0x30 | |
178 | #define WLAN_OFDM_RX_TSF 0x30 | |
179 | #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ | |
180 | #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ | |
181 | #define WLAN_DRV_EARLY_INT 0x04 | |
182 | #define WLAN_BCN_DMA_TIME 0x02 | |
183 | ||
184 | #define WLAN_RX_FILTER0 0x0FFFFFFF | |
185 | #define WLAN_RX_FILTER2 0xFFFF | |
186 | #define WLAN_RCR_CFG 0xE400220E | |
187 | #define WLAN_RXPKT_MAX_SZ 12288 | |
188 | #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) | |
189 | ||
190 | #define WLAN_AMPDU_MAX_TIME 0x70 | |
191 | #define WLAN_RTS_LEN_TH 0xFF | |
192 | #define WLAN_RTS_TX_TIME_TH 0x08 | |
193 | #define WLAN_MAX_AGG_PKT_LIMIT 0x20 | |
194 | #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 | |
195 | #define FAST_EDCA_VO_TH 0x06 | |
196 | #define FAST_EDCA_VI_TH 0x06 | |
197 | #define FAST_EDCA_BE_TH 0x06 | |
198 | #define FAST_EDCA_BK_TH 0x06 | |
199 | #define WLAN_BAR_RETRY_LIMIT 0x01 | |
200 | #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 | |
201 | ||
202 | #define WLAN_TX_FUNC_CFG1 0x30 | |
203 | #define WLAN_TX_FUNC_CFG2 0x30 | |
204 | #define WLAN_MAC_OPT_NORM_FUNC1 0x98 | |
205 | #define WLAN_MAC_OPT_LB_FUNC1 0x80 | |
206 | #define WLAN_MAC_OPT_FUNC2 0x30810041 | |
207 | ||
208 | #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ | |
209 | (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ | |
210 | (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ | |
211 | (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) | |
212 | ||
213 | #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ | |
214 | (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) | |
215 | ||
216 | #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) | |
217 | #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) | |
218 | ||
219 | static int rtw8822b_mac_init(struct rtw_dev *rtwdev) | |
220 | { | |
221 | u32 value32; | |
222 | ||
223 | /* protocol configuration */ | |
224 | rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD); | |
225 | rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); | |
226 | rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); | |
227 | value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | | |
228 | (WLAN_MAX_AGG_PKT_LIMIT << 16) | | |
229 | (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); | |
230 | rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); | |
231 | rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, | |
232 | WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); | |
233 | rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); | |
234 | rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); | |
235 | rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); | |
236 | rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); | |
237 | /* EDCA configuration */ | |
238 | rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); | |
239 | rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); | |
240 | rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); | |
241 | rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); | |
242 | rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); | |
243 | rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); | |
244 | rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); | |
245 | rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); | |
246 | rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); | |
247 | /* Set beacon cotnrol - enable TSF and other related functions */ | |
248 | rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); | |
249 | /* Set send beacon related registers */ | |
250 | rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); | |
251 | rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); | |
252 | rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); | |
253 | rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); | |
254 | /* WMAC configuration */ | |
255 | rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); | |
256 | rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); | |
257 | rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); | |
258 | rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); | |
259 | rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); | |
260 | rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); | |
261 | rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); | |
262 | rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel) | |
268 | { | |
269 | struct rtw_hal *hal = &rtwdev->hal; | |
e3037485 | 270 | |
8575b534 | 271 | if (IS_CH_2G_BAND(channel)) { |
e3037485 YHC |
272 | rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); |
273 | rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); | |
274 | rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); | |
275 | } else { | |
276 | rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); | |
277 | rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); | |
278 | rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); | |
279 | } | |
280 | ||
281 | rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); | |
282 | ||
283 | if (hal->antenna_rx == BB_PATH_AB || | |
284 | hal->antenna_tx == BB_PATH_AB) { | |
285 | /* 2TX or 2RX */ | |
286 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); | |
287 | } else if (hal->antenna_rx == hal->antenna_tx) { | |
288 | /* TXA+RXA or TXB+RXB */ | |
289 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); | |
290 | } else { | |
291 | /* TXB+RXA or TXA+RXB */ | |
292 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); | |
293 | } | |
294 | } | |
295 | ||
296 | static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel) | |
297 | { | |
298 | struct rtw_hal *hal = &rtwdev->hal; | |
e3037485 | 299 | |
8575b534 | 300 | if (IS_CH_2G_BAND(channel)) { |
e3037485 YHC |
301 | /* signal source */ |
302 | rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); | |
303 | rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); | |
304 | } else { | |
305 | /* signal source */ | |
306 | rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); | |
307 | rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); | |
308 | } | |
309 | ||
310 | rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); | |
311 | ||
8575b534 | 312 | if (IS_CH_2G_BAND(channel)) { |
e3037485 YHC |
313 | if (hal->antenna_rx == BB_PATH_AB || |
314 | hal->antenna_tx == BB_PATH_AB) { | |
315 | /* 2TX or 2RX */ | |
316 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); | |
317 | } else if (hal->antenna_rx == hal->antenna_tx) { | |
318 | /* TXA+RXA or TXB+RXB */ | |
319 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); | |
320 | } else { | |
321 | /* TXB+RXA or TXA+RXB */ | |
322 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); | |
323 | } | |
324 | } else { | |
325 | rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); | |
326 | } | |
327 | } | |
328 | ||
329 | enum { | |
330 | CCUT_IDX_1R_2G, | |
331 | CCUT_IDX_2R_2G, | |
332 | CCUT_IDX_1R_5G, | |
333 | CCUT_IDX_2R_5G, | |
334 | CCUT_IDX_NR, | |
335 | }; | |
336 | ||
337 | struct cca_ccut { | |
338 | u32 reg82c[CCUT_IDX_NR]; | |
339 | u32 reg830[CCUT_IDX_NR]; | |
340 | u32 reg838[CCUT_IDX_NR]; | |
341 | }; | |
342 | ||
343 | static const struct cca_ccut cca_ifem_ccut = { | |
344 | {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ | |
345 | {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ | |
346 | {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/ | |
347 | }; | |
348 | ||
349 | static const struct cca_ccut cca_efem_ccut = { | |
350 | {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ | |
351 | {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ | |
352 | {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ | |
353 | }; | |
354 | ||
355 | static const struct cca_ccut cca_ifem_ccut_ext = { | |
356 | {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ | |
357 | {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ | |
358 | {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/ | |
359 | }; | |
360 | ||
361 | static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col, | |
362 | u32 *reg82c, u32 *reg830, u32 *reg838) | |
363 | { | |
364 | *reg82c = cca_ccut->reg82c[col]; | |
365 | *reg830 = cca_ccut->reg830[col]; | |
366 | *reg838 = cca_ccut->reg838[col]; | |
367 | } | |
368 | ||
369 | struct rtw8822b_rfe_info { | |
370 | const struct cca_ccut *cca_ccut_2g; | |
371 | const struct cca_ccut *cca_ccut_5g; | |
372 | enum rtw_rfe_fem fem; | |
373 | bool ifem_ext; | |
374 | void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel); | |
375 | }; | |
376 | ||
377 | #define I2GE5G_CCUT(set_ch) { \ | |
378 | .cca_ccut_2g = &cca_ifem_ccut, \ | |
379 | .cca_ccut_5g = &cca_efem_ccut, \ | |
380 | .fem = RTW_RFE_IFEM2G_EFEM5G, \ | |
381 | .ifem_ext = false, \ | |
382 | .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ | |
383 | } | |
384 | #define IFEM_EXT_CCUT(set_ch) { \ | |
385 | .cca_ccut_2g = &cca_ifem_ccut_ext, \ | |
386 | .cca_ccut_5g = &cca_ifem_ccut_ext, \ | |
387 | .fem = RTW_RFE_IFEM, \ | |
388 | .ifem_ext = true, \ | |
389 | .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ | |
390 | } | |
391 | ||
392 | static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = { | |
393 | [2] = I2GE5G_CCUT(efem), | |
7436a470 | 394 | [3] = IFEM_EXT_CCUT(ifem), |
e3037485 YHC |
395 | [5] = IFEM_EXT_CCUT(ifem), |
396 | }; | |
397 | ||
398 | static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw, | |
399 | const struct rtw8822b_rfe_info *rfe_info) | |
400 | { | |
401 | struct rtw_hal *hal = &rtwdev->hal; | |
402 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
403 | const struct cca_ccut *cca_ccut; | |
404 | u8 col; | |
405 | u32 reg82c, reg830, reg838; | |
406 | bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; | |
407 | ||
8575b534 | 408 | if (IS_CH_2G_BAND(channel)) { |
e3037485 YHC |
409 | cca_ccut = rfe_info->cca_ccut_2g; |
410 | ||
411 | if (hal->antenna_rx == BB_PATH_A || | |
412 | hal->antenna_rx == BB_PATH_B) | |
413 | col = CCUT_IDX_1R_2G; | |
414 | else | |
415 | col = CCUT_IDX_2R_2G; | |
416 | } else { | |
417 | cca_ccut = rfe_info->cca_ccut_5g; | |
418 | ||
419 | if (hal->antenna_rx == BB_PATH_A || | |
420 | hal->antenna_rx == BB_PATH_B) | |
421 | col = CCUT_IDX_1R_5G; | |
422 | else | |
423 | col = CCUT_IDX_2R_5G; | |
424 | } | |
425 | ||
426 | rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838); | |
427 | ||
428 | switch (rfe_info->fem) { | |
429 | case RTW_RFE_IFEM: | |
430 | default: | |
431 | is_ifem_cca = true; | |
432 | if (rfe_info->ifem_ext) | |
433 | is_rfe_type = true; | |
434 | break; | |
435 | case RTW_RFE_EFEM: | |
436 | is_efem_cca = true; | |
437 | break; | |
438 | case RTW_RFE_IFEM2G_EFEM5G: | |
8575b534 | 439 | if (IS_CH_2G_BAND(channel)) |
e3037485 YHC |
440 | is_ifem_cca = true; |
441 | else | |
442 | is_efem_cca = true; | |
443 | break; | |
444 | } | |
445 | ||
446 | if (is_ifem_cca) { | |
447 | if ((hal->cut_version == RTW_CHIP_VER_CUT_B && | |
448 | (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) && | |
449 | bw == RTW_CHANNEL_WIDTH_40) || | |
450 | (!is_rfe_type && col == CCUT_IDX_2R_5G && | |
451 | bw == RTW_CHANNEL_WIDTH_40) || | |
452 | (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) | |
453 | reg830 = 0x79a0ea28; | |
454 | } | |
455 | ||
456 | rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); | |
457 | rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830); | |
458 | rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838); | |
459 | ||
460 | if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) | |
461 | rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); | |
462 | ||
8575b534 | 463 | if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel)) |
e3037485 YHC |
464 | rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); |
465 | } | |
466 | ||
467 | static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, | |
468 | 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; | |
469 | static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, | |
470 | 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, | |
471 | 0x6, 0x5, 0x0, 0x0, 0x7}; | |
472 | static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, | |
473 | 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; | |
474 | ||
475 | static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) | |
476 | { | |
477 | #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) | |
478 | #define RF18_BAND_2G (0) | |
479 | #define RF18_BAND_5G (BIT(16) | BIT(8)) | |
480 | #define RF18_CHANNEL_MASK (MASKBYTE0) | |
481 | #define RF18_RFSI_MASK (BIT(18) | BIT(17)) | |
482 | #define RF18_RFSI_GE_CH80 (BIT(17)) | |
483 | #define RF18_RFSI_GT_CH144 (BIT(18)) | |
484 | #define RF18_BW_MASK (BIT(11) | BIT(10)) | |
485 | #define RF18_BW_20M (BIT(11) | BIT(10)) | |
486 | #define RF18_BW_40M (BIT(11)) | |
487 | #define RF18_BW_80M (BIT(10)) | |
488 | #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) | |
489 | ||
490 | struct rtw_hal *hal = &rtwdev->hal; | |
491 | u32 rf_reg18, rf_reg_be; | |
492 | ||
493 | rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); | |
494 | ||
495 | rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | | |
496 | RF18_BW_MASK); | |
497 | ||
8575b534 | 498 | rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); |
e3037485 YHC |
499 | rf_reg18 |= (channel & RF18_CHANNEL_MASK); |
500 | if (channel > 144) | |
501 | rf_reg18 |= RF18_RFSI_GT_CH144; | |
502 | else if (channel >= 80) | |
503 | rf_reg18 |= RF18_RFSI_GE_CH80; | |
504 | ||
505 | switch (bw) { | |
506 | case RTW_CHANNEL_WIDTH_5: | |
507 | case RTW_CHANNEL_WIDTH_10: | |
508 | case RTW_CHANNEL_WIDTH_20: | |
509 | default: | |
510 | rf_reg18 |= RF18_BW_20M; | |
511 | break; | |
512 | case RTW_CHANNEL_WIDTH_40: | |
513 | rf_reg18 |= RF18_BW_40M; | |
514 | break; | |
515 | case RTW_CHANNEL_WIDTH_80: | |
516 | rf_reg18 |= RF18_BW_80M; | |
517 | break; | |
518 | } | |
519 | ||
8575b534 | 520 | if (IS_CH_2G_BAND(channel)) |
e3037485 | 521 | rf_reg_be = 0x0; |
8575b534 | 522 | else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) |
e3037485 | 523 | rf_reg_be = low_band[(channel - 36) >> 1]; |
8575b534 | 524 | else if (IS_CH_5G_BAND_3(channel)) |
e3037485 | 525 | rf_reg_be = middle_band[(channel - 100) >> 1]; |
8575b534 | 526 | else if (IS_CH_5G_BAND_4(channel)) |
e3037485 YHC |
527 | rf_reg_be = high_band[(channel - 149) >> 1]; |
528 | else | |
529 | goto err; | |
530 | ||
531 | rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be); | |
532 | ||
533 | /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ | |
534 | if (channel == 144) | |
535 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); | |
536 | else | |
537 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); | |
538 | ||
539 | rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); | |
540 | if (hal->rf_type > RF_1T1R) | |
541 | rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); | |
542 | ||
543 | rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); | |
544 | rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); | |
545 | ||
546 | return; | |
547 | ||
548 | err: | |
549 | WARN_ON(1); | |
550 | } | |
551 | ||
552 | static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev) | |
553 | { | |
554 | struct rtw_hal *hal = &rtwdev->hal; | |
555 | u32 igi; | |
556 | ||
557 | igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); | |
558 | rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); | |
559 | rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); | |
560 | rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); | |
561 | rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); | |
562 | ||
563 | rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); | |
564 | rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, | |
565 | hal->antenna_rx | (hal->antenna_rx << 4)); | |
566 | } | |
567 | ||
568 | static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) | |
569 | { | |
570 | if (bw == RTW_CHANNEL_WIDTH_40) { | |
571 | /* RX DFIR for BW40 */ | |
572 | rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); | |
573 | rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); | |
574 | rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); | |
575 | } else if (bw == RTW_CHANNEL_WIDTH_80) { | |
576 | /* RX DFIR for BW80 */ | |
577 | rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); | |
578 | rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); | |
579 | rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); | |
580 | } else { | |
581 | /* RX DFIR for BW20, BW10 and BW5*/ | |
582 | rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); | |
583 | rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); | |
584 | rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); | |
585 | } | |
586 | } | |
587 | ||
588 | static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, | |
589 | u8 primary_ch_idx) | |
590 | { | |
591 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
592 | u8 rfe_option = efuse->rfe_option; | |
593 | u32 val32; | |
594 | ||
8575b534 | 595 | if (IS_CH_2G_BAND(channel)) { |
e3037485 YHC |
596 | rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); |
597 | rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); | |
598 | rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); | |
599 | rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); | |
600 | ||
601 | rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); | |
602 | rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); | |
603 | if (channel == 14) { | |
604 | rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); | |
605 | rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); | |
606 | } else { | |
607 | rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); | |
608 | rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); | |
609 | } | |
610 | ||
611 | rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); | |
8575b534 | 612 | } else if (IS_CH_5G_BAND(channel)) { |
e3037485 YHC |
613 | rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); |
614 | rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); | |
615 | rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); | |
616 | rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); | |
617 | ||
8575b534 | 618 | if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) |
e3037485 | 619 | rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); |
8575b534 | 620 | else if (IS_CH_5G_BAND_3(channel)) |
e3037485 | 621 | rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); |
8575b534 | 622 | else if (IS_CH_5G_BAND_4(channel)) |
e3037485 YHC |
623 | rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); |
624 | ||
8575b534 | 625 | if (IS_CH_5G_BAND_1(channel)) |
e3037485 | 626 | rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); |
8575b534 | 627 | else if (IS_CH_5G_BAND_2(channel)) |
e3037485 YHC |
628 | rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); |
629 | else if (channel >= 100 && channel <= 116) | |
630 | rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); | |
631 | else if (channel >= 118 && channel <= 177) | |
632 | rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); | |
633 | ||
634 | rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); | |
635 | } | |
636 | ||
637 | switch (bw) { | |
638 | case RTW_CHANNEL_WIDTH_20: | |
639 | default: | |
640 | val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); | |
641 | val32 &= 0xFFCFFC00; | |
642 | val32 |= (RTW_CHANNEL_WIDTH_20); | |
643 | rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); | |
644 | ||
645 | rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); | |
646 | break; | |
647 | case RTW_CHANNEL_WIDTH_40: | |
648 | if (primary_ch_idx == 1) | |
649 | rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); | |
650 | else | |
651 | rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); | |
652 | ||
653 | val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); | |
654 | val32 &= 0xFF3FF300; | |
655 | val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); | |
656 | rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); | |
657 | ||
658 | rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); | |
659 | break; | |
660 | case RTW_CHANNEL_WIDTH_80: | |
661 | val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); | |
662 | val32 &= 0xFCEFCF00; | |
663 | val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); | |
664 | rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); | |
665 | ||
666 | rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); | |
667 | ||
7436a470 | 668 | if (rfe_option == 2 || rfe_option == 3) { |
e3037485 YHC |
669 | rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); |
670 | rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); | |
671 | } | |
672 | break; | |
673 | case RTW_CHANNEL_WIDTH_5: | |
674 | val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); | |
675 | val32 &= 0xEFEEFE00; | |
676 | val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); | |
677 | rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); | |
678 | ||
679 | rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); | |
680 | rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); | |
681 | break; | |
682 | case RTW_CHANNEL_WIDTH_10: | |
683 | val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); | |
684 | val32 &= 0xEFFEFF00; | |
685 | val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); | |
686 | rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); | |
687 | ||
688 | rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); | |
689 | rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); | |
690 | break; | |
691 | } | |
692 | } | |
693 | ||
694 | static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, | |
695 | u8 primary_chan_idx) | |
696 | { | |
697 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
698 | const struct rtw8822b_rfe_info *rfe_info; | |
699 | ||
700 | if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), | |
701 | "rfe_option %d is out of boundary\n", efuse->rfe_option)) | |
702 | return; | |
703 | ||
704 | rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; | |
705 | ||
706 | rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); | |
707 | rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); | |
708 | rtw8822b_set_channel_rf(rtwdev, channel, bw); | |
709 | rtw8822b_set_channel_rxdfir(rtwdev, bw); | |
710 | rtw8822b_toggle_igi(rtwdev); | |
711 | rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info); | |
712 | (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); | |
713 | } | |
714 | ||
715 | static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, | |
716 | u8 rx_path, bool is_tx2_path) | |
717 | { | |
718 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
719 | const struct rtw8822b_rfe_info *rfe_info; | |
720 | u8 ch = rtwdev->hal.current_channel; | |
721 | u8 tx_path_sel, rx_path_sel; | |
722 | int counter; | |
723 | ||
724 | if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), | |
725 | "rfe_option %d is out of boundary\n", efuse->rfe_option)) | |
726 | return; | |
727 | ||
728 | rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; | |
729 | ||
730 | if ((tx_path | rx_path) & BB_PATH_A) | |
731 | rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); | |
732 | else | |
733 | rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); | |
734 | ||
735 | if ((tx_path | rx_path) & BB_PATH_B) | |
736 | rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); | |
737 | else | |
738 | rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); | |
739 | ||
740 | rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); | |
741 | rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); | |
742 | rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); | |
743 | ||
744 | if (tx_path & BB_PATH_A) { | |
745 | rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); | |
746 | rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); | |
747 | } else if (tx_path & BB_PATH_B) { | |
748 | rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); | |
749 | rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); | |
750 | } | |
751 | ||
752 | if (tx_path == BB_PATH_A || tx_path == BB_PATH_B) | |
753 | rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); | |
754 | else | |
755 | rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); | |
756 | ||
757 | tx_path_sel = (tx_path << 4) | tx_path; | |
758 | rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel); | |
759 | ||
760 | if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) { | |
761 | if (is_tx2_path || rtwdev->mp_mode) { | |
762 | rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); | |
763 | rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); | |
764 | } | |
765 | } | |
766 | ||
767 | rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); | |
768 | rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); | |
769 | ||
770 | if (rx_path & BB_PATH_A) | |
771 | rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); | |
772 | else if (rx_path & BB_PATH_B) | |
773 | rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); | |
774 | ||
775 | rx_path_sel = (rx_path << 4) | rx_path; | |
776 | rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); | |
777 | ||
778 | if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { | |
779 | rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); | |
780 | rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); | |
781 | rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); | |
782 | } else { | |
783 | rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); | |
784 | rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); | |
785 | rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); | |
786 | } | |
787 | ||
788 | for (counter = 100; counter > 0; counter--) { | |
789 | u32 rf_reg33; | |
790 | ||
791 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); | |
792 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); | |
793 | ||
794 | udelay(2); | |
795 | rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); | |
796 | ||
797 | if (rf_reg33 == 0x00001) | |
798 | break; | |
799 | } | |
800 | ||
801 | if (WARN(counter <= 0, "write RF mode table fail\n")) | |
802 | return; | |
803 | ||
804 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); | |
805 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); | |
806 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); | |
807 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); | |
808 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); | |
809 | rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); | |
810 | ||
811 | rtw8822b_toggle_igi(rtwdev); | |
812 | rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info); | |
813 | (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); | |
814 | } | |
815 | ||
816 | static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, | |
817 | struct rtw_rx_pkt_stat *pkt_stat) | |
818 | { | |
082a36dc | 819 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; |
e3037485 YHC |
820 | s8 min_rx_power = -120; |
821 | u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); | |
822 | ||
98ab76ef | 823 | /* 8822B uses only 1 antenna to RX CCK rates */ |
e3037485 YHC |
824 | pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; |
825 | pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); | |
826 | pkt_stat->bw = RTW_CHANNEL_WIDTH_20; | |
827 | pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], | |
828 | min_rx_power); | |
082a36dc | 829 | dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; |
e3037485 YHC |
830 | } |
831 | ||
832 | static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, | |
833 | struct rtw_rx_pkt_stat *pkt_stat) | |
834 | { | |
082a36dc | 835 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; |
e3037485 YHC |
836 | u8 rxsc, bw; |
837 | s8 min_rx_power = -120; | |
082a36dc TSL |
838 | s8 rx_evm; |
839 | u8 evm_dbm = 0; | |
840 | u8 rssi; | |
841 | int path; | |
e3037485 YHC |
842 | |
843 | if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) | |
844 | rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); | |
845 | else | |
846 | rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); | |
847 | ||
848 | if (rxsc >= 1 && rxsc <= 8) | |
849 | bw = RTW_CHANNEL_WIDTH_20; | |
850 | else if (rxsc >= 9 && rxsc <= 12) | |
851 | bw = RTW_CHANNEL_WIDTH_40; | |
852 | else if (rxsc >= 13) | |
853 | bw = RTW_CHANNEL_WIDTH_80; | |
854 | else | |
855 | bw = GET_PHY_STAT_P1_RF_MODE(phy_status); | |
856 | ||
857 | pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; | |
858 | pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; | |
859 | pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); | |
860 | pkt_stat->bw = bw; | |
861 | pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], | |
862 | pkt_stat->rx_power[RF_PATH_B], | |
863 | min_rx_power); | |
082a36dc TSL |
864 | |
865 | dm_info->curr_rx_rate = pkt_stat->rate; | |
866 | ||
867 | pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); | |
868 | pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); | |
869 | ||
870 | pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); | |
871 | pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); | |
872 | ||
873 | pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); | |
874 | pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); | |
875 | ||
876 | for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { | |
877 | rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); | |
878 | dm_info->rssi[path] = rssi; | |
879 | dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; | |
880 | dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; | |
881 | ||
882 | rx_evm = pkt_stat->rx_evm[path]; | |
883 | ||
884 | if (rx_evm < 0) { | |
885 | if (rx_evm == S8_MIN) | |
886 | evm_dbm = 0; | |
887 | else | |
888 | evm_dbm = ((u8)-rx_evm >> 1); | |
889 | } | |
890 | dm_info->rx_evm_dbm[path] = evm_dbm; | |
891 | } | |
e3037485 YHC |
892 | } |
893 | ||
894 | static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, | |
895 | struct rtw_rx_pkt_stat *pkt_stat) | |
896 | { | |
897 | u8 page; | |
898 | ||
899 | page = *phy_status & 0xf; | |
900 | ||
901 | switch (page) { | |
902 | case 0: | |
903 | query_phy_status_page0(rtwdev, phy_status, pkt_stat); | |
904 | break; | |
905 | case 1: | |
906 | query_phy_status_page1(rtwdev, phy_status, pkt_stat); | |
907 | break; | |
908 | default: | |
909 | rtw_warn(rtwdev, "unused phy status page (%d)\n", page); | |
910 | return; | |
911 | } | |
912 | } | |
913 | ||
914 | static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, | |
915 | struct rtw_rx_pkt_stat *pkt_stat, | |
916 | struct ieee80211_rx_status *rx_status) | |
917 | { | |
918 | struct ieee80211_hdr *hdr; | |
919 | u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; | |
920 | u8 *phy_status = NULL; | |
921 | ||
922 | memset(pkt_stat, 0, sizeof(*pkt_stat)); | |
923 | ||
924 | pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); | |
925 | pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); | |
926 | pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); | |
0649ff58 PKS |
927 | pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && |
928 | GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; | |
e3037485 YHC |
929 | pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); |
930 | pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); | |
931 | pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); | |
932 | pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); | |
933 | pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); | |
934 | pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); | |
935 | pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); | |
936 | pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); | |
937 | ||
938 | /* drv_info_sz is in unit of 8-bytes */ | |
939 | pkt_stat->drv_info_sz *= 8; | |
940 | ||
941 | /* c2h cmd pkt's rx/phy status is not interested */ | |
942 | if (pkt_stat->is_c2h) | |
943 | return; | |
944 | ||
945 | hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + | |
946 | pkt_stat->drv_info_sz); | |
947 | if (pkt_stat->phy_status) { | |
948 | phy_status = rx_desc + desc_sz + pkt_stat->shift; | |
949 | query_phy_status(rtwdev, phy_status, pkt_stat); | |
950 | } | |
951 | ||
952 | rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); | |
953 | } | |
954 | ||
955 | static void | |
956 | rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) | |
957 | { | |
958 | struct rtw_hal *hal = &rtwdev->hal; | |
959 | static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; | |
960 | static u32 phy_pwr_idx; | |
961 | u8 rate, rate_idx, pwr_index, shift; | |
962 | int j; | |
963 | ||
964 | for (j = 0; j < rtw_rate_size[rs]; j++) { | |
965 | rate = rtw_rate_section[rs][j]; | |
966 | pwr_index = hal->tx_pwr_tbl[path][rate]; | |
967 | shift = rate & 0x3; | |
968 | phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); | |
969 | if (shift == 0x3) { | |
970 | rate_idx = rate & 0xfc; | |
971 | rtw_write32(rtwdev, offset_txagc[path] + rate_idx, | |
972 | phy_pwr_idx); | |
973 | phy_pwr_idx = 0; | |
974 | } | |
975 | } | |
976 | } | |
977 | ||
978 | static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev) | |
979 | { | |
980 | struct rtw_hal *hal = &rtwdev->hal; | |
981 | int rs, path; | |
982 | ||
983 | for (path = 0; path < hal->rf_path_num; path++) { | |
984 | for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) | |
985 | rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs); | |
986 | } | |
987 | } | |
988 | ||
989 | static bool rtw8822b_check_rf_path(u8 antenna) | |
990 | { | |
991 | switch (antenna) { | |
992 | case BB_PATH_A: | |
993 | case BB_PATH_B: | |
994 | case BB_PATH_AB: | |
995 | return true; | |
996 | default: | |
997 | return false; | |
998 | } | |
999 | } | |
1000 | ||
1001 | static void rtw8822b_set_antenna(struct rtw_dev *rtwdev, u8 antenna_tx, | |
1002 | u8 antenna_rx) | |
1003 | { | |
1004 | struct rtw_hal *hal = &rtwdev->hal; | |
1005 | ||
1006 | rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", | |
1007 | antenna_tx, antenna_rx); | |
1008 | ||
1009 | if (!rtw8822b_check_rf_path(antenna_tx)) { | |
1010 | rtw_info(rtwdev, "unsupport tx path, set to default path ab\n"); | |
1011 | antenna_tx = BB_PATH_AB; | |
1012 | } | |
1013 | if (!rtw8822b_check_rf_path(antenna_rx)) { | |
1014 | rtw_info(rtwdev, "unsupport rx path, set to default path ab\n"); | |
1015 | antenna_rx = BB_PATH_AB; | |
1016 | } | |
1017 | hal->antenna_tx = antenna_tx; | |
1018 | hal->antenna_rx = antenna_rx; | |
1019 | rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); | |
1020 | } | |
1021 | ||
1022 | static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) | |
1023 | { | |
1024 | u8 ldo_pwr; | |
1025 | ||
1026 | ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); | |
1027 | ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); | |
1028 | rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); | |
1029 | } | |
1030 | ||
1031 | static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev) | |
1032 | { | |
1033 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
1034 | u32 cck_enable; | |
1035 | u32 cck_fa_cnt; | |
1036 | u32 ofdm_fa_cnt; | |
4136214f | 1037 | u32 crc32_cnt; |
082a36dc | 1038 | u32 cca32_cnt; |
e3037485 YHC |
1039 | |
1040 | cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); | |
1041 | cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); | |
1042 | ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); | |
1043 | ||
1044 | dm_info->cck_fa_cnt = cck_fa_cnt; | |
1045 | dm_info->ofdm_fa_cnt = ofdm_fa_cnt; | |
1046 | dm_info->total_fa_cnt = ofdm_fa_cnt; | |
1047 | dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; | |
1048 | ||
4136214f YHC |
1049 | crc32_cnt = rtw_read32(rtwdev, 0xf04); |
1050 | dm_info->cck_ok_cnt = crc32_cnt & 0xffff; | |
1051 | dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; | |
1052 | crc32_cnt = rtw_read32(rtwdev, 0xf14); | |
1053 | dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; | |
1054 | dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; | |
1055 | crc32_cnt = rtw_read32(rtwdev, 0xf10); | |
1056 | dm_info->ht_ok_cnt = crc32_cnt & 0xffff; | |
1057 | dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; | |
1058 | crc32_cnt = rtw_read32(rtwdev, 0xf0c); | |
1059 | dm_info->vht_ok_cnt = crc32_cnt & 0xffff; | |
1060 | dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; | |
1061 | ||
082a36dc TSL |
1062 | cca32_cnt = rtw_read32(rtwdev, 0xf08); |
1063 | dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); | |
1064 | dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; | |
1065 | if (cck_enable) { | |
1066 | cca32_cnt = rtw_read32(rtwdev, 0xfcc); | |
1067 | dm_info->cck_cca_cnt = cca32_cnt & 0xffff; | |
1068 | dm_info->total_cca_cnt += dm_info->cck_cca_cnt; | |
1069 | } | |
1070 | ||
e3037485 YHC |
1071 | rtw_write32_set(rtwdev, 0x9a4, BIT(17)); |
1072 | rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); | |
1073 | rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); | |
1074 | rtw_write32_set(rtwdev, 0xa2c, BIT(15)); | |
1075 | rtw_write32_set(rtwdev, 0xb58, BIT(0)); | |
1076 | rtw_write32_clr(rtwdev, 0xb58, BIT(0)); | |
1077 | } | |
1078 | ||
1079 | static void rtw8822b_do_iqk(struct rtw_dev *rtwdev) | |
1080 | { | |
1081 | static int do_iqk_cnt; | |
1082 | struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; | |
1083 | u32 rf_reg, iqk_fail_mask; | |
1084 | int counter; | |
1085 | bool reload; | |
1086 | ||
1087 | rtw_fw_do_iqk(rtwdev, ¶); | |
1088 | ||
1089 | for (counter = 0; counter < 300; counter++) { | |
1090 | rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); | |
1091 | if (rf_reg == 0xabcde) | |
1092 | break; | |
1093 | msleep(20); | |
1094 | } | |
1095 | rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); | |
1096 | ||
1097 | reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); | |
5ff29d83 | 1098 | iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); |
e3037485 YHC |
1099 | rtw_dbg(rtwdev, RTW_DBG_PHY, |
1100 | "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", | |
1101 | counter, reload, ++do_iqk_cnt, iqk_fail_mask); | |
1102 | } | |
1103 | ||
f27b886d | 1104 | static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev) |
5227c2ee | 1105 | { |
f27b886d | 1106 | rtw8822b_do_iqk(rtwdev); |
5227c2ee TEH |
1107 | } |
1108 | ||
4136214f YHC |
1109 | static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) |
1110 | { | |
1111 | /* enable TBTT nterrupt */ | |
1112 | rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); | |
1113 | ||
1114 | /* BT report packet sample rate */ | |
1115 | /* 0x790[5:0]=0x5 */ | |
1116 | rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); | |
1117 | ||
1118 | /* enable BT counter statistics */ | |
1119 | rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); | |
1120 | ||
1121 | /* enable PTA (3-wire function form BT side) */ | |
1122 | rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); | |
1123 | rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); | |
1124 | ||
1125 | /* enable PTA (tx/rx signal form WiFi side) */ | |
1126 | rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); | |
1127 | /* wl tx signal to PTA not case EDCCA */ | |
1128 | rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); | |
1129 | /* GNT_BT=1 while select both */ | |
1130 | rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); | |
1131 | } | |
1132 | ||
1133 | static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev, | |
1134 | u8 ctrl_type, u8 pos_type) | |
1135 | { | |
1136 | struct rtw_coex *coex = &rtwdev->coex; | |
1137 | struct rtw_coex_dm *coex_dm = &coex->dm; | |
1138 | struct rtw_coex_rfe *coex_rfe = &coex->rfe; | |
1139 | bool polarity_inverse; | |
1140 | u8 regval = 0; | |
1141 | ||
1142 | if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) | |
1143 | return; | |
1144 | ||
1145 | coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; | |
1146 | ||
1147 | if (coex_rfe->ant_switch_diversity && | |
1148 | ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) | |
1149 | ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; | |
1150 | ||
1151 | polarity_inverse = (coex_rfe->ant_switch_polarity == 1); | |
1152 | ||
1153 | switch (ctrl_type) { | |
1154 | default: | |
1155 | case COEX_SWITCH_CTRL_BY_BBSW: | |
1156 | /* 0x4c[23] = 0 */ | |
1157 | rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); | |
1158 | /* 0x4c[24] = 1 */ | |
1159 | rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); | |
1160 | /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ | |
1161 | rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); | |
1162 | ||
1163 | if (pos_type == COEX_SWITCH_TO_WLG_BT) { | |
1164 | if (coex_rfe->rfe_module_type != 0x4 && | |
1165 | coex_rfe->rfe_module_type != 0x2) | |
1166 | regval = 0x3; | |
1167 | else | |
1168 | regval = (!polarity_inverse ? 0x2 : 0x1); | |
1169 | } else if (pos_type == COEX_SWITCH_TO_WLG) { | |
1170 | regval = (!polarity_inverse ? 0x2 : 0x1); | |
1171 | } else { | |
1172 | regval = (!polarity_inverse ? 0x1 : 0x2); | |
1173 | } | |
1174 | ||
1175 | rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); | |
1176 | break; | |
1177 | case COEX_SWITCH_CTRL_BY_PTA: | |
1178 | /* 0x4c[23] = 0 */ | |
1179 | rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); | |
1180 | /* 0x4c[24] = 1 */ | |
1181 | rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); | |
1182 | /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ | |
1183 | rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); | |
1184 | ||
1185 | regval = (!polarity_inverse ? 0x2 : 0x1); | |
1186 | rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); | |
1187 | break; | |
1188 | case COEX_SWITCH_CTRL_BY_ANTDIV: | |
1189 | /* 0x4c[23] = 0 */ | |
1190 | rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); | |
1191 | /* 0x4c[24] = 1 */ | |
1192 | rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); | |
1193 | rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); | |
1194 | break; | |
1195 | case COEX_SWITCH_CTRL_BY_MAC: | |
1196 | /* 0x4c[23] = 1 */ | |
1197 | rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); | |
1198 | ||
1199 | regval = (!polarity_inverse ? 0x0 : 0x1); | |
1200 | rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); | |
1201 | break; | |
1202 | case COEX_SWITCH_CTRL_BY_FW: | |
1203 | /* 0x4c[23] = 0 */ | |
1204 | rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); | |
1205 | /* 0x4c[24] = 1 */ | |
1206 | rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); | |
1207 | break; | |
1208 | case COEX_SWITCH_CTRL_BY_BT: | |
1209 | /* 0x4c[23] = 0 */ | |
1210 | rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); | |
1211 | /* 0x4c[24] = 0 */ | |
1212 | rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); | |
1213 | break; | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) | |
1218 | { | |
1219 | } | |
1220 | ||
1221 | static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) | |
1222 | { | |
1223 | rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); | |
1224 | rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); | |
1225 | rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); | |
1226 | rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); | |
1227 | rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); | |
1228 | } | |
1229 | ||
1230 | static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev) | |
1231 | { | |
1232 | struct rtw_coex *coex = &rtwdev->coex; | |
1233 | struct rtw_coex_rfe *coex_rfe = &coex->rfe; | |
1234 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
1235 | bool is_ext_fem = false; | |
1236 | ||
1237 | coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; | |
1238 | coex_rfe->ant_switch_polarity = 0; | |
1239 | coex_rfe->ant_switch_diversity = false; | |
1240 | if (coex_rfe->rfe_module_type == 0x12 || | |
1241 | coex_rfe->rfe_module_type == 0x15 || | |
1242 | coex_rfe->rfe_module_type == 0x16) | |
1243 | coex_rfe->ant_switch_exist = false; | |
1244 | else | |
1245 | coex_rfe->ant_switch_exist = true; | |
1246 | ||
1247 | if (coex_rfe->rfe_module_type == 2 || | |
1248 | coex_rfe->rfe_module_type == 4) { | |
1249 | rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true); | |
1250 | is_ext_fem = true; | |
1251 | } else { | |
1252 | rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false); | |
1253 | } | |
1254 | ||
1255 | coex_rfe->wlg_at_btg = false; | |
1256 | ||
1257 | if (efuse->share_ant && | |
1258 | coex_rfe->ant_switch_exist && !is_ext_fem) | |
1259 | coex_rfe->ant_switch_with_bt = true; | |
1260 | else | |
1261 | coex_rfe->ant_switch_with_bt = false; | |
1262 | ||
1263 | /* Ext switch buffer mux */ | |
1264 | rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); | |
1265 | rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); | |
1266 | rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); | |
1267 | ||
1268 | /* Disable LTE Coex Function in WiFi side */ | |
1269 | rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); | |
1270 | ||
1271 | /* BTC_CTT_WL_VS_LTE */ | |
1272 | rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); | |
1273 | ||
1274 | /* BTC_CTT_BT_VS_LTE */ | |
1275 | rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); | |
1276 | } | |
1277 | ||
1278 | static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) | |
1279 | { | |
1280 | struct rtw_coex *coex = &rtwdev->coex; | |
1281 | struct rtw_coex_dm *coex_dm = &coex->dm; | |
1282 | static const u16 reg_addr[] = {0xc58, 0xe58}; | |
1283 | static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; | |
1284 | u8 i, pwr; | |
1285 | ||
1286 | if (wl_pwr == coex_dm->cur_wl_pwr_lvl) | |
1287 | return; | |
1288 | ||
1289 | coex_dm->cur_wl_pwr_lvl = wl_pwr; | |
1290 | ||
1291 | if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) | |
1292 | coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; | |
1293 | ||
1294 | pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; | |
1295 | ||
1296 | for (i = 0; i < ARRAY_SIZE(reg_addr); i++) | |
1297 | rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); | |
1298 | } | |
1299 | ||
1300 | static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) | |
1301 | { | |
1302 | struct rtw_coex *coex = &rtwdev->coex; | |
1303 | struct rtw_coex_dm *coex_dm = &coex->dm; | |
1304 | /* WL Rx Low gain on */ | |
1305 | static const u32 wl_rx_low_gain_on[] = { | |
1306 | 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, | |
1307 | 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, | |
1308 | 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, | |
1309 | 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, | |
1310 | 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, | |
1311 | 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, | |
1312 | 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, | |
1313 | 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, | |
1314 | 0x007e0403 | |
1315 | }; | |
1316 | ||
1317 | /* WL Rx Low gain off */ | |
1318 | static const u32 wl_rx_low_gain_off[] = { | |
1319 | 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, | |
1320 | 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, | |
1321 | 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, | |
1322 | 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, | |
1323 | 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, | |
1324 | 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, | |
1325 | 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, | |
1326 | 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, | |
1327 | 0x007e0403 | |
1328 | }; | |
1329 | u8 i; | |
1330 | ||
1331 | if (low_gain == coex_dm->cur_wl_rx_low_gain_en) | |
1332 | return; | |
1333 | ||
1334 | coex_dm->cur_wl_rx_low_gain_en = low_gain; | |
1335 | ||
1336 | if (coex_dm->cur_wl_rx_low_gain_en) { | |
1337 | for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) | |
1338 | rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]); | |
1339 | ||
1340 | /* set Rx filter corner RCK offset */ | |
1341 | rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); | |
1342 | rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); | |
1343 | rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); | |
1344 | rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); | |
1345 | } else { | |
1346 | for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) | |
1347 | rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); | |
1348 | ||
1349 | /* set Rx filter corner RCK offset */ | |
1350 | rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); | |
1351 | rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); | |
1352 | rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); | |
1353 | rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); | |
1354 | } | |
1355 | } | |
1356 | ||
c97ee3e0 TEH |
1357 | static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, |
1358 | u8 tx_pwr_idx_offset, | |
1359 | s8 *txagc_idx, u8 *swing_idx) | |
1360 | { | |
1361 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
1362 | s8 delta_pwr_idx = dm_info->delta_power_index[path]; | |
1363 | u8 swing_upper_bound = dm_info->default_ofdm_index + 10; | |
1364 | u8 swing_lower_bound = 0; | |
1365 | u8 max_tx_pwr_idx_offset = 0xf; | |
1366 | s8 agc_index = 0; | |
1367 | u8 swing_index = dm_info->default_ofdm_index; | |
1368 | ||
1369 | tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); | |
1370 | ||
1371 | if (delta_pwr_idx >= 0) { | |
1372 | if (delta_pwr_idx <= tx_pwr_idx_offset) { | |
1373 | agc_index = delta_pwr_idx; | |
1374 | swing_index = dm_info->default_ofdm_index; | |
1375 | } else if (delta_pwr_idx > tx_pwr_idx_offset) { | |
1376 | agc_index = tx_pwr_idx_offset; | |
1377 | swing_index = dm_info->default_ofdm_index + | |
1378 | delta_pwr_idx - tx_pwr_idx_offset; | |
1379 | swing_index = min_t(u8, swing_index, swing_upper_bound); | |
1380 | } | |
1381 | } else { | |
1382 | if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) | |
1383 | swing_index = | |
1384 | dm_info->default_ofdm_index + delta_pwr_idx; | |
1385 | else | |
1386 | swing_index = swing_lower_bound; | |
1387 | swing_index = max_t(u8, swing_index, swing_lower_bound); | |
1388 | ||
1389 | agc_index = 0; | |
1390 | } | |
1391 | ||
1392 | if (swing_index >= RTW_TXSCALE_SIZE) { | |
1393 | rtw_warn(rtwdev, "swing index overflow\n"); | |
1394 | swing_index = RTW_TXSCALE_SIZE - 1; | |
1395 | } | |
1396 | *txagc_idx = agc_index; | |
1397 | *swing_idx = swing_index; | |
1398 | } | |
1399 | ||
1400 | static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, | |
1401 | u8 pwr_idx_offset) | |
1402 | { | |
1403 | s8 txagc_idx; | |
1404 | u8 swing_idx; | |
1405 | u32 reg1, reg2; | |
1406 | ||
1407 | if (path == RF_PATH_A) { | |
1408 | reg1 = 0xc94; | |
1409 | reg2 = 0xc1c; | |
1410 | } else if (path == RF_PATH_B) { | |
1411 | reg1 = 0xe94; | |
1412 | reg2 = 0xe1c; | |
1413 | } else { | |
1414 | return; | |
1415 | } | |
1416 | ||
1417 | rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset, | |
1418 | &txagc_idx, &swing_idx); | |
1419 | rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx); | |
1420 | rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21), | |
1421 | rtw8822b_txscale_tbl[swing_idx]); | |
1422 | } | |
1423 | ||
1424 | static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) | |
1425 | { | |
1426 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
1427 | u8 pwr_idx_offset, tx_pwr_idx; | |
1428 | u8 channel = rtwdev->hal.current_channel; | |
1429 | u8 band_width = rtwdev->hal.current_band_width; | |
1430 | u8 regd = rtwdev->regd.txpwr_regd; | |
1431 | u8 tx_rate = dm_info->tx_rate; | |
1432 | u8 max_pwr_idx = rtwdev->chip->max_power_index; | |
1433 | ||
1434 | tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, | |
1435 | band_width, channel, regd); | |
1436 | ||
1437 | tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); | |
1438 | ||
1439 | pwr_idx_offset = max_pwr_idx - tx_pwr_idx; | |
1440 | ||
1441 | rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); | |
1442 | } | |
1443 | ||
1444 | static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev, | |
1445 | struct rtw_swing_table *swing_table, | |
1446 | u8 path) | |
1447 | { | |
1448 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
1449 | u8 power_idx_cur, power_idx_last; | |
1450 | u8 delta; | |
1451 | ||
1452 | /* 8822B only has one thermal meter at PATH A */ | |
1453 | delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); | |
1454 | ||
1455 | power_idx_last = dm_info->delta_power_index[path]; | |
1456 | power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, | |
1457 | path, RF_PATH_A, delta); | |
1458 | ||
1459 | /* if delta of power indexes are the same, just skip */ | |
1460 | if (power_idx_cur == power_idx_last) | |
1461 | return; | |
1462 | ||
1463 | dm_info->delta_power_index[path] = power_idx_cur; | |
1464 | rtw8822b_pwrtrack_set(rtwdev, path); | |
1465 | } | |
1466 | ||
1467 | static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev) | |
1468 | { | |
1469 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
1470 | struct rtw_swing_table swing_table; | |
1471 | u8 thermal_value, path; | |
1472 | ||
1473 | rtw_phy_config_swing_table(rtwdev, &swing_table); | |
1474 | ||
1475 | if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) | |
1476 | return; | |
1477 | ||
1478 | thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); | |
1479 | ||
1480 | rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); | |
1481 | ||
1482 | if (dm_info->pwr_trk_init_trigger) | |
1483 | dm_info->pwr_trk_init_trigger = false; | |
1484 | else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, | |
1485 | RF_PATH_A)) | |
1486 | goto iqk; | |
1487 | ||
1488 | for (path = 0; path < rtwdev->hal.rf_path_num; path++) | |
1489 | rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path); | |
1490 | ||
1491 | iqk: | |
1492 | if (rtw_phy_pwrtrack_need_iqk(rtwdev)) | |
1493 | rtw8822b_do_iqk(rtwdev); | |
1494 | } | |
1495 | ||
a969cf42 | 1496 | static void rtw8822b_pwr_track(struct rtw_dev *rtwdev) |
c97ee3e0 TEH |
1497 | { |
1498 | struct rtw_efuse *efuse = &rtwdev->efuse; | |
1499 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; | |
1500 | ||
1501 | if (efuse->power_track_type != 0) | |
1502 | return; | |
1503 | ||
1504 | if (!dm_info->pwr_trk_triggered) { | |
1505 | rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, | |
1506 | GENMASK(17, 16), 0x03); | |
1507 | dm_info->pwr_trk_triggered = true; | |
1508 | return; | |
1509 | } | |
1510 | ||
1511 | rtw8822b_phy_pwrtrack(rtwdev); | |
1512 | dm_info->pwr_trk_triggered = false; | |
1513 | } | |
1514 | ||
0bd95573 TEH |
1515 | static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev, |
1516 | struct rtw_vif *vif, | |
1517 | struct rtw_bfee *bfee, bool enable) | |
1518 | { | |
1519 | if (enable) | |
1520 | rtw_bf_enable_bfee_su(rtwdev, vif, bfee); | |
1521 | else | |
1522 | rtw_bf_remove_bfee_su(rtwdev, bfee); | |
1523 | } | |
1524 | ||
1525 | static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev, | |
1526 | struct rtw_vif *vif, | |
1527 | struct rtw_bfee *bfee, bool enable) | |
1528 | { | |
1529 | if (enable) | |
1530 | rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); | |
1531 | else | |
1532 | rtw_bf_remove_bfee_mu(rtwdev, bfee); | |
1533 | } | |
1534 | ||
1535 | static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, | |
1536 | struct rtw_bfee *bfee, bool enable) | |
1537 | { | |
1538 | if (bfee->role == RTW_BFEE_SU) | |
1539 | rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable); | |
1540 | else if (bfee->role == RTW_BFEE_MU) | |
1541 | rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable); | |
1542 | else | |
1543 | rtw_warn(rtwdev, "wrong bfee role\n"); | |
1544 | } | |
1545 | ||
e3037485 YHC |
1546 | static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = { |
1547 | {0x0086, | |
1548 | RTW_PWR_CUT_ALL_MSK, | |
1549 | RTW_PWR_INTF_SDIO_MSK, | |
1550 | RTW_PWR_ADDR_SDIO, | |
1551 | RTW_PWR_CMD_WRITE, BIT(0), 0}, | |
1552 | {0x0086, | |
1553 | RTW_PWR_CUT_ALL_MSK, | |
1554 | RTW_PWR_INTF_SDIO_MSK, | |
1555 | RTW_PWR_ADDR_SDIO, | |
1556 | RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, | |
1557 | {0x004A, | |
1558 | RTW_PWR_CUT_ALL_MSK, | |
1559 | RTW_PWR_INTF_USB_MSK, | |
1560 | RTW_PWR_ADDR_MAC, | |
1561 | RTW_PWR_CMD_WRITE, BIT(0), 0}, | |
1562 | {0x0005, | |
1563 | RTW_PWR_CUT_ALL_MSK, | |
1564 | RTW_PWR_INTF_ALL_MSK, | |
1565 | RTW_PWR_ADDR_MAC, | |
1566 | RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, | |
1567 | {0x0300, | |
1568 | RTW_PWR_CUT_ALL_MSK, | |
1569 | RTW_PWR_INTF_PCI_MSK, | |
1570 | RTW_PWR_ADDR_MAC, | |
1571 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1572 | {0x0301, | |
1573 | RTW_PWR_CUT_ALL_MSK, | |
1574 | RTW_PWR_INTF_PCI_MSK, | |
1575 | RTW_PWR_ADDR_MAC, | |
1576 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1577 | {0xFFFF, | |
1578 | RTW_PWR_CUT_ALL_MSK, | |
1579 | RTW_PWR_INTF_ALL_MSK, | |
1580 | 0, | |
1581 | RTW_PWR_CMD_END, 0, 0}, | |
1582 | }; | |
1583 | ||
1584 | static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = { | |
1585 | {0x0012, | |
1586 | RTW_PWR_CUT_ALL_MSK, | |
1587 | RTW_PWR_INTF_ALL_MSK, | |
1588 | RTW_PWR_ADDR_MAC, | |
1589 | RTW_PWR_CMD_WRITE, BIT(1), 0}, | |
1590 | {0x0012, | |
1591 | RTW_PWR_CUT_ALL_MSK, | |
1592 | RTW_PWR_INTF_ALL_MSK, | |
1593 | RTW_PWR_ADDR_MAC, | |
1594 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1595 | {0x0020, | |
1596 | RTW_PWR_CUT_ALL_MSK, | |
1597 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, | |
1598 | RTW_PWR_ADDR_MAC, | |
1599 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1600 | {0x0001, | |
1601 | RTW_PWR_CUT_ALL_MSK, | |
1602 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, | |
1603 | RTW_PWR_ADDR_MAC, | |
1604 | RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, | |
1605 | {0x0000, | |
1606 | RTW_PWR_CUT_ALL_MSK, | |
1607 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, | |
1608 | RTW_PWR_ADDR_MAC, | |
1609 | RTW_PWR_CMD_WRITE, BIT(5), 0}, | |
1610 | {0x0005, | |
1611 | RTW_PWR_CUT_ALL_MSK, | |
1612 | RTW_PWR_INTF_ALL_MSK, | |
1613 | RTW_PWR_ADDR_MAC, | |
1614 | RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, | |
1615 | {0x0075, | |
1616 | RTW_PWR_CUT_ALL_MSK, | |
1617 | RTW_PWR_INTF_PCI_MSK, | |
1618 | RTW_PWR_ADDR_MAC, | |
1619 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1620 | {0x0006, | |
1621 | RTW_PWR_CUT_ALL_MSK, | |
1622 | RTW_PWR_INTF_ALL_MSK, | |
1623 | RTW_PWR_ADDR_MAC, | |
1624 | RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, | |
1625 | {0x0075, | |
1626 | RTW_PWR_CUT_ALL_MSK, | |
1627 | RTW_PWR_INTF_PCI_MSK, | |
1628 | RTW_PWR_ADDR_MAC, | |
1629 | RTW_PWR_CMD_WRITE, BIT(0), 0}, | |
1630 | {0xFF1A, | |
1631 | RTW_PWR_CUT_ALL_MSK, | |
1632 | RTW_PWR_INTF_USB_MSK, | |
1633 | RTW_PWR_ADDR_MAC, | |
1634 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1635 | {0x0006, | |
1636 | RTW_PWR_CUT_ALL_MSK, | |
1637 | RTW_PWR_INTF_ALL_MSK, | |
1638 | RTW_PWR_ADDR_MAC, | |
1639 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1640 | {0x0005, | |
1641 | RTW_PWR_CUT_ALL_MSK, | |
1642 | RTW_PWR_INTF_ALL_MSK, | |
1643 | RTW_PWR_ADDR_MAC, | |
1644 | RTW_PWR_CMD_WRITE, BIT(7), 0}, | |
1645 | {0x0005, | |
1646 | RTW_PWR_CUT_ALL_MSK, | |
1647 | RTW_PWR_INTF_ALL_MSK, | |
1648 | RTW_PWR_ADDR_MAC, | |
1649 | RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, | |
1650 | {0x10C3, | |
1651 | RTW_PWR_CUT_ALL_MSK, | |
1652 | RTW_PWR_INTF_USB_MSK, | |
1653 | RTW_PWR_ADDR_MAC, | |
1654 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1655 | {0x0005, | |
1656 | RTW_PWR_CUT_ALL_MSK, | |
1657 | RTW_PWR_INTF_ALL_MSK, | |
1658 | RTW_PWR_ADDR_MAC, | |
1659 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1660 | {0x0005, | |
1661 | RTW_PWR_CUT_ALL_MSK, | |
1662 | RTW_PWR_INTF_ALL_MSK, | |
1663 | RTW_PWR_ADDR_MAC, | |
1664 | RTW_PWR_CMD_POLLING, BIT(0), 0}, | |
1665 | {0x0020, | |
1666 | RTW_PWR_CUT_ALL_MSK, | |
1667 | RTW_PWR_INTF_ALL_MSK, | |
1668 | RTW_PWR_ADDR_MAC, | |
1669 | RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, | |
1670 | {0x10A8, | |
1671 | RTW_PWR_CUT_C_MSK, | |
1672 | RTW_PWR_INTF_ALL_MSK, | |
1673 | RTW_PWR_ADDR_MAC, | |
1674 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1675 | {0x10A9, | |
1676 | RTW_PWR_CUT_C_MSK, | |
1677 | RTW_PWR_INTF_ALL_MSK, | |
1678 | RTW_PWR_ADDR_MAC, | |
1679 | RTW_PWR_CMD_WRITE, 0xFF, 0xef}, | |
1680 | {0x10AA, | |
1681 | RTW_PWR_CUT_C_MSK, | |
1682 | RTW_PWR_INTF_ALL_MSK, | |
1683 | RTW_PWR_ADDR_MAC, | |
1684 | RTW_PWR_CMD_WRITE, 0xFF, 0x0c}, | |
1685 | {0x0068, | |
1686 | RTW_PWR_CUT_C_MSK, | |
1687 | RTW_PWR_INTF_SDIO_MSK, | |
1688 | RTW_PWR_ADDR_MAC, | |
1689 | RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, | |
1690 | {0x0029, | |
1691 | RTW_PWR_CUT_ALL_MSK, | |
1692 | RTW_PWR_INTF_ALL_MSK, | |
1693 | RTW_PWR_ADDR_MAC, | |
1694 | RTW_PWR_CMD_WRITE, 0xFF, 0xF9}, | |
1695 | {0x0024, | |
1696 | RTW_PWR_CUT_ALL_MSK, | |
1697 | RTW_PWR_INTF_ALL_MSK, | |
1698 | RTW_PWR_ADDR_MAC, | |
1699 | RTW_PWR_CMD_WRITE, BIT(2), 0}, | |
1700 | {0x0074, | |
1701 | RTW_PWR_CUT_ALL_MSK, | |
1702 | RTW_PWR_INTF_PCI_MSK, | |
1703 | RTW_PWR_ADDR_MAC, | |
1704 | RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, | |
1705 | {0x00AF, | |
1706 | RTW_PWR_CUT_ALL_MSK, | |
1707 | RTW_PWR_INTF_ALL_MSK, | |
1708 | RTW_PWR_ADDR_MAC, | |
1709 | RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, | |
1710 | {0xFFFF, | |
1711 | RTW_PWR_CUT_ALL_MSK, | |
1712 | RTW_PWR_INTF_ALL_MSK, | |
1713 | 0, | |
1714 | RTW_PWR_CMD_END, 0, 0}, | |
1715 | }; | |
1716 | ||
1717 | static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = { | |
1718 | {0x0003, | |
1719 | RTW_PWR_CUT_ALL_MSK, | |
1720 | RTW_PWR_INTF_SDIO_MSK, | |
1721 | RTW_PWR_ADDR_MAC, | |
1722 | RTW_PWR_CMD_WRITE, BIT(2), 0}, | |
1723 | {0x0093, | |
1724 | RTW_PWR_CUT_ALL_MSK, | |
1725 | RTW_PWR_INTF_ALL_MSK, | |
1726 | RTW_PWR_ADDR_MAC, | |
1727 | RTW_PWR_CMD_WRITE, BIT(3), 0}, | |
1728 | {0x001F, | |
1729 | RTW_PWR_CUT_ALL_MSK, | |
1730 | RTW_PWR_INTF_ALL_MSK, | |
1731 | RTW_PWR_ADDR_MAC, | |
1732 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1733 | {0x00EF, | |
1734 | RTW_PWR_CUT_ALL_MSK, | |
1735 | RTW_PWR_INTF_ALL_MSK, | |
1736 | RTW_PWR_ADDR_MAC, | |
1737 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1738 | {0xFF1A, | |
1739 | RTW_PWR_CUT_ALL_MSK, | |
1740 | RTW_PWR_INTF_USB_MSK, | |
1741 | RTW_PWR_ADDR_MAC, | |
1742 | RTW_PWR_CMD_WRITE, 0xFF, 0x30}, | |
1743 | {0x0049, | |
1744 | RTW_PWR_CUT_ALL_MSK, | |
1745 | RTW_PWR_INTF_ALL_MSK, | |
1746 | RTW_PWR_ADDR_MAC, | |
1747 | RTW_PWR_CMD_WRITE, BIT(1), 0}, | |
1748 | {0x0006, | |
1749 | RTW_PWR_CUT_ALL_MSK, | |
1750 | RTW_PWR_INTF_ALL_MSK, | |
1751 | RTW_PWR_ADDR_MAC, | |
1752 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1753 | {0x0002, | |
1754 | RTW_PWR_CUT_ALL_MSK, | |
1755 | RTW_PWR_INTF_ALL_MSK, | |
1756 | RTW_PWR_ADDR_MAC, | |
1757 | RTW_PWR_CMD_WRITE, BIT(1), 0}, | |
1758 | {0x10C3, | |
1759 | RTW_PWR_CUT_ALL_MSK, | |
1760 | RTW_PWR_INTF_USB_MSK, | |
1761 | RTW_PWR_ADDR_MAC, | |
1762 | RTW_PWR_CMD_WRITE, BIT(0), 0}, | |
1763 | {0x0005, | |
1764 | RTW_PWR_CUT_ALL_MSK, | |
1765 | RTW_PWR_INTF_ALL_MSK, | |
1766 | RTW_PWR_ADDR_MAC, | |
1767 | RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, | |
1768 | {0x0005, | |
1769 | RTW_PWR_CUT_ALL_MSK, | |
1770 | RTW_PWR_INTF_ALL_MSK, | |
1771 | RTW_PWR_ADDR_MAC, | |
1772 | RTW_PWR_CMD_POLLING, BIT(1), 0}, | |
1773 | {0x0020, | |
1774 | RTW_PWR_CUT_ALL_MSK, | |
1775 | RTW_PWR_INTF_ALL_MSK, | |
1776 | RTW_PWR_ADDR_MAC, | |
1777 | RTW_PWR_CMD_WRITE, BIT(3), 0}, | |
1778 | {0x0000, | |
1779 | RTW_PWR_CUT_ALL_MSK, | |
1780 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, | |
1781 | RTW_PWR_ADDR_MAC, | |
1782 | RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, | |
1783 | {0xFFFF, | |
1784 | RTW_PWR_CUT_ALL_MSK, | |
1785 | RTW_PWR_INTF_ALL_MSK, | |
1786 | 0, | |
1787 | RTW_PWR_CMD_END, 0, 0}, | |
1788 | }; | |
1789 | ||
1790 | static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = { | |
1791 | {0x0005, | |
1792 | RTW_PWR_CUT_ALL_MSK, | |
1793 | RTW_PWR_INTF_SDIO_MSK, | |
1794 | RTW_PWR_ADDR_MAC, | |
1795 | RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, | |
1796 | {0x0007, | |
1797 | RTW_PWR_CUT_ALL_MSK, | |
1798 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, | |
1799 | RTW_PWR_ADDR_MAC, | |
1800 | RTW_PWR_CMD_WRITE, 0xFF, 0x20}, | |
1801 | {0x0067, | |
1802 | RTW_PWR_CUT_ALL_MSK, | |
1803 | RTW_PWR_INTF_ALL_MSK, | |
1804 | RTW_PWR_ADDR_MAC, | |
1805 | RTW_PWR_CMD_WRITE, BIT(5), 0}, | |
1806 | {0x0005, | |
1807 | RTW_PWR_CUT_ALL_MSK, | |
1808 | RTW_PWR_INTF_PCI_MSK, | |
1809 | RTW_PWR_ADDR_MAC, | |
1810 | RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, | |
1811 | {0x004A, | |
1812 | RTW_PWR_CUT_ALL_MSK, | |
1813 | RTW_PWR_INTF_USB_MSK, | |
1814 | RTW_PWR_ADDR_MAC, | |
1815 | RTW_PWR_CMD_WRITE, BIT(0), 0}, | |
1816 | {0x0067, | |
1817 | RTW_PWR_CUT_ALL_MSK, | |
1818 | RTW_PWR_INTF_SDIO_MSK, | |
1819 | RTW_PWR_ADDR_MAC, | |
1820 | RTW_PWR_CMD_WRITE, BIT(5), 0}, | |
1821 | {0x0067, | |
1822 | RTW_PWR_CUT_ALL_MSK, | |
1823 | RTW_PWR_INTF_SDIO_MSK, | |
1824 | RTW_PWR_ADDR_MAC, | |
1825 | RTW_PWR_CMD_WRITE, BIT(4), 0}, | |
1826 | {0x004F, | |
1827 | RTW_PWR_CUT_ALL_MSK, | |
1828 | RTW_PWR_INTF_SDIO_MSK, | |
1829 | RTW_PWR_ADDR_MAC, | |
1830 | RTW_PWR_CMD_WRITE, BIT(0), 0}, | |
1831 | {0x0067, | |
1832 | RTW_PWR_CUT_ALL_MSK, | |
1833 | RTW_PWR_INTF_SDIO_MSK, | |
1834 | RTW_PWR_ADDR_MAC, | |
1835 | RTW_PWR_CMD_WRITE, BIT(1), 0}, | |
1836 | {0x0046, | |
1837 | RTW_PWR_CUT_ALL_MSK, | |
1838 | RTW_PWR_INTF_SDIO_MSK, | |
1839 | RTW_PWR_ADDR_MAC, | |
1840 | RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, | |
1841 | {0x0067, | |
1842 | RTW_PWR_CUT_ALL_MSK, | |
1843 | RTW_PWR_INTF_SDIO_MSK, | |
1844 | RTW_PWR_ADDR_MAC, | |
1845 | RTW_PWR_CMD_WRITE, BIT(2), 0}, | |
1846 | {0x0046, | |
1847 | RTW_PWR_CUT_ALL_MSK, | |
1848 | RTW_PWR_INTF_SDIO_MSK, | |
1849 | RTW_PWR_ADDR_MAC, | |
1850 | RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, | |
1851 | {0x0062, | |
1852 | RTW_PWR_CUT_ALL_MSK, | |
1853 | RTW_PWR_INTF_SDIO_MSK, | |
1854 | RTW_PWR_ADDR_MAC, | |
1855 | RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, | |
1856 | {0x0081, | |
1857 | RTW_PWR_CUT_ALL_MSK, | |
1858 | RTW_PWR_INTF_ALL_MSK, | |
1859 | RTW_PWR_ADDR_MAC, | |
1860 | RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, | |
1861 | {0x0005, | |
1862 | RTW_PWR_CUT_ALL_MSK, | |
1863 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, | |
1864 | RTW_PWR_ADDR_MAC, | |
1865 | RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, | |
1866 | {0x0086, | |
1867 | RTW_PWR_CUT_ALL_MSK, | |
1868 | RTW_PWR_INTF_SDIO_MSK, | |
1869 | RTW_PWR_ADDR_SDIO, | |
1870 | RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, | |
1871 | {0x0086, | |
1872 | RTW_PWR_CUT_ALL_MSK, | |
1873 | RTW_PWR_INTF_SDIO_MSK, | |
1874 | RTW_PWR_ADDR_SDIO, | |
1875 | RTW_PWR_CMD_POLLING, BIT(1), 0}, | |
1876 | {0x0090, | |
1877 | RTW_PWR_CUT_ALL_MSK, | |
1878 | RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, | |
1879 | RTW_PWR_ADDR_MAC, | |
1880 | RTW_PWR_CMD_WRITE, BIT(1), 0}, | |
1881 | {0x0044, | |
1882 | RTW_PWR_CUT_ALL_MSK, | |
1883 | RTW_PWR_INTF_SDIO_MSK, | |
1884 | RTW_PWR_ADDR_SDIO, | |
1885 | RTW_PWR_CMD_WRITE, 0xFF, 0}, | |
1886 | {0x0040, | |
1887 | RTW_PWR_CUT_ALL_MSK, | |
1888 | RTW_PWR_INTF_SDIO_MSK, | |
1889 | RTW_PWR_ADDR_SDIO, | |
1890 | RTW_PWR_CMD_WRITE, 0xFF, 0x90}, | |
1891 | {0x0041, | |
1892 | RTW_PWR_CUT_ALL_MSK, | |
1893 | RTW_PWR_INTF_SDIO_MSK, | |
1894 | RTW_PWR_ADDR_SDIO, | |
1895 | RTW_PWR_CMD_WRITE, 0xFF, 0x00}, | |
1896 | {0x0042, | |
1897 | RTW_PWR_CUT_ALL_MSK, | |
1898 | RTW_PWR_INTF_SDIO_MSK, | |
1899 | RTW_PWR_ADDR_SDIO, | |
1900 | RTW_PWR_CMD_WRITE, 0xFF, 0x04}, | |
1901 | {0xFFFF, | |
1902 | RTW_PWR_CUT_ALL_MSK, | |
1903 | RTW_PWR_INTF_ALL_MSK, | |
1904 | 0, | |
1905 | RTW_PWR_CMD_END, 0, 0}, | |
1906 | }; | |
1907 | ||
1908 | static struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = { | |
1909 | trans_carddis_to_cardemu_8822b, | |
1910 | trans_cardemu_to_act_8822b, | |
1911 | NULL | |
1912 | }; | |
1913 | ||
1914 | static struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = { | |
1915 | trans_act_to_cardemu_8822b, | |
1916 | trans_cardemu_to_carddis_8822b, | |
1917 | NULL | |
1918 | }; | |
1919 | ||
1920 | static struct rtw_intf_phy_para usb2_param_8822b[] = { | |
1921 | {0xFFFF, 0x00, | |
1922 | RTW_IP_SEL_PHY, | |
1923 | RTW_INTF_PHY_CUT_ALL, | |
1924 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1925 | }; | |
1926 | ||
1927 | static struct rtw_intf_phy_para usb3_param_8822b[] = { | |
1928 | {0x0001, 0xA841, | |
1929 | RTW_IP_SEL_PHY, | |
1930 | RTW_INTF_PHY_CUT_D, | |
1931 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1932 | {0xFFFF, 0x0000, | |
1933 | RTW_IP_SEL_PHY, | |
1934 | RTW_INTF_PHY_CUT_ALL, | |
1935 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1936 | }; | |
1937 | ||
1938 | static struct rtw_intf_phy_para pcie_gen1_param_8822b[] = { | |
1939 | {0x0001, 0xA841, | |
1940 | RTW_IP_SEL_PHY, | |
1941 | RTW_INTF_PHY_CUT_C, | |
1942 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1943 | {0x0002, 0x60C6, | |
1944 | RTW_IP_SEL_PHY, | |
1945 | RTW_INTF_PHY_CUT_C, | |
1946 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1947 | {0x0008, 0x3596, | |
1948 | RTW_IP_SEL_PHY, | |
1949 | RTW_INTF_PHY_CUT_C, | |
1950 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1951 | {0x0009, 0x321C, | |
1952 | RTW_IP_SEL_PHY, | |
1953 | RTW_INTF_PHY_CUT_C, | |
1954 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1955 | {0x000A, 0x9623, | |
1956 | RTW_IP_SEL_PHY, | |
1957 | RTW_INTF_PHY_CUT_C, | |
1958 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1959 | {0x0020, 0x94FF, | |
1960 | RTW_IP_SEL_PHY, | |
1961 | RTW_INTF_PHY_CUT_C, | |
1962 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1963 | {0x0021, 0xFFCF, | |
1964 | RTW_IP_SEL_PHY, | |
1965 | RTW_INTF_PHY_CUT_C, | |
1966 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1967 | {0x0026, 0xC006, | |
1968 | RTW_IP_SEL_PHY, | |
1969 | RTW_INTF_PHY_CUT_C, | |
1970 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1971 | {0x0029, 0xFF0E, | |
1972 | RTW_IP_SEL_PHY, | |
1973 | RTW_INTF_PHY_CUT_C, | |
1974 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1975 | {0x002A, 0x1840, | |
1976 | RTW_IP_SEL_PHY, | |
1977 | RTW_INTF_PHY_CUT_C, | |
1978 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1979 | {0xFFFF, 0x0000, | |
1980 | RTW_IP_SEL_PHY, | |
1981 | RTW_INTF_PHY_CUT_ALL, | |
1982 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1983 | }; | |
1984 | ||
1985 | static struct rtw_intf_phy_para pcie_gen2_param_8822b[] = { | |
1986 | {0x0001, 0xA841, | |
1987 | RTW_IP_SEL_PHY, | |
1988 | RTW_INTF_PHY_CUT_C, | |
1989 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1990 | {0x0002, 0x60C6, | |
1991 | RTW_IP_SEL_PHY, | |
1992 | RTW_INTF_PHY_CUT_C, | |
1993 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1994 | {0x0008, 0x3597, | |
1995 | RTW_IP_SEL_PHY, | |
1996 | RTW_INTF_PHY_CUT_C, | |
1997 | RTW_INTF_PHY_PLATFORM_ALL}, | |
1998 | {0x0009, 0x321C, | |
1999 | RTW_IP_SEL_PHY, | |
2000 | RTW_INTF_PHY_CUT_C, | |
2001 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2002 | {0x000A, 0x9623, | |
2003 | RTW_IP_SEL_PHY, | |
2004 | RTW_INTF_PHY_CUT_C, | |
2005 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2006 | {0x0020, 0x94FF, | |
2007 | RTW_IP_SEL_PHY, | |
2008 | RTW_INTF_PHY_CUT_C, | |
2009 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2010 | {0x0021, 0xFFCF, | |
2011 | RTW_IP_SEL_PHY, | |
2012 | RTW_INTF_PHY_CUT_C, | |
2013 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2014 | {0x0026, 0xC006, | |
2015 | RTW_IP_SEL_PHY, | |
2016 | RTW_INTF_PHY_CUT_C, | |
2017 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2018 | {0x0029, 0xFF0E, | |
2019 | RTW_IP_SEL_PHY, | |
2020 | RTW_INTF_PHY_CUT_C, | |
2021 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2022 | {0x002A, 0x3040, | |
2023 | RTW_IP_SEL_PHY, | |
2024 | RTW_INTF_PHY_CUT_C, | |
2025 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2026 | {0xFFFF, 0x0000, | |
2027 | RTW_IP_SEL_PHY, | |
2028 | RTW_INTF_PHY_CUT_ALL, | |
2029 | RTW_INTF_PHY_PLATFORM_ALL}, | |
2030 | }; | |
2031 | ||
2032 | static struct rtw_intf_phy_para_table phy_para_table_8822b = { | |
2033 | .usb2_para = usb2_param_8822b, | |
2034 | .usb3_para = usb3_param_8822b, | |
2035 | .gen1_para = pcie_gen1_param_8822b, | |
2036 | .gen2_para = pcie_gen2_param_8822b, | |
2037 | .n_usb2_para = ARRAY_SIZE(usb2_param_8822b), | |
2038 | .n_usb3_para = ARRAY_SIZE(usb2_param_8822b), | |
2039 | .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b), | |
2040 | .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b), | |
2041 | }; | |
2042 | ||
2043 | static const struct rtw_rfe_def rtw8822b_rfe_defs[] = { | |
2044 | [2] = RTW_DEF_RFE(8822b, 2, 2), | |
7436a470 | 2045 | [3] = RTW_DEF_RFE(8822b, 3, 0), |
e3037485 YHC |
2046 | [5] = RTW_DEF_RFE(8822b, 5, 5), |
2047 | }; | |
2048 | ||
2049 | static struct rtw_hw_reg rtw8822b_dig[] = { | |
2050 | [0] = { .addr = 0xc50, .mask = 0x7f }, | |
2051 | [1] = { .addr = 0xe50, .mask = 0x7f }, | |
2052 | }; | |
2053 | ||
2054 | static struct rtw_page_table page_table_8822b[] = { | |
2055 | {64, 64, 64, 64, 1}, | |
2056 | {64, 64, 64, 64, 1}, | |
2057 | {64, 64, 0, 0, 1}, | |
2058 | {64, 64, 64, 0, 1}, | |
2059 | {64, 64, 64, 64, 1}, | |
2060 | }; | |
2061 | ||
2062 | static struct rtw_rqpn rqpn_table_8822b[] = { | |
2063 | {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, | |
2064 | RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, | |
2065 | RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, | |
2066 | {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, | |
2067 | RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, | |
2068 | RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, | |
2069 | {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, | |
2070 | RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, | |
2071 | RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, | |
2072 | {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, | |
2073 | RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, | |
2074 | RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, | |
2075 | {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, | |
2076 | RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, | |
2077 | RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, | |
2078 | }; | |
2079 | ||
2080 | static struct rtw_chip_ops rtw8822b_ops = { | |
2081 | .phy_set_param = rtw8822b_phy_set_param, | |
2082 | .read_efuse = rtw8822b_read_efuse, | |
2083 | .query_rx_desc = rtw8822b_query_rx_desc, | |
2084 | .set_channel = rtw8822b_set_channel, | |
2085 | .mac_init = rtw8822b_mac_init, | |
2086 | .read_rf = rtw_phy_read_rf, | |
2087 | .write_rf = rtw_phy_write_rf_reg_sipi, | |
2088 | .set_tx_power_index = rtw8822b_set_tx_power_index, | |
2089 | .set_antenna = rtw8822b_set_antenna, | |
2090 | .cfg_ldo25 = rtw8822b_cfg_ldo25, | |
2091 | .false_alarm_statistics = rtw8822b_false_alarm_statistics, | |
f27b886d | 2092 | .phy_calibration = rtw8822b_phy_calibration, |
c97ee3e0 | 2093 | .pwr_track = rtw8822b_pwr_track, |
0bd95573 TEH |
2094 | .config_bfee = rtw8822b_bf_config_bfee, |
2095 | .set_gid_table = rtw_bf_set_gid_table, | |
2096 | .cfg_csi_rate = rtw_bf_cfg_csi_rate, | |
4136214f YHC |
2097 | |
2098 | .coex_set_init = rtw8822b_coex_cfg_init, | |
2099 | .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch, | |
2100 | .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix, | |
2101 | .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug, | |
2102 | .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type, | |
2103 | .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power, | |
2104 | .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain, | |
2105 | }; | |
2106 | ||
2107 | /* Shared-Antenna Coex Table */ | |
2108 | static const struct coex_table_para table_sant_8822b[] = { | |
2109 | {0xffffffff, 0xffffffff}, /* case-0 */ | |
2110 | {0x55555555, 0x55555555}, | |
2111 | {0x66555555, 0x66555555}, | |
2112 | {0xaaaaaaaa, 0xaaaaaaaa}, | |
2113 | {0x5a5a5a5a, 0x5a5a5a5a}, | |
2114 | {0xfafafafa, 0xfafafafa}, /* case-5 */ | |
2115 | {0x6a5a6a5a, 0xaaaaaaaa}, | |
2116 | {0x6a5a56aa, 0x6a5a56aa}, | |
2117 | {0x6a5a5a5a, 0x6a5a5a5a}, | |
2118 | {0x66555555, 0x5a5a5a5a}, | |
2119 | {0x66555555, 0x6a5a5a5a}, /* case-10 */ | |
2120 | {0x66555555, 0xfafafafa}, | |
2121 | {0x66555555, 0x6a5a5aaa}, | |
2122 | {0x66555555, 0x5aaa5aaa}, | |
2123 | {0x66555555, 0xaaaa5aaa}, | |
2124 | {0x66555555, 0xaaaaaaaa}, /* case-15 */ | |
2125 | {0xffff55ff, 0xfafafafa}, | |
2126 | {0xffff55ff, 0x6afa5afa}, | |
2127 | {0xaaffffaa, 0xfafafafa}, | |
2128 | {0xaa5555aa, 0x5a5a5a5a}, | |
2129 | {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ | |
2130 | {0xaa5555aa, 0xaaaaaaaa}, | |
2131 | {0xffffffff, 0x5a5a5a5a}, | |
2132 | {0xffffffff, 0x6a5a5a5a}, | |
2133 | {0xffffffff, 0x55555555}, | |
2134 | {0xffffffff, 0x6a5a5aaa}, /* case-25 */ | |
2135 | {0x55555555, 0x5a5a5a5a}, | |
2136 | {0x55555555, 0xaaaaaaaa}, | |
2137 | {0x55555555, 0x6a5a6a5a}, | |
2138 | {0x66556655, 0x66556655} | |
2139 | }; | |
2140 | ||
2141 | /* Non-Shared-Antenna Coex Table */ | |
2142 | static const struct coex_table_para table_nsant_8822b[] = { | |
2143 | {0xffffffff, 0xffffffff}, /* case-100 */ | |
2144 | {0x55555555, 0x55555555}, | |
2145 | {0x66555555, 0x66555555}, | |
2146 | {0xaaaaaaaa, 0xaaaaaaaa}, | |
2147 | {0x5a5a5a5a, 0x5a5a5a5a}, | |
2148 | {0xfafafafa, 0xfafafafa}, /* case-105 */ | |
2149 | {0x5afa5afa, 0x5afa5afa}, | |
2150 | {0x55555555, 0xfafafafa}, | |
2151 | {0x66555555, 0xfafafafa}, | |
2152 | {0x66555555, 0x5a5a5a5a}, | |
2153 | {0x66555555, 0x6a5a5a5a}, /* case-110 */ | |
2154 | {0x66555555, 0xaaaaaaaa}, | |
2155 | {0xffff55ff, 0xfafafafa}, | |
2156 | {0xffff55ff, 0x5afa5afa}, | |
2157 | {0xffff55ff, 0xaaaaaaaa}, | |
2158 | {0xaaffffaa, 0xfafafafa}, /* case-115 */ | |
2159 | {0xaaffffaa, 0x5afa5afa}, | |
2160 | {0xaaffffaa, 0xaaaaaaaa}, | |
2161 | {0xffffffff, 0xfafafafa}, | |
2162 | {0xffffffff, 0x5afa5afa}, | |
2163 | {0xffffffff, 0xaaaaaaaa}, /* case-120 */ | |
2164 | {0x55ff55ff, 0x5afa5afa}, | |
2165 | {0x55ff55ff, 0xaaaaaaaa}, | |
2166 | {0x55ff55ff, 0x55ff55ff} | |
e3037485 YHC |
2167 | }; |
2168 | ||
4136214f YHC |
2169 | /* Shared-Antenna TDMA */ |
2170 | static const struct coex_tdma_para tdma_sant_8822b[] = { | |
2171 | { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ | |
2172 | { {0x61, 0x45, 0x03, 0x11, 0x11} }, | |
2173 | { {0x61, 0x3a, 0x03, 0x11, 0x11} }, | |
2174 | { {0x61, 0x30, 0x03, 0x11, 0x11} }, | |
2175 | { {0x61, 0x20, 0x03, 0x11, 0x11} }, | |
2176 | { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ | |
2177 | { {0x61, 0x45, 0x03, 0x11, 0x10} }, | |
2178 | { {0x61, 0x3a, 0x03, 0x11, 0x10} }, | |
2179 | { {0x61, 0x30, 0x03, 0x11, 0x10} }, | |
2180 | { {0x61, 0x20, 0x03, 0x11, 0x10} }, | |
2181 | { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ | |
2182 | { {0x61, 0x08, 0x03, 0x11, 0x14} }, | |
2183 | { {0x61, 0x08, 0x03, 0x10, 0x14} }, | |
2184 | { {0x51, 0x08, 0x03, 0x10, 0x54} }, | |
2185 | { {0x51, 0x08, 0x03, 0x10, 0x55} }, | |
2186 | { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ | |
2187 | { {0x51, 0x45, 0x03, 0x10, 0x10} }, | |
2188 | { {0x51, 0x3a, 0x03, 0x10, 0x50} }, | |
2189 | { {0x51, 0x30, 0x03, 0x10, 0x50} }, | |
2190 | { {0x51, 0x20, 0x03, 0x10, 0x50} }, | |
2191 | { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ | |
2192 | { {0x51, 0x4a, 0x03, 0x10, 0x50} }, | |
2193 | { {0x51, 0x0c, 0x03, 0x10, 0x54} }, | |
2194 | { {0x55, 0x08, 0x03, 0x10, 0x54} }, | |
2195 | { {0x65, 0x10, 0x03, 0x11, 0x11} }, | |
2196 | { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ | |
2197 | { {0x51, 0x08, 0x03, 0x10, 0x50} } | |
2198 | }; | |
2199 | ||
2200 | /* Non-Shared-Antenna TDMA */ | |
2201 | static const struct coex_tdma_para tdma_nsant_8822b[] = { | |
2202 | { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ | |
2203 | { {0x61, 0x45, 0x03, 0x11, 0x11} }, | |
2204 | { {0x61, 0x3a, 0x03, 0x11, 0x11} }, | |
2205 | { {0x61, 0x30, 0x03, 0x11, 0x11} }, | |
2206 | { {0x61, 0x20, 0x03, 0x11, 0x11} }, | |
2207 | { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ | |
2208 | { {0x61, 0x45, 0x03, 0x11, 0x10} }, | |
2209 | { {0x61, 0x3a, 0x03, 0x11, 0x10} }, | |
2210 | { {0x61, 0x30, 0x03, 0x11, 0x10} }, | |
2211 | { {0x61, 0x20, 0x03, 0x11, 0x10} }, | |
2212 | { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ | |
2213 | { {0x61, 0x08, 0x03, 0x11, 0x14} }, | |
2214 | { {0x61, 0x08, 0x03, 0x10, 0x14} }, | |
2215 | { {0x51, 0x08, 0x03, 0x10, 0x54} }, | |
2216 | { {0x51, 0x08, 0x03, 0x10, 0x55} }, | |
2217 | { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ | |
2218 | { {0x51, 0x45, 0x03, 0x10, 0x50} }, | |
2219 | { {0x51, 0x3a, 0x03, 0x10, 0x50} }, | |
2220 | { {0x51, 0x30, 0x03, 0x10, 0x50} }, | |
2221 | { {0x51, 0x20, 0x03, 0x10, 0x50} }, | |
2222 | { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ | |
2223 | }; | |
2224 | ||
2225 | /* rssi in percentage % (dbm = % - 100) */ | |
2226 | static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30}; | |
2227 | static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30}; | |
2228 | static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} }; | |
2229 | ||
2230 | /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ | |
2231 | static const struct coex_rf_para rf_para_tx_8822b[] = { | |
2232 | {0, 0, false, 7}, /* for normal */ | |
2233 | {0, 16, false, 7}, /* for WL-CPT */ | |
2234 | {4, 0, true, 1}, | |
2235 | {3, 6, true, 1}, | |
2236 | {2, 9, true, 1}, | |
2237 | {1, 13, true, 1} | |
2238 | }; | |
2239 | ||
2240 | static const struct coex_rf_para rf_para_rx_8822b[] = { | |
2241 | {0, 0, false, 7}, /* for normal */ | |
2242 | {0, 16, false, 7}, /* for WL-CPT */ | |
2243 | {4, 0, true, 1}, | |
2244 | {3, 6, true, 1}, | |
2245 | {2, 9, true, 1}, | |
2246 | {1, 13, true, 1} | |
2247 | }; | |
2248 | ||
2249 | static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b)); | |
2250 | ||
c97ee3e0 TEH |
2251 | static const u8 |
2252 | rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { | |
2253 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2254 | 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, | |
2255 | 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, | |
2256 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2257 | 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, | |
2258 | 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, | |
2259 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2260 | 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, | |
2261 | 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, | |
2262 | }; | |
2263 | ||
2264 | static const u8 | |
2265 | rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { | |
2266 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2267 | 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, | |
2268 | 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, | |
2269 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2270 | 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, | |
2271 | 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, | |
2272 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2273 | 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, | |
2274 | 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, | |
2275 | }; | |
2276 | ||
2277 | static const u8 | |
2278 | rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { | |
2279 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2280 | 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, | |
2281 | 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, | |
2282 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2283 | 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, | |
2284 | 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, | |
2285 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2286 | 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, | |
2287 | 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, | |
2288 | }; | |
2289 | ||
2290 | static const u8 | |
2291 | rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { | |
2292 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2293 | 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, | |
2294 | 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, | |
2295 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2296 | 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, | |
2297 | 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, | |
2298 | { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, | |
2299 | 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, | |
2300 | 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, | |
2301 | }; | |
2302 | ||
2303 | static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { | |
2304 | 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, | |
2305 | 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, | |
2306 | 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 | |
2307 | }; | |
2308 | ||
2309 | static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { | |
2310 | 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, | |
2311 | 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, | |
2312 | 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 | |
2313 | }; | |
2314 | ||
2315 | static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { | |
2316 | 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, | |
2317 | 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, | |
2318 | 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 | |
2319 | }; | |
2320 | ||
2321 | static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { | |
2322 | 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, | |
2323 | 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, | |
2324 | 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 | |
2325 | }; | |
2326 | ||
2327 | static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { | |
2328 | 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, | |
2329 | 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, | |
2330 | 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 | |
2331 | }; | |
2332 | ||
2333 | static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { | |
2334 | 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, | |
2335 | 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, | |
2336 | 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 | |
2337 | }; | |
2338 | ||
2339 | static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { | |
2340 | 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, | |
2341 | 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, | |
2342 | 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 | |
2343 | }; | |
2344 | ||
2345 | static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { | |
2346 | 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, | |
2347 | 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, | |
2348 | 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 | |
2349 | }; | |
2350 | ||
2351 | static const struct rtw_pwr_track_tbl rtw8822b_rtw_pwr_track_tbl = { | |
2352 | .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], | |
2353 | .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], | |
2354 | .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], | |
2355 | .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], | |
2356 | .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], | |
2357 | .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], | |
2358 | .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], | |
2359 | .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], | |
2360 | .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], | |
2361 | .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], | |
2362 | .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], | |
2363 | .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], | |
2364 | .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n, | |
2365 | .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p, | |
2366 | .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n, | |
2367 | .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p, | |
2368 | .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n, | |
2369 | .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p, | |
2370 | .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n, | |
2371 | .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p, | |
2372 | }; | |
2373 | ||
e3037485 YHC |
2374 | struct rtw_chip_info rtw8822b_hw_spec = { |
2375 | .ops = &rtw8822b_ops, | |
2376 | .id = RTW_CHIP_TYPE_8822B, | |
2377 | .fw_name = "rtw88/rtw8822b_fw.bin", | |
2378 | .tx_pkt_desc_sz = 48, | |
2379 | .tx_buf_desc_sz = 16, | |
2380 | .rx_pkt_desc_sz = 24, | |
2381 | .rx_buf_desc_sz = 8, | |
2382 | .phy_efuse_size = 1024, | |
2383 | .log_efuse_size = 768, | |
2384 | .ptct_efuse_size = 96, | |
2385 | .txff_size = 262144, | |
2386 | .rxff_size = 24576, | |
2387 | .txgi_factor = 1, | |
2388 | .is_pwr_by_rate_dec = true, | |
2389 | .max_power_index = 0x3f, | |
2390 | .csi_buf_pg_num = 0, | |
2391 | .band = RTW_BAND_2G | RTW_BAND_5G, | |
2392 | .page_size = 128, | |
2393 | .dig_min = 0x1c, | |
2394 | .ht_supported = true, | |
2395 | .vht_supported = true, | |
d3be4d11 | 2396 | .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), |
e3037485 YHC |
2397 | .sys_func_en = 0xDC, |
2398 | .pwr_on_seq = card_enable_flow_8822b, | |
2399 | .pwr_off_seq = card_disable_flow_8822b, | |
2400 | .page_table = page_table_8822b, | |
2401 | .rqpn_table = rqpn_table_8822b, | |
2402 | .intf_table = &phy_para_table_8822b, | |
2403 | .dig = rtw8822b_dig, | |
2404 | .rf_base_addr = {0x2800, 0x2c00}, | |
2405 | .rf_sipi_addr = {0xc90, 0xe90}, | |
2406 | .mac_tbl = &rtw8822b_mac_tbl, | |
2407 | .agc_tbl = &rtw8822b_agc_tbl, | |
2408 | .bb_tbl = &rtw8822b_bb_tbl, | |
2409 | .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl}, | |
2410 | .rfe_defs = rtw8822b_rfe_defs, | |
2411 | .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs), | |
c97ee3e0 TEH |
2412 | .pwr_track_tbl = &rtw8822b_rtw_pwr_track_tbl, |
2413 | .iqk_threshold = 8, | |
0bd95573 TEH |
2414 | .bfer_su_max_num = 2, |
2415 | .bfer_mu_max_num = 1, | |
4136214f YHC |
2416 | |
2417 | .coex_para_ver = 0x19062706, | |
2418 | .bt_desired_ver = 0x6, | |
2419 | .scbd_support = true, | |
2420 | .new_scbd10_def = false, | |
2421 | .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, | |
2422 | .bt_rssi_type = COEX_BTRSSI_RATIO, | |
2423 | .ant_isolation = 15, | |
2424 | .rssi_tolerance = 2, | |
2425 | .wl_rssi_step = wl_rssi_step_8822b, | |
2426 | .bt_rssi_step = bt_rssi_step_8822b, | |
2427 | .table_sant_num = ARRAY_SIZE(table_sant_8822b), | |
2428 | .table_sant = table_sant_8822b, | |
2429 | .table_nsant_num = ARRAY_SIZE(table_nsant_8822b), | |
2430 | .table_nsant = table_nsant_8822b, | |
2431 | .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b), | |
2432 | .tdma_sant = tdma_sant_8822b, | |
2433 | .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b), | |
2434 | .tdma_nsant = tdma_nsant_8822b, | |
2435 | .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b), | |
2436 | .wl_rf_para_tx = rf_para_tx_8822b, | |
2437 | .wl_rf_para_rx = rf_para_rx_8822b, | |
2438 | .bt_afh_span_bw20 = 0x24, | |
2439 | .bt_afh_span_bw40 = 0x36, | |
2440 | .afh_5g_num = ARRAY_SIZE(afh_5g_8822b), | |
2441 | .afh_5g = afh_5g_8822b, | |
e3037485 YHC |
2442 | }; |
2443 | EXPORT_SYMBOL(rtw8822b_hw_spec); | |
2444 | ||
2445 | MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin"); |