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1 | /** |
2 | * Copyright (c) 2014 Redpine Signals Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef __RSI_MAIN_H__ | |
18 | #define __RSI_MAIN_H__ | |
19 | ||
20 | #include <linux/string.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <net/mac80211.h> | |
23 | ||
24 | #define ERR_ZONE BIT(0) /* For Error Msgs */ | |
25 | #define INFO_ZONE BIT(1) /* For General Status Msgs */ | |
26 | #define INIT_ZONE BIT(2) /* For Driver Init Seq Msgs */ | |
27 | #define MGMT_TX_ZONE BIT(3) /* For TX Mgmt Path Msgs */ | |
28 | #define MGMT_RX_ZONE BIT(4) /* For RX Mgmt Path Msgs */ | |
29 | #define DATA_TX_ZONE BIT(5) /* For TX Data Path Msgs */ | |
30 | #define DATA_RX_ZONE BIT(6) /* For RX Data Path Msgs */ | |
31 | #define FSM_ZONE BIT(7) /* For State Machine Msgs */ | |
32 | #define ISR_ZONE BIT(8) /* For Interrupt Msgs */ | |
33 | ||
34 | #define FSM_CARD_NOT_READY 0 | |
35 | #define FSM_BOOT_PARAMS_SENT 1 | |
36 | #define FSM_EEPROM_READ_MAC_ADDR 2 | |
37 | #define FSM_RESET_MAC_SENT 3 | |
38 | #define FSM_RADIO_CAPS_SENT 4 | |
39 | #define FSM_BB_RF_PROG_SENT 5 | |
40 | #define FSM_MAC_INIT_DONE 6 | |
41 | ||
42 | extern u32 rsi_zone_enabled; | |
5fe1b76a | 43 | extern __printf(2, 3) void rsi_dbg(u32 zone, const char *fmt, ...); |
dad0d04f FF |
44 | |
45 | #define RSI_MAX_VIFS 1 | |
46 | #define NUM_EDCA_QUEUES 4 | |
47 | #define IEEE80211_ADDR_LEN 6 | |
48 | #define FRAME_DESC_SZ 16 | |
49 | #define MIN_802_11_HDR_LEN 24 | |
50 | ||
51 | #define DATA_QUEUE_WATER_MARK 400 | |
52 | #define MIN_DATA_QUEUE_WATER_MARK 300 | |
53 | #define MULTICAST_WATER_MARK 200 | |
54 | #define MAC_80211_HDR_FRAME_CONTROL 0 | |
55 | #define WME_NUM_AC 4 | |
56 | #define NUM_SOFT_QUEUES 5 | |
57 | #define MAX_HW_QUEUES 8 | |
58 | #define INVALID_QUEUE 0xff | |
59 | #define MAX_CONTINUOUS_VO_PKTS 8 | |
60 | #define MAX_CONTINUOUS_VI_PKTS 4 | |
61 | ||
62 | /* Queue information */ | |
63 | #define RSI_WIFI_MGMT_Q 0x4 | |
64 | #define RSI_WIFI_DATA_Q 0x5 | |
65 | #define IEEE80211_MGMT_FRAME 0x00 | |
66 | #define IEEE80211_CTL_FRAME 0x04 | |
67 | ||
68 | #define IEEE80211_QOS_TID 0x0f | |
69 | #define IEEE80211_NONQOS_TID 16 | |
70 | ||
71 | #define MAX_DEBUGFS_ENTRIES 4 | |
72 | ||
73 | #define TID_TO_WME_AC(_tid) ( \ | |
74 | ((_tid) == 0 || (_tid) == 3) ? BE_Q : \ | |
75 | ((_tid) < 3) ? BK_Q : \ | |
76 | ((_tid) < 6) ? VI_Q : \ | |
77 | VO_Q) | |
78 | ||
79 | #define WME_AC(_q) ( \ | |
80 | ((_q) == BK_Q) ? IEEE80211_AC_BK : \ | |
81 | ((_q) == BE_Q) ? IEEE80211_AC_BE : \ | |
82 | ((_q) == VI_Q) ? IEEE80211_AC_VI : \ | |
83 | IEEE80211_AC_VO) | |
84 | ||
85 | struct version_info { | |
86 | u16 major; | |
87 | u16 minor; | |
88 | u16 release_num; | |
89 | u16 patch_num; | |
90 | } __packed; | |
91 | ||
92 | struct skb_info { | |
93 | s8 rssi; | |
94 | u32 flags; | |
95 | u16 channel; | |
96 | s8 tid; | |
97 | s8 sta_id; | |
98 | }; | |
99 | ||
100 | enum edca_queue { | |
101 | BK_Q, | |
102 | BE_Q, | |
103 | VI_Q, | |
104 | VO_Q, | |
105 | MGMT_SOFT_Q | |
106 | }; | |
107 | ||
108 | struct security_info { | |
109 | bool security_enable; | |
110 | u32 ptk_cipher; | |
111 | u32 gtk_cipher; | |
112 | }; | |
113 | ||
114 | struct wmm_qinfo { | |
115 | s32 weight; | |
116 | s32 wme_params; | |
117 | s32 pkt_contended; | |
360accb0 | 118 | s32 txop; |
dad0d04f FF |
119 | }; |
120 | ||
121 | struct transmit_q_stats { | |
122 | u32 total_tx_pkt_send[NUM_EDCA_QUEUES + 1]; | |
123 | u32 total_tx_pkt_freed[NUM_EDCA_QUEUES + 1]; | |
124 | }; | |
125 | ||
126 | struct vif_priv { | |
127 | bool is_ht; | |
128 | bool sgi; | |
129 | u16 seq_start; | |
130 | }; | |
131 | ||
132 | struct rsi_event { | |
133 | atomic_t event_condition; | |
134 | wait_queue_head_t event_queue; | |
135 | }; | |
136 | ||
137 | struct rsi_thread { | |
138 | void (*thread_function)(void *); | |
139 | struct completion completion; | |
140 | struct task_struct *task; | |
141 | struct rsi_event event; | |
142 | atomic_t thread_done; | |
143 | }; | |
144 | ||
686a2541 JM |
145 | struct cqm_info { |
146 | s8 last_cqm_event_rssi; | |
147 | int rssi_thold; | |
148 | u32 rssi_hyst; | |
149 | }; | |
150 | ||
dad0d04f FF |
151 | struct rsi_hw; |
152 | ||
153 | struct rsi_common { | |
154 | struct rsi_hw *priv; | |
155 | struct vif_priv vif_info[RSI_MAX_VIFS]; | |
156 | ||
157 | bool mgmt_q_block; | |
158 | struct version_info driver_ver; | |
159 | struct version_info fw_ver; | |
160 | ||
161 | struct rsi_thread tx_thread; | |
162 | struct sk_buff_head tx_queue[NUM_EDCA_QUEUES + 1]; | |
163 | /* Mutex declaration */ | |
164 | struct mutex mutex; | |
165 | /* Mutex used between tx/rx threads */ | |
166 | struct mutex tx_rxlock; | |
167 | u8 endpoint; | |
168 | ||
169 | /* Channel/band related */ | |
170 | u8 band; | |
171 | u8 channel_width; | |
172 | ||
173 | u16 rts_threshold; | |
174 | u16 bitrate_mask[2]; | |
175 | u32 fixedrate_mask[2]; | |
176 | ||
177 | u8 rf_reset; | |
178 | struct transmit_q_stats tx_stats; | |
179 | struct security_info secinfo; | |
180 | struct wmm_qinfo tx_qinfo[NUM_EDCA_QUEUES]; | |
181 | struct ieee80211_tx_queue_params edca_params[NUM_EDCA_QUEUES]; | |
182 | u8 mac_addr[IEEE80211_ADDR_LEN]; | |
183 | ||
184 | /* state related */ | |
185 | u32 fsm_state; | |
186 | bool init_done; | |
187 | u8 bb_rf_prog_count; | |
188 | bool iface_down; | |
189 | ||
190 | /* Generic */ | |
191 | u8 channel; | |
192 | u8 *rx_data_pkt; | |
193 | u8 mac_id; | |
194 | u8 radio_id; | |
195 | u16 rate_pwr[20]; | |
196 | u16 min_rate; | |
197 | ||
198 | /* WMM algo related */ | |
199 | u8 selected_qnum; | |
200 | u32 pkt_cnt; | |
201 | u8 min_weight; | |
360accb0 | 202 | |
686a2541 JM |
203 | /* bgscan related */ |
204 | struct cqm_info cqm_info; | |
205 | ||
360accb0 | 206 | bool hw_data_qs_blocked; |
dad0d04f FF |
207 | }; |
208 | ||
209 | struct rsi_hw { | |
210 | struct rsi_common *priv; | |
211 | struct ieee80211_hw *hw; | |
212 | struct ieee80211_vif *vifs[RSI_MAX_VIFS]; | |
213 | struct ieee80211_tx_queue_params edca_params[NUM_EDCA_QUEUES]; | |
57fbcce3 | 214 | struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; |
dad0d04f FF |
215 | |
216 | struct device *device; | |
217 | u8 sc_nvifs; | |
218 | ||
219 | #ifdef CONFIG_RSI_DEBUGFS | |
220 | struct rsi_debugfs *dfsentry; | |
221 | u8 num_debugfs_entries; | |
222 | #endif | |
223 | void *rsi_dev; | |
224 | int (*host_intf_read_pkt)(struct rsi_hw *adapter, u8 *pkt, u32 len); | |
225 | int (*host_intf_write_pkt)(struct rsi_hw *adapter, u8 *pkt, u32 len); | |
226 | int (*check_hw_queue_status)(struct rsi_hw *adapter, u8 q_num); | |
227 | int (*rx_urb_submit)(struct rsi_hw *adapter); | |
228 | int (*determine_event_timeout)(struct rsi_hw *adapter); | |
229 | }; | |
230 | #endif |