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[PATCH] rt2x00: Use enum defines
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt2400pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt2400pci.h"
43
44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58{
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70}
71
72static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
74{
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2400pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96}
97
98static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
100{
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2400pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2400pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133}
134
135static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
137{
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163}
164
165static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166{
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178}
179
180static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181{
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193}
194
195#ifdef CONFIG_RT2X00_LIB_DEBUGFS
196#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
200{
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202}
203
204static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
206{
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208}
209
210static const struct rt2x00debug rt2400pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2400pci_read_csr,
214 .write = rt2400pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2400pci_bbp_read,
226 .write = rt2400pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2400pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236};
237#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239#ifdef CONFIG_RT2400PCI_RFKILL
240static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241{
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246}
81873e9c
ID		 247#else
248#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 249#endif /* CONFIG_RT2400PCI_RFKILL */
250
251/*
252 * Configuration handlers.
253 */
4abee4bb
ID		 254static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
255 __le32 *mac)
95ea3627 256{
4abee4bb
ID		 257 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
258 (2 * sizeof(__le32)));
95ea3627
ID		 259}
260
4abee4bb
ID		 261static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
262 __le32 *bssid)
95ea3627 263{
4abee4bb
ID		 264 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
265 (2 * sizeof(__le32)));
95ea3627
ID		 266}
267
feb24691
ID		 268static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
269 const int tsf_sync)
95ea3627
ID		 270{
271 u32 reg;
272
273 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
274
95ea3627
ID		 275 /*
276 * Enable beacon config
277 */
278 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
279 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
a137e202 280 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
95ea3627
ID		 281 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
282
283 /*
284 * Enable synchronisation.
285 */
286 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572
JB		 287 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
288 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627 289 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
feb24691 290 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
95ea3627
ID		 291 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
292}
293
5c58ee51
ID		 294static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
295 const int short_preamble,
296 const int ack_timeout,
297 const int ack_consume_time)
95ea3627 298{
5c58ee51 299 int preamble_mask;
95ea3627 300 u32 reg;
95ea3627 301
5c58ee51
ID		 302 /*
303 * When short preamble is enabled, we should set bit 0x08
304 */
305 preamble_mask = short_preamble << 3;
95ea3627
ID		 306
307 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 308 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
309 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 310 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
311
95ea3627 312 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 313 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 314 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
315 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
316 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
317
318 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 319 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 320 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
321 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
322 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
323
324 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 325 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 326 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
327 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
328 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
329
330 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 331 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 332 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
333 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
334 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
335}
336
337static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 338 const int basic_rate_mask)
95ea3627 339{
5c58ee51 340 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 341}
342
343static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 344 struct rf_channel *rf)
95ea3627 345{
95ea3627
ID		 346 /*
347 * Switch on tuning bits.
348 */
5c58ee51
ID		 349 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
350 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 351
5c58ee51
ID		 352 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
353 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
354 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 355
356 /*
357 * RF2420 chipset don't need any additional actions.
358 */
359 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
360 return;
361
362 /*
363 * For the RT2421 chipsets we need to write an invalid
364 * reference clock rate to activate auto_tune.
365 * After that we set the value back to the correct channel.
366 */
5c58ee51 367 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 368 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 369 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 370
371 msleep(1);
372
5c58ee51
ID		 373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 376
377 msleep(1);
378
379 /*
380 * Switch off tuning bits.
381 */
5c58ee51
ID		 382 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
383 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 384
5c58ee51
ID		 385 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 387
388 /*
389 * Clear false CRC during channel switch.
390 */
5c58ee51 391 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 392}
393
394static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
395{
396 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
397}
398
399static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
400 int antenna_tx, int antenna_rx)
401{
402 u8 r1;
403 u8 r4;
404
405 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
406 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
407
408 /*
409 * Configure the TX antenna.
410 */
411 switch (antenna_tx) {
412 case ANTENNA_SW_DIVERSITY:
413 case ANTENNA_HW_DIVERSITY:
414 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
415 break;
416 case ANTENNA_A:
417 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
418 break;
419 case ANTENNA_B:
420 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
421 break;
422 }
423
424 /*
425 * Configure the RX antenna.
426 */
427 switch (antenna_rx) {
428 case ANTENNA_SW_DIVERSITY:
429 case ANTENNA_HW_DIVERSITY:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
431 break;
432 case ANTENNA_A:
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
434 break;
435 case ANTENNA_B:
436 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
437 break;
438 }
439
440 rt2400pci_bbp_write(rt2x00dev, 4, r4);
441 rt2400pci_bbp_write(rt2x00dev, 1, r1);
442}
443
444static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 445 struct rt2x00lib_conf *libconf)
95ea3627
ID		 446{
447 u32 reg;
448
449 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 450 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 451 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
452
453 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 454 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
455 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 456 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
457
458 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 459 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
460 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 461 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
462
463 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
464 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
465 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
466 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
467
468 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 469 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
470 libconf->conf->beacon_int * 16);
471 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
472 libconf->conf->beacon_int * 16);
95ea3627
ID		 473 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
474}
475
476static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
477 const unsigned int flags,
5c58ee51 478 struct rt2x00lib_conf *libconf)
95ea3627 479{
95ea3627 480 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 481 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 482 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 483 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 484 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 485 rt2400pci_config_txpower(rt2x00dev,
486 libconf->conf->power_level);
95ea3627 487 if (flags & CONFIG_UPDATE_ANTENNA)
5c58ee51
ID		 488 rt2400pci_config_antenna(rt2x00dev,
489 libconf->conf->antenna_sel_tx,
490 libconf->conf->antenna_sel_rx);
95ea3627 491 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 492 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 493}
494
495static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
496 struct ieee80211_tx_queue_params *params)
497{
498 u32 reg;
499
500 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
501 rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
502 rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
503 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
504}
505
506/*
507 * LED functions.
508 */
509static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
510{
511 u32 reg;
512
513 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
514
515 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
516 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
517
518 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
519 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
520 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
521 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
522 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
523 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
524 } else {
525 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
526 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
527 }
528
529 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
530}
531
532static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
533{
534 u32 reg;
535
536 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
537 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
538 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
539 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
540}
541
542/*
543 * Link tuning
544 */
ebcf26da
ID		 545static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
546 struct link_qual *qual)
95ea3627
ID		 547{
548 u32 reg;
549 u8 bbp;
550
551 /*
552 * Update FCS error count from register.
553 */
554 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 555 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 556
557 /*
558 * Update False CCA count from register.
559 */
560 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 561 qual->false_cca = bbp;
95ea3627
ID		 562}
563
564static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
565{
566 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
567 rt2x00dev->link.vgc_level = 0x08;
568}
569
570static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
571{
572 u8 reg;
573
574 /*
575 * The link tuner should not run longer then 60 seconds,
576 * and should run once every 2 seconds.
577 */
578 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
579 return;
580
581 /*
582 * Base r13 link tuning on the false cca count.
583 */
584 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
585
ebcf26da 586 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 587 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
588 rt2x00dev->link.vgc_level = reg;
ebcf26da 589 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 590 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
591 rt2x00dev->link.vgc_level = reg;
592 }
593}
594
595/*
596 * Initialization functions.
597 */
598static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
599{
600 struct data_ring *ring = rt2x00dev->rx;
601 struct data_desc *rxd;
602 unsigned int i;
603 u32 word;
604
605 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
606
607 for (i = 0; i < ring->stats.limit; i++) {
608 rxd = ring->entry[i].priv;
609
610 rt2x00_desc_read(rxd, 2, &word);
611 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
612 ring->data_size);
613 rt2x00_desc_write(rxd, 2, word);
614
615 rt2x00_desc_read(rxd, 1, &word);
616 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
617 ring->entry[i].data_dma);
618 rt2x00_desc_write(rxd, 1, word);
619
620 rt2x00_desc_read(rxd, 0, &word);
621 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
622 rt2x00_desc_write(rxd, 0, word);
623 }
624
625 rt2x00_ring_index_clear(rt2x00dev->rx);
626}
627
628static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
629{
630 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
631 struct data_desc *txd;
632 unsigned int i;
633 u32 word;
634
635 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
636
637 for (i = 0; i < ring->stats.limit; i++) {
638 txd = ring->entry[i].priv;
639
640 rt2x00_desc_read(txd, 1, &word);
641 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
642 ring->entry[i].data_dma);
643 rt2x00_desc_write(txd, 1, word);
644
645 rt2x00_desc_read(txd, 2, &word);
646 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
647 ring->data_size);
648 rt2x00_desc_write(txd, 2, word);
649
650 rt2x00_desc_read(txd, 0, &word);
651 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
652 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
653 rt2x00_desc_write(txd, 0, word);
654 }
655
656 rt2x00_ring_index_clear(ring);
657}
658
659static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
660{
661 u32 reg;
662
663 /*
664 * Initialize rings.
665 */
666 rt2400pci_init_rxring(rt2x00dev);
667 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
668 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
669 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
670 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
671
672 /*
673 * Initialize registers.
674 */
675 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
676 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
677 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
678 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
679 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
680 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
681 rt2x00dev->bcn[1].stats.limit);
682 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
683 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
684 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
685
686 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
687 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
688 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
689 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
690
691 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
692 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
693 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
694 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
695
696 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
697 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
698 rt2x00dev->bcn[1].data_dma);
699 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
700
701 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
702 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
703 rt2x00dev->bcn[0].data_dma);
704 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
705
706 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
707 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
708 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
709 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
710
711 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
712 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
713 rt2x00dev->rx->data_dma);
714 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
715
716 return 0;
717}
718
719static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
720{
721 u32 reg;
722
723 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
724 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
725 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
726 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
727
728 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
729 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
730 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
731 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
732 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
733
734 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
735 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
736 (rt2x00dev->rx->data_size / 128));
737 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
738
739 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
740
741 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
742 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
743 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
744 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
745 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
746 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
747
748 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
749 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
750 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
751 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
752 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
753 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
754 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
755 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
756
757 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
758
759 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
760 return -EBUSY;
761
762 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
763 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
764
765 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
766 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
767 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
768
769 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
770 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
771 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
772 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
773 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
774 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
775
776 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
777 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
778 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
779 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
780 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
781
782 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
783 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
784 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
785 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
786
787 /*
788 * We must clear the FCS and FIFO error count.
789 * These registers are cleared on read,
790 * so we may pass a useless variable to store the value.
791 */
792 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
793 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
794
795 return 0;
796}
797
798static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
799{
800 unsigned int i;
801 u16 eeprom;
802 u8 reg_id;
803 u8 value;
804
805 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
806 rt2400pci_bbp_read(rt2x00dev, 0, &value);
807 if ((value != 0xff) && (value != 0x00))
808 goto continue_csr_init;
809 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
810 udelay(REGISTER_BUSY_DELAY);
811 }
812
813 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
814 return -EACCES;
815
816continue_csr_init:
817 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
818 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
819 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
820 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
821 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
822 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
823 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
824 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
825 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
826 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
827 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
828 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
829 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
830 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
831
832 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
833 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
834 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
835
836 if (eeprom != 0xffff && eeprom != 0x0000) {
837 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
838 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
839 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
840 reg_id, value);
841 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
842 }
843 }
844 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
845
846 return 0;
847}
848
849/*
850 * Device state switch handlers.
851 */
852static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
853 enum dev_state state)
854{
855 u32 reg;
856
857 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
858 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
859 state == STATE_RADIO_RX_OFF);
860 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
861}
862
863static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
864 enum dev_state state)
865{
866 int mask = (state == STATE_RADIO_IRQ_OFF);
867 u32 reg;
868
869 /*
870 * When interrupts are being enabled, the interrupt registers
871 * should clear the register to assure a clean state.
872 */
873 if (state == STATE_RADIO_IRQ_ON) {
874 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
875 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
876 }
877
878 /*
879 * Only toggle the interrupts bits we are going to use.
880 * Non-checked interrupt bits are disabled by default.
881 */
882 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
883 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
884 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
885 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
886 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
887 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
888 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
889}
890
891static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
892{
893 /*
894 * Initialize all registers.
895 */
896 if (rt2400pci_init_rings(rt2x00dev) ||
897 rt2400pci_init_registers(rt2x00dev) ||
898 rt2400pci_init_bbp(rt2x00dev)) {
899 ERROR(rt2x00dev, "Register initialization failed.\n");
900 return -EIO;
901 }
902
903 /*
904 * Enable interrupts.
905 */
906 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
907
908 /*
909 * Enable LED
910 */
911 rt2400pci_enable_led(rt2x00dev);
912
913 return 0;
914}
915
916static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
917{
918 u32 reg;
919
920 /*
921 * Disable LED
922 */
923 rt2400pci_disable_led(rt2x00dev);
924
925 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
926
927 /*
928 * Disable synchronisation.
929 */
930 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
931
932 /*
933 * Cancel RX and TX.
934 */
935 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
936 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
937 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
938
939 /*
940 * Disable interrupts.
941 */
942 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
943}
944
945static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
946 enum dev_state state)
947{
948 u32 reg;
949 unsigned int i;
950 char put_to_sleep;
951 char bbp_state;
952 char rf_state;
953
954 put_to_sleep = (state != STATE_AWAKE);
955
956 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
957 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
958 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
959 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
960 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
961 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
962
963 /*
964 * Device is not guaranteed to be in the requested state yet.
965 * We must wait until the register indicates that the
966 * device has entered the correct state.
967 */
968 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
969 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
970 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
971 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
972 if (bbp_state == state && rf_state == state)
973 return 0;
974 msleep(10);
975 }
976
977 NOTICE(rt2x00dev, "Device failed to enter state %d, "
978 "current device state: bbp %d and rf %d.\n",
979 state, bbp_state, rf_state);
980
981 return -EBUSY;
982}
983
984static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
985 enum dev_state state)
986{
987 int retval = 0;
988
989 switch (state) {
990 case STATE_RADIO_ON:
991 retval = rt2400pci_enable_radio(rt2x00dev);
992 break;
993 case STATE_RADIO_OFF:
994 rt2400pci_disable_radio(rt2x00dev);
995 break;
996 case STATE_RADIO_RX_ON:
997 case STATE_RADIO_RX_OFF:
998 rt2400pci_toggle_rx(rt2x00dev, state);
999 break;
1000 case STATE_DEEP_SLEEP:
1001 case STATE_SLEEP:
1002 case STATE_STANDBY:
1003 case STATE_AWAKE:
1004 retval = rt2400pci_set_state(rt2x00dev, state);
1005 break;
1006 default:
1007 retval = -ENOTSUPP;
1008 break;
1009 }
1010
1011 return retval;
1012}
1013
1014/*
1015 * TX descriptor initialization
1016 */
1017static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1018 struct data_desc *txd,
4150c572 1019 struct txdata_entry_desc *desc,
95ea3627
ID		 1020 struct ieee80211_hdr *ieee80211hdr,
1021 unsigned int length,
1022 struct ieee80211_tx_control *control)
1023{
1024 u32 word;
1025 u32 signal = 0;
1026 u32 service = 0;
1027 u32 length_high = 0;
1028 u32 length_low = 0;
1029
1030 /*
1031 * The PLCP values should be treated as if they
1032 * were BBP values.
1033 */
1034 rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1035 rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1036 rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1037
1038 rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1039 rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1040 rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1041
1042 rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1043 rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1044 rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1045
1046 rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1047 rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1048 rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1049
1050 /*
1051 * Start writing the descriptor words.
1052 */
1053 rt2x00_desc_read(txd, 2, &word);
1054 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1055 rt2x00_desc_write(txd, 2, word);
1056
1057 rt2x00_desc_read(txd, 3, &word);
1058 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1059 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1060 rt2x00_desc_write(txd, 3, word);
1061
1062 rt2x00_desc_read(txd, 4, &word);
1063 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1064 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1065 rt2x00_desc_write(txd, 4, word);
1066
1067 rt2x00_desc_read(txd, 0, &word);
1068 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1069 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1070 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1071 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1072 rt2x00_set_field32(&word, TXD_W0_ACK,
1073 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1074 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1075 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1076 rt2x00_set_field32(&word, TXD_W0_RTS,
1077 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1078 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1079 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1080 !!(control->flags &
1081 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1082 rt2x00_desc_write(txd, 0, word);
1083}
1084
1085/*
1086 * TX data initialization
1087 */
1088static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1089 unsigned int queue)
1090{
1091 u32 reg;
1092
1093 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1094 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1095 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1096 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1097 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1098 }
1099 return;
1100 }
1101
1102 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1103 if (queue == IEEE80211_TX_QUEUE_DATA0)
1104 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1105 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1106 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1107 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1108 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1109 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1110}
1111
1112/*
1113 * RX control handlers
1114 */
4150c572
JB		 1115static void rt2400pci_fill_rxdone(struct data_entry *entry,
1116 struct rxdata_entry_desc *desc)
95ea3627
ID		 1117{
1118 struct data_desc *rxd = entry->priv;
1119 u32 word0;
1120 u32 word2;
1121
1122 rt2x00_desc_read(rxd, 0, &word0);
1123 rt2x00_desc_read(rxd, 2, &word2);
1124
4150c572
JB		 1125 desc->flags = 0;
1126 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1127 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1128 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1129 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1130
1131 /*
1132 * Obtain the status about this packet.
1133 */
4150c572
JB		 1134 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1135 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
95ea3627 1136 entry->ring->rt2x00dev->rssi_offset;
4150c572
JB		 1137 desc->ofdm = 0;
1138 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1139}
1140
1141/*
1142 * Interrupt functions.
1143 */
1144static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1145{
1146 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1147 struct data_entry *entry;
1148 struct data_desc *txd;
1149 u32 word;
1150 int tx_status;
1151 int retry;
1152
1153 while (!rt2x00_ring_empty(ring)) {
1154 entry = rt2x00_get_data_entry_done(ring);
1155 txd = entry->priv;
1156 rt2x00_desc_read(txd, 0, &word);
1157
1158 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1159 !rt2x00_get_field32(word, TXD_W0_VALID))
1160 break;
1161
1162 /*
1163 * Obtain the status about this packet.
1164 */
1165 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1166 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1167
1168 rt2x00lib_txdone(entry, tx_status, retry);
1169
1170 /*
1171 * Make this entry available for reuse.
1172 */
1173 entry->flags = 0;
1174 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1175 rt2x00_desc_write(txd, 0, word);
1176 rt2x00_ring_index_done_inc(ring);
1177 }
1178
1179 /*
1180 * If the data ring was full before the txdone handler
1181 * we must make sure the packet queue in the mac80211 stack
1182 * is reenabled when the txdone handler has finished.
1183 */
1184 entry = ring->entry;
1185 if (!rt2x00_ring_full(ring))
1186 ieee80211_wake_queue(rt2x00dev->hw,
1187 entry->tx_status.control.queue);
1188}
1189
1190static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1191{
1192 struct rt2x00_dev *rt2x00dev = dev_instance;
1193 u32 reg;
1194
1195 /*
1196 * Get the interrupt sources & saved to local variable.
1197 * Write register value back to clear pending interrupts.
1198 */
1199 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1200 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1201
1202 if (!reg)
1203 return IRQ_NONE;
1204
1205 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1206 return IRQ_HANDLED;
1207
1208 /*
1209 * Handle interrupts, walk through all bits
1210 * and run the tasks, the bits are checked in order of
1211 * priority.
1212 */
1213
1214 /*
1215 * 1 - Beacon timer expired interrupt.
1216 */
1217 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1218 rt2x00lib_beacondone(rt2x00dev);
1219
1220 /*
1221 * 2 - Rx ring done interrupt.
1222 */
1223 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1224 rt2x00pci_rxdone(rt2x00dev);
1225
1226 /*
1227 * 3 - Atim ring transmit done interrupt.
1228 */
1229 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1230 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1231
1232 /*
1233 * 4 - Priority ring transmit done interrupt.
1234 */
1235 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1236 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1237
1238 /*
1239 * 5 - Tx ring transmit done interrupt.
1240 */
1241 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1242 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1243
1244 return IRQ_HANDLED;
1245}
1246
1247/*
1248 * Device probe functions.
1249 */
1250static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1251{
1252 struct eeprom_93cx6 eeprom;
1253 u32 reg;
1254 u16 word;
1255 u8 *mac;
1256
1257 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1258
1259 eeprom.data = rt2x00dev;
1260 eeprom.register_read = rt2400pci_eepromregister_read;
1261 eeprom.register_write = rt2400pci_eepromregister_write;
1262 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1263 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1264 eeprom.reg_data_in = 0;
1265 eeprom.reg_data_out = 0;
1266 eeprom.reg_data_clock = 0;
1267 eeprom.reg_chip_select = 0;
1268
1269 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1270 EEPROM_SIZE / sizeof(u16));
1271
1272 /*
1273 * Start validation of the data that has been read.
1274 */
1275 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1276 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1277 DECLARE_MAC_BUF(macbuf);
1278
95ea3627 1279 random_ether_addr(mac);
0795af57 1280 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1281 }
1282
1283 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1284 if (word == 0xffff) {
1285 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1286 return -EINVAL;
1287 }
1288
1289 return 0;
1290}
1291
1292static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1293{
1294 u32 reg;
1295 u16 value;
1296 u16 eeprom;
1297
1298 /*
1299 * Read EEPROM word for configuration.
1300 */
1301 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1302
1303 /*
1304 * Identify RF chipset.
1305 */
1306 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1307 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1308 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1309
1310 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1311 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1312 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1313 return -ENODEV;
1314 }
1315
1316 /*
1317 * Identify default antenna configuration.
1318 */
1319 rt2x00dev->hw->conf.antenna_sel_tx =
1320 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1321 rt2x00dev->hw->conf.antenna_sel_rx =
1322 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1323
1324 /*
1325 * Store led mode, for correct led behaviour.
1326 */
1327 rt2x00dev->led_mode =
1328 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1329
1330 /*
1331 * Detect if this device has an hardware controlled radio.
1332 */
81873e9c 1333#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1334 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1335 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1336#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1337
1338 /*
1339 * Check if the BBP tuning should be enabled.
1340 */
1341 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1342 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1343
1344 return 0;
1345}
1346
1347/*
1348 * RF value list for RF2420 & RF2421
1349 * Supports: 2.4 GHz
1350 */
1351static const struct rf_channel rf_vals_bg[] = {
1352 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1353 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1354 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1355 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1356 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1357 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1358 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1359 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1360 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1361 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1362 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1363 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1364 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1365 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1366};
1367
1368static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1369{
1370 struct hw_mode_spec *spec = &rt2x00dev->spec;
1371 u8 *txpower;
1372 unsigned int i;
1373
1374 /*
1375 * Initialize all hw fields.
1376 */
4150c572 1377 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1378 rt2x00dev->hw->extra_tx_headroom = 0;
1379 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1380 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1381 rt2x00dev->hw->queues = 2;
1382
1383 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1384 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1385 rt2x00_eeprom_addr(rt2x00dev,
1386 EEPROM_MAC_ADDR_0));
1387
1388 /*
1389 * Convert tx_power array in eeprom.
1390 */
1391 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1392 for (i = 0; i < 14; i++)
1393 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1394
1395 /*
1396 * Initialize hw_mode information.
1397 */
1398 spec->num_modes = 1;
1399 spec->num_rates = 4;
1400 spec->tx_power_a = NULL;
1401 spec->tx_power_bg = txpower;
1402 spec->tx_power_default = DEFAULT_TXPOWER;
1403
1404 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1405 spec->channels = rf_vals_bg;
1406}
1407
1408static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1409{
1410 int retval;
1411
1412 /*
1413 * Allocate eeprom data.
1414 */
1415 retval = rt2400pci_validate_eeprom(rt2x00dev);
1416 if (retval)
1417 return retval;
1418
1419 retval = rt2400pci_init_eeprom(rt2x00dev);
1420 if (retval)
1421 return retval;
1422
1423 /*
1424 * Initialize hw specifications.
1425 */
1426 rt2400pci_probe_hw_mode(rt2x00dev);
1427
1428 /*
1429 * This device requires the beacon ring
1430 */
066cb637 1431 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
95ea3627
ID		 1432
1433 /*
1434 * Set the rssi offset.
1435 */
1436 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1437
1438 return 0;
1439}
1440
1441/*
1442 * IEEE80211 stack callback functions.
1443 */
4150c572
JB		 1444static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1445 unsigned int changed_flags,
1446 unsigned int *total_flags,
1447 int mc_count,
1448 struct dev_addr_list *mc_list)
1449{
1450 struct rt2x00_dev *rt2x00dev = hw->priv;
1451 struct interface *intf = &rt2x00dev->interface;
1452 u32 reg;
1453
1454 /*
1455 * Mask off any flags we are going to ignore from
1456 * the total_flags field.
1457 */
1458 *total_flags &=
1459 FIF_ALLMULTI |
1460 FIF_FCSFAIL |
1461 FIF_PLCPFAIL |
1462 FIF_CONTROL |
1463 FIF_OTHER_BSS |
1464 FIF_PROMISC_IN_BSS;
1465
1466 /*
1467 * Apply some rules to the filters:
1468 * - Some filters imply different filters to be set.
1469 * - Some things we can't filter out at all.
1470 * - Some filters are set based on interface type.
1471 */
1472 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1473 if (*total_flags & FIF_OTHER_BSS ||
1474 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1475 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1476 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1477 *total_flags |= FIF_PROMISC_IN_BSS;
1478
1479 /*
1480 * Check if there is any work left for us.
1481 */
1482 if (intf->filter == *total_flags)
1483 return;
1484 intf->filter = *total_flags;
1485
1486 /*
1487 * Start configuration steps.
1488 * Note that the version error will always be dropped
1489 * since there is no filter for it at this time.
1490 */
1491 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1492 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1493 !(*total_flags & FIF_FCSFAIL));
1494 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1495 !(*total_flags & FIF_PLCPFAIL));
1496 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1497 !(*total_flags & FIF_CONTROL));
1498 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1499 !(*total_flags & FIF_PROMISC_IN_BSS));
1500 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1501 !(*total_flags & FIF_PROMISC_IN_BSS));
1502 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1503 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1504}
1505
95ea3627
ID		 1506static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1507 u32 short_retry, u32 long_retry)
1508{
1509 struct rt2x00_dev *rt2x00dev = hw->priv;
1510 u32 reg;
1511
1512 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1513 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1514 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1515 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1516
1517 return 0;
1518}
1519
1520static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1521 int queue,
1522 const struct ieee80211_tx_queue_params *params)
1523{
1524 struct rt2x00_dev *rt2x00dev = hw->priv;
1525
1526 /*
1527 * We don't support variating cw_min and cw_max variables
1528 * per queue. So by default we only configure the TX queue,
1529 * and ignore all other configurations.
1530 */
1531 if (queue != IEEE80211_TX_QUEUE_DATA0)
1532 return -EINVAL;
1533
1534 if (rt2x00mac_conf_tx(hw, queue, params))
1535 return -EINVAL;
1536
1537 /*
1538 * Write configuration to register.
1539 */
1540 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1541
1542 return 0;
1543}
1544
1545static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1546{
1547 struct rt2x00_dev *rt2x00dev = hw->priv;
1548 u64 tsf;
1549 u32 reg;
1550
1551 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1552 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1553 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1554 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1555
1556 return tsf;
1557}
1558
1559static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1560{
1561 struct rt2x00_dev *rt2x00dev = hw->priv;
1562
1563 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1564 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1565}
1566
1567static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1568{
1569 struct rt2x00_dev *rt2x00dev = hw->priv;
1570 u32 reg;
1571
1572 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1573 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1574}
1575
1576static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1577 .tx = rt2x00mac_tx,
4150c572
JB		 1578 .start = rt2x00mac_start,
1579 .stop = rt2x00mac_stop,
95ea3627
ID		 1580 .add_interface = rt2x00mac_add_interface,
1581 .remove_interface = rt2x00mac_remove_interface,
1582 .config = rt2x00mac_config,
1583 .config_interface = rt2x00mac_config_interface,
4150c572 1584 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1585 .get_stats = rt2x00mac_get_stats,
1586 .set_retry_limit = rt2400pci_set_retry_limit,
5c58ee51 1587 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 1588 .conf_tx = rt2400pci_conf_tx,
1589 .get_tx_stats = rt2x00mac_get_tx_stats,
1590 .get_tsf = rt2400pci_get_tsf,
1591 .reset_tsf = rt2400pci_reset_tsf,
1592 .beacon_update = rt2x00pci_beacon_update,
1593 .tx_last_beacon = rt2400pci_tx_last_beacon,
1594};
1595
1596static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1597 .irq_handler = rt2400pci_interrupt,
1598 .probe_hw = rt2400pci_probe_hw,
1599 .initialize = rt2x00pci_initialize,
1600 .uninitialize = rt2x00pci_uninitialize,
1601 .set_device_state = rt2400pci_set_device_state,
95ea3627 1602 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1603 .link_stats = rt2400pci_link_stats,
1604 .reset_tuner = rt2400pci_reset_tuner,
1605 .link_tuner = rt2400pci_link_tuner,
1606 .write_tx_desc = rt2400pci_write_tx_desc,
1607 .write_tx_data = rt2x00pci_write_tx_data,
1608 .kick_tx_queue = rt2400pci_kick_tx_queue,
1609 .fill_rxdone = rt2400pci_fill_rxdone,
1610 .config_mac_addr = rt2400pci_config_mac_addr,
1611 .config_bssid = rt2400pci_config_bssid,
95ea3627 1612 .config_type = rt2400pci_config_type,
5c58ee51 1613 .config_preamble = rt2400pci_config_preamble,
95ea3627
ID		 1614 .config = rt2400pci_config,
1615};
1616
1617static const struct rt2x00_ops rt2400pci_ops = {
1618 .name = DRV_NAME,
1619 .rxd_size = RXD_DESC_SIZE,
1620 .txd_size = TXD_DESC_SIZE,
1621 .eeprom_size = EEPROM_SIZE,
1622 .rf_size = RF_SIZE,
1623 .lib = &rt2400pci_rt2x00_ops,
1624 .hw = &rt2400pci_mac80211_ops,
1625#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1626 .debugfs = &rt2400pci_rt2x00debug,
1627#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1628};
1629
1630/*
1631 * RT2400pci module information.
1632 */
1633static struct pci_device_id rt2400pci_device_table[] = {
1634 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1635 { 0, }
1636};
1637
1638MODULE_AUTHOR(DRV_PROJECT);
1639MODULE_VERSION(DRV_VERSION);
1640MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1641MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1642MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1643MODULE_LICENSE("GPL");
1644
1645static struct pci_driver rt2400pci_driver = {
1646 .name = DRV_NAME,
1647 .id_table = rt2400pci_device_table,
1648 .probe = rt2x00pci_probe,
1649 .remove = __devexit_p(rt2x00pci_remove),
1650 .suspend = rt2x00pci_suspend,
1651 .resume = rt2x00pci_resume,
1652};
1653
1654static int __init rt2400pci_init(void)
1655{
1656 return pci_register_driver(&rt2400pci_driver);
1657}
1658
1659static void __exit rt2400pci_exit(void)
1660{
1661 pci_unregister_driver(&rt2400pci_driver);
1662}
1663
1664module_init(rt2400pci_init);
1665module_exit(rt2400pci_exit);
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