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rt2x00: Make rt2x00leds_register return void
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
a9450b70
ID		 246#ifdef CONFIG_RT2400PCI_LEDS
247static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2400pci_led_brightness NULL
268#endif /* CONFIG_RT2400PCI_LEDS */
269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
6bb40dd1
ID		 273static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
95ea3627 277{
6bb40dd1
ID		 278 unsigned int bcn_preload;
279 u32 reg;
95ea3627 280
6bb40dd1 281 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 282 /*
283 * Enable beacon config
284 */
285 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
286 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
287 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
288 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 289
6bb40dd1
ID		 290 /*
291 * Enable synchronisation.
292 */
293 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
6bb40dd1
ID		 294 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
295 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
296 }
95ea3627 297
6bb40dd1
ID		 298 if (flags & CONFIG_UPDATE_MAC)
299 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
300 conf->mac, sizeof(conf->mac));
95ea3627 301
6bb40dd1
ID		 302 if (flags & CONFIG_UPDATE_BSSID)
303 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
304 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 305}
306
72810379
ID		 307static int rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
308 struct rt2x00lib_erp *erp)
95ea3627 309{
5c58ee51 310 int preamble_mask;
95ea3627 311 u32 reg;
95ea3627 312
5c58ee51
ID		 313 /*
314 * When short preamble is enabled, we should set bit 0x08
315 */
72810379 316 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 317
318 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 319 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
320 erp->ack_timeout);
321 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
322 erp->ack_consume_time);
95ea3627
ID		 323 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
324
95ea3627 325 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 326 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 327 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
328 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
329 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
330
331 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 332 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 333 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
334 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
335 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
336
337 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 338 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 339 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
340 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
341 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
342
343 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 344 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 345 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
346 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
347 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
6bb40dd1
ID		 348
349 return 0;
95ea3627
ID		 350}
351
352static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 353 const int basic_rate_mask)
95ea3627 354{
5c58ee51 355 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 356}
357
358static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 359 struct rf_channel *rf)
95ea3627 360{
95ea3627
ID		 361 /*
362 * Switch on tuning bits.
363 */
5c58ee51
ID		 364 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
365 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 366
5c58ee51
ID		 367 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
368 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
369 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 370
371 /*
372 * RF2420 chipset don't need any additional actions.
373 */
374 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
375 return;
376
377 /*
378 * For the RT2421 chipsets we need to write an invalid
379 * reference clock rate to activate auto_tune.
380 * After that we set the value back to the correct channel.
381 */
5c58ee51 382 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 383 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 384 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 385
386 msleep(1);
387
5c58ee51
ID		 388 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
389 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
390 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 391
392 msleep(1);
393
394 /*
395 * Switch off tuning bits.
396 */
5c58ee51
ID		 397 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
398 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 399
5c58ee51
ID		 400 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
401 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 402
403 /*
404 * Clear false CRC during channel switch.
405 */
5c58ee51 406 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 407}
408
409static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
410{
411 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
412}
413
414static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 415 struct antenna_setup *ant)
95ea3627
ID		 416{
417 u8 r1;
418 u8 r4;
419
a4fe07d9
ID		 420 /*
421 * We should never come here because rt2x00lib is supposed
422 * to catch this and send us the correct antenna explicitely.
423 */
424 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
425 ant->tx == ANTENNA_SW_DIVERSITY);
426
95ea3627
ID		 427 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
428 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
429
430 /*
431 * Configure the TX antenna.
432 */
addc81bd 433 switch (ant->tx) {
95ea3627
ID		 434 case ANTENNA_HW_DIVERSITY:
435 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
436 break;
437 case ANTENNA_A:
438 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
439 break;
440 case ANTENNA_B:
a4fe07d9 441 default:
95ea3627
ID		 442 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
443 break;
444 }
445
446 /*
447 * Configure the RX antenna.
448 */
addc81bd 449 switch (ant->rx) {
95ea3627
ID		 450 case ANTENNA_HW_DIVERSITY:
451 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
452 break;
453 case ANTENNA_A:
454 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
455 break;
456 case ANTENNA_B:
a4fe07d9 457 default:
95ea3627
ID		 458 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
459 break;
460 }
461
462 rt2400pci_bbp_write(rt2x00dev, 4, r4);
463 rt2400pci_bbp_write(rt2x00dev, 1, r1);
464}
465
466static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 467 struct rt2x00lib_conf *libconf)
95ea3627
ID		 468{
469 u32 reg;
470
471 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 472 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 473 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
474
475 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 476 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
477 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 478 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
479
480 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 481 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
482 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 483 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
484
485 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
486 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
487 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
488 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
489
490 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 491 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
492 libconf->conf->beacon_int * 16);
493 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
494 libconf->conf->beacon_int * 16);
95ea3627
ID		 495 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
496}
497
498static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 499 struct rt2x00lib_conf *libconf,
500 const unsigned int flags)
95ea3627 501{
95ea3627 502 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 503 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 504 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 505 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 506 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 507 rt2400pci_config_txpower(rt2x00dev,
508 libconf->conf->power_level);
95ea3627 509 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 510 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 511 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 512 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 513}
514
515static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 516 const int cw_min, const int cw_max)
95ea3627
ID		 517{
518 u32 reg;
519
520 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 521 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
522 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 523 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
524}
525
95ea3627
ID		 526/*
527 * Link tuning
528 */
ebcf26da
ID		 529static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
530 struct link_qual *qual)
95ea3627
ID		 531{
532 u32 reg;
533 u8 bbp;
534
535 /*
536 * Update FCS error count from register.
537 */
538 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 539 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 540
541 /*
542 * Update False CCA count from register.
543 */
544 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 545 qual->false_cca = bbp;
95ea3627
ID		 546}
547
548static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
549{
550 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
551 rt2x00dev->link.vgc_level = 0x08;
552}
553
554static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
555{
556 u8 reg;
557
558 /*
559 * The link tuner should not run longer then 60 seconds,
560 * and should run once every 2 seconds.
561 */
562 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
563 return;
564
565 /*
566 * Base r13 link tuning on the false cca count.
567 */
568 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
569
ebcf26da 570 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 571 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
572 rt2x00dev->link.vgc_level = reg;
ebcf26da 573 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 574 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
575 rt2x00dev->link.vgc_level = reg;
576 }
577}
578
579/*
580 * Initialization functions.
581 */
837e7f24 582static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 583 struct queue_entry *entry)
95ea3627 584{
181d6902 585 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 586 u32 word;
587
181d6902 588 rt2x00_desc_read(priv_rx->desc, 2, &word);
30b3a23c
ID		 589 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
590 entry->queue->data_size);
181d6902 591 rt2x00_desc_write(priv_rx->desc, 2, word);
95ea3627 592
181d6902 593 rt2x00_desc_read(priv_rx->desc, 1, &word);
30b3a23c 594 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
181d6902 595 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 596
181d6902 597 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 598 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 599 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 600}
601
837e7f24 602static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 603 struct queue_entry *entry)
95ea3627 604{
181d6902 605 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 606 u32 word;
607
181d6902 608 rt2x00_desc_read(priv_tx->desc, 1, &word);
30b3a23c 609 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
181d6902 610 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 611
181d6902
ID		 612 rt2x00_desc_read(priv_tx->desc, 2, &word);
613 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
614 entry->queue->data_size);
615 rt2x00_desc_write(priv_tx->desc, 2, word);
95ea3627 616
181d6902 617 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 618 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
619 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 620 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 621}
622
181d6902 623static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 624{
181d6902
ID		 625 struct queue_entry_priv_pci_rx *priv_rx;
626 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 627 u32 reg;
628
95ea3627
ID		 629 /*
630 * Initialize registers.
631 */
632 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 633 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
634 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
635 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
636 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 637 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
638
181d6902 639 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 640 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c
ID		 641 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
642 priv_tx->desc_dma);
95ea3627
ID		 643 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
644
181d6902 645 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 646 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c
ID		 647 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
648 priv_tx->desc_dma);
95ea3627
ID		 649 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
650
181d6902 651 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 652 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c
ID		 653 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
654 priv_tx->desc_dma);
95ea3627
ID		 655 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
656
181d6902 657 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 658 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c
ID		 659 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
660 priv_tx->desc_dma);
95ea3627
ID		 661 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
662
663 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
664 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 665 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 666 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
667
181d6902 668 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 669 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
30b3a23c 670 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
95ea3627
ID		 671 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
672
673 return 0;
674}
675
676static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
677{
678 u32 reg;
679
680 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
681 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
682 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
683 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
684
685 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
686 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
687 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
688 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
689 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
690
691 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
692 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
693 (rt2x00dev->rx->data_size / 128));
694 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
695
a9450b70
ID		 696 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
697 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
698 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
699 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
700
95ea3627
ID		 701 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
702
703 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
704 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
705 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
706 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
707 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
708 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
709
710 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
711 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
712 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
713 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
714 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
715 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
716 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
717 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
718
719 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
720
721 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
722 return -EBUSY;
723
724 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
725 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
726
727 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
728 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
729 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
730
731 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
732 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
733 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
734 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
735 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
736 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
737
738 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
739 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
740 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
741 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
742 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
743
744 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
745 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
746 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
747 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
748
749 /*
750 * We must clear the FCS and FIFO error count.
751 * These registers are cleared on read,
752 * so we may pass a useless variable to store the value.
753 */
754 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
755 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
756
757 return 0;
758}
759
760static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
761{
762 unsigned int i;
763 u16 eeprom;
764 u8 reg_id;
765 u8 value;
766
767 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
768 rt2400pci_bbp_read(rt2x00dev, 0, &value);
769 if ((value != 0xff) && (value != 0x00))
770 goto continue_csr_init;
771 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
772 udelay(REGISTER_BUSY_DELAY);
773 }
774
775 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
776 return -EACCES;
777
778continue_csr_init:
779 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
780 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
781 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
782 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
783 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
784 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
785 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
786 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
787 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
788 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
789 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
790 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
791 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
792 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
793
95ea3627
ID		 794 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
795 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
796
797 if (eeprom != 0xffff && eeprom != 0x0000) {
798 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
799 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 800 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
801 }
802 }
95ea3627
ID		 803
804 return 0;
805}
806
807/*
808 * Device state switch handlers.
809 */
810static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
811 enum dev_state state)
812{
813 u32 reg;
814
815 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
816 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
817 state == STATE_RADIO_RX_OFF);
818 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
819}
820
821static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
822 enum dev_state state)
823{
824 int mask = (state == STATE_RADIO_IRQ_OFF);
825 u32 reg;
826
827 /*
828 * When interrupts are being enabled, the interrupt registers
829 * should clear the register to assure a clean state.
830 */
831 if (state == STATE_RADIO_IRQ_ON) {
832 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
833 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
834 }
835
836 /*
837 * Only toggle the interrupts bits we are going to use.
838 * Non-checked interrupt bits are disabled by default.
839 */
840 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
841 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
842 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
843 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
844 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
845 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
846 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
847}
848
849static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
850{
851 /*
852 * Initialize all registers.
853 */
181d6902 854 if (rt2400pci_init_queues(rt2x00dev) ||
95ea3627
ID		 855 rt2400pci_init_registers(rt2x00dev) ||
856 rt2400pci_init_bbp(rt2x00dev)) {
857 ERROR(rt2x00dev, "Register initialization failed.\n");
858 return -EIO;
859 }
860
861 /*
862 * Enable interrupts.
863 */
864 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
865
95ea3627
ID		 866 return 0;
867}
868
869static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
870{
871 u32 reg;
872
95ea3627
ID		 873 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
874
875 /*
876 * Disable synchronisation.
877 */
878 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
879
880 /*
881 * Cancel RX and TX.
882 */
883 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
884 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
885 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
886
887 /*
888 * Disable interrupts.
889 */
890 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
891}
892
893static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
894 enum dev_state state)
895{
896 u32 reg;
897 unsigned int i;
898 char put_to_sleep;
899 char bbp_state;
900 char rf_state;
901
902 put_to_sleep = (state != STATE_AWAKE);
903
904 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
905 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
906 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
907 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
908 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
909 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
910
911 /*
912 * Device is not guaranteed to be in the requested state yet.
913 * We must wait until the register indicates that the
914 * device has entered the correct state.
915 */
916 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
917 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
918 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
919 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
920 if (bbp_state == state && rf_state == state)
921 return 0;
922 msleep(10);
923 }
924
925 NOTICE(rt2x00dev, "Device failed to enter state %d, "
926 "current device state: bbp %d and rf %d.\n",
927 state, bbp_state, rf_state);
928
929 return -EBUSY;
930}
931
932static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
933 enum dev_state state)
934{
935 int retval = 0;
936
937 switch (state) {
938 case STATE_RADIO_ON:
939 retval = rt2400pci_enable_radio(rt2x00dev);
940 break;
941 case STATE_RADIO_OFF:
942 rt2400pci_disable_radio(rt2x00dev);
943 break;
944 case STATE_RADIO_RX_ON:
61667d8d
ID		 945 case STATE_RADIO_RX_ON_LINK:
946 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
947 break;
95ea3627 948 case STATE_RADIO_RX_OFF:
61667d8d
ID		 949 case STATE_RADIO_RX_OFF_LINK:
950 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 951 break;
952 case STATE_DEEP_SLEEP:
953 case STATE_SLEEP:
954 case STATE_STANDBY:
955 case STATE_AWAKE:
956 retval = rt2400pci_set_state(rt2x00dev, state);
957 break;
958 default:
959 retval = -ENOTSUPP;
960 break;
961 }
962
963 return retval;
964}
965
966/*
967 * TX descriptor initialization
968 */
969static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 970 struct sk_buff *skb,
181d6902 971 struct txentry_desc *txdesc,
95ea3627
ID		 972 struct ieee80211_tx_control *control)
973{
181d6902 974 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 975 __le32 *txd = skbdesc->desc;
95ea3627 976 u32 word;
95ea3627
ID		 977
978 /*
979 * Start writing the descriptor words.
980 */
981 rt2x00_desc_read(txd, 2, &word);
dd3193e1 982 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 983 rt2x00_desc_write(txd, 2, word);
984
985 rt2x00_desc_read(txd, 3, &word);
181d6902 986 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 987 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
988 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 989 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 990 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
991 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 992 rt2x00_desc_write(txd, 3, word);
993
994 rt2x00_desc_read(txd, 4, &word);
181d6902 995 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 996 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
997 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 998 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 999 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1000 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1001 rt2x00_desc_write(txd, 4, word);
1002
1003 rt2x00_desc_read(txd, 0, &word);
1004 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1005 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1006 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1007 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1008 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1009 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1010 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1011 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1012 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1013 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1014 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1015 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1016 !!(control->flags &
1017 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1018 rt2x00_desc_write(txd, 0, word);
1019}
1020
1021/*
1022 * TX data initialization
1023 */
1024static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1025 const unsigned int queue)
95ea3627
ID		 1026{
1027 u32 reg;
1028
5957da4c 1029 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1030 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1031 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1032 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1033 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1034 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1035 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1036 }
1037 return;
1038 }
1039
1040 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1041 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1042 (queue == IEEE80211_TX_QUEUE_DATA0));
1043 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1044 (queue == IEEE80211_TX_QUEUE_DATA1));
1045 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1046 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1047 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1048}
1049
1050/*
1051 * RX control handlers
1052 */
181d6902
ID		 1053static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1054 struct rxdone_entry_desc *rxdesc)
95ea3627 1055{
181d6902 1056 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1057 u32 word0;
1058 u32 word2;
1059
181d6902
ID		 1060 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1061 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1062
181d6902 1063 rxdesc->flags = 0;
4150c572 1064 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1065 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1066 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1067 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1068
1069 /*
1070 * Obtain the status about this packet.
1071 */
181d6902
ID		 1072 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1073 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1074 entry->queue->rt2x00dev->rssi_offset;
1075 rxdesc->ofdm = 0;
1076 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1077 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1078}
1079
1080/*
1081 * Interrupt functions.
1082 */
181d6902
ID		 1083static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1084 const enum ieee80211_tx_queue queue_idx)
95ea3627 1085{
181d6902
ID		 1086 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1087 struct queue_entry_priv_pci_tx *priv_tx;
1088 struct queue_entry *entry;
1089 struct txdone_entry_desc txdesc;
95ea3627 1090 u32 word;
95ea3627 1091
181d6902
ID		 1092 while (!rt2x00queue_empty(queue)) {
1093 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1094 priv_tx = entry->priv_data;
1095 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1096
1097 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1098 !rt2x00_get_field32(word, TXD_W0_VALID))
1099 break;
1100
1101 /*
1102 * Obtain the status about this packet.
1103 */
181d6902
ID		 1104 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1105 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1106
181d6902 1107 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1108 }
95ea3627
ID		 1109}
1110
1111static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1112{
1113 struct rt2x00_dev *rt2x00dev = dev_instance;
1114 u32 reg;
1115
1116 /*
1117 * Get the interrupt sources & saved to local variable.
1118 * Write register value back to clear pending interrupts.
1119 */
1120 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1121 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1122
1123 if (!reg)
1124 return IRQ_NONE;
1125
1126 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1127 return IRQ_HANDLED;
1128
1129 /*
1130 * Handle interrupts, walk through all bits
1131 * and run the tasks, the bits are checked in order of
1132 * priority.
1133 */
1134
1135 /*
1136 * 1 - Beacon timer expired interrupt.
1137 */
1138 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1139 rt2x00lib_beacondone(rt2x00dev);
1140
1141 /*
1142 * 2 - Rx ring done interrupt.
1143 */
1144 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1145 rt2x00pci_rxdone(rt2x00dev);
1146
1147 /*
1148 * 3 - Atim ring transmit done interrupt.
1149 */
1150 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1151 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1152
1153 /*
1154 * 4 - Priority ring transmit done interrupt.
1155 */
1156 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1157 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1158
1159 /*
1160 * 5 - Tx ring transmit done interrupt.
1161 */
1162 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1163 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1164
1165 return IRQ_HANDLED;
1166}
1167
1168/*
1169 * Device probe functions.
1170 */
1171static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1172{
1173 struct eeprom_93cx6 eeprom;
1174 u32 reg;
1175 u16 word;
1176 u8 *mac;
1177
1178 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1179
1180 eeprom.data = rt2x00dev;
1181 eeprom.register_read = rt2400pci_eepromregister_read;
1182 eeprom.register_write = rt2400pci_eepromregister_write;
1183 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1184 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1185 eeprom.reg_data_in = 0;
1186 eeprom.reg_data_out = 0;
1187 eeprom.reg_data_clock = 0;
1188 eeprom.reg_chip_select = 0;
1189
1190 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1191 EEPROM_SIZE / sizeof(u16));
1192
1193 /*
1194 * Start validation of the data that has been read.
1195 */
1196 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1197 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1198 DECLARE_MAC_BUF(macbuf);
1199
95ea3627 1200 random_ether_addr(mac);
0795af57 1201 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1202 }
1203
1204 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1205 if (word == 0xffff) {
1206 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1207 return -EINVAL;
1208 }
1209
1210 return 0;
1211}
1212
1213static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1214{
1215 u32 reg;
1216 u16 value;
1217 u16 eeprom;
1218
1219 /*
1220 * Read EEPROM word for configuration.
1221 */
1222 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1223
1224 /*
1225 * Identify RF chipset.
1226 */
1227 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1228 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1229 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1230
1231 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1232 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1233 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1234 return -ENODEV;
1235 }
1236
1237 /*
1238 * Identify default antenna configuration.
1239 */
addc81bd 1240 rt2x00dev->default_ant.tx =
95ea3627 1241 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1242 rt2x00dev->default_ant.rx =
95ea3627
ID		 1243 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1244
addc81bd
ID		 1245 /*
1246 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1247 * I am not 100% sure about this, but the legacy drivers do not
1248 * indicate antenna swapping in software is required when
1249 * diversity is enabled.
1250 */
1251 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1252 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1253 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1254 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1255
95ea3627
ID		 1256 /*
1257 * Store led mode, for correct led behaviour.
1258 */
a9450b70
ID		 1259#ifdef CONFIG_RT2400PCI_LEDS
1260 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1261
1262 switch (value) {
1263 case LED_MODE_ASUS:
1264 case LED_MODE_ALPHA:
1265 case LED_MODE_DEFAULT:
1266 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1267 break;
1268 case LED_MODE_TXRX_ACTIVITY:
1269 rt2x00dev->led_flags =
1270 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1271 break;
1272 case LED_MODE_SIGNAL_STRENGTH:
1273 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1274 break;
1275 }
1276#endif /* CONFIG_RT2400PCI_LEDS */
95ea3627
ID		 1277
1278 /*
1279 * Detect if this device has an hardware controlled radio.
1280 */
81873e9c 1281#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1282 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1283 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1284#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1285
1286 /*
1287 * Check if the BBP tuning should be enabled.
1288 */
1289 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1290 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1291
1292 return 0;
1293}
1294
1295/*
1296 * RF value list for RF2420 & RF2421
1297 * Supports: 2.4 GHz
1298 */
1299static const struct rf_channel rf_vals_bg[] = {
1300 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1301 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1302 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1303 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1304 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1305 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1306 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1307 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1308 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1309 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1310 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1311 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1312 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1313 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1314};
1315
1316static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1317{
1318 struct hw_mode_spec *spec = &rt2x00dev->spec;
1319 u8 *txpower;
1320 unsigned int i;
1321
1322 /*
1323 * Initialize all hw fields.
1324 */
4150c572 1325 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1326 rt2x00dev->hw->extra_tx_headroom = 0;
1327 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1328 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1329 rt2x00dev->hw->queues = 2;
1330
1331 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1332 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1333 rt2x00_eeprom_addr(rt2x00dev,
1334 EEPROM_MAC_ADDR_0));
1335
1336 /*
1337 * Convert tx_power array in eeprom.
1338 */
1339 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1340 for (i = 0; i < 14; i++)
1341 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1342
1343 /*
1344 * Initialize hw_mode information.
1345 */
31562e80
ID		 1346 spec->supported_bands = SUPPORT_BAND_2GHZ;
1347 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627
ID		 1348 spec->tx_power_a = NULL;
1349 spec->tx_power_bg = txpower;
1350 spec->tx_power_default = DEFAULT_TXPOWER;
1351
1352 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1353 spec->channels = rf_vals_bg;
1354}
1355
1356static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1357{
1358 int retval;
1359
1360 /*
1361 * Allocate eeprom data.
1362 */
1363 retval = rt2400pci_validate_eeprom(rt2x00dev);
1364 if (retval)
1365 return retval;
1366
1367 retval = rt2400pci_init_eeprom(rt2x00dev);
1368 if (retval)
1369 return retval;
1370
1371 /*
1372 * Initialize hw specifications.
1373 */
1374 rt2400pci_probe_hw_mode(rt2x00dev);
1375
1376 /*
181d6902 1377 * This device requires the atim queue
95ea3627 1378 */
181d6902 1379 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1380
1381 /*
1382 * Set the rssi offset.
1383 */
1384 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1385
1386 return 0;
1387}
1388
1389/*
1390 * IEEE80211 stack callback functions.
1391 */
4150c572
JB		 1392static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1393 unsigned int changed_flags,
1394 unsigned int *total_flags,
1395 int mc_count,
1396 struct dev_addr_list *mc_list)
1397{
1398 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1399 u32 reg;
1400
1401 /*
1402 * Mask off any flags we are going to ignore from
1403 * the total_flags field.
1404 */
1405 *total_flags &=
1406 FIF_ALLMULTI |
1407 FIF_FCSFAIL |
1408 FIF_PLCPFAIL |
1409 FIF_CONTROL |
1410 FIF_OTHER_BSS |
1411 FIF_PROMISC_IN_BSS;
1412
1413 /*
1414 * Apply some rules to the filters:
1415 * - Some filters imply different filters to be set.
1416 * - Some things we can't filter out at all.
4150c572
JB		 1417 */
1418 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1419 if (*total_flags & FIF_OTHER_BSS ||
1420 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1421 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1422
1423 /*
1424 * Check if there is any work left for us.
1425 */
3c4f2085 1426 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1427 return;
3c4f2085 1428 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1429
1430 /*
1431 * Start configuration steps.
1432 * Note that the version error will always be dropped
1433 * since there is no filter for it at this time.
1434 */
1435 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1436 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1437 !(*total_flags & FIF_FCSFAIL));
1438 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1439 !(*total_flags & FIF_PLCPFAIL));
1440 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1441 !(*total_flags & FIF_CONTROL));
1442 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1443 !(*total_flags & FIF_PROMISC_IN_BSS));
1444 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1445 !(*total_flags & FIF_PROMISC_IN_BSS));
1446 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1447 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1448}
1449
95ea3627
ID		 1450static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1451 u32 short_retry, u32 long_retry)
1452{
1453 struct rt2x00_dev *rt2x00dev = hw->priv;
1454 u32 reg;
1455
1456 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1457 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1458 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1459 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1460
1461 return 0;
1462}
1463
1464static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1465 int queue,
1466 const struct ieee80211_tx_queue_params *params)
1467{
1468 struct rt2x00_dev *rt2x00dev = hw->priv;
1469
1470 /*
1471 * We don't support variating cw_min and cw_max variables
1472 * per queue. So by default we only configure the TX queue,
1473 * and ignore all other configurations.
1474 */
1475 if (queue != IEEE80211_TX_QUEUE_DATA0)
1476 return -EINVAL;
1477
1478 if (rt2x00mac_conf_tx(hw, queue, params))
1479 return -EINVAL;
1480
1481 /*
1482 * Write configuration to register.
1483 */
181d6902
ID		 1484 rt2400pci_config_cw(rt2x00dev,
1485 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1486
1487 return 0;
1488}
1489
1490static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1491{
1492 struct rt2x00_dev *rt2x00dev = hw->priv;
1493 u64 tsf;
1494 u32 reg;
1495
1496 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1497 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1498 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1499 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1500
1501 return tsf;
1502}
1503
5957da4c
ID		 1504static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1505 struct ieee80211_tx_control *control)
1506{
1507 struct rt2x00_dev *rt2x00dev = hw->priv;
1508 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1509 struct queue_entry_priv_pci_tx *priv_tx;
1510 struct skb_frame_desc *skbdesc;
8af244cc 1511 u32 reg;
5957da4c
ID		 1512
1513 if (unlikely(!intf->beacon))
1514 return -ENOBUFS;
5957da4c
ID		 1515 priv_tx = intf->beacon->priv_data;
1516
1517 /*
1518 * Fill in skb descriptor
1519 */
1520 skbdesc = get_skb_frame_desc(skb);
1521 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1522 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1523 skbdesc->data = skb->data;
1524 skbdesc->data_len = skb->len;
1525 skbdesc->desc = priv_tx->desc;
1526 skbdesc->desc_len = intf->beacon->queue->desc_size;
1527 skbdesc->entry = intf->beacon;
1528
8af244cc
ID		 1529 /*
1530 * Disable beaconing while we are reloading the beacon data,
1531 * otherwise we might be sending out invalid data.
1532 */
1533 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1534 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1535 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1536 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1537 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1538
5957da4c
ID		 1539 /*
1540 * mac80211 doesn't provide the control->queue variable
1541 * for beacons. Set our own queue identification so
1542 * it can be used during descriptor initialization.
1543 */
1544 control->queue = RT2X00_BCN_QUEUE_BEACON;
1545 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1546
1547 /*
1548 * Enable beacon generation.
1549 * Write entire beacon with descriptor to register,
1550 * and kick the beacon generator.
1551 */
1552 memcpy(priv_tx->data, skb->data, skb->len);
1553 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1554
1555 return 0;
1556}
1557
95ea3627
ID		 1558static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1559{
1560 struct rt2x00_dev *rt2x00dev = hw->priv;
1561 u32 reg;
1562
1563 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1564 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1565}
1566
1567static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1568 .tx = rt2x00mac_tx,
4150c572
JB		 1569 .start = rt2x00mac_start,
1570 .stop = rt2x00mac_stop,
95ea3627
ID		 1571 .add_interface = rt2x00mac_add_interface,
1572 .remove_interface = rt2x00mac_remove_interface,
1573 .config = rt2x00mac_config,
1574 .config_interface = rt2x00mac_config_interface,
4150c572 1575 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1576 .get_stats = rt2x00mac_get_stats,
1577 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1578 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1579 .conf_tx = rt2400pci_conf_tx,
1580 .get_tx_stats = rt2x00mac_get_tx_stats,
1581 .get_tsf = rt2400pci_get_tsf,
5957da4c 1582 .beacon_update = rt2400pci_beacon_update,
95ea3627
ID		 1583 .tx_last_beacon = rt2400pci_tx_last_beacon,
1584};
1585
1586static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1587 .irq_handler = rt2400pci_interrupt,
1588 .probe_hw = rt2400pci_probe_hw,
1589 .initialize = rt2x00pci_initialize,
1590 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1591 .init_rxentry = rt2400pci_init_rxentry,
1592 .init_txentry = rt2400pci_init_txentry,
95ea3627 1593 .set_device_state = rt2400pci_set_device_state,
95ea3627 1594 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1595 .link_stats = rt2400pci_link_stats,
1596 .reset_tuner = rt2400pci_reset_tuner,
1597 .link_tuner = rt2400pci_link_tuner,
a9450b70 1598 .led_brightness = rt2400pci_led_brightness,
95ea3627
ID		 1599 .write_tx_desc = rt2400pci_write_tx_desc,
1600 .write_tx_data = rt2x00pci_write_tx_data,
1601 .kick_tx_queue = rt2400pci_kick_tx_queue,
1602 .fill_rxdone = rt2400pci_fill_rxdone,
6bb40dd1 1603 .config_intf = rt2400pci_config_intf,
72810379 1604 .config_erp = rt2400pci_config_erp,
95ea3627
ID		 1605 .config = rt2400pci_config,
1606};
1607
181d6902
ID		 1608static const struct data_queue_desc rt2400pci_queue_rx = {
1609 .entry_num = RX_ENTRIES,
1610 .data_size = DATA_FRAME_SIZE,
1611 .desc_size = RXD_DESC_SIZE,
1612 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1613};
1614
1615static const struct data_queue_desc rt2400pci_queue_tx = {
1616 .entry_num = TX_ENTRIES,
1617 .data_size = DATA_FRAME_SIZE,
1618 .desc_size = TXD_DESC_SIZE,
1619 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1620};
1621
1622static const struct data_queue_desc rt2400pci_queue_bcn = {
1623 .entry_num = BEACON_ENTRIES,
1624 .data_size = MGMT_FRAME_SIZE,
1625 .desc_size = TXD_DESC_SIZE,
1626 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1627};
1628
1629static const struct data_queue_desc rt2400pci_queue_atim = {
1630 .entry_num = ATIM_ENTRIES,
1631 .data_size = DATA_FRAME_SIZE,
1632 .desc_size = TXD_DESC_SIZE,
1633 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1634};
1635
95ea3627 1636static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1637 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1638 .max_sta_intf = 1,
1639 .max_ap_intf = 1,
95ea3627
ID		 1640 .eeprom_size = EEPROM_SIZE,
1641 .rf_size = RF_SIZE,
181d6902
ID		 1642 .rx = &rt2400pci_queue_rx,
1643 .tx = &rt2400pci_queue_tx,
1644 .bcn = &rt2400pci_queue_bcn,
1645 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1646 .lib = &rt2400pci_rt2x00_ops,
1647 .hw = &rt2400pci_mac80211_ops,
1648#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1649 .debugfs = &rt2400pci_rt2x00debug,
1650#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1651};
1652
1653/*
1654 * RT2400pci module information.
1655 */
1656static struct pci_device_id rt2400pci_device_table[] = {
1657 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1658 { 0, }
1659};
1660
1661MODULE_AUTHOR(DRV_PROJECT);
1662MODULE_VERSION(DRV_VERSION);
1663MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1664MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1665MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1666MODULE_LICENSE("GPL");
1667
1668static struct pci_driver rt2400pci_driver = {
2360157c 1669 .name = KBUILD_MODNAME,
95ea3627
ID		 1670 .id_table = rt2400pci_device_table,
1671 .probe = rt2x00pci_probe,
1672 .remove = __devexit_p(rt2x00pci_remove),
1673 .suspend = rt2x00pci_suspend,
1674 .resume = rt2x00pci_resume,
1675};
1676
1677static int __init rt2400pci_init(void)
1678{
1679 return pci_register_driver(&rt2400pci_driver);
1680}
1681
1682static void __exit rt2400pci_exit(void)
1683{
1684 pci_unregister_driver(&rt2400pci_driver);
1685}
1686
1687module_init(rt2400pci_init);
1688module_exit(rt2400pci_exit);
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