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rt2x00: Determine MY_BSS from descriptor
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
246/*
247 * Configuration handlers.
248 */
4abee4bb
ID		 249static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
250 __le32 *mac)
95ea3627 251{
4abee4bb
ID		 252 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
253 (2 * sizeof(__le32)));
95ea3627
ID		 254}
255
4abee4bb
ID		 256static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
257 __le32 *bssid)
95ea3627 258{
4abee4bb
ID		 259 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
260 (2 * sizeof(__le32)));
95ea3627
ID		 261}
262
feb24691
ID		 263static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
264 const int tsf_sync)
95ea3627
ID		 265{
266 u32 reg;
267
268 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
269
95ea3627
ID		 270 /*
271 * Enable beacon config
272 */
273 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
274 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
a137e202 275 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
95ea3627
ID		 276 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
277
278 /*
279 * Enable synchronisation.
280 */
281 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572 282 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
3867705b 283 rt2x00_set_field32(&reg, CSR14_TBCN, (tsf_sync == TSF_SYNC_BEACON));
95ea3627 284 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
feb24691 285 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
95ea3627
ID		 286 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
287}
288
5c58ee51
ID		 289static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
290 const int short_preamble,
291 const int ack_timeout,
292 const int ack_consume_time)
95ea3627 293{
5c58ee51 294 int preamble_mask;
95ea3627 295 u32 reg;
95ea3627 296
5c58ee51
ID		 297 /*
298 * When short preamble is enabled, we should set bit 0x08
299 */
300 preamble_mask = short_preamble << 3;
95ea3627
ID		 301
302 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 303 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
304 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 305 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
306
95ea3627 307 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 308 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 309 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
310 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
311 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
312
313 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 314 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 315 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
316 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
317 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
318
319 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 320 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 321 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
322 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
323 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
324
325 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 326 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 327 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
328 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
329 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
330}
331
332static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 333 const int basic_rate_mask)
95ea3627 334{
5c58ee51 335 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 336}
337
338static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 339 struct rf_channel *rf)
95ea3627 340{
95ea3627
ID		 341 /*
342 * Switch on tuning bits.
343 */
5c58ee51
ID		 344 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
345 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 346
5c58ee51
ID		 347 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
348 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
349 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 350
351 /*
352 * RF2420 chipset don't need any additional actions.
353 */
354 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
355 return;
356
357 /*
358 * For the RT2421 chipsets we need to write an invalid
359 * reference clock rate to activate auto_tune.
360 * After that we set the value back to the correct channel.
361 */
5c58ee51 362 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 363 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 364 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 365
366 msleep(1);
367
5c58ee51
ID		 368 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
369 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
370 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 371
372 msleep(1);
373
374 /*
375 * Switch off tuning bits.
376 */
5c58ee51
ID		 377 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
378 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 379
5c58ee51
ID		 380 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
381 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 382
383 /*
384 * Clear false CRC during channel switch.
385 */
5c58ee51 386 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 387}
388
389static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
390{
391 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
392}
393
394static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 395 struct antenna_setup *ant)
95ea3627
ID		 396{
397 u8 r1;
398 u8 r4;
399
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
402
403 /*
404 * Configure the TX antenna.
405 */
addc81bd 406 switch (ant->tx) {
95ea3627
ID		 407 case ANTENNA_HW_DIVERSITY:
408 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
409 break;
410 case ANTENNA_A:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
412 break;
39e75857
ID		 413 case ANTENNA_SW_DIVERSITY:
414 /*
415 * NOTE: We should never come here because rt2x00lib is
416 * supposed to catch this and send us the correct antenna
417 * explicitely. However we are nog going to bug about this.
418 * Instead, just default to antenna B.
419 */
95ea3627
ID		 420 case ANTENNA_B:
421 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
422 break;
423 }
424
425 /*
426 * Configure the RX antenna.
427 */
addc81bd 428 switch (ant->rx) {
95ea3627
ID		 429 case ANTENNA_HW_DIVERSITY:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
431 break;
432 case ANTENNA_A:
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
434 break;
39e75857
ID		 435 case ANTENNA_SW_DIVERSITY:
436 /*
437 * NOTE: We should never come here because rt2x00lib is
438 * supposed to catch this and send us the correct antenna
439 * explicitely. However we are nog going to bug about this.
440 * Instead, just default to antenna B.
441 */
95ea3627
ID		 442 case ANTENNA_B:
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
444 break;
445 }
446
447 rt2400pci_bbp_write(rt2x00dev, 4, r4);
448 rt2400pci_bbp_write(rt2x00dev, 1, r1);
449}
450
451static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 452 struct rt2x00lib_conf *libconf)
95ea3627
ID		 453{
454 u32 reg;
455
456 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 457 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 458 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
459
460 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 461 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
462 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 463 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
464
465 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 466 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
467 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 468 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
469
470 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
471 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
472 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
473 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
474
475 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 476 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
477 libconf->conf->beacon_int * 16);
478 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
479 libconf->conf->beacon_int * 16);
95ea3627
ID		 480 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
481}
482
483static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
484 const unsigned int flags,
5c58ee51 485 struct rt2x00lib_conf *libconf)
95ea3627 486{
95ea3627 487 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 488 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 489 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 490 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 491 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 492 rt2400pci_config_txpower(rt2x00dev,
493 libconf->conf->power_level);
95ea3627 494 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 495 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 496 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 497 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 498}
499
500static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
501 struct ieee80211_tx_queue_params *params)
502{
503 u32 reg;
504
505 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
506 rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
507 rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
508 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
509}
510
511/*
512 * LED functions.
513 */
514static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
515{
516 u32 reg;
517
518 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
519
520 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
521 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
ddc827f9
ID		 522 rt2x00_set_field32(&reg, LEDCSR_LINK,
523 (rt2x00dev->led_mode != LED_MODE_ASUS));
524 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
525 (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
95ea3627
ID		 526 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
527}
528
529static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
530{
531 u32 reg;
532
533 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
534 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
535 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
536 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
537}
538
539/*
540 * Link tuning
541 */
ebcf26da
ID		 542static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
543 struct link_qual *qual)
95ea3627
ID		 544{
545 u32 reg;
546 u8 bbp;
547
548 /*
549 * Update FCS error count from register.
550 */
551 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 552 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 553
554 /*
555 * Update False CCA count from register.
556 */
557 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 558 qual->false_cca = bbp;
95ea3627
ID		 559}
560
561static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
562{
563 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
564 rt2x00dev->link.vgc_level = 0x08;
565}
566
567static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
568{
569 u8 reg;
570
571 /*
572 * The link tuner should not run longer then 60 seconds,
573 * and should run once every 2 seconds.
574 */
575 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
576 return;
577
578 /*
579 * Base r13 link tuning on the false cca count.
580 */
581 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
582
ebcf26da 583 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 584 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
585 rt2x00dev->link.vgc_level = reg;
ebcf26da 586 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 587 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
588 rt2x00dev->link.vgc_level = reg;
589 }
590}
591
592/*
593 * Initialization functions.
594 */
595static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
596{
597 struct data_ring *ring = rt2x00dev->rx;
4bd7c452 598 __le32 *rxd;
95ea3627
ID		 599 unsigned int i;
600 u32 word;
601
602 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
603
604 for (i = 0; i < ring->stats.limit; i++) {
605 rxd = ring->entry[i].priv;
606
607 rt2x00_desc_read(rxd, 2, &word);
608 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
609 ring->data_size);
610 rt2x00_desc_write(rxd, 2, word);
611
612 rt2x00_desc_read(rxd, 1, &word);
613 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
614 ring->entry[i].data_dma);
615 rt2x00_desc_write(rxd, 1, word);
616
617 rt2x00_desc_read(rxd, 0, &word);
618 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
619 rt2x00_desc_write(rxd, 0, word);
620 }
621
622 rt2x00_ring_index_clear(rt2x00dev->rx);
623}
624
625static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
626{
627 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
4bd7c452 628 __le32 *txd;
95ea3627
ID		 629 unsigned int i;
630 u32 word;
631
632 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
633
634 for (i = 0; i < ring->stats.limit; i++) {
635 txd = ring->entry[i].priv;
636
637 rt2x00_desc_read(txd, 1, &word);
638 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
639 ring->entry[i].data_dma);
640 rt2x00_desc_write(txd, 1, word);
641
642 rt2x00_desc_read(txd, 2, &word);
643 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
644 ring->data_size);
645 rt2x00_desc_write(txd, 2, word);
646
647 rt2x00_desc_read(txd, 0, &word);
648 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
649 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
650 rt2x00_desc_write(txd, 0, word);
651 }
652
653 rt2x00_ring_index_clear(ring);
654}
655
656static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
657{
658 u32 reg;
659
660 /*
661 * Initialize rings.
662 */
663 rt2400pci_init_rxring(rt2x00dev);
664 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
665 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
666 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
667 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
668
669 /*
670 * Initialize registers.
671 */
672 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
673 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
674 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
675 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
676 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
677 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
678 rt2x00dev->bcn[1].stats.limit);
679 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
680 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
681 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
682
683 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
684 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
685 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
686 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
687
688 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
689 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
690 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
691 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
692
693 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
694 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
695 rt2x00dev->bcn[1].data_dma);
696 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
697
698 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
699 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
700 rt2x00dev->bcn[0].data_dma);
701 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
702
703 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
704 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
705 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
706 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
707
708 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
709 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
710 rt2x00dev->rx->data_dma);
711 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
712
713 return 0;
714}
715
716static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
717{
718 u32 reg;
719
720 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
721 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
722 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
723 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
724
725 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
726 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
727 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
728 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
729 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
730
731 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
732 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
733 (rt2x00dev->rx->data_size / 128));
734 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
735
736 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
737
738 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
739 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
740 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
741 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
742 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
743 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
744
745 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
746 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
747 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
748 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
749 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
750 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
751 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
752 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
753
754 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
755
756 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
757 return -EBUSY;
758
759 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
760 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
761
762 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
763 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
764 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
765
766 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
767 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
768 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
769 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
770 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
771 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
772
773 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
774 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
775 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
776 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
777 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
778
779 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
780 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
781 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
782 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
783
784 /*
785 * We must clear the FCS and FIFO error count.
786 * These registers are cleared on read,
787 * so we may pass a useless variable to store the value.
788 */
789 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
790 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
791
792 return 0;
793}
794
795static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
796{
797 unsigned int i;
798 u16 eeprom;
799 u8 reg_id;
800 u8 value;
801
802 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
803 rt2400pci_bbp_read(rt2x00dev, 0, &value);
804 if ((value != 0xff) && (value != 0x00))
805 goto continue_csr_init;
806 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
807 udelay(REGISTER_BUSY_DELAY);
808 }
809
810 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
811 return -EACCES;
812
813continue_csr_init:
814 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
815 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
816 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
817 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
818 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
819 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
820 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
821 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
822 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
823 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
824 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
825 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
826 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
827 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
828
829 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
830 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
831 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
832
833 if (eeprom != 0xffff && eeprom != 0x0000) {
834 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
835 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
836 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
837 reg_id, value);
838 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
839 }
840 }
841 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
842
843 return 0;
844}
845
846/*
847 * Device state switch handlers.
848 */
849static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
850 enum dev_state state)
851{
852 u32 reg;
853
854 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
855 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
856 state == STATE_RADIO_RX_OFF);
857 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
858}
859
860static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
861 enum dev_state state)
862{
863 int mask = (state == STATE_RADIO_IRQ_OFF);
864 u32 reg;
865
866 /*
867 * When interrupts are being enabled, the interrupt registers
868 * should clear the register to assure a clean state.
869 */
870 if (state == STATE_RADIO_IRQ_ON) {
871 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
872 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
873 }
874
875 /*
876 * Only toggle the interrupts bits we are going to use.
877 * Non-checked interrupt bits are disabled by default.
878 */
879 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
880 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
881 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
882 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
883 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
884 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
885 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
886}
887
888static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
889{
890 /*
891 * Initialize all registers.
892 */
893 if (rt2400pci_init_rings(rt2x00dev) ||
894 rt2400pci_init_registers(rt2x00dev) ||
895 rt2400pci_init_bbp(rt2x00dev)) {
896 ERROR(rt2x00dev, "Register initialization failed.\n");
897 return -EIO;
898 }
899
900 /*
901 * Enable interrupts.
902 */
903 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
904
905 /*
906 * Enable LED
907 */
908 rt2400pci_enable_led(rt2x00dev);
909
910 return 0;
911}
912
913static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
914{
915 u32 reg;
916
917 /*
918 * Disable LED
919 */
920 rt2400pci_disable_led(rt2x00dev);
921
922 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
923
924 /*
925 * Disable synchronisation.
926 */
927 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
928
929 /*
930 * Cancel RX and TX.
931 */
932 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
933 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
934 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
935
936 /*
937 * Disable interrupts.
938 */
939 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
940}
941
942static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
943 enum dev_state state)
944{
945 u32 reg;
946 unsigned int i;
947 char put_to_sleep;
948 char bbp_state;
949 char rf_state;
950
951 put_to_sleep = (state != STATE_AWAKE);
952
953 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
954 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
955 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
956 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
957 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
958 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
959
960 /*
961 * Device is not guaranteed to be in the requested state yet.
962 * We must wait until the register indicates that the
963 * device has entered the correct state.
964 */
965 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
966 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
967 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
968 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
969 if (bbp_state == state && rf_state == state)
970 return 0;
971 msleep(10);
972 }
973
974 NOTICE(rt2x00dev, "Device failed to enter state %d, "
975 "current device state: bbp %d and rf %d.\n",
976 state, bbp_state, rf_state);
977
978 return -EBUSY;
979}
980
981static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
982 enum dev_state state)
983{
984 int retval = 0;
985
986 switch (state) {
987 case STATE_RADIO_ON:
988 retval = rt2400pci_enable_radio(rt2x00dev);
989 break;
990 case STATE_RADIO_OFF:
991 rt2400pci_disable_radio(rt2x00dev);
992 break;
993 case STATE_RADIO_RX_ON:
994 case STATE_RADIO_RX_OFF:
995 rt2400pci_toggle_rx(rt2x00dev, state);
996 break;
997 case STATE_DEEP_SLEEP:
998 case STATE_SLEEP:
999 case STATE_STANDBY:
1000 case STATE_AWAKE:
1001 retval = rt2400pci_set_state(rt2x00dev, state);
1002 break;
1003 default:
1004 retval = -ENOTSUPP;
1005 break;
1006 }
1007
1008 return retval;
1009}
1010
1011/*
1012 * TX descriptor initialization
1013 */
1014static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1015 struct sk_buff *skb,
4150c572 1016 struct txdata_entry_desc *desc,
95ea3627
ID		 1017 struct ieee80211_tx_control *control)
1018{
dd3193e1
ID		 1019 struct skb_desc *skbdesc = get_skb_desc(skb);
1020 __le32 *txd = skbdesc->desc;
95ea3627 1021 u32 word;
95ea3627
ID		 1022
1023 /*
1024 * Start writing the descriptor words.
1025 */
1026 rt2x00_desc_read(txd, 2, &word);
dd3193e1 1027 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1028 rt2x00_desc_write(txd, 2, word);
1029
1030 rt2x00_desc_read(txd, 3, &word);
49da2605
ID		 1031 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1032 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1033 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1034 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1035 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1037 rt2x00_desc_write(txd, 3, word);
1038
1039 rt2x00_desc_read(txd, 4, &word);
49da2605
ID		 1040 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, desc->length_low);
1041 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1042 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1043 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, desc->length_high);
1044 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1045 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1046 rt2x00_desc_write(txd, 4, word);
1047
1048 rt2x00_desc_read(txd, 0, &word);
1049 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1050 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1051 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1052 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1053 rt2x00_set_field32(&word, TXD_W0_ACK,
2700f8b0 1054 test_bit(ENTRY_TXD_ACK, &desc->flags));
95ea3627
ID		 1055 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1056 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1057 rt2x00_set_field32(&word, TXD_W0_RTS,
1058 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1059 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1060 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1061 !!(control->flags &
1062 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1063 rt2x00_desc_write(txd, 0, word);
1064}
1065
1066/*
1067 * TX data initialization
1068 */
1069static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1070 unsigned int queue)
1071{
1072 u32 reg;
1073
1074 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1075 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1076 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1077 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1078 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1079 }
1080 return;
1081 }
1082
1083 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1084 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1085 (queue == IEEE80211_TX_QUEUE_DATA0));
1086 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1087 (queue == IEEE80211_TX_QUEUE_DATA1));
1088 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1089 (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
95ea3627
ID		 1090 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1091}
1092
1093/*
1094 * RX control handlers
1095 */
4150c572
JB		 1096static void rt2400pci_fill_rxdone(struct data_entry *entry,
1097 struct rxdata_entry_desc *desc)
95ea3627 1098{
4bd7c452 1099 __le32 *rxd = entry->priv;
95ea3627
ID		 1100 u32 word0;
1101 u32 word2;
1102
1103 rt2x00_desc_read(rxd, 0, &word0);
1104 rt2x00_desc_read(rxd, 2, &word2);
1105
4150c572
JB		 1106 desc->flags = 0;
1107 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1108 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1109 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1110 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1111
1112 /*
1113 * Obtain the status about this packet.
1114 */
4150c572
JB		 1115 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1116 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
95ea3627 1117 entry->ring->rt2x00dev->rssi_offset;
4150c572
JB		 1118 desc->ofdm = 0;
1119 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
7e56d38d 1120 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1121}
1122
1123/*
1124 * Interrupt functions.
1125 */
1126static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1127{
1128 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1129 struct data_entry *entry;
4bd7c452 1130 __le32 *txd;
95ea3627
ID		 1131 u32 word;
1132 int tx_status;
1133 int retry;
1134
1135 while (!rt2x00_ring_empty(ring)) {
1136 entry = rt2x00_get_data_entry_done(ring);
1137 txd = entry->priv;
1138 rt2x00_desc_read(txd, 0, &word);
1139
1140 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1141 !rt2x00_get_field32(word, TXD_W0_VALID))
1142 break;
1143
1144 /*
1145 * Obtain the status about this packet.
1146 */
1147 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1148 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1149
3957ccb5 1150 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
95ea3627 1151 }
95ea3627
ID		 1152}
1153
1154static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1155{
1156 struct rt2x00_dev *rt2x00dev = dev_instance;
1157 u32 reg;
1158
1159 /*
1160 * Get the interrupt sources & saved to local variable.
1161 * Write register value back to clear pending interrupts.
1162 */
1163 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1164 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1165
1166 if (!reg)
1167 return IRQ_NONE;
1168
1169 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1170 return IRQ_HANDLED;
1171
1172 /*
1173 * Handle interrupts, walk through all bits
1174 * and run the tasks, the bits are checked in order of
1175 * priority.
1176 */
1177
1178 /*
1179 * 1 - Beacon timer expired interrupt.
1180 */
1181 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1182 rt2x00lib_beacondone(rt2x00dev);
1183
1184 /*
1185 * 2 - Rx ring done interrupt.
1186 */
1187 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1188 rt2x00pci_rxdone(rt2x00dev);
1189
1190 /*
1191 * 3 - Atim ring transmit done interrupt.
1192 */
1193 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1194 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1195
1196 /*
1197 * 4 - Priority ring transmit done interrupt.
1198 */
1199 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1200 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1201
1202 /*
1203 * 5 - Tx ring transmit done interrupt.
1204 */
1205 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1206 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1207
1208 return IRQ_HANDLED;
1209}
1210
1211/*
1212 * Device probe functions.
1213 */
1214static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1215{
1216 struct eeprom_93cx6 eeprom;
1217 u32 reg;
1218 u16 word;
1219 u8 *mac;
1220
1221 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1222
1223 eeprom.data = rt2x00dev;
1224 eeprom.register_read = rt2400pci_eepromregister_read;
1225 eeprom.register_write = rt2400pci_eepromregister_write;
1226 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1227 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1228 eeprom.reg_data_in = 0;
1229 eeprom.reg_data_out = 0;
1230 eeprom.reg_data_clock = 0;
1231 eeprom.reg_chip_select = 0;
1232
1233 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1234 EEPROM_SIZE / sizeof(u16));
1235
1236 /*
1237 * Start validation of the data that has been read.
1238 */
1239 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1240 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1241 DECLARE_MAC_BUF(macbuf);
1242
95ea3627 1243 random_ether_addr(mac);
0795af57 1244 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1245 }
1246
1247 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1248 if (word == 0xffff) {
1249 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1250 return -EINVAL;
1251 }
1252
1253 return 0;
1254}
1255
1256static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1257{
1258 u32 reg;
1259 u16 value;
1260 u16 eeprom;
1261
1262 /*
1263 * Read EEPROM word for configuration.
1264 */
1265 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1266
1267 /*
1268 * Identify RF chipset.
1269 */
1270 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1271 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1272 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1273
1274 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1275 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1276 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1277 return -ENODEV;
1278 }
1279
1280 /*
1281 * Identify default antenna configuration.
1282 */
addc81bd 1283 rt2x00dev->default_ant.tx =
95ea3627 1284 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1285 rt2x00dev->default_ant.rx =
95ea3627
ID		 1286 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1287
addc81bd
ID		 1288 /*
1289 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1290 * I am not 100% sure about this, but the legacy drivers do not
1291 * indicate antenna swapping in software is required when
1292 * diversity is enabled.
1293 */
1294 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1295 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1296 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1297 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1298
95ea3627
ID		 1299 /*
1300 * Store led mode, for correct led behaviour.
1301 */
1302 rt2x00dev->led_mode =
1303 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1304
1305 /*
1306 * Detect if this device has an hardware controlled radio.
1307 */
81873e9c 1308#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1309 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1310 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1311#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1312
1313 /*
1314 * Check if the BBP tuning should be enabled.
1315 */
1316 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1317 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1318
1319 return 0;
1320}
1321
1322/*
1323 * RF value list for RF2420 & RF2421
1324 * Supports: 2.4 GHz
1325 */
1326static const struct rf_channel rf_vals_bg[] = {
1327 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1328 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1329 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1330 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1331 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1332 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1333 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1334 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1335 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1336 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1337 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1338 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1339 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1340 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1341};
1342
1343static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1344{
1345 struct hw_mode_spec *spec = &rt2x00dev->spec;
1346 u8 *txpower;
1347 unsigned int i;
1348
1349 /*
1350 * Initialize all hw fields.
1351 */
4150c572 1352 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1353 rt2x00dev->hw->extra_tx_headroom = 0;
1354 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1355 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1356 rt2x00dev->hw->queues = 2;
1357
1358 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1359 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1360 rt2x00_eeprom_addr(rt2x00dev,
1361 EEPROM_MAC_ADDR_0));
1362
1363 /*
1364 * Convert tx_power array in eeprom.
1365 */
1366 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1367 for (i = 0; i < 14; i++)
1368 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1369
1370 /*
1371 * Initialize hw_mode information.
1372 */
1373 spec->num_modes = 1;
1374 spec->num_rates = 4;
1375 spec->tx_power_a = NULL;
1376 spec->tx_power_bg = txpower;
1377 spec->tx_power_default = DEFAULT_TXPOWER;
1378
1379 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1380 spec->channels = rf_vals_bg;
1381}
1382
1383static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1384{
1385 int retval;
1386
1387 /*
1388 * Allocate eeprom data.
1389 */
1390 retval = rt2400pci_validate_eeprom(rt2x00dev);
1391 if (retval)
1392 return retval;
1393
1394 retval = rt2400pci_init_eeprom(rt2x00dev);
1395 if (retval)
1396 return retval;
1397
1398 /*
1399 * Initialize hw specifications.
1400 */
1401 rt2400pci_probe_hw_mode(rt2x00dev);
1402
1403 /*
1404 * This device requires the beacon ring
1405 */
066cb637 1406 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
95ea3627
ID		 1407
1408 /*
1409 * Set the rssi offset.
1410 */
1411 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1412
1413 return 0;
1414}
1415
1416/*
1417 * IEEE80211 stack callback functions.
1418 */
4150c572
JB		 1419static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1420 unsigned int changed_flags,
1421 unsigned int *total_flags,
1422 int mc_count,
1423 struct dev_addr_list *mc_list)
1424{
1425 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1426 u32 reg;
1427
1428 /*
1429 * Mask off any flags we are going to ignore from
1430 * the total_flags field.
1431 */
1432 *total_flags &=
1433 FIF_ALLMULTI |
1434 FIF_FCSFAIL |
1435 FIF_PLCPFAIL |
1436 FIF_CONTROL |
1437 FIF_OTHER_BSS |
1438 FIF_PROMISC_IN_BSS;
1439
1440 /*
1441 * Apply some rules to the filters:
1442 * - Some filters imply different filters to be set.
1443 * - Some things we can't filter out at all.
4150c572
JB		 1444 */
1445 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1446 if (*total_flags & FIF_OTHER_BSS ||
1447 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1448 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1449
1450 /*
1451 * Check if there is any work left for us.
1452 */
3c4f2085 1453 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1454 return;
3c4f2085 1455 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1456
1457 /*
1458 * Start configuration steps.
1459 * Note that the version error will always be dropped
1460 * since there is no filter for it at this time.
1461 */
1462 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1463 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1464 !(*total_flags & FIF_FCSFAIL));
1465 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1466 !(*total_flags & FIF_PLCPFAIL));
1467 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1468 !(*total_flags & FIF_CONTROL));
1469 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1470 !(*total_flags & FIF_PROMISC_IN_BSS));
1471 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1472 !(*total_flags & FIF_PROMISC_IN_BSS));
1473 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1474 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1475}
1476
95ea3627
ID		 1477static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1478 u32 short_retry, u32 long_retry)
1479{
1480 struct rt2x00_dev *rt2x00dev = hw->priv;
1481 u32 reg;
1482
1483 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1484 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1485 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1486 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1487
1488 return 0;
1489}
1490
1491static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1492 int queue,
1493 const struct ieee80211_tx_queue_params *params)
1494{
1495 struct rt2x00_dev *rt2x00dev = hw->priv;
1496
1497 /*
1498 * We don't support variating cw_min and cw_max variables
1499 * per queue. So by default we only configure the TX queue,
1500 * and ignore all other configurations.
1501 */
1502 if (queue != IEEE80211_TX_QUEUE_DATA0)
1503 return -EINVAL;
1504
1505 if (rt2x00mac_conf_tx(hw, queue, params))
1506 return -EINVAL;
1507
1508 /*
1509 * Write configuration to register.
1510 */
1511 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1512
1513 return 0;
1514}
1515
1516static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1517{
1518 struct rt2x00_dev *rt2x00dev = hw->priv;
1519 u64 tsf;
1520 u32 reg;
1521
1522 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1523 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1524 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1525 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1526
1527 return tsf;
1528}
1529
1530static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1531{
1532 struct rt2x00_dev *rt2x00dev = hw->priv;
1533
1534 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1535 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1536}
1537
1538static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1539{
1540 struct rt2x00_dev *rt2x00dev = hw->priv;
1541 u32 reg;
1542
1543 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1544 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1545}
1546
1547static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1548 .tx = rt2x00mac_tx,
4150c572
JB		 1549 .start = rt2x00mac_start,
1550 .stop = rt2x00mac_stop,
95ea3627
ID		 1551 .add_interface = rt2x00mac_add_interface,
1552 .remove_interface = rt2x00mac_remove_interface,
1553 .config = rt2x00mac_config,
1554 .config_interface = rt2x00mac_config_interface,
4150c572 1555 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1556 .get_stats = rt2x00mac_get_stats,
1557 .set_retry_limit = rt2400pci_set_retry_limit,
5c58ee51 1558 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 1559 .conf_tx = rt2400pci_conf_tx,
1560 .get_tx_stats = rt2x00mac_get_tx_stats,
1561 .get_tsf = rt2400pci_get_tsf,
1562 .reset_tsf = rt2400pci_reset_tsf,
1563 .beacon_update = rt2x00pci_beacon_update,
1564 .tx_last_beacon = rt2400pci_tx_last_beacon,
1565};
1566
1567static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1568 .irq_handler = rt2400pci_interrupt,
1569 .probe_hw = rt2400pci_probe_hw,
1570 .initialize = rt2x00pci_initialize,
1571 .uninitialize = rt2x00pci_uninitialize,
1572 .set_device_state = rt2400pci_set_device_state,
95ea3627 1573 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1574 .link_stats = rt2400pci_link_stats,
1575 .reset_tuner = rt2400pci_reset_tuner,
1576 .link_tuner = rt2400pci_link_tuner,
1577 .write_tx_desc = rt2400pci_write_tx_desc,
1578 .write_tx_data = rt2x00pci_write_tx_data,
1579 .kick_tx_queue = rt2400pci_kick_tx_queue,
1580 .fill_rxdone = rt2400pci_fill_rxdone,
1581 .config_mac_addr = rt2400pci_config_mac_addr,
1582 .config_bssid = rt2400pci_config_bssid,
95ea3627 1583 .config_type = rt2400pci_config_type,
5c58ee51 1584 .config_preamble = rt2400pci_config_preamble,
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ID		 1585 .config = rt2400pci_config,
1586};
1587
1588static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1589 .name = KBUILD_MODNAME,
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ID		 1590 .rxd_size = RXD_DESC_SIZE,
1591 .txd_size = TXD_DESC_SIZE,
1592 .eeprom_size = EEPROM_SIZE,
1593 .rf_size = RF_SIZE,
1594 .lib = &rt2400pci_rt2x00_ops,
1595 .hw = &rt2400pci_mac80211_ops,
1596#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1597 .debugfs = &rt2400pci_rt2x00debug,
1598#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1599};
1600
1601/*
1602 * RT2400pci module information.
1603 */
1604static struct pci_device_id rt2400pci_device_table[] = {
1605 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1606 { 0, }
1607};
1608
1609MODULE_AUTHOR(DRV_PROJECT);
1610MODULE_VERSION(DRV_VERSION);
1611MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1612MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1613MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1614MODULE_LICENSE("GPL");
1615
1616static struct pci_driver rt2400pci_driver = {
2360157c 1617 .name = KBUILD_MODNAME,
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ID		 1618 .id_table = rt2400pci_device_table,
1619 .probe = rt2x00pci_probe,
1620 .remove = __devexit_p(rt2x00pci_remove),
1621 .suspend = rt2x00pci_suspend,
1622 .resume = rt2x00pci_resume,
1623};
1624
1625static int __init rt2400pci_init(void)
1626{
1627 return pci_register_driver(&rt2400pci_driver);
1628}
1629
1630static void __exit rt2400pci_exit(void)
1631{
1632 pci_unregister_driver(&rt2400pci_driver);
1633}
1634
1635module_init(rt2400pci_init);
1636module_exit(rt2400pci_exit);
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